]> git.proxmox.com Git - mirror_qemu.git/blame - softmmu_template.h
usb: Call wakeup when data becomes available for all devices with int eps
[mirror_qemu.git] / softmmu_template.h
CommitLineData
b92e5a22
FB
1/*
2 * Software MMU support
5fafdf24 3 *
efbf29b6
BS
4 * Generate helpers used by TCG for qemu_ld/st ops and code load
5 * functions.
6 *
7 * Included from target op helpers and exec.c.
8 *
b92e5a22
FB
9 * Copyright (c) 2003 Fabrice Bellard
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
8167ee88 22 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
b92e5a22 23 */
29e922b6 24#include "qemu-timer.h"
0e0df1e2 25#include "memory.h"
29e922b6 26
b92e5a22
FB
27#define DATA_SIZE (1 << SHIFT)
28
29#if DATA_SIZE == 8
30#define SUFFIX q
61382a50 31#define USUFFIX q
b92e5a22
FB
32#define DATA_TYPE uint64_t
33#elif DATA_SIZE == 4
34#define SUFFIX l
61382a50 35#define USUFFIX l
b92e5a22
FB
36#define DATA_TYPE uint32_t
37#elif DATA_SIZE == 2
38#define SUFFIX w
61382a50 39#define USUFFIX uw
b92e5a22
FB
40#define DATA_TYPE uint16_t
41#elif DATA_SIZE == 1
42#define SUFFIX b
61382a50 43#define USUFFIX ub
b92e5a22
FB
44#define DATA_TYPE uint8_t
45#else
46#error unsupported data size
47#endif
48
b769d8fe
FB
49#ifdef SOFTMMU_CODE_ACCESS
50#define READ_ACCESS_TYPE 2
84b7b8e7 51#define ADDR_READ addr_code
b769d8fe
FB
52#else
53#define READ_ACCESS_TYPE 0
84b7b8e7 54#define ADDR_READ addr_read
b769d8fe
FB
55#endif
56
89c33337 57static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
e141ab52 58 target_ulong addr,
6ebbf390 59 int mmu_idx,
20503968 60 uintptr_t retaddr);
89c33337 61static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
a8170e5e 62 hwaddr physaddr,
2e70f6ef 63 target_ulong addr,
20503968 64 uintptr_t retaddr)
b92e5a22
FB
65{
66 DATA_TYPE res;
37ec01d4
AK
67 MemoryRegion *mr = iotlb_to_region(physaddr);
68
0f459d16 69 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
20503968 70 env->mem_io_pc = retaddr;
37ec01d4
AK
71 if (mr != &io_mem_ram && mr != &io_mem_rom
72 && mr != &io_mem_unassigned
73 && mr != &io_mem_notdirty
2e70f6ef
PB
74 && !can_do_io(env)) {
75 cpu_io_recompile(env, retaddr);
76 }
b92e5a22 77
db8886d3 78 env->mem_io_vaddr = addr;
b92e5a22 79#if SHIFT <= 2
37ec01d4 80 res = io_mem_read(mr, physaddr, 1 << SHIFT);
b92e5a22
FB
81#else
82#ifdef TARGET_WORDS_BIGENDIAN
37ec01d4
AK
83 res = io_mem_read(mr, physaddr, 4) << 32;
84 res |= io_mem_read(mr, physaddr + 4, 4);
b92e5a22 85#else
37ec01d4
AK
86 res = io_mem_read(mr, physaddr, 4);
87 res |= io_mem_read(mr, physaddr + 4, 4) << 32;
b92e5a22
FB
88#endif
89#endif /* SHIFT > 2 */
90 return res;
91}
92
b92e5a22 93/* handle all cases except unaligned access which span two pages */
e141ab52 94DATA_TYPE
89c33337
BS
95glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
96 int mmu_idx)
b92e5a22
FB
97{
98 DATA_TYPE res;
61382a50 99 int index;
c27004ec 100 target_ulong tlb_addr;
a8170e5e 101 hwaddr ioaddr;
20503968 102 uintptr_t retaddr;
3b46e624 103
b92e5a22
FB
104 /* test if there is match for unaligned or IO access */
105 /* XXX: could done more in memory macro in a non portable way */
b92e5a22
FB
106 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
107 redo:
6ebbf390 108 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22 109 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
b92e5a22
FB
110 if (tlb_addr & ~TARGET_PAGE_MASK) {
111 /* IO access */
112 if ((addr & (DATA_SIZE - 1)) != 0)
113 goto do_unaligned_access;
fdbb84d1 114 retaddr = GETPC_EXT();
37ec01d4 115 ioaddr = env->iotlb[mmu_idx][index];
89c33337 116 res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
98699967 117 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22
FB
118 /* slow unaligned access (it spans two pages or IO) */
119 do_unaligned_access:
fdbb84d1 120 retaddr = GETPC_EXT();
a64d4718 121#ifdef ALIGNED_ONLY
89c33337 122 do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718 123#endif
89c33337 124 res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr,
6ebbf390 125 mmu_idx, retaddr);
b92e5a22 126 } else {
a64d4718 127 /* unaligned/aligned access in the same page */
b065927a 128 uintptr_t addend;
a64d4718
FB
129#ifdef ALIGNED_ONLY
130 if ((addr & (DATA_SIZE - 1)) != 0) {
fdbb84d1 131 retaddr = GETPC_EXT();
89c33337 132 do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718
FB
133 }
134#endif
0f459d16 135 addend = env->tlb_table[mmu_idx][index].addend;
b065927a
SW
136 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(intptr_t)
137 (addr + addend));
b92e5a22
FB
138 }
139 } else {
140 /* the page is not in the TLB : fill it */
fdbb84d1 141 retaddr = GETPC_EXT();
a64d4718
FB
142#ifdef ALIGNED_ONLY
143 if ((addr & (DATA_SIZE - 1)) != 0)
89c33337 144 do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718 145#endif
bccd9ec5 146 tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22
FB
147 goto redo;
148 }
149 return res;
150}
151
152/* handle all unaligned cases */
e141ab52 153static DATA_TYPE
89c33337 154glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
e141ab52
BS
155 target_ulong addr,
156 int mmu_idx,
20503968 157 uintptr_t retaddr)
b92e5a22
FB
158{
159 DATA_TYPE res, res1, res2;
61382a50 160 int index, shift;
a8170e5e 161 hwaddr ioaddr;
c27004ec 162 target_ulong tlb_addr, addr1, addr2;
b92e5a22 163
b92e5a22
FB
164 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
165 redo:
6ebbf390 166 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22 167 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
b92e5a22
FB
168 if (tlb_addr & ~TARGET_PAGE_MASK) {
169 /* IO access */
170 if ((addr & (DATA_SIZE - 1)) != 0)
171 goto do_unaligned_access;
37ec01d4 172 ioaddr = env->iotlb[mmu_idx][index];
89c33337 173 res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
98699967 174 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22
FB
175 do_unaligned_access:
176 /* slow unaligned access (it spans two pages) */
177 addr1 = addr & ~(DATA_SIZE - 1);
178 addr2 = addr1 + DATA_SIZE;
89c33337 179 res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr1,
6ebbf390 180 mmu_idx, retaddr);
89c33337 181 res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr2,
6ebbf390 182 mmu_idx, retaddr);
b92e5a22
FB
183 shift = (addr & (DATA_SIZE - 1)) * 8;
184#ifdef TARGET_WORDS_BIGENDIAN
185 res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
186#else
187 res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
188#endif
6986f88c 189 res = (DATA_TYPE)res;
b92e5a22
FB
190 } else {
191 /* unaligned/aligned access in the same page */
b065927a
SW
192 uintptr_t addend = env->tlb_table[mmu_idx][index].addend;
193 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(intptr_t)
194 (addr + addend));
b92e5a22
FB
195 }
196 } else {
197 /* the page is not in the TLB : fill it */
bccd9ec5 198 tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22
FB
199 goto redo;
200 }
201 return res;
202}
203
b769d8fe
FB
204#ifndef SOFTMMU_CODE_ACCESS
205
89c33337 206static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
e141ab52 207 target_ulong addr,
5fafdf24 208 DATA_TYPE val,
6ebbf390 209 int mmu_idx,
20503968 210 uintptr_t retaddr);
b769d8fe 211
89c33337 212static inline void glue(io_write, SUFFIX)(CPUArchState *env,
a8170e5e 213 hwaddr physaddr,
b769d8fe 214 DATA_TYPE val,
0f459d16 215 target_ulong addr,
20503968 216 uintptr_t retaddr)
b769d8fe 217{
37ec01d4
AK
218 MemoryRegion *mr = iotlb_to_region(physaddr);
219
0f459d16 220 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
37ec01d4
AK
221 if (mr != &io_mem_ram && mr != &io_mem_rom
222 && mr != &io_mem_unassigned
223 && mr != &io_mem_notdirty
2e70f6ef
PB
224 && !can_do_io(env)) {
225 cpu_io_recompile(env, retaddr);
226 }
b769d8fe 227
2e70f6ef 228 env->mem_io_vaddr = addr;
20503968 229 env->mem_io_pc = retaddr;
b769d8fe 230#if SHIFT <= 2
37ec01d4 231 io_mem_write(mr, physaddr, val, 1 << SHIFT);
b769d8fe
FB
232#else
233#ifdef TARGET_WORDS_BIGENDIAN
37ec01d4
AK
234 io_mem_write(mr, physaddr, (val >> 32), 4);
235 io_mem_write(mr, physaddr + 4, (uint32_t)val, 4);
b769d8fe 236#else
37ec01d4
AK
237 io_mem_write(mr, physaddr, (uint32_t)val, 4);
238 io_mem_write(mr, physaddr + 4, val >> 32, 4);
b769d8fe
FB
239#endif
240#endif /* SHIFT > 2 */
241}
b92e5a22 242
89c33337
BS
243void glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
244 target_ulong addr, DATA_TYPE val,
245 int mmu_idx)
b92e5a22 246{
a8170e5e 247 hwaddr ioaddr;
c27004ec 248 target_ulong tlb_addr;
20503968 249 uintptr_t retaddr;
61382a50 250 int index;
3b46e624 251
b92e5a22
FB
252 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
253 redo:
6ebbf390 254 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22 255 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
b92e5a22
FB
256 if (tlb_addr & ~TARGET_PAGE_MASK) {
257 /* IO access */
258 if ((addr & (DATA_SIZE - 1)) != 0)
259 goto do_unaligned_access;
fdbb84d1 260 retaddr = GETPC_EXT();
37ec01d4 261 ioaddr = env->iotlb[mmu_idx][index];
89c33337 262 glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
98699967 263 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 264 do_unaligned_access:
fdbb84d1 265 retaddr = GETPC_EXT();
a64d4718 266#ifdef ALIGNED_ONLY
89c33337 267 do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
a64d4718 268#endif
89c33337 269 glue(glue(slow_st, SUFFIX), MMUSUFFIX)(env, addr, val,
6ebbf390 270 mmu_idx, retaddr);
b92e5a22
FB
271 } else {
272 /* aligned/unaligned access in the same page */
b065927a 273 uintptr_t addend;
a64d4718
FB
274#ifdef ALIGNED_ONLY
275 if ((addr & (DATA_SIZE - 1)) != 0) {
fdbb84d1 276 retaddr = GETPC_EXT();
89c33337 277 do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
a64d4718
FB
278 }
279#endif
0f459d16 280 addend = env->tlb_table[mmu_idx][index].addend;
b065927a
SW
281 glue(glue(st, SUFFIX), _raw)((uint8_t *)(intptr_t)
282 (addr + addend), val);
b92e5a22
FB
283 }
284 } else {
285 /* the page is not in the TLB : fill it */
fdbb84d1 286 retaddr = GETPC_EXT();
a64d4718
FB
287#ifdef ALIGNED_ONLY
288 if ((addr & (DATA_SIZE - 1)) != 0)
89c33337 289 do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
a64d4718 290#endif
bccd9ec5 291 tlb_fill(env, addr, 1, mmu_idx, retaddr);
b92e5a22
FB
292 goto redo;
293 }
294}
295
296/* handles all unaligned cases */
89c33337 297static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
e141ab52 298 target_ulong addr,
61382a50 299 DATA_TYPE val,
6ebbf390 300 int mmu_idx,
20503968 301 uintptr_t retaddr)
b92e5a22 302{
a8170e5e 303 hwaddr ioaddr;
c27004ec 304 target_ulong tlb_addr;
61382a50 305 int index, i;
b92e5a22 306
b92e5a22
FB
307 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
308 redo:
6ebbf390 309 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22 310 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
b92e5a22
FB
311 if (tlb_addr & ~TARGET_PAGE_MASK) {
312 /* IO access */
313 if ((addr & (DATA_SIZE - 1)) != 0)
314 goto do_unaligned_access;
37ec01d4 315 ioaddr = env->iotlb[mmu_idx][index];
89c33337 316 glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
98699967 317 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22
FB
318 do_unaligned_access:
319 /* XXX: not efficient, but simple */
6c41b272
AZ
320 /* Note: relies on the fact that tlb_fill() does not remove the
321 * previous page from the TLB cache. */
7221fa98 322 for(i = DATA_SIZE - 1; i >= 0; i--) {
b92e5a22 323#ifdef TARGET_WORDS_BIGENDIAN
89c33337 324 glue(slow_stb, MMUSUFFIX)(env, addr + i,
e141ab52 325 val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
6ebbf390 326 mmu_idx, retaddr);
b92e5a22 327#else
89c33337 328 glue(slow_stb, MMUSUFFIX)(env, addr + i,
e141ab52 329 val >> (i * 8),
6ebbf390 330 mmu_idx, retaddr);
b92e5a22
FB
331#endif
332 }
333 } else {
334 /* aligned/unaligned access in the same page */
b065927a
SW
335 uintptr_t addend = env->tlb_table[mmu_idx][index].addend;
336 glue(glue(st, SUFFIX), _raw)((uint8_t *)(intptr_t)
337 (addr + addend), val);
b92e5a22
FB
338 }
339 } else {
340 /* the page is not in the TLB : fill it */
bccd9ec5 341 tlb_fill(env, addr, 1, mmu_idx, retaddr);
b92e5a22
FB
342 goto redo;
343 }
344}
345
b769d8fe
FB
346#endif /* !defined(SOFTMMU_CODE_ACCESS) */
347
348#undef READ_ACCESS_TYPE
b92e5a22
FB
349#undef SHIFT
350#undef DATA_TYPE
351#undef SUFFIX
61382a50 352#undef USUFFIX
b92e5a22 353#undef DATA_SIZE
84b7b8e7 354#undef ADDR_READ