[mirror_qemu.git] / softmmu_template.h

/*
 *  Software MMU support
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#define DATA_SIZE (1 << SHIFT)

#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#else
#error unsupported data size
#endif

#ifdef SOFTMMU_CODE_ACCESS
#define READ_ACCESS_TYPE 2
#else
#define READ_ACCESS_TYPE 0
#endif

static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr, 
                                                        int is_user,
                                                        void *retaddr);
static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr, 
                                              target_ulong tlb_addr)
{
    DATA_TYPE res;
    int index;

    index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
#if SHIFT <= 2
    res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
    res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
#else
    res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
    res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
#endif
#endif /* SHIFT > 2 */
    return res;
}

/* handle all cases except unaligned access which span two pages */
DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                         int is_user)
{
    DATA_TYPE res;
    int index;
    target_ulong tlb_addr;
    target_phys_addr_t physaddr;
    void *retaddr;
    
    /* test if there is match for unaligned or IO access */
    /* XXX: could done more in memory macro in a non portable way */
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_read[is_user][index].address;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        physaddr = addr + env->tlb_read[is_user][index].addend;
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
            /* slow unaligned access (it spans two pages or IO) */
        do_unaligned_access:
            retaddr = GETPC();
            res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr, 
                                                         is_user, retaddr);
        } else {
            /* unaligned access in the same page */
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
        tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
        goto redo;
    }
    return res;
}

/* handle all unaligned cases */
static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr, 
                                                        int is_user,
                                                        void *retaddr)
{
    DATA_TYPE res, res1, res2;
    int index, shift;
    target_phys_addr_t physaddr;
    target_ulong tlb_addr, addr1, addr2;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_read[is_user][index].address;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        physaddr = addr + env->tlb_read[is_user][index].addend;
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* slow unaligned access (it spans two pages) */
            addr1 = addr & ~(DATA_SIZE - 1);
            addr2 = addr1 + DATA_SIZE;
            res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1, 
                                                          is_user, retaddr);
            res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2, 
                                                          is_user, retaddr);
            shift = (addr & (DATA_SIZE - 1)) * 8;
#ifdef TARGET_WORDS_BIGENDIAN
            res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
#else
            res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
#endif
            res = (DATA_TYPE)res;
        } else {
            /* unaligned/aligned access in the same page */
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
        goto redo;
    }
    return res;
}

#ifndef SOFTMMU_CODE_ACCESS

static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, 
                                                   DATA_TYPE val, 
                                                   int is_user,
                                                   void *retaddr);

static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr, 
                                          DATA_TYPE val,
                                          target_ulong tlb_addr,
                                          void *retaddr)
{
    int index;

    index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
    env->mem_write_vaddr = tlb_addr;
    env->mem_write_pc = (unsigned long)retaddr;
#if SHIFT <= 2
    io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
#else
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
#endif
#endif /* SHIFT > 2 */
}

void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, 
                                                    DATA_TYPE val,
                                                    int is_user)
{
    target_phys_addr_t physaddr;
    target_ulong tlb_addr;
    void *retaddr;
    int index;
    
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_write[is_user][index].address;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        physaddr = addr + env->tlb_write[is_user][index].addend;
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            retaddr = GETPC();
            glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val, 
                                                   is_user, retaddr);
        } else {
            /* aligned/unaligned access in the same page */
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
        tlb_fill(addr, 1, is_user, retaddr);
        goto redo;
    }
}

/* handles all unaligned cases */
static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, 
                                                   DATA_TYPE val,
                                                   int is_user,
                                                   void *retaddr)
{
    target_phys_addr_t physaddr;
    target_ulong tlb_addr;
    int index, i;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_write[is_user][index].address;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        physaddr = addr + env->tlb_write[is_user][index].addend;
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* XXX: not efficient, but simple */
            for(i = 0;i < DATA_SIZE; i++) {
#ifdef TARGET_WORDS_BIGENDIAN
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)), 
                                          is_user, retaddr);
#else
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8), 
                                          is_user, retaddr);
#endif
            }
        } else {
            /* aligned/unaligned access in the same page */
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, 1, is_user, retaddr);
        goto redo;
    }
}

#endif /* !defined(SOFTMMU_CODE_ACCESS) */

#undef READ_ACCESS_TYPE
#undef SHIFT
#undef DATA_TYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
Commit	Line	Data
b92e5a22 FB	1	/*
	2	* Software MMU support
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#define DATA_SIZE (1 << SHIFT)
	21
	22	#if DATA_SIZE == 8
	23	#define SUFFIX q
61382a50	24	#define USUFFIX q
b92e5a22 FB	25	#define DATA_TYPE uint64_t
	26	#elif DATA_SIZE == 4
	27	#define SUFFIX l
61382a50	28	#define USUFFIX l
b92e5a22 FB	29	#define DATA_TYPE uint32_t
	30	#elif DATA_SIZE == 2
	31	#define SUFFIX w
61382a50	32	#define USUFFIX uw
b92e5a22 FB	33	#define DATA_TYPE uint16_t
	34	#elif DATA_SIZE == 1
	35	#define SUFFIX b
61382a50	36	#define USUFFIX ub
b92e5a22 FB	37	#define DATA_TYPE uint8_t
	38	#else
	39	#error unsupported data size
	40	#endif
	41
b769d8fe FB	42	#ifdef SOFTMMU_CODE_ACCESS
	43	#define READ_ACCESS_TYPE 2
	44	#else
	45	#define READ_ACCESS_TYPE 0
	46	#endif
	47
c27004ec	48	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50 FB	49	int is_user,
61382a50 FB	50	void *retaddr);
108c49b8	51	static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
c27004ec	52	target_ulong tlb_addr)
b92e5a22 FB	53	{
	54	DATA_TYPE res;
	55	int index;
	56
	57	index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
	58	#if SHIFT <= 2
a4193c8a	59	res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
b92e5a22 FB	60	#else
b92e5a22 FB	61	#ifdef TARGET_WORDS_BIGENDIAN
a4193c8a FB	62	res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
a4193c8a FB	63	res \|= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
b92e5a22	64	#else
a4193c8a FB	65	res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
a4193c8a FB	66	res \|= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
b92e5a22 FB	67	#endif
	68	#endif /* SHIFT > 2 */
	69	return res;
	70	}
	71
b92e5a22	72	/* handle all cases except unaligned access which span two pages */
c27004ec	73	DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50	74	int is_user)
b92e5a22 FB	75	{
b92e5a22 FB	76	DATA_TYPE res;
61382a50	77	int index;
c27004ec	78	target_ulong tlb_addr;
108c49b8	79	target_phys_addr_t physaddr;
b92e5a22 FB	80	void *retaddr;
	81
	82	/* test if there is match for unaligned or IO access */
	83	/* XXX: could done more in memory macro in a non portable way */
b92e5a22 FB	84	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	85	redo:
	86	tlb_addr = env->tlb_read[is_user][index].address;
	87	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
	88	physaddr = addr + env->tlb_read[is_user][index].addend;
	89	if (tlb_addr & ~TARGET_PAGE_MASK) {
	90	/* IO access */
	91	if ((addr & (DATA_SIZE - 1)) != 0)
	92	goto do_unaligned_access;
	93	res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
98699967	94	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	95	/* slow unaligned access (it spans two pages or IO) */
b92e5a22 FB	96	do_unaligned_access:
61382a50 FB	97	retaddr = GETPC();
	98	res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
	99	is_user, retaddr);
b92e5a22 FB	100	} else {
b92e5a22 FB	101	/* unaligned access in the same page */
108c49b8	102	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
b92e5a22 FB	103	}
	104	} else {
	105	/* the page is not in the TLB : fill it */
61382a50	106	retaddr = GETPC();
b769d8fe	107	tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
b92e5a22 FB	108	goto redo;
	109	}
	110	return res;
	111	}
	112
	113	/* handle all unaligned cases */
c27004ec	114	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50 FB	115	int is_user,
61382a50 FB	116	void *retaddr)
b92e5a22 FB	117	{
b92e5a22 FB	118	DATA_TYPE res, res1, res2;
61382a50	119	int index, shift;
108c49b8	120	target_phys_addr_t physaddr;
c27004ec	121	target_ulong tlb_addr, addr1, addr2;
b92e5a22	122
b92e5a22 FB	123	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	124	redo:
	125	tlb_addr = env->tlb_read[is_user][index].address;
	126	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
	127	physaddr = addr + env->tlb_read[is_user][index].addend;
	128	if (tlb_addr & ~TARGET_PAGE_MASK) {
	129	/* IO access */
	130	if ((addr & (DATA_SIZE - 1)) != 0)
	131	goto do_unaligned_access;
	132	res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
98699967	133	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	134	do_unaligned_access:
	135	/* slow unaligned access (it spans two pages) */
	136	addr1 = addr & ~(DATA_SIZE - 1);
	137	addr2 = addr1 + DATA_SIZE;
61382a50 FB	138	res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
	139	is_user, retaddr);
	140	res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
	141	is_user, retaddr);
b92e5a22 FB	142	shift = (addr & (DATA_SIZE - 1)) * 8;
	143	#ifdef TARGET_WORDS_BIGENDIAN
	144	res = (res1 << shift) \| (res2 >> ((DATA_SIZE * 8) - shift));
	145	#else
	146	res = (res1 >> shift) \| (res2 << ((DATA_SIZE * 8) - shift));
	147	#endif
6986f88c	148	res = (DATA_TYPE)res;
b92e5a22 FB	149	} else {
b92e5a22 FB	150	/* unaligned/aligned access in the same page */
108c49b8	151	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
b92e5a22 FB	152	}
	153	} else {
	154	/* the page is not in the TLB : fill it */
b769d8fe	155	tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
b92e5a22 FB	156	goto redo;
	157	}
	158	return res;
	159	}
	160
b769d8fe FB	161	#ifndef SOFTMMU_CODE_ACCESS
b769d8fe FB	162
c27004ec	163	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
b769d8fe FB	164	DATA_TYPE val,
	165	int is_user,
	166	void *retaddr);
	167
108c49b8	168	static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
b769d8fe	169	DATA_TYPE val,
c27004ec	170	target_ulong tlb_addr,
b769d8fe FB	171	void *retaddr)
	172	{
	173	int index;
	174
	175	index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
	176	env->mem_write_vaddr = tlb_addr;
	177	env->mem_write_pc = (unsigned long)retaddr;
	178	#if SHIFT <= 2
	179	io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
	180	#else
	181	#ifdef TARGET_WORDS_BIGENDIAN
	182	io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
	183	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
	184	#else
	185	io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
	186	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
	187	#endif
	188	#endif /* SHIFT > 2 */
	189	}
b92e5a22	190
c27004ec	191	void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50 FB	192	DATA_TYPE val,
61382a50 FB	193	int is_user)
b92e5a22	194	{
108c49b8	195	target_phys_addr_t physaddr;
c27004ec	196	target_ulong tlb_addr;
b92e5a22	197	void *retaddr;
61382a50	198	int index;
b92e5a22	199
b92e5a22 FB	200	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	201	redo:
	202	tlb_addr = env->tlb_write[is_user][index].address;
	203	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
4ad06a29	204	physaddr = addr + env->tlb_write[is_user][index].addend;
b92e5a22 FB	205	if (tlb_addr & ~TARGET_PAGE_MASK) {
	206	/* IO access */
	207	if ((addr & (DATA_SIZE - 1)) != 0)
	208	goto do_unaligned_access;
d720b93d FB	209	retaddr = GETPC();
d720b93d FB	210	glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
98699967	211	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22	212	do_unaligned_access:
61382a50 FB	213	retaddr = GETPC();
	214	glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
	215	is_user, retaddr);
b92e5a22 FB	216	} else {
b92e5a22 FB	217	/* aligned/unaligned access in the same page */
108c49b8	218	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
b92e5a22 FB	219	}
	220	} else {
	221	/* the page is not in the TLB : fill it */
61382a50 FB	222	retaddr = GETPC();
61382a50 FB	223	tlb_fill(addr, 1, is_user, retaddr);
b92e5a22 FB	224	goto redo;
	225	}
	226	}
	227
	228	/* handles all unaligned cases */
c27004ec	229	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50 FB	230	DATA_TYPE val,
	231	int is_user,
	232	void *retaddr)
b92e5a22	233	{
108c49b8	234	target_phys_addr_t physaddr;
c27004ec	235	target_ulong tlb_addr;
61382a50	236	int index, i;
b92e5a22	237
b92e5a22 FB	238	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
	239	redo:
	240	tlb_addr = env->tlb_write[is_user][index].address;
	241	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
4ad06a29	242	physaddr = addr + env->tlb_write[is_user][index].addend;
b92e5a22 FB	243	if (tlb_addr & ~TARGET_PAGE_MASK) {
	244	/* IO access */
	245	if ((addr & (DATA_SIZE - 1)) != 0)
	246	goto do_unaligned_access;
d720b93d	247	glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
98699967	248	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	249	do_unaligned_access:
	250	/* XXX: not efficient, but simple */
	251	for(i = 0;i < DATA_SIZE; i++) {
	252	#ifdef TARGET_WORDS_BIGENDIAN
61382a50 FB	253	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
61382a50 FB	254	is_user, retaddr);
b92e5a22	255	#else
61382a50 FB	256	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
61382a50 FB	257	is_user, retaddr);
b92e5a22 FB	258	#endif
	259	}
	260	} else {
	261	/* aligned/unaligned access in the same page */
108c49b8	262	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
b92e5a22 FB	263	}
	264	} else {
	265	/* the page is not in the TLB : fill it */
61382a50	266	tlb_fill(addr, 1, is_user, retaddr);
b92e5a22 FB	267	goto redo;
	268	}
	269	}
	270
b769d8fe FB	271	#endif /* !defined(SOFTMMU_CODE_ACCESS) */
	272
	273	#undef READ_ACCESS_TYPE
b92e5a22 FB	274	#undef SHIFT
	275	#undef DATA_TYPE
	276	#undef SUFFIX
61382a50	277	#undef USUFFIX
b92e5a22	278	#undef DATA_SIZE