[mirror_qemu.git] / softmmu_template.h

/*
 *  Software MMU support
 *
 * Generate helpers used by TCG for qemu_ld/st ops and code load
 * functions.
 *
 * Included from target op helpers and exec.c.
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu-timer.h"
#include "memory.h"

#define DATA_SIZE (1 << SHIFT)

#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#else
#error unsupported data size
#endif

#ifdef SOFTMMU_CODE_ACCESS
#define READ_ACCESS_TYPE 2
#define ADDR_READ addr_code
#else
#define READ_ACCESS_TYPE 0
#define ADDR_READ addr_read
#endif

#ifndef CONFIG_TCG_PASS_AREG0
#define ENV_PARAM
#define ENV_VAR
#define CPU_PREFIX
#define HELPER_PREFIX __
#else
#define ENV_PARAM CPUArchState *env,
#define ENV_VAR env,
#define CPU_PREFIX cpu_
#define HELPER_PREFIX helper_
#endif

static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
                                                        target_ulong addr,
                                                        int mmu_idx,
                                                        void *retaddr);
static inline DATA_TYPE glue(io_read, SUFFIX)(ENV_PARAM
                                              target_phys_addr_t physaddr,
                                              target_ulong addr,
                                              void *retaddr)
{
    DATA_TYPE res;
    MemoryRegion *mr = iotlb_to_region(physaddr);

    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    env->mem_io_pc = (unsigned long)retaddr;
    if (mr != &io_mem_ram && mr != &io_mem_rom
        && mr != &io_mem_unassigned
        && mr != &io_mem_notdirty
            && !can_do_io(env)) {
        cpu_io_recompile(env, retaddr);
    }

    env->mem_io_vaddr = addr;
#if SHIFT <= 2
    res = io_mem_read(mr, physaddr, 1 << SHIFT);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    res = io_mem_read(mr, physaddr, 4) << 32;
    res |= io_mem_read(mr, physaddr + 4, 4);
#else
    res = io_mem_read(mr, physaddr, 4);
    res |= io_mem_read(mr, physaddr + 4, 4) << 32;
#endif
#endif /* SHIFT > 2 */
    return res;
}

/* handle all cases except unaligned access which span two pages */
DATA_TYPE
glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
                                                       target_ulong addr,
                                                       int mmu_idx)
{
    DATA_TYPE res;
    int index;
    target_ulong tlb_addr;
    target_phys_addr_t ioaddr;
    unsigned long addend;
    void *retaddr;

    /* test if there is match for unaligned or IO access */
    /* XXX: could done more in memory macro in a non portable way */
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            ioaddr = env->iotlb[mmu_idx][index];
            res = glue(io_read, SUFFIX)(ENV_VAR ioaddr, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
            /* slow unaligned access (it spans two pages or IO) */
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
            res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr,
                                                         mmu_idx, retaddr);
        } else {
            /* unaligned/aligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
            }
#endif
            addend = env->tlb_table[mmu_idx][index].addend;
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
        tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

/* handle all unaligned cases */
static DATA_TYPE
glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
                                       target_ulong addr,
                                       int mmu_idx,
                                       void *retaddr)
{
    DATA_TYPE res, res1, res2;
    int index, shift;
    target_phys_addr_t ioaddr;
    unsigned long addend;
    target_ulong tlb_addr, addr1, addr2;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            ioaddr = env->iotlb[mmu_idx][index];
            res = glue(io_read, SUFFIX)(ENV_VAR ioaddr, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* slow unaligned access (it spans two pages) */
            addr1 = addr & ~(DATA_SIZE - 1);
            addr2 = addr1 + DATA_SIZE;
            res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr1,
                                                          mmu_idx, retaddr);
            res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr2,
                                                          mmu_idx, retaddr);
            shift = (addr & (DATA_SIZE - 1)) * 8;
#ifdef TARGET_WORDS_BIGENDIAN
            res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
#else
            res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
#endif
            res = (DATA_TYPE)res;
        } else {
            /* unaligned/aligned access in the same page */
            addend = env->tlb_table[mmu_idx][index].addend;
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

#ifndef SOFTMMU_CODE_ACCESS

static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
                                                   target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   void *retaddr);

static inline void glue(io_write, SUFFIX)(ENV_PARAM
                                          target_phys_addr_t physaddr,
                                          DATA_TYPE val,
                                          target_ulong addr,
                                          void *retaddr)
{
    MemoryRegion *mr = iotlb_to_region(physaddr);

    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    if (mr != &io_mem_ram && mr != &io_mem_rom
        && mr != &io_mem_unassigned
        && mr != &io_mem_notdirty
            && !can_do_io(env)) {
        cpu_io_recompile(env, retaddr);
    }

    env->mem_io_vaddr = addr;
    env->mem_io_pc = (unsigned long)retaddr;
#if SHIFT <= 2
    io_mem_write(mr, physaddr, val, 1 << SHIFT);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    io_mem_write(mr, physaddr, (val >> 32), 4);
    io_mem_write(mr, physaddr + 4, (uint32_t)val, 4);
#else
    io_mem_write(mr, physaddr, (uint32_t)val, 4);
    io_mem_write(mr, physaddr + 4, val >> 32, 4);
#endif
#endif /* SHIFT > 2 */
}

void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
                                                            target_ulong addr,
                                                            DATA_TYPE val,
                                                            int mmu_idx)
{
    target_phys_addr_t ioaddr;
    unsigned long addend;
    target_ulong tlb_addr;
    void *retaddr;
    int index;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            ioaddr = env->iotlb[mmu_idx][index];
            glue(io_write, SUFFIX)(ENV_VAR ioaddr, val, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
#endif
            glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_VAR addr, val,
                                                   mmu_idx, retaddr);
        } else {
            /* aligned/unaligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
            }
#endif
            addend = env->tlb_table[mmu_idx][index].addend;
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
#endif
        tlb_fill(env, addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

/* handles all unaligned cases */
static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
                                                   target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   void *retaddr)
{
    target_phys_addr_t ioaddr;
    unsigned long addend;
    target_ulong tlb_addr;
    int index, i;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            ioaddr = env->iotlb[mmu_idx][index];
            glue(io_write, SUFFIX)(ENV_VAR ioaddr, val, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* XXX: not efficient, but simple */
            /* Note: relies on the fact that tlb_fill() does not remove the
             * previous page from the TLB cache.  */
            for(i = DATA_SIZE - 1; i >= 0; i--) {
#ifdef TARGET_WORDS_BIGENDIAN
                glue(slow_stb, MMUSUFFIX)(ENV_VAR addr + i,
                                          val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
                                          mmu_idx, retaddr);
#else
                glue(slow_stb, MMUSUFFIX)(ENV_VAR addr + i,
                                          val >> (i * 8),
                                          mmu_idx, retaddr);
#endif
            }
        } else {
            /* aligned/unaligned access in the same page */
            addend = env->tlb_table[mmu_idx][index].addend;
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(env, addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

#endif /* !defined(SOFTMMU_CODE_ACCESS) */

#undef READ_ACCESS_TYPE
#undef SHIFT
#undef DATA_TYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef ADDR_READ
#undef ENV_PARAM
#undef ENV_VAR
#undef CPU_PREFIX
#undef HELPER_PREFIX
Commit	Line	Data
b92e5a22 FB	1	/*
b92e5a22 FB	2	* Software MMU support
5fafdf24	3	*
efbf29b6 BS	4	* Generate helpers used by TCG for qemu_ld/st ops and code load
	5	* functions.
	6	*
	7	* Included from target op helpers and exec.c.
	8	*
b92e5a22 FB	9	* Copyright (c) 2003 Fabrice Bellard
	10	*
	11	* This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU Lesser General Public
	13	* License as published by the Free Software Foundation; either
	14	* version 2 of the License, or (at your option) any later version.
	15	*
	16	* This library is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	19	* Lesser General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU Lesser General Public
8167ee88	22	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
b92e5a22	23	*/
29e922b6	24	#include "qemu-timer.h"
0e0df1e2	25	#include "memory.h"
29e922b6	26
b92e5a22 FB	27	#define DATA_SIZE (1 << SHIFT)
	28
	29	#if DATA_SIZE == 8
	30	#define SUFFIX q
61382a50	31	#define USUFFIX q
b92e5a22 FB	32	#define DATA_TYPE uint64_t
	33	#elif DATA_SIZE == 4
	34	#define SUFFIX l
61382a50	35	#define USUFFIX l
b92e5a22 FB	36	#define DATA_TYPE uint32_t
	37	#elif DATA_SIZE == 2
	38	#define SUFFIX w
61382a50	39	#define USUFFIX uw
b92e5a22 FB	40	#define DATA_TYPE uint16_t
	41	#elif DATA_SIZE == 1
	42	#define SUFFIX b
61382a50	43	#define USUFFIX ub
b92e5a22 FB	44	#define DATA_TYPE uint8_t
	45	#else
	46	#error unsupported data size
	47	#endif
	48
b769d8fe FB	49	#ifdef SOFTMMU_CODE_ACCESS
b769d8fe FB	50	#define READ_ACCESS_TYPE 2
84b7b8e7	51	#define ADDR_READ addr_code
b769d8fe FB	52	#else
b769d8fe FB	53	#define READ_ACCESS_TYPE 0
84b7b8e7	54	#define ADDR_READ addr_read
b769d8fe FB	55	#endif
b769d8fe FB	56
e141ab52 BS	57	#ifndef CONFIG_TCG_PASS_AREG0
	58	#define ENV_PARAM
	59	#define ENV_VAR
	60	#define CPU_PREFIX
	61	#define HELPER_PREFIX __
	62	#else
	63	#define ENV_PARAM CPUArchState *env,
	64	#define ENV_VAR env,
	65	#define CPU_PREFIX cpu_
	66	#define HELPER_PREFIX helper_
	67	#endif
	68
	69	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
	70	target_ulong addr,
6ebbf390	71	int mmu_idx,
61382a50	72	void *retaddr);
e141ab52 BS	73	static inline DATA_TYPE glue(io_read, SUFFIX)(ENV_PARAM
e141ab52 BS	74	target_phys_addr_t physaddr,
2e70f6ef PB	75	target_ulong addr,
2e70f6ef PB	76	void *retaddr)
b92e5a22 FB	77	{
b92e5a22 FB	78	DATA_TYPE res;
37ec01d4 AK	79	MemoryRegion *mr = iotlb_to_region(physaddr);
37ec01d4 AK	80
0f459d16	81	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
2e70f6ef	82	env->mem_io_pc = (unsigned long)retaddr;
37ec01d4 AK	83	if (mr != &io_mem_ram && mr != &io_mem_rom
	84	&& mr != &io_mem_unassigned
	85	&& mr != &io_mem_notdirty
2e70f6ef PB	86	&& !can_do_io(env)) {
	87	cpu_io_recompile(env, retaddr);
	88	}
b92e5a22	89
db8886d3	90	env->mem_io_vaddr = addr;
b92e5a22	91	#if SHIFT <= 2
37ec01d4	92	res = io_mem_read(mr, physaddr, 1 << SHIFT);
b92e5a22 FB	93	#else
b92e5a22 FB	94	#ifdef TARGET_WORDS_BIGENDIAN
37ec01d4 AK	95	res = io_mem_read(mr, physaddr, 4) << 32;
37ec01d4 AK	96	res \|= io_mem_read(mr, physaddr + 4, 4);
b92e5a22	97	#else
37ec01d4 AK	98	res = io_mem_read(mr, physaddr, 4);
37ec01d4 AK	99	res \|= io_mem_read(mr, physaddr + 4, 4) << 32;
b92e5a22 FB	100	#endif
	101	#endif /* SHIFT > 2 */
	102	return res;
	103	}
	104
b92e5a22	105	/* handle all cases except unaligned access which span two pages */
e141ab52 BS	106	DATA_TYPE
	107	glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
	108	target_ulong addr,
	109	int mmu_idx)
b92e5a22 FB	110	{
b92e5a22 FB	111	DATA_TYPE res;
61382a50	112	int index;
c27004ec	113	target_ulong tlb_addr;
355b1943 PB	114	target_phys_addr_t ioaddr;
355b1943 PB	115	unsigned long addend;
b92e5a22	116	void *retaddr;
3b46e624	117
b92e5a22 FB	118	/* test if there is match for unaligned or IO access */
b92e5a22 FB	119	/* XXX: could done more in memory macro in a non portable way */
b92e5a22 FB	120	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	121	redo:
6ebbf390	122	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22	123	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	124	if (tlb_addr & ~TARGET_PAGE_MASK) {
	125	/* IO access */
	126	if ((addr & (DATA_SIZE - 1)) != 0)
	127	goto do_unaligned_access;
2e70f6ef	128	retaddr = GETPC();
37ec01d4	129	ioaddr = env->iotlb[mmu_idx][index];
e141ab52	130	res = glue(io_read, SUFFIX)(ENV_VAR ioaddr, addr, retaddr);
98699967	131	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	132	/* slow unaligned access (it spans two pages or IO) */
b92e5a22 FB	133	do_unaligned_access:
61382a50	134	retaddr = GETPC();
a64d4718	135	#ifdef ALIGNED_ONLY
e141ab52	136	do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718	137	#endif
e141ab52	138	res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr,
6ebbf390	139	mmu_idx, retaddr);
b92e5a22	140	} else {
a64d4718 FB	141	/* unaligned/aligned access in the same page */
	142	#ifdef ALIGNED_ONLY
	143	if ((addr & (DATA_SIZE - 1)) != 0) {
	144	retaddr = GETPC();
e141ab52	145	do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718 FB	146	}
a64d4718 FB	147	#endif
0f459d16 PB	148	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	149	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
b92e5a22 FB	150	}
	151	} else {
	152	/* the page is not in the TLB : fill it */
61382a50	153	retaddr = GETPC();
a64d4718 FB	154	#ifdef ALIGNED_ONLY
a64d4718 FB	155	if ((addr & (DATA_SIZE - 1)) != 0)
e141ab52	156	do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718	157	#endif
bccd9ec5	158	tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22 FB	159	goto redo;
	160	}
	161	return res;
	162	}
	163
	164	/* handle all unaligned cases */
e141ab52 BS	165	static DATA_TYPE
	166	glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
	167	target_ulong addr,
	168	int mmu_idx,
	169	void *retaddr)
b92e5a22 FB	170	{
b92e5a22 FB	171	DATA_TYPE res, res1, res2;
61382a50	172	int index, shift;
355b1943 PB	173	target_phys_addr_t ioaddr;
355b1943 PB	174	unsigned long addend;
c27004ec	175	target_ulong tlb_addr, addr1, addr2;
b92e5a22	176
b92e5a22 FB	177	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	178	redo:
6ebbf390	179	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22	180	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	181	if (tlb_addr & ~TARGET_PAGE_MASK) {
	182	/* IO access */
	183	if ((addr & (DATA_SIZE - 1)) != 0)
	184	goto do_unaligned_access;
37ec01d4	185	ioaddr = env->iotlb[mmu_idx][index];
e141ab52	186	res = glue(io_read, SUFFIX)(ENV_VAR ioaddr, addr, retaddr);
98699967	187	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	188	do_unaligned_access:
	189	/* slow unaligned access (it spans two pages) */
	190	addr1 = addr & ~(DATA_SIZE - 1);
	191	addr2 = addr1 + DATA_SIZE;
e141ab52	192	res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr1,
6ebbf390	193	mmu_idx, retaddr);
e141ab52	194	res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr2,
6ebbf390	195	mmu_idx, retaddr);
b92e5a22 FB	196	shift = (addr & (DATA_SIZE - 1)) * 8;
	197	#ifdef TARGET_WORDS_BIGENDIAN
	198	res = (res1 << shift) \| (res2 >> ((DATA_SIZE * 8) - shift));
	199	#else
	200	res = (res1 >> shift) \| (res2 << ((DATA_SIZE * 8) - shift));
	201	#endif
6986f88c	202	res = (DATA_TYPE)res;
b92e5a22 FB	203	} else {
b92e5a22 FB	204	/* unaligned/aligned access in the same page */
0f459d16 PB	205	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	206	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
b92e5a22 FB	207	}
	208	} else {
	209	/* the page is not in the TLB : fill it */
bccd9ec5	210	tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22 FB	211	goto redo;
	212	}
	213	return res;
	214	}
	215
b769d8fe FB	216	#ifndef SOFTMMU_CODE_ACCESS
b769d8fe FB	217
e141ab52 BS	218	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
e141ab52 BS	219	target_ulong addr,
5fafdf24	220	DATA_TYPE val,
6ebbf390	221	int mmu_idx,
b769d8fe FB	222	void *retaddr);
b769d8fe FB	223
e141ab52 BS	224	static inline void glue(io_write, SUFFIX)(ENV_PARAM
e141ab52 BS	225	target_phys_addr_t physaddr,
b769d8fe	226	DATA_TYPE val,
0f459d16	227	target_ulong addr,
b769d8fe FB	228	void *retaddr)
b769d8fe FB	229	{
37ec01d4 AK	230	MemoryRegion *mr = iotlb_to_region(physaddr);
37ec01d4 AK	231
0f459d16	232	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
37ec01d4 AK	233	if (mr != &io_mem_ram && mr != &io_mem_rom
	234	&& mr != &io_mem_unassigned
	235	&& mr != &io_mem_notdirty
2e70f6ef PB	236	&& !can_do_io(env)) {
	237	cpu_io_recompile(env, retaddr);
	238	}
b769d8fe	239
2e70f6ef PB	240	env->mem_io_vaddr = addr;
2e70f6ef PB	241	env->mem_io_pc = (unsigned long)retaddr;
b769d8fe	242	#if SHIFT <= 2
37ec01d4	243	io_mem_write(mr, physaddr, val, 1 << SHIFT);
b769d8fe FB	244	#else
b769d8fe FB	245	#ifdef TARGET_WORDS_BIGENDIAN
37ec01d4 AK	246	io_mem_write(mr, physaddr, (val >> 32), 4);
37ec01d4 AK	247	io_mem_write(mr, physaddr + 4, (uint32_t)val, 4);
b769d8fe	248	#else
37ec01d4 AK	249	io_mem_write(mr, physaddr, (uint32_t)val, 4);
37ec01d4 AK	250	io_mem_write(mr, physaddr + 4, val >> 32, 4);
b769d8fe FB	251	#endif
	252	#endif /* SHIFT > 2 */
	253	}
b92e5a22	254
e141ab52 BS	255	void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
	256	target_ulong addr,
	257	DATA_TYPE val,
	258	int mmu_idx)
b92e5a22	259	{
355b1943 PB	260	target_phys_addr_t ioaddr;
355b1943 PB	261	unsigned long addend;
c27004ec	262	target_ulong tlb_addr;
b92e5a22	263	void *retaddr;
61382a50	264	int index;
3b46e624	265
b92e5a22 FB	266	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	267	redo:
6ebbf390	268	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22	269	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	270	if (tlb_addr & ~TARGET_PAGE_MASK) {
	271	/* IO access */
	272	if ((addr & (DATA_SIZE - 1)) != 0)
	273	goto do_unaligned_access;
d720b93d	274	retaddr = GETPC();
37ec01d4	275	ioaddr = env->iotlb[mmu_idx][index];
e141ab52	276	glue(io_write, SUFFIX)(ENV_VAR ioaddr, val, addr, retaddr);
98699967	277	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22	278	do_unaligned_access:
61382a50	279	retaddr = GETPC();
a64d4718	280	#ifdef ALIGNED_ONLY
e141ab52	281	do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
a64d4718	282	#endif
e141ab52	283	glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_VAR addr, val,
6ebbf390	284	mmu_idx, retaddr);
b92e5a22 FB	285	} else {
b92e5a22 FB	286	/* aligned/unaligned access in the same page */
a64d4718 FB	287	#ifdef ALIGNED_ONLY
	288	if ((addr & (DATA_SIZE - 1)) != 0) {
	289	retaddr = GETPC();
e141ab52	290	do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
a64d4718 FB	291	}
a64d4718 FB	292	#endif
0f459d16 PB	293	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	294	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
b92e5a22 FB	295	}
	296	} else {
	297	/* the page is not in the TLB : fill it */
61382a50	298	retaddr = GETPC();
a64d4718 FB	299	#ifdef ALIGNED_ONLY
a64d4718 FB	300	if ((addr & (DATA_SIZE - 1)) != 0)
e141ab52	301	do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
a64d4718	302	#endif
bccd9ec5	303	tlb_fill(env, addr, 1, mmu_idx, retaddr);
b92e5a22 FB	304	goto redo;
	305	}
	306	}
	307
	308	/* handles all unaligned cases */
e141ab52 BS	309	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
e141ab52 BS	310	target_ulong addr,
61382a50	311	DATA_TYPE val,
6ebbf390	312	int mmu_idx,
61382a50	313	void *retaddr)
b92e5a22	314	{
355b1943 PB	315	target_phys_addr_t ioaddr;
355b1943 PB	316	unsigned long addend;
c27004ec	317	target_ulong tlb_addr;
61382a50	318	int index, i;
b92e5a22	319
b92e5a22 FB	320	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	321	redo:
6ebbf390	322	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22	323	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	324	if (tlb_addr & ~TARGET_PAGE_MASK) {
	325	/* IO access */
	326	if ((addr & (DATA_SIZE - 1)) != 0)
	327	goto do_unaligned_access;
37ec01d4	328	ioaddr = env->iotlb[mmu_idx][index];
e141ab52	329	glue(io_write, SUFFIX)(ENV_VAR ioaddr, val, addr, retaddr);
98699967	330	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	331	do_unaligned_access:
b92e5a22 FB	332	/* XXX: not efficient, but simple */
6c41b272 AZ	333	/* Note: relies on the fact that tlb_fill() does not remove the
6c41b272 AZ	334	* previous page from the TLB cache. */
7221fa98	335	for(i = DATA_SIZE - 1; i >= 0; i--) {
b92e5a22	336	#ifdef TARGET_WORDS_BIGENDIAN
e141ab52 BS	337	glue(slow_stb, MMUSUFFIX)(ENV_VAR addr + i,
e141ab52 BS	338	val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
6ebbf390	339	mmu_idx, retaddr);
b92e5a22	340	#else
e141ab52 BS	341	glue(slow_stb, MMUSUFFIX)(ENV_VAR addr + i,
e141ab52 BS	342	val >> (i * 8),
6ebbf390	343	mmu_idx, retaddr);
b92e5a22 FB	344	#endif
	345	}
	346	} else {
	347	/* aligned/unaligned access in the same page */
0f459d16 PB	348	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	349	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
b92e5a22 FB	350	}
	351	} else {
	352	/* the page is not in the TLB : fill it */
bccd9ec5	353	tlb_fill(env, addr, 1, mmu_idx, retaddr);
b92e5a22 FB	354	goto redo;
	355	}
	356	}
	357
b769d8fe FB	358	#endif /* !defined(SOFTMMU_CODE_ACCESS) */
	359
	360	#undef READ_ACCESS_TYPE
b92e5a22 FB	361	#undef SHIFT
	362	#undef DATA_TYPE
	363	#undef SUFFIX
61382a50	364	#undef USUFFIX
b92e5a22	365	#undef DATA_SIZE
84b7b8e7	366	#undef ADDR_READ
e141ab52 BS	367	#undef ENV_PARAM
	368	#undef ENV_VAR
	369	#undef CPU_PREFIX
	370	#undef HELPER_PREFIX