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cb5a6ffc RK |
1 | /* |
2 | * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver | |
3 | * | |
4 | * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Documentation: ARM DDI 0173B | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/ioport.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/err.h> | |
a62c80e5 | 20 | #include <linux/amba/bus.h> |
cb5a6ffc RK |
21 | |
22 | #include <asm/io.h> | |
23 | #include <asm/irq.h> | |
c6b8fdad | 24 | #include <asm/sizes.h> |
cb5a6ffc RK |
25 | |
26 | #include <sound/driver.h> | |
27 | #include <sound/core.h> | |
28 | #include <sound/initval.h> | |
29 | #include <sound/ac97_codec.h> | |
30 | #include <sound/pcm.h> | |
31 | #include <sound/pcm_params.h> | |
32 | ||
33 | #include "aaci.h" | |
34 | #include "devdma.h" | |
35 | ||
36 | #define DRIVER_NAME "aaci-pl041" | |
37 | ||
38 | /* | |
39 | * PM support is not complete. Turn it off. | |
40 | */ | |
41 | #undef CONFIG_PM | |
42 | ||
ceb9e476 | 43 | static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97) |
cb5a6ffc RK |
44 | { |
45 | u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num); | |
46 | ||
47 | /* | |
48 | * Ensure that the slot 1/2 RX registers are empty. | |
49 | */ | |
50 | v = readl(aaci->base + AACI_SLFR); | |
51 | if (v & SLFR_2RXV) | |
52 | readl(aaci->base + AACI_SL2RX); | |
53 | if (v & SLFR_1RXV) | |
54 | readl(aaci->base + AACI_SL1RX); | |
55 | ||
56 | writel(maincr, aaci->base + AACI_MAINCR); | |
57 | } | |
58 | ||
59 | /* | |
60 | * P29: | |
61 | * The recommended use of programming the external codec through slot 1 | |
62 | * and slot 2 data is to use the channels during setup routines and the | |
63 | * slot register at any other time. The data written into slot 1, slot 2 | |
64 | * and slot 12 registers is transmitted only when their corresponding | |
65 | * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR | |
66 | * register. | |
67 | */ | |
ceb9e476 | 68 | static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) |
cb5a6ffc RK |
69 | { |
70 | struct aaci *aaci = ac97->private_data; | |
71 | u32 v; | |
72 | ||
73 | if (ac97->num >= 4) | |
74 | return; | |
75 | ||
76 | down(&aaci->ac97_sem); | |
77 | ||
78 | aaci_ac97_select_codec(aaci, ac97); | |
79 | ||
80 | /* | |
81 | * P54: You must ensure that AACI_SL2TX is always written | |
82 | * to, if required, before data is written to AACI_SL1TX. | |
83 | */ | |
84 | writel(val << 4, aaci->base + AACI_SL2TX); | |
85 | writel(reg << 12, aaci->base + AACI_SL1TX); | |
86 | ||
87 | /* | |
88 | * Wait for the transmission of both slots to complete. | |
89 | */ | |
90 | do { | |
91 | v = readl(aaci->base + AACI_SLFR); | |
92 | } while (v & (SLFR_1TXB|SLFR_2TXB)); | |
93 | ||
94 | up(&aaci->ac97_sem); | |
95 | } | |
96 | ||
97 | /* | |
98 | * Read an AC'97 register. | |
99 | */ | |
ceb9e476 | 100 | static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg) |
cb5a6ffc RK |
101 | { |
102 | struct aaci *aaci = ac97->private_data; | |
103 | u32 v; | |
104 | ||
105 | if (ac97->num >= 4) | |
106 | return ~0; | |
107 | ||
108 | down(&aaci->ac97_sem); | |
109 | ||
110 | aaci_ac97_select_codec(aaci, ac97); | |
111 | ||
112 | /* | |
113 | * Write the register address to slot 1. | |
114 | */ | |
115 | writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX); | |
116 | ||
117 | /* | |
118 | * Wait for the transmission to complete. | |
119 | */ | |
120 | do { | |
121 | v = readl(aaci->base + AACI_SLFR); | |
122 | } while (v & SLFR_1TXB); | |
123 | ||
124 | /* | |
125 | * Give the AC'97 codec more than enough time | |
126 | * to respond. (42us = ~2 frames at 48kHz.) | |
127 | */ | |
128 | udelay(42); | |
129 | ||
130 | /* | |
131 | * Wait for slot 2 to indicate data. | |
132 | */ | |
133 | do { | |
134 | cond_resched(); | |
135 | v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV); | |
136 | } while (v != (SLFR_1RXV|SLFR_2RXV)); | |
137 | ||
138 | v = readl(aaci->base + AACI_SL1RX) >> 12; | |
139 | if (v == reg) { | |
140 | v = readl(aaci->base + AACI_SL2RX) >> 4; | |
141 | } else { | |
142 | dev_err(&aaci->dev->dev, | |
143 | "wrong ac97 register read back (%x != %x)\n", | |
144 | v, reg); | |
145 | v = ~0; | |
146 | } | |
147 | ||
148 | up(&aaci->ac97_sem); | |
149 | return v; | |
150 | } | |
151 | ||
152 | static inline void aaci_chan_wait_ready(struct aaci_runtime *aacirun) | |
153 | { | |
154 | u32 val; | |
155 | int timeout = 5000; | |
156 | ||
157 | do { | |
158 | val = readl(aacirun->base + AACI_SR); | |
159 | } while (val & (SR_TXB|SR_RXB) && timeout--); | |
160 | } | |
161 | ||
162 | ||
163 | ||
164 | /* | |
165 | * Interrupt support. | |
166 | */ | |
167 | static void aaci_fifo_irq(struct aaci *aaci, u32 mask) | |
168 | { | |
169 | if (mask & ISR_URINTR) { | |
170 | writel(ICLR_TXUEC1, aaci->base + AACI_INTCLR); | |
171 | } | |
172 | ||
173 | if (mask & ISR_TXINTR) { | |
174 | struct aaci_runtime *aacirun = &aaci->playback; | |
175 | void *ptr; | |
176 | ||
177 | if (!aacirun->substream || !aacirun->start) { | |
178 | dev_warn(&aaci->dev->dev, "TX interrupt???"); | |
179 | writel(0, aacirun->base + AACI_IE); | |
180 | return; | |
181 | } | |
182 | ||
183 | ptr = aacirun->ptr; | |
184 | do { | |
185 | unsigned int len = aacirun->fifosz; | |
186 | u32 val; | |
187 | ||
188 | if (aacirun->bytes <= 0) { | |
189 | aacirun->bytes += aacirun->period; | |
190 | aacirun->ptr = ptr; | |
191 | spin_unlock(&aaci->lock); | |
192 | snd_pcm_period_elapsed(aacirun->substream); | |
193 | spin_lock(&aaci->lock); | |
194 | } | |
195 | if (!(aacirun->cr & TXCR_TXEN)) | |
196 | break; | |
197 | ||
198 | val = readl(aacirun->base + AACI_SR); | |
199 | if (!(val & SR_TXHE)) | |
200 | break; | |
201 | if (!(val & SR_TXFE)) | |
202 | len >>= 1; | |
203 | ||
204 | aacirun->bytes -= len; | |
205 | ||
206 | /* writing 16 bytes at a time */ | |
207 | for ( ; len > 0; len -= 16) { | |
208 | asm( | |
209 | "ldmia %0!, {r0, r1, r2, r3}\n\t" | |
210 | "stmia %1, {r0, r1, r2, r3}" | |
211 | : "+r" (ptr) | |
212 | : "r" (aacirun->fifo) | |
213 | : "r0", "r1", "r2", "r3", "cc"); | |
214 | ||
215 | if (ptr >= aacirun->end) | |
216 | ptr = aacirun->start; | |
217 | } | |
218 | } while (1); | |
219 | ||
220 | aacirun->ptr = ptr; | |
221 | } | |
222 | } | |
223 | ||
224 | static irqreturn_t aaci_irq(int irq, void *devid, struct pt_regs *regs) | |
225 | { | |
226 | struct aaci *aaci = devid; | |
227 | u32 mask; | |
228 | int i; | |
229 | ||
230 | spin_lock(&aaci->lock); | |
231 | mask = readl(aaci->base + AACI_ALLINTS); | |
232 | if (mask) { | |
233 | u32 m = mask; | |
234 | for (i = 0; i < 4; i++, m >>= 7) { | |
235 | if (m & 0x7f) { | |
236 | aaci_fifo_irq(aaci, m); | |
237 | } | |
238 | } | |
239 | } | |
240 | spin_unlock(&aaci->lock); | |
241 | ||
242 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
243 | } | |
244 | ||
245 | ||
246 | ||
247 | /* | |
248 | * ALSA support. | |
249 | */ | |
250 | ||
251 | struct aaci_stream { | |
252 | unsigned char codec_idx; | |
253 | unsigned char rate_idx; | |
254 | }; | |
255 | ||
256 | static struct aaci_stream aaci_streams[] = { | |
257 | [ACSTREAM_FRONT] = { | |
258 | .codec_idx = 0, | |
259 | .rate_idx = AC97_RATES_FRONT_DAC, | |
260 | }, | |
261 | [ACSTREAM_SURROUND] = { | |
262 | .codec_idx = 0, | |
263 | .rate_idx = AC97_RATES_SURR_DAC, | |
264 | }, | |
265 | [ACSTREAM_LFE] = { | |
266 | .codec_idx = 0, | |
267 | .rate_idx = AC97_RATES_LFE_DAC, | |
268 | }, | |
269 | }; | |
270 | ||
271 | static inline unsigned int aaci_rate_mask(struct aaci *aaci, int streamid) | |
272 | { | |
273 | struct aaci_stream *s = aaci_streams + streamid; | |
274 | return aaci->ac97_bus->codec[s->codec_idx]->rates[s->rate_idx]; | |
275 | } | |
276 | ||
277 | static unsigned int rate_list[] = { | |
278 | 5512, 8000, 11025, 16000, 22050, 32000, 44100, | |
279 | 48000, 64000, 88200, 96000, 176400, 192000 | |
280 | }; | |
281 | ||
282 | /* | |
283 | * Double-rate rule: we can support double rate iff channels == 2 | |
284 | * (unimplemented) | |
285 | */ | |
286 | static int | |
ceb9e476 | 287 | aaci_rule_rate_by_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule) |
cb5a6ffc RK |
288 | { |
289 | struct aaci *aaci = rule->private; | |
290 | unsigned int rate_mask = SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_5512; | |
ceb9e476 | 291 | struct snd_interval *c = hw_param_interval(p, SNDRV_PCM_HW_PARAM_CHANNELS); |
cb5a6ffc RK |
292 | |
293 | switch (c->max) { | |
294 | case 6: | |
295 | rate_mask &= aaci_rate_mask(aaci, ACSTREAM_LFE); | |
296 | case 4: | |
297 | rate_mask &= aaci_rate_mask(aaci, ACSTREAM_SURROUND); | |
298 | case 2: | |
299 | rate_mask &= aaci_rate_mask(aaci, ACSTREAM_FRONT); | |
300 | } | |
301 | ||
302 | return snd_interval_list(hw_param_interval(p, rule->var), | |
303 | ARRAY_SIZE(rate_list), rate_list, | |
304 | rate_mask); | |
305 | } | |
306 | ||
ceb9e476 | 307 | static struct snd_pcm_hardware aaci_hw_info = { |
cb5a6ffc RK |
308 | .info = SNDRV_PCM_INFO_MMAP | |
309 | SNDRV_PCM_INFO_MMAP_VALID | | |
310 | SNDRV_PCM_INFO_INTERLEAVED | | |
311 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
312 | SNDRV_PCM_INFO_RESUME, | |
313 | ||
314 | /* | |
315 | * ALSA doesn't support 18-bit or 20-bit packed into 32-bit | |
316 | * words. It also doesn't support 12-bit at all. | |
317 | */ | |
318 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
319 | ||
320 | /* should this be continuous or knot? */ | |
321 | .rates = SNDRV_PCM_RATE_CONTINUOUS, | |
322 | .rate_max = 48000, | |
323 | .rate_min = 4000, | |
324 | .channels_min = 2, | |
325 | .channels_max = 6, | |
326 | .buffer_bytes_max = 64 * 1024, | |
327 | .period_bytes_min = 256, | |
328 | .period_bytes_max = PAGE_SIZE, | |
329 | .periods_min = 4, | |
330 | .periods_max = PAGE_SIZE / 16, | |
331 | }; | |
332 | ||
ceb9e476 | 333 | static int aaci_pcm_open(struct aaci *aaci, struct snd_pcm_substream *substream, |
cb5a6ffc RK |
334 | struct aaci_runtime *aacirun) |
335 | { | |
ceb9e476 | 336 | struct snd_pcm_runtime *runtime = substream->runtime; |
cb5a6ffc RK |
337 | int ret; |
338 | ||
339 | aacirun->substream = substream; | |
340 | runtime->private_data = aacirun; | |
341 | runtime->hw = aaci_hw_info; | |
342 | ||
343 | /* | |
344 | * FIXME: ALSA specifies fifo_size in bytes. If we're in normal | |
345 | * mode, each 32-bit word contains one sample. If we're in | |
346 | * compact mode, each 32-bit word contains two samples, effectively | |
347 | * halving the FIFO size. However, we don't know for sure which | |
348 | * we'll be using at this point. We set this to the lower limit. | |
349 | */ | |
350 | runtime->hw.fifo_size = aaci->fifosize * 2; | |
351 | ||
352 | /* | |
353 | * Add rule describing hardware rate dependency | |
354 | * on the number of channels. | |
355 | */ | |
356 | ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
357 | aaci_rule_rate_by_channels, aaci, | |
358 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
359 | SNDRV_PCM_HW_PARAM_RATE, -1); | |
360 | if (ret) | |
361 | goto out; | |
362 | ||
363 | ret = request_irq(aaci->dev->irq[0], aaci_irq, SA_SHIRQ|SA_INTERRUPT, | |
364 | DRIVER_NAME, aaci); | |
365 | if (ret) | |
366 | goto out; | |
367 | ||
368 | return 0; | |
369 | ||
370 | out: | |
371 | return ret; | |
372 | } | |
373 | ||
374 | ||
375 | /* | |
376 | * Common ALSA stuff | |
377 | */ | |
ceb9e476 | 378 | static int aaci_pcm_close(struct snd_pcm_substream *substream) |
cb5a6ffc RK |
379 | { |
380 | struct aaci *aaci = substream->private_data; | |
381 | struct aaci_runtime *aacirun = substream->runtime->private_data; | |
382 | ||
383 | WARN_ON(aacirun->cr & TXCR_TXEN); | |
384 | ||
385 | aacirun->substream = NULL; | |
386 | free_irq(aaci->dev->irq[0], aaci); | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
ceb9e476 | 391 | static int aaci_pcm_hw_free(struct snd_pcm_substream *substream) |
cb5a6ffc RK |
392 | { |
393 | struct aaci_runtime *aacirun = substream->runtime->private_data; | |
394 | ||
395 | /* | |
396 | * This must not be called with the device enabled. | |
397 | */ | |
398 | WARN_ON(aacirun->cr & TXCR_TXEN); | |
399 | ||
400 | if (aacirun->pcm_open) | |
401 | snd_ac97_pcm_close(aacirun->pcm); | |
402 | aacirun->pcm_open = 0; | |
403 | ||
404 | /* | |
405 | * Clear out the DMA and any allocated buffers. | |
406 | */ | |
407 | devdma_hw_free(NULL, substream); | |
408 | ||
409 | return 0; | |
410 | } | |
411 | ||
ceb9e476 | 412 | static int aaci_pcm_hw_params(struct snd_pcm_substream *substream, |
cb5a6ffc | 413 | struct aaci_runtime *aacirun, |
ceb9e476 | 414 | struct snd_pcm_hw_params *params) |
cb5a6ffc RK |
415 | { |
416 | int err; | |
417 | ||
418 | aaci_pcm_hw_free(substream); | |
419 | ||
420 | err = devdma_hw_alloc(NULL, substream, | |
421 | params_buffer_bytes(params)); | |
422 | if (err < 0) | |
423 | goto out; | |
424 | ||
425 | err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params), | |
426 | params_channels(params), | |
427 | aacirun->pcm->r[0].slots); | |
428 | if (err) | |
429 | goto out; | |
430 | ||
431 | aacirun->pcm_open = 1; | |
432 | ||
433 | out: | |
434 | return err; | |
435 | } | |
436 | ||
ceb9e476 | 437 | static int aaci_pcm_prepare(struct snd_pcm_substream *substream) |
cb5a6ffc | 438 | { |
ceb9e476 | 439 | struct snd_pcm_runtime *runtime = substream->runtime; |
cb5a6ffc RK |
440 | struct aaci_runtime *aacirun = runtime->private_data; |
441 | ||
442 | aacirun->start = (void *)runtime->dma_area; | |
443 | aacirun->end = aacirun->start + runtime->dma_bytes; | |
444 | aacirun->ptr = aacirun->start; | |
445 | aacirun->period = | |
446 | aacirun->bytes = frames_to_bytes(runtime, runtime->period_size); | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
ceb9e476 | 451 | static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream) |
cb5a6ffc | 452 | { |
ceb9e476 | 453 | struct snd_pcm_runtime *runtime = substream->runtime; |
cb5a6ffc RK |
454 | struct aaci_runtime *aacirun = runtime->private_data; |
455 | ssize_t bytes = aacirun->ptr - aacirun->start; | |
456 | ||
457 | return bytes_to_frames(runtime, bytes); | |
458 | } | |
459 | ||
ceb9e476 | 460 | static int aaci_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma) |
cb5a6ffc RK |
461 | { |
462 | return devdma_mmap(NULL, substream, vma); | |
463 | } | |
464 | ||
465 | ||
466 | /* | |
467 | * Playback specific ALSA stuff | |
468 | */ | |
469 | static const u32 channels_to_txmask[] = { | |
470 | [2] = TXCR_TX3 | TXCR_TX4, | |
471 | [4] = TXCR_TX3 | TXCR_TX4 | TXCR_TX7 | TXCR_TX8, | |
472 | [6] = TXCR_TX3 | TXCR_TX4 | TXCR_TX7 | TXCR_TX8 | TXCR_TX6 | TXCR_TX9, | |
473 | }; | |
474 | ||
475 | /* | |
476 | * We can support two and four channel audio. Unfortunately | |
477 | * six channel audio requires a non-standard channel ordering: | |
478 | * 2 -> FL(3), FR(4) | |
479 | * 4 -> FL(3), FR(4), SL(7), SR(8) | |
480 | * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required) | |
481 | * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual) | |
482 | * This requires an ALSA configuration file to correct. | |
483 | */ | |
484 | static unsigned int channel_list[] = { 2, 4, 6 }; | |
485 | ||
486 | static int | |
ceb9e476 | 487 | aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule) |
cb5a6ffc RK |
488 | { |
489 | struct aaci *aaci = rule->private; | |
490 | unsigned int chan_mask = 1 << 0, slots; | |
491 | ||
492 | /* | |
493 | * pcms[0] is the our 5.1 PCM instance. | |
494 | */ | |
495 | slots = aaci->ac97_bus->pcms[0].r[0].slots; | |
496 | if (slots & (1 << AC97_SLOT_PCM_SLEFT)) { | |
497 | chan_mask |= 1 << 1; | |
498 | if (slots & (1 << AC97_SLOT_LFE)) | |
499 | chan_mask |= 1 << 2; | |
500 | } | |
501 | ||
502 | return snd_interval_list(hw_param_interval(p, rule->var), | |
503 | ARRAY_SIZE(channel_list), channel_list, | |
504 | chan_mask); | |
505 | } | |
506 | ||
ceb9e476 | 507 | static int aaci_pcm_playback_open(struct snd_pcm_substream *substream) |
cb5a6ffc RK |
508 | { |
509 | struct aaci *aaci = substream->private_data; | |
510 | int ret; | |
511 | ||
512 | /* | |
513 | * Add rule describing channel dependency. | |
514 | */ | |
515 | ret = snd_pcm_hw_rule_add(substream->runtime, 0, | |
516 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
517 | aaci_rule_channels, aaci, | |
518 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
519 | if (ret) | |
520 | return ret; | |
521 | ||
522 | return aaci_pcm_open(aaci, substream, &aaci->playback); | |
523 | } | |
524 | ||
ceb9e476 TI |
525 | static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream, |
526 | struct snd_pcm_hw_params *params) | |
cb5a6ffc RK |
527 | { |
528 | struct aaci *aaci = substream->private_data; | |
529 | struct aaci_runtime *aacirun = substream->runtime->private_data; | |
530 | unsigned int channels = params_channels(params); | |
531 | int ret; | |
532 | ||
533 | WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) || | |
534 | !channels_to_txmask[channels]); | |
535 | ||
536 | ret = aaci_pcm_hw_params(substream, aacirun, params); | |
537 | ||
538 | /* | |
539 | * Enable FIFO, compact mode, 16 bits per sample. | |
540 | * FIXME: double rate slots? | |
541 | */ | |
542 | if (ret >= 0) { | |
543 | aacirun->cr = TXCR_FEN | TXCR_COMPACT | TXCR_TSZ16; | |
544 | aacirun->cr |= channels_to_txmask[channels]; | |
545 | ||
546 | aacirun->fifosz = aaci->fifosize * 4; | |
547 | if (aacirun->cr & TXCR_COMPACT) | |
548 | aacirun->fifosz >>= 1; | |
549 | } | |
550 | return ret; | |
551 | } | |
552 | ||
553 | static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun) | |
554 | { | |
555 | u32 ie; | |
556 | ||
557 | ie = readl(aacirun->base + AACI_IE); | |
558 | ie &= ~(IE_URIE|IE_TXIE); | |
559 | writel(ie, aacirun->base + AACI_IE); | |
560 | aacirun->cr &= ~TXCR_TXEN; | |
561 | aaci_chan_wait_ready(aacirun); | |
562 | writel(aacirun->cr, aacirun->base + AACI_TXCR); | |
563 | } | |
564 | ||
565 | static void aaci_pcm_playback_start(struct aaci_runtime *aacirun) | |
566 | { | |
567 | u32 ie; | |
568 | ||
569 | aaci_chan_wait_ready(aacirun); | |
570 | aacirun->cr |= TXCR_TXEN; | |
571 | ||
572 | ie = readl(aacirun->base + AACI_IE); | |
573 | ie |= IE_URIE | IE_TXIE; | |
574 | writel(ie, aacirun->base + AACI_IE); | |
575 | writel(aacirun->cr, aacirun->base + AACI_TXCR); | |
576 | } | |
577 | ||
ceb9e476 | 578 | static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd) |
cb5a6ffc RK |
579 | { |
580 | struct aaci *aaci = substream->private_data; | |
581 | struct aaci_runtime *aacirun = substream->runtime->private_data; | |
582 | unsigned long flags; | |
583 | int ret = 0; | |
584 | ||
585 | spin_lock_irqsave(&aaci->lock, flags); | |
586 | switch (cmd) { | |
587 | case SNDRV_PCM_TRIGGER_START: | |
588 | aaci_pcm_playback_start(aacirun); | |
589 | break; | |
590 | ||
591 | case SNDRV_PCM_TRIGGER_RESUME: | |
592 | aaci_pcm_playback_start(aacirun); | |
593 | break; | |
594 | ||
595 | case SNDRV_PCM_TRIGGER_STOP: | |
596 | aaci_pcm_playback_stop(aacirun); | |
597 | break; | |
598 | ||
599 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
600 | aaci_pcm_playback_stop(aacirun); | |
601 | break; | |
602 | ||
603 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
604 | break; | |
605 | ||
606 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
607 | break; | |
608 | ||
609 | default: | |
610 | ret = -EINVAL; | |
611 | } | |
612 | spin_unlock_irqrestore(&aaci->lock, flags); | |
613 | ||
614 | return ret; | |
615 | } | |
616 | ||
ceb9e476 | 617 | static struct snd_pcm_ops aaci_playback_ops = { |
cb5a6ffc RK |
618 | .open = aaci_pcm_playback_open, |
619 | .close = aaci_pcm_close, | |
620 | .ioctl = snd_pcm_lib_ioctl, | |
621 | .hw_params = aaci_pcm_playback_hw_params, | |
622 | .hw_free = aaci_pcm_hw_free, | |
623 | .prepare = aaci_pcm_prepare, | |
624 | .trigger = aaci_pcm_playback_trigger, | |
625 | .pointer = aaci_pcm_pointer, | |
626 | .mmap = aaci_pcm_mmap, | |
627 | }; | |
628 | ||
629 | ||
630 | ||
631 | /* | |
632 | * Power Management. | |
633 | */ | |
634 | #ifdef CONFIG_PM | |
ceb9e476 | 635 | static int aaci_do_suspend(struct snd_card *card, unsigned int state) |
cb5a6ffc RK |
636 | { |
637 | struct aaci *aaci = card->private_data; | |
792a6c51 TI |
638 | snd_power_change_state(card, SNDRV_CTL_POWER_D3cold); |
639 | snd_pcm_suspend_all(aaci->pcm); | |
cb5a6ffc RK |
640 | return 0; |
641 | } | |
642 | ||
ceb9e476 | 643 | static int aaci_do_resume(struct snd_card *card, unsigned int state) |
cb5a6ffc | 644 | { |
792a6c51 | 645 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
cb5a6ffc RK |
646 | return 0; |
647 | } | |
648 | ||
e36d394d | 649 | static int aaci_suspend(struct amba_device *dev, pm_message_t state) |
cb5a6ffc | 650 | { |
ceb9e476 | 651 | struct snd_card *card = amba_get_drvdata(dev); |
cb5a6ffc RK |
652 | return card ? aaci_do_suspend(card) : 0; |
653 | } | |
654 | ||
655 | static int aaci_resume(struct amba_device *dev) | |
656 | { | |
ceb9e476 | 657 | struct snd_card *card = amba_get_drvdata(dev); |
cb5a6ffc RK |
658 | return card ? aaci_do_resume(card) : 0; |
659 | } | |
660 | #else | |
661 | #define aaci_do_suspend NULL | |
662 | #define aaci_do_resume NULL | |
663 | #define aaci_suspend NULL | |
664 | #define aaci_resume NULL | |
665 | #endif | |
666 | ||
667 | ||
668 | static struct ac97_pcm ac97_defs[] __devinitdata = { | |
669 | [0] = { /* Front PCM */ | |
670 | .exclusive = 1, | |
671 | .r = { | |
672 | [0] = { | |
673 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
674 | (1 << AC97_SLOT_PCM_RIGHT) | | |
675 | (1 << AC97_SLOT_PCM_CENTER) | | |
676 | (1 << AC97_SLOT_PCM_SLEFT) | | |
677 | (1 << AC97_SLOT_PCM_SRIGHT) | | |
678 | (1 << AC97_SLOT_LFE), | |
679 | }, | |
680 | }, | |
681 | }, | |
682 | [1] = { /* PCM in */ | |
683 | .stream = 1, | |
684 | .exclusive = 1, | |
685 | .r = { | |
686 | [0] = { | |
687 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
688 | (1 << AC97_SLOT_PCM_RIGHT), | |
689 | }, | |
690 | }, | |
691 | }, | |
692 | [2] = { /* Mic in */ | |
693 | .stream = 1, | |
694 | .exclusive = 1, | |
695 | .r = { | |
696 | [0] = { | |
697 | .slots = (1 << AC97_SLOT_MIC), | |
698 | }, | |
699 | }, | |
700 | } | |
701 | }; | |
702 | ||
ceb9e476 | 703 | static struct snd_ac97_bus_ops aaci_bus_ops = { |
cb5a6ffc RK |
704 | .write = aaci_ac97_write, |
705 | .read = aaci_ac97_read, | |
706 | }; | |
707 | ||
708 | static int __devinit aaci_probe_ac97(struct aaci *aaci) | |
709 | { | |
ceb9e476 TI |
710 | struct snd_ac97_template ac97_template; |
711 | struct snd_ac97_bus *ac97_bus; | |
712 | struct snd_ac97 *ac97; | |
cb5a6ffc RK |
713 | int ret; |
714 | ||
715 | /* | |
716 | * Assert AACIRESET for 2us | |
717 | */ | |
718 | writel(0, aaci->base + AACI_RESET); | |
719 | udelay(2); | |
720 | writel(RESET_NRST, aaci->base + AACI_RESET); | |
721 | ||
722 | /* | |
723 | * Give the AC'97 codec more than enough time | |
724 | * to wake up. (42us = ~2 frames at 48kHz.) | |
725 | */ | |
726 | udelay(42); | |
727 | ||
728 | ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus); | |
729 | if (ret) | |
730 | goto out; | |
731 | ||
732 | ac97_bus->clock = 48000; | |
733 | aaci->ac97_bus = ac97_bus; | |
734 | ||
ceb9e476 | 735 | memset(&ac97_template, 0, sizeof(struct snd_ac97_template)); |
cb5a6ffc RK |
736 | ac97_template.private_data = aaci; |
737 | ac97_template.num = 0; | |
738 | ac97_template.scaps = AC97_SCAP_SKIP_MODEM; | |
739 | ||
740 | ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97); | |
741 | if (ret) | |
742 | goto out; | |
743 | ||
744 | /* | |
745 | * Disable AC97 PC Beep input on audio codecs. | |
746 | */ | |
747 | if (ac97_is_audio(ac97)) | |
748 | snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e); | |
749 | ||
750 | ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs); | |
751 | if (ret) | |
752 | goto out; | |
753 | ||
754 | aaci->playback.pcm = &ac97_bus->pcms[0]; | |
755 | ||
756 | out: | |
757 | return ret; | |
758 | } | |
759 | ||
ceb9e476 | 760 | static void aaci_free_card(struct snd_card *card) |
cb5a6ffc RK |
761 | { |
762 | struct aaci *aaci = card->private_data; | |
763 | if (aaci->base) | |
764 | iounmap(aaci->base); | |
765 | } | |
766 | ||
767 | static struct aaci * __devinit aaci_init_card(struct amba_device *dev) | |
768 | { | |
769 | struct aaci *aaci; | |
ceb9e476 | 770 | struct snd_card *card; |
cb5a6ffc RK |
771 | |
772 | card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, | |
773 | THIS_MODULE, sizeof(struct aaci)); | |
774 | if (card == NULL) | |
775 | return ERR_PTR(-ENOMEM); | |
776 | ||
777 | card->private_free = aaci_free_card; | |
cb5a6ffc RK |
778 | |
779 | strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver)); | |
780 | strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname)); | |
781 | snprintf(card->longname, sizeof(card->longname), | |
782 | "%s at 0x%08lx, irq %d", | |
783 | card->shortname, dev->res.start, dev->irq[0]); | |
784 | ||
785 | aaci = card->private_data; | |
786 | init_MUTEX(&aaci->ac97_sem); | |
787 | spin_lock_init(&aaci->lock); | |
788 | aaci->card = card; | |
789 | aaci->dev = dev; | |
790 | ||
791 | /* Set MAINCR to allow slot 1 and 2 data IO */ | |
792 | aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN | | |
793 | MAINCR_SL2RXEN | MAINCR_SL2TXEN; | |
794 | ||
795 | return aaci; | |
796 | } | |
797 | ||
798 | static int __devinit aaci_init_pcm(struct aaci *aaci) | |
799 | { | |
ceb9e476 | 800 | struct snd_pcm *pcm; |
cb5a6ffc RK |
801 | int ret; |
802 | ||
803 | ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 0, &pcm); | |
804 | if (ret == 0) { | |
805 | aaci->pcm = pcm; | |
806 | pcm->private_data = aaci; | |
807 | pcm->info_flags = 0; | |
808 | ||
809 | strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name)); | |
810 | ||
811 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops); | |
812 | } | |
813 | ||
814 | return ret; | |
815 | } | |
816 | ||
817 | static unsigned int __devinit aaci_size_fifo(struct aaci *aaci) | |
818 | { | |
e12ba644 | 819 | void __iomem *base = aaci->base + AACI_CSCH1; |
cb5a6ffc RK |
820 | int i; |
821 | ||
822 | writel(TXCR_FEN | TXCR_TSZ16 | TXCR_TXEN, base + AACI_TXCR); | |
823 | ||
824 | for (i = 0; !(readl(base + AACI_SR) & SR_TXFF) && i < 4096; i++) | |
825 | writel(0, aaci->base + AACI_DR1); | |
826 | ||
827 | writel(0, base + AACI_TXCR); | |
828 | ||
829 | /* | |
830 | * Re-initialise the AACI after the FIFO depth test, to | |
831 | * ensure that the FIFOs are empty. Unfortunately, merely | |
832 | * disabling the channel doesn't clear the FIFO. | |
833 | */ | |
834 | writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR); | |
835 | writel(aaci->maincr, aaci->base + AACI_MAINCR); | |
836 | ||
837 | /* | |
838 | * If we hit 4096, we failed. Go back to the specified | |
839 | * fifo depth. | |
840 | */ | |
841 | if (i == 4096) | |
842 | i = 8; | |
843 | ||
844 | return i; | |
845 | } | |
846 | ||
847 | static int __devinit aaci_probe(struct amba_device *dev, void *id) | |
848 | { | |
849 | struct aaci *aaci; | |
850 | int ret, i; | |
851 | ||
852 | ret = amba_request_regions(dev, NULL); | |
853 | if (ret) | |
854 | return ret; | |
855 | ||
856 | aaci = aaci_init_card(dev); | |
857 | if (IS_ERR(aaci)) { | |
858 | ret = PTR_ERR(aaci); | |
859 | goto out; | |
860 | } | |
861 | ||
862 | aaci->base = ioremap(dev->res.start, SZ_4K); | |
863 | if (!aaci->base) { | |
864 | ret = -ENOMEM; | |
865 | goto out; | |
866 | } | |
867 | ||
868 | /* | |
869 | * Playback uses AACI channel 0 | |
870 | */ | |
871 | aaci->playback.base = aaci->base + AACI_CSCH1; | |
872 | aaci->playback.fifo = aaci->base + AACI_DR1; | |
873 | ||
874 | for (i = 0; i < 4; i++) { | |
e12ba644 | 875 | void __iomem *base = aaci->base + i * 0x14; |
cb5a6ffc RK |
876 | |
877 | writel(0, base + AACI_IE); | |
878 | writel(0, base + AACI_TXCR); | |
879 | writel(0, base + AACI_RXCR); | |
880 | } | |
881 | ||
882 | writel(0x1fff, aaci->base + AACI_INTCLR); | |
883 | writel(aaci->maincr, aaci->base + AACI_MAINCR); | |
884 | ||
f27f218c CM |
885 | ret = aaci_probe_ac97(aaci); |
886 | if (ret) | |
887 | goto out; | |
888 | ||
cb5a6ffc | 889 | /* |
f27f218c | 890 | * Size the FIFOs (must be multiple of 16). |
cb5a6ffc RK |
891 | */ |
892 | aaci->fifosize = aaci_size_fifo(aaci); | |
f27f218c CM |
893 | if (aaci->fifosize & 15) { |
894 | printk(KERN_WARNING "AACI: fifosize = %d not supported\n", | |
895 | aaci->fifosize); | |
896 | ret = -ENODEV; | |
cb5a6ffc | 897 | goto out; |
f27f218c | 898 | } |
cb5a6ffc RK |
899 | |
900 | ret = aaci_init_pcm(aaci); | |
901 | if (ret) | |
902 | goto out; | |
903 | ||
a76af199 TI |
904 | snd_card_set_dev(aaci->card, &dev->dev); |
905 | ||
cb5a6ffc RK |
906 | ret = snd_card_register(aaci->card); |
907 | if (ret == 0) { | |
908 | dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname, | |
909 | aaci->fifosize); | |
910 | amba_set_drvdata(dev, aaci->card); | |
911 | return ret; | |
912 | } | |
913 | ||
914 | out: | |
915 | if (aaci) | |
916 | snd_card_free(aaci->card); | |
917 | amba_release_regions(dev); | |
918 | return ret; | |
919 | } | |
920 | ||
921 | static int __devexit aaci_remove(struct amba_device *dev) | |
922 | { | |
ceb9e476 | 923 | struct snd_card *card = amba_get_drvdata(dev); |
cb5a6ffc RK |
924 | |
925 | amba_set_drvdata(dev, NULL); | |
926 | ||
927 | if (card) { | |
928 | struct aaci *aaci = card->private_data; | |
929 | writel(0, aaci->base + AACI_MAINCR); | |
930 | ||
931 | snd_card_free(card); | |
932 | amba_release_regions(dev); | |
933 | } | |
934 | ||
935 | return 0; | |
936 | } | |
937 | ||
938 | static struct amba_id aaci_ids[] = { | |
939 | { | |
940 | .id = 0x00041041, | |
941 | .mask = 0x000fffff, | |
942 | }, | |
943 | { 0, 0 }, | |
944 | }; | |
945 | ||
946 | static struct amba_driver aaci_driver = { | |
947 | .drv = { | |
948 | .name = DRIVER_NAME, | |
949 | }, | |
950 | .probe = aaci_probe, | |
951 | .remove = __devexit_p(aaci_remove), | |
952 | .suspend = aaci_suspend, | |
953 | .resume = aaci_resume, | |
954 | .id_table = aaci_ids, | |
955 | }; | |
956 | ||
957 | static int __init aaci_init(void) | |
958 | { | |
959 | return amba_driver_register(&aaci_driver); | |
960 | } | |
961 | ||
962 | static void __exit aaci_exit(void) | |
963 | { | |
964 | amba_driver_unregister(&aaci_driver); | |
965 | } | |
966 | ||
967 | module_init(aaci_init); | |
968 | module_exit(aaci_exit); | |
969 | ||
970 | MODULE_LICENSE("GPL"); | |
971 | MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver"); |