[mirror_ubuntu-bionic-kernel.git] / sound / arm / pxa2xx-ac97-lib.c

/*
 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
 * which contain:
 *
 * Author:	Nicolas Pitre
 * Created:	Dec 02, 2004
 * Copyright:	MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/delay.h>

#include <sound/ac97_codec.h>
#include <sound/pxa2xx-lib.h>

#include <asm/irq.h>
#include <mach/hardware.h>
#include <mach/regs-ac97.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/audio.h>

static DEFINE_MUTEX(car_mutex);
static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
static volatile long gsr_bits;
static struct clk *ac97_clk;
static struct clk *ac97conf_clk;
static int reset_gpio;

/*
 * Beware PXA27x bugs:
 *
 *   o Slot 12 read from modem space will hang controller.
 *   o CDONE, SDONE interrupt fails after any slot 12 IO.
 *
 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
 * 1 jiffy timeout if interrupt never comes).
 */

enum {
	RESETGPIO_FORCE_HIGH,
	RESETGPIO_FORCE_LOW,
	RESETGPIO_NORMAL_ALTFUNC
};

/**
 * set_resetgpio_mode - computes and sets the AC97_RESET gpio mode on PXA
 * @mode: chosen action
 *
 * As the PXA27x CPUs suffer from a AC97 bug, a manual control of the reset line
 * must be done to insure proper work of AC97 reset line.  This function
 * computes the correct gpio_mode for further use by reset functions, and
 * applied the change through pxa_gpio_mode.
 */
static void set_resetgpio_mode(int resetgpio_action)
{
	int mode = 0;

	if (reset_gpio)
		switch (resetgpio_action) {
		case RESETGPIO_NORMAL_ALTFUNC:
			if (reset_gpio == 113)
				mode = 113 | GPIO_OUT | GPIO_DFLT_LOW;
			if (reset_gpio == 95)
				mode = 95 | GPIO_ALT_FN_1_OUT;
			break;
		case RESETGPIO_FORCE_LOW:
			mode = reset_gpio | GPIO_OUT | GPIO_DFLT_LOW;
			break;
		case RESETGPIO_FORCE_HIGH:
			mode = reset_gpio | GPIO_OUT | GPIO_DFLT_HIGH;
			break;
		};

	if (mode)
		pxa_gpio_mode(mode);
}

unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
{
	unsigned short val = -1;
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
		reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	else
		reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	/* start read access across the ac97 link */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;
	if (reg == AC97_GPIO_STATUS)
		goto out;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_SDONE)) {
		printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);
		val = -1;
		goto out;
	}

	/* valid data now */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;
	/* but we've just started another cycle... */
	wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);

out:	mutex_unlock(&car_mutex);
	return val;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);

void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
			unsigned short val)
{
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
		reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	else
		reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	*reg_addr = val;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_CDONE))
		printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);

	mutex_unlock(&car_mutex);
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);

#ifdef CONFIG_PXA25x
static inline void pxa_ac97_warm_pxa25x(void)
{
	gsr_bits = 0;

	GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
}

static inline void pxa_ac97_cold_pxa25x(void)
{
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	GCR = GCR_COLD_RST;
	GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
}
#endif

#ifdef CONFIG_PXA27x
static inline void pxa_ac97_warm_pxa27x(void)
{
	gsr_bits = 0;

	/* warm reset broken on Bulverde,
	   so manually keep AC97 reset high */
	set_resetgpio_mode(RESETGPIO_FORCE_HIGH);
	udelay(10);
	GCR |= GCR_WARM_RST;
	set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
	udelay(500);
}

static inline void pxa_ac97_cold_pxa27x(void)
{
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	/* PXA27x Developers Manual section 13.5.2.2.1 */
	clk_enable(ac97conf_clk);
	udelay(5);
	clk_disable(ac97conf_clk);
	GCR = GCR_COLD_RST;
	udelay(50);
}
#endif

#ifdef CONFIG_PXA3xx
static inline void pxa_ac97_warm_pxa3xx(void)
{
	int timeout = 100;

	gsr_bits = 0;

	/* Can't use interrupts */
	GCR |= GCR_WARM_RST;
	while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(1);
}

static inline void pxa_ac97_cold_pxa3xx(void)
{
	int timeout = 1000;

	/* Hold CLKBPB for 100us */
	GCR = 0;
	GCR = GCR_CLKBPB;
	udelay(100);
	GCR = 0;

	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	/* Can't use interrupts on PXA3xx */
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);

	GCR = GCR_WARM_RST | GCR_COLD_RST;
	while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(10);
}
#endif

bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
{
#ifdef CONFIG_PXA25x
	if (cpu_is_pxa25x())
		pxa_ac97_warm_pxa25x();
	else
#endif
#ifdef CONFIG_PXA27x
	if (cpu_is_pxa27x())
		pxa_ac97_warm_pxa27x();
	else
#endif
#ifdef CONFIG_PXA3xx
	if (cpu_is_pxa3xx())
		pxa_ac97_warm_pxa3xx();
	else
#endif
		BUG();

	if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
				 __func__, gsr_bits);

		return false;
	}

	return true;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);

bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
{
#ifdef CONFIG_PXA25x
	if (cpu_is_pxa25x())
		pxa_ac97_cold_pxa25x();
	else
#endif
#ifdef CONFIG_PXA27x
	if (cpu_is_pxa27x())
		pxa_ac97_cold_pxa27x();
	else
#endif
#ifdef CONFIG_PXA3xx
	if (cpu_is_pxa3xx())
		pxa_ac97_cold_pxa3xx();
	else
#endif
		BUG();

	if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
				 __func__, gsr_bits);

		return false;
	}

	return true;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);


void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
{
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
	GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);

static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
{
	long status;

	status = GSR;
	if (status) {
		GSR = status;
		gsr_bits |= status;
		wake_up(&gsr_wq);

		/* Although we don't use those we still need to clear them
		   since they tend to spuriously trigger when MMC is used
		   (hardware bug? go figure)... */
		if (cpu_is_pxa27x()) {
			MISR = MISR_EOC;
			PISR = PISR_EOC;
			MCSR = MCSR_EOC;
		}

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

#ifdef CONFIG_PM
int pxa2xx_ac97_hw_suspend(void)
{
	GCR |= GCR_ACLINK_OFF;
	clk_disable(ac97_clk);
	return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);

int pxa2xx_ac97_hw_resume(void)
{
	if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
		pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
		pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
		pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
		pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
	}
	if (cpu_is_pxa27x()) {
		/* Use GPIO 113 or 95 as AC97 Reset on Bulverde */
		set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
	}
	clk_enable(ac97_clk);
	return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
#endif

int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
{
	int ret;
	struct pxa2xx_ac97_platform_data *pdata = dev->dev.platform_data;

	if (pdata) {
		switch (pdata->reset_gpio) {
		case 95:
		case 113:
			reset_gpio = pdata->reset_gpio;
			break;
		case 0:
			reset_gpio = 113;
			break;
		case -1:
			break;
		default:
			dev_err(dev, "Invalid reset GPIO %d\n",
				pdata->reset_gpio);
		}
	} else {
		if (cpu_is_pxa27x())
			reset_gpio = 113;
	}

	if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
		pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
		pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
		pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
		pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
	}

	if (cpu_is_pxa27x()) {
		/* Use GPIO 113 as AC97 Reset on Bulverde */
		set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
		ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
		if (IS_ERR(ac97conf_clk)) {
			ret = PTR_ERR(ac97conf_clk);
			ac97conf_clk = NULL;
			goto err_conf;
		}
	}

	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	if (IS_ERR(ac97_clk)) {
		ret = PTR_ERR(ac97_clk);
		ac97_clk = NULL;
		goto err_clk;
	}

	ret = clk_enable(ac97_clk);
	if (ret)
		goto err_clk2;

	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
	if (ret < 0)
		goto err_irq;

	return 0;

err_irq:
	GCR |= GCR_ACLINK_OFF;
err_clk2:
	clk_put(ac97_clk);
	ac97_clk = NULL;
err_clk:
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
err_conf:
	return ret;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);

void pxa2xx_ac97_hw_remove(struct platform_device *dev)
{
	GCR |= GCR_ACLINK_OFF;
	free_irq(IRQ_AC97, NULL);
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
	clk_disable(ac97_clk);
	clk_put(ac97_clk);
	ac97_clk = NULL;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);

MODULE_AUTHOR("Nicolas Pitre");
MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
MODULE_LICENSE("GPL");
Commit	Line	Data
9c636342 DES	1	/*
	2	* Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
	3	* which contain:
	4	*
	5	* Author: Nicolas Pitre
	6	* Created: Dec 02, 2004
	7	* Copyright: MontaVista Software Inc.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/clk.h>
	18	#include <linux/delay.h>
	19
	20	#include <sound/ac97_codec.h>
	21	#include <sound/pxa2xx-lib.h>
	22
	23	#include <asm/irq.h>
	24	#include <mach/hardware.h>
1f017a99	25	#include <mach/regs-ac97.h>
9c636342 DES	26	#include <mach/pxa2xx-gpio.h>
	27	#include <mach/audio.h>
	28
	29	static DEFINE_MUTEX(car_mutex);
	30	static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
	31	static volatile long gsr_bits;
	32	static struct clk *ac97_clk;
9c636342	33	static struct clk *ac97conf_clk;
26ade896	34	static int reset_gpio;
9c636342 DES	35
	36	/*
	37	* Beware PXA27x bugs:
	38	*
	39	* o Slot 12 read from modem space will hang controller.
	40	* o CDONE, SDONE interrupt fails after any slot 12 IO.
	41	*
	42	* We therefore have an hybrid approach for waiting on SDONE (interrupt or
	43	* 1 jiffy timeout if interrupt never comes).
	44	*/
	45
26ade896 RJ	46	enum {
	47	RESETGPIO_FORCE_HIGH,
	48	RESETGPIO_FORCE_LOW,
	49	RESETGPIO_NORMAL_ALTFUNC
	50	};
	51
	52	/**
	53	* set_resetgpio_mode - computes and sets the AC97_RESET gpio mode on PXA
	54	* @mode: chosen action
	55	*
	56	* As the PXA27x CPUs suffer from a AC97 bug, a manual control of the reset line
	57	* must be done to insure proper work of AC97 reset line. This function
	58	* computes the correct gpio_mode for further use by reset functions, and
	59	* applied the change through pxa_gpio_mode.
	60	*/
	61	static void set_resetgpio_mode(int resetgpio_action)
	62	{
	63	int mode = 0;
	64
	65	if (reset_gpio)
	66	switch (resetgpio_action) {
	67	case RESETGPIO_NORMAL_ALTFUNC:
	68	if (reset_gpio == 113)
	69	mode = 113 \| GPIO_OUT \| GPIO_DFLT_LOW;
	70	if (reset_gpio == 95)
	71	mode = 95 \| GPIO_ALT_FN_1_OUT;
	72	break;
	73	case RESETGPIO_FORCE_LOW:
	74	mode = reset_gpio \| GPIO_OUT \| GPIO_DFLT_LOW;
	75	break;
	76	case RESETGPIO_FORCE_HIGH:
	77	mode = reset_gpio \| GPIO_OUT \| GPIO_DFLT_HIGH;
	78	break;
	79	};
	80
	81	if (mode)
	82	pxa_gpio_mode(mode);
	83	}
	84
9c636342 DES	85	unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
	86	{
	87	unsigned short val = -1;
	88	volatile u32 *reg_addr;
	89
	90	mutex_lock(&car_mutex);
	91
	92	/* set up primary or secondary codec space */
8825e8e8	93	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
9c636342 DES	94	reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	95	else
	96	reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
9c636342 DES	97	reg_addr += (reg >> 1);
	98
	99	/* start read access across the ac97 link */
	100	GSR = GSR_CDONE \| GSR_SDONE;
	101	gsr_bits = 0;
	102	val = *reg_addr;
	103	if (reg == AC97_GPIO_STATUS)
	104	goto out;
	105	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1) <= 0 &&
	106	!((GSR \| gsr_bits) & GSR_SDONE)) {
	107	printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
	108	__func__, reg, GSR \| gsr_bits);
	109	val = -1;
	110	goto out;
	111	}
	112
	113	/* valid data now */
	114	GSR = GSR_CDONE \| GSR_SDONE;
	115	gsr_bits = 0;
	116	val = *reg_addr;
	117	/* but we've just started another cycle... */
	118	wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1);
	119
	120	out: mutex_unlock(&car_mutex);
	121	return val;
	122	}
	123	EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
	124
	125	void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
	126	unsigned short val)
	127	{
	128	volatile u32 *reg_addr;
	129
	130	mutex_lock(&car_mutex);
	131
	132	/* set up primary or secondary codec space */
8825e8e8	133	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
9c636342 DES	134	reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	135	else
	136	reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
9c636342 DES	137	reg_addr += (reg >> 1);
	138
	139	GSR = GSR_CDONE \| GSR_SDONE;
	140	gsr_bits = 0;
	141	*reg_addr = val;
	142	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_CDONE, 1) <= 0 &&
	143	!((GSR \| gsr_bits) & GSR_CDONE))
	144	printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
	145	__func__, reg, GSR \| gsr_bits);
	146
	147	mutex_unlock(&car_mutex);
	148	}
	149	EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
	150
9d1cf39b DES	151	#ifdef CONFIG_PXA25x
9d1cf39b DES	152	static inline void pxa_ac97_warm_pxa25x(void)
9c636342	153	{
9c636342 DES	154	gsr_bits = 0;
9c636342 DES	155
9d1cf39b DES	156	GCR \|= GCR_WARM_RST \| GCR_PRIRDY_IEN \| GCR_SECRDY_IEN;
	157	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR \| GSR_SCR), 1);
	158	}
	159
	160	static inline void pxa_ac97_cold_pxa25x(void)
	161	{
	162	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	163	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	164
	165	gsr_bits = 0;
	166
	167	GCR = GCR_COLD_RST;
	168	GCR \|= GCR_CDONE_IE\|GCR_SDONE_IE;
	169	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR \| GSR_SCR), 1);
	170	}
	171	#endif
	172
9c636342	173	#ifdef CONFIG_PXA27x
9d1cf39b DES	174	static inline void pxa_ac97_warm_pxa27x(void)
	175	{
	176	gsr_bits = 0;
	177
9c636342 DES	178	/* warm reset broken on Bulverde,
9c636342 DES	179	so manually keep AC97 reset high */
26ade896	180	set_resetgpio_mode(RESETGPIO_FORCE_HIGH);
9c636342 DES	181	udelay(10);
9c636342 DES	182	GCR \|= GCR_WARM_RST;
26ade896	183	set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
9c636342	184	udelay(500);
9d1cf39b DES	185	}
	186
	187	static inline void pxa_ac97_cold_pxa27x(void)
	188	{
	189	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	190	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	191
	192	gsr_bits = 0;
	193
	194	/* PXA27x Developers Manual section 13.5.2.2.1 */
	195	clk_enable(ac97conf_clk);
	196	udelay(5);
	197	clk_disable(ac97conf_clk);
	198	GCR = GCR_COLD_RST;
	199	udelay(50);
	200	}
9c636342 DES	201	#endif
9c636342 DES	202
9d1cf39b DES	203	#ifdef CONFIG_PXA3xx
	204	static inline void pxa_ac97_warm_pxa3xx(void)
	205	{
	206	int timeout = 100;
9c636342	207
9d1cf39b	208	gsr_bits = 0;
9c636342	209
9d1cf39b DES	210	/* Can't use interrupts */
	211	GCR \|= GCR_WARM_RST;
	212	while (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR)) && timeout--)
	213	mdelay(1);
9c636342	214	}
9c636342	215
9d1cf39b	216	static inline void pxa_ac97_cold_pxa3xx(void)
9c636342	217	{
9c636342 DES	218	int timeout = 1000;
	219
	220	/* Hold CLKBPB for 100us */
	221	GCR = 0;
	222	GCR = GCR_CLKBPB;
	223	udelay(100);
	224	GCR = 0;
9c636342 DES	225
	226	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	227	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	228
	229	gsr_bits = 0;
9d1cf39b	230
9c636342 DES	231	/* Can't use interrupts on PXA3xx */
	232	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	233
	234	GCR = GCR_WARM_RST \| GCR_COLD_RST;
	235	while (!(GSR & (GSR_PCR \| GSR_SCR)) && timeout--)
	236	mdelay(10);
9d1cf39b DES	237	}
	238	#endif
	239
	240	bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
	241	{
	242	#ifdef CONFIG_PXA25x
8825e8e8	243	if (cpu_is_pxa25x())
9d1cf39b DES	244	pxa_ac97_warm_pxa25x();
9d1cf39b DES	245	else
9c636342	246	#endif
9d1cf39b DES	247	#ifdef CONFIG_PXA27x
	248	if (cpu_is_pxa27x())
	249	pxa_ac97_warm_pxa27x();
	250	else
	251	#endif
	252	#ifdef CONFIG_PXA3xx
	253	if (cpu_is_pxa3xx())
	254	pxa_ac97_warm_pxa3xx();
	255	else
	256	#endif
	257	BUG();
	258
	259	if (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR))) {
	260	printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
	261	__func__, gsr_bits);
	262
	263	return false;
	264	}
	265
	266	return true;
	267	}
	268	EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
	269
	270	bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
	271	{
	272	#ifdef CONFIG_PXA25x
8825e8e8	273	if (cpu_is_pxa25x())
9d1cf39b DES	274	pxa_ac97_cold_pxa25x();
	275	else
	276	#endif
	277	#ifdef CONFIG_PXA27x
	278	if (cpu_is_pxa27x())
	279	pxa_ac97_cold_pxa27x();
	280	else
	281	#endif
	282	#ifdef CONFIG_PXA3xx
	283	if (cpu_is_pxa3xx())
	284	pxa_ac97_cold_pxa3xx();
	285	else
	286	#endif
	287	BUG();
9c636342 DES	288
	289	if (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR))) {
	290	printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
	291	__func__, gsr_bits);
	292
	293	return false;
	294	}
	295
	296	return true;
	297	}
	298	EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
	299
	300
	301	void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
	302	{
	303	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	304	GCR \|= GCR_SDONE_IE\|GCR_CDONE_IE;
	305	}
	306	EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
	307
	308	static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
	309	{
	310	long status;
	311
	312	status = GSR;
	313	if (status) {
	314	GSR = status;
	315	gsr_bits \|= status;
	316	wake_up(&gsr_wq);
	317
9c636342 DES	318	/* Although we don't use those we still need to clear them
	319	since they tend to spuriously trigger when MMC is used
	320	(hardware bug? go figure)... */
9d1cf39b DES	321	if (cpu_is_pxa27x()) {
	322	MISR = MISR_EOC;
	323	PISR = PISR_EOC;
	324	MCSR = MCSR_EOC;
	325	}
9c636342 DES	326
	327	return IRQ_HANDLED;
	328	}
	329
	330	return IRQ_NONE;
	331	}
	332
	333	#ifdef CONFIG_PM
	334	int pxa2xx_ac97_hw_suspend(void)
	335	{
	336	GCR \|= GCR_ACLINK_OFF;
	337	clk_disable(ac97_clk);
	338	return 0;
	339	}
	340	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
	341
	342	int pxa2xx_ac97_hw_resume(void)
	343	{
8825e8e8	344	if (cpu_is_pxa25x() \|\| cpu_is_pxa27x()) {
9d1cf39b DES	345	pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
	346	pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
	347	pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
	348	pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
	349	}
	350	if (cpu_is_pxa27x()) {
26ade896 RJ	351	/* Use GPIO 113 or 95 as AC97 Reset on Bulverde */
26ade896 RJ	352	set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
9d1cf39b	353	}
9c636342 DES	354	clk_enable(ac97_clk);
	355	return 0;
	356	}
	357	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
	358	#endif
	359
	360	int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
	361	{
	362	int ret;
26ade896 RJ	363	struct pxa2xx_ac97_platform_data *pdata = dev->dev.platform_data;
	364
	365	if (pdata) {
	366	switch (pdata->reset_gpio) {
	367	case 95:
	368	case 113:
	369	reset_gpio = pdata->reset_gpio;
	370	break;
	371	case 0:
	372	reset_gpio = 113;
	373	break;
	374	case -1:
	375	break;
	376	default:
	377	dev_err(dev, "Invalid reset GPIO %d\n",
	378	pdata->reset_gpio);
	379	}
	380	} else {
	381	if (cpu_is_pxa27x())
	382	reset_gpio = 113;
	383	}
9c636342	384
8825e8e8	385	if (cpu_is_pxa25x() \|\| cpu_is_pxa27x()) {
9d1cf39b DES	386	pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
	387	pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
	388	pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
	389	pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
	390	}
	391
	392	if (cpu_is_pxa27x()) {
	393	/* Use GPIO 113 as AC97 Reset on Bulverde */
26ade896	394	set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
9d1cf39b DES	395	ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
	396	if (IS_ERR(ac97conf_clk)) {
	397	ret = PTR_ERR(ac97conf_clk);
	398	ac97conf_clk = NULL;
79612336	399	goto err_conf;
9d1cf39b	400	}
9c636342	401	}
9c636342 DES	402
	403	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	404	if (IS_ERR(ac97_clk)) {
	405	ret = PTR_ERR(ac97_clk);
	406	ac97_clk = NULL;
79612336	407	goto err_clk;
9c636342 DES	408	}
9c636342 DES	409
79612336 DES	410	ret = clk_enable(ac97_clk);
	411	if (ret)
	412	goto err_clk2;
	413
	414	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
	415	if (ret < 0)
	416	goto err_irq;
	417
	418	return 0;
9c636342 DES	419
	420	err_irq:
	421	GCR \|= GCR_ACLINK_OFF;
79612336 DES	422	err_clk2:
	423	clk_put(ac97_clk);
	424	ac97_clk = NULL;
	425	err_clk:
9c636342 DES	426	if (ac97conf_clk) {
	427	clk_put(ac97conf_clk);
	428	ac97conf_clk = NULL;
	429	}
79612336	430	err_conf:
9c636342 DES	431	return ret;
	432	}
	433	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
	434
	435	void pxa2xx_ac97_hw_remove(struct platform_device *dev)
	436	{
	437	GCR \|= GCR_ACLINK_OFF;
	438	free_irq(IRQ_AC97, NULL);
9d1cf39b DES	439	if (ac97conf_clk) {
	440	clk_put(ac97conf_clk);
	441	ac97conf_clk = NULL;
	442	}
9c636342 DES	443	clk_disable(ac97_clk);
	444	clk_put(ac97_clk);
	445	ac97_clk = NULL;
	446	}
	447	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
	448
	449	MODULE_AUTHOR("Nicolas Pitre");
	450	MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
	451	MODULE_LICENSE("GPL");
	452