[mirror_ubuntu-zesty-kernel.git] / sound / arm / pxa2xx-ac97-lib.c

/*
 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
 * which contain:
 *
 * Author:	Nicolas Pitre
 * Created:	Dec 02, 2004
 * Copyright:	MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/delay.h>

#include <sound/ac97_codec.h>
#include <sound/pxa2xx-lib.h>

#include <asm/irq.h>
#include <mach/regs-ac97.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/audio.h>

static DEFINE_MUTEX(car_mutex);
static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
static volatile long gsr_bits;
static struct clk *ac97_clk;
static struct clk *ac97conf_clk;
static int reset_gpio;

/*
 * Beware PXA27x bugs:
 *
 *   o Slot 12 read from modem space will hang controller.
 *   o CDONE, SDONE interrupt fails after any slot 12 IO.
 *
 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
 * 1 jiffy timeout if interrupt never comes).
 */

enum {
	RESETGPIO_FORCE_HIGH,
	RESETGPIO_FORCE_LOW,
	RESETGPIO_NORMAL_ALTFUNC
};

/**
 * set_resetgpio_mode - computes and sets the AC97_RESET gpio mode on PXA
 * @mode: chosen action
 *
 * As the PXA27x CPUs suffer from a AC97 bug, a manual control of the reset line
 * must be done to insure proper work of AC97 reset line.  This function
 * computes the correct gpio_mode for further use by reset functions, and
 * applied the change through pxa_gpio_mode.
 */
static void set_resetgpio_mode(int resetgpio_action)
{
	int mode = 0;

	if (reset_gpio)
		switch (resetgpio_action) {
		case RESETGPIO_NORMAL_ALTFUNC:
			if (reset_gpio == 113)
				mode = 113 | GPIO_ALT_FN_2_OUT;
			if (reset_gpio == 95)
				mode = 95 | GPIO_ALT_FN_1_OUT;
			break;
		case RESETGPIO_FORCE_LOW:
			mode = reset_gpio | GPIO_OUT | GPIO_DFLT_LOW;
			break;
		case RESETGPIO_FORCE_HIGH:
			mode = reset_gpio | GPIO_OUT | GPIO_DFLT_HIGH;
			break;
		};

	if (mode)
		pxa_gpio_mode(mode);
}

unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
{
	unsigned short val = -1;
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
		reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	else
		reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	/* start read access across the ac97 link */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;
	if (reg == AC97_GPIO_STATUS)
		goto out;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_SDONE)) {
		printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);
		val = -1;
		goto out;
	}

	/* valid data now */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;
	/* but we've just started another cycle... */
	wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);

out:	mutex_unlock(&car_mutex);
	return val;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);

void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
			unsigned short val)
{
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
		reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	else
		reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	*reg_addr = val;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_CDONE))
		printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);

	mutex_unlock(&car_mutex);
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);

#ifdef CONFIG_PXA25x
static inline void pxa_ac97_warm_pxa25x(void)
{
	gsr_bits = 0;

	GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
}

static inline void pxa_ac97_cold_pxa25x(void)
{
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	GCR = GCR_COLD_RST;
	GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
}
#endif

#ifdef CONFIG_PXA27x
static inline void pxa_ac97_warm_pxa27x(void)
{
	gsr_bits = 0;

	/* warm reset broken on Bulverde,
	   so manually keep AC97 reset high */
	set_resetgpio_mode(RESETGPIO_FORCE_HIGH);
	udelay(10);
	GCR |= GCR_WARM_RST;
	set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
	udelay(500);
}

static inline void pxa_ac97_cold_pxa27x(void)
{
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	/* PXA27x Developers Manual section 13.5.2.2.1 */
	clk_enable(ac97conf_clk);
	udelay(5);
	clk_disable(ac97conf_clk);
	GCR = GCR_COLD_RST;
	udelay(50);
}
#endif

#ifdef CONFIG_PXA3xx
static inline void pxa_ac97_warm_pxa3xx(void)
{
	int timeout = 100;

	gsr_bits = 0;

	/* Can't use interrupts */
	GCR |= GCR_WARM_RST;
	while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(1);
}

static inline void pxa_ac97_cold_pxa3xx(void)
{
	int timeout = 1000;

	/* Hold CLKBPB for 100us */
	GCR = 0;
	GCR = GCR_CLKBPB;
	udelay(100);
	GCR = 0;

	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	/* Can't use interrupts on PXA3xx */
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);

	GCR = GCR_WARM_RST | GCR_COLD_RST;
	while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(10);
}
#endif

bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
{
	unsigned long gsr;

#ifdef CONFIG_PXA25x
	if (cpu_is_pxa25x())
		pxa_ac97_warm_pxa25x();
	else
#endif
#ifdef CONFIG_PXA27x
	if (cpu_is_pxa27x())
		pxa_ac97_warm_pxa27x();
	else
#endif
#ifdef CONFIG_PXA3xx
	if (cpu_is_pxa3xx())
		pxa_ac97_warm_pxa3xx();
	else
#endif
		BUG();
	gsr = GSR | gsr_bits;
	if (!(gsr & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
				 __func__, gsr);

		return false;
	}

	return true;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);

bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
{
	unsigned long gsr;

#ifdef CONFIG_PXA25x
	if (cpu_is_pxa25x())
		pxa_ac97_cold_pxa25x();
	else
#endif
#ifdef CONFIG_PXA27x
	if (cpu_is_pxa27x())
		pxa_ac97_cold_pxa27x();
	else
#endif
#ifdef CONFIG_PXA3xx
	if (cpu_is_pxa3xx())
		pxa_ac97_cold_pxa3xx();
	else
#endif
		BUG();

	gsr = GSR | gsr_bits;
	if (!(gsr & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
				 __func__, gsr);

		return false;
	}

	return true;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);


void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
{
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
	GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);

static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
{
	long status;

	status = GSR;
	if (status) {
		GSR = status;
		gsr_bits |= status;
		wake_up(&gsr_wq);

		/* Although we don't use those we still need to clear them
		   since they tend to spuriously trigger when MMC is used
		   (hardware bug? go figure)... */
		if (cpu_is_pxa27x()) {
			MISR = MISR_EOC;
			PISR = PISR_EOC;
			MCSR = MCSR_EOC;
		}

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

#ifdef CONFIG_PM
int pxa2xx_ac97_hw_suspend(void)
{
	GCR |= GCR_ACLINK_OFF;
	clk_disable(ac97_clk);
	return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);

int pxa2xx_ac97_hw_resume(void)
{
	clk_enable(ac97_clk);
	return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
#endif

int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
{
	int ret;
	pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;

	if (pdata) {
		switch (pdata->reset_gpio) {
		case 95:
		case 113:
			reset_gpio = pdata->reset_gpio;
			break;
		case 0:
			reset_gpio = 113;
			break;
		case -1:
			break;
		default:
			dev_err(&dev->dev, "Invalid reset GPIO %d\n",
				pdata->reset_gpio);
		}
	} else {
		if (cpu_is_pxa27x())
			reset_gpio = 113;
	}

	if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
		pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
		pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
		pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
		pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
	}

	if (cpu_is_pxa27x()) {
		/* Use GPIO 113 as AC97 Reset on Bulverde */
		set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
		ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
		if (IS_ERR(ac97conf_clk)) {
			ret = PTR_ERR(ac97conf_clk);
			ac97conf_clk = NULL;
			goto err_conf;
		}
	}

	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	if (IS_ERR(ac97_clk)) {
		ret = PTR_ERR(ac97_clk);
		ac97_clk = NULL;
		goto err_clk;
	}

	ret = clk_enable(ac97_clk);
	if (ret)
		goto err_clk2;

	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
	if (ret < 0)
		goto err_irq;

	return 0;

err_irq:
	GCR |= GCR_ACLINK_OFF;
err_clk2:
	clk_put(ac97_clk);
	ac97_clk = NULL;
err_clk:
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
err_conf:
	return ret;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);

void pxa2xx_ac97_hw_remove(struct platform_device *dev)
{
	GCR |= GCR_ACLINK_OFF;
	free_irq(IRQ_AC97, NULL);
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
	clk_disable(ac97_clk);
	clk_put(ac97_clk);
	ac97_clk = NULL;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);

MODULE_AUTHOR("Nicolas Pitre");
MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
MODULE_LICENSE("GPL");
Commit	Line	Data
9c636342 DES	1	/*
	2	* Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
	3	* which contain:
	4	*
	5	* Author: Nicolas Pitre
	6	* Created: Dec 02, 2004
	7	* Copyright: MontaVista Software Inc.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/clk.h>
	18	#include <linux/delay.h>
	19
	20	#include <sound/ac97_codec.h>
	21	#include <sound/pxa2xx-lib.h>
	22
	23	#include <asm/irq.h>
1f017a99	24	#include <mach/regs-ac97.h>
9c636342 DES	25	#include <mach/pxa2xx-gpio.h>
	26	#include <mach/audio.h>
	27
	28	static DEFINE_MUTEX(car_mutex);
	29	static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
	30	static volatile long gsr_bits;
	31	static struct clk *ac97_clk;
9c636342	32	static struct clk *ac97conf_clk;
26ade896	33	static int reset_gpio;
9c636342 DES	34
	35	/*
	36	* Beware PXA27x bugs:
	37	*
	38	* o Slot 12 read from modem space will hang controller.
	39	* o CDONE, SDONE interrupt fails after any slot 12 IO.
	40	*
	41	* We therefore have an hybrid approach for waiting on SDONE (interrupt or
	42	* 1 jiffy timeout if interrupt never comes).
	43	*/
	44
26ade896 RJ	45	enum {
	46	RESETGPIO_FORCE_HIGH,
	47	RESETGPIO_FORCE_LOW,
	48	RESETGPIO_NORMAL_ALTFUNC
	49	};
	50
	51	/**
	52	* set_resetgpio_mode - computes and sets the AC97_RESET gpio mode on PXA
	53	* @mode: chosen action
	54	*
	55	* As the PXA27x CPUs suffer from a AC97 bug, a manual control of the reset line
	56	* must be done to insure proper work of AC97 reset line. This function
	57	* computes the correct gpio_mode for further use by reset functions, and
	58	* applied the change through pxa_gpio_mode.
	59	*/
	60	static void set_resetgpio_mode(int resetgpio_action)
	61	{
	62	int mode = 0;
	63
	64	if (reset_gpio)
	65	switch (resetgpio_action) {
	66	case RESETGPIO_NORMAL_ALTFUNC:
	67	if (reset_gpio == 113)
1ffafeb5	68	mode = 113 \| GPIO_ALT_FN_2_OUT;
26ade896 RJ	69	if (reset_gpio == 95)
	70	mode = 95 \| GPIO_ALT_FN_1_OUT;
	71	break;
	72	case RESETGPIO_FORCE_LOW:
	73	mode = reset_gpio \| GPIO_OUT \| GPIO_DFLT_LOW;
	74	break;
	75	case RESETGPIO_FORCE_HIGH:
	76	mode = reset_gpio \| GPIO_OUT \| GPIO_DFLT_HIGH;
	77	break;
	78	};
	79
	80	if (mode)
	81	pxa_gpio_mode(mode);
	82	}
	83
9c636342 DES	84	unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
	85	{
	86	unsigned short val = -1;
	87	volatile u32 *reg_addr;
	88
	89	mutex_lock(&car_mutex);
	90
	91	/* set up primary or secondary codec space */
8825e8e8	92	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
9c636342 DES	93	reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	94	else
	95	reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
9c636342 DES	96	reg_addr += (reg >> 1);
	97
	98	/* start read access across the ac97 link */
	99	GSR = GSR_CDONE \| GSR_SDONE;
	100	gsr_bits = 0;
	101	val = *reg_addr;
	102	if (reg == AC97_GPIO_STATUS)
	103	goto out;
	104	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1) <= 0 &&
	105	!((GSR \| gsr_bits) & GSR_SDONE)) {
	106	printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
	107	__func__, reg, GSR \| gsr_bits);
	108	val = -1;
	109	goto out;
	110	}
	111
	112	/* valid data now */
	113	GSR = GSR_CDONE \| GSR_SDONE;
	114	gsr_bits = 0;
	115	val = *reg_addr;
	116	/* but we've just started another cycle... */
	117	wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1);
	118
	119	out: mutex_unlock(&car_mutex);
	120	return val;
	121	}
	122	EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
	123
	124	void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
	125	unsigned short val)
	126	{
	127	volatile u32 *reg_addr;
	128
	129	mutex_lock(&car_mutex);
	130
	131	/* set up primary or secondary codec space */
8825e8e8	132	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
9c636342 DES	133	reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	134	else
	135	reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
9c636342 DES	136	reg_addr += (reg >> 1);
	137
	138	GSR = GSR_CDONE \| GSR_SDONE;
	139	gsr_bits = 0;
	140	*reg_addr = val;
	141	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_CDONE, 1) <= 0 &&
	142	!((GSR \| gsr_bits) & GSR_CDONE))
	143	printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
	144	__func__, reg, GSR \| gsr_bits);
	145
	146	mutex_unlock(&car_mutex);
	147	}
	148	EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
	149
9d1cf39b DES	150	#ifdef CONFIG_PXA25x
9d1cf39b DES	151	static inline void pxa_ac97_warm_pxa25x(void)
9c636342	152	{
9c636342 DES	153	gsr_bits = 0;
9c636342 DES	154
9d1cf39b DES	155	GCR \|= GCR_WARM_RST \| GCR_PRIRDY_IEN \| GCR_SECRDY_IEN;
	156	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR \| GSR_SCR), 1);
	157	}
	158
	159	static inline void pxa_ac97_cold_pxa25x(void)
	160	{
	161	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	162	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	163
	164	gsr_bits = 0;
	165
	166	GCR = GCR_COLD_RST;
	167	GCR \|= GCR_CDONE_IE\|GCR_SDONE_IE;
	168	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR \| GSR_SCR), 1);
	169	}
	170	#endif
	171
9c636342	172	#ifdef CONFIG_PXA27x
9d1cf39b DES	173	static inline void pxa_ac97_warm_pxa27x(void)
	174	{
	175	gsr_bits = 0;
	176
9c636342 DES	177	/* warm reset broken on Bulverde,
9c636342 DES	178	so manually keep AC97 reset high */
26ade896	179	set_resetgpio_mode(RESETGPIO_FORCE_HIGH);
9c636342 DES	180	udelay(10);
9c636342 DES	181	GCR \|= GCR_WARM_RST;
26ade896	182	set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
9c636342	183	udelay(500);
9d1cf39b DES	184	}
	185
	186	static inline void pxa_ac97_cold_pxa27x(void)
	187	{
	188	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	189	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	190
	191	gsr_bits = 0;
	192
	193	/* PXA27x Developers Manual section 13.5.2.2.1 */
	194	clk_enable(ac97conf_clk);
	195	udelay(5);
	196	clk_disable(ac97conf_clk);
	197	GCR = GCR_COLD_RST;
	198	udelay(50);
	199	}
9c636342 DES	200	#endif
9c636342 DES	201
9d1cf39b DES	202	#ifdef CONFIG_PXA3xx
	203	static inline void pxa_ac97_warm_pxa3xx(void)
	204	{
	205	int timeout = 100;
9c636342	206
9d1cf39b	207	gsr_bits = 0;
9c636342	208
9d1cf39b DES	209	/* Can't use interrupts */
	210	GCR \|= GCR_WARM_RST;
	211	while (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR)) && timeout--)
	212	mdelay(1);
9c636342	213	}
9c636342	214
9d1cf39b	215	static inline void pxa_ac97_cold_pxa3xx(void)
9c636342	216	{
9c636342 DES	217	int timeout = 1000;
	218
	219	/* Hold CLKBPB for 100us */
	220	GCR = 0;
	221	GCR = GCR_CLKBPB;
	222	udelay(100);
	223	GCR = 0;
9c636342 DES	224
	225	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	226	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	227
	228	gsr_bits = 0;
9d1cf39b	229
9c636342 DES	230	/* Can't use interrupts on PXA3xx */
	231	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	232
	233	GCR = GCR_WARM_RST \| GCR_COLD_RST;
	234	while (!(GSR & (GSR_PCR \| GSR_SCR)) && timeout--)
	235	mdelay(10);
9d1cf39b DES	236	}
	237	#endif
	238
	239	bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
	240	{
057de50c LF	241	unsigned long gsr;
057de50c LF	242
9d1cf39b	243	#ifdef CONFIG_PXA25x
8825e8e8	244	if (cpu_is_pxa25x())
9d1cf39b DES	245	pxa_ac97_warm_pxa25x();
9d1cf39b DES	246	else
9c636342	247	#endif
9d1cf39b DES	248	#ifdef CONFIG_PXA27x
	249	if (cpu_is_pxa27x())
	250	pxa_ac97_warm_pxa27x();
	251	else
	252	#endif
	253	#ifdef CONFIG_PXA3xx
	254	if (cpu_is_pxa3xx())
	255	pxa_ac97_warm_pxa3xx();
	256	else
	257	#endif
	258	BUG();
057de50c LF	259	gsr = GSR \| gsr_bits;
057de50c LF	260	if (!(gsr & (GSR_PCR \| GSR_SCR))) {
9d1cf39b	261	printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
057de50c	262	__func__, gsr);
9d1cf39b DES	263
	264	return false;
	265	}
	266
	267	return true;
	268	}
	269	EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
	270
	271	bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
	272	{
057de50c LF	273	unsigned long gsr;
057de50c LF	274
9d1cf39b	275	#ifdef CONFIG_PXA25x
8825e8e8	276	if (cpu_is_pxa25x())
9d1cf39b DES	277	pxa_ac97_cold_pxa25x();
	278	else
	279	#endif
	280	#ifdef CONFIG_PXA27x
	281	if (cpu_is_pxa27x())
	282	pxa_ac97_cold_pxa27x();
	283	else
	284	#endif
	285	#ifdef CONFIG_PXA3xx
	286	if (cpu_is_pxa3xx())
	287	pxa_ac97_cold_pxa3xx();
	288	else
	289	#endif
	290	BUG();
9c636342	291
057de50c LF	292	gsr = GSR \| gsr_bits;
057de50c LF	293	if (!(gsr & (GSR_PCR \| GSR_SCR))) {
9c636342	294	printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
057de50c	295	__func__, gsr);
9c636342 DES	296
	297	return false;
	298	}
	299
	300	return true;
	301	}
	302	EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
	303
	304
	305	void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
	306	{
	307	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	308	GCR \|= GCR_SDONE_IE\|GCR_CDONE_IE;
	309	}
	310	EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
	311
	312	static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
	313	{
	314	long status;
	315
	316	status = GSR;
	317	if (status) {
	318	GSR = status;
	319	gsr_bits \|= status;
	320	wake_up(&gsr_wq);
	321
9c636342 DES	322	/* Although we don't use those we still need to clear them
	323	since they tend to spuriously trigger when MMC is used
	324	(hardware bug? go figure)... */
9d1cf39b DES	325	if (cpu_is_pxa27x()) {
	326	MISR = MISR_EOC;
	327	PISR = PISR_EOC;
	328	MCSR = MCSR_EOC;
	329	}
9c636342 DES	330
	331	return IRQ_HANDLED;
	332	}
	333
	334	return IRQ_NONE;
	335	}
	336
	337	#ifdef CONFIG_PM
	338	int pxa2xx_ac97_hw_suspend(void)
	339	{
	340	GCR \|= GCR_ACLINK_OFF;
	341	clk_disable(ac97_clk);
	342	return 0;
	343	}
	344	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
	345
	346	int pxa2xx_ac97_hw_resume(void)
	347	{
9c636342 DES	348	clk_enable(ac97_clk);
	349	return 0;
	350	}
	351	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
	352	#endif
	353
	354	int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
	355	{
	356	int ret;
eae17754	357	pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
26ade896 RJ	358
	359	if (pdata) {
	360	switch (pdata->reset_gpio) {
	361	case 95:
	362	case 113:
	363	reset_gpio = pdata->reset_gpio;
	364	break;
	365	case 0:
	366	reset_gpio = 113;
	367	break;
	368	case -1:
	369	break;
	370	default:
1f218695	371	dev_err(&dev->dev, "Invalid reset GPIO %d\n",
26ade896 RJ	372	pdata->reset_gpio);
	373	}
	374	} else {
	375	if (cpu_is_pxa27x())
	376	reset_gpio = 113;
	377	}
9c636342	378
8825e8e8	379	if (cpu_is_pxa25x() \|\| cpu_is_pxa27x()) {
9d1cf39b DES	380	pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
	381	pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
	382	pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
	383	pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
	384	}
	385
	386	if (cpu_is_pxa27x()) {
	387	/* Use GPIO 113 as AC97 Reset on Bulverde */
26ade896	388	set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
9d1cf39b DES	389	ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
	390	if (IS_ERR(ac97conf_clk)) {
	391	ret = PTR_ERR(ac97conf_clk);
	392	ac97conf_clk = NULL;
79612336	393	goto err_conf;
9d1cf39b	394	}
9c636342	395	}
9c636342 DES	396
	397	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	398	if (IS_ERR(ac97_clk)) {
	399	ret = PTR_ERR(ac97_clk);
	400	ac97_clk = NULL;
79612336	401	goto err_clk;
9c636342 DES	402	}
9c636342 DES	403
79612336 DES	404	ret = clk_enable(ac97_clk);
	405	if (ret)
	406	goto err_clk2;
	407
	408	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
	409	if (ret < 0)
	410	goto err_irq;
	411
	412	return 0;
9c636342 DES	413
	414	err_irq:
	415	GCR \|= GCR_ACLINK_OFF;
79612336 DES	416	err_clk2:
	417	clk_put(ac97_clk);
	418	ac97_clk = NULL;
	419	err_clk:
9c636342 DES	420	if (ac97conf_clk) {
	421	clk_put(ac97conf_clk);
	422	ac97conf_clk = NULL;
	423	}
79612336	424	err_conf:
9c636342 DES	425	return ret;
	426	}
	427	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
	428
	429	void pxa2xx_ac97_hw_remove(struct platform_device *dev)
	430	{
	431	GCR \|= GCR_ACLINK_OFF;
	432	free_irq(IRQ_AC97, NULL);
9d1cf39b DES	433	if (ac97conf_clk) {
	434	clk_put(ac97conf_clk);
	435	ac97conf_clk = NULL;
	436	}
9c636342 DES	437	clk_disable(ac97_clk);
	438	clk_put(ac97_clk);
	439	ac97_clk = NULL;
	440	}
	441	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
	442
	443	MODULE_AUTHOR("Nicolas Pitre");
	444	MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
	445	MODULE_LICENSE("GPL");
	446