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Commit | Line | Data |
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31ef9134 CL |
1 | /* |
2 | * Audio and Music Data Transmission Protocol (IEC 61883-6) streams | |
3 | * with Common Isochronous Packet (IEC 61883-1) headers | |
4 | * | |
5 | * Copyright (c) Clemens Ladisch <clemens@ladisch.de> | |
6 | * Licensed under the terms of the GNU General Public License, version 2. | |
7 | */ | |
8 | ||
9 | #include <linux/device.h> | |
10 | #include <linux/err.h> | |
11 | #include <linux/firewire.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/slab.h> | |
14 | #include <sound/pcm.h> | |
7b2d99fa | 15 | #include <sound/pcm_params.h> |
d67c46b9 | 16 | #include "amdtp-stream.h" |
31ef9134 CL |
17 | |
18 | #define TICKS_PER_CYCLE 3072 | |
19 | #define CYCLES_PER_SECOND 8000 | |
20 | #define TICKS_PER_SECOND (TICKS_PER_CYCLE * CYCLES_PER_SECOND) | |
21 | ||
0c95c1d6 TS |
22 | /* Always support Linux tracing subsystem. */ |
23 | #define CREATE_TRACE_POINTS | |
24 | #include "amdtp-stream-trace.h" | |
25 | ||
ca5b5050 | 26 | #define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 microseconds */ |
31ef9134 | 27 | |
b445db44 TS |
28 | /* isochronous header parameters */ |
29 | #define ISO_DATA_LENGTH_SHIFT 16 | |
31ef9134 CL |
30 | #define TAG_CIP 1 |
31 | ||
b445db44 | 32 | /* common isochronous packet header parameters */ |
9a2820c1 TS |
33 | #define CIP_EOH_SHIFT 31 |
34 | #define CIP_EOH (1u << CIP_EOH_SHIFT) | |
b445db44 | 35 | #define CIP_EOH_MASK 0x80000000 |
9a2820c1 TS |
36 | #define CIP_SID_SHIFT 24 |
37 | #define CIP_SID_MASK 0x3f000000 | |
38 | #define CIP_DBS_MASK 0x00ff0000 | |
39 | #define CIP_DBS_SHIFT 16 | |
9863874f TS |
40 | #define CIP_SPH_MASK 0x00000400 |
41 | #define CIP_SPH_SHIFT 10 | |
9a2820c1 TS |
42 | #define CIP_DBC_MASK 0x000000ff |
43 | #define CIP_FMT_SHIFT 24 | |
b445db44 | 44 | #define CIP_FMT_MASK 0x3f000000 |
9a2820c1 TS |
45 | #define CIP_FDF_MASK 0x00ff0000 |
46 | #define CIP_FDF_SHIFT 16 | |
b445db44 TS |
47 | #define CIP_SYT_MASK 0x0000ffff |
48 | #define CIP_SYT_NO_INFO 0xffff | |
b445db44 | 49 | |
51c29fd2 | 50 | /* Audio and Music transfer protocol specific parameters */ |
414ba022 | 51 | #define CIP_FMT_AM 0x10 |
2b3fc456 | 52 | #define AMDTP_FDF_NO_DATA 0xff |
31ef9134 CL |
53 | |
54 | /* TODO: make these configurable */ | |
55 | #define INTERRUPT_INTERVAL 16 | |
56 | #define QUEUE_LENGTH 48 | |
57 | ||
2b3fc456 | 58 | #define IN_PACKET_HEADER_SIZE 4 |
4b7da117 TS |
59 | #define OUT_PACKET_HEADER_SIZE 0 |
60 | ||
76fb8789 CL |
61 | static void pcm_period_tasklet(unsigned long data); |
62 | ||
31ef9134 | 63 | /** |
be4a2894 TS |
64 | * amdtp_stream_init - initialize an AMDTP stream structure |
65 | * @s: the AMDTP stream to initialize | |
31ef9134 | 66 | * @unit: the target of the stream |
3ff7e8f0 | 67 | * @dir: the direction of stream |
31ef9134 | 68 | * @flags: the packet transmission method to use |
5955815e | 69 | * @fmt: the value of fmt field in CIP header |
df075fee TS |
70 | * @process_data_blocks: callback handler to process data blocks |
71 | * @protocol_size: the size to allocate newly for protocol | |
31ef9134 | 72 | */ |
be4a2894 | 73 | int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit, |
5955815e | 74 | enum amdtp_stream_direction dir, enum cip_flags flags, |
df075fee TS |
75 | unsigned int fmt, |
76 | amdtp_stream_process_data_blocks_t process_data_blocks, | |
77 | unsigned int protocol_size) | |
31ef9134 | 78 | { |
df075fee TS |
79 | if (process_data_blocks == NULL) |
80 | return -EINVAL; | |
81 | ||
82 | s->protocol = kzalloc(protocol_size, GFP_KERNEL); | |
83 | if (!s->protocol) | |
84 | return -ENOMEM; | |
85 | ||
c6f224dc | 86 | s->unit = unit; |
3ff7e8f0 | 87 | s->direction = dir; |
31ef9134 CL |
88 | s->flags = flags; |
89 | s->context = ERR_PTR(-1); | |
90 | mutex_init(&s->mutex); | |
76fb8789 | 91 | tasklet_init(&s->period_tasklet, pcm_period_tasklet, (unsigned long)s); |
ec00f5e4 | 92 | s->packet_index = 0; |
31ef9134 | 93 | |
7b3b0d85 TS |
94 | init_waitqueue_head(&s->callback_wait); |
95 | s->callbacked = false; | |
7b3b0d85 | 96 | |
5955815e | 97 | s->fmt = fmt; |
df075fee | 98 | s->process_data_blocks = process_data_blocks; |
414ba022 | 99 | |
31ef9134 CL |
100 | return 0; |
101 | } | |
be4a2894 | 102 | EXPORT_SYMBOL(amdtp_stream_init); |
31ef9134 CL |
103 | |
104 | /** | |
be4a2894 TS |
105 | * amdtp_stream_destroy - free stream resources |
106 | * @s: the AMDTP stream to destroy | |
31ef9134 | 107 | */ |
be4a2894 | 108 | void amdtp_stream_destroy(struct amdtp_stream *s) |
31ef9134 | 109 | { |
44c376b9 TS |
110 | /* Not initialized. */ |
111 | if (s->protocol == NULL) | |
112 | return; | |
113 | ||
be4a2894 | 114 | WARN_ON(amdtp_stream_running(s)); |
df075fee | 115 | kfree(s->protocol); |
31ef9134 | 116 | mutex_destroy(&s->mutex); |
31ef9134 | 117 | } |
be4a2894 | 118 | EXPORT_SYMBOL(amdtp_stream_destroy); |
31ef9134 | 119 | |
c5280e99 | 120 | const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = { |
a7304e3b CL |
121 | [CIP_SFC_32000] = 8, |
122 | [CIP_SFC_44100] = 8, | |
123 | [CIP_SFC_48000] = 8, | |
124 | [CIP_SFC_88200] = 16, | |
125 | [CIP_SFC_96000] = 16, | |
126 | [CIP_SFC_176400] = 32, | |
127 | [CIP_SFC_192000] = 32, | |
128 | }; | |
129 | EXPORT_SYMBOL(amdtp_syt_intervals); | |
130 | ||
f9503a68 | 131 | const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = { |
1017abed TS |
132 | [CIP_SFC_32000] = 32000, |
133 | [CIP_SFC_44100] = 44100, | |
134 | [CIP_SFC_48000] = 48000, | |
135 | [CIP_SFC_88200] = 88200, | |
136 | [CIP_SFC_96000] = 96000, | |
137 | [CIP_SFC_176400] = 176400, | |
138 | [CIP_SFC_192000] = 192000, | |
139 | }; | |
140 | EXPORT_SYMBOL(amdtp_rate_table); | |
141 | ||
7b2d99fa TS |
142 | /** |
143 | * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream | |
144 | * @s: the AMDTP stream, which must be initialized. | |
145 | * @runtime: the PCM substream runtime | |
146 | */ | |
147 | int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s, | |
148 | struct snd_pcm_runtime *runtime) | |
149 | { | |
150 | int err; | |
151 | ||
7b2d99fa TS |
152 | /* |
153 | * Currently firewire-lib processes 16 packets in one software | |
154 | * interrupt callback. This equals to 2msec but actually the | |
155 | * interval of the interrupts has a jitter. | |
156 | * Additionally, even if adding a constraint to fit period size to | |
157 | * 2msec, actual calculated frames per period doesn't equal to 2msec, | |
158 | * depending on sampling rate. | |
159 | * Anyway, the interval to call snd_pcm_period_elapsed() cannot 2msec. | |
160 | * Here let us use 5msec for safe period interrupt. | |
161 | */ | |
162 | err = snd_pcm_hw_constraint_minmax(runtime, | |
163 | SNDRV_PCM_HW_PARAM_PERIOD_TIME, | |
164 | 5000, UINT_MAX); | |
165 | if (err < 0) | |
166 | goto end; | |
167 | ||
168 | /* Non-Blocking stream has no more constraints */ | |
169 | if (!(s->flags & CIP_BLOCKING)) | |
170 | goto end; | |
171 | ||
172 | /* | |
173 | * One AMDTP packet can include some frames. In blocking mode, the | |
174 | * number equals to SYT_INTERVAL. So the number is 8, 16 or 32, | |
175 | * depending on its sampling rate. For accurate period interrupt, it's | |
ce991981 | 176 | * preferrable to align period/buffer sizes to current SYT_INTERVAL. |
7b2d99fa | 177 | * |
ce991981 YG |
178 | * TODO: These constraints can be improved with proper rules. |
179 | * Currently apply LCM of SYT_INTERVALs. | |
7b2d99fa TS |
180 | */ |
181 | err = snd_pcm_hw_constraint_step(runtime, 0, | |
182 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32); | |
183 | if (err < 0) | |
184 | goto end; | |
185 | err = snd_pcm_hw_constraint_step(runtime, 0, | |
186 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32); | |
187 | end: | |
188 | return err; | |
189 | } | |
190 | EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints); | |
191 | ||
31ef9134 | 192 | /** |
be4a2894 TS |
193 | * amdtp_stream_set_parameters - set stream parameters |
194 | * @s: the AMDTP stream to configure | |
31ef9134 | 195 | * @rate: the sample rate |
df075fee | 196 | * @data_block_quadlets: the size of a data block in quadlet unit |
31ef9134 | 197 | * |
a7304e3b | 198 | * The parameters must be set before the stream is started, and must not be |
31ef9134 CL |
199 | * changed while the stream is running. |
200 | */ | |
df075fee TS |
201 | int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate, |
202 | unsigned int data_block_quadlets) | |
31ef9134 | 203 | { |
df075fee | 204 | unsigned int sfc; |
31ef9134 | 205 | |
547e631c | 206 | for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) { |
1017abed | 207 | if (amdtp_rate_table[sfc] == rate) |
547e631c TS |
208 | break; |
209 | } | |
210 | if (sfc == ARRAY_SIZE(amdtp_rate_table)) | |
211 | return -EINVAL; | |
e84d15f6 | 212 | |
e84d15f6 | 213 | s->sfc = sfc; |
df075fee | 214 | s->data_block_quadlets = data_block_quadlets; |
a7304e3b | 215 | s->syt_interval = amdtp_syt_intervals[sfc]; |
e84d15f6 CL |
216 | |
217 | /* default buffering in the device */ | |
218 | s->transfer_delay = TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE; | |
219 | if (s->flags & CIP_BLOCKING) | |
220 | /* additional buffering needed to adjust for no-data packets */ | |
221 | s->transfer_delay += TICKS_PER_SECOND * s->syt_interval / rate; | |
77d2a8a4 | 222 | |
547e631c | 223 | return 0; |
31ef9134 | 224 | } |
be4a2894 | 225 | EXPORT_SYMBOL(amdtp_stream_set_parameters); |
31ef9134 CL |
226 | |
227 | /** | |
be4a2894 TS |
228 | * amdtp_stream_get_max_payload - get the stream's packet size |
229 | * @s: the AMDTP stream | |
31ef9134 CL |
230 | * |
231 | * This function must not be called before the stream has been configured | |
be4a2894 | 232 | * with amdtp_stream_set_parameters(). |
31ef9134 | 233 | */ |
be4a2894 | 234 | unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s) |
31ef9134 | 235 | { |
a2064710 TS |
236 | unsigned int multiplier = 1; |
237 | ||
238 | if (s->flags & CIP_JUMBO_PAYLOAD) | |
239 | multiplier = 5; | |
240 | ||
241 | return 8 + s->syt_interval * s->data_block_quadlets * 4 * multiplier; | |
31ef9134 | 242 | } |
be4a2894 | 243 | EXPORT_SYMBOL(amdtp_stream_get_max_payload); |
31ef9134 | 244 | |
76fb8789 | 245 | /** |
be4a2894 TS |
246 | * amdtp_stream_pcm_prepare - prepare PCM device for running |
247 | * @s: the AMDTP stream | |
76fb8789 CL |
248 | * |
249 | * This function should be called from the PCM device's .prepare callback. | |
250 | */ | |
be4a2894 | 251 | void amdtp_stream_pcm_prepare(struct amdtp_stream *s) |
76fb8789 CL |
252 | { |
253 | tasklet_kill(&s->period_tasklet); | |
254 | s->pcm_buffer_pointer = 0; | |
255 | s->pcm_period_pointer = 0; | |
256 | } | |
be4a2894 | 257 | EXPORT_SYMBOL(amdtp_stream_pcm_prepare); |
76fb8789 | 258 | |
875be091 TS |
259 | static unsigned int calculate_data_blocks(struct amdtp_stream *s, |
260 | unsigned int syt) | |
31ef9134 CL |
261 | { |
262 | unsigned int phase, data_blocks; | |
263 | ||
875be091 TS |
264 | /* Blocking mode. */ |
265 | if (s->flags & CIP_BLOCKING) { | |
266 | /* This module generate empty packet for 'no data'. */ | |
267 | if (syt == CIP_SYT_NO_INFO) | |
268 | data_blocks = 0; | |
269 | else | |
270 | data_blocks = s->syt_interval; | |
271 | /* Non-blocking mode. */ | |
31ef9134 | 272 | } else { |
875be091 TS |
273 | if (!cip_sfc_is_base_44100(s->sfc)) { |
274 | /* Sample_rate / 8000 is an integer, and precomputed. */ | |
275 | data_blocks = s->data_block_state; | |
276 | } else { | |
277 | phase = s->data_block_state; | |
31ef9134 CL |
278 | |
279 | /* | |
280 | * This calculates the number of data blocks per packet so that | |
281 | * 1) the overall rate is correct and exactly synchronized to | |
282 | * the bus clock, and | |
283 | * 2) packets with a rounded-up number of blocks occur as early | |
284 | * as possible in the sequence (to prevent underruns of the | |
285 | * device's buffer). | |
286 | */ | |
875be091 TS |
287 | if (s->sfc == CIP_SFC_44100) |
288 | /* 6 6 5 6 5 6 5 ... */ | |
289 | data_blocks = 5 + ((phase & 1) ^ | |
290 | (phase == 0 || phase >= 40)); | |
291 | else | |
292 | /* 12 11 11 11 11 ... or 23 22 22 22 22 ... */ | |
293 | data_blocks = 11 * (s->sfc >> 1) + (phase == 0); | |
294 | if (++phase >= (80 >> (s->sfc >> 1))) | |
295 | phase = 0; | |
296 | s->data_block_state = phase; | |
297 | } | |
31ef9134 CL |
298 | } |
299 | ||
300 | return data_blocks; | |
301 | } | |
302 | ||
be4a2894 | 303 | static unsigned int calculate_syt(struct amdtp_stream *s, |
31ef9134 CL |
304 | unsigned int cycle) |
305 | { | |
306 | unsigned int syt_offset, phase, index, syt; | |
307 | ||
308 | if (s->last_syt_offset < TICKS_PER_CYCLE) { | |
309 | if (!cip_sfc_is_base_44100(s->sfc)) | |
310 | syt_offset = s->last_syt_offset + s->syt_offset_state; | |
311 | else { | |
312 | /* | |
313 | * The time, in ticks, of the n'th SYT_INTERVAL sample is: | |
314 | * n * SYT_INTERVAL * 24576000 / sample_rate | |
315 | * Modulo TICKS_PER_CYCLE, the difference between successive | |
316 | * elements is about 1386.23. Rounding the results of this | |
317 | * formula to the SYT precision results in a sequence of | |
318 | * differences that begins with: | |
319 | * 1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ... | |
320 | * This code generates _exactly_ the same sequence. | |
321 | */ | |
322 | phase = s->syt_offset_state; | |
323 | index = phase % 13; | |
324 | syt_offset = s->last_syt_offset; | |
325 | syt_offset += 1386 + ((index && !(index & 3)) || | |
326 | phase == 146); | |
327 | if (++phase >= 147) | |
328 | phase = 0; | |
329 | s->syt_offset_state = phase; | |
330 | } | |
331 | } else | |
332 | syt_offset = s->last_syt_offset - TICKS_PER_CYCLE; | |
333 | s->last_syt_offset = syt_offset; | |
334 | ||
be454366 | 335 | if (syt_offset < TICKS_PER_CYCLE) { |
e84d15f6 | 336 | syt_offset += s->transfer_delay; |
be454366 CL |
337 | syt = (cycle + syt_offset / TICKS_PER_CYCLE) << 12; |
338 | syt += syt_offset % TICKS_PER_CYCLE; | |
31ef9134 | 339 | |
b445db44 | 340 | return syt & CIP_SYT_MASK; |
be454366 | 341 | } else { |
b445db44 | 342 | return CIP_SYT_NO_INFO; |
be454366 | 343 | } |
31ef9134 CL |
344 | } |
345 | ||
4b7da117 TS |
346 | static void update_pcm_pointers(struct amdtp_stream *s, |
347 | struct snd_pcm_substream *pcm, | |
348 | unsigned int frames) | |
65845f29 TS |
349 | { |
350 | unsigned int ptr; | |
351 | ||
4b7da117 TS |
352 | ptr = s->pcm_buffer_pointer + frames; |
353 | if (ptr >= pcm->runtime->buffer_size) | |
354 | ptr -= pcm->runtime->buffer_size; | |
355 | ACCESS_ONCE(s->pcm_buffer_pointer) = ptr; | |
356 | ||
357 | s->pcm_period_pointer += frames; | |
358 | if (s->pcm_period_pointer >= pcm->runtime->period_size) { | |
359 | s->pcm_period_pointer -= pcm->runtime->period_size; | |
4b7da117 TS |
360 | tasklet_hi_schedule(&s->period_tasklet); |
361 | } | |
362 | } | |
363 | ||
364 | static void pcm_period_tasklet(unsigned long data) | |
365 | { | |
366 | struct amdtp_stream *s = (void *)data; | |
367 | struct snd_pcm_substream *pcm = ACCESS_ONCE(s->pcm); | |
368 | ||
369 | if (pcm) | |
370 | snd_pcm_period_elapsed(pcm); | |
371 | } | |
372 | ||
ff38e0c7 TS |
373 | static int queue_packet(struct amdtp_stream *s, unsigned int header_length, |
374 | unsigned int payload_length) | |
4b7da117 TS |
375 | { |
376 | struct fw_iso_packet p = {0}; | |
7b3b0d85 TS |
377 | int err = 0; |
378 | ||
379 | if (IS_ERR(s->context)) | |
380 | goto end; | |
4b7da117 TS |
381 | |
382 | p.interrupt = IS_ALIGNED(s->packet_index + 1, INTERRUPT_INTERVAL); | |
383 | p.tag = TAG_CIP; | |
384 | p.header_length = header_length; | |
ff38e0c7 TS |
385 | if (payload_length > 0) |
386 | p.payload_length = payload_length; | |
387 | else | |
388 | p.skip = true; | |
4b7da117 TS |
389 | err = fw_iso_context_queue(s->context, &p, &s->buffer.iso_buffer, |
390 | s->buffer.packets[s->packet_index].offset); | |
391 | if (err < 0) { | |
392 | dev_err(&s->unit->device, "queueing error: %d\n", err); | |
393 | goto end; | |
394 | } | |
395 | ||
396 | if (++s->packet_index >= QUEUE_LENGTH) | |
397 | s->packet_index = 0; | |
398 | end: | |
399 | return err; | |
400 | } | |
401 | ||
402 | static inline int queue_out_packet(struct amdtp_stream *s, | |
ff38e0c7 | 403 | unsigned int payload_length) |
4b7da117 | 404 | { |
ff38e0c7 | 405 | return queue_packet(s, OUT_PACKET_HEADER_SIZE, payload_length); |
4b7da117 TS |
406 | } |
407 | ||
2b3fc456 TS |
408 | static inline int queue_in_packet(struct amdtp_stream *s) |
409 | { | |
410 | return queue_packet(s, IN_PACKET_HEADER_SIZE, | |
ff38e0c7 | 411 | amdtp_stream_get_max_payload(s)); |
2b3fc456 TS |
412 | } |
413 | ||
a9c4284b TS |
414 | static int handle_out_packet(struct amdtp_stream *s, unsigned int cycle, |
415 | unsigned int index) | |
31ef9134 CL |
416 | { |
417 | __be32 *buffer; | |
390a1512 TS |
418 | unsigned int syt; |
419 | unsigned int data_blocks; | |
6fc6b9ce | 420 | unsigned int payload_length; |
20e44577 | 421 | unsigned int pcm_frames; |
31ef9134 | 422 | struct snd_pcm_substream *pcm; |
31ef9134 | 423 | |
ccccad86 | 424 | buffer = s->buffer.packets[s->packet_index].buffer; |
390a1512 TS |
425 | syt = calculate_syt(s, cycle); |
426 | data_blocks = calculate_data_blocks(s, syt); | |
df075fee | 427 | pcm_frames = s->process_data_blocks(s, buffer + 2, data_blocks, &syt); |
20e44577 | 428 | |
9dae017b TS |
429 | if (s->flags & CIP_DBC_IS_END_EVENT) |
430 | s->data_block_counter = | |
431 | (s->data_block_counter + data_blocks) & 0xff; | |
432 | ||
31ef9134 | 433 | buffer[0] = cpu_to_be32(ACCESS_ONCE(s->source_node_id_field) | |
9a2820c1 | 434 | (s->data_block_quadlets << CIP_DBS_SHIFT) | |
9863874f | 435 | ((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) | |
31ef9134 | 436 | s->data_block_counter); |
414ba022 TS |
437 | buffer[1] = cpu_to_be32(CIP_EOH | |
438 | ((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) | | |
439 | ((s->fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) | | |
440 | (syt & CIP_SYT_MASK)); | |
31ef9134 | 441 | |
9dae017b TS |
442 | if (!(s->flags & CIP_DBC_IS_END_EVENT)) |
443 | s->data_block_counter = | |
444 | (s->data_block_counter + data_blocks) & 0xff; | |
4b7da117 | 445 | payload_length = 8 + data_blocks * 4 * s->data_block_quadlets; |
0c95c1d6 | 446 | |
a9c4284b | 447 | trace_out_packet(s, cycle, buffer, payload_length, index); |
0c95c1d6 | 448 | |
ff38e0c7 | 449 | if (queue_out_packet(s, payload_length) < 0) |
a4103bd7 | 450 | return -EIO; |
31ef9134 | 451 | |
20e44577 TS |
452 | pcm = ACCESS_ONCE(s->pcm); |
453 | if (pcm && pcm_frames > 0) | |
454 | update_pcm_pointers(s, pcm, pcm_frames); | |
a4103bd7 TS |
455 | |
456 | /* No need to return the number of handled data blocks. */ | |
457 | return 0; | |
76fb8789 CL |
458 | } |
459 | ||
6fc6b9ce | 460 | static int handle_in_packet(struct amdtp_stream *s, |
a9c4284b TS |
461 | unsigned int payload_quadlets, unsigned int cycle, |
462 | unsigned int index) | |
2b3fc456 | 463 | { |
d9a16fc9 | 464 | __be32 *buffer; |
2b3fc456 | 465 | u32 cip_header[2]; |
9863874f | 466 | unsigned int sph, fmt, fdf, syt; |
6fc6b9ce | 467 | unsigned int data_block_quadlets, data_block_counter, dbc_interval; |
d9a16fc9 | 468 | unsigned int data_blocks; |
20e44577 TS |
469 | struct snd_pcm_substream *pcm; |
470 | unsigned int pcm_frames; | |
c8bdf49b | 471 | bool lost; |
2b3fc456 | 472 | |
d9a16fc9 | 473 | buffer = s->buffer.packets[s->packet_index].buffer; |
2b3fc456 TS |
474 | cip_header[0] = be32_to_cpu(buffer[0]); |
475 | cip_header[1] = be32_to_cpu(buffer[1]); | |
476 | ||
a9c4284b | 477 | trace_in_packet(s, cycle, cip_header, payload_quadlets, index); |
0c95c1d6 | 478 | |
2b3fc456 TS |
479 | /* |
480 | * This module supports 'Two-quadlet CIP header with SYT field'. | |
77d2a8a4 | 481 | * For convenience, also check FMT field is AM824 or not. |
2b3fc456 | 482 | */ |
2128f78f TS |
483 | if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) || |
484 | ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) && | |
485 | (!(s->flags & CIP_HEADER_WITHOUT_EOH))) { | |
2b3fc456 TS |
486 | dev_info_ratelimited(&s->unit->device, |
487 | "Invalid CIP header for AMDTP: %08X:%08X\n", | |
488 | cip_header[0], cip_header[1]); | |
d9a16fc9 | 489 | data_blocks = 0; |
20e44577 | 490 | pcm_frames = 0; |
2b3fc456 TS |
491 | goto end; |
492 | } | |
493 | ||
414ba022 | 494 | /* Check valid protocol or not. */ |
9863874f | 495 | sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT; |
414ba022 | 496 | fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT; |
9863874f | 497 | if (sph != s->sph || fmt != s->fmt) { |
2a7e1713 TS |
498 | dev_info_ratelimited(&s->unit->device, |
499 | "Detect unexpected protocol: %08x %08x\n", | |
500 | cip_header[0], cip_header[1]); | |
d9a16fc9 | 501 | data_blocks = 0; |
2a7e1713 TS |
502 | pcm_frames = 0; |
503 | goto end; | |
414ba022 TS |
504 | } |
505 | ||
2b3fc456 | 506 | /* Calculate data blocks */ |
414ba022 | 507 | fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT; |
2b3fc456 | 508 | if (payload_quadlets < 3 || |
414ba022 | 509 | (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) { |
d9a16fc9 | 510 | data_blocks = 0; |
2b3fc456 TS |
511 | } else { |
512 | data_block_quadlets = | |
9a2820c1 | 513 | (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT; |
2b3fc456 TS |
514 | /* avoid division by zero */ |
515 | if (data_block_quadlets == 0) { | |
12e0f438 | 516 | dev_err(&s->unit->device, |
2b3fc456 TS |
517 | "Detect invalid value in dbs field: %08X\n", |
518 | cip_header[0]); | |
a9007054 | 519 | return -EPROTO; |
2b3fc456 | 520 | } |
69702239 TS |
521 | if (s->flags & CIP_WRONG_DBS) |
522 | data_block_quadlets = s->data_block_quadlets; | |
2b3fc456 | 523 | |
d9a16fc9 | 524 | data_blocks = (payload_quadlets - 2) / data_block_quadlets; |
2b3fc456 TS |
525 | } |
526 | ||
527 | /* Check data block counter continuity */ | |
9a2820c1 | 528 | data_block_counter = cip_header[0] & CIP_DBC_MASK; |
d9a16fc9 | 529 | if (data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) && |
9d59124c TS |
530 | s->data_block_counter != UINT_MAX) |
531 | data_block_counter = s->data_block_counter; | |
532 | ||
18f5ed36 TS |
533 | if (((s->flags & CIP_SKIP_DBC_ZERO_CHECK) && |
534 | data_block_counter == s->tx_first_dbc) || | |
535 | s->data_block_counter == UINT_MAX) { | |
b84b1a27 TS |
536 | lost = false; |
537 | } else if (!(s->flags & CIP_DBC_IS_END_EVENT)) { | |
c8bdf49b | 538 | lost = data_block_counter != s->data_block_counter; |
d9cd0065 | 539 | } else { |
d9a16fc9 | 540 | if (data_blocks > 0 && s->tx_dbc_interval > 0) |
d9cd0065 TS |
541 | dbc_interval = s->tx_dbc_interval; |
542 | else | |
d9a16fc9 | 543 | dbc_interval = data_blocks; |
d9cd0065 | 544 | |
c8bdf49b | 545 | lost = data_block_counter != |
d9cd0065 TS |
546 | ((s->data_block_counter + dbc_interval) & 0xff); |
547 | } | |
c8bdf49b TS |
548 | |
549 | if (lost) { | |
12e0f438 TS |
550 | dev_err(&s->unit->device, |
551 | "Detect discontinuity of CIP: %02X %02X\n", | |
552 | s->data_block_counter, data_block_counter); | |
6fc6b9ce | 553 | return -EIO; |
2b3fc456 TS |
554 | } |
555 | ||
d9a16fc9 TS |
556 | syt = be32_to_cpu(buffer[1]) & CIP_SYT_MASK; |
557 | pcm_frames = s->process_data_blocks(s, buffer + 2, data_blocks, &syt); | |
2b3fc456 | 558 | |
c8bdf49b TS |
559 | if (s->flags & CIP_DBC_IS_END_EVENT) |
560 | s->data_block_counter = data_block_counter; | |
561 | else | |
562 | s->data_block_counter = | |
d9a16fc9 | 563 | (data_block_counter + data_blocks) & 0xff; |
2b3fc456 TS |
564 | end: |
565 | if (queue_in_packet(s) < 0) | |
6fc6b9ce | 566 | return -EIO; |
2b3fc456 | 567 | |
20e44577 TS |
568 | pcm = ACCESS_ONCE(s->pcm); |
569 | if (pcm && pcm_frames > 0) | |
570 | update_pcm_pointers(s, pcm, pcm_frames); | |
2b3fc456 | 571 | |
31ea49ba | 572 | return 0; |
2b3fc456 TS |
573 | } |
574 | ||
73fc7f08 TS |
575 | /* |
576 | * In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On | |
577 | * the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent | |
578 | * it. Thus, via Linux firewire subsystem, we can get the 3 bits for second. | |
579 | */ | |
580 | static inline u32 compute_cycle_count(u32 tstamp) | |
581 | { | |
582 | return (((tstamp >> 13) & 0x07) * 8000) + (tstamp & 0x1fff); | |
583 | } | |
584 | ||
585 | static inline u32 increment_cycle_count(u32 cycle, unsigned int addend) | |
586 | { | |
587 | cycle += addend; | |
588 | if (cycle >= 8 * CYCLES_PER_SECOND) | |
589 | cycle -= 8 * CYCLES_PER_SECOND; | |
590 | return cycle; | |
591 | } | |
592 | ||
f90e2ded TS |
593 | static inline u32 decrement_cycle_count(u32 cycle, unsigned int subtrahend) |
594 | { | |
595 | if (cycle < subtrahend) | |
596 | cycle += 8 * CYCLES_PER_SECOND; | |
597 | return cycle - subtrahend; | |
598 | } | |
599 | ||
73fc7f08 | 600 | static void out_stream_callback(struct fw_iso_context *context, u32 tstamp, |
4b7da117 TS |
601 | size_t header_length, void *header, |
602 | void *private_data) | |
31ef9134 | 603 | { |
be4a2894 | 604 | struct amdtp_stream *s = private_data; |
390a1512 | 605 | unsigned int i, packets = header_length / 4; |
73fc7f08 | 606 | u32 cycle; |
31ef9134 | 607 | |
a4103bd7 TS |
608 | if (s->packet_index < 0) |
609 | return; | |
610 | ||
73fc7f08 TS |
611 | cycle = compute_cycle_count(tstamp); |
612 | ||
613 | /* Align to actual cycle count for the last packet. */ | |
614 | cycle = increment_cycle_count(cycle, QUEUE_LENGTH - packets); | |
31ef9134 | 615 | |
ccccad86 | 616 | for (i = 0; i < packets; ++i) { |
73fc7f08 | 617 | cycle = increment_cycle_count(cycle, 1); |
a9c4284b | 618 | if (handle_out_packet(s, cycle, i) < 0) { |
a4103bd7 TS |
619 | s->packet_index = -1; |
620 | amdtp_stream_pcm_abort(s); | |
621 | return; | |
622 | } | |
ccccad86 | 623 | } |
a4103bd7 | 624 | |
13882a82 | 625 | fw_iso_context_queue_flush(s->context); |
31ef9134 CL |
626 | } |
627 | ||
73fc7f08 | 628 | static void in_stream_callback(struct fw_iso_context *context, u32 tstamp, |
2b3fc456 TS |
629 | size_t header_length, void *header, |
630 | void *private_data) | |
631 | { | |
632 | struct amdtp_stream *s = private_data; | |
d9a16fc9 | 633 | unsigned int i, packets; |
a2064710 | 634 | unsigned int payload_quadlets, max_payload_quadlets; |
d9a16fc9 | 635 | __be32 *headers = header; |
f90e2ded | 636 | u32 cycle; |
2b3fc456 | 637 | |
a4103bd7 TS |
638 | if (s->packet_index < 0) |
639 | return; | |
640 | ||
2b3fc456 TS |
641 | /* The number of packets in buffer */ |
642 | packets = header_length / IN_PACKET_HEADER_SIZE; | |
643 | ||
f90e2ded TS |
644 | cycle = compute_cycle_count(tstamp); |
645 | ||
646 | /* Align to actual cycle count for the last packet. */ | |
647 | cycle = decrement_cycle_count(cycle, packets); | |
648 | ||
a2064710 TS |
649 | /* For buffer-over-run prevention. */ |
650 | max_payload_quadlets = amdtp_stream_get_max_payload(s) / 4; | |
651 | ||
d9a16fc9 | 652 | for (i = 0; i < packets; i++) { |
f90e2ded | 653 | cycle = increment_cycle_count(cycle, 1); |
2b3fc456 TS |
654 | |
655 | /* The number of quadlets in this packet */ | |
656 | payload_quadlets = | |
d9a16fc9 | 657 | (be32_to_cpu(headers[i]) >> ISO_DATA_LENGTH_SHIFT) / 4; |
a2064710 TS |
658 | if (payload_quadlets > max_payload_quadlets) { |
659 | dev_err(&s->unit->device, | |
660 | "Detect jumbo payload: %02x %02x\n", | |
661 | payload_quadlets, max_payload_quadlets); | |
a2064710 TS |
662 | break; |
663 | } | |
664 | ||
a9c4284b | 665 | if (handle_in_packet(s, payload_quadlets, cycle, i) < 0) |
6fc6b9ce | 666 | break; |
2b3fc456 TS |
667 | } |
668 | ||
dec63cc8 | 669 | /* Queueing error or detecting invalid payload. */ |
d9a16fc9 | 670 | if (i < packets) { |
dec63cc8 | 671 | s->packet_index = -1; |
6fc6b9ce | 672 | amdtp_stream_pcm_abort(s); |
7b3b0d85 TS |
673 | return; |
674 | } | |
675 | ||
2b3fc456 TS |
676 | fw_iso_context_queue_flush(s->context); |
677 | } | |
678 | ||
7b3b0d85 TS |
679 | /* this is executed one time */ |
680 | static void amdtp_stream_first_callback(struct fw_iso_context *context, | |
73fc7f08 | 681 | u32 tstamp, size_t header_length, |
7b3b0d85 TS |
682 | void *header, void *private_data) |
683 | { | |
684 | struct amdtp_stream *s = private_data; | |
a04513f8 TS |
685 | u32 cycle; |
686 | unsigned int packets; | |
7b3b0d85 TS |
687 | |
688 | /* | |
689 | * For in-stream, first packet has come. | |
690 | * For out-stream, prepared to transmit first packet | |
691 | */ | |
692 | s->callbacked = true; | |
693 | wake_up(&s->callback_wait); | |
694 | ||
a04513f8 TS |
695 | cycle = compute_cycle_count(tstamp); |
696 | ||
697 | if (s->direction == AMDTP_IN_STREAM) { | |
698 | packets = header_length / IN_PACKET_HEADER_SIZE; | |
699 | cycle = decrement_cycle_count(cycle, packets); | |
7b3b0d85 | 700 | context->callback.sc = in_stream_callback; |
a04513f8 TS |
701 | } else { |
702 | packets = header_length / 4; | |
703 | cycle = increment_cycle_count(cycle, QUEUE_LENGTH - packets); | |
7b3b0d85 | 704 | context->callback.sc = out_stream_callback; |
a04513f8 TS |
705 | } |
706 | ||
707 | s->start_cycle = cycle; | |
7b3b0d85 | 708 | |
73fc7f08 | 709 | context->callback.sc(context, tstamp, header_length, header, s); |
7b3b0d85 TS |
710 | } |
711 | ||
31ef9134 | 712 | /** |
be4a2894 TS |
713 | * amdtp_stream_start - start transferring packets |
714 | * @s: the AMDTP stream to start | |
31ef9134 CL |
715 | * @channel: the isochronous channel on the bus |
716 | * @speed: firewire speed code | |
717 | * | |
718 | * The stream cannot be started until it has been configured with | |
be4a2894 TS |
719 | * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI |
720 | * device can be started. | |
31ef9134 | 721 | */ |
be4a2894 | 722 | int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed) |
31ef9134 CL |
723 | { |
724 | static const struct { | |
725 | unsigned int data_block; | |
726 | unsigned int syt_offset; | |
727 | } initial_state[] = { | |
728 | [CIP_SFC_32000] = { 4, 3072 }, | |
729 | [CIP_SFC_48000] = { 6, 1024 }, | |
730 | [CIP_SFC_96000] = { 12, 1024 }, | |
731 | [CIP_SFC_192000] = { 24, 1024 }, | |
732 | [CIP_SFC_44100] = { 0, 67 }, | |
733 | [CIP_SFC_88200] = { 0, 67 }, | |
734 | [CIP_SFC_176400] = { 0, 67 }, | |
735 | }; | |
2b3fc456 TS |
736 | unsigned int header_size; |
737 | enum dma_data_direction dir; | |
7ab56645 | 738 | int type, tag, err; |
31ef9134 CL |
739 | |
740 | mutex_lock(&s->mutex); | |
741 | ||
be4a2894 | 742 | if (WARN_ON(amdtp_stream_running(s) || |
4b7da117 | 743 | (s->data_block_quadlets < 1))) { |
31ef9134 CL |
744 | err = -EBADFD; |
745 | goto err_unlock; | |
746 | } | |
747 | ||
62f00e40 | 748 | if (s->direction == AMDTP_IN_STREAM) |
b6bc8123 TS |
749 | s->data_block_counter = UINT_MAX; |
750 | else | |
751 | s->data_block_counter = 0; | |
31ef9134 CL |
752 | s->data_block_state = initial_state[s->sfc].data_block; |
753 | s->syt_offset_state = initial_state[s->sfc].syt_offset; | |
754 | s->last_syt_offset = TICKS_PER_CYCLE; | |
755 | ||
2b3fc456 TS |
756 | /* initialize packet buffer */ |
757 | if (s->direction == AMDTP_IN_STREAM) { | |
758 | dir = DMA_FROM_DEVICE; | |
759 | type = FW_ISO_CONTEXT_RECEIVE; | |
760 | header_size = IN_PACKET_HEADER_SIZE; | |
2b3fc456 TS |
761 | } else { |
762 | dir = DMA_TO_DEVICE; | |
763 | type = FW_ISO_CONTEXT_TRANSMIT; | |
764 | header_size = OUT_PACKET_HEADER_SIZE; | |
2b3fc456 | 765 | } |
31ef9134 | 766 | err = iso_packets_buffer_init(&s->buffer, s->unit, QUEUE_LENGTH, |
2b3fc456 | 767 | amdtp_stream_get_max_payload(s), dir); |
31ef9134 CL |
768 | if (err < 0) |
769 | goto err_unlock; | |
770 | ||
771 | s->context = fw_iso_context_create(fw_parent_device(s->unit)->card, | |
2b3fc456 | 772 | type, channel, speed, header_size, |
7b3b0d85 | 773 | amdtp_stream_first_callback, s); |
31ef9134 CL |
774 | if (IS_ERR(s->context)) { |
775 | err = PTR_ERR(s->context); | |
776 | if (err == -EBUSY) | |
777 | dev_err(&s->unit->device, | |
be4a2894 | 778 | "no free stream on this controller\n"); |
31ef9134 CL |
779 | goto err_buffer; |
780 | } | |
781 | ||
be4a2894 | 782 | amdtp_stream_update(s); |
31ef9134 | 783 | |
ec00f5e4 | 784 | s->packet_index = 0; |
4b7da117 | 785 | do { |
2b3fc456 TS |
786 | if (s->direction == AMDTP_IN_STREAM) |
787 | err = queue_in_packet(s); | |
788 | else | |
ff38e0c7 | 789 | err = queue_out_packet(s, 0); |
4b7da117 TS |
790 | if (err < 0) |
791 | goto err_context; | |
792 | } while (s->packet_index > 0); | |
31ef9134 | 793 | |
2b3fc456 | 794 | /* NOTE: TAG1 matches CIP. This just affects in stream. */ |
7ab56645 TS |
795 | tag = FW_ISO_CONTEXT_MATCH_TAG1; |
796 | if (s->flags & CIP_EMPTY_WITH_TAG0) | |
797 | tag |= FW_ISO_CONTEXT_MATCH_TAG0; | |
798 | ||
7b3b0d85 | 799 | s->callbacked = false; |
7ab56645 | 800 | err = fw_iso_context_start(s->context, -1, 0, tag); |
31ef9134 CL |
801 | if (err < 0) |
802 | goto err_context; | |
803 | ||
804 | mutex_unlock(&s->mutex); | |
805 | ||
806 | return 0; | |
807 | ||
808 | err_context: | |
809 | fw_iso_context_destroy(s->context); | |
810 | s->context = ERR_PTR(-1); | |
811 | err_buffer: | |
812 | iso_packets_buffer_destroy(&s->buffer, s->unit); | |
813 | err_unlock: | |
814 | mutex_unlock(&s->mutex); | |
815 | ||
816 | return err; | |
817 | } | |
be4a2894 | 818 | EXPORT_SYMBOL(amdtp_stream_start); |
31ef9134 | 819 | |
e9148ddd | 820 | /** |
be4a2894 TS |
821 | * amdtp_stream_pcm_pointer - get the PCM buffer position |
822 | * @s: the AMDTP stream that transports the PCM data | |
e9148ddd CL |
823 | * |
824 | * Returns the current buffer position, in frames. | |
825 | */ | |
be4a2894 | 826 | unsigned long amdtp_stream_pcm_pointer(struct amdtp_stream *s) |
e9148ddd | 827 | { |
1dba9db0 TS |
828 | /* |
829 | * This function is called in software IRQ context of period_tasklet or | |
830 | * process context. | |
831 | * | |
832 | * When the software IRQ context was scheduled by software IRQ context | |
833 | * of IR/IT contexts, queued packets were already handled. Therefore, | |
834 | * no need to flush the queue in buffer anymore. | |
835 | * | |
836 | * When the process context reach here, some packets will be already | |
837 | * queued in the buffer. These packets should be handled immediately | |
838 | * to keep better granularity of PCM pointer. | |
839 | * | |
840 | * Later, the process context will sometimes schedules software IRQ | |
841 | * context of the period_tasklet. Then, no need to flush the queue by | |
842 | * the same reason as described for IR/IT contexts. | |
843 | */ | |
844 | if (!in_interrupt() && amdtp_stream_running(s)) | |
92b862c7 | 845 | fw_iso_context_flush_completions(s->context); |
e9148ddd CL |
846 | |
847 | return ACCESS_ONCE(s->pcm_buffer_pointer); | |
848 | } | |
be4a2894 | 849 | EXPORT_SYMBOL(amdtp_stream_pcm_pointer); |
e9148ddd | 850 | |
31ef9134 | 851 | /** |
be4a2894 TS |
852 | * amdtp_stream_update - update the stream after a bus reset |
853 | * @s: the AMDTP stream | |
31ef9134 | 854 | */ |
be4a2894 | 855 | void amdtp_stream_update(struct amdtp_stream *s) |
31ef9134 | 856 | { |
9a2820c1 | 857 | /* Precomputing. */ |
31ef9134 | 858 | ACCESS_ONCE(s->source_node_id_field) = |
9a2820c1 TS |
859 | (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & |
860 | CIP_SID_MASK; | |
31ef9134 | 861 | } |
be4a2894 | 862 | EXPORT_SYMBOL(amdtp_stream_update); |
31ef9134 CL |
863 | |
864 | /** | |
be4a2894 TS |
865 | * amdtp_stream_stop - stop sending packets |
866 | * @s: the AMDTP stream to stop | |
31ef9134 CL |
867 | * |
868 | * All PCM and MIDI devices of the stream must be stopped before the stream | |
869 | * itself can be stopped. | |
870 | */ | |
be4a2894 | 871 | void amdtp_stream_stop(struct amdtp_stream *s) |
31ef9134 CL |
872 | { |
873 | mutex_lock(&s->mutex); | |
874 | ||
be4a2894 | 875 | if (!amdtp_stream_running(s)) { |
31ef9134 CL |
876 | mutex_unlock(&s->mutex); |
877 | return; | |
878 | } | |
879 | ||
76fb8789 | 880 | tasklet_kill(&s->period_tasklet); |
31ef9134 CL |
881 | fw_iso_context_stop(s->context); |
882 | fw_iso_context_destroy(s->context); | |
883 | s->context = ERR_PTR(-1); | |
884 | iso_packets_buffer_destroy(&s->buffer, s->unit); | |
885 | ||
7b3b0d85 TS |
886 | s->callbacked = false; |
887 | ||
31ef9134 CL |
888 | mutex_unlock(&s->mutex); |
889 | } | |
be4a2894 | 890 | EXPORT_SYMBOL(amdtp_stream_stop); |
31ef9134 CL |
891 | |
892 | /** | |
be4a2894 | 893 | * amdtp_stream_pcm_abort - abort the running PCM device |
31ef9134 CL |
894 | * @s: the AMDTP stream about to be stopped |
895 | * | |
896 | * If the isochronous stream needs to be stopped asynchronously, call this | |
897 | * function first to stop the PCM device. | |
898 | */ | |
be4a2894 | 899 | void amdtp_stream_pcm_abort(struct amdtp_stream *s) |
31ef9134 CL |
900 | { |
901 | struct snd_pcm_substream *pcm; | |
902 | ||
903 | pcm = ACCESS_ONCE(s->pcm); | |
1fb8510c TI |
904 | if (pcm) |
905 | snd_pcm_stop_xrun(pcm); | |
31ef9134 | 906 | } |
be4a2894 | 907 | EXPORT_SYMBOL(amdtp_stream_pcm_abort); |