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da607e19 1// SPDX-License-Identifier: GPL-2.0-only
31ef9134
CL
2/*
3 * Audio and Music Data Transmission Protocol (IEC 61883-6) streams
4 * with Common Isochronous Packet (IEC 61883-1) headers
5 *
6 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
31ef9134
CL
7 */
8
9#include <linux/device.h>
10#include <linux/err.h>
11#include <linux/firewire.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <sound/pcm.h>
7b2d99fa 15#include <sound/pcm_params.h>
d67c46b9 16#include "amdtp-stream.h"
31ef9134
CL
17
18#define TICKS_PER_CYCLE 3072
19#define CYCLES_PER_SECOND 8000
20#define TICKS_PER_SECOND (TICKS_PER_CYCLE * CYCLES_PER_SECOND)
21
0c95c1d6
TS
22/* Always support Linux tracing subsystem. */
23#define CREATE_TRACE_POINTS
24#include "amdtp-stream-trace.h"
25
ca5b5050 26#define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 microseconds */
31ef9134 27
b445db44
TS
28/* isochronous header parameters */
29#define ISO_DATA_LENGTH_SHIFT 16
3b196c39 30#define TAG_NO_CIP_HEADER 0
31ef9134
CL
31#define TAG_CIP 1
32
b445db44 33/* common isochronous packet header parameters */
9a2820c1
TS
34#define CIP_EOH_SHIFT 31
35#define CIP_EOH (1u << CIP_EOH_SHIFT)
b445db44 36#define CIP_EOH_MASK 0x80000000
9a2820c1
TS
37#define CIP_SID_SHIFT 24
38#define CIP_SID_MASK 0x3f000000
39#define CIP_DBS_MASK 0x00ff0000
40#define CIP_DBS_SHIFT 16
9863874f
TS
41#define CIP_SPH_MASK 0x00000400
42#define CIP_SPH_SHIFT 10
9a2820c1
TS
43#define CIP_DBC_MASK 0x000000ff
44#define CIP_FMT_SHIFT 24
b445db44 45#define CIP_FMT_MASK 0x3f000000
9a2820c1
TS
46#define CIP_FDF_MASK 0x00ff0000
47#define CIP_FDF_SHIFT 16
b445db44
TS
48#define CIP_SYT_MASK 0x0000ffff
49#define CIP_SYT_NO_INFO 0xffff
b445db44 50
51c29fd2 51/* Audio and Music transfer protocol specific parameters */
414ba022 52#define CIP_FMT_AM 0x10
2b3fc456 53#define AMDTP_FDF_NO_DATA 0xff
31ef9134
CL
54
55/* TODO: make these configurable */
56#define INTERRUPT_INTERVAL 16
57#define QUEUE_LENGTH 48
58
f11453c7
TS
59// For iso header, tstamp and 2 CIP header.
60#define IR_CTX_HEADER_SIZE_CIP 16
61// For iso header and tstamp.
62#define IR_CTX_HEADER_SIZE_NO_CIP 8
cc4f8e91 63#define HEADER_TSTAMP_MASK 0x0000ffff
4b7da117 64
b18f0cfa
TS
65#define IT_PKT_HEADER_SIZE_CIP 8 // For 2 CIP header.
66#define IT_PKT_HEADER_SIZE_NO_CIP 0 // Nothing.
67
76fb8789
CL
68static void pcm_period_tasklet(unsigned long data);
69
31ef9134 70/**
be4a2894
TS
71 * amdtp_stream_init - initialize an AMDTP stream structure
72 * @s: the AMDTP stream to initialize
31ef9134 73 * @unit: the target of the stream
3ff7e8f0 74 * @dir: the direction of stream
31ef9134 75 * @flags: the packet transmission method to use
5955815e 76 * @fmt: the value of fmt field in CIP header
9a738ad1 77 * @process_ctx_payloads: callback handler to process payloads of isoc context
df075fee 78 * @protocol_size: the size to allocate newly for protocol
31ef9134 79 */
be4a2894 80int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit,
5955815e 81 enum amdtp_stream_direction dir, enum cip_flags flags,
df075fee 82 unsigned int fmt,
9a738ad1 83 amdtp_stream_process_ctx_payloads_t process_ctx_payloads,
df075fee 84 unsigned int protocol_size)
31ef9134 85{
9a738ad1 86 if (process_ctx_payloads == NULL)
df075fee
TS
87 return -EINVAL;
88
89 s->protocol = kzalloc(protocol_size, GFP_KERNEL);
90 if (!s->protocol)
91 return -ENOMEM;
92
c6f224dc 93 s->unit = unit;
3ff7e8f0 94 s->direction = dir;
31ef9134
CL
95 s->flags = flags;
96 s->context = ERR_PTR(-1);
97 mutex_init(&s->mutex);
76fb8789 98 tasklet_init(&s->period_tasklet, pcm_period_tasklet, (unsigned long)s);
ec00f5e4 99 s->packet_index = 0;
31ef9134 100
7b3b0d85
TS
101 init_waitqueue_head(&s->callback_wait);
102 s->callbacked = false;
7b3b0d85 103
5955815e 104 s->fmt = fmt;
9a738ad1 105 s->process_ctx_payloads = process_ctx_payloads;
414ba022 106
3baf3053
TS
107 if (dir == AMDTP_OUT_STREAM)
108 s->ctx_data.rx.syt_override = -1;
109
31ef9134
CL
110 return 0;
111}
be4a2894 112EXPORT_SYMBOL(amdtp_stream_init);
31ef9134
CL
113
114/**
be4a2894
TS
115 * amdtp_stream_destroy - free stream resources
116 * @s: the AMDTP stream to destroy
31ef9134 117 */
be4a2894 118void amdtp_stream_destroy(struct amdtp_stream *s)
31ef9134 119{
44c376b9
TS
120 /* Not initialized. */
121 if (s->protocol == NULL)
122 return;
123
be4a2894 124 WARN_ON(amdtp_stream_running(s));
df075fee 125 kfree(s->protocol);
31ef9134 126 mutex_destroy(&s->mutex);
31ef9134 127}
be4a2894 128EXPORT_SYMBOL(amdtp_stream_destroy);
31ef9134 129
c5280e99 130const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = {
a7304e3b
CL
131 [CIP_SFC_32000] = 8,
132 [CIP_SFC_44100] = 8,
133 [CIP_SFC_48000] = 8,
134 [CIP_SFC_88200] = 16,
135 [CIP_SFC_96000] = 16,
136 [CIP_SFC_176400] = 32,
137 [CIP_SFC_192000] = 32,
138};
139EXPORT_SYMBOL(amdtp_syt_intervals);
140
f9503a68 141const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = {
1017abed
TS
142 [CIP_SFC_32000] = 32000,
143 [CIP_SFC_44100] = 44100,
144 [CIP_SFC_48000] = 48000,
145 [CIP_SFC_88200] = 88200,
146 [CIP_SFC_96000] = 96000,
147 [CIP_SFC_176400] = 176400,
148 [CIP_SFC_192000] = 192000,
149};
150EXPORT_SYMBOL(amdtp_rate_table);
151
59502295
TS
152static int apply_constraint_to_size(struct snd_pcm_hw_params *params,
153 struct snd_pcm_hw_rule *rule)
154{
155 struct snd_interval *s = hw_param_interval(params, rule->var);
156 const struct snd_interval *r =
157 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
826b5de9
TS
158 struct snd_interval t = {0};
159 unsigned int step = 0;
59502295
TS
160 int i;
161
162 for (i = 0; i < CIP_SFC_COUNT; ++i) {
826b5de9
TS
163 if (snd_interval_test(r, amdtp_rate_table[i]))
164 step = max(step, amdtp_syt_intervals[i]);
59502295
TS
165 }
166
826b5de9
TS
167 t.min = roundup(s->min, step);
168 t.max = rounddown(s->max, step);
169 t.integer = 1;
59502295
TS
170
171 return snd_interval_refine(s, &t);
172}
173
7b2d99fa
TS
174/**
175 * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream
176 * @s: the AMDTP stream, which must be initialized.
177 * @runtime: the PCM substream runtime
178 */
179int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s,
180 struct snd_pcm_runtime *runtime)
181{
55799c5a 182 struct snd_pcm_hardware *hw = &runtime->hw;
7b2d99fa
TS
183 int err;
184
55799c5a
TS
185 hw->info = SNDRV_PCM_INFO_BATCH |
186 SNDRV_PCM_INFO_BLOCK_TRANSFER |
187 SNDRV_PCM_INFO_INTERLEAVED |
188 SNDRV_PCM_INFO_JOINT_DUPLEX |
189 SNDRV_PCM_INFO_MMAP |
190 SNDRV_PCM_INFO_MMAP_VALID;
191
192 /* SNDRV_PCM_INFO_BATCH */
193 hw->periods_min = 2;
194 hw->periods_max = UINT_MAX;
195
196 /* bytes for a frame */
197 hw->period_bytes_min = 4 * hw->channels_max;
198
199 /* Just to prevent from allocating much pages. */
200 hw->period_bytes_max = hw->period_bytes_min * 2048;
201 hw->buffer_bytes_max = hw->period_bytes_max * hw->periods_min;
202
7b2d99fa
TS
203 /*
204 * Currently firewire-lib processes 16 packets in one software
205 * interrupt callback. This equals to 2msec but actually the
206 * interval of the interrupts has a jitter.
207 * Additionally, even if adding a constraint to fit period size to
208 * 2msec, actual calculated frames per period doesn't equal to 2msec,
209 * depending on sampling rate.
210 * Anyway, the interval to call snd_pcm_period_elapsed() cannot 2msec.
211 * Here let us use 5msec for safe period interrupt.
212 */
213 err = snd_pcm_hw_constraint_minmax(runtime,
214 SNDRV_PCM_HW_PARAM_PERIOD_TIME,
215 5000, UINT_MAX);
216 if (err < 0)
217 goto end;
218
219 /* Non-Blocking stream has no more constraints */
220 if (!(s->flags & CIP_BLOCKING))
221 goto end;
222
223 /*
224 * One AMDTP packet can include some frames. In blocking mode, the
225 * number equals to SYT_INTERVAL. So the number is 8, 16 or 32,
226 * depending on its sampling rate. For accurate period interrupt, it's
ce991981 227 * preferrable to align period/buffer sizes to current SYT_INTERVAL.
7b2d99fa 228 */
59502295
TS
229 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
230 apply_constraint_to_size, NULL,
826b5de9 231 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
59502295
TS
232 SNDRV_PCM_HW_PARAM_RATE, -1);
233 if (err < 0)
234 goto end;
59502295
TS
235 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
236 apply_constraint_to_size, NULL,
826b5de9 237 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
59502295
TS
238 SNDRV_PCM_HW_PARAM_RATE, -1);
239 if (err < 0)
240 goto end;
7b2d99fa
TS
241end:
242 return err;
243}
244EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints);
245
31ef9134 246/**
be4a2894
TS
247 * amdtp_stream_set_parameters - set stream parameters
248 * @s: the AMDTP stream to configure
31ef9134 249 * @rate: the sample rate
df075fee 250 * @data_block_quadlets: the size of a data block in quadlet unit
31ef9134 251 *
a7304e3b 252 * The parameters must be set before the stream is started, and must not be
31ef9134
CL
253 * changed while the stream is running.
254 */
df075fee
TS
255int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate,
256 unsigned int data_block_quadlets)
31ef9134 257{
df075fee 258 unsigned int sfc;
31ef9134 259
547e631c 260 for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) {
1017abed 261 if (amdtp_rate_table[sfc] == rate)
547e631c
TS
262 break;
263 }
264 if (sfc == ARRAY_SIZE(amdtp_rate_table))
265 return -EINVAL;
e84d15f6 266
e84d15f6 267 s->sfc = sfc;
df075fee 268 s->data_block_quadlets = data_block_quadlets;
a7304e3b 269 s->syt_interval = amdtp_syt_intervals[sfc];
e84d15f6 270
d3d10a4a
TS
271 // default buffering in the device.
272 if (s->direction == AMDTP_OUT_STREAM) {
273 s->ctx_data.rx.transfer_delay =
274 TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE;
275
276 if (s->flags & CIP_BLOCKING) {
277 // additional buffering needed to adjust for no-data
278 // packets.
279 s->ctx_data.rx.transfer_delay +=
280 TICKS_PER_SECOND * s->syt_interval / rate;
281 }
282 }
77d2a8a4 283
547e631c 284 return 0;
31ef9134 285}
be4a2894 286EXPORT_SYMBOL(amdtp_stream_set_parameters);
31ef9134
CL
287
288/**
be4a2894
TS
289 * amdtp_stream_get_max_payload - get the stream's packet size
290 * @s: the AMDTP stream
31ef9134
CL
291 *
292 * This function must not be called before the stream has been configured
be4a2894 293 * with amdtp_stream_set_parameters().
31ef9134 294 */
be4a2894 295unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s)
31ef9134 296{
a2064710 297 unsigned int multiplier = 1;
07ea238c 298 unsigned int cip_header_size = 0;
a2064710
TS
299
300 if (s->flags & CIP_JUMBO_PAYLOAD)
301 multiplier = 5;
3b196c39 302 if (!(s->flags & CIP_NO_HEADER))
07ea238c 303 cip_header_size = sizeof(__be32) * 2;
a2064710 304
07ea238c
TS
305 return cip_header_size +
306 s->syt_interval * s->data_block_quadlets * sizeof(__be32) * multiplier;
31ef9134 307}
be4a2894 308EXPORT_SYMBOL(amdtp_stream_get_max_payload);
31ef9134 309
76fb8789 310/**
be4a2894
TS
311 * amdtp_stream_pcm_prepare - prepare PCM device for running
312 * @s: the AMDTP stream
76fb8789
CL
313 *
314 * This function should be called from the PCM device's .prepare callback.
315 */
be4a2894 316void amdtp_stream_pcm_prepare(struct amdtp_stream *s)
76fb8789
CL
317{
318 tasklet_kill(&s->period_tasklet);
319 s->pcm_buffer_pointer = 0;
320 s->pcm_period_pointer = 0;
321}
be4a2894 322EXPORT_SYMBOL(amdtp_stream_pcm_prepare);
76fb8789 323
875be091
TS
324static unsigned int calculate_data_blocks(struct amdtp_stream *s,
325 unsigned int syt)
31ef9134
CL
326{
327 unsigned int phase, data_blocks;
328
875be091
TS
329 /* Blocking mode. */
330 if (s->flags & CIP_BLOCKING) {
331 /* This module generate empty packet for 'no data'. */
332 if (syt == CIP_SYT_NO_INFO)
333 data_blocks = 0;
334 else
335 data_blocks = s->syt_interval;
336 /* Non-blocking mode. */
31ef9134 337 } else {
875be091 338 if (!cip_sfc_is_base_44100(s->sfc)) {
d3d10a4a
TS
339 // Sample_rate / 8000 is an integer, and precomputed.
340 data_blocks = s->ctx_data.rx.data_block_state;
875be091 341 } else {
d3d10a4a 342 phase = s->ctx_data.rx.data_block_state;
31ef9134
CL
343
344 /*
345 * This calculates the number of data blocks per packet so that
346 * 1) the overall rate is correct and exactly synchronized to
347 * the bus clock, and
348 * 2) packets with a rounded-up number of blocks occur as early
349 * as possible in the sequence (to prevent underruns of the
350 * device's buffer).
351 */
875be091
TS
352 if (s->sfc == CIP_SFC_44100)
353 /* 6 6 5 6 5 6 5 ... */
354 data_blocks = 5 + ((phase & 1) ^
355 (phase == 0 || phase >= 40));
356 else
357 /* 12 11 11 11 11 ... or 23 22 22 22 22 ... */
358 data_blocks = 11 * (s->sfc >> 1) + (phase == 0);
359 if (++phase >= (80 >> (s->sfc >> 1)))
360 phase = 0;
d3d10a4a 361 s->ctx_data.rx.data_block_state = phase;
875be091 362 }
31ef9134
CL
363 }
364
365 return data_blocks;
366}
367
be4a2894 368static unsigned int calculate_syt(struct amdtp_stream *s,
31ef9134
CL
369 unsigned int cycle)
370{
371 unsigned int syt_offset, phase, index, syt;
372
d3d10a4a 373 if (s->ctx_data.rx.last_syt_offset < TICKS_PER_CYCLE) {
31ef9134 374 if (!cip_sfc_is_base_44100(s->sfc))
d3d10a4a
TS
375 syt_offset = s->ctx_data.rx.last_syt_offset +
376 s->ctx_data.rx.syt_offset_state;
31ef9134
CL
377 else {
378 /*
379 * The time, in ticks, of the n'th SYT_INTERVAL sample is:
380 * n * SYT_INTERVAL * 24576000 / sample_rate
381 * Modulo TICKS_PER_CYCLE, the difference between successive
382 * elements is about 1386.23. Rounding the results of this
383 * formula to the SYT precision results in a sequence of
384 * differences that begins with:
385 * 1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ...
386 * This code generates _exactly_ the same sequence.
387 */
d3d10a4a 388 phase = s->ctx_data.rx.syt_offset_state;
31ef9134 389 index = phase % 13;
d3d10a4a 390 syt_offset = s->ctx_data.rx.last_syt_offset;
31ef9134
CL
391 syt_offset += 1386 + ((index && !(index & 3)) ||
392 phase == 146);
393 if (++phase >= 147)
394 phase = 0;
d3d10a4a 395 s->ctx_data.rx.syt_offset_state = phase;
31ef9134
CL
396 }
397 } else
d3d10a4a
TS
398 syt_offset = s->ctx_data.rx.last_syt_offset - TICKS_PER_CYCLE;
399 s->ctx_data.rx.last_syt_offset = syt_offset;
31ef9134 400
be454366 401 if (syt_offset < TICKS_PER_CYCLE) {
d3d10a4a 402 syt_offset += s->ctx_data.rx.transfer_delay;
be454366
CL
403 syt = (cycle + syt_offset / TICKS_PER_CYCLE) << 12;
404 syt += syt_offset % TICKS_PER_CYCLE;
31ef9134 405
b445db44 406 return syt & CIP_SYT_MASK;
be454366 407 } else {
b445db44 408 return CIP_SYT_NO_INFO;
be454366 409 }
31ef9134
CL
410}
411
4b7da117
TS
412static void update_pcm_pointers(struct amdtp_stream *s,
413 struct snd_pcm_substream *pcm,
414 unsigned int frames)
65845f29
TS
415{
416 unsigned int ptr;
417
4b7da117
TS
418 ptr = s->pcm_buffer_pointer + frames;
419 if (ptr >= pcm->runtime->buffer_size)
420 ptr -= pcm->runtime->buffer_size;
6aa7de05 421 WRITE_ONCE(s->pcm_buffer_pointer, ptr);
4b7da117
TS
422
423 s->pcm_period_pointer += frames;
424 if (s->pcm_period_pointer >= pcm->runtime->period_size) {
425 s->pcm_period_pointer -= pcm->runtime->period_size;
4b7da117
TS
426 tasklet_hi_schedule(&s->period_tasklet);
427 }
428}
429
430static void pcm_period_tasklet(unsigned long data)
431{
432 struct amdtp_stream *s = (void *)data;
6aa7de05 433 struct snd_pcm_substream *pcm = READ_ONCE(s->pcm);
4b7da117
TS
434
435 if (pcm)
436 snd_pcm_period_elapsed(pcm);
437}
438
6007bf54 439static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params)
4b7da117 440{
6007bf54 441 int err;
df9160b9 442
6007bf54
TS
443 params->interrupt = IS_ALIGNED(s->packet_index + 1, INTERRUPT_INTERVAL);
444 params->tag = s->tag;
445 params->sy = 0;
df9160b9 446
6007bf54 447 err = fw_iso_context_queue(s->context, params, &s->buffer.iso_buffer,
4b7da117
TS
448 s->buffer.packets[s->packet_index].offset);
449 if (err < 0) {
450 dev_err(&s->unit->device, "queueing error: %d\n", err);
451 goto end;
452 }
453
454 if (++s->packet_index >= QUEUE_LENGTH)
455 s->packet_index = 0;
456end:
457 return err;
458}
459
460static inline int queue_out_packet(struct amdtp_stream *s,
b18f0cfa 461 struct fw_iso_packet *params)
4b7da117 462{
b18f0cfa
TS
463 params->skip =
464 !!(params->header_length == 0 && params->payload_length == 0);
6007bf54 465 return queue_packet(s, params);
4b7da117
TS
466}
467
6007bf54
TS
468static inline int queue_in_packet(struct amdtp_stream *s,
469 struct fw_iso_packet *params)
2b3fc456 470{
6007bf54
TS
471 // Queue one packet for IR context.
472 params->header_length = s->ctx_data.tx.ctx_header_size;
473 params->payload_length = s->ctx_data.tx.max_ctx_payload_length;
474 params->skip = false;
475 return queue_packet(s, params);
2b3fc456
TS
476}
477
252219c7 478static void generate_cip_header(struct amdtp_stream *s, __be32 cip_header[2],
860d798c 479 unsigned int data_block_counter, unsigned int syt)
252219c7
TS
480{
481 cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) |
482 (s->data_block_quadlets << CIP_DBS_SHIFT) |
483 ((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) |
860d798c 484 data_block_counter);
252219c7
TS
485 cip_header[1] = cpu_to_be32(CIP_EOH |
486 ((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) |
487 ((s->ctx_data.rx.fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) |
488 (syt & CIP_SYT_MASK));
489}
490
6bc1a269
TS
491static void build_it_pkt_header(struct amdtp_stream *s, unsigned int cycle,
492 struct fw_iso_packet *params,
860d798c
TS
493 unsigned int data_blocks,
494 unsigned int data_block_counter,
495 unsigned int syt, unsigned int index)
31ef9134 496{
0ebf3ceb 497 unsigned int payload_length;
16be4589 498 __be32 *cip_header;
20e44577 499
0ebf3ceb
TS
500 payload_length = data_blocks * sizeof(__be32) * s->data_block_quadlets;
501 params->payload_length = payload_length;
502
b18f0cfa 503 if (!(s->flags & CIP_NO_HEADER)) {
6bc1a269 504 cip_header = (__be32 *)params->header;
860d798c 505 generate_cip_header(s, cip_header, data_block_counter, syt);
6bc1a269 506 params->header_length = 2 * sizeof(__be32);
0ebf3ceb 507 payload_length += params->header_length;
b18f0cfa
TS
508 } else {
509 cip_header = NULL;
510 }
31ef9134 511
213fa989 512 trace_amdtp_packet(s, cycle, cip_header, payload_length, data_blocks,
860d798c 513 data_block_counter, index);
3b196c39
TS
514}
515
e335425b
TS
516static int check_cip_header(struct amdtp_stream *s, const __be32 *buf,
517 unsigned int payload_length,
a35463d1
TS
518 unsigned int *data_blocks,
519 unsigned int *data_block_counter, unsigned int *syt)
2b3fc456
TS
520{
521 u32 cip_header[2];
e335425b
TS
522 unsigned int sph;
523 unsigned int fmt;
524 unsigned int fdf;
a35463d1 525 unsigned int dbc;
c8bdf49b 526 bool lost;
2b3fc456 527
e335425b
TS
528 cip_header[0] = be32_to_cpu(buf[0]);
529 cip_header[1] = be32_to_cpu(buf[1]);
2b3fc456
TS
530
531 /*
532 * This module supports 'Two-quadlet CIP header with SYT field'.
77d2a8a4 533 * For convenience, also check FMT field is AM824 or not.
2b3fc456 534 */
2128f78f
TS
535 if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) ||
536 ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) &&
537 (!(s->flags & CIP_HEADER_WITHOUT_EOH))) {
2b3fc456
TS
538 dev_info_ratelimited(&s->unit->device,
539 "Invalid CIP header for AMDTP: %08X:%08X\n",
540 cip_header[0], cip_header[1]);
e335425b 541 return -EAGAIN;
2b3fc456
TS
542 }
543
414ba022 544 /* Check valid protocol or not. */
9863874f 545 sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT;
414ba022 546 fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT;
9863874f 547 if (sph != s->sph || fmt != s->fmt) {
2a7e1713
TS
548 dev_info_ratelimited(&s->unit->device,
549 "Detect unexpected protocol: %08x %08x\n",
550 cip_header[0], cip_header[1]);
e335425b 551 return -EAGAIN;
414ba022
TS
552 }
553
2b3fc456 554 /* Calculate data blocks */
414ba022 555 fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT;
e335425b 556 if (payload_length < sizeof(__be32) * 2 ||
414ba022 557 (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) {
e335425b 558 *data_blocks = 0;
2b3fc456 559 } else {
e335425b
TS
560 unsigned int data_block_quadlets =
561 (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT;
2b3fc456
TS
562 /* avoid division by zero */
563 if (data_block_quadlets == 0) {
12e0f438 564 dev_err(&s->unit->device,
2b3fc456
TS
565 "Detect invalid value in dbs field: %08X\n",
566 cip_header[0]);
a9007054 567 return -EPROTO;
2b3fc456 568 }
69702239
TS
569 if (s->flags & CIP_WRONG_DBS)
570 data_block_quadlets = s->data_block_quadlets;
2b3fc456 571
e335425b 572 *data_blocks = (payload_length / sizeof(__be32) - 2) /
ff0fb5aa 573 data_block_quadlets;
2b3fc456
TS
574 }
575
576 /* Check data block counter continuity */
a35463d1 577 dbc = cip_header[0] & CIP_DBC_MASK;
e335425b 578 if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) &&
a35463d1
TS
579 *data_block_counter != UINT_MAX)
580 dbc = *data_block_counter;
9d59124c 581
a35463d1
TS
582 if ((dbc == 0x00 && (s->flags & CIP_SKIP_DBC_ZERO_CHECK)) ||
583 *data_block_counter == UINT_MAX) {
b84b1a27
TS
584 lost = false;
585 } else if (!(s->flags & CIP_DBC_IS_END_EVENT)) {
a35463d1 586 lost = dbc != *data_block_counter;
d9cd0065 587 } else {
e335425b
TS
588 unsigned int dbc_interval;
589
590 if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0)
d3d10a4a 591 dbc_interval = s->ctx_data.tx.dbc_interval;
d9cd0065 592 else
e335425b 593 dbc_interval = *data_blocks;
d9cd0065 594
a35463d1 595 lost = dbc != ((*data_block_counter + dbc_interval) & 0xff);
d9cd0065 596 }
c8bdf49b
TS
597
598 if (lost) {
12e0f438
TS
599 dev_err(&s->unit->device,
600 "Detect discontinuity of CIP: %02X %02X\n",
a35463d1 601 *data_block_counter, dbc);
6fc6b9ce 602 return -EIO;
2b3fc456
TS
603 }
604
753e7179
TS
605 *data_block_counter = dbc;
606
e335425b 607 *syt = cip_header[1] & CIP_SYT_MASK;
2b3fc456 608
e335425b
TS
609 return 0;
610}
611
98e3e43b
TS
612static int parse_ir_ctx_header(struct amdtp_stream *s, unsigned int cycle,
613 const __be32 *ctx_header,
614 unsigned int *payload_length,
a35463d1
TS
615 unsigned int *data_blocks,
616 unsigned int *data_block_counter,
617 unsigned int *syt, unsigned int index)
e335425b 618{
f11453c7 619 const __be32 *cip_header;
93fca2e5 620 unsigned int cip_header_size;
e335425b
TS
621 int err;
622
98e3e43b 623 *payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT;
93fca2e5
TS
624
625 if (!(s->flags & CIP_NO_HEADER))
626 cip_header_size = 8;
627 else
628 cip_header_size = 0;
629
630 if (*payload_length > cip_header_size + s->ctx_data.tx.max_ctx_payload_length) {
e335425b
TS
631 dev_err(&s->unit->device,
632 "Detect jumbo payload: %04x %04x\n",
93fca2e5 633 *payload_length, cip_header_size + s->ctx_data.tx.max_ctx_payload_length);
e335425b
TS
634 return -EIO;
635 }
636
93fca2e5 637 if (cip_header_size > 0) {
98e3e43b
TS
638 cip_header = ctx_header + 2;
639 err = check_cip_header(s, cip_header, *payload_length,
a35463d1 640 data_blocks, data_block_counter, syt);
b8b0e24c
TS
641 if (err < 0)
642 return err;
947b437e
TS
643 } else {
644 cip_header = NULL;
76864868 645 err = 0;
98e3e43b
TS
646 *data_blocks = *payload_length / sizeof(__be32) /
647 s->data_block_quadlets;
648 *syt = 0;
7fbf9096 649
a35463d1
TS
650 if (*data_block_counter == UINT_MAX)
651 *data_block_counter = 0;
e335425b
TS
652 }
653
98e3e43b 654 trace_amdtp_packet(s, cycle, cip_header, *payload_length, *data_blocks,
a35463d1 655 *data_block_counter, index);
e335425b 656
76864868 657 return err;
2b3fc456
TS
658}
659
26cd1e58
TS
660// In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On
661// the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent
662// it. Thus, via Linux firewire subsystem, we can get the 3 bits for second.
663static inline u32 compute_cycle_count(__be32 ctx_header_tstamp)
73fc7f08 664{
26cd1e58 665 u32 tstamp = be32_to_cpu(ctx_header_tstamp) & HEADER_TSTAMP_MASK;
73fc7f08
TS
666 return (((tstamp >> 13) & 0x07) * 8000) + (tstamp & 0x1fff);
667}
668
669static inline u32 increment_cycle_count(u32 cycle, unsigned int addend)
670{
671 cycle += addend;
672 if (cycle >= 8 * CYCLES_PER_SECOND)
673 cycle -= 8 * CYCLES_PER_SECOND;
674 return cycle;
675}
676
26cd1e58
TS
677// Align to actual cycle count for the packet which is going to be scheduled.
678// This module queued the same number of isochronous cycle as QUEUE_LENGTH to
679// skip isochronous cycle, therefore it's OK to just increment the cycle by
680// QUEUE_LENGTH for scheduled cycle.
681static inline u32 compute_it_cycle(const __be32 ctx_header_tstamp)
682{
683 u32 cycle = compute_cycle_count(ctx_header_tstamp);
684 return increment_cycle_count(cycle, QUEUE_LENGTH);
685}
686
753e7179
TS
687static int generate_device_pkt_descs(struct amdtp_stream *s,
688 struct pkt_desc *descs,
689 const __be32 *ctx_header,
690 unsigned int packets)
691{
692 unsigned int dbc = s->data_block_counter;
693 int i;
694 int err;
695
696 for (i = 0; i < packets; ++i) {
697 struct pkt_desc *desc = descs + i;
698 unsigned int index = (s->packet_index + i) % QUEUE_LENGTH;
699 unsigned int cycle;
700 unsigned int payload_length;
701 unsigned int data_blocks;
702 unsigned int syt;
703
704 cycle = compute_cycle_count(ctx_header[1]);
705
706 err = parse_ir_ctx_header(s, cycle, ctx_header, &payload_length,
707 &data_blocks, &dbc, &syt, i);
708 if (err < 0)
709 return err;
710
711 desc->cycle = cycle;
712 desc->syt = syt;
713 desc->data_blocks = data_blocks;
714 desc->data_block_counter = dbc;
715 desc->ctx_payload = s->buffer.packets[index].buffer;
716
717 if (!(s->flags & CIP_DBC_IS_END_EVENT))
718 dbc = (dbc + desc->data_blocks) & 0xff;
719
720 ctx_header +=
721 s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header);
722 }
723
724 s->data_block_counter = dbc;
725
726 return 0;
727}
728
f4f6ae7b
TS
729static void generate_ideal_pkt_descs(struct amdtp_stream *s,
730 struct pkt_desc *descs,
731 const __be32 *ctx_header,
732 unsigned int packets)
733{
734 unsigned int dbc = s->data_block_counter;
735 int i;
736
737 for (i = 0; i < packets; ++i) {
738 struct pkt_desc *desc = descs + i;
739 unsigned int index = (s->packet_index + i) % QUEUE_LENGTH;
740
f155e79a 741 desc->cycle = compute_it_cycle(*ctx_header);
f4f6ae7b
TS
742 desc->syt = calculate_syt(s, desc->cycle);
743 desc->data_blocks = calculate_data_blocks(s, desc->syt);
744
745 if (s->flags & CIP_DBC_IS_END_EVENT)
746 dbc = (dbc + desc->data_blocks) & 0xff;
747
748 desc->data_block_counter = dbc;
749
750 if (!(s->flags & CIP_DBC_IS_END_EVENT))
751 dbc = (dbc + desc->data_blocks) & 0xff;
752
753 desc->ctx_payload = s->buffer.packets[index].buffer;
754
755 ++ctx_header;
756 }
757
758 s->data_block_counter = dbc;
759}
760
fce9b013
TS
761static inline void cancel_stream(struct amdtp_stream *s)
762{
763 s->packet_index = -1;
764 if (in_interrupt())
765 amdtp_stream_pcm_abort(s);
766 WRITE_ONCE(s->pcm_buffer_pointer, SNDRV_PCM_POS_XRUN);
767}
768
0f5cfcb2
TS
769static void process_ctx_payloads(struct amdtp_stream *s,
770 const struct pkt_desc *descs,
771 unsigned int packets)
31ef9134 772{
9a738ad1
TS
773 struct snd_pcm_substream *pcm;
774 unsigned int pcm_frames;
5e2ece0f 775
9a738ad1
TS
776 pcm = READ_ONCE(s->pcm);
777 pcm_frames = s->process_ctx_payloads(s, descs, packets, pcm);
778 if (pcm)
779 update_pcm_pointers(s, pcm, pcm_frames);
0f5cfcb2
TS
780}
781
782static void out_stream_callback(struct fw_iso_context *context, u32 tstamp,
783 size_t header_length, void *header,
784 void *private_data)
785{
786 struct amdtp_stream *s = private_data;
787 const __be32 *ctx_header = header;
788 unsigned int packets = header_length / sizeof(*ctx_header);
789 int i;
790
791 if (s->packet_index < 0)
792 return;
793
794 generate_ideal_pkt_descs(s, s->pkt_descs, ctx_header, packets);
795
796 process_ctx_payloads(s, s->pkt_descs, packets);
5e2ece0f
TS
797
798 for (i = 0; i < packets; ++i) {
799 const struct pkt_desc *desc = s->pkt_descs + i;
f4f6ae7b 800 unsigned int syt;
6bc1a269
TS
801 struct {
802 struct fw_iso_packet params;
803 __be32 header[IT_PKT_HEADER_SIZE_CIP / sizeof(__be32)];
804 } template = { {0}, {0} };
31ef9134 805
f4f6ae7b
TS
806 if (s->ctx_data.rx.syt_override < 0)
807 syt = desc->syt;
808 else
3baf3053
TS
809 syt = s->ctx_data.rx.syt_override;
810
f4f6ae7b
TS
811 build_it_pkt_header(s, desc->cycle, &template.params,
812 desc->data_blocks, desc->data_block_counter,
813 syt, i);
6bc1a269
TS
814
815 if (queue_out_packet(s, &template.params) < 0) {
fce9b013 816 cancel_stream(s);
a4103bd7
TS
817 return;
818 }
ccccad86 819 }
a4103bd7 820
13882a82 821 fw_iso_context_queue_flush(s->context);
31ef9134
CL
822}
823
73fc7f08 824static void in_stream_callback(struct fw_iso_context *context, u32 tstamp,
2b3fc456
TS
825 size_t header_length, void *header,
826 void *private_data)
827{
828 struct amdtp_stream *s = private_data;
753e7179 829 unsigned int packets;
cc4f8e91 830 __be32 *ctx_header = header;
753e7179
TS
831 int i;
832 int err;
2b3fc456 833
a4103bd7
TS
834 if (s->packet_index < 0)
835 return;
836
d3d10a4a
TS
837 // The number of packets in buffer.
838 packets = header_length / s->ctx_data.tx.ctx_header_size;
f90e2ded 839
753e7179
TS
840 err = generate_device_pkt_descs(s, s->pkt_descs, ctx_header, packets);
841 if (err < 0) {
842 if (err != -EAGAIN) {
843 cancel_stream(s);
844 return;
845 }
5e2ece0f 846 } else {
0f5cfcb2 847 process_ctx_payloads(s, s->pkt_descs, packets);
5e2ece0f
TS
848 }
849
850 for (i = 0; i < packets; ++i) {
851 struct fw_iso_packet params = {0};
2b3fc456 852
753e7179
TS
853 if (queue_in_packet(s, &params) < 0) {
854 cancel_stream(s);
855 return;
856 }
7b3b0d85
TS
857 }
858
2b3fc456
TS
859 fw_iso_context_queue_flush(s->context);
860}
861
7b3b0d85
TS
862/* this is executed one time */
863static void amdtp_stream_first_callback(struct fw_iso_context *context,
73fc7f08 864 u32 tstamp, size_t header_length,
7b3b0d85
TS
865 void *header, void *private_data)
866{
867 struct amdtp_stream *s = private_data;
26cd1e58 868 const __be32 *ctx_header = header;
a04513f8 869 u32 cycle;
7b3b0d85
TS
870
871 /*
872 * For in-stream, first packet has come.
873 * For out-stream, prepared to transmit first packet
874 */
875 s->callbacked = true;
876 wake_up(&s->callback_wait);
877
a04513f8 878 if (s->direction == AMDTP_IN_STREAM) {
26cd1e58 879 cycle = compute_cycle_count(ctx_header[1]);
cc4f8e91 880
7b3b0d85 881 context->callback.sc = in_stream_callback;
a04513f8 882 } else {
26cd1e58
TS
883 cycle = compute_it_cycle(*ctx_header);
884
7b3b0d85 885 context->callback.sc = out_stream_callback;
a04513f8
TS
886 }
887
888 s->start_cycle = cycle;
7b3b0d85 889
73fc7f08 890 context->callback.sc(context, tstamp, header_length, header, s);
7b3b0d85
TS
891}
892
31ef9134 893/**
be4a2894
TS
894 * amdtp_stream_start - start transferring packets
895 * @s: the AMDTP stream to start
31ef9134
CL
896 * @channel: the isochronous channel on the bus
897 * @speed: firewire speed code
898 *
899 * The stream cannot be started until it has been configured with
be4a2894
TS
900 * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI
901 * device can be started.
31ef9134 902 */
74f94e41 903static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed)
31ef9134
CL
904{
905 static const struct {
906 unsigned int data_block;
907 unsigned int syt_offset;
d3d10a4a 908 } *entry, initial_state[] = {
31ef9134
CL
909 [CIP_SFC_32000] = { 4, 3072 },
910 [CIP_SFC_48000] = { 6, 1024 },
911 [CIP_SFC_96000] = { 12, 1024 },
912 [CIP_SFC_192000] = { 24, 1024 },
913 [CIP_SFC_44100] = { 0, 67 },
914 [CIP_SFC_88200] = { 0, 67 },
915 [CIP_SFC_176400] = { 0, 67 },
916 };
d3d10a4a 917 unsigned int ctx_header_size;
f11453c7 918 unsigned int max_ctx_payload_size;
2b3fc456 919 enum dma_data_direction dir;
7ab56645 920 int type, tag, err;
31ef9134
CL
921
922 mutex_lock(&s->mutex);
923
be4a2894 924 if (WARN_ON(amdtp_stream_running(s) ||
4b7da117 925 (s->data_block_quadlets < 1))) {
31ef9134
CL
926 err = -EBADFD;
927 goto err_unlock;
928 }
929
d3d10a4a 930 if (s->direction == AMDTP_IN_STREAM) {
b6bc8123 931 s->data_block_counter = UINT_MAX;
d3d10a4a
TS
932 } else {
933 entry = &initial_state[s->sfc];
934
b6bc8123 935 s->data_block_counter = 0;
d3d10a4a
TS
936 s->ctx_data.rx.data_block_state = entry->data_block;
937 s->ctx_data.rx.syt_offset_state = entry->syt_offset;
938 s->ctx_data.rx.last_syt_offset = TICKS_PER_CYCLE;
939 }
31ef9134 940
ab118bd8
TS
941 // initialize packet buffer.
942 max_ctx_payload_size = amdtp_stream_get_max_payload(s);
2b3fc456
TS
943 if (s->direction == AMDTP_IN_STREAM) {
944 dir = DMA_FROM_DEVICE;
945 type = FW_ISO_CONTEXT_RECEIVE;
ab118bd8
TS
946 if (!(s->flags & CIP_NO_HEADER)) {
947 max_ctx_payload_size -= 8;
f11453c7 948 ctx_header_size = IR_CTX_HEADER_SIZE_CIP;
ab118bd8 949 } else {
f11453c7 950 ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP;
ab118bd8 951 }
2b3fc456
TS
952 } else {
953 dir = DMA_TO_DEVICE;
954 type = FW_ISO_CONTEXT_TRANSMIT;
df9160b9 955 ctx_header_size = 0; // No effect for IT context.
f11453c7 956
b18f0cfa
TS
957 if (!(s->flags & CIP_NO_HEADER))
958 max_ctx_payload_size -= IT_PKT_HEADER_SIZE_CIP;
959 }
f11453c7 960
31ef9134 961 err = iso_packets_buffer_init(&s->buffer, s->unit, QUEUE_LENGTH,
f11453c7 962 max_ctx_payload_size, dir);
31ef9134
CL
963 if (err < 0)
964 goto err_unlock;
965
966 s->context = fw_iso_context_create(fw_parent_device(s->unit)->card,
d3d10a4a
TS
967 type, channel, speed, ctx_header_size,
968 amdtp_stream_first_callback, s);
31ef9134
CL
969 if (IS_ERR(s->context)) {
970 err = PTR_ERR(s->context);
971 if (err == -EBUSY)
972 dev_err(&s->unit->device,
be4a2894 973 "no free stream on this controller\n");
31ef9134
CL
974 goto err_buffer;
975 }
976
be4a2894 977 amdtp_stream_update(s);
31ef9134 978
d3d10a4a 979 if (s->direction == AMDTP_IN_STREAM) {
f11453c7 980 s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size;
d3d10a4a
TS
981 s->ctx_data.tx.ctx_header_size = ctx_header_size;
982 }
52759c09 983
3b196c39
TS
984 if (s->flags & CIP_NO_HEADER)
985 s->tag = TAG_NO_CIP_HEADER;
986 else
987 s->tag = TAG_CIP;
988
04130cf8
TS
989 s->pkt_descs = kcalloc(INTERRUPT_INTERVAL, sizeof(*s->pkt_descs),
990 GFP_KERNEL);
991 if (!s->pkt_descs) {
992 err = -ENOMEM;
993 goto err_context;
994 }
995
ec00f5e4 996 s->packet_index = 0;
4b7da117 997 do {
6007bf54 998 struct fw_iso_packet params;
b18f0cfa 999 if (s->direction == AMDTP_IN_STREAM) {
6007bf54 1000 err = queue_in_packet(s, &params);
b18f0cfa
TS
1001 } else {
1002 params.header_length = 0;
1003 params.payload_length = 0;
1004 err = queue_out_packet(s, &params);
1005 }
4b7da117 1006 if (err < 0)
04130cf8 1007 goto err_pkt_descs;
4b7da117 1008 } while (s->packet_index > 0);
31ef9134 1009
2b3fc456 1010 /* NOTE: TAG1 matches CIP. This just affects in stream. */
7ab56645 1011 tag = FW_ISO_CONTEXT_MATCH_TAG1;
3b196c39 1012 if ((s->flags & CIP_EMPTY_WITH_TAG0) || (s->flags & CIP_NO_HEADER))
7ab56645
TS
1013 tag |= FW_ISO_CONTEXT_MATCH_TAG0;
1014
7b3b0d85 1015 s->callbacked = false;
7ab56645 1016 err = fw_iso_context_start(s->context, -1, 0, tag);
31ef9134 1017 if (err < 0)
04130cf8 1018 goto err_pkt_descs;
31ef9134
CL
1019
1020 mutex_unlock(&s->mutex);
1021
1022 return 0;
04130cf8
TS
1023err_pkt_descs:
1024 kfree(s->pkt_descs);
31ef9134
CL
1025err_context:
1026 fw_iso_context_destroy(s->context);
1027 s->context = ERR_PTR(-1);
1028err_buffer:
1029 iso_packets_buffer_destroy(&s->buffer, s->unit);
1030err_unlock:
1031 mutex_unlock(&s->mutex);
1032
1033 return err;
1034}
31ef9134 1035
e9148ddd 1036/**
be4a2894
TS
1037 * amdtp_stream_pcm_pointer - get the PCM buffer position
1038 * @s: the AMDTP stream that transports the PCM data
e9148ddd
CL
1039 *
1040 * Returns the current buffer position, in frames.
1041 */
be4a2894 1042unsigned long amdtp_stream_pcm_pointer(struct amdtp_stream *s)
e9148ddd 1043{
1dba9db0
TS
1044 /*
1045 * This function is called in software IRQ context of period_tasklet or
1046 * process context.
1047 *
1048 * When the software IRQ context was scheduled by software IRQ context
1049 * of IR/IT contexts, queued packets were already handled. Therefore,
1050 * no need to flush the queue in buffer anymore.
1051 *
1052 * When the process context reach here, some packets will be already
1053 * queued in the buffer. These packets should be handled immediately
1054 * to keep better granularity of PCM pointer.
1055 *
1056 * Later, the process context will sometimes schedules software IRQ
1057 * context of the period_tasklet. Then, no need to flush the queue by
1058 * the same reason as described for IR/IT contexts.
1059 */
1060 if (!in_interrupt() && amdtp_stream_running(s))
92b862c7 1061 fw_iso_context_flush_completions(s->context);
e9148ddd 1062
6aa7de05 1063 return READ_ONCE(s->pcm_buffer_pointer);
e9148ddd 1064}
be4a2894 1065EXPORT_SYMBOL(amdtp_stream_pcm_pointer);
e9148ddd 1066
875becf8
TS
1067/**
1068 * amdtp_stream_pcm_ack - acknowledge queued PCM frames
1069 * @s: the AMDTP stream that transfers the PCM frames
1070 *
1071 * Returns zero always.
1072 */
1073int amdtp_stream_pcm_ack(struct amdtp_stream *s)
1074{
1075 /*
1076 * Process isochronous packets for recent isochronous cycle to handle
1077 * queued PCM frames.
1078 */
1079 if (amdtp_stream_running(s))
1080 fw_iso_context_flush_completions(s->context);
1081
1082 return 0;
1083}
1084EXPORT_SYMBOL(amdtp_stream_pcm_ack);
1085
31ef9134 1086/**
be4a2894
TS
1087 * amdtp_stream_update - update the stream after a bus reset
1088 * @s: the AMDTP stream
31ef9134 1089 */
be4a2894 1090void amdtp_stream_update(struct amdtp_stream *s)
31ef9134 1091{
9a2820c1 1092 /* Precomputing. */
6aa7de05
MR
1093 WRITE_ONCE(s->source_node_id_field,
1094 (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & CIP_SID_MASK);
31ef9134 1095}
be4a2894 1096EXPORT_SYMBOL(amdtp_stream_update);
31ef9134
CL
1097
1098/**
be4a2894
TS
1099 * amdtp_stream_stop - stop sending packets
1100 * @s: the AMDTP stream to stop
31ef9134
CL
1101 *
1102 * All PCM and MIDI devices of the stream must be stopped before the stream
1103 * itself can be stopped.
1104 */
74f94e41 1105static void amdtp_stream_stop(struct amdtp_stream *s)
31ef9134
CL
1106{
1107 mutex_lock(&s->mutex);
1108
be4a2894 1109 if (!amdtp_stream_running(s)) {
31ef9134
CL
1110 mutex_unlock(&s->mutex);
1111 return;
1112 }
1113
76fb8789 1114 tasklet_kill(&s->period_tasklet);
31ef9134
CL
1115 fw_iso_context_stop(s->context);
1116 fw_iso_context_destroy(s->context);
1117 s->context = ERR_PTR(-1);
1118 iso_packets_buffer_destroy(&s->buffer, s->unit);
04130cf8 1119 kfree(s->pkt_descs);
31ef9134 1120
7b3b0d85
TS
1121 s->callbacked = false;
1122
31ef9134
CL
1123 mutex_unlock(&s->mutex);
1124}
31ef9134
CL
1125
1126/**
be4a2894 1127 * amdtp_stream_pcm_abort - abort the running PCM device
31ef9134
CL
1128 * @s: the AMDTP stream about to be stopped
1129 *
1130 * If the isochronous stream needs to be stopped asynchronously, call this
1131 * function first to stop the PCM device.
1132 */
be4a2894 1133void amdtp_stream_pcm_abort(struct amdtp_stream *s)
31ef9134
CL
1134{
1135 struct snd_pcm_substream *pcm;
1136
6aa7de05 1137 pcm = READ_ONCE(s->pcm);
1fb8510c
TI
1138 if (pcm)
1139 snd_pcm_stop_xrun(pcm);
31ef9134 1140}
be4a2894 1141EXPORT_SYMBOL(amdtp_stream_pcm_abort);
3ec3d7a3
TS
1142
1143/**
1144 * amdtp_domain_init - initialize an AMDTP domain structure
1145 * @d: the AMDTP domain to initialize.
1146 */
1147int amdtp_domain_init(struct amdtp_domain *d)
1148{
1149 INIT_LIST_HEAD(&d->streams);
1150
1151 return 0;
1152}
1153EXPORT_SYMBOL_GPL(amdtp_domain_init);
1154
1155/**
1156 * amdtp_domain_destroy - destroy an AMDTP domain structure
1157 * @d: the AMDTP domain to destroy.
1158 */
1159void amdtp_domain_destroy(struct amdtp_domain *d)
1160{
8d0d5c3f
TS
1161 // At present nothing to do.
1162 return;
3ec3d7a3
TS
1163}
1164EXPORT_SYMBOL_GPL(amdtp_domain_destroy);
6261f90b 1165
157a53ee
TS
1166/**
1167 * amdtp_domain_add_stream - register isoc context into the domain.
1168 * @d: the AMDTP domain.
1169 * @s: the AMDTP stream.
1170 * @channel: the isochronous channel on the bus.
1171 * @speed: firewire speed code.
1172 */
1173int amdtp_domain_add_stream(struct amdtp_domain *d, struct amdtp_stream *s,
1174 int channel, int speed)
1175{
1176 struct amdtp_stream *tmp;
1177
1178 list_for_each_entry(tmp, &d->streams, list) {
1179 if (s == tmp)
1180 return -EBUSY;
1181 }
1182
1183 list_add(&s->list, &d->streams);
1184
1185 s->channel = channel;
1186 s->speed = speed;
1187
1188 return 0;
1189}
1190EXPORT_SYMBOL_GPL(amdtp_domain_add_stream);
1191
9b4702b0
TS
1192/**
1193 * amdtp_domain_start - start sending packets for isoc context in the domain.
1194 * @d: the AMDTP domain.
1195 */
1196int amdtp_domain_start(struct amdtp_domain *d)
1197{
1198 struct amdtp_stream *s;
1199 int err = 0;
1200
1201 list_for_each_entry(s, &d->streams, list) {
1202 err = amdtp_stream_start(s, s->channel, s->speed);
1203 if (err < 0)
1204 break;
1205 }
1206
1207 if (err < 0) {
1208 list_for_each_entry(s, &d->streams, list)
1209 amdtp_stream_stop(s);
1210 }
1211
1212 return err;
1213}
1214EXPORT_SYMBOL_GPL(amdtp_domain_start);
1215
6261f90b
TS
1216/**
1217 * amdtp_domain_stop - stop sending packets for isoc context in the same domain.
1218 * @d: the AMDTP domain to which the isoc contexts belong.
1219 */
1220void amdtp_domain_stop(struct amdtp_domain *d)
1221{
1222 struct amdtp_stream *s, *next;
1223
1224 list_for_each_entry_safe(s, next, &d->streams, list) {
1225 list_del(&s->list);
1226
1227 amdtp_stream_stop(s);
1228 }
1229}
1230EXPORT_SYMBOL_GPL(amdtp_domain_stop);