[mirror_ubuntu-kernels.git] / sound / firewire / tascam / tascam-stream.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * tascam-stream.c - a part of driver for TASCAM FireWire series
 *
 * Copyright (c) 2015 Takashi Sakamoto
 */

#include <linux/delay.h>
#include "tascam.h"

#define CLOCK_STATUS_MASK      0xffff0000
#define CLOCK_CONFIG_MASK      0x0000ffff

#define READY_TIMEOUT_MS	4000

static int get_clock(struct snd_tscm *tscm, u32 *data)
{
	int trial = 0;
	__be32 reg;
	int err;

	while (trial++ < 5) {
		err = snd_fw_transaction(tscm->unit, TCODE_READ_QUADLET_REQUEST,
				TSCM_ADDR_BASE + TSCM_OFFSET_CLOCK_STATUS,
				&reg, sizeof(reg), 0);
		if (err < 0)
			return err;

		*data = be32_to_cpu(reg);
		if (*data & CLOCK_STATUS_MASK)
			break;

		// In intermediate state after changing clock status.
		msleep(50);
	}

	// Still in the intermediate state.
	if (trial >= 5)
		return -EAGAIN;

	return 0;
}

static int set_clock(struct snd_tscm *tscm, unsigned int rate,
		     enum snd_tscm_clock clock)
{
	u32 data;
	__be32 reg;
	int err;

	err = get_clock(tscm, &data);
	if (err < 0)
		return err;
	data &= CLOCK_CONFIG_MASK;

	if (rate > 0) {
		data &= 0x000000ff;
		/* Base rate. */
		if ((rate % 44100) == 0) {
			data |= 0x00000100;
			/* Multiplier. */
			if (rate / 44100 == 2)
				data |= 0x00008000;
		} else if ((rate % 48000) == 0) {
			data |= 0x00000200;
			/* Multiplier. */
			if (rate / 48000 == 2)
				data |= 0x00008000;
		} else {
			return -EAGAIN;
		}
	}

	if (clock != INT_MAX) {
		data &= 0x0000ff00;
		data |= clock + 1;
	}

	reg = cpu_to_be32(data);

	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
				 TSCM_ADDR_BASE + TSCM_OFFSET_CLOCK_STATUS,
				 &reg, sizeof(reg), 0);
	if (err < 0)
		return err;

	if (data & 0x00008000)
		reg = cpu_to_be32(0x0000001a);
	else
		reg = cpu_to_be32(0x0000000d);

	return snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
				  TSCM_ADDR_BASE + TSCM_OFFSET_MULTIPLEX_MODE,
				  &reg, sizeof(reg), 0);
}

int snd_tscm_stream_get_rate(struct snd_tscm *tscm, unsigned int *rate)
{
	u32 data;
	int err;

	err = get_clock(tscm, &data);
	if (err < 0)
		return err;

	data = (data & 0xff000000) >> 24;

	/* Check base rate. */
	if ((data & 0x0f) == 0x01)
		*rate = 44100;
	else if ((data & 0x0f) == 0x02)
		*rate = 48000;
	else
		return -EAGAIN;

	/* Check multiplier. */
	if ((data & 0xf0) == 0x80)
		*rate *= 2;
	else if ((data & 0xf0) != 0x00)
		return -EAGAIN;

	return err;
}

int snd_tscm_stream_get_clock(struct snd_tscm *tscm, enum snd_tscm_clock *clock)
{
	u32 data;
	int err;

	err = get_clock(tscm, &data);
	if (err < 0)
		return err;

	*clock = ((data & 0x00ff0000) >> 16) - 1;
	if (*clock < 0 || *clock > SND_TSCM_CLOCK_ADAT)
		return -EIO;

	return 0;
}

static int enable_data_channels(struct snd_tscm *tscm)
{
	__be32 reg;
	u32 data;
	unsigned int i;
	int err;

	data = 0;
	for (i = 0; i < tscm->spec->pcm_capture_analog_channels; ++i)
		data |= BIT(i);
	if (tscm->spec->has_adat)
		data |= 0x0000ff00;
	if (tscm->spec->has_spdif)
		data |= 0x00030000;

	reg = cpu_to_be32(data);
	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
				 TSCM_ADDR_BASE + TSCM_OFFSET_TX_PCM_CHANNELS,
				 &reg, sizeof(reg), 0);
	if (err < 0)
		return err;

	data = 0;
	for (i = 0; i < tscm->spec->pcm_playback_analog_channels; ++i)
		data |= BIT(i);
	if (tscm->spec->has_adat)
		data |= 0x0000ff00;
	if (tscm->spec->has_spdif)
		data |= 0x00030000;

	reg = cpu_to_be32(data);
	return snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
				  TSCM_ADDR_BASE + TSCM_OFFSET_RX_PCM_CHANNELS,
				  &reg, sizeof(reg), 0);
}

static int set_stream_formats(struct snd_tscm *tscm, unsigned int rate)
{
	__be32 reg;
	int err;

	// Set an option for unknown purpose.
	reg = cpu_to_be32(0x00200000);
	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
				 TSCM_ADDR_BASE + TSCM_OFFSET_SET_OPTION,
				 &reg, sizeof(reg), 0);
	if (err < 0)
		return err;

	return enable_data_channels(tscm);
}

static void finish_session(struct snd_tscm *tscm)
{
	__be32 reg;

	reg = 0;
	snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
			   TSCM_ADDR_BASE + TSCM_OFFSET_START_STREAMING,
			   &reg, sizeof(reg), 0);

	reg = 0;
	snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
			   TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_ON,
			   &reg, sizeof(reg), 0);

	// Unregister channels.
	reg = cpu_to_be32(0x00000000);
	snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
			   TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_CH,
			   &reg, sizeof(reg), 0);
	reg = cpu_to_be32(0x00000000);
	snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
			   TSCM_ADDR_BASE + TSCM_OFFSET_UNKNOWN,
			   &reg, sizeof(reg), 0);
	reg = cpu_to_be32(0x00000000);
	snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
			   TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_CH,
			   &reg, sizeof(reg), 0);
}

static int begin_session(struct snd_tscm *tscm)
{
	__be32 reg;
	int err;

	// Register the isochronous channel for transmitting stream.
	reg = cpu_to_be32(tscm->tx_resources.channel);
	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
				 TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_CH,
				 &reg, sizeof(reg), 0);
	if (err < 0)
		return err;

	// Unknown.
	reg = cpu_to_be32(0x00000002);
	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
				 TSCM_ADDR_BASE + TSCM_OFFSET_UNKNOWN,
				 &reg, sizeof(reg), 0);
	if (err < 0)
		return err;

	// Register the isochronous channel for receiving stream.
	reg = cpu_to_be32(tscm->rx_resources.channel);
	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
				 TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_CH,
				 &reg, sizeof(reg), 0);
	if (err < 0)
		return err;

	reg = cpu_to_be32(0x00000001);
	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
				 TSCM_ADDR_BASE + TSCM_OFFSET_START_STREAMING,
				 &reg, sizeof(reg), 0);
	if (err < 0)
		return err;

	reg = cpu_to_be32(0x00000001);
	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
				 TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_ON,
				 &reg, sizeof(reg), 0);
	if (err < 0)
		return err;

	// Set an option for unknown purpose.
	reg = cpu_to_be32(0x00002000);
	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
				 TSCM_ADDR_BASE + TSCM_OFFSET_SET_OPTION,
				 &reg, sizeof(reg), 0);
	if (err < 0)
		return err;

	// Start multiplexing PCM samples on packets.
	reg = cpu_to_be32(0x00000001);
	return snd_fw_transaction(tscm->unit,
				  TCODE_WRITE_QUADLET_REQUEST,
				  TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_ON,
				  &reg, sizeof(reg), 0);
}

static int keep_resources(struct snd_tscm *tscm, unsigned int rate,
			  struct amdtp_stream *stream)
{
	struct fw_iso_resources *resources;
	int err;

	if (stream == &tscm->tx_stream)
		resources = &tscm->tx_resources;
	else
		resources = &tscm->rx_resources;

	err = amdtp_tscm_set_parameters(stream, rate);
	if (err < 0)
		return err;

	return fw_iso_resources_allocate(resources,
				amdtp_stream_get_max_payload(stream),
				fw_parent_device(tscm->unit)->max_speed);
}

static int init_stream(struct snd_tscm *tscm, struct amdtp_stream *s)
{
	struct fw_iso_resources *resources;
	enum amdtp_stream_direction dir;
	unsigned int pcm_channels;
	int err;

	if (s == &tscm->tx_stream) {
		resources = &tscm->tx_resources;
		dir = AMDTP_IN_STREAM;
		pcm_channels = tscm->spec->pcm_capture_analog_channels;
	} else {
		resources = &tscm->rx_resources;
		dir = AMDTP_OUT_STREAM;
		pcm_channels = tscm->spec->pcm_playback_analog_channels;
	}

	if (tscm->spec->has_adat)
		pcm_channels += 8;
	if (tscm->spec->has_spdif)
		pcm_channels += 2;

	err = fw_iso_resources_init(resources, tscm->unit);
	if (err < 0)
		return err;

	err = amdtp_tscm_init(s, tscm->unit, dir, pcm_channels);
	if (err < 0)
		fw_iso_resources_free(resources);

	return err;
}

static void destroy_stream(struct snd_tscm *tscm, struct amdtp_stream *s)
{
	amdtp_stream_destroy(s);

	if (s == &tscm->tx_stream)
		fw_iso_resources_destroy(&tscm->tx_resources);
	else
		fw_iso_resources_destroy(&tscm->rx_resources);
}

int snd_tscm_stream_init_duplex(struct snd_tscm *tscm)
{
	int err;

	err = init_stream(tscm, &tscm->tx_stream);
	if (err < 0)
		return err;

	err = init_stream(tscm, &tscm->rx_stream);
	if (err < 0) {
		destroy_stream(tscm, &tscm->tx_stream);
		return err;
	}

	err = amdtp_domain_init(&tscm->domain);
	if (err < 0) {
		destroy_stream(tscm, &tscm->tx_stream);
		destroy_stream(tscm, &tscm->rx_stream);
	}

	return err;
}

// At bus reset, streaming is stopped and some registers are clear.
void snd_tscm_stream_update_duplex(struct snd_tscm *tscm)
{
	amdtp_domain_stop(&tscm->domain);

	amdtp_stream_pcm_abort(&tscm->tx_stream);
	amdtp_stream_pcm_abort(&tscm->rx_stream);
}

// This function should be called before starting streams or after stopping
// streams.
void snd_tscm_stream_destroy_duplex(struct snd_tscm *tscm)
{
	amdtp_domain_destroy(&tscm->domain);

	destroy_stream(tscm, &tscm->rx_stream);
	destroy_stream(tscm, &tscm->tx_stream);
}

int snd_tscm_stream_reserve_duplex(struct snd_tscm *tscm, unsigned int rate,
				   unsigned int frames_per_period,
				   unsigned int frames_per_buffer)
{
	unsigned int curr_rate;
	int err;

	err = snd_tscm_stream_get_rate(tscm, &curr_rate);
	if (err < 0)
		return err;

	if (tscm->substreams_counter == 0 || rate != curr_rate) {
		amdtp_domain_stop(&tscm->domain);

		finish_session(tscm);

		fw_iso_resources_free(&tscm->tx_resources);
		fw_iso_resources_free(&tscm->rx_resources);

		err = set_clock(tscm, rate, INT_MAX);
		if (err < 0)
			return err;

		err = keep_resources(tscm, rate, &tscm->tx_stream);
		if (err < 0)
			return err;

		err = keep_resources(tscm, rate, &tscm->rx_stream);
		if (err < 0) {
			fw_iso_resources_free(&tscm->tx_resources);
			return err;
		}

		err = amdtp_domain_set_events_per_period(&tscm->domain,
					frames_per_period, frames_per_buffer);
		if (err < 0) {
			fw_iso_resources_free(&tscm->tx_resources);
			fw_iso_resources_free(&tscm->rx_resources);
			return err;
		}

		tscm->need_long_tx_init_skip = (rate != curr_rate);
	}

	return 0;
}

int snd_tscm_stream_start_duplex(struct snd_tscm *tscm, unsigned int rate)
{
	unsigned int generation = tscm->rx_resources.generation;
	int err;

	if (tscm->substreams_counter == 0)
		return 0;

	if (amdtp_streaming_error(&tscm->rx_stream) ||
	    amdtp_streaming_error(&tscm->tx_stream)) {
		amdtp_domain_stop(&tscm->domain);
		finish_session(tscm);
	}

	if (generation != fw_parent_device(tscm->unit)->card->generation) {
		err = fw_iso_resources_update(&tscm->tx_resources);
		if (err < 0)
			goto error;

		err = fw_iso_resources_update(&tscm->rx_resources);
		if (err < 0)
			goto error;
	}

	if (!amdtp_stream_running(&tscm->rx_stream)) {
		int spd = fw_parent_device(tscm->unit)->max_speed;
		unsigned int tx_init_skip_cycles;

		err = set_stream_formats(tscm, rate);
		if (err < 0)
			goto error;

		err = begin_session(tscm);
		if (err < 0)
			goto error;

		err = amdtp_domain_add_stream(&tscm->domain, &tscm->rx_stream,
					      tscm->rx_resources.channel, spd);
		if (err < 0)
			goto error;

		err = amdtp_domain_add_stream(&tscm->domain, &tscm->tx_stream,
					      tscm->tx_resources.channel, spd);
		if (err < 0)
			goto error;

		if (tscm->need_long_tx_init_skip)
			tx_init_skip_cycles = 16000;
		else
			tx_init_skip_cycles = 0;

		// MEMO: Just after starting packet streaming, it transfers packets without any
		// event. Enough after receiving the sequence of packets, it multiplexes events into
		// the packet. However, just after changing sampling transfer frequency, it stops
		// multiplexing during packet transmission. Enough after, it restarts multiplexing
		// again. The device ignores presentation time expressed by the value of syt field
		// of CIP header in received packets. The sequence of the number of data blocks per
		// packet is important for media clock recovery.
		err = amdtp_domain_start(&tscm->domain, tx_init_skip_cycles, true, true);
		if (err < 0)
			goto error;

		if (!amdtp_domain_wait_ready(&tscm->domain, READY_TIMEOUT_MS)) {
			err = -ETIMEDOUT;
			goto error;
		}
	}

	return 0;
error:
	amdtp_domain_stop(&tscm->domain);
	finish_session(tscm);

	return err;
}

void snd_tscm_stream_stop_duplex(struct snd_tscm *tscm)
{
	if (tscm->substreams_counter == 0) {
		amdtp_domain_stop(&tscm->domain);
		finish_session(tscm);

		fw_iso_resources_free(&tscm->tx_resources);
		fw_iso_resources_free(&tscm->rx_resources);

		tscm->need_long_tx_init_skip = false;
	}
}

void snd_tscm_stream_lock_changed(struct snd_tscm *tscm)
{
	tscm->dev_lock_changed = true;
	wake_up(&tscm->hwdep_wait);
}

int snd_tscm_stream_lock_try(struct snd_tscm *tscm)
{
	int err;

	spin_lock_irq(&tscm->lock);

	/* user land lock this */
	if (tscm->dev_lock_count < 0) {
		err = -EBUSY;
		goto end;
	}

	/* this is the first time */
	if (tscm->dev_lock_count++ == 0)
		snd_tscm_stream_lock_changed(tscm);
	err = 0;
end:
	spin_unlock_irq(&tscm->lock);
	return err;
}

void snd_tscm_stream_lock_release(struct snd_tscm *tscm)
{
	spin_lock_irq(&tscm->lock);

	if (WARN_ON(tscm->dev_lock_count <= 0))
		goto end;
	if (--tscm->dev_lock_count == 0)
		snd_tscm_stream_lock_changed(tscm);
end:
	spin_unlock_irq(&tscm->lock);
}
Commit	Line	Data
da607e19	1	// SPDX-License-Identifier: GPL-2.0-only
35efa5c4 TS	2	/*
	3	* tascam-stream.c - a part of driver for TASCAM FireWire series
	4	*
	5	* Copyright (c) 2015 Takashi Sakamoto
35efa5c4 TS	6	*/
	7
	8	#include <linux/delay.h>
	9	#include "tascam.h"
	10
e1a00b5b TS	11	#define CLOCK_STATUS_MASK 0xffff0000
	12	#define CLOCK_CONFIG_MASK 0x0000ffff
	13
a9dd8a61	14	#define READY_TIMEOUT_MS 4000
35efa5c4 TS	15
	16	static int get_clock(struct snd_tscm tscm, u32 data)
	17	{
e1a00b5b	18	int trial = 0;
35efa5c4 TS	19	__be32 reg;
	20	int err;
	21
e1a00b5b TS	22	while (trial++ < 5) {
	23	err = snd_fw_transaction(tscm->unit, TCODE_READ_QUADLET_REQUEST,
	24	TSCM_ADDR_BASE + TSCM_OFFSET_CLOCK_STATUS,
	25	&reg, sizeof(reg), 0);
	26	if (err < 0)
	27	return err;
	28
35efa5c4	29	*data = be32_to_cpu(reg);
e1a00b5b TS	30	if (*data & CLOCK_STATUS_MASK)
e1a00b5b TS	31	break;
35efa5c4	32
e1a00b5b TS	33	// In intermediate state after changing clock status.
	34	msleep(50);
	35	}
	36
	37	// Still in the intermediate state.
	38	if (trial >= 5)
	39	return -EAGAIN;
	40
	41	return 0;
35efa5c4 TS	42	}
	43
	44	static int set_clock(struct snd_tscm *tscm, unsigned int rate,
	45	enum snd_tscm_clock clock)
	46	{
	47	u32 data;
	48	__be32 reg;
	49	int err;
	50
	51	err = get_clock(tscm, &data);
	52	if (err < 0)
	53	return err;
e1a00b5b	54	data &= CLOCK_CONFIG_MASK;
35efa5c4 TS	55
	56	if (rate > 0) {
	57	data &= 0x000000ff;
	58	/* Base rate. */
	59	if ((rate % 44100) == 0) {
	60	data \|= 0x00000100;
	61	/* Multiplier. */
	62	if (rate / 44100 == 2)
	63	data \|= 0x00008000;
	64	} else if ((rate % 48000) == 0) {
	65	data \|= 0x00000200;
	66	/* Multiplier. */
	67	if (rate / 48000 == 2)
	68	data \|= 0x00008000;
	69	} else {
	70	return -EAGAIN;
	71	}
	72	}
	73
	74	if (clock != INT_MAX) {
	75	data &= 0x0000ff00;
	76	data \|= clock + 1;
	77	}
	78
	79	reg = cpu_to_be32(data);
	80
	81	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	82	TSCM_ADDR_BASE + TSCM_OFFSET_CLOCK_STATUS,
	83	&reg, sizeof(reg), 0);
	84	if (err < 0)
	85	return err;
	86
	87	if (data & 0x00008000)
	88	reg = cpu_to_be32(0x0000001a);
	89	else
	90	reg = cpu_to_be32(0x0000000d);
	91
	92	return snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	93	TSCM_ADDR_BASE + TSCM_OFFSET_MULTIPLEX_MODE,
	94	&reg, sizeof(reg), 0);
	95	}
	96
	97	int snd_tscm_stream_get_rate(struct snd_tscm tscm, unsigned int rate)
	98	{
e1a00b5b	99	u32 data;
35efa5c4 TS	100	int err;
35efa5c4 TS	101
e1a00b5b TS	102	err = get_clock(tscm, &data);
	103	if (err < 0)
	104	return err;
35efa5c4	105
e1a00b5b	106	data = (data & 0xff000000) >> 24;
35efa5c4 TS	107
	108	/* Check base rate. */
	109	if ((data & 0x0f) == 0x01)
	110	*rate = 44100;
	111	else if ((data & 0x0f) == 0x02)
	112	*rate = 48000;
	113	else
	114	return -EAGAIN;
	115
	116	/* Check multiplier. */
	117	if ((data & 0xf0) == 0x80)
	118	rate = 2;
	119	else if ((data & 0xf0) != 0x00)
	120	return -EAGAIN;
	121
	122	return err;
	123	}
	124
	125	int snd_tscm_stream_get_clock(struct snd_tscm tscm, enum snd_tscm_clock clock)
	126	{
	127	u32 data;
	128	int err;
	129
	130	err = get_clock(tscm, &data);
	131	if (err < 0)
	132	return err;
	133
	134	*clock = ((data & 0x00ff0000) >> 16) - 1;
	135	if (clock < 0 \|\| clock > SND_TSCM_CLOCK_ADAT)
	136	return -EIO;
	137
	138	return 0;
	139	}
	140
	141	static int enable_data_channels(struct snd_tscm *tscm)
	142	{
	143	__be32 reg;
	144	u32 data;
	145	unsigned int i;
	146	int err;
	147
	148	data = 0;
	149	for (i = 0; i < tscm->spec->pcm_capture_analog_channels; ++i)
	150	data \|= BIT(i);
	151	if (tscm->spec->has_adat)
	152	data \|= 0x0000ff00;
	153	if (tscm->spec->has_spdif)
	154	data \|= 0x00030000;
	155
	156	reg = cpu_to_be32(data);
	157	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	158	TSCM_ADDR_BASE + TSCM_OFFSET_TX_PCM_CHANNELS,
	159	&reg, sizeof(reg), 0);
	160	if (err < 0)
	161	return err;
	162
	163	data = 0;
	164	for (i = 0; i < tscm->spec->pcm_playback_analog_channels; ++i)
	165	data \|= BIT(i);
	166	if (tscm->spec->has_adat)
	167	data \|= 0x0000ff00;
	168	if (tscm->spec->has_spdif)
	169	data \|= 0x00030000;
	170
171	reg = cpu_to_be32(data);
172	return snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
173	TSCM_ADDR_BASE + TSCM_OFFSET_RX_PCM_CHANNELS,
174	&reg, sizeof(reg), 0);
175	}
176
177	static int set_stream_formats(struct snd_tscm *tscm, unsigned int rate)
178	{
179	__be32 reg;
180	int err;
181
07b26642	182	// Set an option for unknown purpose.
35efa5c4 TS	183	reg = cpu_to_be32(0x00200000);
	184	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	185	TSCM_ADDR_BASE + TSCM_OFFSET_SET_OPTION,
	186	&reg, sizeof(reg), 0);
	187	if (err < 0)
	188	return err;
	189
07b26642	190	return enable_data_channels(tscm);
35efa5c4 TS	191	}
	192
	193	static void finish_session(struct snd_tscm *tscm)
	194	{
	195	__be32 reg;
	196
	197	reg = 0;
	198	snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	199	TSCM_ADDR_BASE + TSCM_OFFSET_START_STREAMING,
	200	&reg, sizeof(reg), 0);
	201
	202	reg = 0;
	203	snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	204	TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_ON,
	205	&reg, sizeof(reg), 0);
	206
2ef0b7cf TS	207	// Unregister channels.
	208	reg = cpu_to_be32(0x00000000);
	209	snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	210	TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_CH,
	211	&reg, sizeof(reg), 0);
	212	reg = cpu_to_be32(0x00000000);
	213	snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	214	TSCM_ADDR_BASE + TSCM_OFFSET_UNKNOWN,
	215	&reg, sizeof(reg), 0);
	216	reg = cpu_to_be32(0x00000000);
	217	snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	218	TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_CH,
	219	&reg, sizeof(reg), 0);
35efa5c4 TS	220	}
	221
	222	static int begin_session(struct snd_tscm *tscm)
	223	{
	224	__be32 reg;
	225	int err;
	226
2ef0b7cf TS	227	// Register the isochronous channel for transmitting stream.
	228	reg = cpu_to_be32(tscm->tx_resources.channel);
	229	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	230	TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_CH,
	231	&reg, sizeof(reg), 0);
	232	if (err < 0)
	233	return err;
	234
	235	// Unknown.
	236	reg = cpu_to_be32(0x00000002);
	237	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	238	TSCM_ADDR_BASE + TSCM_OFFSET_UNKNOWN,
	239	&reg, sizeof(reg), 0);
	240	if (err < 0)
	241	return err;
	242
	243	// Register the isochronous channel for receiving stream.
	244	reg = cpu_to_be32(tscm->rx_resources.channel);
	245	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	246	TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_CH,
	247	&reg, sizeof(reg), 0);
	248	if (err < 0)
	249	return err;
	250
35efa5c4 TS	251	reg = cpu_to_be32(0x00000001);
	252	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	253	TSCM_ADDR_BASE + TSCM_OFFSET_START_STREAMING,
	254	&reg, sizeof(reg), 0);
	255	if (err < 0)
	256	return err;
	257
	258	reg = cpu_to_be32(0x00000001);
	259	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	260	TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_ON,
	261	&reg, sizeof(reg), 0);
	262	if (err < 0)
	263	return err;
	264
2ef0b7cf	265	// Set an option for unknown purpose.
35efa5c4 TS	266	reg = cpu_to_be32(0x00002000);
	267	err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
	268	TSCM_ADDR_BASE + TSCM_OFFSET_SET_OPTION,
	269	&reg, sizeof(reg), 0);
	270	if (err < 0)
	271	return err;
	272
2ef0b7cf	273	// Start multiplexing PCM samples on packets.
35efa5c4 TS	274	reg = cpu_to_be32(0x00000001);
	275	return snd_fw_transaction(tscm->unit,
	276	TCODE_WRITE_QUADLET_REQUEST,
	277	TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_ON,
	278	&reg, sizeof(reg), 0);
	279	}
	280
810b37ff TS	281	static int keep_resources(struct snd_tscm *tscm, unsigned int rate,
810b37ff TS	282	struct amdtp_stream *stream)
35efa5c4	283	{
810b37ff	284	struct fw_iso_resources *resources;
35efa5c4 TS	285	int err;
35efa5c4 TS	286
810b37ff TS	287	if (stream == &tscm->tx_stream)
	288	resources = &tscm->tx_resources;
	289	else
	290	resources = &tscm->rx_resources;
35efa5c4	291
810b37ff	292	err = amdtp_tscm_set_parameters(stream, rate);
35efa5c4 TS	293	if (err < 0)
	294	return err;
	295
810b37ff TS	296	return fw_iso_resources_allocate(resources,
	297	amdtp_stream_get_max_payload(stream),
	298	fw_parent_device(tscm->unit)->max_speed);
35efa5c4 TS	299	}
35efa5c4 TS	300
5f9625a5	301	static int init_stream(struct snd_tscm tscm, struct amdtp_stream s)
35efa5c4	302	{
5f9625a5 TS	303	struct fw_iso_resources *resources;
5f9625a5 TS	304	enum amdtp_stream_direction dir;
35efa5c4 TS	305	unsigned int pcm_channels;
	306	int err;
	307
5f9625a5 TS	308	if (s == &tscm->tx_stream) {
	309	resources = &tscm->tx_resources;
	310	dir = AMDTP_IN_STREAM;
	311	pcm_channels = tscm->spec->pcm_capture_analog_channels;
	312	} else {
	313	resources = &tscm->rx_resources;
	314	dir = AMDTP_OUT_STREAM;
	315	pcm_channels = tscm->spec->pcm_playback_analog_channels;
	316	}
	317
35efa5c4 TS	318	if (tscm->spec->has_adat)
	319	pcm_channels += 8;
	320	if (tscm->spec->has_spdif)
	321	pcm_channels += 2;
5f9625a5 TS	322
5f9625a5 TS	323	err = fw_iso_resources_init(resources, tscm->unit);
35efa5c4 TS	324	if (err < 0)
	325	return err;
	326
5f9625a5	327	err = amdtp_tscm_init(s, tscm->unit, dir, pcm_channels);
35efa5c4	328	if (err < 0)
5f9625a5 TS	329	fw_iso_resources_free(resources);
	330
	331	return err;
	332	}
	333
	334	static void destroy_stream(struct snd_tscm tscm, struct amdtp_stream s)
	335	{
	336	amdtp_stream_destroy(s);
	337
	338	if (s == &tscm->tx_stream)
	339	fw_iso_resources_destroy(&tscm->tx_resources);
	340	else
	341	fw_iso_resources_destroy(&tscm->rx_resources);
	342	}
	343
	344	int snd_tscm_stream_init_duplex(struct snd_tscm *tscm)
	345	{
	346	int err;
	347
	348	err = init_stream(tscm, &tscm->tx_stream);
35efa5c4	349	if (err < 0)
35efa5c4	350	return err;
5f9625a5 TS	351
5f9625a5 TS	352	err = init_stream(tscm, &tscm->rx_stream);
c281d46a TS	353	if (err < 0) {
	354	destroy_stream(tscm, &tscm->tx_stream);
	355	return err;
	356	}
	357
	358	err = amdtp_domain_init(&tscm->domain);
	359	if (err < 0) {
5f9625a5	360	destroy_stream(tscm, &tscm->tx_stream);
c281d46a TS	361	destroy_stream(tscm, &tscm->rx_stream);
c281d46a TS	362	}
35efa5c4	363
6a2a2f45	364	return err;
35efa5c4 TS	365	}
35efa5c4 TS	366
a0c049a6	367	// At bus reset, streaming is stopped and some registers are clear.
35efa5c4 TS	368	void snd_tscm_stream_update_duplex(struct snd_tscm *tscm)
35efa5c4 TS	369	{
c281d46a	370	amdtp_domain_stop(&tscm->domain);
35efa5c4	371
c281d46a	372	amdtp_stream_pcm_abort(&tscm->tx_stream);
35efa5c4	373	amdtp_stream_pcm_abort(&tscm->rx_stream);
35efa5c4 TS	374	}
35efa5c4 TS	375
5f9625a5 TS	376	// This function should be called before starting streams or after stopping
5f9625a5 TS	377	// streams.
35efa5c4 TS	378	void snd_tscm_stream_destroy_duplex(struct snd_tscm *tscm)
35efa5c4 TS	379	{
c281d46a	380	amdtp_domain_destroy(&tscm->domain);
35efa5c4	381
5f9625a5 TS	382	destroy_stream(tscm, &tscm->rx_stream);
5f9625a5 TS	383	destroy_stream(tscm, &tscm->tx_stream);
35efa5c4 TS	384	}
35efa5c4 TS	385
262542ed	386	int snd_tscm_stream_reserve_duplex(struct snd_tscm *tscm, unsigned int rate,
128307d5 TS	387	unsigned int frames_per_period,
128307d5 TS	388	unsigned int frames_per_buffer)
35efa5c4 TS	389	{
	390	unsigned int curr_rate;
	391	int err;
	392
35efa5c4 TS	393	err = snd_tscm_stream_get_rate(tscm, &curr_rate);
	394	if (err < 0)
	395	return err;
35efa5c4	396
07b26642	397	if (tscm->substreams_counter == 0 \|\| rate != curr_rate) {
c281d46a TS	398	amdtp_domain_stop(&tscm->domain);
c281d46a TS	399
07b26642 TS	400	finish_session(tscm);
07b26642 TS	401
a364af2e TS	402	fw_iso_resources_free(&tscm->tx_resources);
a364af2e TS	403	fw_iso_resources_free(&tscm->rx_resources);
35efa5c4	404
07b26642 TS	405	err = set_clock(tscm, rate, INT_MAX);
	406	if (err < 0)
	407	return err;
	408
810b37ff TS	409	err = keep_resources(tscm, rate, &tscm->tx_stream);
810b37ff TS	410	if (err < 0)
07b26642	411	return err;
810b37ff TS	412
810b37ff TS	413	err = keep_resources(tscm, rate, &tscm->rx_stream);
07b26642 TS	414	if (err < 0) {
	415	fw_iso_resources_free(&tscm->tx_resources);
	416	return err;
	417	}
262542ed TS	418
262542ed TS	419	err = amdtp_domain_set_events_per_period(&tscm->domain,
128307d5	420	frames_per_period, frames_per_buffer);
262542ed TS	421	if (err < 0) {
	422	fw_iso_resources_free(&tscm->tx_resources);
	423	fw_iso_resources_free(&tscm->rx_resources);
	424	return err;
	425	}
a9dd8a61 TS	426
a9dd8a61 TS	427	tscm->need_long_tx_init_skip = (rate != curr_rate);
07b26642 TS	428	}
	429
	430	return 0;
	431	}
	432
07b26642 TS	433	int snd_tscm_stream_start_duplex(struct snd_tscm *tscm, unsigned int rate)
07b26642 TS	434	{
a0c049a6	435	unsigned int generation = tscm->rx_resources.generation;
07b26642 TS	436	int err;
	437
	438	if (tscm->substreams_counter == 0)
	439	return 0;
	440
	441	if (amdtp_streaming_error(&tscm->rx_stream) \|\|
c281d46a TS	442	amdtp_streaming_error(&tscm->tx_stream)) {
c281d46a TS	443	amdtp_domain_stop(&tscm->domain);
07b26642	444	finish_session(tscm);
c281d46a	445	}
07b26642	446
a0c049a6 TS	447	if (generation != fw_parent_device(tscm->unit)->card->generation) {
	448	err = fw_iso_resources_update(&tscm->tx_resources);
	449	if (err < 0)
	450	goto error;
	451
	452	err = fw_iso_resources_update(&tscm->rx_resources);
	453	if (err < 0)
	454	goto error;
	455	}
	456
07b26642	457	if (!amdtp_stream_running(&tscm->rx_stream)) {
c281d46a	458	int spd = fw_parent_device(tscm->unit)->max_speed;
a9dd8a61	459	unsigned int tx_init_skip_cycles;
c281d46a	460
35efa5c4 TS	461	err = set_stream_formats(tscm, rate);
	462	if (err < 0)
	463	goto error;
	464
	465	err = begin_session(tscm);
	466	if (err < 0)
	467	goto error;
	468
c281d46a TS	469	err = amdtp_domain_add_stream(&tscm->domain, &tscm->rx_stream,
c281d46a TS	470	tscm->rx_resources.channel, spd);
35efa5c4 TS	471	if (err < 0)
	472	goto error;
	473
c281d46a TS	474	err = amdtp_domain_add_stream(&tscm->domain, &tscm->tx_stream,
	475	tscm->tx_resources.channel, spd);
	476	if (err < 0)
35efa5c4	477	goto error;
35efa5c4	478
a9dd8a61 TS	479	if (tscm->need_long_tx_init_skip)
	480	tx_init_skip_cycles = 16000;
	481	else
	482	tx_init_skip_cycles = 0;
	483
	484	// MEMO: Just after starting packet streaming, it transfers packets without any
	485	// event. Enough after receiving the sequence of packets, it multiplexes events into
	486	// the packet. However, just after changing sampling transfer frequency, it stops
	487	// multiplexing during packet transmission. Enough after, it restarts multiplexing
	488	// again. The device ignores presentation time expressed by the value of syt field
	489	// of CIP header in received packets. The sequence of the number of data blocks per
	490	// packet is important for media clock recovery.
	491	err = amdtp_domain_start(&tscm->domain, tx_init_skip_cycles, true, true);
35efa5c4	492	if (err < 0)
fb4a624f	493	goto error;
35efa5c4	494
bdaedca7	495	if (!amdtp_domain_wait_ready(&tscm->domain, READY_TIMEOUT_MS)) {
35efa5c4 TS	496	err = -ETIMEDOUT;
	497	goto error;
	498	}
	499	}
	500
	501	return 0;
	502	error:
c281d46a	503	amdtp_domain_stop(&tscm->domain);
35efa5c4	504	finish_session(tscm);
a364af2e	505
35efa5c4 TS	506	return err;
	507	}
	508
	509	void snd_tscm_stream_stop_duplex(struct snd_tscm *tscm)
	510	{
9628fc82	511	if (tscm->substreams_counter == 0) {
c281d46a	512	amdtp_domain_stop(&tscm->domain);
07b26642	513	finish_session(tscm);
9628fc82 TS	514
	515	fw_iso_resources_free(&tscm->tx_resources);
	516	fw_iso_resources_free(&tscm->rx_resources);
a9dd8a61 TS	517
a9dd8a61 TS	518	tscm->need_long_tx_init_skip = false;
9628fc82	519	}
35efa5c4	520	}
e5e0c3dd TS	521
	522	void snd_tscm_stream_lock_changed(struct snd_tscm *tscm)
	523	{
	524	tscm->dev_lock_changed = true;
	525	wake_up(&tscm->hwdep_wait);
	526	}
	527
	528	int snd_tscm_stream_lock_try(struct snd_tscm *tscm)
	529	{
	530	int err;
	531
	532	spin_lock_irq(&tscm->lock);
	533
	534	/* user land lock this */
	535	if (tscm->dev_lock_count < 0) {
	536	err = -EBUSY;
	537	goto end;
	538	}
	539
	540	/* this is the first time */
	541	if (tscm->dev_lock_count++ == 0)
	542	snd_tscm_stream_lock_changed(tscm);
	543	err = 0;
	544	end:
	545	spin_unlock_irq(&tscm->lock);
	546	return err;
	547	}
	548
	549	void snd_tscm_stream_lock_release(struct snd_tscm *tscm)
	550	{
	551	spin_lock_irq(&tscm->lock);
	552
	553	if (WARN_ON(tscm->dev_lock_count <= 0))
	554	goto end;
	555	if (--tscm->dev_lock_count == 0)
	556	snd_tscm_stream_lock_changed(tscm);
	557	end:
	558	spin_unlock_irq(&tscm->lock);
	559	}