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719f82d3 EB |
1 | /****************************************************************************** |
2 | ||
3 | AudioScience HPI driver | |
4 | Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com> | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of version 2 of the GNU General Public License as | |
8 | published by the Free Software Foundation; | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ||
19 | Hardware Programming Interface (HPI) for AudioScience | |
20 | ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters. | |
21 | These PCI and PCIe bus adapters are based on a | |
22 | TMS320C6205 PCI bus mastering DSP, | |
23 | and (except ASI50xx) TI TMS320C6xxx floating point DSP | |
24 | ||
25 | Exported function: | |
26 | void HPI_6205(struct hpi_message *phm, struct hpi_response *phr) | |
27 | ||
28 | (C) Copyright AudioScience Inc. 1998-2010 | |
29 | *******************************************************************************/ | |
30 | #define SOURCEFILE_NAME "hpi6205.c" | |
31 | ||
32 | #include "hpi_internal.h" | |
33 | #include "hpimsginit.h" | |
34 | #include "hpidebug.h" | |
35 | #include "hpi6205.h" | |
36 | #include "hpidspcd.h" | |
37 | #include "hpicmn.h" | |
38 | ||
39 | /*****************************************************************************/ | |
40 | /* HPI6205 specific error codes */ | |
deb21a23 | 41 | #define HPI6205_ERROR_BASE 1000 /* not actually used anywhere */ |
3285ea10 EB |
42 | |
43 | /* operational/messaging errors */ | |
44 | #define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015 | |
45 | #define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016 | |
46 | ||
47 | /* initialization/bootload errors */ | |
719f82d3 EB |
48 | #define HPI6205_ERROR_6205_NO_IRQ 1002 |
49 | #define HPI6205_ERROR_6205_INIT_FAILED 1003 | |
719f82d3 EB |
50 | #define HPI6205_ERROR_6205_REG 1006 |
51 | #define HPI6205_ERROR_6205_DSPPAGE 1007 | |
719f82d3 EB |
52 | #define HPI6205_ERROR_C6713_HPIC 1009 |
53 | #define HPI6205_ERROR_C6713_HPIA 1010 | |
54 | #define HPI6205_ERROR_C6713_PLL 1011 | |
55 | #define HPI6205_ERROR_DSP_INTMEM 1012 | |
56 | #define HPI6205_ERROR_DSP_EXTMEM 1013 | |
57 | #define HPI6205_ERROR_DSP_PLD 1014 | |
719f82d3 EB |
58 | #define HPI6205_ERROR_6205_EEPROM 1017 |
59 | #define HPI6205_ERROR_DSP_EMIF 1018 | |
60 | ||
719f82d3 EB |
61 | /*****************************************************************************/ |
62 | /* for C6205 PCI i/f */ | |
63 | /* Host Status Register (HSR) bitfields */ | |
64 | #define C6205_HSR_INTSRC 0x01 | |
65 | #define C6205_HSR_INTAVAL 0x02 | |
66 | #define C6205_HSR_INTAM 0x04 | |
67 | #define C6205_HSR_CFGERR 0x08 | |
68 | #define C6205_HSR_EEREAD 0x10 | |
69 | /* Host-to-DSP Control Register (HDCR) bitfields */ | |
70 | #define C6205_HDCR_WARMRESET 0x01 | |
71 | #define C6205_HDCR_DSPINT 0x02 | |
72 | #define C6205_HDCR_PCIBOOT 0x04 | |
73 | /* DSP Page Register (DSPP) bitfields, */ | |
74 | /* defines 4 Mbyte page that BAR0 points to */ | |
75 | #define C6205_DSPP_MAP1 0x400 | |
76 | ||
77 | /* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP. | |
78 | * BAR1 maps to non-prefetchable 8 Mbyte memory block | |
79 | * of DSP memory mapped registers (starting at 0x01800000). | |
80 | * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this | |
81 | * needs to be added to the BAR1 base address set in the PCI config reg | |
82 | */ | |
83 | #define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L) | |
84 | #define C6205_BAR1_HSR (C6205_BAR1_PCI_IO_OFFSET) | |
85 | #define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4) | |
86 | #define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8) | |
87 | ||
88 | /* used to control LED (revA) and reset C6713 (revB) */ | |
89 | #define C6205_BAR0_TIMER1_CTL (0x01980000L) | |
90 | ||
91 | /* For first 6713 in CE1 space, using DA17,16,2 */ | |
92 | #define HPICL_ADDR 0x01400000L | |
93 | #define HPICH_ADDR 0x01400004L | |
94 | #define HPIAL_ADDR 0x01410000L | |
95 | #define HPIAH_ADDR 0x01410004L | |
96 | #define HPIDIL_ADDR 0x01420000L | |
97 | #define HPIDIH_ADDR 0x01420004L | |
98 | #define HPIDL_ADDR 0x01430000L | |
99 | #define HPIDH_ADDR 0x01430004L | |
100 | ||
101 | #define C6713_EMIF_GCTL 0x01800000 | |
102 | #define C6713_EMIF_CE1 0x01800004 | |
103 | #define C6713_EMIF_CE0 0x01800008 | |
104 | #define C6713_EMIF_CE2 0x01800010 | |
105 | #define C6713_EMIF_CE3 0x01800014 | |
106 | #define C6713_EMIF_SDRAMCTL 0x01800018 | |
107 | #define C6713_EMIF_SDRAMTIMING 0x0180001C | |
108 | #define C6713_EMIF_SDRAMEXT 0x01800020 | |
109 | ||
110 | struct hpi_hw_obj { | |
111 | /* PCI registers */ | |
112 | __iomem u32 *prHSR; | |
113 | __iomem u32 *prHDCR; | |
114 | __iomem u32 *prDSPP; | |
115 | ||
116 | u32 dsp_page; | |
117 | ||
118 | struct consistent_dma_area h_locked_mem; | |
119 | struct bus_master_interface *p_interface_buffer; | |
120 | ||
121 | u16 flag_outstream_just_reset[HPI_MAX_STREAMS]; | |
122 | /* a non-NULL handle means there is an HPI allocated buffer */ | |
123 | struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS]; | |
124 | struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS]; | |
125 | /* non-zero size means a buffer exists, may be external */ | |
126 | u32 instream_host_buffer_size[HPI_MAX_STREAMS]; | |
127 | u32 outstream_host_buffer_size[HPI_MAX_STREAMS]; | |
128 | ||
129 | struct consistent_dma_area h_control_cache; | |
719f82d3 EB |
130 | struct hpi_control_cache *p_cache; |
131 | }; | |
132 | ||
133 | /*****************************************************************************/ | |
134 | /* local prototypes */ | |
135 | ||
136 | #define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write) | |
137 | ||
138 | static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us); | |
139 | ||
140 | static void send_dsp_command(struct hpi_hw_obj *phw, int cmd); | |
141 | ||
142 | static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao, | |
143 | u32 *pos_error_code); | |
144 | ||
145 | static u16 message_response_sequence(struct hpi_adapter_obj *pao, | |
146 | struct hpi_message *phm, struct hpi_response *phr); | |
147 | ||
148 | static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, | |
149 | struct hpi_response *phr); | |
150 | ||
151 | #define HPI6205_TIMEOUT 1000000 | |
152 | ||
153 | static void subsys_create_adapter(struct hpi_message *phm, | |
154 | struct hpi_response *phr); | |
155 | static void subsys_delete_adapter(struct hpi_message *phm, | |
156 | struct hpi_response *phr); | |
157 | ||
158 | static u16 create_adapter_obj(struct hpi_adapter_obj *pao, | |
159 | u32 *pos_error_code); | |
160 | ||
161 | static void delete_adapter_obj(struct hpi_adapter_obj *pao); | |
162 | ||
163 | static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao, | |
164 | struct hpi_message *phm, struct hpi_response *phr); | |
165 | ||
166 | static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao, | |
167 | struct hpi_message *phm, struct hpi_response *phr); | |
168 | ||
169 | static void outstream_host_buffer_free(struct hpi_adapter_obj *pao, | |
170 | struct hpi_message *phm, struct hpi_response *phr); | |
171 | static void outstream_write(struct hpi_adapter_obj *pao, | |
172 | struct hpi_message *phm, struct hpi_response *phr); | |
173 | ||
174 | static void outstream_get_info(struct hpi_adapter_obj *pao, | |
175 | struct hpi_message *phm, struct hpi_response *phr); | |
176 | ||
177 | static void outstream_start(struct hpi_adapter_obj *pao, | |
178 | struct hpi_message *phm, struct hpi_response *phr); | |
179 | ||
180 | static void outstream_open(struct hpi_adapter_obj *pao, | |
181 | struct hpi_message *phm, struct hpi_response *phr); | |
182 | ||
183 | static void outstream_reset(struct hpi_adapter_obj *pao, | |
184 | struct hpi_message *phm, struct hpi_response *phr); | |
185 | ||
186 | static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao, | |
187 | struct hpi_message *phm, struct hpi_response *phr); | |
188 | ||
189 | static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao, | |
190 | struct hpi_message *phm, struct hpi_response *phr); | |
191 | ||
192 | static void instream_host_buffer_free(struct hpi_adapter_obj *pao, | |
193 | struct hpi_message *phm, struct hpi_response *phr); | |
194 | ||
195 | static void instream_read(struct hpi_adapter_obj *pao, | |
196 | struct hpi_message *phm, struct hpi_response *phr); | |
197 | ||
198 | static void instream_get_info(struct hpi_adapter_obj *pao, | |
199 | struct hpi_message *phm, struct hpi_response *phr); | |
200 | ||
201 | static void instream_start(struct hpi_adapter_obj *pao, | |
202 | struct hpi_message *phm, struct hpi_response *phr); | |
203 | ||
204 | static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index, | |
205 | u32 address); | |
206 | ||
3285ea10 EB |
207 | static void boot_loader_write_mem32(struct hpi_adapter_obj *pao, |
208 | int dsp_index, u32 address, u32 data); | |
719f82d3 EB |
209 | |
210 | static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, | |
211 | int dsp_index); | |
212 | ||
213 | static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index, | |
214 | u32 address, u32 length); | |
215 | ||
216 | static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao, | |
217 | int dsp_index); | |
218 | ||
219 | static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao, | |
220 | int dsp_index); | |
221 | ||
222 | static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index); | |
223 | ||
224 | /*****************************************************************************/ | |
225 | ||
226 | static void subsys_message(struct hpi_message *phm, struct hpi_response *phr) | |
227 | { | |
719f82d3 | 228 | switch (phm->function) { |
719f82d3 EB |
229 | case HPI_SUBSYS_CREATE_ADAPTER: |
230 | subsys_create_adapter(phm, phr); | |
231 | break; | |
232 | case HPI_SUBSYS_DELETE_ADAPTER: | |
233 | subsys_delete_adapter(phm, phr); | |
234 | break; | |
235 | default: | |
236 | phr->error = HPI_ERROR_INVALID_FUNC; | |
237 | break; | |
238 | } | |
239 | } | |
240 | ||
241 | static void control_message(struct hpi_adapter_obj *pao, | |
242 | struct hpi_message *phm, struct hpi_response *phr) | |
243 | { | |
244 | ||
245 | struct hpi_hw_obj *phw = pao->priv; | |
3285ea10 | 246 | u16 pending_cache_error = 0; |
719f82d3 EB |
247 | |
248 | switch (phm->function) { | |
249 | case HPI_CONTROL_GET_STATE: | |
250 | if (pao->has_control_cache) { | |
3285ea10 EB |
251 | rmb(); /* make sure we see updates DMAed from DSP */ |
252 | if (hpi_check_control_cache(phw->p_cache, phm, phr)) { | |
719f82d3 | 253 | break; |
3285ea10 EB |
254 | } else if (phm->u.c.attribute == HPI_METER_PEAK) { |
255 | pending_cache_error = | |
256 | HPI_ERROR_CONTROL_CACHING; | |
257 | } | |
719f82d3 EB |
258 | } |
259 | hw_message(pao, phm, phr); | |
3285ea10 EB |
260 | if (pending_cache_error && !phr->error) |
261 | phr->error = pending_cache_error; | |
719f82d3 EB |
262 | break; |
263 | case HPI_CONTROL_GET_INFO: | |
264 | hw_message(pao, phm, phr); | |
265 | break; | |
266 | case HPI_CONTROL_SET_STATE: | |
267 | hw_message(pao, phm, phr); | |
268 | if (pao->has_control_cache) | |
3285ea10 EB |
269 | hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm, |
270 | phr); | |
719f82d3 EB |
271 | break; |
272 | default: | |
273 | phr->error = HPI_ERROR_INVALID_FUNC; | |
274 | break; | |
275 | } | |
276 | } | |
277 | ||
278 | static void adapter_message(struct hpi_adapter_obj *pao, | |
279 | struct hpi_message *phm, struct hpi_response *phr) | |
280 | { | |
281 | switch (phm->function) { | |
282 | default: | |
283 | hw_message(pao, phm, phr); | |
284 | break; | |
285 | } | |
286 | } | |
287 | ||
288 | static void outstream_message(struct hpi_adapter_obj *pao, | |
289 | struct hpi_message *phm, struct hpi_response *phr) | |
290 | { | |
291 | ||
292 | if (phm->obj_index >= HPI_MAX_STREAMS) { | |
deb21a23 | 293 | phr->error = HPI_ERROR_INVALID_OBJ_INDEX; |
719f82d3 | 294 | HPI_DEBUG_LOG(WARNING, |
3285ea10 | 295 | "Message referencing invalid stream %d " |
719f82d3 EB |
296 | "on adapter index %d\n", phm->obj_index, |
297 | phm->adapter_index); | |
298 | return; | |
299 | } | |
300 | ||
301 | switch (phm->function) { | |
302 | case HPI_OSTREAM_WRITE: | |
303 | outstream_write(pao, phm, phr); | |
304 | break; | |
305 | case HPI_OSTREAM_GET_INFO: | |
306 | outstream_get_info(pao, phm, phr); | |
307 | break; | |
308 | case HPI_OSTREAM_HOSTBUFFER_ALLOC: | |
309 | outstream_host_buffer_allocate(pao, phm, phr); | |
310 | break; | |
311 | case HPI_OSTREAM_HOSTBUFFER_GET_INFO: | |
312 | outstream_host_buffer_get_info(pao, phm, phr); | |
313 | break; | |
314 | case HPI_OSTREAM_HOSTBUFFER_FREE: | |
315 | outstream_host_buffer_free(pao, phm, phr); | |
316 | break; | |
317 | case HPI_OSTREAM_START: | |
318 | outstream_start(pao, phm, phr); | |
319 | break; | |
320 | case HPI_OSTREAM_OPEN: | |
321 | outstream_open(pao, phm, phr); | |
322 | break; | |
323 | case HPI_OSTREAM_RESET: | |
324 | outstream_reset(pao, phm, phr); | |
325 | break; | |
326 | default: | |
327 | hw_message(pao, phm, phr); | |
328 | break; | |
329 | } | |
330 | } | |
331 | ||
332 | static void instream_message(struct hpi_adapter_obj *pao, | |
333 | struct hpi_message *phm, struct hpi_response *phr) | |
334 | { | |
335 | ||
336 | if (phm->obj_index >= HPI_MAX_STREAMS) { | |
deb21a23 | 337 | phr->error = HPI_ERROR_INVALID_OBJ_INDEX; |
719f82d3 | 338 | HPI_DEBUG_LOG(WARNING, |
3285ea10 | 339 | "Message referencing invalid stream %d " |
719f82d3 EB |
340 | "on adapter index %d\n", phm->obj_index, |
341 | phm->adapter_index); | |
342 | return; | |
343 | } | |
344 | ||
345 | switch (phm->function) { | |
346 | case HPI_ISTREAM_READ: | |
347 | instream_read(pao, phm, phr); | |
348 | break; | |
349 | case HPI_ISTREAM_GET_INFO: | |
350 | instream_get_info(pao, phm, phr); | |
351 | break; | |
352 | case HPI_ISTREAM_HOSTBUFFER_ALLOC: | |
353 | instream_host_buffer_allocate(pao, phm, phr); | |
354 | break; | |
355 | case HPI_ISTREAM_HOSTBUFFER_GET_INFO: | |
356 | instream_host_buffer_get_info(pao, phm, phr); | |
357 | break; | |
358 | case HPI_ISTREAM_HOSTBUFFER_FREE: | |
359 | instream_host_buffer_free(pao, phm, phr); | |
360 | break; | |
361 | case HPI_ISTREAM_START: | |
362 | instream_start(pao, phm, phr); | |
363 | break; | |
364 | default: | |
365 | hw_message(pao, phm, phr); | |
366 | break; | |
367 | } | |
368 | } | |
369 | ||
370 | /*****************************************************************************/ | |
371 | /** Entry point to this HPI backend | |
372 | * All calls to the HPI start here | |
373 | */ | |
374 | void HPI_6205(struct hpi_message *phm, struct hpi_response *phr) | |
375 | { | |
376 | struct hpi_adapter_obj *pao = NULL; | |
377 | ||
378 | /* subsytem messages are processed by every HPI. | |
379 | * All other messages are ignored unless the adapter index matches | |
380 | * an adapter in the HPI | |
381 | */ | |
3285ea10 EB |
382 | /* HPI_DEBUG_LOG(DEBUG, "HPI Obj=%d, Func=%d\n", phm->wObject, |
383 | phm->wFunction); */ | |
719f82d3 EB |
384 | |
385 | /* if Dsp has crashed then do not communicate with it any more */ | |
386 | if (phm->object != HPI_OBJ_SUBSYSTEM) { | |
387 | pao = hpi_find_adapter(phm->adapter_index); | |
388 | if (!pao) { | |
389 | HPI_DEBUG_LOG(DEBUG, | |
390 | " %d,%d refused, for another HPI?\n", | |
391 | phm->object, phm->function); | |
392 | return; | |
393 | } | |
394 | ||
395 | if ((pao->dsp_crashed >= 10) | |
396 | && (phm->function != HPI_ADAPTER_DEBUG_READ)) { | |
397 | /* allow last resort debug read even after crash */ | |
398 | hpi_init_response(phr, phm->object, phm->function, | |
399 | HPI_ERROR_DSP_HARDWARE); | |
400 | HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n", | |
401 | phm->object, phm->function); | |
402 | return; | |
403 | } | |
404 | } | |
405 | ||
406 | /* Init default response */ | |
407 | if (phm->function != HPI_SUBSYS_CREATE_ADAPTER) | |
3285ea10 | 408 | phr->error = HPI_ERROR_PROCESSING_MESSAGE; |
719f82d3 EB |
409 | |
410 | HPI_DEBUG_LOG(VERBOSE, "start of switch\n"); | |
411 | switch (phm->type) { | |
412 | case HPI_TYPE_MESSAGE: | |
413 | switch (phm->object) { | |
414 | case HPI_OBJ_SUBSYSTEM: | |
415 | subsys_message(phm, phr); | |
416 | break; | |
417 | ||
418 | case HPI_OBJ_ADAPTER: | |
719f82d3 EB |
419 | adapter_message(pao, phm, phr); |
420 | break; | |
421 | ||
422 | case HPI_OBJ_CONTROLEX: | |
423 | case HPI_OBJ_CONTROL: | |
424 | control_message(pao, phm, phr); | |
425 | break; | |
426 | ||
427 | case HPI_OBJ_OSTREAM: | |
428 | outstream_message(pao, phm, phr); | |
429 | break; | |
430 | ||
431 | case HPI_OBJ_ISTREAM: | |
432 | instream_message(pao, phm, phr); | |
433 | break; | |
434 | ||
435 | default: | |
436 | hw_message(pao, phm, phr); | |
437 | break; | |
438 | } | |
439 | break; | |
440 | ||
441 | default: | |
442 | phr->error = HPI_ERROR_INVALID_TYPE; | |
443 | break; | |
444 | } | |
445 | } | |
446 | ||
447 | /*****************************************************************************/ | |
448 | /* SUBSYSTEM */ | |
449 | ||
450 | /** Create an adapter object and initialise it based on resource information | |
451 | * passed in in the message | |
452 | * *** NOTE - you cannot use this function AND the FindAdapters function at the | |
453 | * same time, the application must use only one of them to get the adapters *** | |
454 | */ | |
455 | static void subsys_create_adapter(struct hpi_message *phm, | |
456 | struct hpi_response *phr) | |
457 | { | |
458 | /* create temp adapter obj, because we don't know what index yet */ | |
459 | struct hpi_adapter_obj ao; | |
460 | u32 os_error_code; | |
461 | u16 err; | |
462 | ||
463 | HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n"); | |
464 | ||
465 | memset(&ao, 0, sizeof(ao)); | |
466 | ||
550a8b69 | 467 | ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL); |
719f82d3 | 468 | if (!ao.priv) { |
25985edc | 469 | HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n"); |
719f82d3 EB |
470 | phr->error = HPI_ERROR_MEMORY_ALLOC; |
471 | return; | |
472 | } | |
719f82d3 EB |
473 | |
474 | ao.pci = *phm->u.s.resource.r.pci; | |
475 | err = create_adapter_obj(&ao, &os_error_code); | |
719f82d3 | 476 | if (err) { |
719f82d3 | 477 | delete_adapter_obj(&ao); |
0a00044d EB |
478 | if (err >= HPI_ERROR_BACKEND_BASE) { |
479 | phr->error = HPI_ERROR_DSP_BOOTLOAD; | |
480 | phr->specific_error = err; | |
481 | } else { | |
482 | phr->error = err; | |
483 | } | |
3285ea10 | 484 | phr->u.s.data = os_error_code; |
719f82d3 EB |
485 | return; |
486 | } | |
487 | ||
2f918a64 | 488 | phr->u.s.adapter_type = ao.adapter_type; |
719f82d3 | 489 | phr->u.s.adapter_index = ao.index; |
719f82d3 EB |
490 | phr->error = 0; |
491 | } | |
492 | ||
493 | /** delete an adapter - required by WDM driver */ | |
494 | static void subsys_delete_adapter(struct hpi_message *phm, | |
495 | struct hpi_response *phr) | |
496 | { | |
497 | struct hpi_adapter_obj *pao; | |
498 | struct hpi_hw_obj *phw; | |
499 | ||
3285ea10 | 500 | pao = hpi_find_adapter(phm->obj_index); |
719f82d3 EB |
501 | if (!pao) { |
502 | phr->error = HPI_ERROR_INVALID_OBJ_INDEX; | |
503 | return; | |
504 | } | |
505 | phw = (struct hpi_hw_obj *)pao->priv; | |
506 | /* reset adapter h/w */ | |
507 | /* Reset C6713 #1 */ | |
508 | boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0); | |
509 | /* reset C6205 */ | |
510 | iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR); | |
511 | ||
512 | delete_adapter_obj(pao); | |
3285ea10 | 513 | hpi_delete_adapter(pao); |
719f82d3 EB |
514 | phr->error = 0; |
515 | } | |
516 | ||
517 | /** Create adapter object | |
518 | allocate buffers, bootload DSPs, initialise control cache | |
519 | */ | |
520 | static u16 create_adapter_obj(struct hpi_adapter_obj *pao, | |
521 | u32 *pos_error_code) | |
522 | { | |
523 | struct hpi_hw_obj *phw = pao->priv; | |
524 | struct bus_master_interface *interface; | |
525 | u32 phys_addr; | |
719f82d3 EB |
526 | int i; |
527 | u16 err; | |
528 | ||
529 | /* init error reporting */ | |
530 | pao->dsp_crashed = 0; | |
531 | ||
532 | for (i = 0; i < HPI_MAX_STREAMS; i++) | |
533 | phw->flag_outstream_just_reset[i] = 1; | |
534 | ||
535 | /* The C6205 memory area 1 is 8Mbyte window into DSP registers */ | |
536 | phw->prHSR = | |
537 | pao->pci.ap_mem_base[1] + | |
538 | C6205_BAR1_HSR / sizeof(*pao->pci.ap_mem_base[1]); | |
539 | phw->prHDCR = | |
540 | pao->pci.ap_mem_base[1] + | |
541 | C6205_BAR1_HDCR / sizeof(*pao->pci.ap_mem_base[1]); | |
542 | phw->prDSPP = | |
543 | pao->pci.ap_mem_base[1] + | |
544 | C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]); | |
545 | ||
546 | pao->has_control_cache = 0; | |
547 | ||
548 | if (hpios_locked_mem_alloc(&phw->h_locked_mem, | |
549 | sizeof(struct bus_master_interface), | |
3285ea10 | 550 | pao->pci.pci_dev)) |
719f82d3 EB |
551 | phw->p_interface_buffer = NULL; |
552 | else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem, | |
553 | (void *)&phw->p_interface_buffer)) | |
554 | phw->p_interface_buffer = NULL; | |
555 | ||
556 | HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n", | |
557 | phw->p_interface_buffer); | |
558 | ||
559 | if (phw->p_interface_buffer) { | |
560 | memset((void *)phw->p_interface_buffer, 0, | |
561 | sizeof(struct bus_master_interface)); | |
562 | phw->p_interface_buffer->dsp_ack = H620_HIF_UNKNOWN; | |
563 | } | |
564 | ||
565 | err = adapter_boot_load_dsp(pao, pos_error_code); | |
566 | if (err) | |
567 | /* no need to clean up as SubSysCreateAdapter */ | |
568 | /* calls DeleteAdapter on error. */ | |
569 | return err; | |
570 | ||
571 | HPI_DEBUG_LOG(INFO, "load DSP code OK\n"); | |
572 | ||
573 | /* allow boot load even if mem alloc wont work */ | |
574 | if (!phw->p_interface_buffer) | |
3285ea10 | 575 | return HPI_ERROR_MEMORY_ALLOC; |
719f82d3 EB |
576 | |
577 | interface = phw->p_interface_buffer; | |
578 | ||
719f82d3 EB |
579 | /* make sure the DSP has started ok */ |
580 | if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) { | |
581 | HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n"); | |
3285ea10 | 582 | return HPI6205_ERROR_6205_INIT_FAILED; |
719f82d3 EB |
583 | } |
584 | /* Note that *pao, *phw are zeroed after allocation, | |
585 | * so pointers and flags are NULL by default. | |
586 | * Allocate bus mastering control cache buffer and tell the DSP about it | |
587 | */ | |
588 | if (interface->control_cache.number_of_controls) { | |
3285ea10 | 589 | u8 *p_control_cache_virtual; |
719f82d3 EB |
590 | |
591 | err = hpios_locked_mem_alloc(&phw->h_control_cache, | |
592 | interface->control_cache.size_in_bytes, | |
3285ea10 | 593 | pao->pci.pci_dev); |
719f82d3 EB |
594 | if (!err) |
595 | err = hpios_locked_mem_get_virt_addr(&phw-> | |
3285ea10 EB |
596 | h_control_cache, |
597 | (void *)&p_control_cache_virtual); | |
719f82d3 EB |
598 | if (!err) { |
599 | memset(p_control_cache_virtual, 0, | |
600 | interface->control_cache.size_in_bytes); | |
601 | ||
602 | phw->p_cache = | |
603 | hpi_alloc_control_cache(interface-> | |
604 | control_cache.number_of_controls, | |
605 | interface->control_cache.size_in_bytes, | |
719f82d3 | 606 | p_control_cache_virtual); |
fd0977d0 JJ |
607 | if (!phw->p_cache) |
608 | err = HPI_ERROR_MEMORY_ALLOC; | |
719f82d3 EB |
609 | } |
610 | if (!err) { | |
611 | err = hpios_locked_mem_get_phys_addr(&phw-> | |
612 | h_control_cache, &phys_addr); | |
613 | interface->control_cache.physical_address32 = | |
614 | phys_addr; | |
615 | } | |
616 | ||
617 | if (!err) | |
618 | pao->has_control_cache = 1; | |
619 | else { | |
620 | if (hpios_locked_mem_valid(&phw->h_control_cache)) | |
621 | hpios_locked_mem_free(&phw->h_control_cache); | |
622 | pao->has_control_cache = 0; | |
623 | } | |
624 | } | |
719f82d3 EB |
625 | send_dsp_command(phw, H620_HIF_IDLE); |
626 | ||
627 | { | |
3285ea10 EB |
628 | struct hpi_message hm; |
629 | struct hpi_response hr; | |
719f82d3 EB |
630 | u32 max_streams; |
631 | ||
632 | HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n"); | |
3285ea10 EB |
633 | memset(&hm, 0, sizeof(hm)); |
634 | hm.type = HPI_TYPE_MESSAGE; | |
635 | hm.size = sizeof(hm); | |
636 | hm.object = HPI_OBJ_ADAPTER; | |
637 | hm.function = HPI_ADAPTER_GET_INFO; | |
638 | hm.adapter_index = 0; | |
639 | memset(&hr, 0, sizeof(hr)); | |
640 | hr.size = sizeof(hr); | |
641 | ||
642 | err = message_response_sequence(pao, &hm, &hr); | |
719f82d3 EB |
643 | if (err) { |
644 | HPI_DEBUG_LOG(ERROR, "message transport error %d\n", | |
645 | err); | |
646 | return err; | |
647 | } | |
3285ea10 EB |
648 | if (hr.error) |
649 | return hr.error; | |
719f82d3 | 650 | |
3285ea10 EB |
651 | pao->adapter_type = hr.u.ax.info.adapter_type; |
652 | pao->index = hr.u.ax.info.adapter_index; | |
719f82d3 | 653 | |
3285ea10 EB |
654 | max_streams = |
655 | hr.u.ax.info.num_outstreams + | |
656 | hr.u.ax.info.num_instreams; | |
719f82d3 EB |
657 | |
658 | hpios_locked_mem_prepare((max_streams * 6) / 10, max_streams, | |
3285ea10 | 659 | 65536, pao->pci.pci_dev); |
719f82d3 EB |
660 | |
661 | HPI_DEBUG_LOG(VERBOSE, | |
662 | "got adapter info type %x index %d serial %d\n", | |
3285ea10 EB |
663 | hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index, |
664 | hr.u.ax.info.serial_number); | |
719f82d3 EB |
665 | } |
666 | ||
667 | pao->open = 0; /* upon creation the adapter is closed */ | |
668 | ||
ffdb5787 EB |
669 | if (phw->p_cache) |
670 | phw->p_cache->adap_idx = pao->index; | |
671 | ||
719f82d3 | 672 | HPI_DEBUG_LOG(INFO, "bootload DSP OK\n"); |
3285ea10 EB |
673 | |
674 | return hpi_add_adapter(pao); | |
719f82d3 EB |
675 | } |
676 | ||
677 | /** Free memory areas allocated by adapter | |
678 | * this routine is called from SubSysDeleteAdapter, | |
679 | * and SubSysCreateAdapter if duplicate index | |
680 | */ | |
681 | static void delete_adapter_obj(struct hpi_adapter_obj *pao) | |
682 | { | |
683 | struct hpi_hw_obj *phw; | |
684 | int i; | |
685 | ||
686 | phw = pao->priv; | |
687 | ||
719f82d3 EB |
688 | if (hpios_locked_mem_valid(&phw->h_control_cache)) { |
689 | hpios_locked_mem_free(&phw->h_control_cache); | |
690 | hpi_free_control_cache(phw->p_cache); | |
691 | } | |
692 | ||
693 | if (hpios_locked_mem_valid(&phw->h_locked_mem)) { | |
694 | hpios_locked_mem_free(&phw->h_locked_mem); | |
695 | phw->p_interface_buffer = NULL; | |
696 | } | |
697 | ||
698 | for (i = 0; i < HPI_MAX_STREAMS; i++) | |
699 | if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) { | |
700 | hpios_locked_mem_free(&phw->instream_host_buffers[i]); | |
701 | /*?phw->InStreamHostBuffers[i] = NULL; */ | |
702 | phw->instream_host_buffer_size[i] = 0; | |
703 | } | |
704 | ||
705 | for (i = 0; i < HPI_MAX_STREAMS; i++) | |
706 | if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) { | |
707 | hpios_locked_mem_free(&phw->outstream_host_buffers | |
708 | [i]); | |
709 | phw->outstream_host_buffer_size[i] = 0; | |
710 | } | |
711 | ||
3285ea10 | 712 | hpios_locked_mem_unprepare(pao->pci.pci_dev); |
719f82d3 | 713 | |
719f82d3 EB |
714 | kfree(phw); |
715 | } | |
716 | ||
1d595d2a EB |
717 | /*****************************************************************************/ |
718 | /* Adapter functions */ | |
719 | ||
719f82d3 EB |
720 | /*****************************************************************************/ |
721 | /* OutStream Host buffer functions */ | |
722 | ||
723 | /** Allocate or attach buffer for busmastering | |
724 | */ | |
725 | static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao, | |
726 | struct hpi_message *phm, struct hpi_response *phr) | |
727 | { | |
728 | u16 err = 0; | |
729 | u32 command = phm->u.d.u.buffer.command; | |
730 | struct hpi_hw_obj *phw = pao->priv; | |
731 | struct bus_master_interface *interface = phw->p_interface_buffer; | |
732 | ||
733 | hpi_init_response(phr, phm->object, phm->function, 0); | |
734 | ||
735 | if (command == HPI_BUFFER_CMD_EXTERNAL | |
736 | || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) { | |
737 | /* ALLOC phase, allocate a buffer with power of 2 size, | |
738 | get its bus address for PCI bus mastering | |
739 | */ | |
740 | phm->u.d.u.buffer.buffer_size = | |
741 | roundup_pow_of_two(phm->u.d.u.buffer.buffer_size); | |
742 | /* return old size and allocated size, | |
743 | so caller can detect change */ | |
744 | phr->u.d.u.stream_info.data_available = | |
745 | phw->outstream_host_buffer_size[phm->obj_index]; | |
746 | phr->u.d.u.stream_info.buffer_size = | |
747 | phm->u.d.u.buffer.buffer_size; | |
748 | ||
749 | if (phw->outstream_host_buffer_size[phm->obj_index] == | |
750 | phm->u.d.u.buffer.buffer_size) { | |
751 | /* Same size, no action required */ | |
752 | return; | |
753 | } | |
754 | ||
755 | if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> | |
756 | obj_index])) | |
757 | hpios_locked_mem_free(&phw->outstream_host_buffers | |
758 | [phm->obj_index]); | |
759 | ||
760 | err = hpios_locked_mem_alloc(&phw->outstream_host_buffers | |
761 | [phm->obj_index], phm->u.d.u.buffer.buffer_size, | |
3285ea10 | 762 | pao->pci.pci_dev); |
719f82d3 EB |
763 | |
764 | if (err) { | |
765 | phr->error = HPI_ERROR_INVALID_DATASIZE; | |
766 | phw->outstream_host_buffer_size[phm->obj_index] = 0; | |
767 | return; | |
768 | } | |
769 | ||
770 | err = hpios_locked_mem_get_phys_addr | |
771 | (&phw->outstream_host_buffers[phm->obj_index], | |
772 | &phm->u.d.u.buffer.pci_address); | |
773 | /* get the phys addr into msg for single call alloc caller | |
774 | * needs to do this for split alloc (or use the same message) | |
775 | * return the phy address for split alloc in the respose too | |
776 | */ | |
777 | phr->u.d.u.stream_info.auxiliary_data_available = | |
778 | phm->u.d.u.buffer.pci_address; | |
779 | ||
780 | if (err) { | |
781 | hpios_locked_mem_free(&phw->outstream_host_buffers | |
782 | [phm->obj_index]); | |
783 | phw->outstream_host_buffer_size[phm->obj_index] = 0; | |
784 | phr->error = HPI_ERROR_MEMORY_ALLOC; | |
785 | return; | |
786 | } | |
787 | } | |
788 | ||
789 | if (command == HPI_BUFFER_CMD_EXTERNAL | |
790 | || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) { | |
791 | /* GRANT phase. Set up the BBM status, tell the DSP about | |
792 | the buffer so it can start using BBM. | |
793 | */ | |
794 | struct hpi_hostbuffer_status *status; | |
795 | ||
796 | if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer. | |
797 | buffer_size - 1)) { | |
798 | HPI_DEBUG_LOG(ERROR, | |
3285ea10 | 799 | "Buffer size must be 2^N not %d\n", |
719f82d3 EB |
800 | phm->u.d.u.buffer.buffer_size); |
801 | phr->error = HPI_ERROR_INVALID_DATASIZE; | |
802 | return; | |
803 | } | |
804 | phw->outstream_host_buffer_size[phm->obj_index] = | |
805 | phm->u.d.u.buffer.buffer_size; | |
806 | status = &interface->outstream_host_buffer_status[phm-> | |
807 | obj_index]; | |
808 | status->samples_processed = 0; | |
809 | status->stream_state = HPI_STATE_STOPPED; | |
810 | status->dSP_index = 0; | |
811 | status->host_index = status->dSP_index; | |
812 | status->size_in_bytes = phm->u.d.u.buffer.buffer_size; | |
deb21a23 | 813 | status->auxiliary_data_available = 0; |
719f82d3 EB |
814 | |
815 | hw_message(pao, phm, phr); | |
816 | ||
817 | if (phr->error | |
818 | && hpios_locked_mem_valid(&phw-> | |
819 | outstream_host_buffers[phm->obj_index])) { | |
820 | hpios_locked_mem_free(&phw->outstream_host_buffers | |
821 | [phm->obj_index]); | |
822 | phw->outstream_host_buffer_size[phm->obj_index] = 0; | |
823 | } | |
824 | } | |
825 | } | |
826 | ||
827 | static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao, | |
828 | struct hpi_message *phm, struct hpi_response *phr) | |
829 | { | |
830 | struct hpi_hw_obj *phw = pao->priv; | |
831 | struct bus_master_interface *interface = phw->p_interface_buffer; | |
832 | struct hpi_hostbuffer_status *status; | |
833 | u8 *p_bbm_data; | |
834 | ||
835 | if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> | |
836 | obj_index])) { | |
837 | if (hpios_locked_mem_get_virt_addr(&phw-> | |
838 | outstream_host_buffers[phm->obj_index], | |
839 | (void *)&p_bbm_data)) { | |
840 | phr->error = HPI_ERROR_INVALID_OPERATION; | |
841 | return; | |
842 | } | |
843 | status = &interface->outstream_host_buffer_status[phm-> | |
844 | obj_index]; | |
845 | hpi_init_response(phr, HPI_OBJ_OSTREAM, | |
846 | HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0); | |
847 | phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data; | |
848 | phr->u.d.u.hostbuffer_info.p_status = status; | |
849 | } else { | |
850 | hpi_init_response(phr, HPI_OBJ_OSTREAM, | |
851 | HPI_OSTREAM_HOSTBUFFER_GET_INFO, | |
852 | HPI_ERROR_INVALID_OPERATION); | |
853 | } | |
854 | } | |
855 | ||
856 | static void outstream_host_buffer_free(struct hpi_adapter_obj *pao, | |
857 | struct hpi_message *phm, struct hpi_response *phr) | |
858 | { | |
859 | struct hpi_hw_obj *phw = pao->priv; | |
860 | u32 command = phm->u.d.u.buffer.command; | |
861 | ||
862 | if (phw->outstream_host_buffer_size[phm->obj_index]) { | |
863 | if (command == HPI_BUFFER_CMD_EXTERNAL | |
864 | || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) { | |
865 | phw->outstream_host_buffer_size[phm->obj_index] = 0; | |
866 | hw_message(pao, phm, phr); | |
867 | /* Tell adapter to stop using the host buffer. */ | |
868 | } | |
869 | if (command == HPI_BUFFER_CMD_EXTERNAL | |
870 | || command == HPI_BUFFER_CMD_INTERNAL_FREE) | |
871 | hpios_locked_mem_free(&phw->outstream_host_buffers | |
872 | [phm->obj_index]); | |
873 | } | |
874 | /* Should HPI_ERROR_INVALID_OPERATION be returned | |
875 | if no host buffer is allocated? */ | |
876 | else | |
877 | hpi_init_response(phr, HPI_OBJ_OSTREAM, | |
878 | HPI_OSTREAM_HOSTBUFFER_FREE, 0); | |
879 | ||
880 | } | |
881 | ||
60f1deb5 | 882 | static u32 outstream_get_space_available(struct hpi_hostbuffer_status *status) |
719f82d3 | 883 | { |
2a383cb3 EB |
884 | return status->size_in_bytes - (status->host_index - |
885 | status->dSP_index); | |
719f82d3 EB |
886 | } |
887 | ||
888 | static void outstream_write(struct hpi_adapter_obj *pao, | |
889 | struct hpi_message *phm, struct hpi_response *phr) | |
890 | { | |
891 | struct hpi_hw_obj *phw = pao->priv; | |
892 | struct bus_master_interface *interface = phw->p_interface_buffer; | |
893 | struct hpi_hostbuffer_status *status; | |
2a383cb3 | 894 | u32 space_available; |
719f82d3 EB |
895 | |
896 | if (!phw->outstream_host_buffer_size[phm->obj_index]) { | |
897 | /* there is no BBM buffer, write via message */ | |
898 | hw_message(pao, phm, phr); | |
899 | return; | |
900 | } | |
901 | ||
902 | hpi_init_response(phr, phm->object, phm->function, 0); | |
903 | status = &interface->outstream_host_buffer_status[phm->obj_index]; | |
904 | ||
719f82d3 | 905 | space_available = outstream_get_space_available(status); |
2a383cb3 | 906 | if (space_available < phm->u.d.u.data.data_size) { |
719f82d3 EB |
907 | phr->error = HPI_ERROR_INVALID_DATASIZE; |
908 | return; | |
909 | } | |
910 | ||
911 | /* HostBuffers is used to indicate host buffer is internally allocated. | |
912 | otherwise, assumed external, data written externally */ | |
913 | if (phm->u.d.u.data.pb_data | |
914 | && hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> | |
915 | obj_index])) { | |
916 | u8 *p_bbm_data; | |
2a383cb3 | 917 | u32 l_first_write; |
719f82d3 EB |
918 | u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data; |
919 | ||
920 | if (hpios_locked_mem_get_virt_addr(&phw-> | |
921 | outstream_host_buffers[phm->obj_index], | |
922 | (void *)&p_bbm_data)) { | |
923 | phr->error = HPI_ERROR_INVALID_OPERATION; | |
924 | return; | |
925 | } | |
926 | ||
927 | /* either all data, | |
928 | or enough to fit from current to end of BBM buffer */ | |
929 | l_first_write = | |
930 | min(phm->u.d.u.data.data_size, | |
931 | status->size_in_bytes - | |
932 | (status->host_index & (status->size_in_bytes - 1))); | |
933 | ||
934 | memcpy(p_bbm_data + | |
935 | (status->host_index & (status->size_in_bytes - 1)), | |
936 | p_app_data, l_first_write); | |
937 | /* remaining data if any */ | |
938 | memcpy(p_bbm_data, p_app_data + l_first_write, | |
939 | phm->u.d.u.data.data_size - l_first_write); | |
940 | } | |
3285ea10 EB |
941 | |
942 | /* | |
943 | * This version relies on the DSP code triggering an OStream buffer | |
944 | * update immediately following a SET_FORMAT call. The host has | |
deb21a23 EB |
945 | * already written data into the BBM buffer, but the DSP won't know |
946 | * about it until dwHostIndex is adjusted. | |
3285ea10 EB |
947 | */ |
948 | if (phw->flag_outstream_just_reset[phm->obj_index]) { | |
949 | /* Format can only change after reset. Must tell DSP. */ | |
950 | u16 function = phm->function; | |
951 | phw->flag_outstream_just_reset[phm->obj_index] = 0; | |
952 | phm->function = HPI_OSTREAM_SET_FORMAT; | |
953 | hw_message(pao, phm, phr); /* send the format to the DSP */ | |
954 | phm->function = function; | |
955 | if (phr->error) | |
956 | return; | |
957 | } | |
958 | ||
719f82d3 EB |
959 | status->host_index += phm->u.d.u.data.data_size; |
960 | } | |
961 | ||
962 | static void outstream_get_info(struct hpi_adapter_obj *pao, | |
963 | struct hpi_message *phm, struct hpi_response *phr) | |
964 | { | |
965 | struct hpi_hw_obj *phw = pao->priv; | |
966 | struct bus_master_interface *interface = phw->p_interface_buffer; | |
967 | struct hpi_hostbuffer_status *status; | |
968 | ||
969 | if (!phw->outstream_host_buffer_size[phm->obj_index]) { | |
970 | hw_message(pao, phm, phr); | |
971 | return; | |
972 | } | |
973 | ||
974 | hpi_init_response(phr, phm->object, phm->function, 0); | |
975 | ||
976 | status = &interface->outstream_host_buffer_status[phm->obj_index]; | |
977 | ||
978 | phr->u.d.u.stream_info.state = (u16)status->stream_state; | |
979 | phr->u.d.u.stream_info.samples_transferred = | |
980 | status->samples_processed; | |
981 | phr->u.d.u.stream_info.buffer_size = status->size_in_bytes; | |
982 | phr->u.d.u.stream_info.data_available = | |
983 | status->size_in_bytes - outstream_get_space_available(status); | |
984 | phr->u.d.u.stream_info.auxiliary_data_available = | |
985 | status->auxiliary_data_available; | |
986 | } | |
987 | ||
988 | static void outstream_start(struct hpi_adapter_obj *pao, | |
989 | struct hpi_message *phm, struct hpi_response *phr) | |
990 | { | |
991 | hw_message(pao, phm, phr); | |
992 | } | |
993 | ||
994 | static void outstream_reset(struct hpi_adapter_obj *pao, | |
995 | struct hpi_message *phm, struct hpi_response *phr) | |
996 | { | |
997 | struct hpi_hw_obj *phw = pao->priv; | |
998 | phw->flag_outstream_just_reset[phm->obj_index] = 1; | |
999 | hw_message(pao, phm, phr); | |
1000 | } | |
1001 | ||
1002 | static void outstream_open(struct hpi_adapter_obj *pao, | |
1003 | struct hpi_message *phm, struct hpi_response *phr) | |
1004 | { | |
1005 | outstream_reset(pao, phm, phr); | |
1006 | } | |
1007 | ||
1008 | /*****************************************************************************/ | |
1009 | /* InStream Host buffer functions */ | |
1010 | ||
1011 | static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao, | |
1012 | struct hpi_message *phm, struct hpi_response *phr) | |
1013 | { | |
1014 | u16 err = 0; | |
1015 | u32 command = phm->u.d.u.buffer.command; | |
1016 | struct hpi_hw_obj *phw = pao->priv; | |
1017 | struct bus_master_interface *interface = phw->p_interface_buffer; | |
1018 | ||
1019 | hpi_init_response(phr, phm->object, phm->function, 0); | |
1020 | ||
1021 | if (command == HPI_BUFFER_CMD_EXTERNAL | |
1022 | || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) { | |
1023 | ||
1024 | phm->u.d.u.buffer.buffer_size = | |
1025 | roundup_pow_of_two(phm->u.d.u.buffer.buffer_size); | |
1026 | phr->u.d.u.stream_info.data_available = | |
1027 | phw->instream_host_buffer_size[phm->obj_index]; | |
1028 | phr->u.d.u.stream_info.buffer_size = | |
1029 | phm->u.d.u.buffer.buffer_size; | |
1030 | ||
1031 | if (phw->instream_host_buffer_size[phm->obj_index] == | |
1032 | phm->u.d.u.buffer.buffer_size) { | |
1033 | /* Same size, no action required */ | |
1034 | return; | |
1035 | } | |
1036 | ||
1037 | if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> | |
1038 | obj_index])) | |
1039 | hpios_locked_mem_free(&phw->instream_host_buffers | |
1040 | [phm->obj_index]); | |
1041 | ||
1042 | err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm-> | |
1043 | obj_index], phm->u.d.u.buffer.buffer_size, | |
3285ea10 | 1044 | pao->pci.pci_dev); |
719f82d3 EB |
1045 | |
1046 | if (err) { | |
1047 | phr->error = HPI_ERROR_INVALID_DATASIZE; | |
1048 | phw->instream_host_buffer_size[phm->obj_index] = 0; | |
1049 | return; | |
1050 | } | |
1051 | ||
1052 | err = hpios_locked_mem_get_phys_addr | |
1053 | (&phw->instream_host_buffers[phm->obj_index], | |
1054 | &phm->u.d.u.buffer.pci_address); | |
1055 | /* get the phys addr into msg for single call alloc. Caller | |
1056 | needs to do this for split alloc so return the phy address */ | |
1057 | phr->u.d.u.stream_info.auxiliary_data_available = | |
1058 | phm->u.d.u.buffer.pci_address; | |
1059 | if (err) { | |
1060 | hpios_locked_mem_free(&phw->instream_host_buffers | |
1061 | [phm->obj_index]); | |
1062 | phw->instream_host_buffer_size[phm->obj_index] = 0; | |
1063 | phr->error = HPI_ERROR_MEMORY_ALLOC; | |
1064 | return; | |
1065 | } | |
1066 | } | |
1067 | ||
1068 | if (command == HPI_BUFFER_CMD_EXTERNAL | |
1069 | || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) { | |
1070 | struct hpi_hostbuffer_status *status; | |
1071 | ||
1072 | if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer. | |
1073 | buffer_size - 1)) { | |
1074 | HPI_DEBUG_LOG(ERROR, | |
3285ea10 | 1075 | "Buffer size must be 2^N not %d\n", |
719f82d3 EB |
1076 | phm->u.d.u.buffer.buffer_size); |
1077 | phr->error = HPI_ERROR_INVALID_DATASIZE; | |
1078 | return; | |
1079 | } | |
1080 | ||
1081 | phw->instream_host_buffer_size[phm->obj_index] = | |
1082 | phm->u.d.u.buffer.buffer_size; | |
1083 | status = &interface->instream_host_buffer_status[phm-> | |
1084 | obj_index]; | |
1085 | status->samples_processed = 0; | |
1086 | status->stream_state = HPI_STATE_STOPPED; | |
1087 | status->dSP_index = 0; | |
1088 | status->host_index = status->dSP_index; | |
1089 | status->size_in_bytes = phm->u.d.u.buffer.buffer_size; | |
deb21a23 | 1090 | status->auxiliary_data_available = 0; |
719f82d3 EB |
1091 | |
1092 | hw_message(pao, phm, phr); | |
ba3a9099 | 1093 | |
719f82d3 EB |
1094 | if (phr->error |
1095 | && hpios_locked_mem_valid(&phw-> | |
1096 | instream_host_buffers[phm->obj_index])) { | |
1097 | hpios_locked_mem_free(&phw->instream_host_buffers | |
1098 | [phm->obj_index]); | |
1099 | phw->instream_host_buffer_size[phm->obj_index] = 0; | |
1100 | } | |
1101 | } | |
1102 | } | |
1103 | ||
1104 | static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao, | |
1105 | struct hpi_message *phm, struct hpi_response *phr) | |
1106 | { | |
1107 | struct hpi_hw_obj *phw = pao->priv; | |
1108 | struct bus_master_interface *interface = phw->p_interface_buffer; | |
1109 | struct hpi_hostbuffer_status *status; | |
1110 | u8 *p_bbm_data; | |
1111 | ||
1112 | if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> | |
1113 | obj_index])) { | |
1114 | if (hpios_locked_mem_get_virt_addr(&phw-> | |
1115 | instream_host_buffers[phm->obj_index], | |
1116 | (void *)&p_bbm_data)) { | |
1117 | phr->error = HPI_ERROR_INVALID_OPERATION; | |
1118 | return; | |
1119 | } | |
1120 | status = &interface->instream_host_buffer_status[phm-> | |
1121 | obj_index]; | |
1122 | hpi_init_response(phr, HPI_OBJ_ISTREAM, | |
1123 | HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0); | |
1124 | phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data; | |
1125 | phr->u.d.u.hostbuffer_info.p_status = status; | |
1126 | } else { | |
1127 | hpi_init_response(phr, HPI_OBJ_ISTREAM, | |
1128 | HPI_ISTREAM_HOSTBUFFER_GET_INFO, | |
1129 | HPI_ERROR_INVALID_OPERATION); | |
1130 | } | |
1131 | } | |
1132 | ||
1133 | static void instream_host_buffer_free(struct hpi_adapter_obj *pao, | |
1134 | struct hpi_message *phm, struct hpi_response *phr) | |
1135 | { | |
1136 | struct hpi_hw_obj *phw = pao->priv; | |
1137 | u32 command = phm->u.d.u.buffer.command; | |
1138 | ||
1139 | if (phw->instream_host_buffer_size[phm->obj_index]) { | |
1140 | if (command == HPI_BUFFER_CMD_EXTERNAL | |
1141 | || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) { | |
1142 | phw->instream_host_buffer_size[phm->obj_index] = 0; | |
1143 | hw_message(pao, phm, phr); | |
1144 | } | |
1145 | ||
1146 | if (command == HPI_BUFFER_CMD_EXTERNAL | |
1147 | || command == HPI_BUFFER_CMD_INTERNAL_FREE) | |
1148 | hpios_locked_mem_free(&phw->instream_host_buffers | |
1149 | [phm->obj_index]); | |
1150 | ||
1151 | } else { | |
1152 | /* Should HPI_ERROR_INVALID_OPERATION be returned | |
1153 | if no host buffer is allocated? */ | |
1154 | hpi_init_response(phr, HPI_OBJ_ISTREAM, | |
1155 | HPI_ISTREAM_HOSTBUFFER_FREE, 0); | |
1156 | ||
1157 | } | |
1158 | ||
1159 | } | |
1160 | ||
1161 | static void instream_start(struct hpi_adapter_obj *pao, | |
1162 | struct hpi_message *phm, struct hpi_response *phr) | |
1163 | { | |
1164 | hw_message(pao, phm, phr); | |
1165 | } | |
1166 | ||
2a383cb3 | 1167 | static u32 instream_get_bytes_available(struct hpi_hostbuffer_status *status) |
719f82d3 | 1168 | { |
2a383cb3 | 1169 | return status->dSP_index - status->host_index; |
719f82d3 EB |
1170 | } |
1171 | ||
1172 | static void instream_read(struct hpi_adapter_obj *pao, | |
1173 | struct hpi_message *phm, struct hpi_response *phr) | |
1174 | { | |
1175 | struct hpi_hw_obj *phw = pao->priv; | |
1176 | struct bus_master_interface *interface = phw->p_interface_buffer; | |
1177 | struct hpi_hostbuffer_status *status; | |
2a383cb3 | 1178 | u32 data_available; |
719f82d3 | 1179 | u8 *p_bbm_data; |
2a383cb3 | 1180 | u32 l_first_read; |
719f82d3 EB |
1181 | u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data; |
1182 | ||
1183 | if (!phw->instream_host_buffer_size[phm->obj_index]) { | |
1184 | hw_message(pao, phm, phr); | |
1185 | return; | |
1186 | } | |
1187 | hpi_init_response(phr, phm->object, phm->function, 0); | |
1188 | ||
1189 | status = &interface->instream_host_buffer_status[phm->obj_index]; | |
1190 | data_available = instream_get_bytes_available(status); | |
2a383cb3 | 1191 | if (data_available < phm->u.d.u.data.data_size) { |
719f82d3 EB |
1192 | phr->error = HPI_ERROR_INVALID_DATASIZE; |
1193 | return; | |
1194 | } | |
1195 | ||
1196 | if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> | |
1197 | obj_index])) { | |
1198 | if (hpios_locked_mem_get_virt_addr(&phw-> | |
1199 | instream_host_buffers[phm->obj_index], | |
1200 | (void *)&p_bbm_data)) { | |
1201 | phr->error = HPI_ERROR_INVALID_OPERATION; | |
1202 | return; | |
1203 | } | |
1204 | ||
1205 | /* either all data, | |
1206 | or enough to fit from current to end of BBM buffer */ | |
1207 | l_first_read = | |
1208 | min(phm->u.d.u.data.data_size, | |
1209 | status->size_in_bytes - | |
1210 | (status->host_index & (status->size_in_bytes - 1))); | |
1211 | ||
1212 | memcpy(p_app_data, | |
1213 | p_bbm_data + | |
1214 | (status->host_index & (status->size_in_bytes - 1)), | |
1215 | l_first_read); | |
1216 | /* remaining data if any */ | |
1217 | memcpy(p_app_data + l_first_read, p_bbm_data, | |
1218 | phm->u.d.u.data.data_size - l_first_read); | |
1219 | } | |
1220 | status->host_index += phm->u.d.u.data.data_size; | |
1221 | } | |
1222 | ||
1223 | static void instream_get_info(struct hpi_adapter_obj *pao, | |
1224 | struct hpi_message *phm, struct hpi_response *phr) | |
1225 | { | |
1226 | struct hpi_hw_obj *phw = pao->priv; | |
1227 | struct bus_master_interface *interface = phw->p_interface_buffer; | |
1228 | struct hpi_hostbuffer_status *status; | |
1229 | if (!phw->instream_host_buffer_size[phm->obj_index]) { | |
1230 | hw_message(pao, phm, phr); | |
1231 | return; | |
1232 | } | |
1233 | ||
1234 | status = &interface->instream_host_buffer_status[phm->obj_index]; | |
1235 | ||
1236 | hpi_init_response(phr, phm->object, phm->function, 0); | |
1237 | ||
1238 | phr->u.d.u.stream_info.state = (u16)status->stream_state; | |
1239 | phr->u.d.u.stream_info.samples_transferred = | |
1240 | status->samples_processed; | |
1241 | phr->u.d.u.stream_info.buffer_size = status->size_in_bytes; | |
1242 | phr->u.d.u.stream_info.data_available = | |
1243 | instream_get_bytes_available(status); | |
1244 | phr->u.d.u.stream_info.auxiliary_data_available = | |
1245 | status->auxiliary_data_available; | |
1246 | } | |
1247 | ||
1248 | /*****************************************************************************/ | |
1249 | /* LOW-LEVEL */ | |
1250 | #define HPI6205_MAX_FILES_TO_LOAD 2 | |
1251 | ||
1252 | static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao, | |
1253 | u32 *pos_error_code) | |
1254 | { | |
1255 | struct hpi_hw_obj *phw = pao->priv; | |
1256 | struct dsp_code dsp_code; | |
1257 | u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD]; | |
719f82d3 EB |
1258 | u32 temp; |
1259 | int dsp = 0, i = 0; | |
1260 | u16 err = 0; | |
1261 | ||
1262 | boot_code_id[0] = HPI_ADAPTER_ASI(0x6205); | |
1263 | ||
ee246fc0 EB |
1264 | boot_code_id[1] = pao->pci.pci_dev->subsystem_device; |
1265 | boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(boot_code_id[1]); | |
1266 | ||
1267 | /* fix up cases where bootcode id[1] != subsys id */ | |
1268 | switch (boot_code_id[1]) { | |
719f82d3 | 1269 | case HPI_ADAPTER_FAMILY_ASI(0x5000): |
ee246fc0 EB |
1270 | boot_code_id[0] = boot_code_id[1]; |
1271 | boot_code_id[1] = 0; | |
719f82d3 EB |
1272 | break; |
1273 | case HPI_ADAPTER_FAMILY_ASI(0x5300): | |
1274 | case HPI_ADAPTER_FAMILY_ASI(0x5400): | |
1275 | case HPI_ADAPTER_FAMILY_ASI(0x6300): | |
ee246fc0 | 1276 | boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6400); |
719f82d3 EB |
1277 | break; |
1278 | case HPI_ADAPTER_FAMILY_ASI(0x5600): | |
1279 | case HPI_ADAPTER_FAMILY_ASI(0x6500): | |
ee246fc0 | 1280 | boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6600); |
719f82d3 | 1281 | break; |
cadae428 | 1282 | case HPI_ADAPTER_FAMILY_ASI(0x8800): |
ee246fc0 EB |
1283 | boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x8900); |
1284 | break; | |
1285 | default: | |
cadae428 | 1286 | break; |
719f82d3 | 1287 | } |
719f82d3 EB |
1288 | |
1289 | /* reset DSP by writing a 1 to the WARMRESET bit */ | |
1290 | temp = C6205_HDCR_WARMRESET; | |
1291 | iowrite32(temp, phw->prHDCR); | |
1292 | hpios_delay_micro_seconds(1000); | |
1293 | ||
1294 | /* check that PCI i/f was configured by EEPROM */ | |
1295 | temp = ioread32(phw->prHSR); | |
1296 | if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) != | |
1297 | C6205_HSR_EEREAD) | |
3285ea10 | 1298 | return HPI6205_ERROR_6205_EEPROM; |
719f82d3 EB |
1299 | temp |= 0x04; |
1300 | /* disable PINTA interrupt */ | |
1301 | iowrite32(temp, phw->prHSR); | |
1302 | ||
1303 | /* check control register reports PCI boot mode */ | |
1304 | temp = ioread32(phw->prHDCR); | |
1305 | if (!(temp & C6205_HDCR_PCIBOOT)) | |
3285ea10 | 1306 | return HPI6205_ERROR_6205_REG; |
719f82d3 | 1307 | |
3285ea10 | 1308 | /* try writing a few numbers to the DSP page register */ |
719f82d3 | 1309 | /* and reading them back. */ |
3285ea10 | 1310 | temp = 3; |
719f82d3 EB |
1311 | iowrite32(temp, phw->prDSPP); |
1312 | if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) | |
3285ea10 | 1313 | return HPI6205_ERROR_6205_DSPPAGE; |
719f82d3 EB |
1314 | temp = 2; |
1315 | iowrite32(temp, phw->prDSPP); | |
1316 | if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) | |
3285ea10 EB |
1317 | return HPI6205_ERROR_6205_DSPPAGE; |
1318 | temp = 1; | |
719f82d3 EB |
1319 | iowrite32(temp, phw->prDSPP); |
1320 | if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) | |
3285ea10 | 1321 | return HPI6205_ERROR_6205_DSPPAGE; |
719f82d3 EB |
1322 | /* reset DSP page to the correct number */ |
1323 | temp = 0; | |
1324 | iowrite32(temp, phw->prDSPP); | |
1325 | if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) | |
3285ea10 | 1326 | return HPI6205_ERROR_6205_DSPPAGE; |
719f82d3 EB |
1327 | phw->dsp_page = 0; |
1328 | ||
1329 | /* release 6713 from reset before 6205 is bootloaded. | |
1330 | This ensures that the EMIF is inactive, | |
1331 | and the 6713 HPI gets the correct bootmode etc | |
1332 | */ | |
1333 | if (boot_code_id[1] != 0) { | |
1334 | /* DSP 1 is a C6713 */ | |
1335 | /* CLKX0 <- '1' release the C6205 bootmode pulldowns */ | |
1336 | boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002202); | |
1337 | hpios_delay_micro_seconds(100); | |
1338 | /* Reset the 6713 #1 - revB */ | |
1339 | boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0); | |
1340 | ||
1341 | /* dummy read every 4 words for 6205 advisory 1.4.4 */ | |
1342 | boot_loader_read_mem32(pao, 0, 0); | |
1343 | ||
1344 | hpios_delay_micro_seconds(100); | |
1345 | /* Release C6713 from reset - revB */ | |
1346 | boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4); | |
1347 | hpios_delay_micro_seconds(100); | |
1348 | } | |
1349 | ||
1350 | for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) { | |
1351 | /* is there a DSP to load? */ | |
1352 | if (boot_code_id[dsp] == 0) | |
1353 | continue; | |
1354 | ||
1355 | err = boot_loader_config_emif(pao, dsp); | |
1356 | if (err) | |
1357 | return err; | |
1358 | ||
1359 | err = boot_loader_test_internal_memory(pao, dsp); | |
1360 | if (err) | |
1361 | return err; | |
1362 | ||
1363 | err = boot_loader_test_external_memory(pao, dsp); | |
1364 | if (err) | |
1365 | return err; | |
1366 | ||
1367 | err = boot_loader_test_pld(pao, dsp); | |
1368 | if (err) | |
1369 | return err; | |
1370 | ||
1371 | /* write the DSP code down into the DSPs memory */ | |
3285ea10 | 1372 | dsp_code.ps_dev = pao->pci.pci_dev; |
719f82d3 EB |
1373 | err = hpi_dsp_code_open(boot_code_id[dsp], &dsp_code, |
1374 | pos_error_code); | |
1375 | if (err) | |
1376 | return err; | |
1377 | ||
1378 | while (1) { | |
1379 | u32 length; | |
1380 | u32 address; | |
1381 | u32 type; | |
1382 | u32 *pcode; | |
1383 | ||
1384 | err = hpi_dsp_code_read_word(&dsp_code, &length); | |
1385 | if (err) | |
1386 | break; | |
1387 | if (length == 0xFFFFFFFF) | |
1388 | break; /* end of code */ | |
1389 | ||
1390 | err = hpi_dsp_code_read_word(&dsp_code, &address); | |
1391 | if (err) | |
1392 | break; | |
1393 | err = hpi_dsp_code_read_word(&dsp_code, &type); | |
1394 | if (err) | |
1395 | break; | |
1396 | err = hpi_dsp_code_read_block(length, &dsp_code, | |
1397 | &pcode); | |
1398 | if (err) | |
1399 | break; | |
1400 | for (i = 0; i < (int)length; i++) { | |
3285ea10 EB |
1401 | boot_loader_write_mem32(pao, dsp, address, |
1402 | *pcode); | |
719f82d3 EB |
1403 | /* dummy read every 4 words */ |
1404 | /* for 6205 advisory 1.4.4 */ | |
1405 | if (i % 4 == 0) | |
1406 | boot_loader_read_mem32(pao, dsp, | |
1407 | address); | |
1408 | pcode++; | |
1409 | address += 4; | |
1410 | } | |
1411 | ||
1412 | } | |
1413 | if (err) { | |
1414 | hpi_dsp_code_close(&dsp_code); | |
1415 | return err; | |
1416 | } | |
1417 | ||
1418 | /* verify code */ | |
1419 | hpi_dsp_code_rewind(&dsp_code); | |
1420 | while (1) { | |
1421 | u32 length = 0; | |
1422 | u32 address = 0; | |
1423 | u32 type = 0; | |
1424 | u32 *pcode = NULL; | |
1425 | u32 data = 0; | |
1426 | ||
1427 | hpi_dsp_code_read_word(&dsp_code, &length); | |
1428 | if (length == 0xFFFFFFFF) | |
1429 | break; /* end of code */ | |
1430 | ||
1431 | hpi_dsp_code_read_word(&dsp_code, &address); | |
1432 | hpi_dsp_code_read_word(&dsp_code, &type); | |
1433 | hpi_dsp_code_read_block(length, &dsp_code, &pcode); | |
1434 | ||
1435 | for (i = 0; i < (int)length; i++) { | |
1436 | data = boot_loader_read_mem32(pao, dsp, | |
1437 | address); | |
1438 | if (data != *pcode) { | |
1439 | err = 0; | |
1440 | break; | |
1441 | } | |
1442 | pcode++; | |
1443 | address += 4; | |
1444 | } | |
1445 | if (err) | |
1446 | break; | |
1447 | } | |
1448 | hpi_dsp_code_close(&dsp_code); | |
1449 | if (err) | |
1450 | return err; | |
1451 | } | |
1452 | ||
1453 | /* After bootloading all DSPs, start DSP0 running | |
1454 | * The DSP0 code will handle starting and synchronizing with its slaves | |
1455 | */ | |
1456 | if (phw->p_interface_buffer) { | |
1457 | /* we need to tell the card the physical PCI address */ | |
1458 | u32 physicalPC_iaddress; | |
1459 | struct bus_master_interface *interface = | |
1460 | phw->p_interface_buffer; | |
1461 | u32 host_mailbox_address_on_dsp; | |
1462 | u32 physicalPC_iaddress_verify = 0; | |
1463 | int time_out = 10; | |
1464 | /* set ack so we know when DSP is ready to go */ | |
1465 | /* (dwDspAck will be changed to HIF_RESET) */ | |
1466 | interface->dsp_ack = H620_HIF_UNKNOWN; | |
1467 | wmb(); /* ensure ack is written before dsp writes back */ | |
1468 | ||
1469 | err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem, | |
1470 | &physicalPC_iaddress); | |
1471 | ||
1472 | /* locate the host mailbox on the DSP. */ | |
1473 | host_mailbox_address_on_dsp = 0x80000000; | |
1474 | while ((physicalPC_iaddress != physicalPC_iaddress_verify) | |
1475 | && time_out--) { | |
3285ea10 | 1476 | boot_loader_write_mem32(pao, 0, |
719f82d3 EB |
1477 | host_mailbox_address_on_dsp, |
1478 | physicalPC_iaddress); | |
1479 | physicalPC_iaddress_verify = | |
1480 | boot_loader_read_mem32(pao, 0, | |
1481 | host_mailbox_address_on_dsp); | |
1482 | } | |
1483 | } | |
1484 | HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n"); | |
1485 | /* enable interrupts */ | |
1486 | temp = ioread32(phw->prHSR); | |
1487 | temp &= ~(u32)C6205_HSR_INTAM; | |
1488 | iowrite32(temp, phw->prHSR); | |
1489 | ||
1490 | /* start code running... */ | |
1491 | temp = ioread32(phw->prHDCR); | |
1492 | temp |= (u32)C6205_HDCR_DSPINT; | |
1493 | iowrite32(temp, phw->prHDCR); | |
1494 | ||
1495 | /* give the DSP 10ms to start up */ | |
1496 | hpios_delay_micro_seconds(10000); | |
1497 | return err; | |
1498 | ||
1499 | } | |
1500 | ||
1501 | /*****************************************************************************/ | |
1502 | /* Bootloader utility functions */ | |
1503 | ||
1504 | static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index, | |
1505 | u32 address) | |
1506 | { | |
1507 | struct hpi_hw_obj *phw = pao->priv; | |
1508 | u32 data = 0; | |
1509 | __iomem u32 *p_data; | |
1510 | ||
1511 | if (dsp_index == 0) { | |
1512 | /* DSP 0 is always C6205 */ | |
1513 | if ((address >= 0x01800000) & (address < 0x02000000)) { | |
1514 | /* BAR1 register access */ | |
1515 | p_data = pao->pci.ap_mem_base[1] + | |
1516 | (address & 0x007fffff) / | |
1517 | sizeof(*pao->pci.ap_mem_base[1]); | |
1518 | /* HPI_DEBUG_LOG(WARNING, | |
1519 | "BAR1 access %08x\n", dwAddress); */ | |
1520 | } else { | |
1521 | u32 dw4M_page = address >> 22L; | |
1522 | if (dw4M_page != phw->dsp_page) { | |
1523 | phw->dsp_page = dw4M_page; | |
1524 | /* *INDENT OFF* */ | |
1525 | iowrite32(phw->dsp_page, phw->prDSPP); | |
1526 | /* *INDENT-ON* */ | |
1527 | } | |
1528 | address &= 0x3fffff; /* address within 4M page */ | |
1529 | /* BAR0 memory access */ | |
1530 | p_data = pao->pci.ap_mem_base[0] + | |
1531 | address / sizeof(u32); | |
1532 | } | |
1533 | data = ioread32(p_data); | |
1534 | } else if (dsp_index == 1) { | |
1535 | /* DSP 1 is a C6713 */ | |
1536 | u32 lsb; | |
1537 | boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address); | |
1538 | boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16); | |
1539 | lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR); | |
1540 | data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR); | |
1541 | data = (data << 16) | (lsb & 0xFFFF); | |
1542 | } | |
1543 | return data; | |
1544 | } | |
1545 | ||
3285ea10 EB |
1546 | static void boot_loader_write_mem32(struct hpi_adapter_obj *pao, |
1547 | int dsp_index, u32 address, u32 data) | |
719f82d3 EB |
1548 | { |
1549 | struct hpi_hw_obj *phw = pao->priv; | |
719f82d3 EB |
1550 | __iomem u32 *p_data; |
1551 | /* u32 dwVerifyData=0; */ | |
1552 | ||
1553 | if (dsp_index == 0) { | |
1554 | /* DSP 0 is always C6205 */ | |
1555 | if ((address >= 0x01800000) & (address < 0x02000000)) { | |
1556 | /* BAR1 - DSP register access using */ | |
1557 | /* Non-prefetchable PCI access */ | |
1558 | p_data = pao->pci.ap_mem_base[1] + | |
1559 | (address & 0x007fffff) / | |
1560 | sizeof(*pao->pci.ap_mem_base[1]); | |
1561 | } else { | |
1562 | /* BAR0 access - all of DSP memory using */ | |
1563 | /* pre-fetchable PCI access */ | |
1564 | u32 dw4M_page = address >> 22L; | |
1565 | if (dw4M_page != phw->dsp_page) { | |
1566 | phw->dsp_page = dw4M_page; | |
1567 | /* *INDENT-OFF* */ | |
1568 | iowrite32(phw->dsp_page, phw->prDSPP); | |
1569 | /* *INDENT-ON* */ | |
1570 | } | |
1571 | address &= 0x3fffff; /* address within 4M page */ | |
1572 | p_data = pao->pci.ap_mem_base[0] + | |
1573 | address / sizeof(u32); | |
1574 | } | |
1575 | iowrite32(data, p_data); | |
1576 | } else if (dsp_index == 1) { | |
1577 | /* DSP 1 is a C6713 */ | |
1578 | boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address); | |
1579 | boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16); | |
1580 | ||
1581 | /* dummy read every 4 words for 6205 advisory 1.4.4 */ | |
1582 | boot_loader_read_mem32(pao, 0, 0); | |
1583 | ||
1584 | boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data); | |
1585 | boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16); | |
1586 | ||
1587 | /* dummy read every 4 words for 6205 advisory 1.4.4 */ | |
1588 | boot_loader_read_mem32(pao, 0, 0); | |
3285ea10 | 1589 | } |
719f82d3 EB |
1590 | } |
1591 | ||
1592 | static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index) | |
1593 | { | |
719f82d3 EB |
1594 | if (dsp_index == 0) { |
1595 | u32 setting; | |
1596 | ||
1597 | /* DSP 0 is always C6205 */ | |
1598 | ||
1599 | /* Set the EMIF */ | |
1600 | /* memory map of C6205 */ | |
1601 | /* 00000000-0000FFFF 16Kx32 internal program */ | |
1602 | /* 00400000-00BFFFFF CE0 2Mx32 SDRAM running @ 100MHz */ | |
1603 | ||
1604 | /* EMIF config */ | |
1605 | /*------------ */ | |
1606 | /* Global EMIF control */ | |
1607 | boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779); | |
1608 | #define WS_OFS 28 | |
1609 | #define WST_OFS 22 | |
1610 | #define WH_OFS 20 | |
1611 | #define RS_OFS 16 | |
1612 | #define RST_OFS 8 | |
1613 | #define MTYPE_OFS 4 | |
1614 | #define RH_OFS 0 | |
1615 | ||
1616 | /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */ | |
1617 | setting = 0x00000030; | |
1618 | boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting); | |
1619 | if (setting != boot_loader_read_mem32(pao, dsp_index, | |
1620 | 0x01800008)) | |
3285ea10 | 1621 | return HPI6205_ERROR_DSP_EMIF; |
719f82d3 EB |
1622 | |
1623 | /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */ | |
1624 | /* which occupies D15..0. 6713 starts at 27MHz, so need */ | |
1625 | /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */ | |
1626 | /* WST should be 71, but 63 is max possible */ | |
1627 | setting = | |
1628 | (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) | | |
1629 | (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) | | |
1630 | (2L << MTYPE_OFS); | |
1631 | boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting); | |
1632 | if (setting != boot_loader_read_mem32(pao, dsp_index, | |
1633 | 0x01800004)) | |
3285ea10 | 1634 | return HPI6205_ERROR_DSP_EMIF; |
719f82d3 EB |
1635 | |
1636 | /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */ | |
1637 | /* which occupies D15..0. 6713 starts at 27MHz, so need */ | |
1638 | /* plenty of wait states */ | |
1639 | setting = | |
1640 | (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) | | |
1641 | (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) | | |
1642 | (2L << MTYPE_OFS); | |
1643 | boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting); | |
1644 | if (setting != boot_loader_read_mem32(pao, dsp_index, | |
1645 | 0x01800010)) | |
3285ea10 | 1646 | return HPI6205_ERROR_DSP_EMIF; |
719f82d3 EB |
1647 | |
1648 | /* EMIF CE3 setup - 32 bit async. */ | |
1649 | /* This is the PLD on the ASI5000 cards only */ | |
1650 | setting = | |
1651 | (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) | | |
1652 | (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) | | |
1653 | (2L << MTYPE_OFS); | |
1654 | boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting); | |
1655 | if (setting != boot_loader_read_mem32(pao, dsp_index, | |
1656 | 0x01800014)) | |
3285ea10 | 1657 | return HPI6205_ERROR_DSP_EMIF; |
719f82d3 EB |
1658 | |
1659 | /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */ | |
1660 | /* need to use this else DSP code crashes? */ | |
1661 | boot_loader_write_mem32(pao, dsp_index, 0x01800018, | |
1662 | 0x07117000); | |
1663 | ||
1664 | /* EMIF SDRAM Refresh Timing */ | |
1665 | /* EMIF SDRAM timing (orig = 0x410, emulator = 0x61a) */ | |
1666 | boot_loader_write_mem32(pao, dsp_index, 0x0180001C, | |
1667 | 0x00000410); | |
1668 | ||
1669 | } else if (dsp_index == 1) { | |
1670 | /* test access to the C6713s HPI registers */ | |
1671 | u32 write_data = 0, read_data = 0, i = 0; | |
1672 | ||
1673 | /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */ | |
1674 | write_data = 1; | |
1675 | boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data); | |
1676 | boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data); | |
1677 | /* C67 HPI is on lower 16bits of 32bit EMIF */ | |
1678 | read_data = | |
1679 | 0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR); | |
1680 | if (write_data != read_data) { | |
719f82d3 EB |
1681 | HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data, |
1682 | read_data); | |
3285ea10 | 1683 | return HPI6205_ERROR_C6713_HPIC; |
719f82d3 EB |
1684 | } |
1685 | /* HPIA - walking ones test */ | |
1686 | write_data = 1; | |
1687 | for (i = 0; i < 32; i++) { | |
1688 | boot_loader_write_mem32(pao, 0, HPIAL_ADDR, | |
1689 | write_data); | |
1690 | boot_loader_write_mem32(pao, 0, HPIAH_ADDR, | |
1691 | (write_data >> 16)); | |
1692 | read_data = | |
1693 | 0xFFFF & boot_loader_read_mem32(pao, 0, | |
1694 | HPIAL_ADDR); | |
1695 | read_data = | |
1696 | read_data | ((0xFFFF & | |
1697 | boot_loader_read_mem32(pao, 0, | |
1698 | HPIAH_ADDR)) | |
1699 | << 16); | |
1700 | if (read_data != write_data) { | |
719f82d3 EB |
1701 | HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n", |
1702 | write_data, read_data); | |
3285ea10 | 1703 | return HPI6205_ERROR_C6713_HPIA; |
719f82d3 EB |
1704 | } |
1705 | write_data = write_data << 1; | |
1706 | } | |
1707 | ||
1708 | /* setup C67x PLL | |
1709 | * ** C6713 datasheet says we cannot program PLL from HPI, | |
1710 | * and indeed if we try to set the PLL multiply from the HPI, | |
1711 | * the PLL does not seem to lock, so we enable the PLL and | |
1712 | * use the default multiply of x 7, which for a 27MHz clock | |
1713 | * gives a DSP speed of 189MHz | |
1714 | */ | |
1715 | /* bypass PLL */ | |
1716 | boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000); | |
1717 | hpios_delay_micro_seconds(1000); | |
1718 | /* EMIF = 189/3=63MHz */ | |
1719 | boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002); | |
1720 | /* peri = 189/2 */ | |
1721 | boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001); | |
1722 | /* cpu = 189/1 */ | |
1723 | boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000); | |
1724 | hpios_delay_micro_seconds(1000); | |
1725 | /* ** SGT test to take GPO3 high when we start the PLL */ | |
1726 | /* and low when the delay is completed */ | |
1727 | /* FSX0 <- '1' (GPO3) */ | |
1728 | boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A); | |
1729 | /* PLL not bypassed */ | |
1730 | boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001); | |
1731 | hpios_delay_micro_seconds(1000); | |
1732 | /* FSX0 <- '0' (GPO3) */ | |
1733 | boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02); | |
1734 | ||
1735 | /* 6205 EMIF CE1 resetup - 32 bit async. */ | |
1736 | /* Now 6713 #1 is running at 189MHz can reduce waitstates */ | |
1737 | boot_loader_write_mem32(pao, 0, 0x01800004, /* CE1 */ | |
1738 | (1L << WS_OFS) | (8L << WST_OFS) | (1L << WH_OFS) | | |
1739 | (1L << RS_OFS) | (12L << RST_OFS) | (1L << RH_OFS) | | |
1740 | (2L << MTYPE_OFS)); | |
1741 | ||
1742 | hpios_delay_micro_seconds(1000); | |
1743 | ||
1744 | /* check that we can read one of the PLL registers */ | |
1745 | /* PLL should not be bypassed! */ | |
1746 | if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF) | |
1747 | != 0x0001) { | |
3285ea10 | 1748 | return HPI6205_ERROR_C6713_PLL; |
719f82d3 EB |
1749 | } |
1750 | /* setup C67x EMIF (note this is the only use of | |
1751 | BAR1 via BootLoader_WriteMem32) */ | |
1752 | boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL, | |
1753 | 0x000034A8); | |
1d595d2a EB |
1754 | |
1755 | /* EMIF CE0 setup - 2Mx32 Sync DRAM | |
1756 | 31..28 Wr setup | |
1757 | 27..22 Wr strobe | |
1758 | 21..20 Wr hold | |
1759 | 19..16 Rd setup | |
1760 | 15..14 - | |
1761 | 13..8 Rd strobe | |
1762 | 7..4 MTYPE 0011 Sync DRAM 32bits | |
1763 | 3 Wr hold MSB | |
1764 | 2..0 Rd hold | |
1765 | */ | |
719f82d3 EB |
1766 | boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0, |
1767 | 0x00000030); | |
1d595d2a EB |
1768 | |
1769 | /* EMIF SDRAM Extension | |
1770 | 0x00 | |
1771 | 31-21 0000b 0000b 000b | |
1772 | 20 WR2RD = 2cycles-1 = 1b | |
1773 | ||
1774 | 19-18 WR2DEAC = 3cycle-1 = 10b | |
1775 | 17 WR2WR = 2cycle-1 = 1b | |
1776 | 16-15 R2WDQM = 4cycle-1 = 11b | |
1777 | 14-12 RD2WR = 6cycles-1 = 101b | |
1778 | ||
1779 | 11-10 RD2DEAC = 4cycle-1 = 11b | |
1780 | 9 RD2RD = 2cycle-1 = 1b | |
1781 | 8-7 THZP = 3cycle-1 = 10b | |
1782 | 6-5 TWR = 2cycle-1 = 01b (tWR = 17ns) | |
1783 | 4 TRRD = 2cycle = 0b (tRRD = 14ns) | |
1784 | 3-1 TRAS = 5cycle-1 = 100b (Tras=42ns) | |
1785 | 1 CAS latency = 3cyc = 1b | |
1786 | (for Micron 2M32-7 operating at 100MHz) | |
1787 | */ | |
719f82d3 EB |
1788 | boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT, |
1789 | 0x001BDF29); | |
1d595d2a EB |
1790 | |
1791 | /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank) | |
1792 | 31 - 0b - | |
1793 | 30 SDBSZ 1b 4 bank | |
1794 | 29..28 SDRSZ 00b 11 row address pins | |
1795 | ||
1796 | 27..26 SDCSZ 01b 8 column address pins | |
1797 | 25 RFEN 1b refersh enabled | |
1798 | 24 INIT 1b init SDRAM! | |
1799 | ||
1800 | 23..20 TRCD 0001b (Trcd/Tcyc)-1 = (20/10)-1 = 1 | |
1801 | ||
1802 | 19..16 TRP 0001b (Trp/Tcyc)-1 = (20/10)-1 = 1 | |
1803 | ||
1804 | 15..12 TRC 0110b (Trc/Tcyc)-1 = (70/10)-1 = 6 | |
1805 | ||
1806 | 11..0 - 0000b 0000b 0000b | |
1807 | */ | |
719f82d3 | 1808 | boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL, |
1d595d2a EB |
1809 | 0x47116000); |
1810 | ||
1811 | /* SDRAM refresh timing | |
1812 | Need 4,096 refresh cycles every 64ms = 15.625us = 1562cycles of 100MHz = 0x61A | |
1813 | */ | |
719f82d3 EB |
1814 | boot_loader_write_mem32(pao, dsp_index, |
1815 | C6713_EMIF_SDRAMTIMING, 0x00000410); | |
1816 | ||
1817 | hpios_delay_micro_seconds(1000); | |
1818 | } else if (dsp_index == 2) { | |
1819 | /* DSP 2 is a C6713 */ | |
3285ea10 | 1820 | } |
719f82d3 | 1821 | |
3285ea10 | 1822 | return 0; |
719f82d3 EB |
1823 | } |
1824 | ||
1825 | static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index, | |
1826 | u32 start_address, u32 length) | |
1827 | { | |
1828 | u32 i = 0, j = 0; | |
1829 | u32 test_addr = 0; | |
1830 | u32 test_data = 0, data = 0; | |
1831 | ||
1832 | length = 1000; | |
1833 | ||
1834 | /* for 1st word, test each bit in the 32bit word, */ | |
1835 | /* dwLength specifies number of 32bit words to test */ | |
1836 | /*for(i=0; i<dwLength; i++) */ | |
1837 | i = 0; | |
1838 | { | |
1839 | test_addr = start_address + i * 4; | |
1840 | test_data = 0x00000001; | |
1841 | for (j = 0; j < 32; j++) { | |
1842 | boot_loader_write_mem32(pao, dsp_index, test_addr, | |
1843 | test_data); | |
1844 | data = boot_loader_read_mem32(pao, dsp_index, | |
1845 | test_addr); | |
1846 | if (data != test_data) { | |
1847 | HPI_DEBUG_LOG(VERBOSE, | |
3285ea10 | 1848 | "Memtest error details " |
719f82d3 EB |
1849 | "%08x %08x %08x %i\n", test_addr, |
1850 | test_data, data, dsp_index); | |
1851 | return 1; /* error */ | |
1852 | } | |
1853 | test_data = test_data << 1; | |
1854 | } /* for(j) */ | |
1855 | } /* for(i) */ | |
1856 | ||
1857 | /* for the next 100 locations test each location, leaving it as zero */ | |
1858 | /* write a zero to the next word in memory before we read */ | |
1859 | /* the previous write to make sure every memory location is unique */ | |
1860 | for (i = 0; i < 100; i++) { | |
1861 | test_addr = start_address + i * 4; | |
1862 | test_data = 0xA5A55A5A; | |
1863 | boot_loader_write_mem32(pao, dsp_index, test_addr, test_data); | |
1864 | boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0); | |
1865 | data = boot_loader_read_mem32(pao, dsp_index, test_addr); | |
1866 | if (data != test_data) { | |
1867 | HPI_DEBUG_LOG(VERBOSE, | |
3285ea10 | 1868 | "Memtest error details " |
719f82d3 EB |
1869 | "%08x %08x %08x %i\n", test_addr, test_data, |
1870 | data, dsp_index); | |
1871 | return 1; /* error */ | |
1872 | } | |
1873 | /* leave location as zero */ | |
1874 | boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0); | |
1875 | } | |
1876 | ||
1877 | /* zero out entire memory block */ | |
1878 | for (i = 0; i < length; i++) { | |
1879 | test_addr = start_address + i * 4; | |
1880 | boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0); | |
1881 | } | |
1882 | return 0; | |
1883 | } | |
1884 | ||
1885 | static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao, | |
1886 | int dsp_index) | |
1887 | { | |
1888 | int err = 0; | |
1889 | if (dsp_index == 0) { | |
1890 | /* DSP 0 is a C6205 */ | |
1891 | /* 64K prog mem */ | |
1892 | err = boot_loader_test_memory(pao, dsp_index, 0x00000000, | |
1893 | 0x10000); | |
1894 | if (!err) | |
1895 | /* 64K data mem */ | |
1896 | err = boot_loader_test_memory(pao, dsp_index, | |
1897 | 0x80000000, 0x10000); | |
3285ea10 EB |
1898 | } else if (dsp_index == 1) { |
1899 | /* DSP 1 is a C6713 */ | |
719f82d3 EB |
1900 | /* 192K internal mem */ |
1901 | err = boot_loader_test_memory(pao, dsp_index, 0x00000000, | |
1902 | 0x30000); | |
1903 | if (!err) | |
1904 | /* 64K internal mem / L2 cache */ | |
1905 | err = boot_loader_test_memory(pao, dsp_index, | |
1906 | 0x00030000, 0x10000); | |
3285ea10 | 1907 | } |
719f82d3 EB |
1908 | |
1909 | if (err) | |
3285ea10 | 1910 | return HPI6205_ERROR_DSP_INTMEM; |
719f82d3 EB |
1911 | else |
1912 | return 0; | |
1913 | } | |
1914 | ||
1915 | static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao, | |
1916 | int dsp_index) | |
1917 | { | |
1918 | u32 dRAM_start_address = 0; | |
1919 | u32 dRAM_size = 0; | |
1920 | ||
1921 | if (dsp_index == 0) { | |
1922 | /* only test for SDRAM if an ASI5000 card */ | |
3285ea10 | 1923 | if (pao->pci.pci_dev->subsystem_device == 0x5000) { |
719f82d3 EB |
1924 | /* DSP 0 is always C6205 */ |
1925 | dRAM_start_address = 0x00400000; | |
1926 | dRAM_size = 0x200000; | |
1927 | /*dwDRAMinc=1024; */ | |
1928 | } else | |
1929 | return 0; | |
3285ea10 | 1930 | } else if (dsp_index == 1) { |
719f82d3 EB |
1931 | /* DSP 1 is a C6713 */ |
1932 | dRAM_start_address = 0x80000000; | |
1933 | dRAM_size = 0x200000; | |
1934 | /*dwDRAMinc=1024; */ | |
3285ea10 | 1935 | } |
719f82d3 EB |
1936 | |
1937 | if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address, | |
1938 | dRAM_size)) | |
3285ea10 | 1939 | return HPI6205_ERROR_DSP_EXTMEM; |
719f82d3 EB |
1940 | return 0; |
1941 | } | |
1942 | ||
1943 | static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index) | |
1944 | { | |
1945 | u32 data = 0; | |
1946 | if (dsp_index == 0) { | |
1947 | /* only test for DSP0 PLD on ASI5000 card */ | |
3285ea10 | 1948 | if (pao->pci.pci_dev->subsystem_device == 0x5000) { |
719f82d3 EB |
1949 | /* PLD is located at CE3=0x03000000 */ |
1950 | data = boot_loader_read_mem32(pao, dsp_index, | |
1951 | 0x03000008); | |
1952 | if ((data & 0xF) != 0x5) | |
3285ea10 | 1953 | return HPI6205_ERROR_DSP_PLD; |
719f82d3 EB |
1954 | data = boot_loader_read_mem32(pao, dsp_index, |
1955 | 0x0300000C); | |
1956 | if ((data & 0xF) != 0xA) | |
3285ea10 | 1957 | return HPI6205_ERROR_DSP_PLD; |
719f82d3 EB |
1958 | } |
1959 | } else if (dsp_index == 1) { | |
1960 | /* DSP 1 is a C6713 */ | |
3285ea10 | 1961 | if (pao->pci.pci_dev->subsystem_device == 0x8700) { |
719f82d3 EB |
1962 | /* PLD is located at CE1=0x90000000 */ |
1963 | data = boot_loader_read_mem32(pao, dsp_index, | |
1964 | 0x90000010); | |
1965 | if ((data & 0xFF) != 0xAA) | |
3285ea10 | 1966 | return HPI6205_ERROR_DSP_PLD; |
719f82d3 EB |
1967 | /* 8713 - LED on */ |
1968 | boot_loader_write_mem32(pao, dsp_index, 0x90000000, | |
1969 | 0x02); | |
1970 | } | |
1971 | } | |
1972 | return 0; | |
1973 | } | |
1974 | ||
1975 | /** Transfer data to or from DSP | |
1976 | nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA | |
1977 | */ | |
1978 | static short hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data, | |
1979 | u32 data_size, int operation) | |
1980 | { | |
1981 | struct hpi_hw_obj *phw = pao->priv; | |
1982 | u32 data_transferred = 0; | |
1983 | u16 err = 0; | |
719f82d3 EB |
1984 | u32 temp2; |
1985 | struct bus_master_interface *interface = phw->p_interface_buffer; | |
1986 | ||
1987 | if (!p_data) | |
deb21a23 | 1988 | return HPI_ERROR_INVALID_DATA_POINTER; |
719f82d3 EB |
1989 | |
1990 | data_size &= ~3L; /* round data_size down to nearest 4 bytes */ | |
1991 | ||
1992 | /* make sure state is IDLE */ | |
1993 | if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) | |
1994 | return HPI_ERROR_DSP_HARDWARE; | |
1995 | ||
1996 | while (data_transferred < data_size) { | |
1997 | u32 this_copy = data_size - data_transferred; | |
1998 | ||
1999 | if (this_copy > HPI6205_SIZEOF_DATA) | |
2000 | this_copy = HPI6205_SIZEOF_DATA; | |
2001 | ||
2002 | if (operation == H620_HIF_SEND_DATA) | |
2003 | memcpy((void *)&interface->u.b_data[0], | |
2004 | &p_data[data_transferred], this_copy); | |
2005 | ||
2006 | interface->transfer_size_in_bytes = this_copy; | |
2007 | ||
719f82d3 EB |
2008 | /* DSP must change this back to nOperation */ |
2009 | interface->dsp_ack = H620_HIF_IDLE; | |
719f82d3 EB |
2010 | send_dsp_command(phw, operation); |
2011 | ||
719f82d3 EB |
2012 | temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT); |
2013 | HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n", | |
2014 | HPI6205_TIMEOUT - temp2, this_copy); | |
2015 | ||
2016 | if (!temp2) { | |
2017 | /* timed out */ | |
2018 | HPI_DEBUG_LOG(ERROR, | |
3285ea10 | 2019 | "Timed out waiting for " "state %d got %d\n", |
719f82d3 EB |
2020 | operation, interface->dsp_ack); |
2021 | ||
2022 | break; | |
2023 | } | |
719f82d3 EB |
2024 | if (operation == H620_HIF_GET_DATA) |
2025 | memcpy(&p_data[data_transferred], | |
2026 | (void *)&interface->u.b_data[0], this_copy); | |
2027 | ||
2028 | data_transferred += this_copy; | |
2029 | } | |
2030 | if (interface->dsp_ack != operation) | |
2031 | HPI_DEBUG_LOG(DEBUG, "interface->dsp_ack=%d, expected %d\n", | |
2032 | interface->dsp_ack, operation); | |
2033 | /* err=HPI_ERROR_DSP_HARDWARE; */ | |
2034 | ||
2035 | send_dsp_command(phw, H620_HIF_IDLE); | |
2036 | ||
2037 | return err; | |
2038 | } | |
2039 | ||
2040 | /* wait for up to timeout_us microseconds for the DSP | |
2041 | to signal state by DMA into dwDspAck | |
2042 | */ | |
2043 | static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us) | |
2044 | { | |
2045 | struct bus_master_interface *interface = phw->p_interface_buffer; | |
2046 | int t = timeout_us / 4; | |
2047 | ||
2048 | rmb(); /* ensure interface->dsp_ack is up to date */ | |
2049 | while ((interface->dsp_ack != state) && --t) { | |
2050 | hpios_delay_micro_seconds(4); | |
2051 | rmb(); /* DSP changes dsp_ack by DMA */ | |
2052 | } | |
2053 | ||
2054 | /*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */ | |
2055 | return t * 4; | |
2056 | } | |
2057 | ||
2058 | /* set the busmaster interface to cmd, then interrupt the DSP */ | |
2059 | static void send_dsp_command(struct hpi_hw_obj *phw, int cmd) | |
2060 | { | |
2061 | struct bus_master_interface *interface = phw->p_interface_buffer; | |
2062 | ||
2063 | u32 r; | |
2064 | ||
2065 | interface->host_cmd = cmd; | |
2066 | wmb(); /* DSP gets state by DMA, make sure it is written to memory */ | |
2067 | /* before we interrupt the DSP */ | |
2068 | r = ioread32(phw->prHDCR); | |
2069 | r |= (u32)C6205_HDCR_DSPINT; | |
2070 | iowrite32(r, phw->prHDCR); | |
2071 | r &= ~(u32)C6205_HDCR_DSPINT; | |
2072 | iowrite32(r, phw->prHDCR); | |
2073 | } | |
2074 | ||
2075 | static unsigned int message_count; | |
2076 | ||
2077 | static u16 message_response_sequence(struct hpi_adapter_obj *pao, | |
2078 | struct hpi_message *phm, struct hpi_response *phr) | |
2079 | { | |
719f82d3 EB |
2080 | u32 time_out, time_out2; |
2081 | struct hpi_hw_obj *phw = pao->priv; | |
2082 | struct bus_master_interface *interface = phw->p_interface_buffer; | |
2083 | u16 err = 0; | |
2084 | ||
2085 | message_count++; | |
3285ea10 | 2086 | if (phm->size > sizeof(interface->u)) { |
deb21a23 | 2087 | phr->error = HPI_ERROR_MESSAGE_BUFFER_TOO_SMALL; |
3285ea10 EB |
2088 | phr->specific_error = sizeof(interface->u); |
2089 | phr->size = sizeof(struct hpi_response_header); | |
2090 | HPI_DEBUG_LOG(ERROR, | |
a2800300 | 2091 | "message len %d too big for buffer %zd \n", phm->size, |
3285ea10 EB |
2092 | sizeof(interface->u)); |
2093 | return 0; | |
2094 | } | |
2095 | ||
719f82d3 EB |
2096 | /* Assume buffer of type struct bus_master_interface |
2097 | is allocated "noncacheable" */ | |
2098 | ||
2099 | if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) { | |
2100 | HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n"); | |
3285ea10 | 2101 | return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT; |
719f82d3 | 2102 | } |
3285ea10 EB |
2103 | |
2104 | memcpy(&interface->u.message_buffer, phm, phm->size); | |
719f82d3 EB |
2105 | /* signal we want a response */ |
2106 | send_dsp_command(phw, H620_HIF_GET_RESP); | |
2107 | ||
2108 | time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT); | |
2109 | ||
3285ea10 | 2110 | if (!time_out2) { |
719f82d3 | 2111 | HPI_DEBUG_LOG(ERROR, |
3285ea10 | 2112 | "(%u) Timed out waiting for " "GET_RESP state [%x]\n", |
719f82d3 EB |
2113 | message_count, interface->dsp_ack); |
2114 | } else { | |
2115 | HPI_DEBUG_LOG(VERBOSE, | |
2116 | "(%u) transition to GET_RESP after %u\n", | |
2117 | message_count, HPI6205_TIMEOUT - time_out2); | |
2118 | } | |
2119 | /* spin waiting on HIF interrupt flag (end of msg process) */ | |
2120 | time_out = HPI6205_TIMEOUT; | |
2121 | ||
719f82d3 | 2122 | /* read the result */ |
3285ea10 EB |
2123 | if (time_out) { |
2124 | if (interface->u.response_buffer.size <= phr->size) | |
2125 | memcpy(phr, &interface->u.response_buffer, | |
2126 | interface->u.response_buffer.size); | |
2127 | else { | |
2128 | HPI_DEBUG_LOG(ERROR, | |
2129 | "response len %d too big for buffer %d\n", | |
2130 | interface->u.response_buffer.size, phr->size); | |
2131 | memcpy(phr, &interface->u.response_buffer, | |
2132 | sizeof(struct hpi_response_header)); | |
2133 | phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL; | |
2134 | phr->specific_error = | |
2135 | interface->u.response_buffer.size; | |
2136 | phr->size = sizeof(struct hpi_response_header); | |
2137 | } | |
2138 | } | |
719f82d3 EB |
2139 | /* set interface back to idle */ |
2140 | send_dsp_command(phw, H620_HIF_IDLE); | |
2141 | ||
3285ea10 | 2142 | if (!time_out || !time_out2) { |
719f82d3 | 2143 | HPI_DEBUG_LOG(DEBUG, "something timed out!\n"); |
3285ea10 | 2144 | return HPI6205_ERROR_MSG_RESP_TIMEOUT; |
719f82d3 EB |
2145 | } |
2146 | /* special case for adapter close - */ | |
2147 | /* wait for the DSP to indicate it is idle */ | |
2148 | if (phm->function == HPI_ADAPTER_CLOSE) { | |
2149 | if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) { | |
2150 | HPI_DEBUG_LOG(DEBUG, | |
3285ea10 | 2151 | "Timeout waiting for idle " |
719f82d3 | 2152 | "(on adapter_close)\n"); |
3285ea10 | 2153 | return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT; |
719f82d3 EB |
2154 | } |
2155 | } | |
2156 | err = hpi_validate_response(phm, phr); | |
2157 | return err; | |
2158 | } | |
2159 | ||
2160 | static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, | |
2161 | struct hpi_response *phr) | |
2162 | { | |
2163 | ||
2164 | u16 err = 0; | |
2165 | ||
2166 | hpios_dsplock_lock(pao); | |
2167 | ||
2168 | err = message_response_sequence(pao, phm, phr); | |
2169 | ||
2170 | /* maybe an error response */ | |
2171 | if (err) { | |
2172 | /* something failed in the HPI/DSP interface */ | |
0a00044d EB |
2173 | if (err >= HPI_ERROR_BACKEND_BASE) { |
2174 | phr->error = HPI_ERROR_DSP_COMMUNICATION; | |
2175 | phr->specific_error = err; | |
2176 | } else { | |
2177 | phr->error = err; | |
2178 | } | |
2179 | ||
719f82d3 EB |
2180 | pao->dsp_crashed++; |
2181 | ||
2182 | /* just the header of the response is valid */ | |
2183 | phr->size = sizeof(struct hpi_response_header); | |
2184 | goto err; | |
2185 | } else | |
2186 | pao->dsp_crashed = 0; | |
2187 | ||
2188 | if (phr->error != 0) /* something failed in the DSP */ | |
2189 | goto err; | |
2190 | ||
2191 | switch (phm->function) { | |
2192 | case HPI_OSTREAM_WRITE: | |
2193 | case HPI_ISTREAM_ANC_WRITE: | |
2194 | err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data, | |
2195 | phm->u.d.u.data.data_size, H620_HIF_SEND_DATA); | |
2196 | break; | |
2197 | ||
2198 | case HPI_ISTREAM_READ: | |
2199 | case HPI_OSTREAM_ANC_READ: | |
2200 | err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data, | |
2201 | phm->u.d.u.data.data_size, H620_HIF_GET_DATA); | |
2202 | break; | |
2203 | ||
2204 | case HPI_CONTROL_SET_STATE: | |
2205 | if (phm->object == HPI_OBJ_CONTROLEX | |
2206 | && phm->u.cx.attribute == HPI_COBRANET_SET_DATA) | |
2207 | err = hpi6205_transfer_data(pao, | |
2208 | phm->u.cx.u.cobranet_bigdata.pb_data, | |
2209 | phm->u.cx.u.cobranet_bigdata.byte_count, | |
2210 | H620_HIF_SEND_DATA); | |
2211 | break; | |
2212 | ||
2213 | case HPI_CONTROL_GET_STATE: | |
2214 | if (phm->object == HPI_OBJ_CONTROLEX | |
2215 | && phm->u.cx.attribute == HPI_COBRANET_GET_DATA) | |
2216 | err = hpi6205_transfer_data(pao, | |
2217 | phm->u.cx.u.cobranet_bigdata.pb_data, | |
2218 | phr->u.cx.u.cobranet_data.byte_count, | |
2219 | H620_HIF_GET_DATA); | |
2220 | break; | |
2221 | } | |
2222 | phr->error = err; | |
2223 | ||
2224 | err: | |
2225 | hpios_dsplock_unlock(pao); | |
2226 | ||
2227 | return; | |
2228 | } |