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1da177e4 LT |
1 | /* |
2 | * Driver for C-Media CMI8338 and 8738 PCI soundcards. | |
3 | * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | /* Does not work. Warning may block system in capture mode */ | |
21 | /* #define USE_VAR48KRATE */ | |
22 | ||
23 | #include <sound/driver.h> | |
24 | #include <asm/io.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/gameport.h> | |
31 | #include <linux/moduleparam.h> | |
32 | #include <sound/core.h> | |
33 | #include <sound/info.h> | |
34 | #include <sound/control.h> | |
35 | #include <sound/pcm.h> | |
36 | #include <sound/rawmidi.h> | |
37 | #include <sound/mpu401.h> | |
38 | #include <sound/opl3.h> | |
39 | #include <sound/sb.h> | |
40 | #include <sound/asoundef.h> | |
41 | #include <sound/initval.h> | |
42 | ||
43 | MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); | |
44 | MODULE_DESCRIPTION("C-Media CMI8x38 PCI"); | |
45 | MODULE_LICENSE("GPL"); | |
46 | MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738}," | |
47 | "{C-Media,CMI8738B}," | |
48 | "{C-Media,CMI8338A}," | |
49 | "{C-Media,CMI8338B}}"); | |
50 | ||
51 | #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) | |
52 | #define SUPPORT_JOYSTICK 1 | |
53 | #endif | |
54 | ||
55 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
56 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
57 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ | |
58 | static long mpu_port[SNDRV_CARDS]; | |
59 | static long fm_port[SNDRV_CARDS]; | |
60 | static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; | |
61 | #ifdef SUPPORT_JOYSTICK | |
62 | static int joystick_port[SNDRV_CARDS]; | |
63 | #endif | |
64 | ||
65 | module_param_array(index, int, NULL, 0444); | |
66 | MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard."); | |
67 | module_param_array(id, charp, NULL, 0444); | |
68 | MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard."); | |
69 | module_param_array(enable, bool, NULL, 0444); | |
70 | MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard."); | |
71 | module_param_array(mpu_port, long, NULL, 0444); | |
72 | MODULE_PARM_DESC(mpu_port, "MPU-401 port."); | |
73 | module_param_array(fm_port, long, NULL, 0444); | |
74 | MODULE_PARM_DESC(fm_port, "FM port."); | |
75 | module_param_array(soft_ac3, bool, NULL, 0444); | |
76 | MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only)."); | |
77 | #ifdef SUPPORT_JOYSTICK | |
78 | module_param_array(joystick_port, int, NULL, 0444); | |
79 | MODULE_PARM_DESC(joystick_port, "Joystick port address."); | |
80 | #endif | |
81 | ||
1da177e4 LT |
82 | /* |
83 | * CM8x38 registers definition | |
84 | */ | |
85 | ||
86 | #define CM_REG_FUNCTRL0 0x00 | |
87 | #define CM_RST_CH1 0x00080000 | |
88 | #define CM_RST_CH0 0x00040000 | |
89 | #define CM_CHEN1 0x00020000 /* ch1: enable */ | |
90 | #define CM_CHEN0 0x00010000 /* ch0: enable */ | |
91 | #define CM_PAUSE1 0x00000008 /* ch1: pause */ | |
92 | #define CM_PAUSE0 0x00000004 /* ch0: pause */ | |
93 | #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */ | |
94 | #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */ | |
95 | ||
96 | #define CM_REG_FUNCTRL1 0x04 | |
97 | #define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */ | |
98 | #define CM_ASFC_SHIFT 13 | |
99 | #define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */ | |
100 | #define CM_DSFC_SHIFT 10 | |
101 | #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */ | |
102 | #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */ | |
103 | #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */ | |
104 | #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */ | |
105 | #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */ | |
106 | #define CM_BREQ 0x00000010 /* bus master enabled */ | |
107 | #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */ | |
108 | #define CM_UART_EN 0x00000004 /* UART */ | |
109 | #define CM_JYSTK_EN 0x00000002 /* joy stick */ | |
110 | ||
111 | #define CM_REG_CHFORMAT 0x08 | |
112 | ||
113 | #define CM_CHB3D5C 0x80000000 /* 5,6 channels */ | |
114 | #define CM_CHB3D 0x20000000 /* 4 channels */ | |
115 | ||
116 | #define CM_CHIP_MASK1 0x1f000000 | |
117 | #define CM_CHIP_037 0x01000000 | |
118 | ||
119 | #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */ | |
120 | #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */ | |
121 | #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */ | |
122 | /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */ | |
123 | ||
124 | #define CM_ADCBITLEN_MASK 0x0000C000 | |
125 | #define CM_ADCBITLEN_16 0x00000000 | |
126 | #define CM_ADCBITLEN_15 0x00004000 | |
127 | #define CM_ADCBITLEN_14 0x00008000 | |
128 | #define CM_ADCBITLEN_13 0x0000C000 | |
129 | ||
130 | #define CM_ADCDACLEN_MASK 0x00003000 | |
131 | #define CM_ADCDACLEN_060 0x00000000 | |
132 | #define CM_ADCDACLEN_066 0x00001000 | |
133 | #define CM_ADCDACLEN_130 0x00002000 | |
134 | #define CM_ADCDACLEN_280 0x00003000 | |
135 | ||
136 | #define CM_CH1_SRATE_176K 0x00000800 | |
137 | #define CM_CH1_SRATE_88K 0x00000400 | |
138 | #define CM_CH0_SRATE_176K 0x00000200 | |
139 | #define CM_CH0_SRATE_88K 0x00000100 | |
140 | ||
141 | #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */ | |
142 | ||
143 | #define CM_CH1FMT_MASK 0x0000000C | |
144 | #define CM_CH1FMT_SHIFT 2 | |
145 | #define CM_CH0FMT_MASK 0x00000003 | |
146 | #define CM_CH0FMT_SHIFT 0 | |
147 | ||
148 | #define CM_REG_INT_HLDCLR 0x0C | |
149 | #define CM_CHIP_MASK2 0xff000000 | |
150 | #define CM_CHIP_039 0x04000000 | |
151 | #define CM_CHIP_039_6CH 0x01000000 | |
152 | #define CM_CHIP_055 0x08000000 | |
153 | #define CM_CHIP_8768 0x20000000 | |
154 | #define CM_TDMA_INT_EN 0x00040000 | |
155 | #define CM_CH1_INT_EN 0x00020000 | |
156 | #define CM_CH0_INT_EN 0x00010000 | |
157 | #define CM_INT_HOLD 0x00000002 | |
158 | #define CM_INT_CLEAR 0x00000001 | |
159 | ||
160 | #define CM_REG_INT_STATUS 0x10 | |
161 | #define CM_INTR 0x80000000 | |
162 | #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */ | |
163 | #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */ | |
164 | #define CM_UARTINT 0x00010000 | |
165 | #define CM_LTDMAINT 0x00008000 | |
166 | #define CM_HTDMAINT 0x00004000 | |
167 | #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */ | |
168 | #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */ | |
169 | #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */ | |
170 | #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */ | |
171 | #define CM_CH1BUSY 0x00000008 | |
172 | #define CM_CH0BUSY 0x00000004 | |
173 | #define CM_CHINT1 0x00000002 | |
174 | #define CM_CHINT0 0x00000001 | |
175 | ||
176 | #define CM_REG_LEGACY_CTRL 0x14 | |
177 | #define CM_NXCHG 0x80000000 /* h/w multi channels? */ | |
178 | #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */ | |
179 | #define CM_VMPU_330 0x00000000 | |
180 | #define CM_VMPU_320 0x20000000 | |
181 | #define CM_VMPU_310 0x40000000 | |
182 | #define CM_VMPU_300 0x60000000 | |
183 | #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */ | |
184 | #define CM_VSBSEL_220 0x00000000 | |
185 | #define CM_VSBSEL_240 0x04000000 | |
186 | #define CM_VSBSEL_260 0x08000000 | |
187 | #define CM_VSBSEL_280 0x0C000000 | |
188 | #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */ | |
189 | #define CM_FMSEL_388 0x00000000 | |
190 | #define CM_FMSEL_3C8 0x01000000 | |
191 | #define CM_FMSEL_3E0 0x02000000 | |
192 | #define CM_FMSEL_3E8 0x03000000 | |
193 | #define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */ | |
194 | #define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */ | |
195 | #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */ | |
196 | #define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */ | |
197 | #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */ | |
198 | #define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */ | |
199 | ||
200 | #define CM_REG_MISC_CTRL 0x18 | |
201 | #define CM_PWD 0x80000000 | |
202 | #define CM_RESET 0x40000000 | |
203 | #define CM_SFIL_MASK 0x30000000 | |
204 | #define CM_TXVX 0x08000000 | |
205 | #define CM_N4SPK3D 0x04000000 /* 4ch output */ | |
206 | #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */ | |
207 | #define CM_SPDIF48K 0x01000000 /* write */ | |
208 | #define CM_SPATUS48K 0x01000000 /* read */ | |
209 | #define CM_ENDBDAC 0x00800000 /* enable dual dac */ | |
210 | #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */ | |
211 | #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */ | |
212 | #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */ | |
213 | #define CM_FM_EN 0x00080000 /* enalbe FM */ | |
214 | #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */ | |
215 | #define CM_VIDWPDSB 0x00010000 | |
216 | #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */ | |
217 | #define CM_MASK_EN 0x00004000 | |
218 | #define CM_VIDWPPRT 0x00002000 | |
219 | #define CM_SFILENB 0x00001000 | |
220 | #define CM_MMODE_MASK 0x00000E00 | |
221 | #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */ | |
222 | #define CM_ENCENTER 0x00000080 | |
223 | #define CM_FLINKON 0x00000040 | |
224 | #define CM_FLINKOFF 0x00000020 | |
225 | #define CM_MIDSMP 0x00000010 | |
226 | #define CM_UPDDMA_MASK 0x0000000C | |
227 | #define CM_TWAIT_MASK 0x00000003 | |
228 | ||
229 | /* byte */ | |
230 | #define CM_REG_MIXER0 0x20 | |
231 | ||
232 | #define CM_REG_SB16_DATA 0x22 | |
233 | #define CM_REG_SB16_ADDR 0x23 | |
234 | ||
235 | #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */ | |
236 | #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */ | |
237 | #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */ | |
238 | #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */ | |
239 | ||
240 | #define CM_REG_MIXER1 0x24 | |
241 | #define CM_FMMUTE 0x80 /* mute FM */ | |
242 | #define CM_FMMUTE_SHIFT 7 | |
243 | #define CM_WSMUTE 0x40 /* mute PCM */ | |
244 | #define CM_WSMUTE_SHIFT 6 | |
245 | #define CM_SPK4 0x20 /* lin-in -> rear line out */ | |
246 | #define CM_SPK4_SHIFT 5 | |
247 | #define CM_REAR2FRONT 0x10 /* exchange rear/front */ | |
248 | #define CM_REAR2FRONT_SHIFT 4 | |
249 | #define CM_WAVEINL 0x08 /* digital wave rec. left chan */ | |
250 | #define CM_WAVEINL_SHIFT 3 | |
251 | #define CM_WAVEINR 0x04 /* digical wave rec. right */ | |
252 | #define CM_WAVEINR_SHIFT 2 | |
253 | #define CM_X3DEN 0x02 /* 3D surround enable */ | |
254 | #define CM_X3DEN_SHIFT 1 | |
255 | #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */ | |
256 | #define CM_CDPLAY_SHIFT 0 | |
257 | ||
258 | #define CM_REG_MIXER2 0x25 | |
259 | #define CM_RAUXREN 0x80 /* AUX right capture */ | |
260 | #define CM_RAUXREN_SHIFT 7 | |
261 | #define CM_RAUXLEN 0x40 /* AUX left capture */ | |
262 | #define CM_RAUXLEN_SHIFT 6 | |
263 | #define CM_VAUXRM 0x20 /* AUX right mute */ | |
264 | #define CM_VAUXRM_SHIFT 5 | |
265 | #define CM_VAUXLM 0x10 /* AUX left mute */ | |
266 | #define CM_VAUXLM_SHIFT 4 | |
267 | #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */ | |
268 | #define CM_VADMIC_SHIFT 1 | |
269 | #define CM_MICGAINZ 0x01 /* mic boost */ | |
270 | #define CM_MICGAINZ_SHIFT 0 | |
271 | ||
cb60e5f5 | 272 | #define CM_REG_MIXER3 0x24 |
1da177e4 LT |
273 | #define CM_REG_AUX_VOL 0x26 |
274 | #define CM_VAUXL_MASK 0xf0 | |
275 | #define CM_VAUXR_MASK 0x0f | |
276 | ||
277 | #define CM_REG_MISC 0x27 | |
278 | #define CM_XGPO1 0x20 | |
279 | // #define CM_XGPBIO 0x04 | |
280 | #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */ | |
281 | #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */ | |
282 | #define CM_SPDVALID 0x02 /* spdif input valid check */ | |
283 | #define CM_DMAUTO 0x01 | |
284 | ||
285 | #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */ | |
286 | /* | |
287 | * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738 | |
288 | * or identical with AC97 codec? | |
289 | */ | |
290 | #define CM_REG_EXTERN_CODEC CM_REG_AC97 | |
291 | ||
292 | /* | |
293 | * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6) | |
294 | */ | |
295 | #define CM_REG_MPU_PCI 0x40 | |
296 | ||
297 | /* | |
298 | * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6) | |
299 | */ | |
300 | #define CM_REG_FM_PCI 0x50 | |
301 | ||
302 | /* | |
2eff7ec8 | 303 | * access from SB-mixer port |
1da177e4 LT |
304 | */ |
305 | #define CM_REG_EXTENT_IND 0xf0 | |
306 | #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */ | |
307 | #define CM_VPHONE_SHIFT 5 | |
308 | #define CM_VPHOM 0x10 /* Phone mute control */ | |
309 | #define CM_VSPKM 0x08 /* Speaker mute control, default high */ | |
310 | #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */ | |
311 | #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */ | |
2eff7ec8 | 312 | #define CM_VADMIC3 0x01 /* Mic record boost */ |
1da177e4 LT |
313 | |
314 | /* | |
315 | * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738): | |
316 | * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL | |
317 | * unit (readonly?). | |
318 | */ | |
319 | #define CM_REG_PLL 0xf8 | |
320 | ||
321 | /* | |
322 | * extended registers | |
323 | */ | |
324 | #define CM_REG_CH0_FRAME1 0x80 /* base address */ | |
325 | #define CM_REG_CH0_FRAME2 0x84 | |
326 | #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */ | |
327 | #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */ | |
cb60e5f5 | 328 | #define CM_REG_EXT_MISC 0x90 |
1da177e4 LT |
329 | #define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */ |
330 | #define CM_CHB3D8C 0x20 /* 7.1 channels support */ | |
331 | #define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */ | |
332 | #define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */ | |
333 | #define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */ | |
334 | #define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */ | |
335 | #define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */ | |
336 | ||
337 | /* | |
338 | * size of i/o region | |
339 | */ | |
340 | #define CM_EXTENT_CODEC 0x100 | |
341 | #define CM_EXTENT_MIDI 0x2 | |
342 | #define CM_EXTENT_SYNTH 0x4 | |
343 | ||
344 | ||
1da177e4 LT |
345 | /* |
346 | * channels for playback / capture | |
347 | */ | |
348 | #define CM_CH_PLAY 0 | |
349 | #define CM_CH_CAPT 1 | |
350 | ||
351 | /* | |
352 | * flags to check device open/close | |
353 | */ | |
354 | #define CM_OPEN_NONE 0 | |
355 | #define CM_OPEN_CH_MASK 0x01 | |
356 | #define CM_OPEN_DAC 0x10 | |
357 | #define CM_OPEN_ADC 0x20 | |
358 | #define CM_OPEN_SPDIF 0x40 | |
359 | #define CM_OPEN_MCHAN 0x80 | |
360 | #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC) | |
361 | #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC) | |
362 | #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN) | |
363 | #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC) | |
364 | #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF) | |
365 | #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF) | |
366 | ||
367 | ||
368 | #if CM_CH_PLAY == 1 | |
369 | #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K | |
370 | #define CM_PLAYBACK_SPDF CM_SPDF_1 | |
371 | #define CM_CAPTURE_SPDF CM_SPDF_0 | |
372 | #else | |
373 | #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K | |
374 | #define CM_PLAYBACK_SPDF CM_SPDF_0 | |
375 | #define CM_CAPTURE_SPDF CM_SPDF_1 | |
376 | #endif | |
377 | ||
378 | ||
379 | /* | |
380 | * driver data | |
381 | */ | |
382 | ||
2cbdb686 TI |
383 | struct cmipci_pcm { |
384 | struct snd_pcm_substream *substream; | |
1da177e4 LT |
385 | int running; /* dac/adc running? */ |
386 | unsigned int dma_size; /* in frames */ | |
387 | unsigned int period_size; /* in frames */ | |
388 | unsigned int offset; /* physical address of the buffer */ | |
389 | unsigned int fmt; /* format bits */ | |
390 | int ch; /* channel (0/1) */ | |
391 | unsigned int is_dac; /* is dac? */ | |
392 | int bytes_per_frame; | |
393 | int shift; | |
394 | }; | |
395 | ||
396 | /* mixer elements toggled/resumed during ac3 playback */ | |
397 | struct cmipci_mixer_auto_switches { | |
398 | const char *name; /* switch to toggle */ | |
399 | int toggle_on; /* value to change when ac3 mode */ | |
400 | }; | |
401 | static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = { | |
402 | {"PCM Playback Switch", 0}, | |
403 | {"IEC958 Output Switch", 1}, | |
404 | {"IEC958 Mix Analog", 0}, | |
405 | // {"IEC958 Out To DAC", 1}, // no longer used | |
406 | {"IEC958 Loop", 0}, | |
407 | }; | |
408 | #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer) | |
409 | ||
2cbdb686 TI |
410 | struct cmipci { |
411 | struct snd_card *card; | |
1da177e4 LT |
412 | |
413 | struct pci_dev *pci; | |
414 | unsigned int device; /* device ID */ | |
415 | int irq; | |
416 | ||
417 | unsigned long iobase; | |
418 | unsigned int ctrl; /* FUNCTRL0 current value */ | |
419 | ||
2cbdb686 TI |
420 | struct snd_pcm *pcm; /* DAC/ADC PCM */ |
421 | struct snd_pcm *pcm2; /* 2nd DAC */ | |
422 | struct snd_pcm *pcm_spdif; /* SPDIF */ | |
1da177e4 LT |
423 | |
424 | int chip_version; | |
425 | int max_channels; | |
426 | unsigned int has_dual_dac: 1; | |
427 | unsigned int can_ac3_sw: 1; | |
428 | unsigned int can_ac3_hw: 1; | |
429 | unsigned int can_multi_ch: 1; | |
430 | unsigned int do_soft_ac3: 1; | |
431 | ||
432 | unsigned int spdif_playback_avail: 1; /* spdif ready? */ | |
433 | unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */ | |
434 | int spdif_counter; /* for software AC3 */ | |
435 | ||
436 | unsigned int dig_status; | |
437 | unsigned int dig_pcm_status; | |
438 | ||
2cbdb686 | 439 | struct snd_pcm_hardware *hw_info[3]; /* for playbacks */ |
1da177e4 LT |
440 | |
441 | int opened[2]; /* open mode */ | |
442 | struct semaphore open_mutex; | |
443 | ||
444 | unsigned int mixer_insensitive: 1; | |
2cbdb686 | 445 | struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS]; |
1da177e4 LT |
446 | int mixer_res_status[CM_SAVED_MIXERS]; |
447 | ||
2cbdb686 | 448 | struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */ |
1da177e4 LT |
449 | |
450 | /* external MIDI */ | |
2cbdb686 | 451 | struct snd_rawmidi *rmidi; |
1da177e4 LT |
452 | |
453 | #ifdef SUPPORT_JOYSTICK | |
454 | struct gameport *gameport; | |
455 | #endif | |
456 | ||
457 | spinlock_t reg_lock; | |
cb60e5f5 TI |
458 | |
459 | #ifdef CONFIG_PM | |
460 | unsigned int saved_regs[0x20]; | |
461 | unsigned char saved_mixers[0x20]; | |
462 | #endif | |
1da177e4 LT |
463 | }; |
464 | ||
465 | ||
466 | /* read/write operations for dword register */ | |
2cbdb686 | 467 | static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data) |
1da177e4 LT |
468 | { |
469 | outl(data, cm->iobase + cmd); | |
470 | } | |
77933d72 | 471 | |
2cbdb686 | 472 | static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd) |
1da177e4 LT |
473 | { |
474 | return inl(cm->iobase + cmd); | |
475 | } | |
476 | ||
477 | /* read/write operations for word register */ | |
2cbdb686 | 478 | static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data) |
1da177e4 LT |
479 | { |
480 | outw(data, cm->iobase + cmd); | |
481 | } | |
77933d72 | 482 | |
2cbdb686 | 483 | static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd) |
1da177e4 LT |
484 | { |
485 | return inw(cm->iobase + cmd); | |
486 | } | |
487 | ||
488 | /* read/write operations for byte register */ | |
2cbdb686 | 489 | static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data) |
1da177e4 LT |
490 | { |
491 | outb(data, cm->iobase + cmd); | |
492 | } | |
493 | ||
2cbdb686 | 494 | static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd) |
1da177e4 LT |
495 | { |
496 | return inb(cm->iobase + cmd); | |
497 | } | |
498 | ||
499 | /* bit operations for dword register */ | |
2cbdb686 | 500 | static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag) |
1da177e4 | 501 | { |
01d25d46 TI |
502 | unsigned int val, oval; |
503 | val = oval = inl(cm->iobase + cmd); | |
1da177e4 | 504 | val |= flag; |
01d25d46 TI |
505 | if (val == oval) |
506 | return 0; | |
1da177e4 | 507 | outl(val, cm->iobase + cmd); |
01d25d46 | 508 | return 1; |
1da177e4 LT |
509 | } |
510 | ||
2cbdb686 | 511 | static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag) |
1da177e4 | 512 | { |
01d25d46 TI |
513 | unsigned int val, oval; |
514 | val = oval = inl(cm->iobase + cmd); | |
1da177e4 | 515 | val &= ~flag; |
01d25d46 TI |
516 | if (val == oval) |
517 | return 0; | |
1da177e4 | 518 | outl(val, cm->iobase + cmd); |
01d25d46 | 519 | return 1; |
1da177e4 LT |
520 | } |
521 | ||
1da177e4 | 522 | /* bit operations for byte register */ |
2cbdb686 | 523 | static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag) |
1da177e4 | 524 | { |
01d25d46 TI |
525 | unsigned char val, oval; |
526 | val = oval = inb(cm->iobase + cmd); | |
1da177e4 | 527 | val |= flag; |
01d25d46 TI |
528 | if (val == oval) |
529 | return 0; | |
1da177e4 | 530 | outb(val, cm->iobase + cmd); |
01d25d46 | 531 | return 1; |
1da177e4 LT |
532 | } |
533 | ||
2cbdb686 | 534 | static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag) |
1da177e4 | 535 | { |
01d25d46 TI |
536 | unsigned char val, oval; |
537 | val = oval = inb(cm->iobase + cmd); | |
1da177e4 | 538 | val &= ~flag; |
01d25d46 TI |
539 | if (val == oval) |
540 | return 0; | |
1da177e4 | 541 | outb(val, cm->iobase + cmd); |
01d25d46 | 542 | return 1; |
1da177e4 | 543 | } |
1da177e4 LT |
544 | |
545 | ||
546 | /* | |
547 | * PCM interface | |
548 | */ | |
549 | ||
550 | /* | |
551 | * calculate frequency | |
552 | */ | |
553 | ||
554 | static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 }; | |
555 | ||
556 | static unsigned int snd_cmipci_rate_freq(unsigned int rate) | |
557 | { | |
558 | unsigned int i; | |
559 | for (i = 0; i < ARRAY_SIZE(rates); i++) { | |
560 | if (rates[i] == rate) | |
561 | return i; | |
562 | } | |
563 | snd_BUG(); | |
564 | return 0; | |
565 | } | |
566 | ||
567 | #ifdef USE_VAR48KRATE | |
568 | /* | |
569 | * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???) | |
570 | * does it this way .. maybe not. Never get any information from C-Media about | |
571 | * that <werner@suse.de>. | |
572 | */ | |
573 | static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n) | |
574 | { | |
575 | unsigned int delta, tolerance; | |
576 | int xm, xn, xr; | |
577 | ||
578 | for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5)) | |
579 | rate <<= 1; | |
580 | *n = -1; | |
581 | if (*r > 0xff) | |
582 | goto out; | |
583 | tolerance = rate*CM_TOLERANCE_RATE; | |
584 | ||
585 | for (xn = (1+2); xn < (0x1f+2); xn++) { | |
586 | for (xm = (1+2); xm < (0xff+2); xm++) { | |
587 | xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn; | |
588 | ||
589 | if (xr < rate) | |
590 | delta = rate - xr; | |
591 | else | |
592 | delta = xr - rate; | |
593 | ||
594 | /* | |
595 | * If we found one, remember this, | |
596 | * and try to find a closer one | |
597 | */ | |
598 | if (delta < tolerance) { | |
599 | tolerance = delta; | |
600 | *m = xm - 2; | |
601 | *n = xn - 2; | |
602 | } | |
603 | } | |
604 | } | |
605 | out: | |
606 | return (*n > -1); | |
607 | } | |
608 | ||
609 | /* | |
610 | * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff | |
611 | * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen | |
612 | * at the register CM_REG_FUNCTRL1 (0x04). | |
613 | * Problem: other ways are also possible (any information about that?) | |
614 | */ | |
2cbdb686 | 615 | static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot) |
1da177e4 LT |
616 | { |
617 | unsigned int reg = CM_REG_PLL + slot; | |
618 | /* | |
619 | * Guess that this programs at reg. 0x04 the pos 15:13/12:10 | |
620 | * for DSFC/ASFC (000 upto 111). | |
621 | */ | |
622 | ||
623 | /* FIXME: Init (Do we've to set an other register first before programming?) */ | |
624 | ||
625 | /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */ | |
626 | snd_cmipci_write_b(cm, reg, rate>>8); | |
627 | snd_cmipci_write_b(cm, reg, rate&0xff); | |
628 | ||
629 | /* FIXME: Setup (Do we've to set an other register first to enable this?) */ | |
630 | } | |
631 | #endif /* USE_VAR48KRATE */ | |
632 | ||
2cbdb686 TI |
633 | static int snd_cmipci_hw_params(struct snd_pcm_substream *substream, |
634 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 LT |
635 | { |
636 | return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
637 | } | |
638 | ||
2cbdb686 TI |
639 | static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream, |
640 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 | 641 | { |
2cbdb686 | 642 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
643 | if (params_channels(hw_params) > 2) { |
644 | down(&cm->open_mutex); | |
645 | if (cm->opened[CM_CH_PLAY]) { | |
646 | up(&cm->open_mutex); | |
647 | return -EBUSY; | |
648 | } | |
649 | /* reserve the channel A */ | |
650 | cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI; | |
651 | up(&cm->open_mutex); | |
652 | } | |
653 | return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
654 | } | |
655 | ||
2cbdb686 | 656 | static void snd_cmipci_ch_reset(struct cmipci *cm, int ch) |
1da177e4 LT |
657 | { |
658 | int reset = CM_RST_CH0 << (cm->channel[ch].ch); | |
659 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); | |
660 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); | |
661 | udelay(10); | |
662 | } | |
663 | ||
2cbdb686 | 664 | static int snd_cmipci_hw_free(struct snd_pcm_substream *substream) |
1da177e4 LT |
665 | { |
666 | return snd_pcm_lib_free_pages(substream); | |
667 | } | |
668 | ||
669 | ||
670 | /* | |
671 | */ | |
672 | ||
673 | static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8}; | |
2cbdb686 | 674 | static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = { |
1da177e4 LT |
675 | .count = 3, |
676 | .list = hw_channels, | |
677 | .mask = 0, | |
678 | }; | |
2cbdb686 | 679 | static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = { |
1da177e4 LT |
680 | .count = 5, |
681 | .list = hw_channels, | |
682 | .mask = 0, | |
683 | }; | |
2cbdb686 | 684 | static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = { |
1da177e4 LT |
685 | .count = 6, |
686 | .list = hw_channels, | |
687 | .mask = 0, | |
688 | }; | |
689 | ||
2cbdb686 | 690 | static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels) |
1da177e4 LT |
691 | { |
692 | if (channels > 2) { | |
693 | if (! cm->can_multi_ch) | |
694 | return -EINVAL; | |
695 | if (rec->fmt != 0x03) /* stereo 16bit only */ | |
696 | return -EINVAL; | |
697 | ||
698 | spin_lock_irq(&cm->reg_lock); | |
699 | snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); | |
700 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); | |
701 | if (channels > 4) { | |
702 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); | |
703 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); | |
704 | } else { | |
705 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); | |
706 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); | |
707 | } | |
708 | if (channels >= 6) { | |
709 | snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); | |
710 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); | |
711 | } else { | |
712 | snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); | |
713 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); | |
714 | } | |
715 | if (cm->chip_version == 68) { | |
716 | if (channels == 8) { | |
717 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C); | |
718 | } else { | |
719 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C); | |
720 | } | |
721 | } | |
722 | spin_unlock_irq(&cm->reg_lock); | |
723 | ||
724 | } else { | |
725 | if (cm->can_multi_ch) { | |
726 | spin_lock_irq(&cm->reg_lock); | |
727 | snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); | |
728 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); | |
729 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); | |
730 | snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); | |
731 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); | |
732 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); | |
733 | spin_unlock_irq(&cm->reg_lock); | |
734 | } | |
735 | } | |
736 | return 0; | |
737 | } | |
738 | ||
739 | ||
740 | /* | |
741 | * prepare playback/capture channel | |
742 | * channel to be used must have been set in rec->ch. | |
743 | */ | |
2cbdb686 TI |
744 | static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec, |
745 | struct snd_pcm_substream *substream) | |
1da177e4 LT |
746 | { |
747 | unsigned int reg, freq, val; | |
2cbdb686 | 748 | struct snd_pcm_runtime *runtime = substream->runtime; |
1da177e4 LT |
749 | |
750 | rec->fmt = 0; | |
751 | rec->shift = 0; | |
752 | if (snd_pcm_format_width(runtime->format) >= 16) { | |
753 | rec->fmt |= 0x02; | |
754 | if (snd_pcm_format_width(runtime->format) > 16) | |
755 | rec->shift++; /* 24/32bit */ | |
756 | } | |
757 | if (runtime->channels > 1) | |
758 | rec->fmt |= 0x01; | |
759 | if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) { | |
760 | snd_printd("cannot set dac channels\n"); | |
761 | return -EINVAL; | |
762 | } | |
763 | ||
764 | rec->offset = runtime->dma_addr; | |
765 | /* buffer and period sizes in frame */ | |
766 | rec->dma_size = runtime->buffer_size << rec->shift; | |
767 | rec->period_size = runtime->period_size << rec->shift; | |
768 | if (runtime->channels > 2) { | |
769 | /* multi-channels */ | |
770 | rec->dma_size = (rec->dma_size * runtime->channels) / 2; | |
771 | rec->period_size = (rec->period_size * runtime->channels) / 2; | |
772 | } | |
773 | ||
774 | spin_lock_irq(&cm->reg_lock); | |
775 | ||
776 | /* set buffer address */ | |
777 | reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; | |
778 | snd_cmipci_write(cm, reg, rec->offset); | |
779 | /* program sample counts */ | |
780 | reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; | |
781 | snd_cmipci_write_w(cm, reg, rec->dma_size - 1); | |
782 | snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1); | |
783 | ||
784 | /* set adc/dac flag */ | |
785 | val = rec->ch ? CM_CHADC1 : CM_CHADC0; | |
786 | if (rec->is_dac) | |
787 | cm->ctrl &= ~val; | |
788 | else | |
789 | cm->ctrl |= val; | |
790 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); | |
791 | //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); | |
792 | ||
793 | /* set sample rate */ | |
794 | freq = snd_cmipci_rate_freq(runtime->rate); | |
795 | val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); | |
796 | if (rec->ch) { | |
797 | val &= ~CM_ASFC_MASK; | |
798 | val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK; | |
799 | } else { | |
800 | val &= ~CM_DSFC_MASK; | |
801 | val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK; | |
802 | } | |
803 | snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); | |
804 | //snd_printd("cmipci: functrl1 = %08x\n", val); | |
805 | ||
806 | /* set format */ | |
807 | val = snd_cmipci_read(cm, CM_REG_CHFORMAT); | |
808 | if (rec->ch) { | |
809 | val &= ~CM_CH1FMT_MASK; | |
810 | val |= rec->fmt << CM_CH1FMT_SHIFT; | |
811 | } else { | |
812 | val &= ~CM_CH0FMT_MASK; | |
813 | val |= rec->fmt << CM_CH0FMT_SHIFT; | |
814 | } | |
815 | snd_cmipci_write(cm, CM_REG_CHFORMAT, val); | |
816 | //snd_printd("cmipci: chformat = %08x\n", val); | |
817 | ||
818 | rec->running = 0; | |
819 | spin_unlock_irq(&cm->reg_lock); | |
820 | ||
821 | return 0; | |
822 | } | |
823 | ||
824 | /* | |
825 | * PCM trigger/stop | |
826 | */ | |
2cbdb686 TI |
827 | static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec, |
828 | struct snd_pcm_substream *substream, int cmd) | |
1da177e4 LT |
829 | { |
830 | unsigned int inthld, chen, reset, pause; | |
831 | int result = 0; | |
832 | ||
833 | inthld = CM_CH0_INT_EN << rec->ch; | |
834 | chen = CM_CHEN0 << rec->ch; | |
835 | reset = CM_RST_CH0 << rec->ch; | |
836 | pause = CM_PAUSE0 << rec->ch; | |
837 | ||
838 | spin_lock(&cm->reg_lock); | |
839 | switch (cmd) { | |
840 | case SNDRV_PCM_TRIGGER_START: | |
841 | rec->running = 1; | |
842 | /* set interrupt */ | |
843 | snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld); | |
844 | cm->ctrl |= chen; | |
845 | /* enable channel */ | |
846 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); | |
847 | //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); | |
848 | break; | |
849 | case SNDRV_PCM_TRIGGER_STOP: | |
850 | rec->running = 0; | |
851 | /* disable interrupt */ | |
852 | snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld); | |
853 | /* reset */ | |
854 | cm->ctrl &= ~chen; | |
855 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); | |
856 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); | |
857 | break; | |
858 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
cb60e5f5 | 859 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1da177e4 LT |
860 | cm->ctrl |= pause; |
861 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); | |
862 | break; | |
863 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
cb60e5f5 | 864 | case SNDRV_PCM_TRIGGER_RESUME: |
1da177e4 LT |
865 | cm->ctrl &= ~pause; |
866 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); | |
867 | break; | |
868 | default: | |
869 | result = -EINVAL; | |
870 | break; | |
871 | } | |
872 | spin_unlock(&cm->reg_lock); | |
873 | return result; | |
874 | } | |
875 | ||
876 | /* | |
877 | * return the current pointer | |
878 | */ | |
2cbdb686 TI |
879 | static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec, |
880 | struct snd_pcm_substream *substream) | |
1da177e4 LT |
881 | { |
882 | size_t ptr; | |
883 | unsigned int reg; | |
884 | if (!rec->running) | |
885 | return 0; | |
886 | #if 1 // this seems better.. | |
887 | reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; | |
888 | ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1); | |
889 | ptr >>= rec->shift; | |
890 | #else | |
891 | reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; | |
892 | ptr = snd_cmipci_read(cm, reg) - rec->offset; | |
893 | ptr = bytes_to_frames(substream->runtime, ptr); | |
894 | #endif | |
895 | if (substream->runtime->channels > 2) | |
896 | ptr = (ptr * 2) / substream->runtime->channels; | |
897 | return ptr; | |
898 | } | |
899 | ||
900 | /* | |
901 | * playback | |
902 | */ | |
903 | ||
2cbdb686 | 904 | static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream, |
1da177e4 LT |
905 | int cmd) |
906 | { | |
2cbdb686 | 907 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
908 | return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd); |
909 | } | |
910 | ||
2cbdb686 | 911 | static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 912 | { |
2cbdb686 | 913 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
914 | return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream); |
915 | } | |
916 | ||
917 | ||
918 | ||
919 | /* | |
920 | * capture | |
921 | */ | |
922 | ||
2cbdb686 | 923 | static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream, |
1da177e4 LT |
924 | int cmd) |
925 | { | |
2cbdb686 | 926 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
927 | return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd); |
928 | } | |
929 | ||
2cbdb686 | 930 | static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 931 | { |
2cbdb686 | 932 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
933 | return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream); |
934 | } | |
935 | ||
936 | ||
937 | /* | |
938 | * hw preparation for spdif | |
939 | */ | |
940 | ||
2cbdb686 TI |
941 | static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol, |
942 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
943 | { |
944 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
945 | uinfo->count = 1; | |
946 | return 0; | |
947 | } | |
948 | ||
2cbdb686 TI |
949 | static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol, |
950 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 951 | { |
2cbdb686 | 952 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
953 | int i; |
954 | ||
955 | spin_lock_irq(&chip->reg_lock); | |
956 | for (i = 0; i < 4; i++) | |
957 | ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff; | |
958 | spin_unlock_irq(&chip->reg_lock); | |
959 | return 0; | |
960 | } | |
961 | ||
2cbdb686 TI |
962 | static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol, |
963 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 964 | { |
2cbdb686 | 965 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
966 | int i, change; |
967 | unsigned int val; | |
968 | ||
969 | val = 0; | |
970 | spin_lock_irq(&chip->reg_lock); | |
971 | for (i = 0; i < 4; i++) | |
972 | val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); | |
973 | change = val != chip->dig_status; | |
974 | chip->dig_status = val; | |
975 | spin_unlock_irq(&chip->reg_lock); | |
976 | return change; | |
977 | } | |
978 | ||
2cbdb686 | 979 | static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata = |
1da177e4 LT |
980 | { |
981 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
982 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), | |
983 | .info = snd_cmipci_spdif_default_info, | |
984 | .get = snd_cmipci_spdif_default_get, | |
985 | .put = snd_cmipci_spdif_default_put | |
986 | }; | |
987 | ||
2cbdb686 TI |
988 | static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol, |
989 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
990 | { |
991 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
992 | uinfo->count = 1; | |
993 | return 0; | |
994 | } | |
995 | ||
2cbdb686 TI |
996 | static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol, |
997 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 LT |
998 | { |
999 | ucontrol->value.iec958.status[0] = 0xff; | |
1000 | ucontrol->value.iec958.status[1] = 0xff; | |
1001 | ucontrol->value.iec958.status[2] = 0xff; | |
1002 | ucontrol->value.iec958.status[3] = 0xff; | |
1003 | return 0; | |
1004 | } | |
1005 | ||
2cbdb686 | 1006 | static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata = |
1da177e4 LT |
1007 | { |
1008 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
67ed4161 | 1009 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
1010 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), |
1011 | .info = snd_cmipci_spdif_mask_info, | |
1012 | .get = snd_cmipci_spdif_mask_get, | |
1013 | }; | |
1014 | ||
2cbdb686 TI |
1015 | static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol, |
1016 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1017 | { |
1018 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1019 | uinfo->count = 1; | |
1020 | return 0; | |
1021 | } | |
1022 | ||
2cbdb686 TI |
1023 | static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol, |
1024 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1025 | { |
2cbdb686 | 1026 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1027 | int i; |
1028 | ||
1029 | spin_lock_irq(&chip->reg_lock); | |
1030 | for (i = 0; i < 4; i++) | |
1031 | ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff; | |
1032 | spin_unlock_irq(&chip->reg_lock); | |
1033 | return 0; | |
1034 | } | |
1035 | ||
2cbdb686 TI |
1036 | static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol, |
1037 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1038 | { |
2cbdb686 | 1039 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1040 | int i, change; |
1041 | unsigned int val; | |
1042 | ||
1043 | val = 0; | |
1044 | spin_lock_irq(&chip->reg_lock); | |
1045 | for (i = 0; i < 4; i++) | |
1046 | val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); | |
1047 | change = val != chip->dig_pcm_status; | |
1048 | chip->dig_pcm_status = val; | |
1049 | spin_unlock_irq(&chip->reg_lock); | |
1050 | return change; | |
1051 | } | |
1052 | ||
2cbdb686 | 1053 | static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata = |
1da177e4 LT |
1054 | { |
1055 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, | |
1056 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1057 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), | |
1058 | .info = snd_cmipci_spdif_stream_info, | |
1059 | .get = snd_cmipci_spdif_stream_get, | |
1060 | .put = snd_cmipci_spdif_stream_put | |
1061 | }; | |
1062 | ||
1063 | /* | |
1064 | */ | |
1065 | ||
1066 | /* save mixer setting and mute for AC3 playback */ | |
2cbdb686 | 1067 | static int save_mixer_state(struct cmipci *cm) |
1da177e4 LT |
1068 | { |
1069 | if (! cm->mixer_insensitive) { | |
2cbdb686 | 1070 | struct snd_ctl_elem_value *val; |
1da177e4 LT |
1071 | unsigned int i; |
1072 | ||
1073 | val = kmalloc(sizeof(*val), GFP_ATOMIC); | |
1074 | if (!val) | |
1075 | return -ENOMEM; | |
1076 | for (i = 0; i < CM_SAVED_MIXERS; i++) { | |
2cbdb686 | 1077 | struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; |
1da177e4 LT |
1078 | if (ctl) { |
1079 | int event; | |
1080 | memset(val, 0, sizeof(*val)); | |
1081 | ctl->get(ctl, val); | |
1082 | cm->mixer_res_status[i] = val->value.integer.value[0]; | |
1083 | val->value.integer.value[0] = cm_saved_mixer[i].toggle_on; | |
1084 | event = SNDRV_CTL_EVENT_MASK_INFO; | |
1085 | if (cm->mixer_res_status[i] != val->value.integer.value[0]) { | |
1086 | ctl->put(ctl, val); /* toggle */ | |
1087 | event |= SNDRV_CTL_EVENT_MASK_VALUE; | |
1088 | } | |
1089 | ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
1090 | snd_ctl_notify(cm->card, event, &ctl->id); | |
1091 | } | |
1092 | } | |
1093 | kfree(val); | |
1094 | cm->mixer_insensitive = 1; | |
1095 | } | |
1096 | return 0; | |
1097 | } | |
1098 | ||
1099 | ||
1100 | /* restore the previously saved mixer status */ | |
2cbdb686 | 1101 | static void restore_mixer_state(struct cmipci *cm) |
1da177e4 LT |
1102 | { |
1103 | if (cm->mixer_insensitive) { | |
2cbdb686 | 1104 | struct snd_ctl_elem_value *val; |
1da177e4 LT |
1105 | unsigned int i; |
1106 | ||
1107 | val = kmalloc(sizeof(*val), GFP_KERNEL); | |
1108 | if (!val) | |
1109 | return; | |
1110 | cm->mixer_insensitive = 0; /* at first clear this; | |
1111 | otherwise the changes will be ignored */ | |
1112 | for (i = 0; i < CM_SAVED_MIXERS; i++) { | |
2cbdb686 | 1113 | struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; |
1da177e4 LT |
1114 | if (ctl) { |
1115 | int event; | |
1116 | ||
1117 | memset(val, 0, sizeof(*val)); | |
1118 | ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
1119 | ctl->get(ctl, val); | |
1120 | event = SNDRV_CTL_EVENT_MASK_INFO; | |
1121 | if (val->value.integer.value[0] != cm->mixer_res_status[i]) { | |
1122 | val->value.integer.value[0] = cm->mixer_res_status[i]; | |
1123 | ctl->put(ctl, val); | |
1124 | event |= SNDRV_CTL_EVENT_MASK_VALUE; | |
1125 | } | |
1126 | snd_ctl_notify(cm->card, event, &ctl->id); | |
1127 | } | |
1128 | } | |
1129 | kfree(val); | |
1130 | } | |
1131 | } | |
1132 | ||
1133 | /* spinlock held! */ | |
2cbdb686 | 1134 | static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate) |
1da177e4 LT |
1135 | { |
1136 | if (do_ac3) { | |
1137 | /* AC3EN for 037 */ | |
1138 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); | |
1139 | /* AC3EN for 039 */ | |
1140 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); | |
1141 | ||
1142 | if (cm->can_ac3_hw) { | |
1143 | /* SPD24SEL for 037, 0x02 */ | |
1144 | /* SPD24SEL for 039, 0x20, but cannot be set */ | |
1145 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); | |
1146 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1147 | } else { /* can_ac3_sw */ | |
1148 | /* SPD32SEL for 037 & 039, 0x20 */ | |
1149 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1150 | /* set 176K sample rate to fix 033 HW bug */ | |
1151 | if (cm->chip_version == 33) { | |
1152 | if (rate >= 48000) { | |
1153 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); | |
1154 | } else { | |
1155 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); | |
1156 | } | |
1157 | } | |
1158 | } | |
1159 | ||
1160 | } else { | |
1161 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); | |
1162 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); | |
1163 | ||
1164 | if (cm->can_ac3_hw) { | |
1165 | /* chip model >= 37 */ | |
1166 | if (snd_pcm_format_width(subs->runtime->format) > 16) { | |
1167 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1168 | snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); | |
1169 | } else { | |
1170 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1171 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); | |
1172 | } | |
1173 | } else { | |
1174 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); | |
1175 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); | |
1176 | snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); | |
1177 | } | |
1178 | } | |
1179 | } | |
1180 | ||
2cbdb686 | 1181 | static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3) |
1da177e4 LT |
1182 | { |
1183 | int rate, err; | |
1184 | ||
1185 | rate = subs->runtime->rate; | |
1186 | ||
1187 | if (up && do_ac3) | |
1188 | if ((err = save_mixer_state(cm)) < 0) | |
1189 | return err; | |
1190 | ||
1191 | spin_lock_irq(&cm->reg_lock); | |
1192 | cm->spdif_playback_avail = up; | |
1193 | if (up) { | |
1194 | /* they are controlled via "IEC958 Output Switch" */ | |
1195 | /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ | |
1196 | /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ | |
1197 | if (cm->spdif_playback_enabled) | |
1198 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); | |
1199 | setup_ac3(cm, subs, do_ac3, rate); | |
1200 | ||
1201 | if (rate == 48000) | |
1202 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); | |
1203 | else | |
1204 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); | |
1205 | ||
1206 | } else { | |
1207 | /* they are controlled via "IEC958 Output Switch" */ | |
1208 | /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ | |
1209 | /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ | |
1210 | snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); | |
1211 | setup_ac3(cm, subs, 0, 0); | |
1212 | } | |
1213 | spin_unlock_irq(&cm->reg_lock); | |
1214 | return 0; | |
1215 | } | |
1216 | ||
1217 | ||
1218 | /* | |
1219 | * preparation | |
1220 | */ | |
1221 | ||
1222 | /* playback - enable spdif only on the certain condition */ | |
2cbdb686 | 1223 | static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1224 | { |
2cbdb686 | 1225 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1226 | int rate = substream->runtime->rate; |
1227 | int err, do_spdif, do_ac3 = 0; | |
1228 | ||
1229 | do_spdif = ((rate == 44100 || rate == 48000) && | |
1230 | substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE && | |
1231 | substream->runtime->channels == 2); | |
1232 | if (do_spdif && cm->can_ac3_hw) | |
1233 | do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; | |
1234 | if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0) | |
1235 | return err; | |
1236 | return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); | |
1237 | } | |
1238 | ||
1239 | /* playback (via device #2) - enable spdif always */ | |
2cbdb686 | 1240 | static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1241 | { |
2cbdb686 | 1242 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1243 | int err, do_ac3; |
1244 | ||
1245 | if (cm->can_ac3_hw) | |
1246 | do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; | |
1247 | else | |
1248 | do_ac3 = 1; /* doesn't matter */ | |
1249 | if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0) | |
1250 | return err; | |
1251 | return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); | |
1252 | } | |
1253 | ||
2cbdb686 | 1254 | static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream) |
1da177e4 | 1255 | { |
2cbdb686 | 1256 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1257 | setup_spdif_playback(cm, substream, 0, 0); |
1258 | restore_mixer_state(cm); | |
1259 | return snd_cmipci_hw_free(substream); | |
1260 | } | |
1261 | ||
1262 | /* capture */ | |
2cbdb686 | 1263 | static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1264 | { |
2cbdb686 | 1265 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1266 | return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); |
1267 | } | |
1268 | ||
1269 | /* capture with spdif (via device #2) */ | |
2cbdb686 | 1270 | static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1271 | { |
2cbdb686 | 1272 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1273 | |
1274 | spin_lock_irq(&cm->reg_lock); | |
1275 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); | |
1276 | spin_unlock_irq(&cm->reg_lock); | |
1277 | ||
1278 | return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); | |
1279 | } | |
1280 | ||
2cbdb686 | 1281 | static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs) |
1da177e4 | 1282 | { |
2cbdb686 | 1283 | struct cmipci *cm = snd_pcm_substream_chip(subs); |
1da177e4 LT |
1284 | |
1285 | spin_lock_irq(&cm->reg_lock); | |
1286 | snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); | |
1287 | spin_unlock_irq(&cm->reg_lock); | |
1288 | ||
1289 | return snd_cmipci_hw_free(subs); | |
1290 | } | |
1291 | ||
1292 | ||
1293 | /* | |
1294 | * interrupt handler | |
1295 | */ | |
1296 | static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
1297 | { | |
2cbdb686 | 1298 | struct cmipci *cm = dev_id; |
1da177e4 LT |
1299 | unsigned int status, mask = 0; |
1300 | ||
1301 | /* fastpath out, to ease interrupt sharing */ | |
1302 | status = snd_cmipci_read(cm, CM_REG_INT_STATUS); | |
1303 | if (!(status & CM_INTR)) | |
1304 | return IRQ_NONE; | |
1305 | ||
1306 | /* acknowledge interrupt */ | |
1307 | spin_lock(&cm->reg_lock); | |
1308 | if (status & CM_CHINT0) | |
1309 | mask |= CM_CH0_INT_EN; | |
1310 | if (status & CM_CHINT1) | |
1311 | mask |= CM_CH1_INT_EN; | |
1312 | snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask); | |
1313 | snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask); | |
1314 | spin_unlock(&cm->reg_lock); | |
1315 | ||
1316 | if (cm->rmidi && (status & CM_UARTINT)) | |
1317 | snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data, regs); | |
1318 | ||
1319 | if (cm->pcm) { | |
1320 | if ((status & CM_CHINT0) && cm->channel[0].running) | |
1321 | snd_pcm_period_elapsed(cm->channel[0].substream); | |
1322 | if ((status & CM_CHINT1) && cm->channel[1].running) | |
1323 | snd_pcm_period_elapsed(cm->channel[1].substream); | |
1324 | } | |
1325 | return IRQ_HANDLED; | |
1326 | } | |
1327 | ||
1328 | /* | |
1329 | * h/w infos | |
1330 | */ | |
1331 | ||
1332 | /* playback on channel A */ | |
2cbdb686 | 1333 | static struct snd_pcm_hardware snd_cmipci_playback = |
1da177e4 LT |
1334 | { |
1335 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1336 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1337 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1338 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, |
1339 | .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, | |
1340 | .rate_min = 5512, | |
1341 | .rate_max = 48000, | |
1342 | .channels_min = 1, | |
1343 | .channels_max = 2, | |
1344 | .buffer_bytes_max = (128*1024), | |
1345 | .period_bytes_min = 64, | |
1346 | .period_bytes_max = (128*1024), | |
1347 | .periods_min = 2, | |
1348 | .periods_max = 1024, | |
1349 | .fifo_size = 0, | |
1350 | }; | |
1351 | ||
1352 | /* capture on channel B */ | |
2cbdb686 | 1353 | static struct snd_pcm_hardware snd_cmipci_capture = |
1da177e4 LT |
1354 | { |
1355 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1356 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1357 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1358 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, |
1359 | .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, | |
1360 | .rate_min = 5512, | |
1361 | .rate_max = 48000, | |
1362 | .channels_min = 1, | |
1363 | .channels_max = 2, | |
1364 | .buffer_bytes_max = (128*1024), | |
1365 | .period_bytes_min = 64, | |
1366 | .period_bytes_max = (128*1024), | |
1367 | .periods_min = 2, | |
1368 | .periods_max = 1024, | |
1369 | .fifo_size = 0, | |
1370 | }; | |
1371 | ||
1372 | /* playback on channel B - stereo 16bit only? */ | |
2cbdb686 | 1373 | static struct snd_pcm_hardware snd_cmipci_playback2 = |
1da177e4 LT |
1374 | { |
1375 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1376 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1377 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1378 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
1379 | .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, | |
1380 | .rate_min = 5512, | |
1381 | .rate_max = 48000, | |
1382 | .channels_min = 2, | |
1383 | .channels_max = 2, | |
1384 | .buffer_bytes_max = (128*1024), | |
1385 | .period_bytes_min = 64, | |
1386 | .period_bytes_max = (128*1024), | |
1387 | .periods_min = 2, | |
1388 | .periods_max = 1024, | |
1389 | .fifo_size = 0, | |
1390 | }; | |
1391 | ||
1392 | /* spdif playback on channel A */ | |
2cbdb686 | 1393 | static struct snd_pcm_hardware snd_cmipci_playback_spdif = |
1da177e4 LT |
1394 | { |
1395 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1396 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1397 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1398 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
1399 | .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, | |
1400 | .rate_min = 44100, | |
1401 | .rate_max = 48000, | |
1402 | .channels_min = 2, | |
1403 | .channels_max = 2, | |
1404 | .buffer_bytes_max = (128*1024), | |
1405 | .period_bytes_min = 64, | |
1406 | .period_bytes_max = (128*1024), | |
1407 | .periods_min = 2, | |
1408 | .periods_max = 1024, | |
1409 | .fifo_size = 0, | |
1410 | }; | |
1411 | ||
1412 | /* spdif playback on channel A (32bit, IEC958 subframes) */ | |
2cbdb686 | 1413 | static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe = |
1da177e4 LT |
1414 | { |
1415 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1416 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1417 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1418 | .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, |
1419 | .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, | |
1420 | .rate_min = 44100, | |
1421 | .rate_max = 48000, | |
1422 | .channels_min = 2, | |
1423 | .channels_max = 2, | |
1424 | .buffer_bytes_max = (128*1024), | |
1425 | .period_bytes_min = 64, | |
1426 | .period_bytes_max = (128*1024), | |
1427 | .periods_min = 2, | |
1428 | .periods_max = 1024, | |
1429 | .fifo_size = 0, | |
1430 | }; | |
1431 | ||
1432 | /* spdif capture on channel B */ | |
2cbdb686 | 1433 | static struct snd_pcm_hardware snd_cmipci_capture_spdif = |
1da177e4 LT |
1434 | { |
1435 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1436 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | | |
cb60e5f5 | 1437 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), |
1da177e4 LT |
1438 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
1439 | .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, | |
1440 | .rate_min = 44100, | |
1441 | .rate_max = 48000, | |
1442 | .channels_min = 2, | |
1443 | .channels_max = 2, | |
1444 | .buffer_bytes_max = (128*1024), | |
1445 | .period_bytes_min = 64, | |
1446 | .period_bytes_max = (128*1024), | |
1447 | .periods_min = 2, | |
1448 | .periods_max = 1024, | |
1449 | .fifo_size = 0, | |
1450 | }; | |
1451 | ||
1452 | /* | |
1453 | * check device open/close | |
1454 | */ | |
2cbdb686 | 1455 | static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs) |
1da177e4 LT |
1456 | { |
1457 | int ch = mode & CM_OPEN_CH_MASK; | |
1458 | ||
1459 | /* FIXME: a file should wait until the device becomes free | |
1460 | * when it's opened on blocking mode. however, since the current | |
1461 | * pcm framework doesn't pass file pointer before actually opened, | |
1462 | * we can't know whether blocking mode or not in open callback.. | |
1463 | */ | |
1464 | down(&cm->open_mutex); | |
1465 | if (cm->opened[ch]) { | |
1466 | up(&cm->open_mutex); | |
1467 | return -EBUSY; | |
1468 | } | |
1469 | cm->opened[ch] = mode; | |
1470 | cm->channel[ch].substream = subs; | |
1471 | if (! (mode & CM_OPEN_DAC)) { | |
1472 | /* disable dual DAC mode */ | |
1473 | cm->channel[ch].is_dac = 0; | |
1474 | spin_lock_irq(&cm->reg_lock); | |
1475 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); | |
1476 | spin_unlock_irq(&cm->reg_lock); | |
1477 | } | |
1478 | up(&cm->open_mutex); | |
1479 | return 0; | |
1480 | } | |
1481 | ||
2cbdb686 | 1482 | static void close_device_check(struct cmipci *cm, int mode) |
1da177e4 LT |
1483 | { |
1484 | int ch = mode & CM_OPEN_CH_MASK; | |
1485 | ||
1486 | down(&cm->open_mutex); | |
1487 | if (cm->opened[ch] == mode) { | |
1488 | if (cm->channel[ch].substream) { | |
1489 | snd_cmipci_ch_reset(cm, ch); | |
1490 | cm->channel[ch].running = 0; | |
1491 | cm->channel[ch].substream = NULL; | |
1492 | } | |
1493 | cm->opened[ch] = 0; | |
1494 | if (! cm->channel[ch].is_dac) { | |
1495 | /* enable dual DAC mode again */ | |
1496 | cm->channel[ch].is_dac = 1; | |
1497 | spin_lock_irq(&cm->reg_lock); | |
1498 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); | |
1499 | spin_unlock_irq(&cm->reg_lock); | |
1500 | } | |
1501 | } | |
1502 | up(&cm->open_mutex); | |
1503 | } | |
1504 | ||
1505 | /* | |
1506 | */ | |
1507 | ||
2cbdb686 | 1508 | static int snd_cmipci_playback_open(struct snd_pcm_substream *substream) |
1da177e4 | 1509 | { |
2cbdb686 TI |
1510 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1511 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1512 | int err; |
1513 | ||
1514 | if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0) | |
1515 | return err; | |
1516 | runtime->hw = snd_cmipci_playback; | |
1517 | runtime->hw.channels_max = cm->max_channels; | |
1518 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); | |
1519 | cm->dig_pcm_status = cm->dig_status; | |
1520 | return 0; | |
1521 | } | |
1522 | ||
2cbdb686 | 1523 | static int snd_cmipci_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 1524 | { |
2cbdb686 TI |
1525 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1526 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1527 | int err; |
1528 | ||
1529 | if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0) | |
1530 | return err; | |
1531 | runtime->hw = snd_cmipci_capture; | |
1532 | if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording | |
1533 | runtime->hw.rate_min = 41000; | |
1534 | runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000; | |
1535 | } | |
1536 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); | |
1537 | return 0; | |
1538 | } | |
1539 | ||
2cbdb686 | 1540 | static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream) |
1da177e4 | 1541 | { |
2cbdb686 TI |
1542 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1543 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1544 | int err; |
1545 | ||
1546 | if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */ | |
1547 | return err; | |
1548 | runtime->hw = snd_cmipci_playback2; | |
1549 | down(&cm->open_mutex); | |
1550 | if (! cm->opened[CM_CH_PLAY]) { | |
1551 | if (cm->can_multi_ch) { | |
1552 | runtime->hw.channels_max = cm->max_channels; | |
1553 | if (cm->max_channels == 4) | |
1554 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4); | |
1555 | else if (cm->max_channels == 6) | |
1556 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6); | |
1557 | else if (cm->max_channels == 8) | |
1558 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8); | |
1559 | } | |
1560 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); | |
1561 | } | |
1562 | up(&cm->open_mutex); | |
1563 | return 0; | |
1564 | } | |
1565 | ||
2cbdb686 | 1566 | static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream) |
1da177e4 | 1567 | { |
2cbdb686 TI |
1568 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1569 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1570 | int err; |
1571 | ||
1572 | if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */ | |
1573 | return err; | |
1574 | if (cm->can_ac3_hw) { | |
1575 | runtime->hw = snd_cmipci_playback_spdif; | |
1576 | if (cm->chip_version >= 37) | |
1577 | runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; | |
1578 | } else { | |
1579 | runtime->hw = snd_cmipci_playback_iec958_subframe; | |
1580 | } | |
1581 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); | |
1582 | cm->dig_pcm_status = cm->dig_status; | |
1583 | return 0; | |
1584 | } | |
1585 | ||
2cbdb686 | 1586 | static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream) |
1da177e4 | 1587 | { |
2cbdb686 TI |
1588 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1589 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1590 | int err; |
1591 | ||
1592 | if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */ | |
1593 | return err; | |
1594 | runtime->hw = snd_cmipci_capture_spdif; | |
1595 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); | |
1596 | return 0; | |
1597 | } | |
1598 | ||
1599 | ||
1600 | /* | |
1601 | */ | |
1602 | ||
2cbdb686 | 1603 | static int snd_cmipci_playback_close(struct snd_pcm_substream *substream) |
1da177e4 | 1604 | { |
2cbdb686 | 1605 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1606 | close_device_check(cm, CM_OPEN_PLAYBACK); |
1607 | return 0; | |
1608 | } | |
1609 | ||
2cbdb686 | 1610 | static int snd_cmipci_capture_close(struct snd_pcm_substream *substream) |
1da177e4 | 1611 | { |
2cbdb686 | 1612 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1613 | close_device_check(cm, CM_OPEN_CAPTURE); |
1614 | return 0; | |
1615 | } | |
1616 | ||
2cbdb686 | 1617 | static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream) |
1da177e4 | 1618 | { |
2cbdb686 | 1619 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1620 | close_device_check(cm, CM_OPEN_PLAYBACK2); |
1621 | close_device_check(cm, CM_OPEN_PLAYBACK_MULTI); | |
1622 | return 0; | |
1623 | } | |
1624 | ||
2cbdb686 | 1625 | static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream) |
1da177e4 | 1626 | { |
2cbdb686 | 1627 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1628 | close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK); |
1629 | return 0; | |
1630 | } | |
1631 | ||
2cbdb686 | 1632 | static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream) |
1da177e4 | 1633 | { |
2cbdb686 | 1634 | struct cmipci *cm = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1635 | close_device_check(cm, CM_OPEN_SPDIF_CAPTURE); |
1636 | return 0; | |
1637 | } | |
1638 | ||
1639 | ||
1640 | /* | |
1641 | */ | |
1642 | ||
2cbdb686 | 1643 | static struct snd_pcm_ops snd_cmipci_playback_ops = { |
1da177e4 LT |
1644 | .open = snd_cmipci_playback_open, |
1645 | .close = snd_cmipci_playback_close, | |
1646 | .ioctl = snd_pcm_lib_ioctl, | |
1647 | .hw_params = snd_cmipci_hw_params, | |
1648 | .hw_free = snd_cmipci_playback_hw_free, | |
1649 | .prepare = snd_cmipci_playback_prepare, | |
1650 | .trigger = snd_cmipci_playback_trigger, | |
1651 | .pointer = snd_cmipci_playback_pointer, | |
1652 | }; | |
1653 | ||
2cbdb686 | 1654 | static struct snd_pcm_ops snd_cmipci_capture_ops = { |
1da177e4 LT |
1655 | .open = snd_cmipci_capture_open, |
1656 | .close = snd_cmipci_capture_close, | |
1657 | .ioctl = snd_pcm_lib_ioctl, | |
1658 | .hw_params = snd_cmipci_hw_params, | |
1659 | .hw_free = snd_cmipci_hw_free, | |
1660 | .prepare = snd_cmipci_capture_prepare, | |
1661 | .trigger = snd_cmipci_capture_trigger, | |
1662 | .pointer = snd_cmipci_capture_pointer, | |
1663 | }; | |
1664 | ||
2cbdb686 | 1665 | static struct snd_pcm_ops snd_cmipci_playback2_ops = { |
1da177e4 LT |
1666 | .open = snd_cmipci_playback2_open, |
1667 | .close = snd_cmipci_playback2_close, | |
1668 | .ioctl = snd_pcm_lib_ioctl, | |
1669 | .hw_params = snd_cmipci_playback2_hw_params, | |
1670 | .hw_free = snd_cmipci_hw_free, | |
1671 | .prepare = snd_cmipci_capture_prepare, /* channel B */ | |
1672 | .trigger = snd_cmipci_capture_trigger, /* channel B */ | |
1673 | .pointer = snd_cmipci_capture_pointer, /* channel B */ | |
1674 | }; | |
1675 | ||
2cbdb686 | 1676 | static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = { |
1da177e4 LT |
1677 | .open = snd_cmipci_playback_spdif_open, |
1678 | .close = snd_cmipci_playback_spdif_close, | |
1679 | .ioctl = snd_pcm_lib_ioctl, | |
1680 | .hw_params = snd_cmipci_hw_params, | |
1681 | .hw_free = snd_cmipci_playback_hw_free, | |
1682 | .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */ | |
1683 | .trigger = snd_cmipci_playback_trigger, | |
1684 | .pointer = snd_cmipci_playback_pointer, | |
1685 | }; | |
1686 | ||
2cbdb686 | 1687 | static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = { |
1da177e4 LT |
1688 | .open = snd_cmipci_capture_spdif_open, |
1689 | .close = snd_cmipci_capture_spdif_close, | |
1690 | .ioctl = snd_pcm_lib_ioctl, | |
1691 | .hw_params = snd_cmipci_hw_params, | |
1692 | .hw_free = snd_cmipci_capture_spdif_hw_free, | |
1693 | .prepare = snd_cmipci_capture_spdif_prepare, | |
1694 | .trigger = snd_cmipci_capture_trigger, | |
1695 | .pointer = snd_cmipci_capture_pointer, | |
1696 | }; | |
1697 | ||
1698 | ||
1699 | /* | |
1700 | */ | |
1701 | ||
2cbdb686 | 1702 | static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device) |
1da177e4 | 1703 | { |
2cbdb686 | 1704 | struct snd_pcm *pcm; |
1da177e4 LT |
1705 | int err; |
1706 | ||
1707 | err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); | |
1708 | if (err < 0) | |
1709 | return err; | |
1710 | ||
1711 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops); | |
1712 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops); | |
1713 | ||
1714 | pcm->private_data = cm; | |
1da177e4 LT |
1715 | pcm->info_flags = 0; |
1716 | strcpy(pcm->name, "C-Media PCI DAC/ADC"); | |
1717 | cm->pcm = pcm; | |
1718 | ||
1719 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1720 | snd_dma_pci_data(cm->pci), 64*1024, 128*1024); | |
1721 | ||
1722 | return 0; | |
1723 | } | |
1724 | ||
2cbdb686 | 1725 | static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device) |
1da177e4 | 1726 | { |
2cbdb686 | 1727 | struct snd_pcm *pcm; |
1da177e4 LT |
1728 | int err; |
1729 | ||
1730 | err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm); | |
1731 | if (err < 0) | |
1732 | return err; | |
1733 | ||
1734 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops); | |
1735 | ||
1736 | pcm->private_data = cm; | |
1da177e4 LT |
1737 | pcm->info_flags = 0; |
1738 | strcpy(pcm->name, "C-Media PCI 2nd DAC"); | |
1739 | cm->pcm2 = pcm; | |
1740 | ||
1741 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1742 | snd_dma_pci_data(cm->pci), 64*1024, 128*1024); | |
1743 | ||
1744 | return 0; | |
1745 | } | |
1746 | ||
2cbdb686 | 1747 | static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device) |
1da177e4 | 1748 | { |
2cbdb686 | 1749 | struct snd_pcm *pcm; |
1da177e4 LT |
1750 | int err; |
1751 | ||
1752 | err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); | |
1753 | if (err < 0) | |
1754 | return err; | |
1755 | ||
1756 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops); | |
1757 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops); | |
1758 | ||
1759 | pcm->private_data = cm; | |
1da177e4 LT |
1760 | pcm->info_flags = 0; |
1761 | strcpy(pcm->name, "C-Media PCI IEC958"); | |
1762 | cm->pcm_spdif = pcm; | |
1763 | ||
1764 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1765 | snd_dma_pci_data(cm->pci), 64*1024, 128*1024); | |
1766 | ||
1767 | return 0; | |
1768 | } | |
1769 | ||
1770 | /* | |
1771 | * mixer interface: | |
1772 | * - CM8338/8738 has a compatible mixer interface with SB16, but | |
1773 | * lack of some elements like tone control, i/o gain and AGC. | |
1774 | * - Access to native registers: | |
1775 | * - A 3D switch | |
1776 | * - Output mute switches | |
1777 | */ | |
1778 | ||
2cbdb686 | 1779 | static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data) |
1da177e4 LT |
1780 | { |
1781 | outb(idx, s->iobase + CM_REG_SB16_ADDR); | |
1782 | outb(data, s->iobase + CM_REG_SB16_DATA); | |
1783 | } | |
1784 | ||
2cbdb686 | 1785 | static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx) |
1da177e4 LT |
1786 | { |
1787 | unsigned char v; | |
1788 | ||
1789 | outb(idx, s->iobase + CM_REG_SB16_ADDR); | |
1790 | v = inb(s->iobase + CM_REG_SB16_DATA); | |
1791 | return v; | |
1792 | } | |
1793 | ||
1794 | /* | |
1795 | * general mixer element | |
1796 | */ | |
2cbdb686 | 1797 | struct cmipci_sb_reg { |
1da177e4 LT |
1798 | unsigned int left_reg, right_reg; |
1799 | unsigned int left_shift, right_shift; | |
1800 | unsigned int mask; | |
1801 | unsigned int invert: 1; | |
1802 | unsigned int stereo: 1; | |
2cbdb686 | 1803 | }; |
1da177e4 LT |
1804 | |
1805 | #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \ | |
1806 | ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23)) | |
1807 | ||
1808 | #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \ | |
1809 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
1810 | .info = snd_cmipci_info_volume, \ | |
1811 | .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \ | |
1812 | .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \ | |
1813 | } | |
1814 | ||
1815 | #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1) | |
1816 | #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0) | |
1817 | #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1) | |
1818 | #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0) | |
1819 | ||
2cbdb686 | 1820 | static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val) |
1da177e4 LT |
1821 | { |
1822 | r->left_reg = val & 0xff; | |
1823 | r->right_reg = (val >> 8) & 0xff; | |
1824 | r->left_shift = (val >> 16) & 0x07; | |
1825 | r->right_shift = (val >> 19) & 0x07; | |
1826 | r->invert = (val >> 22) & 1; | |
1827 | r->stereo = (val >> 23) & 1; | |
1828 | r->mask = (val >> 24) & 0xff; | |
1829 | } | |
1830 | ||
2cbdb686 TI |
1831 | static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol, |
1832 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 | 1833 | { |
2cbdb686 | 1834 | struct cmipci_sb_reg reg; |
1da177e4 LT |
1835 | |
1836 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
1837 | uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; | |
1838 | uinfo->count = reg.stereo + 1; | |
1839 | uinfo->value.integer.min = 0; | |
1840 | uinfo->value.integer.max = reg.mask; | |
1841 | return 0; | |
1842 | } | |
1843 | ||
2cbdb686 TI |
1844 | static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol, |
1845 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1846 | { |
2cbdb686 TI |
1847 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1848 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
1849 | int val; |
1850 | ||
1851 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
1852 | spin_lock_irq(&cm->reg_lock); | |
1853 | val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask; | |
1854 | if (reg.invert) | |
1855 | val = reg.mask - val; | |
1856 | ucontrol->value.integer.value[0] = val; | |
1857 | if (reg.stereo) { | |
1858 | val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask; | |
1859 | if (reg.invert) | |
1860 | val = reg.mask - val; | |
1861 | ucontrol->value.integer.value[1] = val; | |
1862 | } | |
1863 | spin_unlock_irq(&cm->reg_lock); | |
1864 | return 0; | |
1865 | } | |
1866 | ||
2cbdb686 TI |
1867 | static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol, |
1868 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1869 | { |
2cbdb686 TI |
1870 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1871 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
1872 | int change; |
1873 | int left, right, oleft, oright; | |
1874 | ||
1875 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
1876 | left = ucontrol->value.integer.value[0] & reg.mask; | |
1877 | if (reg.invert) | |
1878 | left = reg.mask - left; | |
1879 | left <<= reg.left_shift; | |
1880 | if (reg.stereo) { | |
1881 | right = ucontrol->value.integer.value[1] & reg.mask; | |
1882 | if (reg.invert) | |
1883 | right = reg.mask - right; | |
1884 | right <<= reg.right_shift; | |
1885 | } else | |
1886 | right = 0; | |
1887 | spin_lock_irq(&cm->reg_lock); | |
1888 | oleft = snd_cmipci_mixer_read(cm, reg.left_reg); | |
1889 | left |= oleft & ~(reg.mask << reg.left_shift); | |
1890 | change = left != oleft; | |
1891 | if (reg.stereo) { | |
1892 | if (reg.left_reg != reg.right_reg) { | |
1893 | snd_cmipci_mixer_write(cm, reg.left_reg, left); | |
1894 | oright = snd_cmipci_mixer_read(cm, reg.right_reg); | |
1895 | } else | |
1896 | oright = left; | |
1897 | right |= oright & ~(reg.mask << reg.right_shift); | |
1898 | change |= right != oright; | |
1899 | snd_cmipci_mixer_write(cm, reg.right_reg, right); | |
1900 | } else | |
1901 | snd_cmipci_mixer_write(cm, reg.left_reg, left); | |
1902 | spin_unlock_irq(&cm->reg_lock); | |
1903 | return change; | |
1904 | } | |
1905 | ||
1906 | /* | |
1907 | * input route (left,right) -> (left,right) | |
1908 | */ | |
1909 | #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \ | |
1910 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
1911 | .info = snd_cmipci_info_input_sw, \ | |
1912 | .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \ | |
1913 | .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \ | |
1914 | } | |
1915 | ||
2cbdb686 TI |
1916 | static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol, |
1917 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1918 | { |
1919 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
1920 | uinfo->count = 4; | |
1921 | uinfo->value.integer.min = 0; | |
1922 | uinfo->value.integer.max = 1; | |
1923 | return 0; | |
1924 | } | |
1925 | ||
2cbdb686 TI |
1926 | static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol, |
1927 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1928 | { |
2cbdb686 TI |
1929 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1930 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
1931 | int val1, val2; |
1932 | ||
1933 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
1934 | spin_lock_irq(&cm->reg_lock); | |
1935 | val1 = snd_cmipci_mixer_read(cm, reg.left_reg); | |
1936 | val2 = snd_cmipci_mixer_read(cm, reg.right_reg); | |
1937 | spin_unlock_irq(&cm->reg_lock); | |
1938 | ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1; | |
1939 | ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1; | |
1940 | ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1; | |
1941 | ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1; | |
1942 | return 0; | |
1943 | } | |
1944 | ||
2cbdb686 TI |
1945 | static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol, |
1946 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1947 | { |
2cbdb686 TI |
1948 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1949 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
1950 | int change; |
1951 | int val1, val2, oval1, oval2; | |
1952 | ||
1953 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
1954 | spin_lock_irq(&cm->reg_lock); | |
1955 | oval1 = snd_cmipci_mixer_read(cm, reg.left_reg); | |
1956 | oval2 = snd_cmipci_mixer_read(cm, reg.right_reg); | |
1957 | val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); | |
1958 | val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); | |
1959 | val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift; | |
1960 | val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift; | |
1961 | val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift; | |
1962 | val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift; | |
1963 | change = val1 != oval1 || val2 != oval2; | |
1964 | snd_cmipci_mixer_write(cm, reg.left_reg, val1); | |
1965 | snd_cmipci_mixer_write(cm, reg.right_reg, val2); | |
1966 | spin_unlock_irq(&cm->reg_lock); | |
1967 | return change; | |
1968 | } | |
1969 | ||
1970 | /* | |
1971 | * native mixer switches/volumes | |
1972 | */ | |
1973 | ||
1974 | #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \ | |
1975 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
1976 | .info = snd_cmipci_info_native_mixer, \ | |
1977 | .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ | |
1978 | .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \ | |
1979 | } | |
1980 | ||
1981 | #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \ | |
1982 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
1983 | .info = snd_cmipci_info_native_mixer, \ | |
1984 | .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ | |
1985 | .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \ | |
1986 | } | |
1987 | ||
1988 | #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \ | |
1989 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
1990 | .info = snd_cmipci_info_native_mixer, \ | |
1991 | .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ | |
1992 | .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \ | |
1993 | } | |
1994 | ||
1995 | #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \ | |
1996 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
1997 | .info = snd_cmipci_info_native_mixer, \ | |
1998 | .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ | |
1999 | .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \ | |
2000 | } | |
2001 | ||
2cbdb686 TI |
2002 | static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol, |
2003 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 | 2004 | { |
2cbdb686 | 2005 | struct cmipci_sb_reg reg; |
1da177e4 LT |
2006 | |
2007 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
2008 | uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; | |
2009 | uinfo->count = reg.stereo + 1; | |
2010 | uinfo->value.integer.min = 0; | |
2011 | uinfo->value.integer.max = reg.mask; | |
2012 | return 0; | |
2013 | ||
2014 | } | |
2015 | ||
2cbdb686 TI |
2016 | static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol, |
2017 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2018 | { |
2cbdb686 TI |
2019 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
2020 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
2021 | unsigned char oreg, val; |
2022 | ||
2023 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
2024 | spin_lock_irq(&cm->reg_lock); | |
2025 | oreg = inb(cm->iobase + reg.left_reg); | |
2026 | val = (oreg >> reg.left_shift) & reg.mask; | |
2027 | if (reg.invert) | |
2028 | val = reg.mask - val; | |
2029 | ucontrol->value.integer.value[0] = val; | |
2030 | if (reg.stereo) { | |
2031 | val = (oreg >> reg.right_shift) & reg.mask; | |
2032 | if (reg.invert) | |
2033 | val = reg.mask - val; | |
2034 | ucontrol->value.integer.value[1] = val; | |
2035 | } | |
2036 | spin_unlock_irq(&cm->reg_lock); | |
2037 | return 0; | |
2038 | } | |
2039 | ||
2cbdb686 TI |
2040 | static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol, |
2041 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2042 | { |
2cbdb686 TI |
2043 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
2044 | struct cmipci_sb_reg reg; | |
1da177e4 LT |
2045 | unsigned char oreg, nreg, val; |
2046 | ||
2047 | cmipci_sb_reg_decode(®, kcontrol->private_value); | |
2048 | spin_lock_irq(&cm->reg_lock); | |
2049 | oreg = inb(cm->iobase + reg.left_reg); | |
2050 | val = ucontrol->value.integer.value[0] & reg.mask; | |
2051 | if (reg.invert) | |
2052 | val = reg.mask - val; | |
2053 | nreg = oreg & ~(reg.mask << reg.left_shift); | |
2054 | nreg |= (val << reg.left_shift); | |
2055 | if (reg.stereo) { | |
2056 | val = ucontrol->value.integer.value[1] & reg.mask; | |
2057 | if (reg.invert) | |
2058 | val = reg.mask - val; | |
2059 | nreg &= ~(reg.mask << reg.right_shift); | |
2060 | nreg |= (val << reg.right_shift); | |
2061 | } | |
2062 | outb(nreg, cm->iobase + reg.left_reg); | |
2063 | spin_unlock_irq(&cm->reg_lock); | |
2064 | return (nreg != oreg); | |
2065 | } | |
2066 | ||
2067 | /* | |
2068 | * special case - check mixer sensitivity | |
2069 | */ | |
2cbdb686 TI |
2070 | static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol, |
2071 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2072 | { |
2cbdb686 | 2073 | //struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2074 | return snd_cmipci_get_native_mixer(kcontrol, ucontrol); |
2075 | } | |
2076 | ||
2cbdb686 TI |
2077 | static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol, |
2078 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2079 | { |
2cbdb686 | 2080 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2081 | if (cm->mixer_insensitive) { |
2082 | /* ignored */ | |
2083 | return 0; | |
2084 | } | |
2085 | return snd_cmipci_put_native_mixer(kcontrol, ucontrol); | |
2086 | } | |
2087 | ||
2088 | ||
2cbdb686 | 2089 | static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = { |
1da177e4 LT |
2090 | CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31), |
2091 | CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0), | |
2092 | CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31), | |
2093 | //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1), | |
2094 | { /* switch with sensitivity */ | |
2095 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2096 | .name = "PCM Playback Switch", | |
2097 | .info = snd_cmipci_info_native_mixer, | |
2098 | .get = snd_cmipci_get_native_mixer_sensitive, | |
2099 | .put = snd_cmipci_put_native_mixer_sensitive, | |
2100 | .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0), | |
2101 | }, | |
2102 | CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0), | |
2103 | CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31), | |
2104 | CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1), | |
2105 | CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5), | |
2106 | CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31), | |
2107 | CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1), | |
2108 | CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1), | |
2109 | CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31), | |
2110 | CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3), | |
2111 | CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3), | |
2112 | CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31), | |
2113 | CMIPCI_SB_SW_MONO("Mic Playback Switch", 0), | |
2114 | CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0), | |
2115 | CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3), | |
2116 | CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15), | |
2117 | CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0), | |
2118 | CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0), | |
2eff7ec8 | 2119 | CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1), |
1da177e4 | 2120 | CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7), |
2eff7ec8 TI |
2121 | CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7), |
2122 | CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0), | |
2123 | CMIPCI_DOUBLE("PC Speaker Playnack Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0), | |
2124 | CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0), | |
1da177e4 LT |
2125 | }; |
2126 | ||
2127 | /* | |
2128 | * other switches | |
2129 | */ | |
2130 | ||
2cbdb686 | 2131 | struct cmipci_switch_args { |
1da177e4 LT |
2132 | int reg; /* register index */ |
2133 | unsigned int mask; /* mask bits */ | |
2134 | unsigned int mask_on; /* mask bits to turn on */ | |
2135 | unsigned int is_byte: 1; /* byte access? */ | |
2cbdb686 TI |
2136 | unsigned int ac3_sensitive: 1; /* access forbidden during |
2137 | * non-audio operation? | |
2138 | */ | |
2139 | }; | |
1da177e4 | 2140 | |
2cbdb686 TI |
2141 | static int snd_cmipci_uswitch_info(struct snd_kcontrol *kcontrol, |
2142 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
2143 | { |
2144 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
2145 | uinfo->count = 1; | |
2146 | uinfo->value.integer.min = 0; | |
2147 | uinfo->value.integer.max = 1; | |
2148 | return 0; | |
2149 | } | |
2150 | ||
2cbdb686 TI |
2151 | static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, |
2152 | struct snd_ctl_elem_value *ucontrol, | |
2153 | struct cmipci_switch_args *args) | |
1da177e4 LT |
2154 | { |
2155 | unsigned int val; | |
2cbdb686 | 2156 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2157 | |
2158 | spin_lock_irq(&cm->reg_lock); | |
2159 | if (args->ac3_sensitive && cm->mixer_insensitive) { | |
2160 | ucontrol->value.integer.value[0] = 0; | |
2161 | spin_unlock_irq(&cm->reg_lock); | |
2162 | return 0; | |
2163 | } | |
2164 | if (args->is_byte) | |
2165 | val = inb(cm->iobase + args->reg); | |
2166 | else | |
2167 | val = snd_cmipci_read(cm, args->reg); | |
2168 | ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0; | |
2169 | spin_unlock_irq(&cm->reg_lock); | |
2170 | return 0; | |
2171 | } | |
2172 | ||
2cbdb686 TI |
2173 | static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, |
2174 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2175 | { |
2cbdb686 TI |
2176 | struct cmipci_switch_args *args; |
2177 | args = (struct cmipci_switch_args *)kcontrol->private_value; | |
1da177e4 LT |
2178 | snd_assert(args != NULL, return -EINVAL); |
2179 | return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args); | |
2180 | } | |
2181 | ||
2cbdb686 TI |
2182 | static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol, |
2183 | struct snd_ctl_elem_value *ucontrol, | |
2184 | struct cmipci_switch_args *args) | |
1da177e4 LT |
2185 | { |
2186 | unsigned int val; | |
2187 | int change; | |
2cbdb686 | 2188 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2189 | |
2190 | spin_lock_irq(&cm->reg_lock); | |
2191 | if (args->ac3_sensitive && cm->mixer_insensitive) { | |
2192 | /* ignored */ | |
2193 | spin_unlock_irq(&cm->reg_lock); | |
2194 | return 0; | |
2195 | } | |
2196 | if (args->is_byte) | |
2197 | val = inb(cm->iobase + args->reg); | |
2198 | else | |
2199 | val = snd_cmipci_read(cm, args->reg); | |
2200 | change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask : 0); | |
2201 | if (change) { | |
2202 | val &= ~args->mask; | |
2203 | if (ucontrol->value.integer.value[0]) | |
2204 | val |= args->mask_on; | |
2205 | else | |
2206 | val |= (args->mask & ~args->mask_on); | |
2207 | if (args->is_byte) | |
2208 | outb((unsigned char)val, cm->iobase + args->reg); | |
2209 | else | |
2210 | snd_cmipci_write(cm, args->reg, val); | |
2211 | } | |
2212 | spin_unlock_irq(&cm->reg_lock); | |
2213 | return change; | |
2214 | } | |
2215 | ||
2cbdb686 TI |
2216 | static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol, |
2217 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2218 | { |
2cbdb686 TI |
2219 | struct cmipci_switch_args *args; |
2220 | args = (struct cmipci_switch_args *)kcontrol->private_value; | |
1da177e4 LT |
2221 | snd_assert(args != NULL, return -EINVAL); |
2222 | return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args); | |
2223 | } | |
2224 | ||
2225 | #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \ | |
2cbdb686 | 2226 | static struct cmipci_switch_args cmipci_switch_arg_##sname = { \ |
1da177e4 LT |
2227 | .reg = xreg, \ |
2228 | .mask = xmask, \ | |
2229 | .mask_on = xmask_on, \ | |
2230 | .is_byte = xis_byte, \ | |
2231 | .ac3_sensitive = xac3, \ | |
2232 | } | |
2233 | ||
2234 | #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \ | |
2235 | DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3) | |
2236 | ||
2237 | #if 0 /* these will be controlled in pcm device */ | |
2238 | DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0); | |
2239 | DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0); | |
2240 | #endif | |
2241 | DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0); | |
2242 | DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0); | |
2243 | DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0); | |
2244 | DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1); | |
2245 | DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0); | |
2246 | DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0); | |
2247 | DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1); | |
2248 | DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */ | |
2249 | // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1); | |
2250 | DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1); | |
2251 | DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0); | |
2252 | /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */ | |
2253 | DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0); | |
2254 | DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0); | |
2255 | #if CM_CH_PLAY == 1 | |
2256 | DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */ | |
2257 | #else | |
2258 | DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0); | |
2259 | #endif | |
2260 | DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0); | |
01d25d46 TI |
2261 | // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0); |
2262 | // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0); | |
1da177e4 LT |
2263 | // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */ |
2264 | DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0); | |
2265 | ||
2266 | #define DEFINE_SWITCH(sname, stype, sarg) \ | |
2267 | { .name = sname, \ | |
2268 | .iface = stype, \ | |
2269 | .info = snd_cmipci_uswitch_info, \ | |
2270 | .get = snd_cmipci_uswitch_get, \ | |
2271 | .put = snd_cmipci_uswitch_put, \ | |
2272 | .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\ | |
2273 | } | |
2274 | ||
2275 | #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg) | |
2276 | #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg) | |
2277 | ||
2278 | ||
2279 | /* | |
2280 | * callbacks for spdif output switch | |
2281 | * needs toggle two registers.. | |
2282 | */ | |
2cbdb686 TI |
2283 | static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol, |
2284 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 LT |
2285 | { |
2286 | int changed; | |
2287 | changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); | |
2288 | changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); | |
2289 | return changed; | |
2290 | } | |
2291 | ||
2cbdb686 TI |
2292 | static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol, |
2293 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 2294 | { |
2cbdb686 | 2295 | struct cmipci *chip = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2296 | int changed; |
2297 | changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); | |
2298 | changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); | |
2299 | if (changed) { | |
2300 | if (ucontrol->value.integer.value[0]) { | |
2301 | if (chip->spdif_playback_avail) | |
2302 | snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); | |
2303 | } else { | |
2304 | if (chip->spdif_playback_avail) | |
2305 | snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); | |
2306 | } | |
2307 | } | |
2308 | chip->spdif_playback_enabled = ucontrol->value.integer.value[0]; | |
2309 | return changed; | |
2310 | } | |
2311 | ||
2312 | ||
2cbdb686 TI |
2313 | static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol, |
2314 | struct snd_ctl_elem_info *uinfo) | |
01d25d46 | 2315 | { |
2cbdb686 | 2316 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
01d25d46 TI |
2317 | static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" }; |
2318 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2319 | uinfo->count = 1; | |
2320 | uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2; | |
2321 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2322 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2323 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2324 | return 0; | |
2325 | } | |
2326 | ||
2cbdb686 | 2327 | static inline unsigned int get_line_in_mode(struct cmipci *cm) |
01d25d46 TI |
2328 | { |
2329 | unsigned int val; | |
2330 | if (cm->chip_version >= 39) { | |
2331 | val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL); | |
2332 | if (val & CM_LINE_AS_BASS) | |
2333 | return 2; | |
2334 | } | |
2335 | val = snd_cmipci_read_b(cm, CM_REG_MIXER1); | |
2336 | if (val & CM_SPK4) | |
2337 | return 1; | |
2338 | return 0; | |
2339 | } | |
2340 | ||
2cbdb686 TI |
2341 | static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol, |
2342 | struct snd_ctl_elem_value *ucontrol) | |
01d25d46 | 2343 | { |
2cbdb686 | 2344 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
01d25d46 TI |
2345 | |
2346 | spin_lock_irq(&cm->reg_lock); | |
2347 | ucontrol->value.enumerated.item[0] = get_line_in_mode(cm); | |
2348 | spin_unlock_irq(&cm->reg_lock); | |
2349 | return 0; | |
2350 | } | |
2351 | ||
2cbdb686 TI |
2352 | static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol, |
2353 | struct snd_ctl_elem_value *ucontrol) | |
01d25d46 | 2354 | { |
2cbdb686 | 2355 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
01d25d46 TI |
2356 | int change; |
2357 | ||
2358 | spin_lock_irq(&cm->reg_lock); | |
2359 | if (ucontrol->value.enumerated.item[0] == 2) | |
2360 | change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS); | |
2361 | else | |
2362 | change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS); | |
2363 | if (ucontrol->value.enumerated.item[0] == 1) | |
2364 | change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4); | |
2365 | else | |
2366 | change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4); | |
2367 | spin_unlock_irq(&cm->reg_lock); | |
2368 | return change; | |
2369 | } | |
2370 | ||
2cbdb686 TI |
2371 | static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol, |
2372 | struct snd_ctl_elem_info *uinfo) | |
01d25d46 TI |
2373 | { |
2374 | static char *texts[2] = { "Mic-In", "Center/LFE Output" }; | |
2375 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2376 | uinfo->count = 1; | |
2377 | uinfo->value.enumerated.items = 2; | |
2378 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2379 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; | |
2380 | strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); | |
2381 | return 0; | |
2382 | } | |
2383 | ||
2cbdb686 TI |
2384 | static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol, |
2385 | struct snd_ctl_elem_value *ucontrol) | |
01d25d46 | 2386 | { |
2cbdb686 | 2387 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
01d25d46 TI |
2388 | /* same bit as spdi_phase */ |
2389 | spin_lock_irq(&cm->reg_lock); | |
2390 | ucontrol->value.enumerated.item[0] = | |
2391 | (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0; | |
2392 | spin_unlock_irq(&cm->reg_lock); | |
2393 | return 0; | |
2394 | } | |
2395 | ||
2cbdb686 TI |
2396 | static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol, |
2397 | struct snd_ctl_elem_value *ucontrol) | |
01d25d46 | 2398 | { |
2cbdb686 | 2399 | struct cmipci *cm = snd_kcontrol_chip(kcontrol); |
01d25d46 TI |
2400 | int change; |
2401 | ||
2402 | spin_lock_irq(&cm->reg_lock); | |
2403 | if (ucontrol->value.enumerated.item[0]) | |
2404 | change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); | |
2405 | else | |
2406 | change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); | |
2407 | spin_unlock_irq(&cm->reg_lock); | |
2408 | return change; | |
2409 | } | |
2410 | ||
1da177e4 | 2411 | /* both for CM8338/8738 */ |
2cbdb686 | 2412 | static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = { |
1da177e4 | 2413 | DEFINE_MIXER_SWITCH("Four Channel Mode", fourch), |
01d25d46 TI |
2414 | { |
2415 | .name = "Line-In Mode", | |
2416 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2417 | .info = snd_cmipci_line_in_mode_info, | |
2418 | .get = snd_cmipci_line_in_mode_get, | |
2419 | .put = snd_cmipci_line_in_mode_put, | |
2420 | }, | |
1da177e4 LT |
2421 | }; |
2422 | ||
2423 | /* for non-multichannel chips */ | |
2cbdb686 | 2424 | static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata = |
1da177e4 LT |
2425 | DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac); |
2426 | ||
2427 | /* only for CM8738 */ | |
2cbdb686 | 2428 | static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = { |
1da177e4 LT |
2429 | #if 0 /* controlled in pcm device */ |
2430 | DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in), | |
2431 | DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out), | |
2432 | DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac), | |
2433 | #endif | |
2434 | // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable), | |
2435 | { .name = "IEC958 Output Switch", | |
2436 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2437 | .info = snd_cmipci_uswitch_info, | |
2438 | .get = snd_cmipci_spdout_enable_get, | |
2439 | .put = snd_cmipci_spdout_enable_put, | |
2440 | }, | |
2441 | DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid), | |
2442 | DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright), | |
2443 | DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v), | |
2444 | // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k), | |
2445 | DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop), | |
2446 | DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor), | |
2447 | }; | |
2448 | ||
2449 | /* only for model 033/037 */ | |
2cbdb686 | 2450 | static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = { |
1da177e4 LT |
2451 | DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out), |
2452 | DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase), | |
2453 | DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1), | |
2454 | }; | |
2455 | ||
2456 | /* only for model 039 or later */ | |
2cbdb686 | 2457 | static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = { |
1da177e4 LT |
2458 | DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2), |
2459 | DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2), | |
01d25d46 TI |
2460 | { |
2461 | .name = "Mic-In Mode", | |
2462 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2463 | .info = snd_cmipci_mic_in_mode_info, | |
2464 | .get = snd_cmipci_mic_in_mode_get, | |
2465 | .put = snd_cmipci_mic_in_mode_put, | |
2466 | } | |
1da177e4 LT |
2467 | }; |
2468 | ||
2469 | /* card control switches */ | |
2cbdb686 | 2470 | static struct snd_kcontrol_new snd_cmipci_control_switches[] __devinitdata = { |
1da177e4 LT |
2471 | // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */ |
2472 | DEFINE_CARD_SWITCH("Modem", modem), | |
2473 | }; | |
2474 | ||
2475 | ||
2cbdb686 | 2476 | static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device) |
1da177e4 | 2477 | { |
2cbdb686 TI |
2478 | struct snd_card *card; |
2479 | struct snd_kcontrol_new *sw; | |
2480 | struct snd_kcontrol *kctl; | |
1da177e4 LT |
2481 | unsigned int idx; |
2482 | int err; | |
2483 | ||
2484 | snd_assert(cm != NULL && cm->card != NULL, return -EINVAL); | |
2485 | ||
2486 | card = cm->card; | |
2487 | ||
2488 | strcpy(card->mixername, "CMedia PCI"); | |
2489 | ||
2490 | spin_lock_irq(&cm->reg_lock); | |
2491 | snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */ | |
2492 | spin_unlock_irq(&cm->reg_lock); | |
2493 | ||
2494 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) { | |
2495 | if (cm->chip_version == 68) { // 8768 has no PCM volume | |
2496 | if (!strcmp(snd_cmipci_mixers[idx].name, | |
2497 | "PCM Playback Volume")) | |
2498 | continue; | |
2499 | } | |
2500 | if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0) | |
2501 | return err; | |
2502 | } | |
2503 | ||
2504 | /* mixer switches */ | |
2505 | sw = snd_cmipci_mixer_switches; | |
2506 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) { | |
2507 | err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); | |
2508 | if (err < 0) | |
2509 | return err; | |
2510 | } | |
2511 | if (! cm->can_multi_ch) { | |
2512 | err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm)); | |
2513 | if (err < 0) | |
2514 | return err; | |
2515 | } | |
2516 | if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 || | |
2517 | cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) { | |
2518 | sw = snd_cmipci_8738_mixer_switches; | |
2519 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) { | |
2520 | err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); | |
2521 | if (err < 0) | |
2522 | return err; | |
2523 | } | |
2524 | if (cm->can_ac3_hw) { | |
2525 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0) | |
2526 | return err; | |
2527 | kctl->id.device = pcm_spdif_device; | |
2528 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0) | |
2529 | return err; | |
2530 | kctl->id.device = pcm_spdif_device; | |
2531 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0) | |
2532 | return err; | |
2533 | kctl->id.device = pcm_spdif_device; | |
2534 | } | |
2535 | if (cm->chip_version <= 37) { | |
2536 | sw = snd_cmipci_old_mixer_switches; | |
2537 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) { | |
2538 | err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); | |
2539 | if (err < 0) | |
2540 | return err; | |
2541 | } | |
2542 | } | |
2543 | } | |
2544 | if (cm->chip_version >= 39) { | |
2545 | sw = snd_cmipci_extra_mixer_switches; | |
2546 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) { | |
2547 | err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); | |
2548 | if (err < 0) | |
2549 | return err; | |
2550 | } | |
2551 | } | |
2552 | ||
2553 | /* card switches */ | |
2554 | sw = snd_cmipci_control_switches; | |
2555 | for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) { | |
2556 | err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); | |
2557 | if (err < 0) | |
2558 | return err; | |
2559 | } | |
2560 | ||
2561 | for (idx = 0; idx < CM_SAVED_MIXERS; idx++) { | |
2cbdb686 TI |
2562 | struct snd_ctl_elem_id id; |
2563 | struct snd_kcontrol *ctl; | |
1da177e4 LT |
2564 | memset(&id, 0, sizeof(id)); |
2565 | id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; | |
2566 | strcpy(id.name, cm_saved_mixer[idx].name); | |
2567 | if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL) | |
2568 | cm->mixer_res_ctl[idx] = ctl; | |
2569 | } | |
2570 | ||
2571 | return 0; | |
2572 | } | |
2573 | ||
2574 | ||
2575 | /* | |
2576 | * proc interface | |
2577 | */ | |
2578 | ||
2579 | #ifdef CONFIG_PROC_FS | |
2cbdb686 TI |
2580 | static void snd_cmipci_proc_read(struct snd_info_entry *entry, |
2581 | struct snd_info_buffer *buffer) | |
1da177e4 | 2582 | { |
2cbdb686 | 2583 | struct cmipci *cm = entry->private_data; |
1da177e4 LT |
2584 | int i; |
2585 | ||
2586 | snd_iprintf(buffer, "%s\n\n", cm->card->longname); | |
2587 | for (i = 0; i < 0x40; i++) { | |
2588 | int v = inb(cm->iobase + i); | |
2589 | if (i % 4 == 0) | |
2590 | snd_iprintf(buffer, "%02x: ", i); | |
2591 | snd_iprintf(buffer, "%02x", v); | |
2592 | if (i % 4 == 3) | |
2593 | snd_iprintf(buffer, "\n"); | |
2594 | else | |
2595 | snd_iprintf(buffer, " "); | |
2596 | } | |
2597 | } | |
2598 | ||
2cbdb686 | 2599 | static void __devinit snd_cmipci_proc_init(struct cmipci *cm) |
1da177e4 | 2600 | { |
2cbdb686 | 2601 | struct snd_info_entry *entry; |
1da177e4 LT |
2602 | |
2603 | if (! snd_card_proc_new(cm->card, "cmipci", &entry)) | |
2604 | snd_info_set_text_ops(entry, cm, 1024, snd_cmipci_proc_read); | |
2605 | } | |
2606 | #else /* !CONFIG_PROC_FS */ | |
2cbdb686 | 2607 | static inline void snd_cmipci_proc_init(struct cmipci *cm) {} |
1da177e4 LT |
2608 | #endif |
2609 | ||
2610 | ||
2611 | static struct pci_device_id snd_cmipci_ids[] = { | |
2612 | {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
2613 | {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
2614 | {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
2615 | {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
2616 | {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
2617 | {0,}, | |
2618 | }; | |
2619 | ||
2620 | ||
2621 | /* | |
2622 | * check chip version and capabilities | |
2623 | * driver name is modified according to the chip model | |
2624 | */ | |
2cbdb686 | 2625 | static void __devinit query_chip(struct cmipci *cm) |
1da177e4 LT |
2626 | { |
2627 | unsigned int detect; | |
2628 | ||
2629 | /* check reg 0Ch, bit 24-31 */ | |
2630 | detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2; | |
2631 | if (! detect) { | |
2632 | /* check reg 08h, bit 24-28 */ | |
2633 | detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1; | |
2634 | if (! detect) { | |
2635 | cm->chip_version = 33; | |
2636 | cm->max_channels = 2; | |
2637 | if (cm->do_soft_ac3) | |
2638 | cm->can_ac3_sw = 1; | |
2639 | else | |
2640 | cm->can_ac3_hw = 1; | |
2641 | cm->has_dual_dac = 1; | |
2642 | } else { | |
2643 | cm->chip_version = 37; | |
2644 | cm->max_channels = 2; | |
2645 | cm->can_ac3_hw = 1; | |
2646 | cm->has_dual_dac = 1; | |
2647 | } | |
2648 | } else { | |
2649 | /* check reg 0Ch, bit 26 */ | |
2650 | if (detect & CM_CHIP_8768) { | |
2651 | cm->chip_version = 68; | |
2652 | cm->max_channels = 8; | |
2653 | cm->can_ac3_hw = 1; | |
2654 | cm->has_dual_dac = 1; | |
2655 | cm->can_multi_ch = 1; | |
2656 | } else if (detect & CM_CHIP_055) { | |
2657 | cm->chip_version = 55; | |
2658 | cm->max_channels = 6; | |
2659 | cm->can_ac3_hw = 1; | |
2660 | cm->has_dual_dac = 1; | |
2661 | cm->can_multi_ch = 1; | |
2662 | } else if (detect & CM_CHIP_039) { | |
2663 | cm->chip_version = 39; | |
2664 | if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */ | |
2665 | cm->max_channels = 6; | |
2666 | else | |
2667 | cm->max_channels = 4; | |
2668 | cm->can_ac3_hw = 1; | |
2669 | cm->has_dual_dac = 1; | |
2670 | cm->can_multi_ch = 1; | |
2671 | } else { | |
2672 | printk(KERN_ERR "chip %x version not supported\n", detect); | |
2673 | } | |
2674 | } | |
2675 | } | |
2676 | ||
2677 | #ifdef SUPPORT_JOYSTICK | |
2cbdb686 | 2678 | static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev) |
1da177e4 LT |
2679 | { |
2680 | static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */ | |
2681 | struct gameport *gp; | |
2682 | struct resource *r = NULL; | |
2683 | int i, io_port = 0; | |
2684 | ||
2685 | if (joystick_port[dev] == 0) | |
2686 | return -ENODEV; | |
2687 | ||
2688 | if (joystick_port[dev] == 1) { /* auto-detect */ | |
2689 | for (i = 0; ports[i]; i++) { | |
2690 | io_port = ports[i]; | |
2691 | r = request_region(io_port, 1, "CMIPCI gameport"); | |
2692 | if (r) | |
2693 | break; | |
2694 | } | |
2695 | } else { | |
2696 | io_port = joystick_port[dev]; | |
2697 | r = request_region(io_port, 1, "CMIPCI gameport"); | |
2698 | } | |
2699 | ||
2700 | if (!r) { | |
2701 | printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n"); | |
2702 | return -EBUSY; | |
2703 | } | |
2704 | ||
2705 | cm->gameport = gp = gameport_allocate_port(); | |
2706 | if (!gp) { | |
2707 | printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n"); | |
b1d5776d | 2708 | release_and_free_resource(r); |
1da177e4 LT |
2709 | return -ENOMEM; |
2710 | } | |
2711 | gameport_set_name(gp, "C-Media Gameport"); | |
2712 | gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci)); | |
2713 | gameport_set_dev_parent(gp, &cm->pci->dev); | |
2714 | gp->io = io_port; | |
2715 | gameport_set_port_data(gp, r); | |
2716 | ||
2717 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); | |
2718 | ||
2719 | gameport_register_port(cm->gameport); | |
2720 | ||
2721 | return 0; | |
2722 | } | |
2723 | ||
2cbdb686 | 2724 | static void snd_cmipci_free_gameport(struct cmipci *cm) |
1da177e4 LT |
2725 | { |
2726 | if (cm->gameport) { | |
2727 | struct resource *r = gameport_get_port_data(cm->gameport); | |
2728 | ||
2729 | gameport_unregister_port(cm->gameport); | |
2730 | cm->gameport = NULL; | |
2731 | ||
2732 | snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); | |
b1d5776d | 2733 | release_and_free_resource(r); |
1da177e4 LT |
2734 | } |
2735 | } | |
2736 | #else | |
2cbdb686 TI |
2737 | static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; } |
2738 | static inline void snd_cmipci_free_gameport(struct cmipci *cm) { } | |
1da177e4 LT |
2739 | #endif |
2740 | ||
2cbdb686 | 2741 | static int snd_cmipci_free(struct cmipci *cm) |
1da177e4 LT |
2742 | { |
2743 | if (cm->irq >= 0) { | |
2744 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); | |
2745 | snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); | |
2746 | snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ | |
2747 | snd_cmipci_ch_reset(cm, CM_CH_PLAY); | |
2748 | snd_cmipci_ch_reset(cm, CM_CH_CAPT); | |
2749 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ | |
2750 | snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); | |
2751 | ||
2752 | /* reset mixer */ | |
2753 | snd_cmipci_mixer_write(cm, 0, 0); | |
2754 | ||
2755 | synchronize_irq(cm->irq); | |
2756 | ||
2cbdb686 | 2757 | free_irq(cm->irq, cm); |
1da177e4 LT |
2758 | } |
2759 | ||
2760 | snd_cmipci_free_gameport(cm); | |
2761 | pci_release_regions(cm->pci); | |
2762 | pci_disable_device(cm->pci); | |
2763 | kfree(cm); | |
2764 | return 0; | |
2765 | } | |
2766 | ||
2cbdb686 | 2767 | static int snd_cmipci_dev_free(struct snd_device *device) |
1da177e4 | 2768 | { |
2cbdb686 | 2769 | struct cmipci *cm = device->device_data; |
1da177e4 LT |
2770 | return snd_cmipci_free(cm); |
2771 | } | |
2772 | ||
2cbdb686 | 2773 | static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port) |
5747e540 CL |
2774 | { |
2775 | long iosynth; | |
2776 | unsigned int val; | |
2cbdb686 | 2777 | struct snd_opl3 *opl3; |
5747e540 CL |
2778 | int err; |
2779 | ||
2780 | /* first try FM regs in PCI port range */ | |
2781 | iosynth = cm->iobase + CM_REG_FM_PCI; | |
2782 | err = snd_opl3_create(cm->card, iosynth, iosynth + 2, | |
2783 | OPL3_HW_OPL3, 1, &opl3); | |
2784 | if (err < 0) { | |
2785 | /* then try legacy ports */ | |
2786 | val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK; | |
2787 | iosynth = fm_port; | |
2788 | switch (iosynth) { | |
2789 | case 0x3E8: val |= CM_FMSEL_3E8; break; | |
2790 | case 0x3E0: val |= CM_FMSEL_3E0; break; | |
2791 | case 0x3C8: val |= CM_FMSEL_3C8; break; | |
2792 | case 0x388: val |= CM_FMSEL_388; break; | |
2793 | default: | |
2794 | return 0; | |
2795 | } | |
2796 | snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); | |
2797 | /* enable FM */ | |
2798 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); | |
2799 | ||
2800 | if (snd_opl3_create(cm->card, iosynth, iosynth + 2, | |
2801 | OPL3_HW_OPL3, 0, &opl3) < 0) { | |
2802 | printk(KERN_ERR "cmipci: no OPL device at %#lx, " | |
2803 | "skipping...\n", iosynth); | |
2804 | /* disable FM */ | |
2805 | snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, | |
2806 | val & ~CM_FMSEL_MASK); | |
2807 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); | |
2808 | return 0; | |
2809 | } | |
2810 | } | |
2811 | if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) { | |
2812 | printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n"); | |
2813 | return err; | |
2814 | } | |
2815 | return 0; | |
2816 | } | |
2817 | ||
2cbdb686 TI |
2818 | static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci, |
2819 | int dev, struct cmipci **rcmipci) | |
1da177e4 | 2820 | { |
2cbdb686 | 2821 | struct cmipci *cm; |
1da177e4 | 2822 | int err; |
2cbdb686 | 2823 | static struct snd_device_ops ops = { |
1da177e4 LT |
2824 | .dev_free = snd_cmipci_dev_free, |
2825 | }; | |
2826 | unsigned int val = 0; | |
5747e540 CL |
2827 | long iomidi; |
2828 | int integrated_midi; | |
1da177e4 LT |
2829 | int pcm_index, pcm_spdif_index; |
2830 | static struct pci_device_id intel_82437vx[] = { | |
2831 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) }, | |
2832 | { }, | |
2833 | }; | |
2834 | ||
2835 | *rcmipci = NULL; | |
2836 | ||
2837 | if ((err = pci_enable_device(pci)) < 0) | |
2838 | return err; | |
2839 | ||
e560d8d8 | 2840 | cm = kzalloc(sizeof(*cm), GFP_KERNEL); |
1da177e4 LT |
2841 | if (cm == NULL) { |
2842 | pci_disable_device(pci); | |
2843 | return -ENOMEM; | |
2844 | } | |
2845 | ||
2846 | spin_lock_init(&cm->reg_lock); | |
2847 | init_MUTEX(&cm->open_mutex); | |
2848 | cm->device = pci->device; | |
2849 | cm->card = card; | |
2850 | cm->pci = pci; | |
2851 | cm->irq = -1; | |
2852 | cm->channel[0].ch = 0; | |
2853 | cm->channel[1].ch = 1; | |
2854 | cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */ | |
2855 | ||
2856 | if ((err = pci_request_regions(pci, card->driver)) < 0) { | |
2857 | kfree(cm); | |
2858 | pci_disable_device(pci); | |
2859 | return err; | |
2860 | } | |
2861 | cm->iobase = pci_resource_start(pci, 0); | |
2862 | ||
2cbdb686 TI |
2863 | if (request_irq(pci->irq, snd_cmipci_interrupt, |
2864 | SA_INTERRUPT|SA_SHIRQ, card->driver, cm)) { | |
99b359ba | 2865 | snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); |
1da177e4 LT |
2866 | snd_cmipci_free(cm); |
2867 | return -EBUSY; | |
2868 | } | |
2869 | cm->irq = pci->irq; | |
2870 | ||
2871 | pci_set_master(cm->pci); | |
2872 | ||
2873 | /* | |
2874 | * check chip version, max channels and capabilities | |
2875 | */ | |
2876 | ||
2877 | cm->chip_version = 0; | |
2878 | cm->max_channels = 2; | |
2879 | cm->do_soft_ac3 = soft_ac3[dev]; | |
2880 | ||
2881 | if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A && | |
2882 | pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B) | |
2883 | query_chip(cm); | |
2884 | /* added -MCx suffix for chip supporting multi-channels */ | |
2885 | if (cm->can_multi_ch) | |
2886 | sprintf(cm->card->driver + strlen(cm->card->driver), | |
2887 | "-MC%d", cm->max_channels); | |
2888 | else if (cm->can_ac3_sw) | |
2889 | strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC"); | |
2890 | ||
2891 | cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF; | |
2892 | cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF; | |
2893 | ||
2894 | #if CM_CH_PLAY == 1 | |
2895 | cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */ | |
2896 | #else | |
2897 | cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */ | |
2898 | #endif | |
2899 | ||
2900 | /* initialize codec registers */ | |
2901 | snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ | |
2902 | snd_cmipci_ch_reset(cm, CM_CH_PLAY); | |
2903 | snd_cmipci_ch_reset(cm, CM_CH_CAPT); | |
2904 | snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ | |
2905 | snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); | |
2906 | ||
2907 | snd_cmipci_write(cm, CM_REG_CHFORMAT, 0); | |
2908 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D); | |
2909 | #if CM_CH_PLAY == 1 | |
2910 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); | |
2911 | #else | |
2912 | snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); | |
2913 | #endif | |
2914 | /* Set Bus Master Request */ | |
2915 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ); | |
2916 | ||
2917 | /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */ | |
2918 | switch (pci->device) { | |
2919 | case PCI_DEVICE_ID_CMEDIA_CM8738: | |
2920 | case PCI_DEVICE_ID_CMEDIA_CM8738B: | |
2921 | if (!pci_dev_present(intel_82437vx)) | |
2922 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX); | |
2923 | break; | |
2924 | default: | |
2925 | break; | |
2926 | } | |
2927 | ||
2928 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) { | |
2929 | snd_cmipci_free(cm); | |
2930 | return err; | |
2931 | } | |
2932 | ||
5747e540 CL |
2933 | integrated_midi = snd_cmipci_read_b(cm, CM_REG_MPU_PCI) != 0xff; |
2934 | if (integrated_midi) | |
2935 | iomidi = cm->iobase + CM_REG_MPU_PCI; | |
2936 | else { | |
2937 | iomidi = mpu_port[dev]; | |
2938 | switch (iomidi) { | |
2939 | case 0x320: val = CM_VMPU_320; break; | |
2940 | case 0x310: val = CM_VMPU_310; break; | |
2941 | case 0x300: val = CM_VMPU_300; break; | |
2942 | case 0x330: val = CM_VMPU_330; break; | |
2943 | default: | |
2944 | iomidi = 0; break; | |
2945 | } | |
2946 | if (iomidi > 0) { | |
2947 | snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); | |
2948 | /* enable UART */ | |
2949 | snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN); | |
1da177e4 LT |
2950 | } |
2951 | } | |
5747e540 CL |
2952 | |
2953 | if ((err = snd_cmipci_create_fm(cm, fm_port[dev])) < 0) | |
2954 | return err; | |
1da177e4 LT |
2955 | |
2956 | /* reset mixer */ | |
2957 | snd_cmipci_mixer_write(cm, 0, 0); | |
2958 | ||
2959 | snd_cmipci_proc_init(cm); | |
2960 | ||
2961 | /* create pcm devices */ | |
2962 | pcm_index = pcm_spdif_index = 0; | |
2963 | if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0) | |
2964 | return err; | |
2965 | pcm_index++; | |
2966 | if (cm->has_dual_dac) { | |
2967 | if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0) | |
2968 | return err; | |
2969 | pcm_index++; | |
2970 | } | |
2971 | if (cm->can_ac3_hw || cm->can_ac3_sw) { | |
2972 | pcm_spdif_index = pcm_index; | |
2973 | if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0) | |
2974 | return err; | |
2975 | } | |
2976 | ||
2977 | /* create mixer interface & switches */ | |
2978 | if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0) | |
2979 | return err; | |
2980 | ||
2981 | if (iomidi > 0) { | |
2982 | if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, | |
5747e540 | 2983 | iomidi, integrated_midi, |
1da177e4 LT |
2984 | cm->irq, 0, &cm->rmidi)) < 0) { |
2985 | printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi); | |
2986 | } | |
2987 | } | |
2988 | ||
2989 | #ifdef USE_VAR48KRATE | |
2990 | for (val = 0; val < ARRAY_SIZE(rates); val++) | |
2991 | snd_cmipci_set_pll(cm, rates[val], val); | |
2992 | ||
2993 | /* | |
2994 | * (Re-)Enable external switch spdo_48k | |
2995 | */ | |
2996 | snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97); | |
2997 | #endif /* USE_VAR48KRATE */ | |
2998 | ||
2999 | if (snd_cmipci_create_gameport(cm, dev) < 0) | |
3000 | snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); | |
3001 | ||
3002 | snd_card_set_dev(card, &pci->dev); | |
3003 | ||
3004 | *rcmipci = cm; | |
3005 | return 0; | |
3006 | } | |
3007 | ||
3008 | /* | |
3009 | */ | |
3010 | ||
3011 | MODULE_DEVICE_TABLE(pci, snd_cmipci_ids); | |
3012 | ||
3013 | static int __devinit snd_cmipci_probe(struct pci_dev *pci, | |
3014 | const struct pci_device_id *pci_id) | |
3015 | { | |
3016 | static int dev; | |
2cbdb686 TI |
3017 | struct snd_card *card; |
3018 | struct cmipci *cm; | |
1da177e4 LT |
3019 | int err; |
3020 | ||
3021 | if (dev >= SNDRV_CARDS) | |
3022 | return -ENODEV; | |
3023 | if (! enable[dev]) { | |
3024 | dev++; | |
3025 | return -ENOENT; | |
3026 | } | |
3027 | ||
3028 | card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); | |
3029 | if (card == NULL) | |
3030 | return -ENOMEM; | |
3031 | ||
3032 | switch (pci->device) { | |
3033 | case PCI_DEVICE_ID_CMEDIA_CM8738: | |
3034 | case PCI_DEVICE_ID_CMEDIA_CM8738B: | |
3035 | strcpy(card->driver, "CMI8738"); | |
3036 | break; | |
3037 | case PCI_DEVICE_ID_CMEDIA_CM8338A: | |
3038 | case PCI_DEVICE_ID_CMEDIA_CM8338B: | |
3039 | strcpy(card->driver, "CMI8338"); | |
3040 | break; | |
3041 | default: | |
3042 | strcpy(card->driver, "CMIPCI"); | |
3043 | break; | |
3044 | } | |
3045 | ||
3046 | if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) { | |
3047 | snd_card_free(card); | |
3048 | return err; | |
3049 | } | |
cb60e5f5 | 3050 | card->private_data = cm; |
1da177e4 LT |
3051 | |
3052 | sprintf(card->shortname, "C-Media PCI %s", card->driver); | |
3053 | sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i", | |
3054 | card->shortname, | |
3055 | cm->chip_version, | |
3056 | cm->iobase, | |
3057 | cm->irq); | |
3058 | ||
3059 | //snd_printd("%s is detected\n", card->longname); | |
3060 | ||
3061 | if ((err = snd_card_register(card)) < 0) { | |
3062 | snd_card_free(card); | |
3063 | return err; | |
3064 | } | |
3065 | pci_set_drvdata(pci, card); | |
3066 | dev++; | |
3067 | return 0; | |
3068 | ||
3069 | } | |
3070 | ||
3071 | static void __devexit snd_cmipci_remove(struct pci_dev *pci) | |
3072 | { | |
3073 | snd_card_free(pci_get_drvdata(pci)); | |
3074 | pci_set_drvdata(pci, NULL); | |
3075 | } | |
3076 | ||
3077 | ||
cb60e5f5 TI |
3078 | #ifdef CONFIG_PM |
3079 | /* | |
3080 | * power management | |
3081 | */ | |
3082 | static unsigned char saved_regs[] = { | |
3083 | CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL, | |
3084 | CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL, | |
3085 | CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2, | |
3086 | CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC, | |
3087 | CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0, | |
3088 | }; | |
3089 | ||
3090 | static unsigned char saved_mixers[] = { | |
3091 | SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1, | |
3092 | SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1, | |
3093 | SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1, | |
3094 | SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1, | |
3095 | SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1, | |
3096 | SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV, | |
3097 | CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW, | |
3098 | SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, | |
3099 | }; | |
3100 | ||
3101 | static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state) | |
3102 | { | |
3103 | struct snd_card *card = pci_get_drvdata(pci); | |
3104 | struct cmipci *cm = card->private_data; | |
3105 | int i; | |
3106 | ||
3107 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); | |
3108 | ||
3109 | snd_pcm_suspend_all(cm->pcm); | |
3110 | snd_pcm_suspend_all(cm->pcm2); | |
3111 | snd_pcm_suspend_all(cm->pcm_spdif); | |
3112 | ||
3113 | /* save registers */ | |
3114 | for (i = 0; i < ARRAY_SIZE(saved_regs); i++) | |
3115 | cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]); | |
3116 | for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) | |
3117 | cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]); | |
3118 | ||
3119 | /* disable ints */ | |
3120 | snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); | |
3121 | ||
3122 | pci_set_power_state(pci, PCI_D3hot); | |
3123 | pci_disable_device(pci); | |
3124 | pci_save_state(pci); | |
3125 | return 0; | |
3126 | } | |
3127 | ||
3128 | static int snd_cmipci_resume(struct pci_dev *pci) | |
3129 | { | |
3130 | struct snd_card *card = pci_get_drvdata(pci); | |
3131 | struct cmipci *cm = card->private_data; | |
3132 | int i; | |
3133 | ||
3134 | pci_restore_state(pci); | |
3135 | pci_enable_device(pci); | |
3136 | pci_set_power_state(pci, PCI_D0); | |
3137 | pci_set_master(pci); | |
3138 | ||
3139 | /* reset / initialize to a sane state */ | |
3140 | snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); | |
3141 | snd_cmipci_ch_reset(cm, CM_CH_PLAY); | |
3142 | snd_cmipci_ch_reset(cm, CM_CH_CAPT); | |
3143 | snd_cmipci_mixer_write(cm, 0, 0); | |
3144 | ||
3145 | /* restore registers */ | |
3146 | for (i = 0; i < ARRAY_SIZE(saved_regs); i++) | |
3147 | snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]); | |
3148 | for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) | |
3149 | snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]); | |
3150 | ||
3151 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); | |
3152 | return 0; | |
3153 | } | |
3154 | #endif /* CONFIG_PM */ | |
3155 | ||
1da177e4 LT |
3156 | static struct pci_driver driver = { |
3157 | .name = "C-Media PCI", | |
3158 | .id_table = snd_cmipci_ids, | |
3159 | .probe = snd_cmipci_probe, | |
3160 | .remove = __devexit_p(snd_cmipci_remove), | |
cb60e5f5 TI |
3161 | #ifdef CONFIG_PM |
3162 | .suspend = snd_cmipci_suspend, | |
3163 | .resume = snd_cmipci_resume, | |
3164 | #endif | |
1da177e4 LT |
3165 | }; |
3166 | ||
3167 | static int __init alsa_card_cmipci_init(void) | |
3168 | { | |
01d25d46 | 3169 | return pci_register_driver(&driver); |
1da177e4 LT |
3170 | } |
3171 | ||
3172 | static void __exit alsa_card_cmipci_exit(void) | |
3173 | { | |
3174 | pci_unregister_driver(&driver); | |
3175 | } | |
3176 | ||
3177 | module_init(alsa_card_cmipci_init) | |
3178 | module_exit(alsa_card_cmipci_exit) |