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8cc72361 WYC |
1 | /** |
2 | * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. | |
3 | * | |
4 | * This source file is released under GPL v2 license (no other versions). | |
5 | * See the COPYING file included in the main directory of this source | |
6 | * distribution for the license terms and conditions. | |
7 | * | |
8 | * @File cthw20k1.c | |
9 | * | |
10 | * @Brief | |
11 | * This file contains the implementation of hardware access methord for 20k1. | |
12 | * | |
13 | * @Author Liu Chun | |
14 | * @Date Jun 24 2008 | |
15 | * | |
16 | */ | |
17 | ||
8cc72361 WYC |
18 | #include <linux/types.h> |
19 | #include <linux/slab.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/string.h> | |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/interrupt.h> | |
d0da727e | 26 | #include <linux/delay.h> |
6d74b86d TI |
27 | #include "cthw20k1.h" |
28 | #include "ct20k1reg.h" | |
8cc72361 | 29 | |
8cc72361 WYC |
30 | struct hw20k1 { |
31 | struct hw hw; | |
32 | spinlock_t reg_20k1_lock; | |
33 | spinlock_t reg_pci_lock; | |
34 | }; | |
35 | ||
36 | static u32 hw_read_20kx(struct hw *hw, u32 reg); | |
37 | static void hw_write_20kx(struct hw *hw, u32 reg, u32 data); | |
38 | static u32 hw_read_pci(struct hw *hw, u32 reg); | |
39 | static void hw_write_pci(struct hw *hw, u32 reg, u32 data); | |
40 | ||
41 | /* | |
42 | * Type definition block. | |
43 | * The layout of control structures can be directly applied on 20k2 chip. | |
44 | */ | |
45 | ||
46 | /* | |
47 | * SRC control block definitions. | |
48 | */ | |
49 | ||
50 | /* SRC resource control block */ | |
51 | #define SRCCTL_STATE 0x00000007 | |
52 | #define SRCCTL_BM 0x00000008 | |
53 | #define SRCCTL_RSR 0x00000030 | |
54 | #define SRCCTL_SF 0x000001C0 | |
55 | #define SRCCTL_WR 0x00000200 | |
56 | #define SRCCTL_PM 0x00000400 | |
57 | #define SRCCTL_ROM 0x00001800 | |
58 | #define SRCCTL_VO 0x00002000 | |
59 | #define SRCCTL_ST 0x00004000 | |
60 | #define SRCCTL_IE 0x00008000 | |
61 | #define SRCCTL_ILSZ 0x000F0000 | |
62 | #define SRCCTL_BP 0x00100000 | |
63 | ||
64 | #define SRCCCR_CISZ 0x000007FF | |
65 | #define SRCCCR_CWA 0x001FF800 | |
66 | #define SRCCCR_D 0x00200000 | |
67 | #define SRCCCR_RS 0x01C00000 | |
68 | #define SRCCCR_NAL 0x3E000000 | |
69 | #define SRCCCR_RA 0xC0000000 | |
70 | ||
71 | #define SRCCA_CA 0x03FFFFFF | |
72 | #define SRCCA_RS 0x1C000000 | |
73 | #define SRCCA_NAL 0xE0000000 | |
74 | ||
75 | #define SRCSA_SA 0x03FFFFFF | |
76 | ||
77 | #define SRCLA_LA 0x03FFFFFF | |
78 | ||
79 | /* Mixer Parameter Ring ram Low and Hight register. | |
80 | * Fixed-point value in 8.24 format for parameter channel */ | |
81 | #define MPRLH_PITCH 0xFFFFFFFF | |
82 | ||
83 | /* SRC resource register dirty flags */ | |
84 | union src_dirty { | |
85 | struct { | |
86 | u16 ctl:1; | |
87 | u16 ccr:1; | |
88 | u16 sa:1; | |
89 | u16 la:1; | |
90 | u16 ca:1; | |
91 | u16 mpr:1; | |
92 | u16 czbfs:1; /* Clear Z-Buffers */ | |
93 | u16 rsv:9; | |
94 | } bf; | |
95 | u16 data; | |
96 | }; | |
97 | ||
98 | struct src_rsc_ctrl_blk { | |
99 | unsigned int ctl; | |
100 | unsigned int ccr; | |
101 | unsigned int ca; | |
102 | unsigned int sa; | |
103 | unsigned int la; | |
104 | unsigned int mpr; | |
105 | union src_dirty dirty; | |
106 | }; | |
107 | ||
108 | /* SRC manager control block */ | |
109 | union src_mgr_dirty { | |
110 | struct { | |
111 | u16 enb0:1; | |
112 | u16 enb1:1; | |
113 | u16 enb2:1; | |
114 | u16 enb3:1; | |
115 | u16 enb4:1; | |
116 | u16 enb5:1; | |
117 | u16 enb6:1; | |
118 | u16 enb7:1; | |
119 | u16 enbsa:1; | |
120 | u16 rsv:7; | |
121 | } bf; | |
122 | u16 data; | |
123 | }; | |
124 | ||
125 | struct src_mgr_ctrl_blk { | |
126 | unsigned int enbsa; | |
127 | unsigned int enb[8]; | |
128 | union src_mgr_dirty dirty; | |
129 | }; | |
130 | ||
131 | /* SRCIMP manager control block */ | |
132 | #define SRCAIM_ARC 0x00000FFF | |
133 | #define SRCAIM_NXT 0x00FF0000 | |
134 | #define SRCAIM_SRC 0xFF000000 | |
135 | ||
136 | struct srcimap { | |
137 | unsigned int srcaim; | |
138 | unsigned int idx; | |
139 | }; | |
140 | ||
141 | /* SRCIMP manager register dirty flags */ | |
142 | union srcimp_mgr_dirty { | |
143 | struct { | |
144 | u16 srcimap:1; | |
145 | u16 rsv:15; | |
146 | } bf; | |
147 | u16 data; | |
148 | }; | |
149 | ||
150 | struct srcimp_mgr_ctrl_blk { | |
151 | struct srcimap srcimap; | |
152 | union srcimp_mgr_dirty dirty; | |
153 | }; | |
154 | ||
155 | /* | |
156 | * Function implementation block. | |
157 | */ | |
158 | ||
159 | static int src_get_rsc_ctrl_blk(void **rblk) | |
160 | { | |
161 | struct src_rsc_ctrl_blk *blk; | |
162 | ||
163 | *rblk = NULL; | |
164 | blk = kzalloc(sizeof(*blk), GFP_KERNEL); | |
35ebf6e7 | 165 | if (!blk) |
8cc72361 WYC |
166 | return -ENOMEM; |
167 | ||
168 | *rblk = blk; | |
169 | ||
170 | return 0; | |
171 | } | |
172 | ||
173 | static int src_put_rsc_ctrl_blk(void *blk) | |
174 | { | |
175 | kfree((struct src_rsc_ctrl_blk *)blk); | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
180 | static int src_set_state(void *blk, unsigned int state) | |
181 | { | |
182 | struct src_rsc_ctrl_blk *ctl = blk; | |
183 | ||
184 | set_field(&ctl->ctl, SRCCTL_STATE, state); | |
185 | ctl->dirty.bf.ctl = 1; | |
186 | return 0; | |
187 | } | |
188 | ||
189 | static int src_set_bm(void *blk, unsigned int bm) | |
190 | { | |
191 | struct src_rsc_ctrl_blk *ctl = blk; | |
192 | ||
193 | set_field(&ctl->ctl, SRCCTL_BM, bm); | |
194 | ctl->dirty.bf.ctl = 1; | |
195 | return 0; | |
196 | } | |
197 | ||
198 | static int src_set_rsr(void *blk, unsigned int rsr) | |
199 | { | |
200 | struct src_rsc_ctrl_blk *ctl = blk; | |
201 | ||
202 | set_field(&ctl->ctl, SRCCTL_RSR, rsr); | |
203 | ctl->dirty.bf.ctl = 1; | |
204 | return 0; | |
205 | } | |
206 | ||
207 | static int src_set_sf(void *blk, unsigned int sf) | |
208 | { | |
209 | struct src_rsc_ctrl_blk *ctl = blk; | |
210 | ||
211 | set_field(&ctl->ctl, SRCCTL_SF, sf); | |
212 | ctl->dirty.bf.ctl = 1; | |
213 | return 0; | |
214 | } | |
215 | ||
216 | static int src_set_wr(void *blk, unsigned int wr) | |
217 | { | |
218 | struct src_rsc_ctrl_blk *ctl = blk; | |
219 | ||
220 | set_field(&ctl->ctl, SRCCTL_WR, wr); | |
221 | ctl->dirty.bf.ctl = 1; | |
222 | return 0; | |
223 | } | |
224 | ||
225 | static int src_set_pm(void *blk, unsigned int pm) | |
226 | { | |
227 | struct src_rsc_ctrl_blk *ctl = blk; | |
228 | ||
229 | set_field(&ctl->ctl, SRCCTL_PM, pm); | |
230 | ctl->dirty.bf.ctl = 1; | |
231 | return 0; | |
232 | } | |
233 | ||
234 | static int src_set_rom(void *blk, unsigned int rom) | |
235 | { | |
236 | struct src_rsc_ctrl_blk *ctl = blk; | |
237 | ||
238 | set_field(&ctl->ctl, SRCCTL_ROM, rom); | |
239 | ctl->dirty.bf.ctl = 1; | |
240 | return 0; | |
241 | } | |
242 | ||
243 | static int src_set_vo(void *blk, unsigned int vo) | |
244 | { | |
245 | struct src_rsc_ctrl_blk *ctl = blk; | |
246 | ||
247 | set_field(&ctl->ctl, SRCCTL_VO, vo); | |
248 | ctl->dirty.bf.ctl = 1; | |
249 | return 0; | |
250 | } | |
251 | ||
252 | static int src_set_st(void *blk, unsigned int st) | |
253 | { | |
254 | struct src_rsc_ctrl_blk *ctl = blk; | |
255 | ||
256 | set_field(&ctl->ctl, SRCCTL_ST, st); | |
257 | ctl->dirty.bf.ctl = 1; | |
258 | return 0; | |
259 | } | |
260 | ||
261 | static int src_set_ie(void *blk, unsigned int ie) | |
262 | { | |
263 | struct src_rsc_ctrl_blk *ctl = blk; | |
264 | ||
265 | set_field(&ctl->ctl, SRCCTL_IE, ie); | |
266 | ctl->dirty.bf.ctl = 1; | |
267 | return 0; | |
268 | } | |
269 | ||
270 | static int src_set_ilsz(void *blk, unsigned int ilsz) | |
271 | { | |
272 | struct src_rsc_ctrl_blk *ctl = blk; | |
273 | ||
274 | set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz); | |
275 | ctl->dirty.bf.ctl = 1; | |
276 | return 0; | |
277 | } | |
278 | ||
279 | static int src_set_bp(void *blk, unsigned int bp) | |
280 | { | |
281 | struct src_rsc_ctrl_blk *ctl = blk; | |
282 | ||
283 | set_field(&ctl->ctl, SRCCTL_BP, bp); | |
284 | ctl->dirty.bf.ctl = 1; | |
285 | return 0; | |
286 | } | |
287 | ||
288 | static int src_set_cisz(void *blk, unsigned int cisz) | |
289 | { | |
290 | struct src_rsc_ctrl_blk *ctl = blk; | |
291 | ||
292 | set_field(&ctl->ccr, SRCCCR_CISZ, cisz); | |
293 | ctl->dirty.bf.ccr = 1; | |
294 | return 0; | |
295 | } | |
296 | ||
297 | static int src_set_ca(void *blk, unsigned int ca) | |
298 | { | |
299 | struct src_rsc_ctrl_blk *ctl = blk; | |
300 | ||
301 | set_field(&ctl->ca, SRCCA_CA, ca); | |
302 | ctl->dirty.bf.ca = 1; | |
303 | return 0; | |
304 | } | |
305 | ||
306 | static int src_set_sa(void *blk, unsigned int sa) | |
307 | { | |
308 | struct src_rsc_ctrl_blk *ctl = blk; | |
309 | ||
310 | set_field(&ctl->sa, SRCSA_SA, sa); | |
311 | ctl->dirty.bf.sa = 1; | |
312 | return 0; | |
313 | } | |
314 | ||
315 | static int src_set_la(void *blk, unsigned int la) | |
316 | { | |
317 | struct src_rsc_ctrl_blk *ctl = blk; | |
318 | ||
319 | set_field(&ctl->la, SRCLA_LA, la); | |
320 | ctl->dirty.bf.la = 1; | |
321 | return 0; | |
322 | } | |
323 | ||
324 | static int src_set_pitch(void *blk, unsigned int pitch) | |
325 | { | |
326 | struct src_rsc_ctrl_blk *ctl = blk; | |
327 | ||
328 | set_field(&ctl->mpr, MPRLH_PITCH, pitch); | |
329 | ctl->dirty.bf.mpr = 1; | |
330 | return 0; | |
331 | } | |
332 | ||
333 | static int src_set_clear_zbufs(void *blk, unsigned int clear) | |
334 | { | |
335 | ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0); | |
336 | return 0; | |
337 | } | |
338 | ||
339 | static int src_set_dirty(void *blk, unsigned int flags) | |
340 | { | |
341 | ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff); | |
342 | return 0; | |
343 | } | |
344 | ||
345 | static int src_set_dirty_all(void *blk) | |
346 | { | |
347 | ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0); | |
348 | return 0; | |
349 | } | |
350 | ||
351 | #define AR_SLOT_SIZE 4096 | |
352 | #define AR_SLOT_BLOCK_SIZE 16 | |
353 | #define AR_PTS_PITCH 6 | |
354 | #define AR_PARAM_SRC_OFFSET 0x60 | |
355 | ||
356 | static unsigned int src_param_pitch_mixer(unsigned int src_idx) | |
357 | { | |
358 | return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE | |
359 | - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE; | |
360 | ||
361 | } | |
362 | ||
363 | static int src_commit_write(struct hw *hw, unsigned int idx, void *blk) | |
364 | { | |
365 | struct src_rsc_ctrl_blk *ctl = blk; | |
514eef9c | 366 | int i; |
8cc72361 WYC |
367 | |
368 | if (ctl->dirty.bf.czbfs) { | |
369 | /* Clear Z-Buffer registers */ | |
370 | for (i = 0; i < 8; i++) | |
371 | hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, 0); | |
372 | ||
373 | for (i = 0; i < 4; i++) | |
374 | hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, 0); | |
375 | ||
376 | for (i = 0; i < 8; i++) | |
377 | hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, 0); | |
378 | ||
379 | ctl->dirty.bf.czbfs = 0; | |
380 | } | |
381 | if (ctl->dirty.bf.mpr) { | |
382 | /* Take the parameter mixer resource in the same group as that | |
383 | * the idx src is in for simplicity. Unlike src, all conjugate | |
384 | * parameter mixer resources must be programmed for | |
385 | * corresponding conjugate src resources. */ | |
386 | unsigned int pm_idx = src_param_pitch_mixer(idx); | |
387 | hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, ctl->mpr); | |
388 | hw_write_20kx(hw, PMOPLO+8*pm_idx, 0x3); | |
389 | hw_write_20kx(hw, PMOPHI+8*pm_idx, 0x0); | |
390 | ctl->dirty.bf.mpr = 0; | |
391 | } | |
392 | if (ctl->dirty.bf.sa) { | |
393 | hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa); | |
394 | ctl->dirty.bf.sa = 0; | |
395 | } | |
396 | if (ctl->dirty.bf.la) { | |
397 | hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la); | |
398 | ctl->dirty.bf.la = 0; | |
399 | } | |
400 | if (ctl->dirty.bf.ca) { | |
401 | hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca); | |
402 | ctl->dirty.bf.ca = 0; | |
403 | } | |
404 | ||
405 | /* Write srccf register */ | |
406 | hw_write_20kx(hw, SRCCF+idx*0x100, 0x0); | |
407 | ||
408 | if (ctl->dirty.bf.ccr) { | |
409 | hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr); | |
410 | ctl->dirty.bf.ccr = 0; | |
411 | } | |
412 | if (ctl->dirty.bf.ctl) { | |
413 | hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl); | |
414 | ctl->dirty.bf.ctl = 0; | |
415 | } | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
420 | static int src_get_ca(struct hw *hw, unsigned int idx, void *blk) | |
421 | { | |
422 | struct src_rsc_ctrl_blk *ctl = blk; | |
423 | ||
424 | ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100); | |
425 | ctl->dirty.bf.ca = 0; | |
426 | ||
427 | return get_field(ctl->ca, SRCCA_CA); | |
428 | } | |
429 | ||
430 | static unsigned int src_get_dirty(void *blk) | |
431 | { | |
432 | return ((struct src_rsc_ctrl_blk *)blk)->dirty.data; | |
433 | } | |
434 | ||
435 | static unsigned int src_dirty_conj_mask(void) | |
436 | { | |
437 | return 0x20; | |
438 | } | |
439 | ||
440 | static int src_mgr_enbs_src(void *blk, unsigned int idx) | |
441 | { | |
442 | ((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0); | |
443 | ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1; | |
444 | ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32)); | |
445 | return 0; | |
446 | } | |
447 | ||
448 | static int src_mgr_enb_src(void *blk, unsigned int idx) | |
449 | { | |
450 | ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32)); | |
451 | ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32)); | |
452 | return 0; | |
453 | } | |
454 | ||
455 | static int src_mgr_dsb_src(void *blk, unsigned int idx) | |
456 | { | |
457 | ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32)); | |
458 | ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32)); | |
459 | return 0; | |
460 | } | |
461 | ||
462 | static int src_mgr_commit_write(struct hw *hw, void *blk) | |
463 | { | |
464 | struct src_mgr_ctrl_blk *ctl = blk; | |
514eef9c TI |
465 | int i; |
466 | unsigned int ret; | |
8cc72361 WYC |
467 | |
468 | if (ctl->dirty.bf.enbsa) { | |
469 | do { | |
470 | ret = hw_read_20kx(hw, SRCENBSTAT); | |
471 | } while (ret & 0x1); | |
472 | hw_write_20kx(hw, SRCENBS, ctl->enbsa); | |
473 | ctl->dirty.bf.enbsa = 0; | |
474 | } | |
475 | for (i = 0; i < 8; i++) { | |
476 | if ((ctl->dirty.data & (0x1 << i))) { | |
477 | hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]); | |
478 | ctl->dirty.data &= ~(0x1 << i); | |
479 | } | |
480 | } | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | static int src_mgr_get_ctrl_blk(void **rblk) | |
486 | { | |
487 | struct src_mgr_ctrl_blk *blk; | |
488 | ||
489 | *rblk = NULL; | |
490 | blk = kzalloc(sizeof(*blk), GFP_KERNEL); | |
35ebf6e7 | 491 | if (!blk) |
8cc72361 WYC |
492 | return -ENOMEM; |
493 | ||
494 | *rblk = blk; | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
499 | static int src_mgr_put_ctrl_blk(void *blk) | |
500 | { | |
501 | kfree((struct src_mgr_ctrl_blk *)blk); | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | static int srcimp_mgr_get_ctrl_blk(void **rblk) | |
507 | { | |
508 | struct srcimp_mgr_ctrl_blk *blk; | |
509 | ||
510 | *rblk = NULL; | |
511 | blk = kzalloc(sizeof(*blk), GFP_KERNEL); | |
35ebf6e7 | 512 | if (!blk) |
8cc72361 WYC |
513 | return -ENOMEM; |
514 | ||
515 | *rblk = blk; | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
520 | static int srcimp_mgr_put_ctrl_blk(void *blk) | |
521 | { | |
522 | kfree((struct srcimp_mgr_ctrl_blk *)blk); | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
527 | static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot) | |
528 | { | |
529 | struct srcimp_mgr_ctrl_blk *ctl = blk; | |
530 | ||
531 | set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot); | |
532 | ctl->dirty.bf.srcimap = 1; | |
533 | return 0; | |
534 | } | |
535 | ||
536 | static int srcimp_mgr_set_imapuser(void *blk, unsigned int user) | |
537 | { | |
538 | struct srcimp_mgr_ctrl_blk *ctl = blk; | |
539 | ||
540 | set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user); | |
541 | ctl->dirty.bf.srcimap = 1; | |
542 | return 0; | |
543 | } | |
544 | ||
545 | static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next) | |
546 | { | |
547 | struct srcimp_mgr_ctrl_blk *ctl = blk; | |
548 | ||
549 | set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next); | |
550 | ctl->dirty.bf.srcimap = 1; | |
551 | return 0; | |
552 | } | |
553 | ||
554 | static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr) | |
555 | { | |
556 | struct srcimp_mgr_ctrl_blk *ctl = blk; | |
557 | ||
558 | ctl->srcimap.idx = addr; | |
559 | ctl->dirty.bf.srcimap = 1; | |
560 | return 0; | |
561 | } | |
562 | ||
563 | static int srcimp_mgr_commit_write(struct hw *hw, void *blk) | |
564 | { | |
565 | struct srcimp_mgr_ctrl_blk *ctl = blk; | |
566 | ||
567 | if (ctl->dirty.bf.srcimap) { | |
568 | hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100, | |
569 | ctl->srcimap.srcaim); | |
570 | ctl->dirty.bf.srcimap = 0; | |
571 | } | |
572 | ||
573 | return 0; | |
574 | } | |
575 | ||
576 | /* | |
577 | * AMIXER control block definitions. | |
578 | */ | |
579 | ||
580 | #define AMOPLO_M 0x00000003 | |
581 | #define AMOPLO_X 0x0003FFF0 | |
582 | #define AMOPLO_Y 0xFFFC0000 | |
583 | ||
584 | #define AMOPHI_SADR 0x000000FF | |
585 | #define AMOPHI_SE 0x80000000 | |
586 | ||
587 | /* AMIXER resource register dirty flags */ | |
588 | union amixer_dirty { | |
589 | struct { | |
590 | u16 amoplo:1; | |
591 | u16 amophi:1; | |
592 | u16 rsv:14; | |
593 | } bf; | |
594 | u16 data; | |
595 | }; | |
596 | ||
597 | /* AMIXER resource control block */ | |
598 | struct amixer_rsc_ctrl_blk { | |
599 | unsigned int amoplo; | |
600 | unsigned int amophi; | |
601 | union amixer_dirty dirty; | |
602 | }; | |
603 | ||
604 | static int amixer_set_mode(void *blk, unsigned int mode) | |
605 | { | |
606 | struct amixer_rsc_ctrl_blk *ctl = blk; | |
607 | ||
608 | set_field(&ctl->amoplo, AMOPLO_M, mode); | |
609 | ctl->dirty.bf.amoplo = 1; | |
610 | return 0; | |
611 | } | |
612 | ||
613 | static int amixer_set_iv(void *blk, unsigned int iv) | |
614 | { | |
615 | /* 20k1 amixer does not have this field */ | |
616 | return 0; | |
617 | } | |
618 | ||
619 | static int amixer_set_x(void *blk, unsigned int x) | |
620 | { | |
621 | struct amixer_rsc_ctrl_blk *ctl = blk; | |
622 | ||
623 | set_field(&ctl->amoplo, AMOPLO_X, x); | |
624 | ctl->dirty.bf.amoplo = 1; | |
625 | return 0; | |
626 | } | |
627 | ||
628 | static int amixer_set_y(void *blk, unsigned int y) | |
629 | { | |
630 | struct amixer_rsc_ctrl_blk *ctl = blk; | |
631 | ||
632 | set_field(&ctl->amoplo, AMOPLO_Y, y); | |
633 | ctl->dirty.bf.amoplo = 1; | |
634 | return 0; | |
635 | } | |
636 | ||
637 | static int amixer_set_sadr(void *blk, unsigned int sadr) | |
638 | { | |
639 | struct amixer_rsc_ctrl_blk *ctl = blk; | |
640 | ||
641 | set_field(&ctl->amophi, AMOPHI_SADR, sadr); | |
642 | ctl->dirty.bf.amophi = 1; | |
643 | return 0; | |
644 | } | |
645 | ||
646 | static int amixer_set_se(void *blk, unsigned int se) | |
647 | { | |
648 | struct amixer_rsc_ctrl_blk *ctl = blk; | |
649 | ||
650 | set_field(&ctl->amophi, AMOPHI_SE, se); | |
651 | ctl->dirty.bf.amophi = 1; | |
652 | return 0; | |
653 | } | |
654 | ||
655 | static int amixer_set_dirty(void *blk, unsigned int flags) | |
656 | { | |
657 | ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff); | |
658 | return 0; | |
659 | } | |
660 | ||
661 | static int amixer_set_dirty_all(void *blk) | |
662 | { | |
663 | ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0); | |
664 | return 0; | |
665 | } | |
666 | ||
667 | static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk) | |
668 | { | |
669 | struct amixer_rsc_ctrl_blk *ctl = blk; | |
670 | ||
671 | if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) { | |
672 | hw_write_20kx(hw, AMOPLO+idx*8, ctl->amoplo); | |
673 | ctl->dirty.bf.amoplo = 0; | |
674 | hw_write_20kx(hw, AMOPHI+idx*8, ctl->amophi); | |
675 | ctl->dirty.bf.amophi = 0; | |
676 | } | |
677 | ||
678 | return 0; | |
679 | } | |
680 | ||
681 | static int amixer_get_y(void *blk) | |
682 | { | |
683 | struct amixer_rsc_ctrl_blk *ctl = blk; | |
684 | ||
685 | return get_field(ctl->amoplo, AMOPLO_Y); | |
686 | } | |
687 | ||
688 | static unsigned int amixer_get_dirty(void *blk) | |
689 | { | |
690 | return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data; | |
691 | } | |
692 | ||
693 | static int amixer_rsc_get_ctrl_blk(void **rblk) | |
694 | { | |
695 | struct amixer_rsc_ctrl_blk *blk; | |
696 | ||
697 | *rblk = NULL; | |
698 | blk = kzalloc(sizeof(*blk), GFP_KERNEL); | |
35ebf6e7 | 699 | if (!blk) |
8cc72361 WYC |
700 | return -ENOMEM; |
701 | ||
702 | *rblk = blk; | |
703 | ||
704 | return 0; | |
705 | } | |
706 | ||
707 | static int amixer_rsc_put_ctrl_blk(void *blk) | |
708 | { | |
709 | kfree((struct amixer_rsc_ctrl_blk *)blk); | |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
714 | static int amixer_mgr_get_ctrl_blk(void **rblk) | |
715 | { | |
716 | /*amixer_mgr_ctrl_blk_t *blk;*/ | |
717 | ||
718 | *rblk = NULL; | |
719 | /*blk = kzalloc(sizeof(*blk), GFP_KERNEL); | |
35ebf6e7 | 720 | if (!blk) |
8cc72361 WYC |
721 | return -ENOMEM; |
722 | ||
723 | *rblk = blk;*/ | |
724 | ||
725 | return 0; | |
726 | } | |
727 | ||
728 | static int amixer_mgr_put_ctrl_blk(void *blk) | |
729 | { | |
730 | /*kfree((amixer_mgr_ctrl_blk_t *)blk);*/ | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
735 | /* | |
736 | * DAIO control block definitions. | |
737 | */ | |
738 | ||
739 | /* Receiver Sample Rate Tracker Control register */ | |
740 | #define SRTCTL_SRCR 0x000000FF | |
741 | #define SRTCTL_SRCL 0x0000FF00 | |
742 | #define SRTCTL_RSR 0x00030000 | |
743 | #define SRTCTL_DRAT 0x000C0000 | |
744 | #define SRTCTL_RLE 0x10000000 | |
745 | #define SRTCTL_RLP 0x20000000 | |
746 | #define SRTCTL_EC 0x40000000 | |
747 | #define SRTCTL_ET 0x80000000 | |
748 | ||
749 | /* DAIO Receiver register dirty flags */ | |
750 | union dai_dirty { | |
751 | struct { | |
752 | u16 srtctl:1; | |
753 | u16 rsv:15; | |
754 | } bf; | |
755 | u16 data; | |
756 | }; | |
757 | ||
758 | /* DAIO Receiver control block */ | |
759 | struct dai_ctrl_blk { | |
760 | unsigned int srtctl; | |
761 | union dai_dirty dirty; | |
762 | }; | |
763 | ||
764 | /* S/PDIF Transmitter register dirty flags */ | |
765 | union dao_dirty { | |
766 | struct { | |
767 | u16 spos:1; | |
768 | u16 rsv:15; | |
769 | } bf; | |
770 | u16 data; | |
771 | }; | |
772 | ||
773 | /* S/PDIF Transmitter control block */ | |
774 | struct dao_ctrl_blk { | |
775 | unsigned int spos; /* S/PDIF Output Channel Status Register */ | |
776 | union dao_dirty dirty; | |
777 | }; | |
778 | ||
779 | /* Audio Input Mapper RAM */ | |
780 | #define AIM_ARC 0x00000FFF | |
781 | #define AIM_NXT 0x007F0000 | |
782 | ||
783 | struct daoimap { | |
784 | unsigned int aim; | |
785 | unsigned int idx; | |
786 | }; | |
787 | ||
788 | /* I2S Transmitter/Receiver Control register */ | |
789 | #define I2SCTL_EA 0x00000004 | |
790 | #define I2SCTL_EI 0x00000010 | |
791 | ||
792 | /* S/PDIF Transmitter Control register */ | |
793 | #define SPOCTL_OE 0x00000001 | |
794 | #define SPOCTL_OS 0x0000000E | |
795 | #define SPOCTL_RIV 0x00000010 | |
796 | #define SPOCTL_LIV 0x00000020 | |
797 | #define SPOCTL_SR 0x000000C0 | |
798 | ||
799 | /* S/PDIF Receiver Control register */ | |
800 | #define SPICTL_EN 0x00000001 | |
801 | #define SPICTL_I24 0x00000002 | |
802 | #define SPICTL_IB 0x00000004 | |
803 | #define SPICTL_SM 0x00000008 | |
804 | #define SPICTL_VM 0x00000010 | |
805 | ||
806 | /* DAIO manager register dirty flags */ | |
807 | union daio_mgr_dirty { | |
808 | struct { | |
809 | u32 i2soctl:4; | |
810 | u32 i2sictl:4; | |
811 | u32 spoctl:4; | |
812 | u32 spictl:4; | |
813 | u32 daoimap:1; | |
814 | u32 rsv:15; | |
815 | } bf; | |
816 | u32 data; | |
817 | }; | |
818 | ||
819 | /* DAIO manager control block */ | |
820 | struct daio_mgr_ctrl_blk { | |
821 | unsigned int i2sctl; | |
822 | unsigned int spoctl; | |
823 | unsigned int spictl; | |
824 | struct daoimap daoimap; | |
825 | union daio_mgr_dirty dirty; | |
826 | }; | |
827 | ||
828 | static int dai_srt_set_srcr(void *blk, unsigned int src) | |
829 | { | |
830 | struct dai_ctrl_blk *ctl = blk; | |
831 | ||
832 | set_field(&ctl->srtctl, SRTCTL_SRCR, src); | |
833 | ctl->dirty.bf.srtctl = 1; | |
834 | return 0; | |
835 | } | |
836 | ||
837 | static int dai_srt_set_srcl(void *blk, unsigned int src) | |
838 | { | |
839 | struct dai_ctrl_blk *ctl = blk; | |
840 | ||
841 | set_field(&ctl->srtctl, SRTCTL_SRCL, src); | |
842 | ctl->dirty.bf.srtctl = 1; | |
843 | return 0; | |
844 | } | |
845 | ||
846 | static int dai_srt_set_rsr(void *blk, unsigned int rsr) | |
847 | { | |
848 | struct dai_ctrl_blk *ctl = blk; | |
849 | ||
850 | set_field(&ctl->srtctl, SRTCTL_RSR, rsr); | |
851 | ctl->dirty.bf.srtctl = 1; | |
852 | return 0; | |
853 | } | |
854 | ||
855 | static int dai_srt_set_drat(void *blk, unsigned int drat) | |
856 | { | |
857 | struct dai_ctrl_blk *ctl = blk; | |
858 | ||
859 | set_field(&ctl->srtctl, SRTCTL_DRAT, drat); | |
860 | ctl->dirty.bf.srtctl = 1; | |
861 | return 0; | |
862 | } | |
863 | ||
864 | static int dai_srt_set_ec(void *blk, unsigned int ec) | |
865 | { | |
866 | struct dai_ctrl_blk *ctl = blk; | |
867 | ||
868 | set_field(&ctl->srtctl, SRTCTL_EC, ec ? 1 : 0); | |
869 | ctl->dirty.bf.srtctl = 1; | |
870 | return 0; | |
871 | } | |
872 | ||
873 | static int dai_srt_set_et(void *blk, unsigned int et) | |
874 | { | |
875 | struct dai_ctrl_blk *ctl = blk; | |
876 | ||
877 | set_field(&ctl->srtctl, SRTCTL_ET, et ? 1 : 0); | |
878 | ctl->dirty.bf.srtctl = 1; | |
879 | return 0; | |
880 | } | |
881 | ||
882 | static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk) | |
883 | { | |
884 | struct dai_ctrl_blk *ctl = blk; | |
885 | ||
886 | if (ctl->dirty.bf.srtctl) { | |
887 | if (idx < 4) { | |
888 | /* S/PDIF SRTs */ | |
889 | hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl); | |
890 | } else { | |
891 | /* I2S SRT */ | |
892 | hw_write_20kx(hw, SRTICTL, ctl->srtctl); | |
893 | } | |
894 | ctl->dirty.bf.srtctl = 0; | |
895 | } | |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
900 | static int dai_get_ctrl_blk(void **rblk) | |
901 | { | |
902 | struct dai_ctrl_blk *blk; | |
903 | ||
904 | *rblk = NULL; | |
905 | blk = kzalloc(sizeof(*blk), GFP_KERNEL); | |
35ebf6e7 | 906 | if (!blk) |
8cc72361 WYC |
907 | return -ENOMEM; |
908 | ||
909 | *rblk = blk; | |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
914 | static int dai_put_ctrl_blk(void *blk) | |
915 | { | |
916 | kfree((struct dai_ctrl_blk *)blk); | |
917 | ||
918 | return 0; | |
919 | } | |
920 | ||
921 | static int dao_set_spos(void *blk, unsigned int spos) | |
922 | { | |
923 | ((struct dao_ctrl_blk *)blk)->spos = spos; | |
924 | ((struct dao_ctrl_blk *)blk)->dirty.bf.spos = 1; | |
925 | return 0; | |
926 | } | |
927 | ||
928 | static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk) | |
929 | { | |
930 | struct dao_ctrl_blk *ctl = blk; | |
931 | ||
932 | if (ctl->dirty.bf.spos) { | |
933 | if (idx < 4) { | |
934 | /* S/PDIF SPOSx */ | |
935 | hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos); | |
936 | } | |
937 | ctl->dirty.bf.spos = 0; | |
938 | } | |
939 | ||
940 | return 0; | |
941 | } | |
942 | ||
943 | static int dao_get_spos(void *blk, unsigned int *spos) | |
944 | { | |
945 | *spos = ((struct dao_ctrl_blk *)blk)->spos; | |
946 | return 0; | |
947 | } | |
948 | ||
949 | static int dao_get_ctrl_blk(void **rblk) | |
950 | { | |
951 | struct dao_ctrl_blk *blk; | |
952 | ||
953 | *rblk = NULL; | |
954 | blk = kzalloc(sizeof(*blk), GFP_KERNEL); | |
35ebf6e7 | 955 | if (!blk) |
8cc72361 WYC |
956 | return -ENOMEM; |
957 | ||
958 | *rblk = blk; | |
959 | ||
960 | return 0; | |
961 | } | |
962 | ||
963 | static int dao_put_ctrl_blk(void *blk) | |
964 | { | |
965 | kfree((struct dao_ctrl_blk *)blk); | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
970 | static int daio_mgr_enb_dai(void *blk, unsigned int idx) | |
971 | { | |
972 | struct daio_mgr_ctrl_blk *ctl = blk; | |
973 | ||
974 | if (idx < 4) { | |
975 | /* S/PDIF input */ | |
976 | set_field(&ctl->spictl, SPICTL_EN << (idx*8), 1); | |
977 | ctl->dirty.bf.spictl |= (0x1 << idx); | |
978 | } else { | |
979 | /* I2S input */ | |
980 | idx %= 4; | |
981 | set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 1); | |
982 | ctl->dirty.bf.i2sictl |= (0x1 << idx); | |
983 | } | |
984 | return 0; | |
985 | } | |
986 | ||
987 | static int daio_mgr_dsb_dai(void *blk, unsigned int idx) | |
988 | { | |
989 | struct daio_mgr_ctrl_blk *ctl = blk; | |
990 | ||
991 | if (idx < 4) { | |
992 | /* S/PDIF input */ | |
993 | set_field(&ctl->spictl, SPICTL_EN << (idx*8), 0); | |
994 | ctl->dirty.bf.spictl |= (0x1 << idx); | |
995 | } else { | |
996 | /* I2S input */ | |
997 | idx %= 4; | |
998 | set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 0); | |
999 | ctl->dirty.bf.i2sictl |= (0x1 << idx); | |
1000 | } | |
1001 | return 0; | |
1002 | } | |
1003 | ||
1004 | static int daio_mgr_enb_dao(void *blk, unsigned int idx) | |
1005 | { | |
1006 | struct daio_mgr_ctrl_blk *ctl = blk; | |
1007 | ||
1008 | if (idx < 4) { | |
1009 | /* S/PDIF output */ | |
1010 | set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 1); | |
1011 | ctl->dirty.bf.spoctl |= (0x1 << idx); | |
1012 | } else { | |
1013 | /* I2S output */ | |
1014 | idx %= 4; | |
1015 | set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 1); | |
1016 | ctl->dirty.bf.i2soctl |= (0x1 << idx); | |
1017 | } | |
1018 | return 0; | |
1019 | } | |
1020 | ||
1021 | static int daio_mgr_dsb_dao(void *blk, unsigned int idx) | |
1022 | { | |
1023 | struct daio_mgr_ctrl_blk *ctl = blk; | |
1024 | ||
1025 | if (idx < 4) { | |
1026 | /* S/PDIF output */ | |
1027 | set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 0); | |
1028 | ctl->dirty.bf.spoctl |= (0x1 << idx); | |
1029 | } else { | |
1030 | /* I2S output */ | |
1031 | idx %= 4; | |
1032 | set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 0); | |
1033 | ctl->dirty.bf.i2soctl |= (0x1 << idx); | |
1034 | } | |
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf) | |
1039 | { | |
1040 | struct daio_mgr_ctrl_blk *ctl = blk; | |
1041 | ||
1042 | if (idx < 4) { | |
1043 | /* S/PDIF output */ | |
1044 | switch ((conf & 0x7)) { | |
1045 | case 0: | |
1046 | set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 3); | |
1047 | break; /* CDIF */ | |
1048 | case 1: | |
1049 | set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 0); | |
1050 | break; | |
1051 | case 2: | |
1052 | set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 1); | |
1053 | break; | |
1054 | case 4: | |
1055 | set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 2); | |
1056 | break; | |
1057 | default: | |
1058 | break; | |
1059 | } | |
1060 | set_field(&ctl->spoctl, SPOCTL_LIV << (idx*8), | |
1061 | (conf >> 4) & 0x1); /* Non-audio */ | |
1062 | set_field(&ctl->spoctl, SPOCTL_RIV << (idx*8), | |
1063 | (conf >> 4) & 0x1); /* Non-audio */ | |
1064 | set_field(&ctl->spoctl, SPOCTL_OS << (idx*8), | |
1065 | ((conf >> 3) & 0x1) ? 2 : 2); /* Raw */ | |
1066 | ||
1067 | ctl->dirty.bf.spoctl |= (0x1 << idx); | |
1068 | } else { | |
1069 | /* I2S output */ | |
1070 | /*idx %= 4; */ | |
1071 | } | |
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | static int daio_mgr_set_imaparc(void *blk, unsigned int slot) | |
1076 | { | |
1077 | struct daio_mgr_ctrl_blk *ctl = blk; | |
1078 | ||
1079 | set_field(&ctl->daoimap.aim, AIM_ARC, slot); | |
1080 | ctl->dirty.bf.daoimap = 1; | |
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | static int daio_mgr_set_imapnxt(void *blk, unsigned int next) | |
1085 | { | |
1086 | struct daio_mgr_ctrl_blk *ctl = blk; | |
1087 | ||
1088 | set_field(&ctl->daoimap.aim, AIM_NXT, next); | |
1089 | ctl->dirty.bf.daoimap = 1; | |
1090 | return 0; | |
1091 | } | |
1092 | ||
1093 | static int daio_mgr_set_imapaddr(void *blk, unsigned int addr) | |
1094 | { | |
1095 | struct daio_mgr_ctrl_blk *ctl = blk; | |
1096 | ||
1097 | ctl->daoimap.idx = addr; | |
1098 | ctl->dirty.bf.daoimap = 1; | |
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | static int daio_mgr_commit_write(struct hw *hw, void *blk) | |
1103 | { | |
1104 | struct daio_mgr_ctrl_blk *ctl = blk; | |
514eef9c | 1105 | int i; |
8cc72361 WYC |
1106 | |
1107 | if (ctl->dirty.bf.i2sictl || ctl->dirty.bf.i2soctl) { | |
1108 | for (i = 0; i < 4; i++) { | |
1109 | if ((ctl->dirty.bf.i2sictl & (0x1 << i))) | |
1110 | ctl->dirty.bf.i2sictl &= ~(0x1 << i); | |
1111 | ||
1112 | if ((ctl->dirty.bf.i2soctl & (0x1 << i))) | |
1113 | ctl->dirty.bf.i2soctl &= ~(0x1 << i); | |
1114 | } | |
1115 | hw_write_20kx(hw, I2SCTL, ctl->i2sctl); | |
1116 | mdelay(1); | |
1117 | } | |
1118 | if (ctl->dirty.bf.spoctl) { | |
1119 | for (i = 0; i < 4; i++) { | |
1120 | if ((ctl->dirty.bf.spoctl & (0x1 << i))) | |
1121 | ctl->dirty.bf.spoctl &= ~(0x1 << i); | |
1122 | } | |
1123 | hw_write_20kx(hw, SPOCTL, ctl->spoctl); | |
1124 | mdelay(1); | |
1125 | } | |
1126 | if (ctl->dirty.bf.spictl) { | |
1127 | for (i = 0; i < 4; i++) { | |
1128 | if ((ctl->dirty.bf.spictl & (0x1 << i))) | |
1129 | ctl->dirty.bf.spictl &= ~(0x1 << i); | |
1130 | } | |
1131 | hw_write_20kx(hw, SPICTL, ctl->spictl); | |
1132 | mdelay(1); | |
1133 | } | |
1134 | if (ctl->dirty.bf.daoimap) { | |
1135 | hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4, | |
1136 | ctl->daoimap.aim); | |
1137 | ctl->dirty.bf.daoimap = 0; | |
1138 | } | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
1143 | static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk) | |
1144 | { | |
1145 | struct daio_mgr_ctrl_blk *blk; | |
1146 | ||
1147 | *rblk = NULL; | |
1148 | blk = kzalloc(sizeof(*blk), GFP_KERNEL); | |
35ebf6e7 | 1149 | if (!blk) |
8cc72361 WYC |
1150 | return -ENOMEM; |
1151 | ||
1152 | blk->i2sctl = hw_read_20kx(hw, I2SCTL); | |
1153 | blk->spoctl = hw_read_20kx(hw, SPOCTL); | |
1154 | blk->spictl = hw_read_20kx(hw, SPICTL); | |
1155 | ||
1156 | *rblk = blk; | |
1157 | ||
1158 | return 0; | |
1159 | } | |
1160 | ||
1161 | static int daio_mgr_put_ctrl_blk(void *blk) | |
1162 | { | |
1163 | kfree((struct daio_mgr_ctrl_blk *)blk); | |
1164 | ||
1165 | return 0; | |
1166 | } | |
1167 | ||
b7bbf876 TI |
1168 | /* Timer interrupt */ |
1169 | static int set_timer_irq(struct hw *hw, int enable) | |
1170 | { | |
1171 | hw_write_20kx(hw, GIE, enable ? IT_INT : 0); | |
1172 | return 0; | |
1173 | } | |
1174 | ||
1175 | static int set_timer_tick(struct hw *hw, unsigned int ticks) | |
1176 | { | |
1177 | if (ticks) | |
1178 | ticks |= TIMR_IE | TIMR_IP; | |
1179 | hw_write_20kx(hw, TIMR, ticks); | |
1180 | return 0; | |
1181 | } | |
1182 | ||
54de6bc8 TI |
1183 | static unsigned int get_wc(struct hw *hw) |
1184 | { | |
1185 | return hw_read_20kx(hw, WC); | |
1186 | } | |
1187 | ||
8cc72361 WYC |
1188 | /* Card hardware initialization block */ |
1189 | struct dac_conf { | |
1190 | unsigned int msr; /* master sample rate in rsrs */ | |
1191 | }; | |
1192 | ||
1193 | struct adc_conf { | |
1194 | unsigned int msr; /* master sample rate in rsrs */ | |
1195 | unsigned char input; /* the input source of ADC */ | |
1196 | unsigned char mic20db; /* boost mic by 20db if input is microphone */ | |
1197 | }; | |
1198 | ||
1199 | struct daio_conf { | |
1200 | unsigned int msr; /* master sample rate in rsrs */ | |
1201 | }; | |
1202 | ||
1203 | struct trn_conf { | |
1204 | unsigned long vm_pgt_phys; | |
1205 | }; | |
1206 | ||
1207 | static int hw_daio_init(struct hw *hw, const struct daio_conf *info) | |
1208 | { | |
514eef9c TI |
1209 | u32 i2sorg; |
1210 | u32 spdorg; | |
8cc72361 WYC |
1211 | |
1212 | /* Read I2S CTL. Keep original value. */ | |
1213 | /*i2sorg = hw_read_20kx(hw, I2SCTL);*/ | |
1214 | i2sorg = 0x94040404; /* enable all audio out and I2S-D input */ | |
1215 | /* Program I2S with proper master sample rate and enable | |
1216 | * the correct I2S channel. */ | |
1217 | i2sorg &= 0xfffffffc; | |
1218 | ||
1219 | /* Enable S/PDIF-out-A in fixed 24-bit data | |
1220 | * format and default to 48kHz. */ | |
1221 | /* Disable all before doing any changes. */ | |
1222 | hw_write_20kx(hw, SPOCTL, 0x0); | |
1223 | spdorg = 0x05; | |
1224 | ||
1225 | switch (info->msr) { | |
1226 | case 1: | |
1227 | i2sorg |= 1; | |
1228 | spdorg |= (0x0 << 6); | |
1229 | break; | |
1230 | case 2: | |
1231 | i2sorg |= 2; | |
1232 | spdorg |= (0x1 << 6); | |
1233 | break; | |
1234 | case 4: | |
1235 | i2sorg |= 3; | |
1236 | spdorg |= (0x2 << 6); | |
1237 | break; | |
1238 | default: | |
1239 | i2sorg |= 1; | |
1240 | break; | |
1241 | } | |
1242 | ||
1243 | hw_write_20kx(hw, I2SCTL, i2sorg); | |
1244 | hw_write_20kx(hw, SPOCTL, spdorg); | |
1245 | ||
1246 | /* Enable S/PDIF-in-A in fixed 24-bit data format. */ | |
1247 | /* Disable all before doing any changes. */ | |
1248 | hw_write_20kx(hw, SPICTL, 0x0); | |
1249 | mdelay(1); | |
1250 | spdorg = 0x0a0a0a0a; | |
1251 | hw_write_20kx(hw, SPICTL, spdorg); | |
1252 | mdelay(1); | |
1253 | ||
1254 | return 0; | |
1255 | } | |
1256 | ||
1257 | /* TRANSPORT operations */ | |
1258 | static int hw_trn_init(struct hw *hw, const struct trn_conf *info) | |
1259 | { | |
514eef9c TI |
1260 | u32 trnctl; |
1261 | u32 ptp_phys_low, ptp_phys_high; | |
8cc72361 WYC |
1262 | |
1263 | /* Set up device page table */ | |
1264 | if ((~0UL) == info->vm_pgt_phys) { | |
0cae90a9 SM |
1265 | dev_err(hw->card->dev, |
1266 | "Wrong device page table page address!\n"); | |
8cc72361 WYC |
1267 | return -1; |
1268 | } | |
1269 | ||
1270 | trnctl = 0x13; /* 32-bit, 4k-size page */ | |
cd391e20 TI |
1271 | ptp_phys_low = (u32)info->vm_pgt_phys; |
1272 | ptp_phys_high = upper_32_bits(info->vm_pgt_phys); | |
1273 | if (sizeof(void *) == 8) /* 64bit address */ | |
1274 | trnctl |= (1 << 2); | |
1275 | #if 0 /* Only 4k h/w pages for simplicitiy */ | |
8cc72361 WYC |
1276 | #if PAGE_SIZE == 8192 |
1277 | trnctl |= (1<<5); | |
cd391e20 | 1278 | #endif |
8cc72361 WYC |
1279 | #endif |
1280 | hw_write_20kx(hw, PTPALX, ptp_phys_low); | |
1281 | hw_write_20kx(hw, PTPAHX, ptp_phys_high); | |
1282 | hw_write_20kx(hw, TRNCTL, trnctl); | |
25985edc | 1283 | hw_write_20kx(hw, TRNIS, 0x200c01); /* really needed? */ |
8cc72361 WYC |
1284 | |
1285 | return 0; | |
1286 | } | |
1287 | ||
1288 | /* Card initialization */ | |
1289 | #define GCTL_EAC 0x00000001 | |
1290 | #define GCTL_EAI 0x00000002 | |
1291 | #define GCTL_BEP 0x00000004 | |
1292 | #define GCTL_BES 0x00000008 | |
1293 | #define GCTL_DSP 0x00000010 | |
1294 | #define GCTL_DBP 0x00000020 | |
1295 | #define GCTL_ABP 0x00000040 | |
1296 | #define GCTL_TBP 0x00000080 | |
1297 | #define GCTL_SBP 0x00000100 | |
1298 | #define GCTL_FBP 0x00000200 | |
1299 | #define GCTL_XA 0x00000400 | |
1300 | #define GCTL_ET 0x00000800 | |
1301 | #define GCTL_PR 0x00001000 | |
1302 | #define GCTL_MRL 0x00002000 | |
1303 | #define GCTL_SDE 0x00004000 | |
1304 | #define GCTL_SDI 0x00008000 | |
1305 | #define GCTL_SM 0x00010000 | |
1306 | #define GCTL_SR 0x00020000 | |
1307 | #define GCTL_SD 0x00040000 | |
1308 | #define GCTL_SE 0x00080000 | |
1309 | #define GCTL_AID 0x00100000 | |
1310 | ||
1311 | static int hw_pll_init(struct hw *hw, unsigned int rsr) | |
1312 | { | |
1313 | unsigned int pllctl; | |
514eef9c | 1314 | int i; |
8cc72361 WYC |
1315 | |
1316 | pllctl = (48000 == rsr) ? 0x1480a001 : 0x1480a731; | |
1317 | for (i = 0; i < 3; i++) { | |
1318 | if (hw_read_20kx(hw, PLLCTL) == pllctl) | |
1319 | break; | |
1320 | ||
1321 | hw_write_20kx(hw, PLLCTL, pllctl); | |
1322 | mdelay(40); | |
1323 | } | |
1324 | if (i >= 3) { | |
0cae90a9 | 1325 | dev_alert(hw->card->dev, "PLL initialization failed!!!\n"); |
8cc72361 WYC |
1326 | return -EBUSY; |
1327 | } | |
1328 | ||
1329 | return 0; | |
1330 | } | |
1331 | ||
1332 | static int hw_auto_init(struct hw *hw) | |
1333 | { | |
1334 | unsigned int gctl; | |
1335 | int i; | |
1336 | ||
1337 | gctl = hw_read_20kx(hw, GCTL); | |
1338 | set_field(&gctl, GCTL_EAI, 0); | |
1339 | hw_write_20kx(hw, GCTL, gctl); | |
1340 | set_field(&gctl, GCTL_EAI, 1); | |
1341 | hw_write_20kx(hw, GCTL, gctl); | |
1342 | mdelay(10); | |
1343 | for (i = 0; i < 400000; i++) { | |
1344 | gctl = hw_read_20kx(hw, GCTL); | |
1345 | if (get_field(gctl, GCTL_AID)) | |
1346 | break; | |
1347 | } | |
1348 | if (!get_field(gctl, GCTL_AID)) { | |
0cae90a9 | 1349 | dev_alert(hw->card->dev, "Card Auto-init failed!!!\n"); |
8cc72361 WYC |
1350 | return -EBUSY; |
1351 | } | |
1352 | ||
1353 | return 0; | |
1354 | } | |
1355 | ||
1356 | static int i2c_unlock(struct hw *hw) | |
1357 | { | |
1358 | if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) | |
1359 | return 0; | |
1360 | ||
1361 | hw_write_pci(hw, 0xcc, 0x8c); | |
1362 | hw_write_pci(hw, 0xcc, 0x0e); | |
1363 | if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) | |
1364 | return 0; | |
1365 | ||
1366 | hw_write_pci(hw, 0xcc, 0xee); | |
1367 | hw_write_pci(hw, 0xcc, 0xaa); | |
1368 | if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) | |
1369 | return 0; | |
1370 | ||
1371 | return -1; | |
1372 | } | |
1373 | ||
1374 | static void i2c_lock(struct hw *hw) | |
1375 | { | |
1376 | if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa) | |
1377 | hw_write_pci(hw, 0xcc, 0x00); | |
1378 | } | |
1379 | ||
1380 | static void i2c_write(struct hw *hw, u32 device, u32 addr, u32 data) | |
1381 | { | |
514eef9c | 1382 | unsigned int ret; |
8cc72361 WYC |
1383 | |
1384 | do { | |
1385 | ret = hw_read_pci(hw, 0xEC); | |
1386 | } while (!(ret & 0x800000)); | |
1387 | hw_write_pci(hw, 0xE0, device); | |
1388 | hw_write_pci(hw, 0xE4, (data << 8) | (addr & 0xff)); | |
1389 | } | |
1390 | ||
1391 | /* DAC operations */ | |
1392 | ||
1393 | static int hw_reset_dac(struct hw *hw) | |
1394 | { | |
514eef9c TI |
1395 | u32 i; |
1396 | u16 gpioorg; | |
1397 | unsigned int ret; | |
8cc72361 WYC |
1398 | |
1399 | if (i2c_unlock(hw)) | |
1400 | return -1; | |
1401 | ||
1402 | do { | |
1403 | ret = hw_read_pci(hw, 0xEC); | |
1404 | } while (!(ret & 0x800000)); | |
1405 | hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */ | |
1406 | ||
1407 | /* To be effective, need to reset the DAC twice. */ | |
1408 | for (i = 0; i < 2; i++) { | |
1409 | /* set gpio */ | |
1410 | mdelay(100); | |
1411 | gpioorg = (u16)hw_read_20kx(hw, GPIO); | |
1412 | gpioorg &= 0xfffd; | |
1413 | hw_write_20kx(hw, GPIO, gpioorg); | |
1414 | mdelay(1); | |
1415 | hw_write_20kx(hw, GPIO, gpioorg | 0x2); | |
1416 | } | |
1417 | ||
1418 | i2c_write(hw, 0x00180080, 0x01, 0x80); | |
1419 | i2c_write(hw, 0x00180080, 0x02, 0x10); | |
1420 | ||
1421 | i2c_lock(hw); | |
1422 | ||
1423 | return 0; | |
1424 | } | |
1425 | ||
1426 | static int hw_dac_init(struct hw *hw, const struct dac_conf *info) | |
1427 | { | |
514eef9c TI |
1428 | u32 data; |
1429 | u16 gpioorg; | |
514eef9c | 1430 | unsigned int ret; |
8cc72361 | 1431 | |
9470195a | 1432 | if (hw->model == CTSB055X) { |
8cc72361 WYC |
1433 | /* SB055x, unmute outputs */ |
1434 | gpioorg = (u16)hw_read_20kx(hw, GPIO); | |
1435 | gpioorg &= 0xffbf; /* set GPIO6 to low */ | |
1436 | gpioorg |= 2; /* set GPIO1 to high */ | |
1437 | hw_write_20kx(hw, GPIO, gpioorg); | |
1438 | return 0; | |
1439 | } | |
1440 | ||
1441 | /* mute outputs */ | |
1442 | gpioorg = (u16)hw_read_20kx(hw, GPIO); | |
1443 | gpioorg &= 0xffbf; | |
1444 | hw_write_20kx(hw, GPIO, gpioorg); | |
1445 | ||
1446 | hw_reset_dac(hw); | |
1447 | ||
1448 | if (i2c_unlock(hw)) | |
1449 | return -1; | |
1450 | ||
1451 | hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */ | |
1452 | do { | |
1453 | ret = hw_read_pci(hw, 0xEC); | |
1454 | } while (!(ret & 0x800000)); | |
1455 | ||
1456 | switch (info->msr) { | |
1457 | case 1: | |
1458 | data = 0x24; | |
1459 | break; | |
1460 | case 2: | |
1461 | data = 0x25; | |
1462 | break; | |
1463 | case 4: | |
1464 | data = 0x26; | |
1465 | break; | |
1466 | default: | |
1467 | data = 0x24; | |
1468 | break; | |
1469 | } | |
1470 | ||
1471 | i2c_write(hw, 0x00180080, 0x06, data); | |
1472 | i2c_write(hw, 0x00180080, 0x09, data); | |
1473 | i2c_write(hw, 0x00180080, 0x0c, data); | |
1474 | i2c_write(hw, 0x00180080, 0x0f, data); | |
1475 | ||
1476 | i2c_lock(hw); | |
1477 | ||
1478 | /* unmute outputs */ | |
1479 | gpioorg = (u16)hw_read_20kx(hw, GPIO); | |
1480 | gpioorg = gpioorg | 0x40; | |
1481 | hw_write_20kx(hw, GPIO, gpioorg); | |
1482 | ||
1483 | return 0; | |
1484 | } | |
1485 | ||
1486 | /* ADC operations */ | |
1487 | ||
1488 | static int is_adc_input_selected_SB055x(struct hw *hw, enum ADCSRC type) | |
1489 | { | |
514eef9c | 1490 | return 0; |
8cc72361 WYC |
1491 | } |
1492 | ||
1493 | static int is_adc_input_selected_SBx(struct hw *hw, enum ADCSRC type) | |
1494 | { | |
514eef9c | 1495 | u32 data; |
8cc72361 WYC |
1496 | |
1497 | data = hw_read_20kx(hw, GPIO); | |
1498 | switch (type) { | |
1499 | case ADC_MICIN: | |
1500 | data = ((data & (0x1<<7)) && (data & (0x1<<8))); | |
1501 | break; | |
1502 | case ADC_LINEIN: | |
1503 | data = (!(data & (0x1<<7)) && (data & (0x1<<8))); | |
1504 | break; | |
1505 | case ADC_NONE: /* Digital I/O */ | |
1506 | data = (!(data & (0x1<<8))); | |
1507 | break; | |
1508 | default: | |
1509 | data = 0; | |
1510 | } | |
1511 | return data; | |
1512 | } | |
1513 | ||
1514 | static int is_adc_input_selected_hendrix(struct hw *hw, enum ADCSRC type) | |
1515 | { | |
514eef9c | 1516 | u32 data; |
8cc72361 WYC |
1517 | |
1518 | data = hw_read_20kx(hw, GPIO); | |
1519 | switch (type) { | |
1520 | case ADC_MICIN: | |
1521 | data = (data & (0x1 << 7)) ? 1 : 0; | |
1522 | break; | |
1523 | case ADC_LINEIN: | |
1524 | data = (data & (0x1 << 7)) ? 0 : 1; | |
1525 | break; | |
1526 | default: | |
1527 | data = 0; | |
1528 | } | |
1529 | return data; | |
1530 | } | |
1531 | ||
1532 | static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type) | |
1533 | { | |
9470195a TI |
1534 | switch (hw->model) { |
1535 | case CTSB055X: | |
8cc72361 | 1536 | return is_adc_input_selected_SB055x(hw, type); |
9470195a | 1537 | case CTSB073X: |
8cc72361 | 1538 | return is_adc_input_selected_hendrix(hw, type); |
09521d2e | 1539 | case CTUAA: |
8cc72361 | 1540 | return is_adc_input_selected_hendrix(hw, type); |
9470195a | 1541 | default: |
8cc72361 WYC |
1542 | return is_adc_input_selected_SBx(hw, type); |
1543 | } | |
1544 | } | |
1545 | ||
1546 | static int | |
1547 | adc_input_select_SB055x(struct hw *hw, enum ADCSRC type, unsigned char boost) | |
1548 | { | |
514eef9c | 1549 | u32 data; |
8cc72361 WYC |
1550 | |
1551 | /* | |
1552 | * check and set the following GPIO bits accordingly | |
1553 | * ADC_Gain = GPIO2 | |
1554 | * DRM_off = GPIO3 | |
1555 | * Mic_Pwr_on = GPIO7 | |
1556 | * Digital_IO_Sel = GPIO8 | |
1557 | * Mic_Sw = GPIO9 | |
1558 | * Aux/MicLine_Sw = GPIO12 | |
1559 | */ | |
1560 | data = hw_read_20kx(hw, GPIO); | |
1561 | data &= 0xec73; | |
1562 | switch (type) { | |
1563 | case ADC_MICIN: | |
1564 | data |= (0x1<<7) | (0x1<<8) | (0x1<<9) ; | |
1565 | data |= boost ? (0x1<<2) : 0; | |
1566 | break; | |
1567 | case ADC_LINEIN: | |
1568 | data |= (0x1<<8); | |
1569 | break; | |
1570 | case ADC_AUX: | |
1571 | data |= (0x1<<8) | (0x1<<12); | |
1572 | break; | |
1573 | case ADC_NONE: | |
1574 | data |= (0x1<<12); /* set to digital */ | |
1575 | break; | |
1576 | default: | |
1577 | return -1; | |
1578 | } | |
1579 | ||
1580 | hw_write_20kx(hw, GPIO, data); | |
1581 | ||
1582 | return 0; | |
1583 | } | |
1584 | ||
1585 | ||
1586 | static int | |
1587 | adc_input_select_SBx(struct hw *hw, enum ADCSRC type, unsigned char boost) | |
1588 | { | |
514eef9c TI |
1589 | u32 data; |
1590 | u32 i2c_data; | |
1591 | unsigned int ret; | |
8cc72361 WYC |
1592 | |
1593 | if (i2c_unlock(hw)) | |
1594 | return -1; | |
1595 | ||
1596 | do { | |
1597 | ret = hw_read_pci(hw, 0xEC); | |
1598 | } while (!(ret & 0x800000)); /* i2c ready poll */ | |
1599 | /* set i2c access mode as Direct Control */ | |
1600 | hw_write_pci(hw, 0xEC, 0x05); | |
1601 | ||
1602 | data = hw_read_20kx(hw, GPIO); | |
1603 | switch (type) { | |
1604 | case ADC_MICIN: | |
1605 | data |= ((0x1 << 7) | (0x1 << 8)); | |
1606 | i2c_data = 0x1; /* Mic-in */ | |
1607 | break; | |
1608 | case ADC_LINEIN: | |
1609 | data &= ~(0x1 << 7); | |
1610 | data |= (0x1 << 8); | |
1611 | i2c_data = 0x2; /* Line-in */ | |
1612 | break; | |
1613 | case ADC_NONE: | |
1614 | data &= ~(0x1 << 8); | |
1615 | i2c_data = 0x0; /* set to Digital */ | |
1616 | break; | |
1617 | default: | |
1618 | i2c_lock(hw); | |
1619 | return -1; | |
1620 | } | |
1621 | hw_write_20kx(hw, GPIO, data); | |
1622 | i2c_write(hw, 0x001a0080, 0x2a, i2c_data); | |
1623 | if (boost) { | |
1624 | i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */ | |
1625 | i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */ | |
1626 | } else { | |
1627 | i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */ | |
1628 | i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */ | |
1629 | } | |
1630 | ||
1631 | i2c_lock(hw); | |
1632 | ||
1633 | return 0; | |
1634 | } | |
1635 | ||
1636 | static int | |
1637 | adc_input_select_hendrix(struct hw *hw, enum ADCSRC type, unsigned char boost) | |
1638 | { | |
514eef9c TI |
1639 | u32 data; |
1640 | u32 i2c_data; | |
1641 | unsigned int ret; | |
8cc72361 WYC |
1642 | |
1643 | if (i2c_unlock(hw)) | |
1644 | return -1; | |
1645 | ||
1646 | do { | |
1647 | ret = hw_read_pci(hw, 0xEC); | |
1648 | } while (!(ret & 0x800000)); /* i2c ready poll */ | |
1649 | /* set i2c access mode as Direct Control */ | |
1650 | hw_write_pci(hw, 0xEC, 0x05); | |
1651 | ||
1652 | data = hw_read_20kx(hw, GPIO); | |
1653 | switch (type) { | |
1654 | case ADC_MICIN: | |
1655 | data |= (0x1 << 7); | |
1656 | i2c_data = 0x1; /* Mic-in */ | |
1657 | break; | |
1658 | case ADC_LINEIN: | |
1659 | data &= ~(0x1 << 7); | |
1660 | i2c_data = 0x2; /* Line-in */ | |
1661 | break; | |
1662 | default: | |
1663 | i2c_lock(hw); | |
1664 | return -1; | |
1665 | } | |
1666 | hw_write_20kx(hw, GPIO, data); | |
1667 | i2c_write(hw, 0x001a0080, 0x2a, i2c_data); | |
1668 | if (boost) { | |
1669 | i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */ | |
1670 | i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */ | |
1671 | } else { | |
1672 | i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */ | |
1673 | i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */ | |
1674 | } | |
1675 | ||
1676 | i2c_lock(hw); | |
1677 | ||
1678 | return 0; | |
1679 | } | |
1680 | ||
1681 | static int hw_adc_input_select(struct hw *hw, enum ADCSRC type) | |
1682 | { | |
9470195a TI |
1683 | int state = type == ADC_MICIN; |
1684 | ||
1685 | switch (hw->model) { | |
1686 | case CTSB055X: | |
1687 | return adc_input_select_SB055x(hw, type, state); | |
1688 | case CTSB073X: | |
1689 | return adc_input_select_hendrix(hw, type, state); | |
09521d2e | 1690 | case CTUAA: |
9470195a TI |
1691 | return adc_input_select_hendrix(hw, type, state); |
1692 | default: | |
1693 | return adc_input_select_SBx(hw, type, state); | |
8cc72361 WYC |
1694 | } |
1695 | } | |
1696 | ||
1697 | static int adc_init_SB055x(struct hw *hw, int input, int mic20db) | |
1698 | { | |
1699 | return adc_input_select_SB055x(hw, input, mic20db); | |
1700 | } | |
1701 | ||
1702 | static int adc_init_SBx(struct hw *hw, int input, int mic20db) | |
1703 | { | |
1704 | u16 gpioorg; | |
1705 | u16 input_source; | |
514eef9c TI |
1706 | u32 adcdata; |
1707 | unsigned int ret; | |
8cc72361 WYC |
1708 | |
1709 | input_source = 0x100; /* default to analog */ | |
1710 | switch (input) { | |
1711 | case ADC_MICIN: | |
1712 | adcdata = 0x1; | |
1713 | input_source = 0x180; /* set GPIO7 to select Mic */ | |
1714 | break; | |
1715 | case ADC_LINEIN: | |
1716 | adcdata = 0x2; | |
1717 | break; | |
1718 | case ADC_VIDEO: | |
1719 | adcdata = 0x4; | |
1720 | break; | |
1721 | case ADC_AUX: | |
1722 | adcdata = 0x8; | |
1723 | break; | |
1724 | case ADC_NONE: | |
1725 | adcdata = 0x0; | |
1726 | input_source = 0x0; /* set to Digital */ | |
1727 | break; | |
1728 | default: | |
514eef9c | 1729 | adcdata = 0x0; |
8cc72361 WYC |
1730 | break; |
1731 | } | |
1732 | ||
1733 | if (i2c_unlock(hw)) | |
1734 | return -1; | |
1735 | ||
1736 | do { | |
1737 | ret = hw_read_pci(hw, 0xEC); | |
1738 | } while (!(ret & 0x800000)); /* i2c ready poll */ | |
1739 | hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */ | |
1740 | ||
1741 | i2c_write(hw, 0x001a0080, 0x0e, 0x08); | |
1742 | i2c_write(hw, 0x001a0080, 0x18, 0x0a); | |
1743 | i2c_write(hw, 0x001a0080, 0x28, 0x86); | |
1744 | i2c_write(hw, 0x001a0080, 0x2a, adcdata); | |
1745 | ||
1746 | if (mic20db) { | |
1747 | i2c_write(hw, 0x001a0080, 0x1c, 0xf7); | |
1748 | i2c_write(hw, 0x001a0080, 0x1e, 0xf7); | |
1749 | } else { | |
1750 | i2c_write(hw, 0x001a0080, 0x1c, 0xcf); | |
1751 | i2c_write(hw, 0x001a0080, 0x1e, 0xcf); | |
1752 | } | |
1753 | ||
1754 | if (!(hw_read_20kx(hw, ID0) & 0x100)) | |
1755 | i2c_write(hw, 0x001a0080, 0x16, 0x26); | |
1756 | ||
1757 | i2c_lock(hw); | |
1758 | ||
1759 | gpioorg = (u16)hw_read_20kx(hw, GPIO); | |
1760 | gpioorg &= 0xfe7f; | |
1761 | gpioorg |= input_source; | |
1762 | hw_write_20kx(hw, GPIO, gpioorg); | |
1763 | ||
1764 | return 0; | |
1765 | } | |
1766 | ||
1767 | static int hw_adc_init(struct hw *hw, const struct adc_conf *info) | |
1768 | { | |
9470195a TI |
1769 | if (hw->model == CTSB055X) |
1770 | return adc_init_SB055x(hw, info->input, info->mic20db); | |
1771 | else | |
1772 | return adc_init_SBx(hw, info->input, info->mic20db); | |
8cc72361 WYC |
1773 | } |
1774 | ||
b028b818 | 1775 | static struct capabilities hw_capabilities(struct hw *hw) |
8cc72361 | 1776 | { |
b028b818 | 1777 | struct capabilities cap; |
55309216 | 1778 | |
b028b818 HB |
1779 | /* SB073x and Vista compatible cards have no digit IO switch */ |
1780 | cap.digit_io_switch = !(hw->model == CTSB073X || hw->model == CTUAA); | |
1781 | cap.dedicated_mic = 0; | |
1782 | cap.output_switch = 0; | |
1783 | cap.mic_source_switch = 0; | |
55309216 | 1784 | |
b028b818 | 1785 | return cap; |
55309216 HB |
1786 | } |
1787 | ||
42a0b318 TI |
1788 | #define CTLBITS(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d)) |
1789 | ||
8cc72361 WYC |
1790 | #define UAA_CFG_PWRSTATUS 0x44 |
1791 | #define UAA_CFG_SPACE_FLAG 0xA0 | |
1792 | #define UAA_CORE_CHANGE 0x3FFC | |
1793 | static int uaa_to_xfi(struct pci_dev *pci) | |
1794 | { | |
1795 | unsigned int bar0, bar1, bar2, bar3, bar4, bar5; | |
1796 | unsigned int cmd, irq, cl_size, l_timer, pwr; | |
514eef9c | 1797 | unsigned int is_uaa; |
8cc72361 WYC |
1798 | unsigned int data[4] = {0}; |
1799 | unsigned int io_base; | |
7a7686bd | 1800 | void __iomem *mem_base; |
514eef9c | 1801 | int i; |
42a0b318 TI |
1802 | const u32 CTLX = CTLBITS('C', 'T', 'L', 'X'); |
1803 | const u32 CTL_ = CTLBITS('C', 'T', 'L', '-'); | |
1804 | const u32 CTLF = CTLBITS('C', 'T', 'L', 'F'); | |
1805 | const u32 CTLi = CTLBITS('C', 'T', 'L', 'i'); | |
1806 | const u32 CTLA = CTLBITS('C', 'T', 'L', 'A'); | |
1807 | const u32 CTLZ = CTLBITS('C', 'T', 'L', 'Z'); | |
1808 | const u32 CTLL = CTLBITS('C', 'T', 'L', 'L'); | |
8cc72361 WYC |
1809 | |
1810 | /* By default, Hendrix card UAA Bar0 should be using memory... */ | |
1811 | io_base = pci_resource_start(pci, 0); | |
1812 | mem_base = ioremap(io_base, pci_resource_len(pci, 0)); | |
35ebf6e7 | 1813 | if (!mem_base) |
8cc72361 WYC |
1814 | return -ENOENT; |
1815 | ||
8cc72361 WYC |
1816 | /* Read current mode from Mode Change Register */ |
1817 | for (i = 0; i < 4; i++) | |
1818 | data[i] = readl(mem_base + UAA_CORE_CHANGE); | |
1819 | ||
1820 | /* Determine current mode... */ | |
1821 | if (data[0] == CTLA) { | |
1822 | is_uaa = ((data[1] == CTLZ && data[2] == CTLL | |
1823 | && data[3] == CTLA) || (data[1] == CTLA | |
1824 | && data[2] == CTLZ && data[3] == CTLL)); | |
1825 | } else if (data[0] == CTLZ) { | |
1826 | is_uaa = (data[1] == CTLL | |
1827 | && data[2] == CTLA && data[3] == CTLA); | |
1828 | } else if (data[0] == CTLL) { | |
1829 | is_uaa = (data[1] == CTLA | |
1830 | && data[2] == CTLA && data[3] == CTLZ); | |
1831 | } else { | |
1832 | is_uaa = 0; | |
1833 | } | |
1834 | ||
1835 | if (!is_uaa) { | |
1836 | /* Not in UAA mode currently. Return directly. */ | |
1837 | iounmap(mem_base); | |
1838 | return 0; | |
1839 | } | |
1840 | ||
1841 | pci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0); | |
1842 | pci_read_config_dword(pci, PCI_BASE_ADDRESS_1, &bar1); | |
1843 | pci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2); | |
1844 | pci_read_config_dword(pci, PCI_BASE_ADDRESS_3, &bar3); | |
1845 | pci_read_config_dword(pci, PCI_BASE_ADDRESS_4, &bar4); | |
1846 | pci_read_config_dword(pci, PCI_BASE_ADDRESS_5, &bar5); | |
1847 | pci_read_config_dword(pci, PCI_INTERRUPT_LINE, &irq); | |
1848 | pci_read_config_dword(pci, PCI_CACHE_LINE_SIZE, &cl_size); | |
1849 | pci_read_config_dword(pci, PCI_LATENCY_TIMER, &l_timer); | |
1850 | pci_read_config_dword(pci, UAA_CFG_PWRSTATUS, &pwr); | |
1851 | pci_read_config_dword(pci, PCI_COMMAND, &cmd); | |
1852 | ||
1853 | /* Set up X-Fi core PCI configuration space. */ | |
1854 | /* Switch to X-Fi config space with BAR0 exposed. */ | |
1855 | pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x87654321); | |
1856 | /* Copy UAA's BAR5 into X-Fi BAR0 */ | |
1857 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5); | |
1858 | /* Switch to X-Fi config space without BAR0 exposed. */ | |
1859 | pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x12345678); | |
1860 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, bar1); | |
1861 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2); | |
1862 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_3, bar3); | |
1863 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_4, bar4); | |
1864 | pci_write_config_dword(pci, PCI_INTERRUPT_LINE, irq); | |
1865 | pci_write_config_dword(pci, PCI_CACHE_LINE_SIZE, cl_size); | |
1866 | pci_write_config_dword(pci, PCI_LATENCY_TIMER, l_timer); | |
1867 | pci_write_config_dword(pci, UAA_CFG_PWRSTATUS, pwr); | |
1868 | pci_write_config_dword(pci, PCI_COMMAND, cmd); | |
1869 | ||
1870 | /* Switch to X-Fi mode */ | |
1871 | writel(CTLX, (mem_base + UAA_CORE_CHANGE)); | |
1872 | writel(CTL_, (mem_base + UAA_CORE_CHANGE)); | |
1873 | writel(CTLF, (mem_base + UAA_CORE_CHANGE)); | |
1874 | writel(CTLi, (mem_base + UAA_CORE_CHANGE)); | |
1875 | ||
1876 | iounmap(mem_base); | |
1877 | ||
1878 | return 0; | |
1879 | } | |
1880 | ||
b7bbf876 TI |
1881 | static irqreturn_t ct_20k1_interrupt(int irq, void *dev_id) |
1882 | { | |
1883 | struct hw *hw = dev_id; | |
1884 | unsigned int status; | |
1885 | ||
1886 | status = hw_read_20kx(hw, GIP); | |
1887 | if (!status) | |
1888 | return IRQ_NONE; | |
1889 | ||
1890 | if (hw->irq_callback) | |
1891 | hw->irq_callback(hw->irq_callback_data, status); | |
1892 | ||
1893 | hw_write_20kx(hw, GIP, status); | |
1894 | return IRQ_HANDLED; | |
1895 | } | |
1896 | ||
8cc72361 WYC |
1897 | static int hw_card_start(struct hw *hw) |
1898 | { | |
514eef9c | 1899 | int err; |
8cc72361 | 1900 | struct pci_dev *pci = hw->pci; |
15c75b09 | 1901 | const unsigned int dma_bits = BITS_PER_LONG; |
8cc72361 WYC |
1902 | |
1903 | err = pci_enable_device(pci); | |
1904 | if (err < 0) | |
1905 | return err; | |
1906 | ||
1907 | /* Set DMA transfer mask */ | |
f363a066 | 1908 | if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { |
15c75b09 TI |
1909 | dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); |
1910 | } else { | |
1911 | dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); | |
1912 | dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); | |
8cc72361 WYC |
1913 | } |
1914 | ||
29959a09 WYC |
1915 | if (!hw->io_base) { |
1916 | err = pci_request_regions(pci, "XFi"); | |
1917 | if (err < 0) | |
1918 | goto error1; | |
1919 | ||
1920 | if (hw->model == CTUAA) | |
1921 | hw->io_base = pci_resource_start(pci, 5); | |
1922 | else | |
1923 | hw->io_base = pci_resource_start(pci, 0); | |
1924 | ||
1925 | } | |
8cc72361 WYC |
1926 | |
1927 | /* Switch to X-Fi mode from UAA mode if neeeded */ | |
09521d2e | 1928 | if (hw->model == CTUAA) { |
8cc72361 WYC |
1929 | err = uaa_to_xfi(pci); |
1930 | if (err) | |
1931 | goto error2; | |
1932 | ||
8cc72361 WYC |
1933 | } |
1934 | ||
29959a09 WYC |
1935 | if (hw->irq < 0) { |
1936 | err = request_irq(pci->irq, ct_20k1_interrupt, IRQF_SHARED, | |
934c2b6d | 1937 | KBUILD_MODNAME, hw); |
29959a09 | 1938 | if (err < 0) { |
0cae90a9 SM |
1939 | dev_err(hw->card->dev, |
1940 | "XFi: Cannot get irq %d\n", pci->irq); | |
29959a09 WYC |
1941 | goto error2; |
1942 | } | |
1943 | hw->irq = pci->irq; | |
8cc72361 | 1944 | } |
8cc72361 WYC |
1945 | |
1946 | pci_set_master(pci); | |
1947 | ||
1948 | return 0; | |
1949 | ||
1950 | error2: | |
1951 | pci_release_regions(pci); | |
1952 | hw->io_base = 0; | |
1953 | error1: | |
1954 | pci_disable_device(pci); | |
1955 | return err; | |
1956 | } | |
1957 | ||
1958 | static int hw_card_stop(struct hw *hw) | |
1959 | { | |
29959a09 WYC |
1960 | unsigned int data; |
1961 | ||
1962 | /* disable transport bus master and queueing of request */ | |
1963 | hw_write_20kx(hw, TRNCTL, 0x00); | |
1964 | ||
1965 | /* disable pll */ | |
1966 | data = hw_read_20kx(hw, PLLCTL); | |
1967 | hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12)))); | |
1968 | ||
8cc72361 | 1969 | /* TODO: Disable interrupt and so on... */ |
b7bbf876 TI |
1970 | if (hw->irq >= 0) |
1971 | synchronize_irq(hw->irq); | |
8cc72361 WYC |
1972 | return 0; |
1973 | } | |
1974 | ||
1975 | static int hw_card_shutdown(struct hw *hw) | |
1976 | { | |
1977 | if (hw->irq >= 0) | |
1978 | free_irq(hw->irq, hw); | |
1979 | ||
1980 | hw->irq = -1; | |
ff6defa6 | 1981 | iounmap(hw->mem_base); |
7a7686bd | 1982 | hw->mem_base = NULL; |
8cc72361 WYC |
1983 | |
1984 | if (hw->io_base) | |
1985 | pci_release_regions(hw->pci); | |
1986 | ||
1987 | hw->io_base = 0; | |
1988 | ||
1989 | pci_disable_device(hw->pci); | |
1990 | ||
1991 | return 0; | |
1992 | } | |
1993 | ||
1994 | static int hw_card_init(struct hw *hw, struct card_conf *info) | |
1995 | { | |
1996 | int err; | |
1997 | unsigned int gctl; | |
514eef9c | 1998 | u32 data; |
8cc72361 WYC |
1999 | struct dac_conf dac_info = {0}; |
2000 | struct adc_conf adc_info = {0}; | |
2001 | struct daio_conf daio_info = {0}; | |
2002 | struct trn_conf trn_info = {0}; | |
2003 | ||
2004 | /* Get PCI io port base address and do Hendrix switch if needed. */ | |
29959a09 WYC |
2005 | err = hw_card_start(hw); |
2006 | if (err) | |
2007 | return err; | |
8cc72361 WYC |
2008 | |
2009 | /* PLL init */ | |
2010 | err = hw_pll_init(hw, info->rsr); | |
2011 | if (err < 0) | |
2012 | return err; | |
2013 | ||
2014 | /* kick off auto-init */ | |
2015 | err = hw_auto_init(hw); | |
2016 | if (err < 0) | |
2017 | return err; | |
2018 | ||
2019 | /* Enable audio ring */ | |
2020 | gctl = hw_read_20kx(hw, GCTL); | |
2021 | set_field(&gctl, GCTL_EAC, 1); | |
2022 | set_field(&gctl, GCTL_DBP, 1); | |
2023 | set_field(&gctl, GCTL_TBP, 1); | |
2024 | set_field(&gctl, GCTL_FBP, 1); | |
2025 | set_field(&gctl, GCTL_ET, 1); | |
2026 | hw_write_20kx(hw, GCTL, gctl); | |
2027 | mdelay(10); | |
2028 | ||
2029 | /* Reset all global pending interrupts */ | |
2030 | hw_write_20kx(hw, GIE, 0); | |
2031 | /* Reset all SRC pending interrupts */ | |
2032 | hw_write_20kx(hw, SRCIP, 0); | |
2033 | mdelay(30); | |
2034 | ||
8cc72361 | 2035 | /* Detect the card ID and configure GPIO accordingly. */ |
9470195a TI |
2036 | switch (hw->model) { |
2037 | case CTSB055X: | |
8cc72361 | 2038 | hw_write_20kx(hw, GPIOCTL, 0x13fe); |
9470195a TI |
2039 | break; |
2040 | case CTSB073X: | |
8cc72361 | 2041 | hw_write_20kx(hw, GPIOCTL, 0x00e6); |
9470195a | 2042 | break; |
09521d2e | 2043 | case CTUAA: |
8cc72361 | 2044 | hw_write_20kx(hw, GPIOCTL, 0x00c2); |
9470195a TI |
2045 | break; |
2046 | default: | |
8cc72361 | 2047 | hw_write_20kx(hw, GPIOCTL, 0x01e6); |
9470195a | 2048 | break; |
8cc72361 WYC |
2049 | } |
2050 | ||
2051 | trn_info.vm_pgt_phys = info->vm_pgt_phys; | |
2052 | err = hw_trn_init(hw, &trn_info); | |
2053 | if (err < 0) | |
2054 | return err; | |
2055 | ||
2056 | daio_info.msr = info->msr; | |
2057 | err = hw_daio_init(hw, &daio_info); | |
2058 | if (err < 0) | |
2059 | return err; | |
2060 | ||
2061 | dac_info.msr = info->msr; | |
2062 | err = hw_dac_init(hw, &dac_info); | |
2063 | if (err < 0) | |
2064 | return err; | |
2065 | ||
2066 | adc_info.msr = info->msr; | |
2067 | adc_info.input = ADC_LINEIN; | |
2068 | adc_info.mic20db = 0; | |
2069 | err = hw_adc_init(hw, &adc_info); | |
2070 | if (err < 0) | |
2071 | return err; | |
2072 | ||
2073 | data = hw_read_20kx(hw, SRCMCTL); | |
2074 | data |= 0x1; /* Enables input from the audio ring */ | |
2075 | hw_write_20kx(hw, SRCMCTL, data); | |
2076 | ||
2077 | return 0; | |
2078 | } | |
2079 | ||
c7561cd8 | 2080 | #ifdef CONFIG_PM_SLEEP |
68cb2b55 | 2081 | static int hw_suspend(struct hw *hw) |
29959a09 WYC |
2082 | { |
2083 | struct pci_dev *pci = hw->pci; | |
2084 | ||
2085 | hw_card_stop(hw); | |
2086 | ||
2087 | if (hw->model == CTUAA) { | |
2088 | /* Switch to UAA config space. */ | |
2089 | pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x0); | |
2090 | } | |
2091 | ||
29959a09 WYC |
2092 | return 0; |
2093 | } | |
2094 | ||
2095 | static int hw_resume(struct hw *hw, struct card_conf *info) | |
2096 | { | |
29959a09 WYC |
2097 | /* Re-initialize card hardware. */ |
2098 | return hw_card_init(hw, info); | |
2099 | } | |
2100 | #endif | |
2101 | ||
8cc72361 WYC |
2102 | static u32 hw_read_20kx(struct hw *hw, u32 reg) |
2103 | { | |
2104 | u32 value; | |
2105 | unsigned long flags; | |
2106 | ||
2107 | spin_lock_irqsave( | |
2108 | &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); | |
2109 | outl(reg, hw->io_base + 0x0); | |
2110 | value = inl(hw->io_base + 0x4); | |
2111 | spin_unlock_irqrestore( | |
2112 | &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); | |
2113 | ||
2114 | return value; | |
2115 | } | |
2116 | ||
2117 | static void hw_write_20kx(struct hw *hw, u32 reg, u32 data) | |
2118 | { | |
2119 | unsigned long flags; | |
2120 | ||
2121 | spin_lock_irqsave( | |
2122 | &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); | |
2123 | outl(reg, hw->io_base + 0x0); | |
2124 | outl(data, hw->io_base + 0x4); | |
2125 | spin_unlock_irqrestore( | |
2126 | &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); | |
2127 | ||
2128 | } | |
2129 | ||
2130 | static u32 hw_read_pci(struct hw *hw, u32 reg) | |
2131 | { | |
2132 | u32 value; | |
2133 | unsigned long flags; | |
2134 | ||
2135 | spin_lock_irqsave( | |
2136 | &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); | |
2137 | outl(reg, hw->io_base + 0x10); | |
2138 | value = inl(hw->io_base + 0x14); | |
2139 | spin_unlock_irqrestore( | |
2140 | &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); | |
2141 | ||
2142 | return value; | |
2143 | } | |
2144 | ||
2145 | static void hw_write_pci(struct hw *hw, u32 reg, u32 data) | |
2146 | { | |
2147 | unsigned long flags; | |
2148 | ||
2149 | spin_lock_irqsave( | |
2150 | &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); | |
2151 | outl(reg, hw->io_base + 0x10); | |
2152 | outl(data, hw->io_base + 0x14); | |
2153 | spin_unlock_irqrestore( | |
2154 | &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); | |
2155 | } | |
2156 | ||
e23e7a14 | 2157 | static struct hw ct20k1_preset = { |
2a36f67f TI |
2158 | .irq = -1, |
2159 | ||
2160 | .card_init = hw_card_init, | |
2161 | .card_stop = hw_card_stop, | |
2162 | .pll_init = hw_pll_init, | |
2163 | .is_adc_source_selected = hw_is_adc_input_selected, | |
2164 | .select_adc_source = hw_adc_input_select, | |
b028b818 | 2165 | .capabilities = hw_capabilities, |
c7561cd8 | 2166 | #ifdef CONFIG_PM_SLEEP |
29959a09 WYC |
2167 | .suspend = hw_suspend, |
2168 | .resume = hw_resume, | |
2169 | #endif | |
2a36f67f TI |
2170 | |
2171 | .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk, | |
2172 | .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk, | |
2173 | .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk, | |
2174 | .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk, | |
2175 | .src_set_state = src_set_state, | |
2176 | .src_set_bm = src_set_bm, | |
2177 | .src_set_rsr = src_set_rsr, | |
2178 | .src_set_sf = src_set_sf, | |
2179 | .src_set_wr = src_set_wr, | |
2180 | .src_set_pm = src_set_pm, | |
2181 | .src_set_rom = src_set_rom, | |
2182 | .src_set_vo = src_set_vo, | |
2183 | .src_set_st = src_set_st, | |
2184 | .src_set_ie = src_set_ie, | |
2185 | .src_set_ilsz = src_set_ilsz, | |
2186 | .src_set_bp = src_set_bp, | |
2187 | .src_set_cisz = src_set_cisz, | |
2188 | .src_set_ca = src_set_ca, | |
2189 | .src_set_sa = src_set_sa, | |
2190 | .src_set_la = src_set_la, | |
2191 | .src_set_pitch = src_set_pitch, | |
2192 | .src_set_dirty = src_set_dirty, | |
2193 | .src_set_clear_zbufs = src_set_clear_zbufs, | |
2194 | .src_set_dirty_all = src_set_dirty_all, | |
2195 | .src_commit_write = src_commit_write, | |
2196 | .src_get_ca = src_get_ca, | |
2197 | .src_get_dirty = src_get_dirty, | |
2198 | .src_dirty_conj_mask = src_dirty_conj_mask, | |
2199 | .src_mgr_enbs_src = src_mgr_enbs_src, | |
2200 | .src_mgr_enb_src = src_mgr_enb_src, | |
2201 | .src_mgr_dsb_src = src_mgr_dsb_src, | |
2202 | .src_mgr_commit_write = src_mgr_commit_write, | |
2203 | ||
2204 | .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk, | |
2205 | .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk, | |
2206 | .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc, | |
2207 | .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser, | |
2208 | .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt, | |
2209 | .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr, | |
2210 | .srcimp_mgr_commit_write = srcimp_mgr_commit_write, | |
2211 | ||
2212 | .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk, | |
2213 | .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk, | |
2214 | .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk, | |
2215 | .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk, | |
2216 | .amixer_set_mode = amixer_set_mode, | |
2217 | .amixer_set_iv = amixer_set_iv, | |
2218 | .amixer_set_x = amixer_set_x, | |
2219 | .amixer_set_y = amixer_set_y, | |
2220 | .amixer_set_sadr = amixer_set_sadr, | |
2221 | .amixer_set_se = amixer_set_se, | |
2222 | .amixer_set_dirty = amixer_set_dirty, | |
2223 | .amixer_set_dirty_all = amixer_set_dirty_all, | |
2224 | .amixer_commit_write = amixer_commit_write, | |
2225 | .amixer_get_y = amixer_get_y, | |
2226 | .amixer_get_dirty = amixer_get_dirty, | |
2227 | ||
2228 | .dai_get_ctrl_blk = dai_get_ctrl_blk, | |
2229 | .dai_put_ctrl_blk = dai_put_ctrl_blk, | |
2230 | .dai_srt_set_srco = dai_srt_set_srcr, | |
2231 | .dai_srt_set_srcm = dai_srt_set_srcl, | |
2232 | .dai_srt_set_rsr = dai_srt_set_rsr, | |
2233 | .dai_srt_set_drat = dai_srt_set_drat, | |
2234 | .dai_srt_set_ec = dai_srt_set_ec, | |
2235 | .dai_srt_set_et = dai_srt_set_et, | |
2236 | .dai_commit_write = dai_commit_write, | |
2237 | ||
2238 | .dao_get_ctrl_blk = dao_get_ctrl_blk, | |
2239 | .dao_put_ctrl_blk = dao_put_ctrl_blk, | |
2240 | .dao_set_spos = dao_set_spos, | |
2241 | .dao_commit_write = dao_commit_write, | |
2242 | .dao_get_spos = dao_get_spos, | |
2243 | ||
2244 | .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk, | |
2245 | .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk, | |
2246 | .daio_mgr_enb_dai = daio_mgr_enb_dai, | |
2247 | .daio_mgr_dsb_dai = daio_mgr_dsb_dai, | |
2248 | .daio_mgr_enb_dao = daio_mgr_enb_dao, | |
2249 | .daio_mgr_dsb_dao = daio_mgr_dsb_dao, | |
2250 | .daio_mgr_dao_init = daio_mgr_dao_init, | |
2251 | .daio_mgr_set_imaparc = daio_mgr_set_imaparc, | |
2252 | .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt, | |
2253 | .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr, | |
2254 | .daio_mgr_commit_write = daio_mgr_commit_write, | |
2255 | ||
2256 | .set_timer_irq = set_timer_irq, | |
2257 | .set_timer_tick = set_timer_tick, | |
54de6bc8 | 2258 | .get_wc = get_wc, |
2a36f67f TI |
2259 | }; |
2260 | ||
e23e7a14 | 2261 | int create_20k1_hw_obj(struct hw **rhw) |
8cc72361 | 2262 | { |
8cc72361 WYC |
2263 | struct hw20k1 *hw20k1; |
2264 | ||
2265 | *rhw = NULL; | |
2266 | hw20k1 = kzalloc(sizeof(*hw20k1), GFP_KERNEL); | |
35ebf6e7 | 2267 | if (!hw20k1) |
8cc72361 WYC |
2268 | return -ENOMEM; |
2269 | ||
2270 | spin_lock_init(&hw20k1->reg_20k1_lock); | |
2271 | spin_lock_init(&hw20k1->reg_pci_lock); | |
2272 | ||
2a36f67f | 2273 | hw20k1->hw = ct20k1_preset; |
8cc72361 | 2274 | |
2a36f67f | 2275 | *rhw = &hw20k1->hw; |
8cc72361 WYC |
2276 | |
2277 | return 0; | |
2278 | } | |
2279 | ||
2280 | int destroy_20k1_hw_obj(struct hw *hw) | |
2281 | { | |
2282 | if (hw->io_base) | |
2283 | hw_card_shutdown(hw); | |
2284 | ||
2285 | kfree(container_of(hw, struct hw20k1, hw)); | |
2286 | return 0; | |
2287 | } |