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Commit | Line | Data |
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05e84878 DR |
1 | /* |
2 | * | |
3 | * Implementation of primary alsa driver code base for Intel HD Audio. | |
4 | * | |
5 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
8 | * PeiSen Hou <pshou@realtek.com.tw> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the Free | |
12 | * Software Foundation; either version 2 of the License, or (at your option) | |
13 | * any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
18 | * more details. | |
19 | * | |
20 | * | |
21 | */ | |
22 | ||
23 | #include <linux/clocksource.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/slab.h> | |
28 | #include <sound/core.h> | |
29 | #include <sound/initval.h> | |
30 | #include "hda_priv.h" | |
31 | #include "hda_controller.h" | |
32 | ||
33 | #define CREATE_TRACE_POINTS | |
34 | #include "hda_intel_trace.h" | |
35 | ||
36 | /* | |
37 | * AZX stream operations. | |
38 | */ | |
39 | ||
40 | /* start a stream */ | |
41 | void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) | |
42 | { | |
43 | /* | |
44 | * Before stream start, initialize parameter | |
45 | */ | |
46 | azx_dev->insufficient = 1; | |
47 | ||
48 | /* enable SIE */ | |
49 | azx_writel(chip, INTCTL, | |
50 | azx_readl(chip, INTCTL) | (1 << azx_dev->index)); | |
51 | /* set DMA start and interrupt mask */ | |
52 | azx_sd_writeb(chip, azx_dev, SD_CTL, | |
53 | azx_sd_readb(chip, azx_dev, SD_CTL) | | |
54 | SD_CTL_DMA_START | SD_INT_MASK); | |
55 | } | |
56 | EXPORT_SYMBOL_GPL(azx_stream_start); | |
57 | ||
58 | /* stop DMA */ | |
59 | static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) | |
60 | { | |
61 | azx_sd_writeb(chip, azx_dev, SD_CTL, | |
62 | azx_sd_readb(chip, azx_dev, SD_CTL) & | |
63 | ~(SD_CTL_DMA_START | SD_INT_MASK)); | |
64 | azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | |
65 | } | |
66 | ||
67 | /* stop a stream */ | |
68 | void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) | |
69 | { | |
70 | azx_stream_clear(chip, azx_dev); | |
71 | /* disable SIE */ | |
72 | azx_writel(chip, INTCTL, | |
73 | azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); | |
74 | } | |
75 | EXPORT_SYMBOL_GPL(azx_stream_stop); | |
76 | ||
77 | /* reset stream */ | |
78 | void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) | |
79 | { | |
80 | unsigned char val; | |
81 | int timeout; | |
82 | ||
83 | azx_stream_clear(chip, azx_dev); | |
84 | ||
85 | azx_sd_writeb(chip, azx_dev, SD_CTL, | |
86 | azx_sd_readb(chip, azx_dev, SD_CTL) | | |
87 | SD_CTL_STREAM_RESET); | |
88 | udelay(3); | |
89 | timeout = 300; | |
90 | while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) & | |
91 | SD_CTL_STREAM_RESET) && --timeout) | |
92 | ; | |
93 | val &= ~SD_CTL_STREAM_RESET; | |
94 | azx_sd_writeb(chip, azx_dev, SD_CTL, val); | |
95 | udelay(3); | |
96 | ||
97 | timeout = 300; | |
98 | /* waiting for hardware to report that the stream is out of reset */ | |
99 | while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) & | |
100 | SD_CTL_STREAM_RESET) && --timeout) | |
101 | ; | |
102 | ||
103 | /* reset first position - may not be synced with hw at this time */ | |
104 | *azx_dev->posbuf = 0; | |
105 | } | |
106 | EXPORT_SYMBOL_GPL(azx_stream_reset); | |
107 | ||
108 | /* | |
109 | * set up the SD for streaming | |
110 | */ | |
111 | int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) | |
112 | { | |
113 | unsigned int val; | |
114 | /* make sure the run bit is zero for SD */ | |
115 | azx_stream_clear(chip, azx_dev); | |
116 | /* program the stream_tag */ | |
117 | val = azx_sd_readl(chip, azx_dev, SD_CTL); | |
118 | val = (val & ~SD_CTL_STREAM_TAG_MASK) | | |
119 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); | |
120 | if (!azx_snoop(chip)) | |
121 | val |= SD_CTL_TRAFFIC_PRIO; | |
122 | azx_sd_writel(chip, azx_dev, SD_CTL, val); | |
123 | ||
124 | /* program the length of samples in cyclic buffer */ | |
125 | azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize); | |
126 | ||
127 | /* program the stream format */ | |
128 | /* this value needs to be the same as the one programmed */ | |
129 | azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val); | |
130 | ||
131 | /* program the stream LVI (last valid index) of the BDL */ | |
132 | azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1); | |
133 | ||
134 | /* program the BDL address */ | |
135 | /* lower BDL address */ | |
136 | azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); | |
137 | /* upper BDL address */ | |
138 | azx_sd_writel(chip, azx_dev, SD_BDLPU, | |
139 | upper_32_bits(azx_dev->bdl.addr)); | |
140 | ||
141 | /* enable the position buffer */ | |
142 | if (chip->position_fix[0] != POS_FIX_LPIB || | |
143 | chip->position_fix[1] != POS_FIX_LPIB) { | |
144 | if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) | |
145 | azx_writel(chip, DPLBASE, | |
146 | (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); | |
147 | } | |
148 | ||
149 | /* set the interrupt enable bits in the descriptor control register */ | |
150 | azx_sd_writel(chip, azx_dev, SD_CTL, | |
151 | azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK); | |
152 | ||
153 | return 0; | |
154 | } | |
155 | EXPORT_SYMBOL_GPL(azx_setup_controller); | |
156 | ||
157 | /* assign a stream for the PCM */ | |
158 | static inline struct azx_dev * | |
159 | azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) | |
160 | { | |
161 | int dev, i, nums; | |
162 | struct azx_dev *res = NULL; | |
163 | /* make a non-zero unique key for the substream */ | |
164 | int key = (substream->pcm->device << 16) | (substream->number << 2) | | |
165 | (substream->stream + 1); | |
166 | ||
167 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
168 | dev = chip->playback_index_offset; | |
169 | nums = chip->playback_streams; | |
170 | } else { | |
171 | dev = chip->capture_index_offset; | |
172 | nums = chip->capture_streams; | |
173 | } | |
174 | for (i = 0; i < nums; i++, dev++) { | |
175 | struct azx_dev *azx_dev = &chip->azx_dev[dev]; | |
176 | dsp_lock(azx_dev); | |
177 | if (!azx_dev->opened && !dsp_is_locked(azx_dev)) { | |
178 | res = azx_dev; | |
179 | if (res->assigned_key == key) { | |
180 | res->opened = 1; | |
181 | res->assigned_key = key; | |
182 | dsp_unlock(azx_dev); | |
183 | return azx_dev; | |
184 | } | |
185 | } | |
186 | dsp_unlock(azx_dev); | |
187 | } | |
188 | if (res) { | |
189 | dsp_lock(res); | |
190 | res->opened = 1; | |
191 | res->assigned_key = key; | |
192 | dsp_unlock(res); | |
193 | } | |
194 | return res; | |
195 | } | |
196 | ||
197 | /* release the assigned stream */ | |
198 | static inline void azx_release_device(struct azx_dev *azx_dev) | |
199 | { | |
200 | azx_dev->opened = 0; | |
201 | } | |
202 | ||
203 | static cycle_t azx_cc_read(const struct cyclecounter *cc) | |
204 | { | |
205 | struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc); | |
206 | struct snd_pcm_substream *substream = azx_dev->substream; | |
207 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
208 | struct azx *chip = apcm->chip; | |
209 | ||
210 | return azx_readl(chip, WALLCLK); | |
211 | } | |
212 | ||
213 | static void azx_timecounter_init(struct snd_pcm_substream *substream, | |
214 | bool force, cycle_t last) | |
215 | { | |
216 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
217 | struct timecounter *tc = &azx_dev->azx_tc; | |
218 | struct cyclecounter *cc = &azx_dev->azx_cc; | |
219 | u64 nsec; | |
220 | ||
221 | cc->read = azx_cc_read; | |
222 | cc->mask = CLOCKSOURCE_MASK(32); | |
223 | ||
224 | /* | |
225 | * Converting from 24 MHz to ns means applying a 125/3 factor. | |
226 | * To avoid any saturation issues in intermediate operations, | |
227 | * the 125 factor is applied first. The division is applied | |
228 | * last after reading the timecounter value. | |
229 | * Applying the 1/3 factor as part of the multiplication | |
230 | * requires at least 20 bits for a decent precision, however | |
231 | * overflows occur after about 4 hours or less, not a option. | |
232 | */ | |
233 | ||
234 | cc->mult = 125; /* saturation after 195 years */ | |
235 | cc->shift = 0; | |
236 | ||
237 | nsec = 0; /* audio time is elapsed time since trigger */ | |
238 | timecounter_init(tc, cc, nsec); | |
239 | if (force) | |
240 | /* | |
241 | * force timecounter to use predefined value, | |
242 | * used for synchronized starts | |
243 | */ | |
244 | tc->cycle_last = last; | |
245 | } | |
246 | ||
247 | static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream, | |
248 | u64 nsec) | |
249 | { | |
250 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
251 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
252 | u64 codec_frames, codec_nsecs; | |
253 | ||
254 | if (!hinfo->ops.get_delay) | |
255 | return nsec; | |
256 | ||
257 | codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream); | |
258 | codec_nsecs = div_u64(codec_frames * 1000000000LL, | |
259 | substream->runtime->rate); | |
260 | ||
261 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
262 | return nsec + codec_nsecs; | |
263 | ||
264 | return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; | |
265 | } | |
266 | ||
267 | /* | |
268 | * set up a BDL entry | |
269 | */ | |
270 | int setup_bdle(struct azx *chip, | |
271 | struct snd_dma_buffer *dmab, | |
272 | struct azx_dev *azx_dev, u32 **bdlp, | |
273 | int ofs, int size, int with_ioc) | |
274 | { | |
275 | u32 *bdl = *bdlp; | |
276 | ||
277 | while (size > 0) { | |
278 | dma_addr_t addr; | |
279 | int chunk; | |
280 | ||
281 | if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) | |
282 | return -EINVAL; | |
283 | ||
284 | addr = snd_sgbuf_get_addr(dmab, ofs); | |
285 | /* program the address field of the BDL entry */ | |
286 | bdl[0] = cpu_to_le32((u32)addr); | |
287 | bdl[1] = cpu_to_le32(upper_32_bits(addr)); | |
288 | /* program the size field of the BDL entry */ | |
289 | chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); | |
290 | /* one BDLE cannot cross 4K boundary on CTHDA chips */ | |
291 | if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) { | |
292 | u32 remain = 0x1000 - (ofs & 0xfff); | |
293 | if (chunk > remain) | |
294 | chunk = remain; | |
295 | } | |
296 | bdl[2] = cpu_to_le32(chunk); | |
297 | /* program the IOC to enable interrupt | |
298 | * only when the whole fragment is processed | |
299 | */ | |
300 | size -= chunk; | |
301 | bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); | |
302 | bdl += 4; | |
303 | azx_dev->frags++; | |
304 | ofs += chunk; | |
305 | } | |
306 | *bdlp = bdl; | |
307 | return ofs; | |
308 | } | |
309 | EXPORT_SYMBOL_GPL(setup_bdle); | |
310 | ||
311 | /* | |
312 | * set up BDL entries | |
313 | */ | |
314 | static int azx_setup_periods(struct azx *chip, | |
315 | struct snd_pcm_substream *substream, | |
316 | struct azx_dev *azx_dev) | |
317 | { | |
318 | u32 *bdl; | |
319 | int i, ofs, periods, period_bytes; | |
320 | int pos_adj = 0; | |
321 | ||
322 | /* reset BDL address */ | |
323 | azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); | |
324 | azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); | |
325 | ||
326 | period_bytes = azx_dev->period_bytes; | |
327 | periods = azx_dev->bufsize / period_bytes; | |
328 | ||
329 | /* program the initial BDL entries */ | |
330 | bdl = (u32 *)azx_dev->bdl.area; | |
331 | ofs = 0; | |
332 | azx_dev->frags = 0; | |
333 | ||
334 | if (chip->bdl_pos_adj) | |
335 | pos_adj = chip->bdl_pos_adj[chip->dev_index]; | |
336 | if (!azx_dev->no_period_wakeup && pos_adj > 0) { | |
337 | struct snd_pcm_runtime *runtime = substream->runtime; | |
338 | int pos_align = pos_adj; | |
339 | pos_adj = (pos_adj * runtime->rate + 47999) / 48000; | |
340 | if (!pos_adj) | |
341 | pos_adj = pos_align; | |
342 | else | |
343 | pos_adj = ((pos_adj + pos_align - 1) / pos_align) * | |
344 | pos_align; | |
345 | pos_adj = frames_to_bytes(runtime, pos_adj); | |
346 | if (pos_adj >= period_bytes) { | |
347 | dev_warn(chip->card->dev,"Too big adjustment %d\n", | |
348 | pos_adj); | |
349 | pos_adj = 0; | |
350 | } else { | |
351 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), | |
352 | azx_dev, | |
353 | &bdl, ofs, pos_adj, true); | |
354 | if (ofs < 0) | |
355 | goto error; | |
356 | } | |
357 | } else | |
358 | pos_adj = 0; | |
359 | ||
360 | for (i = 0; i < periods; i++) { | |
361 | if (i == periods - 1 && pos_adj) | |
362 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), | |
363 | azx_dev, &bdl, ofs, | |
364 | period_bytes - pos_adj, 0); | |
365 | else | |
366 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), | |
367 | azx_dev, &bdl, ofs, | |
368 | period_bytes, | |
369 | !azx_dev->no_period_wakeup); | |
370 | if (ofs < 0) | |
371 | goto error; | |
372 | } | |
373 | return 0; | |
374 | ||
375 | error: | |
376 | dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n", | |
377 | azx_dev->bufsize, period_bytes); | |
378 | return -EINVAL; | |
379 | } | |
380 | ||
381 | /* | |
382 | * PCM ops | |
383 | */ | |
384 | ||
385 | static int azx_pcm_close(struct snd_pcm_substream *substream) | |
386 | { | |
387 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
388 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
389 | struct azx *chip = apcm->chip; | |
390 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
391 | unsigned long flags; | |
392 | ||
393 | mutex_lock(&chip->open_mutex); | |
394 | spin_lock_irqsave(&chip->reg_lock, flags); | |
395 | azx_dev->substream = NULL; | |
396 | azx_dev->running = 0; | |
397 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
398 | azx_release_device(azx_dev); | |
399 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
400 | snd_hda_power_down(apcm->codec); | |
401 | mutex_unlock(&chip->open_mutex); | |
402 | return 0; | |
403 | } | |
404 | ||
405 | static int azx_pcm_hw_params(struct snd_pcm_substream *substream, | |
406 | struct snd_pcm_hw_params *hw_params) | |
407 | { | |
408 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
409 | struct azx *chip = apcm->chip; | |
410 | int ret; | |
411 | ||
412 | dsp_lock(get_azx_dev(substream)); | |
413 | if (dsp_is_locked(get_azx_dev(substream))) { | |
414 | ret = -EBUSY; | |
415 | goto unlock; | |
416 | } | |
417 | ||
418 | ret = chip->ops->substream_alloc_pages(chip, substream, | |
419 | params_buffer_bytes(hw_params)); | |
420 | unlock: | |
421 | dsp_unlock(get_azx_dev(substream)); | |
422 | return ret; | |
423 | } | |
424 | ||
425 | static int azx_pcm_hw_free(struct snd_pcm_substream *substream) | |
426 | { | |
427 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
428 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
429 | struct azx *chip = apcm->chip; | |
430 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
431 | int err; | |
432 | ||
433 | /* reset BDL address */ | |
434 | dsp_lock(azx_dev); | |
435 | if (!dsp_is_locked(azx_dev)) { | |
436 | azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); | |
437 | azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); | |
438 | azx_sd_writel(chip, azx_dev, SD_CTL, 0); | |
439 | azx_dev->bufsize = 0; | |
440 | azx_dev->period_bytes = 0; | |
441 | azx_dev->format_val = 0; | |
442 | } | |
443 | ||
444 | snd_hda_codec_cleanup(apcm->codec, hinfo, substream); | |
445 | ||
446 | err = chip->ops->substream_free_pages(chip, substream); | |
447 | azx_dev->prepared = 0; | |
448 | dsp_unlock(azx_dev); | |
449 | return err; | |
450 | } | |
451 | ||
452 | static int azx_pcm_prepare(struct snd_pcm_substream *substream) | |
453 | { | |
454 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
455 | struct azx *chip = apcm->chip; | |
456 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
457 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
458 | struct snd_pcm_runtime *runtime = substream->runtime; | |
459 | unsigned int bufsize, period_bytes, format_val, stream_tag; | |
460 | int err; | |
461 | struct hda_spdif_out *spdif = | |
462 | snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid); | |
463 | unsigned short ctls = spdif ? spdif->ctls : 0; | |
464 | ||
465 | dsp_lock(azx_dev); | |
466 | if (dsp_is_locked(azx_dev)) { | |
467 | err = -EBUSY; | |
468 | goto unlock; | |
469 | } | |
470 | ||
471 | azx_stream_reset(chip, azx_dev); | |
472 | format_val = snd_hda_calc_stream_format(runtime->rate, | |
473 | runtime->channels, | |
474 | runtime->format, | |
475 | hinfo->maxbps, | |
476 | ctls); | |
477 | if (!format_val) { | |
478 | dev_err(chip->card->dev, | |
479 | "invalid format_val, rate=%d, ch=%d, format=%d\n", | |
480 | runtime->rate, runtime->channels, runtime->format); | |
481 | err = -EINVAL; | |
482 | goto unlock; | |
483 | } | |
484 | ||
485 | bufsize = snd_pcm_lib_buffer_bytes(substream); | |
486 | period_bytes = snd_pcm_lib_period_bytes(substream); | |
487 | ||
488 | dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", | |
489 | bufsize, format_val); | |
490 | ||
491 | if (bufsize != azx_dev->bufsize || | |
492 | period_bytes != azx_dev->period_bytes || | |
493 | format_val != azx_dev->format_val || | |
494 | runtime->no_period_wakeup != azx_dev->no_period_wakeup) { | |
495 | azx_dev->bufsize = bufsize; | |
496 | azx_dev->period_bytes = period_bytes; | |
497 | azx_dev->format_val = format_val; | |
498 | azx_dev->no_period_wakeup = runtime->no_period_wakeup; | |
499 | err = azx_setup_periods(chip, substream, azx_dev); | |
500 | if (err < 0) | |
501 | goto unlock; | |
502 | } | |
503 | ||
504 | /* when LPIB delay correction gives a small negative value, | |
505 | * we ignore it; currently set the threshold statically to | |
506 | * 64 frames | |
507 | */ | |
508 | if (runtime->period_size > 64) | |
509 | azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64); | |
510 | else | |
511 | azx_dev->delay_negative_threshold = 0; | |
512 | ||
513 | /* wallclk has 24Mhz clock source */ | |
514 | azx_dev->period_wallclk = (((runtime->period_size * 24000) / | |
515 | runtime->rate) * 1000); | |
516 | azx_setup_controller(chip, azx_dev); | |
517 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
518 | azx_dev->fifo_size = | |
519 | azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1; | |
520 | else | |
521 | azx_dev->fifo_size = 0; | |
522 | ||
523 | stream_tag = azx_dev->stream_tag; | |
524 | /* CA-IBG chips need the playback stream starting from 1 */ | |
525 | if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) && | |
526 | stream_tag > chip->capture_streams) | |
527 | stream_tag -= chip->capture_streams; | |
528 | err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, | |
529 | azx_dev->format_val, substream); | |
530 | ||
531 | unlock: | |
532 | if (!err) | |
533 | azx_dev->prepared = 1; | |
534 | dsp_unlock(azx_dev); | |
535 | return err; | |
536 | } | |
537 | ||
538 | static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) | |
539 | { | |
540 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
541 | struct azx *chip = apcm->chip; | |
542 | struct azx_dev *azx_dev; | |
543 | struct snd_pcm_substream *s; | |
544 | int rstart = 0, start, nsync = 0, sbits = 0; | |
545 | int nwait, timeout; | |
546 | ||
547 | azx_dev = get_azx_dev(substream); | |
548 | trace_azx_pcm_trigger(chip, azx_dev, cmd); | |
549 | ||
550 | if (dsp_is_locked(azx_dev) || !azx_dev->prepared) | |
551 | return -EPIPE; | |
552 | ||
553 | switch (cmd) { | |
554 | case SNDRV_PCM_TRIGGER_START: | |
555 | rstart = 1; | |
556 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
557 | case SNDRV_PCM_TRIGGER_RESUME: | |
558 | start = 1; | |
559 | break; | |
560 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
561 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
562 | case SNDRV_PCM_TRIGGER_STOP: | |
563 | start = 0; | |
564 | break; | |
565 | default: | |
566 | return -EINVAL; | |
567 | } | |
568 | ||
569 | snd_pcm_group_for_each_entry(s, substream) { | |
570 | if (s->pcm->card != substream->pcm->card) | |
571 | continue; | |
572 | azx_dev = get_azx_dev(s); | |
573 | sbits |= 1 << azx_dev->index; | |
574 | nsync++; | |
575 | snd_pcm_trigger_done(s, substream); | |
576 | } | |
577 | ||
578 | spin_lock(&chip->reg_lock); | |
579 | ||
580 | /* first, set SYNC bits of corresponding streams */ | |
581 | if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) | |
582 | azx_writel(chip, OLD_SSYNC, | |
583 | azx_readl(chip, OLD_SSYNC) | sbits); | |
584 | else | |
585 | azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits); | |
586 | ||
587 | snd_pcm_group_for_each_entry(s, substream) { | |
588 | if (s->pcm->card != substream->pcm->card) | |
589 | continue; | |
590 | azx_dev = get_azx_dev(s); | |
591 | if (start) { | |
592 | azx_dev->start_wallclk = azx_readl(chip, WALLCLK); | |
593 | if (!rstart) | |
594 | azx_dev->start_wallclk -= | |
595 | azx_dev->period_wallclk; | |
596 | azx_stream_start(chip, azx_dev); | |
597 | } else { | |
598 | azx_stream_stop(chip, azx_dev); | |
599 | } | |
600 | azx_dev->running = start; | |
601 | } | |
602 | spin_unlock(&chip->reg_lock); | |
603 | if (start) { | |
604 | /* wait until all FIFOs get ready */ | |
605 | for (timeout = 5000; timeout; timeout--) { | |
606 | nwait = 0; | |
607 | snd_pcm_group_for_each_entry(s, substream) { | |
608 | if (s->pcm->card != substream->pcm->card) | |
609 | continue; | |
610 | azx_dev = get_azx_dev(s); | |
611 | if (!(azx_sd_readb(chip, azx_dev, SD_STS) & | |
612 | SD_STS_FIFO_READY)) | |
613 | nwait++; | |
614 | } | |
615 | if (!nwait) | |
616 | break; | |
617 | cpu_relax(); | |
618 | } | |
619 | } else { | |
620 | /* wait until all RUN bits are cleared */ | |
621 | for (timeout = 5000; timeout; timeout--) { | |
622 | nwait = 0; | |
623 | snd_pcm_group_for_each_entry(s, substream) { | |
624 | if (s->pcm->card != substream->pcm->card) | |
625 | continue; | |
626 | azx_dev = get_azx_dev(s); | |
627 | if (azx_sd_readb(chip, azx_dev, SD_CTL) & | |
628 | SD_CTL_DMA_START) | |
629 | nwait++; | |
630 | } | |
631 | if (!nwait) | |
632 | break; | |
633 | cpu_relax(); | |
634 | } | |
635 | } | |
636 | spin_lock(&chip->reg_lock); | |
637 | /* reset SYNC bits */ | |
638 | if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) | |
639 | azx_writel(chip, OLD_SSYNC, | |
640 | azx_readl(chip, OLD_SSYNC) & ~sbits); | |
641 | else | |
642 | azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits); | |
643 | if (start) { | |
644 | azx_timecounter_init(substream, 0, 0); | |
645 | if (nsync > 1) { | |
646 | cycle_t cycle_last; | |
647 | ||
648 | /* same start cycle for master and group */ | |
649 | azx_dev = get_azx_dev(substream); | |
650 | cycle_last = azx_dev->azx_tc.cycle_last; | |
651 | ||
652 | snd_pcm_group_for_each_entry(s, substream) { | |
653 | if (s->pcm->card != substream->pcm->card) | |
654 | continue; | |
655 | azx_timecounter_init(s, 1, cycle_last); | |
656 | } | |
657 | } | |
658 | } | |
659 | spin_unlock(&chip->reg_lock); | |
660 | return 0; | |
661 | } | |
662 | ||
663 | /* get the current DMA position with correction on VIA chips */ | |
664 | static unsigned int azx_via_get_position(struct azx *chip, | |
665 | struct azx_dev *azx_dev) | |
666 | { | |
667 | unsigned int link_pos, mini_pos, bound_pos; | |
668 | unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; | |
669 | unsigned int fifo_size; | |
670 | ||
671 | link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB); | |
672 | if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
673 | /* Playback, no problem using link position */ | |
674 | return link_pos; | |
675 | } | |
676 | ||
677 | /* Capture */ | |
678 | /* For new chipset, | |
679 | * use mod to get the DMA position just like old chipset | |
680 | */ | |
681 | mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); | |
682 | mod_dma_pos %= azx_dev->period_bytes; | |
683 | ||
684 | /* azx_dev->fifo_size can't get FIFO size of in stream. | |
685 | * Get from base address + offset. | |
686 | */ | |
687 | fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); | |
688 | ||
689 | if (azx_dev->insufficient) { | |
690 | /* Link position never gather than FIFO size */ | |
691 | if (link_pos <= fifo_size) | |
692 | return 0; | |
693 | ||
694 | azx_dev->insufficient = 0; | |
695 | } | |
696 | ||
697 | if (link_pos <= fifo_size) | |
698 | mini_pos = azx_dev->bufsize + link_pos - fifo_size; | |
699 | else | |
700 | mini_pos = link_pos - fifo_size; | |
701 | ||
702 | /* Find nearest previous boudary */ | |
703 | mod_mini_pos = mini_pos % azx_dev->period_bytes; | |
704 | mod_link_pos = link_pos % azx_dev->period_bytes; | |
705 | if (mod_link_pos >= fifo_size) | |
706 | bound_pos = link_pos - mod_link_pos; | |
707 | else if (mod_dma_pos >= mod_mini_pos) | |
708 | bound_pos = mini_pos - mod_mini_pos; | |
709 | else { | |
710 | bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; | |
711 | if (bound_pos >= azx_dev->bufsize) | |
712 | bound_pos = 0; | |
713 | } | |
714 | ||
715 | /* Calculate real DMA position we want */ | |
716 | return bound_pos + mod_dma_pos; | |
717 | } | |
718 | ||
719 | unsigned int azx_get_position(struct azx *chip, | |
720 | struct azx_dev *azx_dev, | |
721 | bool with_check) | |
722 | { | |
723 | struct snd_pcm_substream *substream = azx_dev->substream; | |
724 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
725 | unsigned int pos; | |
726 | int stream = substream->stream; | |
727 | struct hda_pcm_stream *hinfo = apcm->hinfo[stream]; | |
728 | int delay = 0; | |
729 | ||
730 | switch (chip->position_fix[stream]) { | |
731 | case POS_FIX_LPIB: | |
732 | /* read LPIB */ | |
733 | pos = azx_sd_readl(chip, azx_dev, SD_LPIB); | |
734 | break; | |
735 | case POS_FIX_VIACOMBO: | |
736 | pos = azx_via_get_position(chip, azx_dev); | |
737 | break; | |
738 | default: | |
739 | /* use the position buffer */ | |
740 | pos = le32_to_cpu(*azx_dev->posbuf); | |
741 | if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) { | |
742 | if (!pos || pos == (u32)-1) { | |
743 | dev_info(chip->card->dev, | |
744 | "Invalid position buffer, using LPIB read method instead.\n"); | |
745 | chip->position_fix[stream] = POS_FIX_LPIB; | |
746 | pos = azx_sd_readl(chip, azx_dev, SD_LPIB); | |
747 | } else | |
748 | chip->position_fix[stream] = POS_FIX_POSBUF; | |
749 | } | |
750 | break; | |
751 | } | |
752 | ||
753 | if (pos >= azx_dev->bufsize) | |
754 | pos = 0; | |
755 | ||
756 | /* calculate runtime delay from LPIB */ | |
757 | if (substream->runtime && | |
758 | chip->position_fix[stream] == POS_FIX_POSBUF && | |
759 | (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { | |
760 | unsigned int lpib_pos = azx_sd_readl(chip, azx_dev, SD_LPIB); | |
761 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) | |
762 | delay = pos - lpib_pos; | |
763 | else | |
764 | delay = lpib_pos - pos; | |
765 | if (delay < 0) { | |
766 | if (delay >= azx_dev->delay_negative_threshold) | |
767 | delay = 0; | |
768 | else | |
769 | delay += azx_dev->bufsize; | |
770 | } | |
771 | if (delay >= azx_dev->period_bytes) { | |
772 | dev_info(chip->card->dev, | |
773 | "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", | |
774 | delay, azx_dev->period_bytes); | |
775 | delay = 0; | |
776 | chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; | |
777 | } | |
778 | delay = bytes_to_frames(substream->runtime, delay); | |
779 | } | |
780 | ||
781 | if (substream->runtime) { | |
782 | if (hinfo->ops.get_delay) | |
783 | delay += hinfo->ops.get_delay(hinfo, apcm->codec, | |
784 | substream); | |
785 | substream->runtime->delay = delay; | |
786 | } | |
787 | ||
788 | trace_azx_get_position(chip, azx_dev, pos, delay); | |
789 | return pos; | |
790 | } | |
791 | EXPORT_SYMBOL_GPL(azx_get_position); | |
792 | ||
793 | static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) | |
794 | { | |
795 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
796 | struct azx *chip = apcm->chip; | |
797 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
798 | return bytes_to_frames(substream->runtime, | |
799 | azx_get_position(chip, azx_dev, false)); | |
800 | } | |
801 | ||
802 | static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream, | |
803 | struct timespec *ts) | |
804 | { | |
805 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
806 | u64 nsec; | |
807 | ||
808 | nsec = timecounter_read(&azx_dev->azx_tc); | |
809 | nsec = div_u64(nsec, 3); /* can be optimized */ | |
810 | nsec = azx_adjust_codec_delay(substream, nsec); | |
811 | ||
812 | *ts = ns_to_timespec(nsec); | |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
817 | static struct snd_pcm_hardware azx_pcm_hw = { | |
818 | .info = (SNDRV_PCM_INFO_MMAP | | |
819 | SNDRV_PCM_INFO_INTERLEAVED | | |
820 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
821 | SNDRV_PCM_INFO_MMAP_VALID | | |
822 | /* No full-resume yet implemented */ | |
823 | /* SNDRV_PCM_INFO_RESUME |*/ | |
824 | SNDRV_PCM_INFO_PAUSE | | |
825 | SNDRV_PCM_INFO_SYNC_START | | |
826 | SNDRV_PCM_INFO_HAS_WALL_CLOCK | | |
827 | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), | |
828 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
829 | .rates = SNDRV_PCM_RATE_48000, | |
830 | .rate_min = 48000, | |
831 | .rate_max = 48000, | |
832 | .channels_min = 2, | |
833 | .channels_max = 2, | |
834 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, | |
835 | .period_bytes_min = 128, | |
836 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | |
837 | .periods_min = 2, | |
838 | .periods_max = AZX_MAX_FRAG, | |
839 | .fifo_size = 0, | |
840 | }; | |
841 | ||
842 | static int azx_pcm_open(struct snd_pcm_substream *substream) | |
843 | { | |
844 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
845 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
846 | struct azx *chip = apcm->chip; | |
847 | struct azx_dev *azx_dev; | |
848 | struct snd_pcm_runtime *runtime = substream->runtime; | |
849 | unsigned long flags; | |
850 | int err; | |
851 | int buff_step; | |
852 | ||
853 | mutex_lock(&chip->open_mutex); | |
854 | azx_dev = azx_assign_device(chip, substream); | |
855 | if (azx_dev == NULL) { | |
856 | mutex_unlock(&chip->open_mutex); | |
857 | return -EBUSY; | |
858 | } | |
859 | runtime->hw = azx_pcm_hw; | |
860 | runtime->hw.channels_min = hinfo->channels_min; | |
861 | runtime->hw.channels_max = hinfo->channels_max; | |
862 | runtime->hw.formats = hinfo->formats; | |
863 | runtime->hw.rates = hinfo->rates; | |
864 | snd_pcm_limit_hw_rates(runtime); | |
865 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | |
866 | ||
867 | /* avoid wrap-around with wall-clock */ | |
868 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, | |
869 | 20, | |
870 | 178000000); | |
871 | ||
872 | if (chip->align_buffer_size) | |
873 | /* constrain buffer sizes to be multiple of 128 | |
874 | bytes. This is more efficient in terms of memory | |
875 | access but isn't required by the HDA spec and | |
876 | prevents users from specifying exact period/buffer | |
877 | sizes. For example for 44.1kHz, a period size set | |
878 | to 20ms will be rounded to 19.59ms. */ | |
879 | buff_step = 128; | |
880 | else | |
881 | /* Don't enforce steps on buffer sizes, still need to | |
882 | be multiple of 4 bytes (HDA spec). Tested on Intel | |
883 | HDA controllers, may not work on all devices where | |
884 | option needs to be disabled */ | |
885 | buff_step = 4; | |
886 | ||
887 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, | |
888 | buff_step); | |
889 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, | |
890 | buff_step); | |
891 | snd_hda_power_up_d3wait(apcm->codec); | |
892 | err = hinfo->ops.open(hinfo, apcm->codec, substream); | |
893 | if (err < 0) { | |
894 | azx_release_device(azx_dev); | |
895 | snd_hda_power_down(apcm->codec); | |
896 | mutex_unlock(&chip->open_mutex); | |
897 | return err; | |
898 | } | |
899 | snd_pcm_limit_hw_rates(runtime); | |
900 | /* sanity check */ | |
901 | if (snd_BUG_ON(!runtime->hw.channels_min) || | |
902 | snd_BUG_ON(!runtime->hw.channels_max) || | |
903 | snd_BUG_ON(!runtime->hw.formats) || | |
904 | snd_BUG_ON(!runtime->hw.rates)) { | |
905 | azx_release_device(azx_dev); | |
906 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
907 | snd_hda_power_down(apcm->codec); | |
908 | mutex_unlock(&chip->open_mutex); | |
909 | return -EINVAL; | |
910 | } | |
911 | ||
912 | /* disable WALLCLOCK timestamps for capture streams | |
913 | until we figure out how to handle digital inputs */ | |
914 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
915 | runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; | |
916 | ||
917 | spin_lock_irqsave(&chip->reg_lock, flags); | |
918 | azx_dev->substream = substream; | |
919 | azx_dev->running = 0; | |
920 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
921 | ||
922 | runtime->private_data = azx_dev; | |
923 | snd_pcm_set_sync(substream); | |
924 | mutex_unlock(&chip->open_mutex); | |
925 | return 0; | |
926 | } | |
927 | ||
928 | static int azx_pcm_mmap(struct snd_pcm_substream *substream, | |
929 | struct vm_area_struct *area) | |
930 | { | |
931 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
932 | struct azx *chip = apcm->chip; | |
933 | if (chip->ops->pcm_mmap_prepare) | |
934 | chip->ops->pcm_mmap_prepare(substream, area); | |
935 | return snd_pcm_lib_default_mmap(substream, area); | |
936 | } | |
937 | ||
938 | static struct snd_pcm_ops azx_pcm_ops = { | |
939 | .open = azx_pcm_open, | |
940 | .close = azx_pcm_close, | |
941 | .ioctl = snd_pcm_lib_ioctl, | |
942 | .hw_params = azx_pcm_hw_params, | |
943 | .hw_free = azx_pcm_hw_free, | |
944 | .prepare = azx_pcm_prepare, | |
945 | .trigger = azx_pcm_trigger, | |
946 | .pointer = azx_pcm_pointer, | |
947 | .wall_clock = azx_get_wallclock_tstamp, | |
948 | .mmap = azx_pcm_mmap, | |
949 | .page = snd_pcm_sgbuf_ops_page, | |
950 | }; | |
951 | ||
952 | static void azx_pcm_free(struct snd_pcm *pcm) | |
953 | { | |
954 | struct azx_pcm *apcm = pcm->private_data; | |
955 | if (apcm) { | |
956 | list_del(&apcm->list); | |
957 | kfree(apcm); | |
958 | } | |
959 | } | |
960 | ||
961 | #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) | |
962 | ||
963 | int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, | |
964 | struct hda_pcm *cpcm) | |
965 | { | |
966 | struct azx *chip = bus->private_data; | |
967 | struct snd_pcm *pcm; | |
968 | struct azx_pcm *apcm; | |
969 | int pcm_dev = cpcm->device; | |
970 | unsigned int size; | |
971 | int s, err; | |
972 | ||
973 | list_for_each_entry(apcm, &chip->pcm_list, list) { | |
974 | if (apcm->pcm->device == pcm_dev) { | |
975 | dev_err(chip->card->dev, "PCM %d already exists\n", | |
976 | pcm_dev); | |
977 | return -EBUSY; | |
978 | } | |
979 | } | |
980 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, | |
981 | cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, | |
982 | cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, | |
983 | &pcm); | |
984 | if (err < 0) | |
985 | return err; | |
986 | strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); | |
987 | apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); | |
988 | if (apcm == NULL) | |
989 | return -ENOMEM; | |
990 | apcm->chip = chip; | |
991 | apcm->pcm = pcm; | |
992 | apcm->codec = codec; | |
993 | pcm->private_data = apcm; | |
994 | pcm->private_free = azx_pcm_free; | |
995 | if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) | |
996 | pcm->dev_class = SNDRV_PCM_CLASS_MODEM; | |
997 | list_add_tail(&apcm->list, &chip->pcm_list); | |
998 | cpcm->pcm = pcm; | |
999 | for (s = 0; s < 2; s++) { | |
1000 | apcm->hinfo[s] = &cpcm->stream[s]; | |
1001 | if (cpcm->stream[s].substreams) | |
1002 | snd_pcm_set_ops(pcm, s, &azx_pcm_ops); | |
1003 | } | |
1004 | /* buffer pre-allocation */ | |
1005 | size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; | |
1006 | if (size > MAX_PREALLOC_SIZE) | |
1007 | size = MAX_PREALLOC_SIZE; | |
1008 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, | |
1009 | chip->card->dev, | |
1010 | size, MAX_PREALLOC_SIZE); | |
1011 | /* link to codec */ | |
1012 | pcm->dev = &codec->dev; | |
1013 | return 0; | |
1014 | } | |
1015 | EXPORT_SYMBOL_GPL(azx_attach_pcm_stream); | |
1016 | ||
67908994 DR |
1017 | int azx_alloc_stream_pages(struct azx *chip) |
1018 | { | |
1019 | int i, err; | |
1020 | struct snd_card *card = chip->card; | |
1021 | ||
1022 | for (i = 0; i < chip->num_streams; i++) { | |
1023 | dsp_lock_init(&chip->azx_dev[i]); | |
1024 | /* allocate memory for the BDL for each stream */ | |
1025 | err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV, | |
1026 | BDL_SIZE, | |
1027 | &chip->azx_dev[i].bdl); | |
1028 | if (err < 0) { | |
1029 | dev_err(card->dev, "cannot allocate BDL\n"); | |
1030 | return -ENOMEM; | |
1031 | } | |
1032 | } | |
1033 | /* allocate memory for the position buffer */ | |
1034 | err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV, | |
1035 | chip->num_streams * 8, &chip->posbuf); | |
1036 | if (err < 0) { | |
1037 | dev_err(card->dev, "cannot allocate posbuf\n"); | |
1038 | return -ENOMEM; | |
1039 | } | |
1040 | return 0; | |
1041 | } | |
1042 | EXPORT_SYMBOL_GPL(azx_alloc_stream_pages); | |
1043 | ||
1044 | void azx_free_stream_pages(struct azx *chip) | |
1045 | { | |
1046 | int i; | |
1047 | if (chip->azx_dev) { | |
1048 | for (i = 0; i < chip->num_streams; i++) | |
1049 | if (chip->azx_dev[i].bdl.area) | |
1050 | chip->ops->dma_free_pages( | |
1051 | chip, &chip->azx_dev[i].bdl); | |
1052 | } | |
1053 | if (chip->rb.area) | |
1054 | chip->ops->dma_free_pages(chip, &chip->rb); | |
1055 | if (chip->posbuf.area) | |
1056 | chip->ops->dma_free_pages(chip, &chip->posbuf); | |
1057 | } | |
1058 | EXPORT_SYMBOL_GPL(azx_free_stream_pages); | |
1059 | ||
05e84878 DR |
1060 | MODULE_LICENSE("GPL"); |
1061 | MODULE_DESCRIPTION("Common HDA driver funcitons"); |