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ALSA: hda - Use shutdown driver ops instead of reboot notifier
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_controller.c
CommitLineData
05e84878
DR		 1/*
2 *
3 * Implementation of primary alsa driver code base for Intel HD Audio.
4 *
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
6 *
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 *
21 */
22
23#include <linux/clocksource.h>
24#include <linux/delay.h>
f0b1df88 25#include <linux/interrupt.h>
05e84878
DR		 26#include <linux/kernel.h>
27#include <linux/module.h>
154867cf 28#include <linux/pm_runtime.h>
05e84878
DR		 29#include <linux/slab.h>
30#include <sound/core.h>
31#include <sound/initval.h>
05e84878
DR		 32#include "hda_controller.h"
33
34#define CREATE_TRACE_POINTS
35#include "hda_intel_trace.h"
36
2b5fd6c2
DR		 37/* DSP lock helpers */
38#ifdef CONFIG_SND_HDA_DSP_LOADER
39#define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
40#define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
41#define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
42#define dsp_is_locked(dev) ((dev)->locked)
43#else
44#define dsp_lock_init(dev) do {} while (0)
45#define dsp_lock(dev) do {} while (0)
46#define dsp_unlock(dev) do {} while (0)
47#define dsp_is_locked(dev) 0
48#endif
49
05e84878
DR		 50/*
51 * AZX stream operations.
52 */
53
54/* start a stream */
2b5fd6c2 55static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
05e84878
DR		 56{
57 /*
58 * Before stream start, initialize parameter
59 */
60 azx_dev->insufficient = 1;
61
62 /* enable SIE */
63 azx_writel(chip, INTCTL,
64 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
65 /* set DMA start and interrupt mask */
66 azx_sd_writeb(chip, azx_dev, SD_CTL,
67 azx_sd_readb(chip, azx_dev, SD_CTL) |
68 SD_CTL_DMA_START | SD_INT_MASK);
69}
05e84878
DR		 70
71/* stop DMA */
72static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
73{
74 azx_sd_writeb(chip, azx_dev, SD_CTL,
75 azx_sd_readb(chip, azx_dev, SD_CTL) &
76 ~(SD_CTL_DMA_START | SD_INT_MASK));
77 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
78}
79
80/* stop a stream */
81void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
82{
83 azx_stream_clear(chip, azx_dev);
84 /* disable SIE */
85 azx_writel(chip, INTCTL,
86 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
87}
88EXPORT_SYMBOL_GPL(azx_stream_stop);
89
90/* reset stream */
2b5fd6c2 91static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
05e84878
DR		 92{
93 unsigned char val;
94 int timeout;
95
96 azx_stream_clear(chip, azx_dev);
97
98 azx_sd_writeb(chip, azx_dev, SD_CTL,
99 azx_sd_readb(chip, azx_dev, SD_CTL) |
100 SD_CTL_STREAM_RESET);
101 udelay(3);
102 timeout = 300;
103 while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
104 SD_CTL_STREAM_RESET) && --timeout)
105 ;
106 val &= ~SD_CTL_STREAM_RESET;
107 azx_sd_writeb(chip, azx_dev, SD_CTL, val);
108 udelay(3);
109
110 timeout = 300;
111 /* waiting for hardware to report that the stream is out of reset */
112 while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
113 SD_CTL_STREAM_RESET) && --timeout)
114 ;
115
116 /* reset first position - may not be synced with hw at this time */
117 *azx_dev->posbuf = 0;
118}
05e84878
DR		 119
120/*
121 * set up the SD for streaming
122 */
2b5fd6c2 123static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
05e84878
DR		 124{
125 unsigned int val;
126 /* make sure the run bit is zero for SD */
127 azx_stream_clear(chip, azx_dev);
128 /* program the stream_tag */
129 val = azx_sd_readl(chip, azx_dev, SD_CTL);
130 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
131 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
132 if (!azx_snoop(chip))
133 val |= SD_CTL_TRAFFIC_PRIO;
134 azx_sd_writel(chip, azx_dev, SD_CTL, val);
135
136 /* program the length of samples in cyclic buffer */
137 azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize);
138
139 /* program the stream format */
140 /* this value needs to be the same as the one programmed */
141 azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val);
142
143 /* program the stream LVI (last valid index) of the BDL */
144 azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1);
145
146 /* program the BDL address */
147 /* lower BDL address */
148 azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
149 /* upper BDL address */
150 azx_sd_writel(chip, azx_dev, SD_BDLPU,
151 upper_32_bits(azx_dev->bdl.addr));
152
153 /* enable the position buffer */
b6050ef6
TI		 154 if (chip->get_position[0] != azx_get_pos_lpib ||
155 chip->get_position[1] != azx_get_pos_lpib) {
fb1d8ac2 156 if (!(azx_readl(chip, DPLBASE) & AZX_DPLBASE_ENABLE))
05e84878 157 azx_writel(chip, DPLBASE,
fb1d8ac2 158 (u32)chip->posbuf.addr | AZX_DPLBASE_ENABLE);
05e84878
DR		 159 }
160
161 /* set the interrupt enable bits in the descriptor control register */
162 azx_sd_writel(chip, azx_dev, SD_CTL,
163 azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK);
164
165 return 0;
166}
05e84878
DR		 167
168/* assign a stream for the PCM */
169static inline struct azx_dev *
170azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
171{
172 int dev, i, nums;
173 struct azx_dev *res = NULL;
174 /* make a non-zero unique key for the substream */
175 int key = (substream->pcm->device << 16) | (substream->number << 2) |
176 (substream->stream + 1);
177
178 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
179 dev = chip->playback_index_offset;
180 nums = chip->playback_streams;
181 } else {
182 dev = chip->capture_index_offset;
183 nums = chip->capture_streams;
184 }
185 for (i = 0; i < nums; i++, dev++) {
186 struct azx_dev *azx_dev = &chip->azx_dev[dev];
187 dsp_lock(azx_dev);
188 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
dcb32ecd
AH		 189 if (azx_dev->assigned_key == key) {
190 azx_dev->opened = 1;
191 azx_dev->assigned_key = key;
05e84878
DR		 192 dsp_unlock(azx_dev);
193 return azx_dev;
194 }
cd50065b
TI		 195 if (!res ||
196 (chip->driver_caps & AZX_DCAPS_REVERSE_ASSIGN))
dcb32ecd 197 res = azx_dev;
05e84878
DR		 198 }
199 dsp_unlock(azx_dev);
200 }
201 if (res) {
202 dsp_lock(res);
203 res->opened = 1;
204 res->assigned_key = key;
205 dsp_unlock(res);
206 }
207 return res;
208}
209
210/* release the assigned stream */
211static inline void azx_release_device(struct azx_dev *azx_dev)
212{
213 azx_dev->opened = 0;
214}
215
216static cycle_t azx_cc_read(const struct cyclecounter *cc)
217{
218 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
219 struct snd_pcm_substream *substream = azx_dev->substream;
220 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
221 struct azx *chip = apcm->chip;
222
223 return azx_readl(chip, WALLCLK);
224}
225
226static void azx_timecounter_init(struct snd_pcm_substream *substream,
227 bool force, cycle_t last)
228{
229 struct azx_dev *azx_dev = get_azx_dev(substream);
230 struct timecounter *tc = &azx_dev->azx_tc;
231 struct cyclecounter *cc = &azx_dev->azx_cc;
232 u64 nsec;
233
234 cc->read = azx_cc_read;
235 cc->mask = CLOCKSOURCE_MASK(32);
236
237 /*
238 * Converting from 24 MHz to ns means applying a 125/3 factor.
239 * To avoid any saturation issues in intermediate operations,
240 * the 125 factor is applied first. The division is applied
241 * last after reading the timecounter value.
242 * Applying the 1/3 factor as part of the multiplication
243 * requires at least 20 bits for a decent precision, however
244 * overflows occur after about 4 hours or less, not a option.
245 */
246
247 cc->mult = 125; /* saturation after 195 years */
248 cc->shift = 0;
249
250 nsec = 0; /* audio time is elapsed time since trigger */
251 timecounter_init(tc, cc, nsec);
252 if (force)
253 /*
254 * force timecounter to use predefined value,
255 * used for synchronized starts
256 */
257 tc->cycle_last = last;
258}
259
820cc6cf
TI		 260static inline struct hda_pcm_stream *
261to_hda_pcm_stream(struct snd_pcm_substream *substream)
262{
263 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
264 return &apcm->info->stream[substream->stream];
265}
266
05e84878
DR		 267static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
268 u64 nsec)
269{
270 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
820cc6cf 271 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
05e84878
DR		 272 u64 codec_frames, codec_nsecs;
273
274 if (!hinfo->ops.get_delay)
275 return nsec;
276
277 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
278 codec_nsecs = div_u64(codec_frames * 1000000000LL,
279 substream->runtime->rate);
280
281 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
282 return nsec + codec_nsecs;
283
284 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
285}
286
287/*
288 * set up a BDL entry
289 */
2b5fd6c2
DR		 290static int setup_bdle(struct azx *chip,
291 struct snd_dma_buffer *dmab,
292 struct azx_dev *azx_dev, u32 **bdlp,
293 int ofs, int size, int with_ioc)
05e84878
DR		 294{
295 u32 *bdl = *bdlp;
296
297 while (size > 0) {
298 dma_addr_t addr;
299 int chunk;
300
301 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
302 return -EINVAL;
303
304 addr = snd_sgbuf_get_addr(dmab, ofs);
305 /* program the address field of the BDL entry */
306 bdl[0] = cpu_to_le32((u32)addr);
307 bdl[1] = cpu_to_le32(upper_32_bits(addr));
308 /* program the size field of the BDL entry */
309 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
310 /* one BDLE cannot cross 4K boundary on CTHDA chips */
311 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
312 u32 remain = 0x1000 - (ofs & 0xfff);
313 if (chunk > remain)
314 chunk = remain;
315 }
316 bdl[2] = cpu_to_le32(chunk);
317 /* program the IOC to enable interrupt
318 * only when the whole fragment is processed
319 */
320 size -= chunk;
321 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
322 bdl += 4;
323 azx_dev->frags++;
324 ofs += chunk;
325 }
326 *bdlp = bdl;
327 return ofs;
328}
05e84878
DR		 329
330/*
331 * set up BDL entries
332 */
333static int azx_setup_periods(struct azx *chip,
334 struct snd_pcm_substream *substream,
335 struct azx_dev *azx_dev)
336{
337 u32 *bdl;
338 int i, ofs, periods, period_bytes;
339 int pos_adj = 0;
340
341 /* reset BDL address */
342 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
343 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
344
345 period_bytes = azx_dev->period_bytes;
346 periods = azx_dev->bufsize / period_bytes;
347
348 /* program the initial BDL entries */
349 bdl = (u32 *)azx_dev->bdl.area;
350 ofs = 0;
351 azx_dev->frags = 0;
352
353 if (chip->bdl_pos_adj)
354 pos_adj = chip->bdl_pos_adj[chip->dev_index];
355 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
356 struct snd_pcm_runtime *runtime = substream->runtime;
357 int pos_align = pos_adj;
358 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
359 if (!pos_adj)
360 pos_adj = pos_align;
361 else
362 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
363 pos_align;
364 pos_adj = frames_to_bytes(runtime, pos_adj);
365 if (pos_adj >= period_bytes) {
366 dev_warn(chip->card->dev,"Too big adjustment %d\n",
367 pos_adj);
368 pos_adj = 0;
369 } else {
370 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
371 azx_dev,
372 &bdl, ofs, pos_adj, true);
373 if (ofs < 0)
374 goto error;
375 }
376 } else
377 pos_adj = 0;
378
379 for (i = 0; i < periods; i++) {
380 if (i == periods - 1 && pos_adj)
381 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
382 azx_dev, &bdl, ofs,
383 period_bytes - pos_adj, 0);
384 else
385 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
386 azx_dev, &bdl, ofs,
387 period_bytes,
388 !azx_dev->no_period_wakeup);
389 if (ofs < 0)
390 goto error;
391 }
392 return 0;
393
394 error:
395 dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n",
396 azx_dev->bufsize, period_bytes);
397 return -EINVAL;
398}
399
400/*
401 * PCM ops
402 */
403
404static int azx_pcm_close(struct snd_pcm_substream *substream)
405{
406 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
820cc6cf 407 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
05e84878
DR		 408 struct azx *chip = apcm->chip;
409 struct azx_dev *azx_dev = get_azx_dev(substream);
410 unsigned long flags;
411
412 mutex_lock(&chip->open_mutex);
413 spin_lock_irqsave(&chip->reg_lock, flags);
414 azx_dev->substream = NULL;
415 azx_dev->running = 0;
416 spin_unlock_irqrestore(&chip->reg_lock, flags);
417 azx_release_device(azx_dev);
61ca4107
TI		 418 if (hinfo->ops.close)
419 hinfo->ops.close(hinfo, apcm->codec, substream);
05e84878
DR		 420 snd_hda_power_down(apcm->codec);
421 mutex_unlock(&chip->open_mutex);
9a6246ff 422 snd_hda_codec_pcm_put(apcm->info);
05e84878
DR		 423 return 0;
424}
425
426static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
427 struct snd_pcm_hw_params *hw_params)
428{
429 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
430 struct azx *chip = apcm->chip;
431 int ret;
432
433 dsp_lock(get_azx_dev(substream));
434 if (dsp_is_locked(get_azx_dev(substream))) {
435 ret = -EBUSY;
436 goto unlock;
437 }
438
439 ret = chip->ops->substream_alloc_pages(chip, substream,
440 params_buffer_bytes(hw_params));
441unlock:
442 dsp_unlock(get_azx_dev(substream));
443 return ret;
444}
445
446static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
447{
448 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
449 struct azx_dev *azx_dev = get_azx_dev(substream);
450 struct azx *chip = apcm->chip;
820cc6cf 451 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
05e84878
DR		 452 int err;
453
454 /* reset BDL address */
455 dsp_lock(azx_dev);
456 if (!dsp_is_locked(azx_dev)) {
457 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
458 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
459 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
460 azx_dev->bufsize = 0;
461 azx_dev->period_bytes = 0;
462 azx_dev->format_val = 0;
463 }
464
465 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
466
467 err = chip->ops->substream_free_pages(chip, substream);
468 azx_dev->prepared = 0;
469 dsp_unlock(azx_dev);
470 return err;
471}
472
473static int azx_pcm_prepare(struct snd_pcm_substream *substream)
474{
475 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
476 struct azx *chip = apcm->chip;
477 struct azx_dev *azx_dev = get_azx_dev(substream);
820cc6cf 478 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
05e84878
DR		 479 struct snd_pcm_runtime *runtime = substream->runtime;
480 unsigned int bufsize, period_bytes, format_val, stream_tag;
481 int err;
482 struct hda_spdif_out *spdif =
483 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
484 unsigned short ctls = spdif ? spdif->ctls : 0;
485
486 dsp_lock(azx_dev);
487 if (dsp_is_locked(azx_dev)) {
488 err = -EBUSY;
489 goto unlock;
490 }
491
492 azx_stream_reset(chip, azx_dev);
6194b99d
TI		 493 format_val = snd_hda_calc_stream_format(apcm->codec,
494 runtime->rate,
05e84878
DR		 495 runtime->channels,
496 runtime->format,
497 hinfo->maxbps,
498 ctls);
499 if (!format_val) {
500 dev_err(chip->card->dev,
501 "invalid format_val, rate=%d, ch=%d, format=%d\n",
502 runtime->rate, runtime->channels, runtime->format);
503 err = -EINVAL;
504 goto unlock;
505 }
506
507 bufsize = snd_pcm_lib_buffer_bytes(substream);
508 period_bytes = snd_pcm_lib_period_bytes(substream);
509
510 dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
511 bufsize, format_val);
512
513 if (bufsize != azx_dev->bufsize ||
514 period_bytes != azx_dev->period_bytes ||
515 format_val != azx_dev->format_val ||
516 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
517 azx_dev->bufsize = bufsize;
518 azx_dev->period_bytes = period_bytes;
519 azx_dev->format_val = format_val;
520 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
521 err = azx_setup_periods(chip, substream, azx_dev);
522 if (err < 0)
523 goto unlock;
524 }
525
526 /* when LPIB delay correction gives a small negative value,
527 * we ignore it; currently set the threshold statically to
528 * 64 frames
529 */
530 if (runtime->period_size > 64)
531 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
532 else
533 azx_dev->delay_negative_threshold = 0;
534
535 /* wallclk has 24Mhz clock source */
536 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
537 runtime->rate) * 1000);
538 azx_setup_controller(chip, azx_dev);
539 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
540 azx_dev->fifo_size =
541 azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1;
542 else
543 azx_dev->fifo_size = 0;
544
545 stream_tag = azx_dev->stream_tag;
546 /* CA-IBG chips need the playback stream starting from 1 */
547 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
548 stream_tag > chip->capture_streams)
549 stream_tag -= chip->capture_streams;
550 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
551 azx_dev->format_val, substream);
552
553 unlock:
554 if (!err)
555 azx_dev->prepared = 1;
556 dsp_unlock(azx_dev);
557 return err;
558}
559
560static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
561{
562 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
563 struct azx *chip = apcm->chip;
564 struct azx_dev *azx_dev;
565 struct snd_pcm_substream *s;
566 int rstart = 0, start, nsync = 0, sbits = 0;
567 int nwait, timeout;
568
569 azx_dev = get_azx_dev(substream);
570 trace_azx_pcm_trigger(chip, azx_dev, cmd);
571
572 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
573 return -EPIPE;
574
575 switch (cmd) {
576 case SNDRV_PCM_TRIGGER_START:
577 rstart = 1;
578 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
579 case SNDRV_PCM_TRIGGER_RESUME:
580 start = 1;
581 break;
582 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
583 case SNDRV_PCM_TRIGGER_SUSPEND:
584 case SNDRV_PCM_TRIGGER_STOP:
585 start = 0;
586 break;
587 default:
588 return -EINVAL;
589 }
590
591 snd_pcm_group_for_each_entry(s, substream) {
592 if (s->pcm->card != substream->pcm->card)
593 continue;
594 azx_dev = get_azx_dev(s);
595 sbits |= 1 << azx_dev->index;
596 nsync++;
597 snd_pcm_trigger_done(s, substream);
598 }
599
600 spin_lock(&chip->reg_lock);
601
602 /* first, set SYNC bits of corresponding streams */
603 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
604 azx_writel(chip, OLD_SSYNC,
605 azx_readl(chip, OLD_SSYNC) | sbits);
606 else
607 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
608
609 snd_pcm_group_for_each_entry(s, substream) {
610 if (s->pcm->card != substream->pcm->card)
611 continue;
612 azx_dev = get_azx_dev(s);
613 if (start) {
614 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
615 if (!rstart)
616 azx_dev->start_wallclk -=
617 azx_dev->period_wallclk;
618 azx_stream_start(chip, azx_dev);
619 } else {
620 azx_stream_stop(chip, azx_dev);
621 }
622 azx_dev->running = start;
623 }
624 spin_unlock(&chip->reg_lock);
625 if (start) {
626 /* wait until all FIFOs get ready */
627 for (timeout = 5000; timeout; timeout--) {
628 nwait = 0;
629 snd_pcm_group_for_each_entry(s, substream) {
630 if (s->pcm->card != substream->pcm->card)
631 continue;
632 azx_dev = get_azx_dev(s);
633 if (!(azx_sd_readb(chip, azx_dev, SD_STS) &
634 SD_STS_FIFO_READY))
635 nwait++;
636 }
637 if (!nwait)
638 break;
639 cpu_relax();
640 }
641 } else {
642 /* wait until all RUN bits are cleared */
643 for (timeout = 5000; timeout; timeout--) {
644 nwait = 0;
645 snd_pcm_group_for_each_entry(s, substream) {
646 if (s->pcm->card != substream->pcm->card)
647 continue;
648 azx_dev = get_azx_dev(s);
649 if (azx_sd_readb(chip, azx_dev, SD_CTL) &
650 SD_CTL_DMA_START)
651 nwait++;
652 }
653 if (!nwait)
654 break;
655 cpu_relax();
656 }
657 }
658 spin_lock(&chip->reg_lock);
659 /* reset SYNC bits */
660 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
661 azx_writel(chip, OLD_SSYNC,
662 azx_readl(chip, OLD_SSYNC) & ~sbits);
663 else
664 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
665 if (start) {
666 azx_timecounter_init(substream, 0, 0);
ed610af8
PLB		 667 snd_pcm_gettime(substream->runtime, &substream->runtime->trigger_tstamp);
668 substream->runtime->trigger_tstamp_latched = true;
669
05e84878
DR		 670 if (nsync > 1) {
671 cycle_t cycle_last;
672
673 /* same start cycle for master and group */
674 azx_dev = get_azx_dev(substream);
675 cycle_last = azx_dev->azx_tc.cycle_last;
676
677 snd_pcm_group_for_each_entry(s, substream) {
678 if (s->pcm->card != substream->pcm->card)
679 continue;
680 azx_timecounter_init(s, 1, cycle_last);
681 }
682 }
683 }
684 spin_unlock(&chip->reg_lock);
685 return 0;
686}
687
b6050ef6 688unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
05e84878 689{
b6050ef6
TI		 690 return azx_sd_readl(chip, azx_dev, SD_LPIB);
691}
692EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
05e84878 693
b6050ef6
TI		 694unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
695{
696 return le32_to_cpu(*azx_dev->posbuf);
05e84878 697}
b6050ef6 698EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
05e84878
DR		 699
700unsigned int azx_get_position(struct azx *chip,
b6050ef6 701 struct azx_dev *azx_dev)
05e84878
DR		 702{
703 struct snd_pcm_substream *substream = azx_dev->substream;
05e84878
DR		 704 unsigned int pos;
705 int stream = substream->stream;
05e84878
DR		 706 int delay = 0;
707
b6050ef6
TI		 708 if (chip->get_position[stream])
709 pos = chip->get_position[stream](chip, azx_dev);
710 else /* use the position buffer as default */
711 pos = azx_get_pos_posbuf(chip, azx_dev);
05e84878
DR		 712
713 if (pos >= azx_dev->bufsize)
714 pos = 0;
715
05e84878 716 if (substream->runtime) {
b6050ef6 717 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
820cc6cf 718 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
b6050ef6
TI		 719
720 if (chip->get_delay[stream])
721 delay += chip->get_delay[stream](chip, azx_dev, pos);
05e84878
DR		 722 if (hinfo->ops.get_delay)
723 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
724 substream);
725 substream->runtime->delay = delay;
726 }
727
728 trace_azx_get_position(chip, azx_dev, pos, delay);
729 return pos;
730}
731EXPORT_SYMBOL_GPL(azx_get_position);
732
733static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
734{
735 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
736 struct azx *chip = apcm->chip;
737 struct azx_dev *azx_dev = get_azx_dev(substream);
738 return bytes_to_frames(substream->runtime,
b6050ef6 739 azx_get_position(chip, azx_dev));
05e84878
DR		 740}
741
9e94df3a
PLB		 742static int azx_get_time_info(struct snd_pcm_substream *substream,
743 struct timespec *system_ts, struct timespec *audio_ts,
744 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
745 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
05e84878
DR		 746{
747 struct azx_dev *azx_dev = get_azx_dev(substream);
748 u64 nsec;
749
9e94df3a
PLB		 750 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
751 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
05e84878 752
9e94df3a
PLB		 753 snd_pcm_gettime(substream->runtime, system_ts);
754
755 nsec = timecounter_read(&azx_dev->azx_tc);
756 nsec = div_u64(nsec, 3); /* can be optimized */
757 if (audio_tstamp_config->report_delay)
758 nsec = azx_adjust_codec_delay(substream, nsec);
759
760 *audio_ts = ns_to_timespec(nsec);
761
762 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
763 audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
764 audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */
765
766 } else
767 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
05e84878
DR		 768
769 return 0;
770}
771
772static struct snd_pcm_hardware azx_pcm_hw = {
773 .info = (SNDRV_PCM_INFO_MMAP |
774 SNDRV_PCM_INFO_INTERLEAVED |
775 SNDRV_PCM_INFO_BLOCK_TRANSFER |
776 SNDRV_PCM_INFO_MMAP_VALID |
777 /* No full-resume yet implemented */
778 /* SNDRV_PCM_INFO_RESUME |*/
779 SNDRV_PCM_INFO_PAUSE |
780 SNDRV_PCM_INFO_SYNC_START |
9e94df3a
PLB		 781 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
782 SNDRV_PCM_INFO_HAS_LINK_ATIME |
05e84878
DR		 783 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
784 .formats = SNDRV_PCM_FMTBIT_S16_LE,
785 .rates = SNDRV_PCM_RATE_48000,
786 .rate_min = 48000,
787 .rate_max = 48000,
788 .channels_min = 2,
789 .channels_max = 2,
790 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
791 .period_bytes_min = 128,
792 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
793 .periods_min = 2,
794 .periods_max = AZX_MAX_FRAG,
795 .fifo_size = 0,
796};
797
798static int azx_pcm_open(struct snd_pcm_substream *substream)
799{
800 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
820cc6cf 801 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
05e84878
DR		 802 struct azx *chip = apcm->chip;
803 struct azx_dev *azx_dev;
804 struct snd_pcm_runtime *runtime = substream->runtime;
805 unsigned long flags;
806 int err;
807 int buff_step;
808
9a6246ff 809 snd_hda_codec_pcm_get(apcm->info);
05e84878
DR		 810 mutex_lock(&chip->open_mutex);
811 azx_dev = azx_assign_device(chip, substream);
812 if (azx_dev == NULL) {
61ca4107
TI		 813 err = -EBUSY;
814 goto unlock;
05e84878
DR		 815 }
816 runtime->hw = azx_pcm_hw;
817 runtime->hw.channels_min = hinfo->channels_min;
818 runtime->hw.channels_max = hinfo->channels_max;
819 runtime->hw.formats = hinfo->formats;
820 runtime->hw.rates = hinfo->rates;
821 snd_pcm_limit_hw_rates(runtime);
822 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
823
824 /* avoid wrap-around with wall-clock */
825 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
826 20,
827 178000000);
828
829 if (chip->align_buffer_size)
830 /* constrain buffer sizes to be multiple of 128
831 bytes. This is more efficient in terms of memory
832 access but isn't required by the HDA spec and
833 prevents users from specifying exact period/buffer
834 sizes. For example for 44.1kHz, a period size set
835 to 20ms will be rounded to 19.59ms. */
836 buff_step = 128;
837 else
838 /* Don't enforce steps on buffer sizes, still need to
839 be multiple of 4 bytes (HDA spec). Tested on Intel
840 HDA controllers, may not work on all devices where
841 option needs to be disabled */
842 buff_step = 4;
843
844 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
845 buff_step);
846 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
847 buff_step);
cc72da7d 848 snd_hda_power_up(apcm->codec);
61ca4107
TI		 849 if (hinfo->ops.open)
850 err = hinfo->ops.open(hinfo, apcm->codec, substream);
851 else
852 err = -ENODEV;
05e84878
DR		 853 if (err < 0) {
854 azx_release_device(azx_dev);
61ca4107 855 goto powerdown;
05e84878
DR		 856 }
857 snd_pcm_limit_hw_rates(runtime);
858 /* sanity check */
859 if (snd_BUG_ON(!runtime->hw.channels_min) ||
860 snd_BUG_ON(!runtime->hw.channels_max) ||
861 snd_BUG_ON(!runtime->hw.formats) ||
862 snd_BUG_ON(!runtime->hw.rates)) {
863 azx_release_device(azx_dev);
61ca4107
TI		 864 if (hinfo->ops.close)
865 hinfo->ops.close(hinfo, apcm->codec, substream);
866 err = -EINVAL;
867 goto powerdown;
05e84878
DR		 868 }
869
9e94df3a 870 /* disable LINK_ATIME timestamps for capture streams
05e84878 871 until we figure out how to handle digital inputs */
9e94df3a
PLB		 872 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
873 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
874 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
875 }
05e84878
DR		 876
877 spin_lock_irqsave(&chip->reg_lock, flags);
878 azx_dev->substream = substream;
879 azx_dev->running = 0;
880 spin_unlock_irqrestore(&chip->reg_lock, flags);
881
882 runtime->private_data = azx_dev;
883 snd_pcm_set_sync(substream);
884 mutex_unlock(&chip->open_mutex);
885 return 0;
61ca4107
TI		 886
887 powerdown:
888 snd_hda_power_down(apcm->codec);
889 unlock:
890 mutex_unlock(&chip->open_mutex);
9a6246ff 891 snd_hda_codec_pcm_put(apcm->info);
61ca4107 892 return err;
05e84878
DR		 893}
894
895static int azx_pcm_mmap(struct snd_pcm_substream *substream,
896 struct vm_area_struct *area)
897{
898 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
899 struct azx *chip = apcm->chip;
900 if (chip->ops->pcm_mmap_prepare)
901 chip->ops->pcm_mmap_prepare(substream, area);
902 return snd_pcm_lib_default_mmap(substream, area);
903}
904
905static struct snd_pcm_ops azx_pcm_ops = {
906 .open = azx_pcm_open,
907 .close = azx_pcm_close,
908 .ioctl = snd_pcm_lib_ioctl,
909 .hw_params = azx_pcm_hw_params,
910 .hw_free = azx_pcm_hw_free,
911 .prepare = azx_pcm_prepare,
912 .trigger = azx_pcm_trigger,
913 .pointer = azx_pcm_pointer,
9e94df3a 914 .get_time_info = azx_get_time_info,
05e84878
DR		 915 .mmap = azx_pcm_mmap,
916 .page = snd_pcm_sgbuf_ops_page,
917};
918
919static void azx_pcm_free(struct snd_pcm *pcm)
920{
921 struct azx_pcm *apcm = pcm->private_data;
922 if (apcm) {
923 list_del(&apcm->list);
820cc6cf 924 apcm->info->pcm = NULL;
05e84878
DR		 925 kfree(apcm);
926 }
927}
928
929#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
930
7c3e438a
DR		 931static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
932 struct hda_pcm *cpcm)
05e84878
DR		 933{
934 struct azx *chip = bus->private_data;
935 struct snd_pcm *pcm;
936 struct azx_pcm *apcm;
937 int pcm_dev = cpcm->device;
938 unsigned int size;
939 int s, err;
940
941 list_for_each_entry(apcm, &chip->pcm_list, list) {
942 if (apcm->pcm->device == pcm_dev) {
943 dev_err(chip->card->dev, "PCM %d already exists\n",
944 pcm_dev);
945 return -EBUSY;
946 }
947 }
948 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
949 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
950 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
951 &pcm);
952 if (err < 0)
953 return err;
954 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
955 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
956 if (apcm == NULL)
957 return -ENOMEM;
958 apcm->chip = chip;
959 apcm->pcm = pcm;
960 apcm->codec = codec;
820cc6cf 961 apcm->info = cpcm;
05e84878
DR		 962 pcm->private_data = apcm;
963 pcm->private_free = azx_pcm_free;
964 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
965 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
966 list_add_tail(&apcm->list, &chip->pcm_list);
967 cpcm->pcm = pcm;
968 for (s = 0; s < 2; s++) {
05e84878
DR		 969 if (cpcm->stream[s].substreams)
970 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
971 }
972 /* buffer pre-allocation */
973 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
974 if (size > MAX_PREALLOC_SIZE)
975 size = MAX_PREALLOC_SIZE;
976 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
977 chip->card->dev,
978 size, MAX_PREALLOC_SIZE);
05e84878
DR		 979 return 0;
980}
05e84878 981
6e85dddc
DR		 982/*
983 * CORB / RIRB interface
984 */
f19c3ec2 985static int azx_alloc_cmd_io(struct azx *chip)
6e85dddc 986{
6e85dddc 987 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
f4de8fe6
TI		 988 return chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
989 PAGE_SIZE, &chip->rb);
6e85dddc
DR		 990}
991EXPORT_SYMBOL_GPL(azx_alloc_cmd_io);
992
f43923ff 993static void azx_init_cmd_io(struct azx *chip)
6e85dddc
DR		 994{
995 int timeout;
996
997 spin_lock_irq(&chip->reg_lock);
998 /* CORB set up */
999 chip->corb.addr = chip->rb.addr;
1000 chip->corb.buf = (u32 *)chip->rb.area;
1001 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
1002 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1003
1004 /* set the corb size to 256 entries (ULI requires explicitly) */
1005 azx_writeb(chip, CORBSIZE, 0x02);
1006 /* set the corb write pointer to 0 */
1007 azx_writew(chip, CORBWP, 0);
1008
1009 /* reset the corb hw read pointer */
fb1d8ac2 1010 azx_writew(chip, CORBRP, AZX_CORBRP_RST);
6ba736dd
TI		 1011 if (!(chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)) {
1012 for (timeout = 1000; timeout > 0; timeout--) {
fb1d8ac2 1013 if ((azx_readw(chip, CORBRP) & AZX_CORBRP_RST) == AZX_CORBRP_RST)
6ba736dd
TI		 1014 break;
1015 udelay(1);
1016 }
1017 if (timeout <= 0)
1018 dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n",
1019 azx_readw(chip, CORBRP));
1020
1021 azx_writew(chip, CORBRP, 0);
1022 for (timeout = 1000; timeout > 0; timeout--) {
1023 if (azx_readw(chip, CORBRP) == 0)
1024 break;
1025 udelay(1);
1026 }
1027 if (timeout <= 0)
1028 dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n",
1029 azx_readw(chip, CORBRP));
6e85dddc 1030 }
6e85dddc
DR		 1031
1032 /* enable corb dma */
fb1d8ac2 1033 azx_writeb(chip, CORBCTL, AZX_CORBCTL_RUN);
6e85dddc
DR		 1034
1035 /* RIRB set up */
1036 chip->rirb.addr = chip->rb.addr + 2048;
1037 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
1038 chip->rirb.wp = chip->rirb.rp = 0;
1039 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1040 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
1041 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1042
1043 /* set the rirb size to 256 entries (ULI requires explicitly) */
1044 azx_writeb(chip, RIRBSIZE, 0x02);
1045 /* reset the rirb hw write pointer */
fb1d8ac2 1046 azx_writew(chip, RIRBWP, AZX_RIRBWP_RST);
6e85dddc
DR		 1047 /* set N=1, get RIRB response interrupt for new entry */
1048 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1049 azx_writew(chip, RINTCNT, 0xc0);
1050 else
1051 azx_writew(chip, RINTCNT, 1);
1052 /* enable rirb dma and response irq */
fb1d8ac2 1053 azx_writeb(chip, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
6e85dddc
DR		 1054 spin_unlock_irq(&chip->reg_lock);
1055}
1056EXPORT_SYMBOL_GPL(azx_init_cmd_io);
1057
f43923ff 1058static void azx_free_cmd_io(struct azx *chip)
6e85dddc
DR		 1059{
1060 spin_lock_irq(&chip->reg_lock);
1061 /* disable ringbuffer DMAs */
1062 azx_writeb(chip, RIRBCTL, 0);
1063 azx_writeb(chip, CORBCTL, 0);
1064 spin_unlock_irq(&chip->reg_lock);
1065}
1066EXPORT_SYMBOL_GPL(azx_free_cmd_io);
1067
1068static unsigned int azx_command_addr(u32 cmd)
1069{
1070 unsigned int addr = cmd >> 28;
1071
1072 if (addr >= AZX_MAX_CODECS) {
1073 snd_BUG();
1074 addr = 0;
1075 }
1076
1077 return addr;
1078}
1079
1080/* send a command */
1081static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1082{
1083 struct azx *chip = bus->private_data;
1084 unsigned int addr = azx_command_addr(val);
1085 unsigned int wp, rp;
1086
1087 spin_lock_irq(&chip->reg_lock);
1088
1089 /* add command to corb */
1090 wp = azx_readw(chip, CORBWP);
1091 if (wp == 0xffff) {
1092 /* something wrong, controller likely turned to D3 */
1093 spin_unlock_irq(&chip->reg_lock);
1094 return -EIO;
1095 }
1096 wp++;
fb1d8ac2 1097 wp %= AZX_MAX_CORB_ENTRIES;
6e85dddc
DR		 1098
1099 rp = azx_readw(chip, CORBRP);
1100 if (wp == rp) {
1101 /* oops, it's full */
1102 spin_unlock_irq(&chip->reg_lock);
1103 return -EAGAIN;
1104 }
1105
1106 chip->rirb.cmds[addr]++;
1107 chip->corb.buf[wp] = cpu_to_le32(val);
1108 azx_writew(chip, CORBWP, wp);
1109
1110 spin_unlock_irq(&chip->reg_lock);
1111
1112 return 0;
1113}
1114
fb1d8ac2 1115#define AZX_RIRB_EX_UNSOL_EV (1<<4)
6e85dddc
DR		 1116
1117/* retrieve RIRB entry - called from interrupt handler */
f0b1df88 1118static void azx_update_rirb(struct azx *chip)
6e85dddc
DR		 1119{
1120 unsigned int rp, wp;
1121 unsigned int addr;
1122 u32 res, res_ex;
1123
1124 wp = azx_readw(chip, RIRBWP);
1125 if (wp == 0xffff) {
1126 /* something wrong, controller likely turned to D3 */
1127 return;
1128 }
1129
1130 if (wp == chip->rirb.wp)
1131 return;
1132 chip->rirb.wp = wp;
1133
1134 while (chip->rirb.rp != wp) {
1135 chip->rirb.rp++;
fb1d8ac2 1136 chip->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
6e85dddc
DR		 1137
1138 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
1139 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
1140 res = le32_to_cpu(chip->rirb.buf[rp]);
1141 addr = res_ex & 0xf;
1142 if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
1143 dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d",
1144 res, res_ex,
1145 chip->rirb.rp, wp);
1146 snd_BUG();
fb1d8ac2 1147 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
6e85dddc
DR		 1148 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
1149 else if (chip->rirb.cmds[addr]) {
1150 chip->rirb.res[addr] = res;
1151 smp_wmb();
1152 chip->rirb.cmds[addr]--;
1153 } else if (printk_ratelimit()) {
1154 dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n",
1155 res, res_ex,
1156 chip->last_cmd[addr]);
1157 }
1158 }
1159}
6e85dddc
DR		 1160
1161/* receive a response */
1162static unsigned int azx_rirb_get_response(struct hda_bus *bus,
1163 unsigned int addr)
1164{
1165 struct azx *chip = bus->private_data;
1166 unsigned long timeout;
1167 unsigned long loopcounter;
1168 int do_poll = 0;
1169
1170 again:
1171 timeout = jiffies + msecs_to_jiffies(1000);
1172
1173 for (loopcounter = 0;; loopcounter++) {
1174 if (chip->polling_mode || do_poll) {
1175 spin_lock_irq(&chip->reg_lock);
1176 azx_update_rirb(chip);
1177 spin_unlock_irq(&chip->reg_lock);
1178 }
1179 if (!chip->rirb.cmds[addr]) {
1180 smp_rmb();
1181 bus->rirb_error = 0;
1182
1183 if (!do_poll)
1184 chip->poll_count = 0;
1185 return chip->rirb.res[addr]; /* the last value */
1186 }
1187 if (time_after(jiffies, timeout))
1188 break;
1189 if (bus->needs_damn_long_delay || loopcounter > 3000)
1190 msleep(2); /* temporary workaround */
1191 else {
1192 udelay(10);
1193 cond_resched();
1194 }
1195 }
1196
1197 if (!bus->no_response_fallback)
1198 return -1;
1199
1200 if (!chip->polling_mode && chip->poll_count < 2) {
1201 dev_dbg(chip->card->dev,
1202 "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
1203 chip->last_cmd[addr]);
1204 do_poll = 1;
1205 chip->poll_count++;
1206 goto again;
1207 }
1208
1209
1210 if (!chip->polling_mode) {
1211 dev_warn(chip->card->dev,
1212 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
1213 chip->last_cmd[addr]);
1214 chip->polling_mode = 1;
1215 goto again;
1216 }
1217
1218 if (chip->msi) {
1219 dev_warn(chip->card->dev,
1220 "No response from codec, disabling MSI: last cmd=0x%08x\n",
1221 chip->last_cmd[addr]);
1222 if (chip->ops->disable_msi_reset_irq(chip) &&
1223 chip->ops->disable_msi_reset_irq(chip) < 0) {
1224 bus->rirb_error = 1;
1225 return -1;
1226 }
1227 goto again;
1228 }
1229
1230 if (chip->probing) {
1231 /* If this critical timeout happens during the codec probing
1232 * phase, this is likely an access to a non-existing codec
1233 * slot. Better to return an error and reset the system.
1234 */
1235 return -1;
1236 }
1237
1238 /* a fatal communication error; need either to reset or to fallback
1239 * to the single_cmd mode
1240 */
1241 bus->rirb_error = 1;
1242 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
1243 bus->response_reset = 1;
1244 return -1; /* give a chance to retry */
1245 }
1246
1247 dev_err(chip->card->dev,
1248 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
1249 chip->last_cmd[addr]);
1250 chip->single_cmd = 1;
1251 bus->response_reset = 0;
1252 /* release CORB/RIRB */
1253 azx_free_cmd_io(chip);
1254 /* disable unsolicited responses */
fb1d8ac2 1255 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_UNSOL);
6e85dddc
DR		 1256 return -1;
1257}
1258
1259/*
1260 * Use the single immediate command instead of CORB/RIRB for simplicity
1261 *
1262 * Note: according to Intel, this is not preferred use. The command was
1263 * intended for the BIOS only, and may get confused with unsolicited
1264 * responses. So, we shouldn't use it for normal operation from the
1265 * driver.
1266 * I left the codes, however, for debugging/testing purposes.
1267 */
1268
1269/* receive a response */
1270static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1271{
1272 int timeout = 50;
1273
1274 while (timeout--) {
1275 /* check IRV busy bit */
fb1d8ac2 1276 if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
6e85dddc
DR		 1277 /* reuse rirb.res as the response return value */
1278 chip->rirb.res[addr] = azx_readl(chip, IR);
1279 return 0;
1280 }
1281 udelay(1);
1282 }
1283 if (printk_ratelimit())
1284 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
1285 azx_readw(chip, IRS));
1286 chip->rirb.res[addr] = -1;
1287 return -EIO;
1288}
1289
1290/* send a command */
1291static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1292{
1293 struct azx *chip = bus->private_data;
1294 unsigned int addr = azx_command_addr(val);
1295 int timeout = 50;
1296
1297 bus->rirb_error = 0;
1298 while (timeout--) {
1299 /* check ICB busy bit */
fb1d8ac2 1300 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
6e85dddc
DR		 1301 /* Clear IRV valid bit */
1302 azx_writew(chip, IRS, azx_readw(chip, IRS) |
fb1d8ac2 1303 AZX_IRS_VALID);
6e85dddc
DR		 1304 azx_writel(chip, IC, val);
1305 azx_writew(chip, IRS, azx_readw(chip, IRS) |
fb1d8ac2 1306 AZX_IRS_BUSY);
6e85dddc
DR		 1307 return azx_single_wait_for_response(chip, addr);
1308 }
1309 udelay(1);
1310 }
1311 if (printk_ratelimit())
1312 dev_dbg(chip->card->dev,
1313 "send_cmd timeout: IRS=0x%x, val=0x%x\n",
1314 azx_readw(chip, IRS), val);
1315 return -EIO;
1316}
1317
1318/* receive a response */
1319static unsigned int azx_single_get_response(struct hda_bus *bus,
1320 unsigned int addr)
1321{
1322 struct azx *chip = bus->private_data;
1323 return chip->rirb.res[addr];
1324}
1325
1326/*
1327 * The below are the main callbacks from hda_codec.
1328 *
1329 * They are just the skeleton to call sub-callbacks according to the
1330 * current setting of chip->single_cmd.
1331 */
1332
1333/* send a command */
154867cf 1334static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
6e85dddc
DR		 1335{
1336 struct azx *chip = bus->private_data;
1337
1338 if (chip->disabled)
1339 return 0;
1340 chip->last_cmd[azx_command_addr(val)] = val;
1341 if (chip->single_cmd)
1342 return azx_single_send_cmd(bus, val);
1343 else
1344 return azx_corb_send_cmd(bus, val);
1345}
1346EXPORT_SYMBOL_GPL(azx_send_cmd);
1347
1348/* get a response */
154867cf 1349static unsigned int azx_get_response(struct hda_bus *bus,
6e85dddc
DR		 1350 unsigned int addr)
1351{
1352 struct azx *chip = bus->private_data;
1353 if (chip->disabled)
1354 return 0;
1355 if (chip->single_cmd)
1356 return azx_single_get_response(bus, addr);
1357 else
1358 return azx_rirb_get_response(bus, addr);
1359}
1360EXPORT_SYMBOL_GPL(azx_get_response);
1361
2b5fd6c2
DR		 1362#ifdef CONFIG_SND_HDA_DSP_LOADER
1363/*
1364 * DSP loading code (e.g. for CA0132)
1365 */
1366
1367/* use the first stream for loading DSP */
1368static struct azx_dev *
1369azx_get_dsp_loader_dev(struct azx *chip)
1370{
1371 return &chip->azx_dev[chip->playback_index_offset];
1372}
1373
154867cf
DR		 1374static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1375 unsigned int byte_size,
1376 struct snd_dma_buffer *bufp)
2b5fd6c2
DR		 1377{
1378 u32 *bdl;
1379 struct azx *chip = bus->private_data;
1380 struct azx_dev *azx_dev;
1381 int err;
1382
1383 azx_dev = azx_get_dsp_loader_dev(chip);
1384
1385 dsp_lock(azx_dev);
1386 spin_lock_irq(&chip->reg_lock);
1387 if (azx_dev->running || azx_dev->locked) {
1388 spin_unlock_irq(&chip->reg_lock);
1389 err = -EBUSY;
1390 goto unlock;
1391 }
1392 azx_dev->prepared = 0;
1393 chip->saved_azx_dev = *azx_dev;
1394 azx_dev->locked = 1;
1395 spin_unlock_irq(&chip->reg_lock);
1396
1397 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV_SG,
1398 byte_size, bufp);
1399 if (err < 0)
1400 goto err_alloc;
1401
1402 azx_dev->bufsize = byte_size;
1403 azx_dev->period_bytes = byte_size;
1404 azx_dev->format_val = format;
1405
1406 azx_stream_reset(chip, azx_dev);
1407
1408 /* reset BDL address */
1409 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1410 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1411
1412 azx_dev->frags = 0;
1413 bdl = (u32 *)azx_dev->bdl.area;
1414 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
1415 if (err < 0)
1416 goto error;
1417
1418 azx_setup_controller(chip, azx_dev);
1419 dsp_unlock(azx_dev);
1420 return azx_dev->stream_tag;
1421
1422 error:
1423 chip->ops->dma_free_pages(chip, bufp);
1424 err_alloc:
1425 spin_lock_irq(&chip->reg_lock);
1426 if (azx_dev->opened)
1427 *azx_dev = chip->saved_azx_dev;
1428 azx_dev->locked = 0;
1429 spin_unlock_irq(&chip->reg_lock);
1430 unlock:
1431 dsp_unlock(azx_dev);
1432 return err;
1433}
2b5fd6c2 1434
154867cf 1435static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2b5fd6c2
DR		 1436{
1437 struct azx *chip = bus->private_data;
1438 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1439
1440 if (start)
1441 azx_stream_start(chip, azx_dev);
1442 else
1443 azx_stream_stop(chip, azx_dev);
1444 azx_dev->running = start;
1445}
2b5fd6c2 1446
154867cf
DR		 1447static void azx_load_dsp_cleanup(struct hda_bus *bus,
1448 struct snd_dma_buffer *dmab)
2b5fd6c2
DR		 1449{
1450 struct azx *chip = bus->private_data;
1451 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1452
1453 if (!dmab->area || !azx_dev->locked)
1454 return;
1455
1456 dsp_lock(azx_dev);
1457 /* reset BDL address */
1458 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1459 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1460 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
1461 azx_dev->bufsize = 0;
1462 azx_dev->period_bytes = 0;
1463 azx_dev->format_val = 0;
1464
1465 chip->ops->dma_free_pages(chip, dmab);
1466 dmab->area = NULL;
1467
1468 spin_lock_irq(&chip->reg_lock);
1469 if (azx_dev->opened)
1470 *azx_dev = chip->saved_azx_dev;
1471 azx_dev->locked = 0;
1472 spin_unlock_irq(&chip->reg_lock);
1473 dsp_unlock(azx_dev);
1474}
2b5fd6c2
DR		 1475#endif /* CONFIG_SND_HDA_DSP_LOADER */
1476
67908994
DR		 1477int azx_alloc_stream_pages(struct azx *chip)
1478{
1479 int i, err;
67908994
DR		 1480
1481 for (i = 0; i < chip->num_streams; i++) {
1482 dsp_lock_init(&chip->azx_dev[i]);
1483 /* allocate memory for the BDL for each stream */
1484 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
1485 BDL_SIZE,
1486 &chip->azx_dev[i].bdl);
f4de8fe6 1487 if (err < 0)
67908994 1488 return -ENOMEM;
67908994
DR		 1489 }
1490 /* allocate memory for the position buffer */
1491 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
1492 chip->num_streams * 8, &chip->posbuf);
f4de8fe6 1493 if (err < 0)
67908994 1494 return -ENOMEM;
f19c3ec2
DR		 1495
1496 /* allocate CORB/RIRB */
1497 err = azx_alloc_cmd_io(chip);
1498 if (err < 0)
1499 return err;
67908994
DR		 1500 return 0;
1501}
1502EXPORT_SYMBOL_GPL(azx_alloc_stream_pages);
1503
1504void azx_free_stream_pages(struct azx *chip)
1505{
1506 int i;
1507 if (chip->azx_dev) {
1508 for (i = 0; i < chip->num_streams; i++)
1509 if (chip->azx_dev[i].bdl.area)
1510 chip->ops->dma_free_pages(
1511 chip, &chip->azx_dev[i].bdl);
1512 }
1513 if (chip->rb.area)
1514 chip->ops->dma_free_pages(chip, &chip->rb);
1515 if (chip->posbuf.area)
1516 chip->ops->dma_free_pages(chip, &chip->posbuf);
1517}
1518EXPORT_SYMBOL_GPL(azx_free_stream_pages);
1519
f43923ff
DR		 1520/*
1521 * Lowlevel interface
1522 */
1523
1524/* enter link reset */
1525void azx_enter_link_reset(struct azx *chip)
1526{
1527 unsigned long timeout;
1528
1529 /* reset controller */
fb1d8ac2 1530 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_RESET);
f43923ff
DR		 1531
1532 timeout = jiffies + msecs_to_jiffies(100);
fb1d8ac2 1533 while ((azx_readb(chip, GCTL) & AZX_GCTL_RESET) &&
f43923ff
DR		 1534 time_before(jiffies, timeout))
1535 usleep_range(500, 1000);
1536}
1537EXPORT_SYMBOL_GPL(azx_enter_link_reset);
1538
1539/* exit link reset */
1540static void azx_exit_link_reset(struct azx *chip)
1541{
1542 unsigned long timeout;
1543
fb1d8ac2 1544 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | AZX_GCTL_RESET);
f43923ff
DR		 1545
1546 timeout = jiffies + msecs_to_jiffies(100);
1547 while (!azx_readb(chip, GCTL) &&
1548 time_before(jiffies, timeout))
1549 usleep_range(500, 1000);
1550}
1551
1552/* reset codec link */
17c3ad03 1553static int azx_reset(struct azx *chip, bool full_reset)
f43923ff
DR		 1554{
1555 if (!full_reset)
1556 goto __skip;
1557
1558 /* clear STATESTS */
1559 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1560
1561 /* reset controller */
1562 azx_enter_link_reset(chip);
1563
1564 /* delay for >= 100us for codec PLL to settle per spec
1565 * Rev 0.9 section 5.5.1
1566 */
1567 usleep_range(500, 1000);
1568
1569 /* Bring controller out of reset */
1570 azx_exit_link_reset(chip);
1571
1572 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1573 usleep_range(1000, 1200);
1574
1575 __skip:
1576 /* check to see if controller is ready */
1577 if (!azx_readb(chip, GCTL)) {
1578 dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n");
1579 return -EBUSY;
1580 }
1581
1582 /* Accept unsolicited responses */
1583 if (!chip->single_cmd)
1584 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
fb1d8ac2 1585 AZX_GCTL_UNSOL);
f43923ff
DR		 1586
1587 /* detect codecs */
1588 if (!chip->codec_mask) {
1589 chip->codec_mask = azx_readw(chip, STATESTS);
1590 dev_dbg(chip->card->dev, "codec_mask = 0x%x\n",
1591 chip->codec_mask);
1592 }
1593
1594 return 0;
1595}
1596
1597/* enable interrupts */
1598static void azx_int_enable(struct azx *chip)
1599{
1600 /* enable controller CIE and GIE */
1601 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
fb1d8ac2 1602 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
f43923ff
DR		 1603}
1604
1605/* disable interrupts */
1606static void azx_int_disable(struct azx *chip)
1607{
1608 int i;
1609
1610 /* disable interrupts in stream descriptor */
1611 for (i = 0; i < chip->num_streams; i++) {
1612 struct azx_dev *azx_dev = &chip->azx_dev[i];
1613 azx_sd_writeb(chip, azx_dev, SD_CTL,
1614 azx_sd_readb(chip, azx_dev, SD_CTL) &
1615 ~SD_INT_MASK);
1616 }
1617
1618 /* disable SIE for all streams */
1619 azx_writeb(chip, INTCTL, 0);
1620
1621 /* disable controller CIE and GIE */
1622 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
fb1d8ac2 1623 ~(AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN));
f43923ff
DR		 1624}
1625
1626/* clear interrupts */
1627static void azx_int_clear(struct azx *chip)
1628{
1629 int i;
1630
1631 /* clear stream status */
1632 for (i = 0; i < chip->num_streams; i++) {
1633 struct azx_dev *azx_dev = &chip->azx_dev[i];
1634 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
1635 }
1636
1637 /* clear STATESTS */
1638 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1639
1640 /* clear rirb status */
1641 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1642
1643 /* clear int status */
fb1d8ac2 1644 azx_writel(chip, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
f43923ff
DR		 1645}
1646
1647/*
1648 * reset and start the controller registers
1649 */
17c3ad03 1650void azx_init_chip(struct azx *chip, bool full_reset)
f43923ff
DR		 1651{
1652 if (chip->initialized)
1653 return;
1654
1655 /* reset controller */
1656 azx_reset(chip, full_reset);
1657
1658 /* initialize interrupts */
1659 azx_int_clear(chip);
1660 azx_int_enable(chip);
1661
1662 /* initialize the codec command I/O */
1663 if (!chip->single_cmd)
1664 azx_init_cmd_io(chip);
1665
1666 /* program the position buffer */
1667 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1668 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1669
1670 chip->initialized = 1;
1671}
1672EXPORT_SYMBOL_GPL(azx_init_chip);
1673
1674void azx_stop_chip(struct azx *chip)
1675{
1676 if (!chip->initialized)
1677 return;
1678
1679 /* disable interrupts */
1680 azx_int_disable(chip);
1681 azx_int_clear(chip);
1682
1683 /* disable CORB/RIRB */
1684 azx_free_cmd_io(chip);
1685
1686 /* disable position buffer */
1687 azx_writel(chip, DPLBASE, 0);
1688 azx_writel(chip, DPUBASE, 0);
1689
1690 chip->initialized = 0;
1691}
154867cf 1692EXPORT_SYMBOL_GPL(azx_stop_chip);
f43923ff 1693
f0b1df88
DR		 1694/*
1695 * interrupt handler
1696 */
1697irqreturn_t azx_interrupt(int irq, void *dev_id)
1698{
1699 struct azx *chip = dev_id;
1700 struct azx_dev *azx_dev;
1701 u32 status;
1702 u8 sd_status;
1703 int i;
1704
641d334b 1705#ifdef CONFIG_PM
364aa716 1706 if (azx_has_pm_runtime(chip))
7b0a48f3 1707 if (!pm_runtime_active(chip->card->dev))
f0b1df88
DR		 1708 return IRQ_NONE;
1709#endif
1710
1711 spin_lock(&chip->reg_lock);
1712
1713 if (chip->disabled) {
1714 spin_unlock(&chip->reg_lock);
1715 return IRQ_NONE;
1716 }
1717
1718 status = azx_readl(chip, INTSTS);
1719 if (status == 0 || status == 0xffffffff) {
1720 spin_unlock(&chip->reg_lock);
1721 return IRQ_NONE;
1722 }
1723
1724 for (i = 0; i < chip->num_streams; i++) {
1725 azx_dev = &chip->azx_dev[i];
1726 if (status & azx_dev->sd_int_sta_mask) {
1727 sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
1728 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
1729 if (!azx_dev->substream || !azx_dev->running ||
1730 !(sd_status & SD_INT_COMPLETE))
1731 continue;
1732 /* check whether this IRQ is really acceptable */
1733 if (!chip->ops->position_check ||
1734 chip->ops->position_check(chip, azx_dev)) {
1735 spin_unlock(&chip->reg_lock);
1736 snd_pcm_period_elapsed(azx_dev->substream);
1737 spin_lock(&chip->reg_lock);
1738 }
1739 }
1740 }
1741
1742 /* clear rirb int */
1743 status = azx_readb(chip, RIRBSTS);
1744 if (status & RIRB_INT_MASK) {
1745 if (status & RIRB_INT_RESPONSE) {
1746 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1747 udelay(80);
1748 azx_update_rirb(chip);
1749 }
1750 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1751 }
1752
1753 spin_unlock(&chip->reg_lock);
1754
1755 return IRQ_HANDLED;
1756}
1757EXPORT_SYMBOL_GPL(azx_interrupt);
1758
154867cf
DR		 1759/*
1760 * Codec initerface
1761 */
1762
1763/*
1764 * Probe the given codec address
1765 */
1766static int probe_codec(struct azx *chip, int addr)
1767{
1768 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1769 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1770 unsigned int res;
1771
1772 mutex_lock(&chip->bus->cmd_mutex);
1773 chip->probing = 1;
1774 azx_send_cmd(chip->bus, cmd);
1775 res = azx_get_response(chip->bus, addr);
1776 chip->probing = 0;
1777 mutex_unlock(&chip->bus->cmd_mutex);
1778 if (res == -1)
1779 return -EIO;
1780 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1781 return 0;
1782}
1783
1784static void azx_bus_reset(struct hda_bus *bus)
1785{
1786 struct azx *chip = bus->private_data;
1787
1788 bus->in_reset = 1;
1789 azx_stop_chip(chip);
17c3ad03 1790 azx_init_chip(chip, true);
59ed1ead
TI		 1791 if (chip->initialized)
1792 snd_hda_bus_reset(chip->bus);
154867cf
DR		 1793 bus->in_reset = 0;
1794}
1795
154867cf
DR		 1796static int get_jackpoll_interval(struct azx *chip)
1797{
1798 int i;
1799 unsigned int j;
1800
1801 if (!chip->jackpoll_ms)
1802 return 0;
1803
1804 i = chip->jackpoll_ms[chip->dev_index];
1805 if (i == 0)
1806 return 0;
1807 if (i < 50 || i > 60000)
1808 j = 0;
1809 else
1810 j = msecs_to_jiffies(i);
1811 if (j == 0)
1812 dev_warn(chip->card->dev,
1813 "jackpoll_ms value out of range: %d\n", i);
1814 return j;
1815}
1816
ef744978
TI		 1817static struct hda_bus_ops bus_ops = {
1818 .command = azx_send_cmd,
1819 .get_response = azx_get_response,
1820 .attach_pcm = azx_attach_pcm_stream,
1821 .bus_reset = azx_bus_reset,
ef744978
TI		 1822#ifdef CONFIG_SND_HDA_DSP_LOADER
1823 .load_dsp_prepare = azx_load_dsp_prepare,
1824 .load_dsp_trigger = azx_load_dsp_trigger,
1825 .load_dsp_cleanup = azx_load_dsp_cleanup,
1826#endif
1827};
1828
96d2bd6e 1829/* HD-audio bus initialization */
bb573928 1830int azx_bus_create(struct azx *chip, const char *model)
154867cf 1831{
ef744978 1832 struct hda_bus *bus;
96d2bd6e 1833 int err;
154867cf 1834
ef744978 1835 err = snd_hda_bus_new(chip->card, &bus);
154867cf
DR		 1836 if (err < 0)
1837 return err;
1838
ef744978
TI		 1839 chip->bus = bus;
1840 bus->private_data = chip;
1841 bus->pci = chip->pci;
1842 bus->modelname = model;
1843 bus->ops = bus_ops;
ef744978 1844
154867cf
DR		 1845 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1846 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
ef744978 1847 bus->needs_damn_long_delay = 1;
154867cf
DR		 1848 }
1849
96d2bd6e
TI		 1850 /* AMD chipsets often cause the communication stalls upon certain
1851 * sequence like the pin-detection. It seems that forcing the synced
1852 * access works around the stall. Grrr...
1853 */
1854 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1855 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1856 bus->sync_write = 1;
1857 bus->allow_bus_reset = 1;
1858 }
1859
1860 return 0;
1861}
1862EXPORT_SYMBOL_GPL(azx_bus_create);
1863
1864/* Probe codecs */
1865int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
1866{
1867 struct hda_bus *bus = chip->bus;
1868 int c, codecs, err;
1869
154867cf
DR		 1870 codecs = 0;
1871 if (!max_slots)
1872 max_slots = AZX_DEFAULT_CODECS;
1873
1874 /* First try to probe all given codec slots */
1875 for (c = 0; c < max_slots; c++) {
1876 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1877 if (probe_codec(chip, c) < 0) {
1878 /* Some BIOSen give you wrong codec addresses
1879 * that don't exist
1880 */
1881 dev_warn(chip->card->dev,
1882 "Codec #%d probe error; disabling it...\n", c);
1883 chip->codec_mask &= ~(1 << c);
1884 /* More badly, accessing to a non-existing
1885 * codec often screws up the controller chip,
1886 * and disturbs the further communications.
1887 * Thus if an error occurs during probing,
1888 * better to reset the controller chip to
1889 * get back to the sanity state.
1890 */
1891 azx_stop_chip(chip);
17c3ad03 1892 azx_init_chip(chip, true);
154867cf
DR		 1893 }
1894 }
1895 }
1896
154867cf
DR		 1897 /* Then create codec instances */
1898 for (c = 0; c < max_slots; c++) {
1899 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1900 struct hda_codec *codec;
6efdd851 1901 err = snd_hda_codec_new(bus, bus->card, c, &codec);
154867cf
DR		 1902 if (err < 0)
1903 continue;
1904 codec->jackpoll_interval = get_jackpoll_interval(chip);
1905 codec->beep_mode = chip->beep_mode;
1906 codecs++;
1907 }
1908 }
1909 if (!codecs) {
1910 dev_err(chip->card->dev, "no codecs initialized\n");
1911 return -ENXIO;
1912 }
1913 return 0;
1914}
96d2bd6e 1915EXPORT_SYMBOL_GPL(azx_probe_codecs);
154867cf
DR		 1916
1917/* configure each codec instance */
1918int azx_codec_configure(struct azx *chip)
1919{
1920 struct hda_codec *codec;
1921 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1922 snd_hda_codec_configure(codec);
1923 }
1924 return 0;
1925}
1926EXPORT_SYMBOL_GPL(azx_codec_configure);
1927
154867cf 1928
93e3423e
RR		 1929static bool is_input_stream(struct azx *chip, unsigned char index)
1930{
1931 return (index >= chip->capture_index_offset &&
1932 index < chip->capture_index_offset + chip->capture_streams);
1933}
1934
154867cf
DR		 1935/* initialize SD streams */
1936int azx_init_stream(struct azx *chip)
1937{
1938 int i;
93e3423e
RR		 1939 int in_stream_tag = 0;
1940 int out_stream_tag = 0;
154867cf
DR		 1941
1942 /* initialize each stream (aka device)
1943 * assign the starting bdl address to each stream (device)
1944 * and initialize
1945 */
1946 for (i = 0; i < chip->num_streams; i++) {
1947 struct azx_dev *azx_dev = &chip->azx_dev[i];
1948 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1949 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1950 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1951 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1952 azx_dev->sd_int_sta_mask = 1 << i;
154867cf 1953 azx_dev->index = i;
93e3423e
RR		 1954
1955 /* stream tag must be unique throughout
1956 * the stream direction group,
1957 * valid values 1...15
1958 * use separate stream tag if the flag
1959 * AZX_DCAPS_SEPARATE_STREAM_TAG is used
1960 */
1961 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
1962 azx_dev->stream_tag =
1963 is_input_stream(chip, i) ?
1964 ++in_stream_tag :
1965 ++out_stream_tag;
1966 else
1967 azx_dev->stream_tag = i + 1;
154867cf
DR		 1968 }
1969
1970 return 0;
1971}
1972EXPORT_SYMBOL_GPL(azx_init_stream);
1973
05e84878 1974MODULE_LICENSE("GPL");
70462457 1975MODULE_DESCRIPTION("Common HDA driver functions");
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