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PCI: PM: Skip devices in D0 for suspend-to-idle
[mirror_ubuntu-bionic-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
7f80f513 56#include <asm/set_memory.h>
50279d9b 57#include <asm/cpufeature.h>
27fe48d9 58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
98d8fc6c
ML		 61#include <sound/hdaudio.h>
62#include <sound/hda_i915.h>
9121947d 63#include <linux/vgaarb.h>
a82d51ed 64#include <linux/vga_switcheroo.h>
4918cdab 65#include <linux/firmware.h>
1da177e4 66#include "hda_codec.h"
05e84878 67#include "hda_controller.h"
347de1f8 68#include "hda_intel.h"
1da177e4 69
785d8c4b
LY		 70#define CREATE_TRACE_POINTS
71#include "hda_intel_trace.h"
72
b6050ef6
TI		 73/* position fix mode */
74enum {
75 POS_FIX_AUTO,
76 POS_FIX_LPIB,
77 POS_FIX_POSBUF,
78 POS_FIX_VIACOMBO,
79 POS_FIX_COMBO,
f87e7f25 80 POS_FIX_SKL,
b6050ef6
TI		 81};
82
9a34af4a
TI		 83/* Defines for ATI HD Audio support in SB450 south bridge */
84#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
85#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
86
87/* Defines for Nvidia HDA support */
88#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
89#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
90#define NVIDIA_HDA_ISTRM_COH 0x4d
91#define NVIDIA_HDA_OSTRM_COH 0x4c
92#define NVIDIA_HDA_ENABLE_COHBIT 0x01
93
94/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 95#define INTEL_HDA_CGCTL 0x48
96#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 97#define INTEL_SCH_HDA_DEVC 0x78
98#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
99
100/* Define IN stream 0 FIFO size offset in VIA controller */
101#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
102/* Define VIA HD Audio Device ID*/
103#define VIA_HDAC_DEVICE_ID 0x3288
104
33124929
TI		 105/* max number of SDs */
106/* ICH, ATI and VIA have 4 playback and 4 capture */
107#define ICH6_NUM_CAPTURE 4
108#define ICH6_NUM_PLAYBACK 4
109
110/* ULI has 6 playback and 5 capture */
111#define ULI_NUM_CAPTURE 5
112#define ULI_NUM_PLAYBACK 6
113
114/* ATI HDMI may have up to 8 playbacks and 0 capture */
115#define ATIHDMI_NUM_CAPTURE 0
116#define ATIHDMI_NUM_PLAYBACK 8
117
118/* TERA has 4 playback and 3 capture */
119#define TERA_NUM_CAPTURE 3
120#define TERA_NUM_PLAYBACK 4
121
1da177e4 122
5aba4f8e
TI		 123static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
124static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 125static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 126static char *model[SNDRV_CARDS];
1dac6695 127static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 128static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 129static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 130static int probe_only[SNDRV_CARDS];
26a6cb6c 131static int jackpoll_ms[SNDRV_CARDS];
41438f13 132static int single_cmd = -1;
71623855 133static int enable_msi = -1;
4ea6fbc8
TI		 134#ifdef CONFIG_SND_HDA_PATCH_LOADER
135static char *patch[SNDRV_CARDS];
136#endif
2dca0bba 137#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 138static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 139 CONFIG_SND_HDA_INPUT_BEEP_MODE};
140#endif
1da177e4 141
5aba4f8e 142module_param_array(index, int, NULL, 0444);
1da177e4 143MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 144module_param_array(id, charp, NULL, 0444);
1da177e4 145MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 146module_param_array(enable, bool, NULL, 0444);
147MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
148module_param_array(model, charp, NULL, 0444);
1da177e4 149MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 150module_param_array(position_fix, int, NULL, 0444);
4cb36310 151MODULE_PARM_DESC(position_fix, "DMA pointer read method."
f87e7f25 152 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
555e219f
TI		 153module_param_array(bdl_pos_adj, int, NULL, 0644);
154MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 155module_param_array(probe_mask, int, NULL, 0444);
606ad75f 156MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 157module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 158MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 159module_param_array(jackpoll_ms, int, NULL, 0444);
160MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 161module_param(single_cmd, bint, 0444);
d01ce99f
TI		 162MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
163 "(for debugging only).");
ac9ef6cf 164module_param(enable_msi, bint, 0444);
134a11f0 165MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 166#ifdef CONFIG_SND_HDA_PATCH_LOADER
167module_param_array(patch, charp, NULL, 0444);
168MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
169#endif
2dca0bba 170#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 171module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 172MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 173 "(0=off, 1=on) (default=1).");
2dca0bba 174#endif
606ad75f 175
83012a7c 176#ifdef CONFIG_PM
65fcd41d 177static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 178static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 179 .set = param_set_xint,
180 .get = param_get_int,
181};
182#define param_check_xint param_check_int
183
027ac1e7 184static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 185module_param(power_save, xint, 0644);
fee2fba3
TI		 186MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
187 "(in second, 0 = disable).");
1da177e4 188
027ac1e7
TI		 189static bool pm_blacklist = true;
190module_param(pm_blacklist, bool, 0644);
191MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
192
dee1b66c
TI		 193/* reset the HD-audio controller in power save mode.
194 * this may give more power-saving, but will take longer time to
195 * wake up.
196 */
8fc24426
TI		 197static bool power_save_controller = 1;
198module_param(power_save_controller, bool, 0644);
dee1b66c 199MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 200#else
bb573928 201#define power_save 0
83012a7c 202#endif /* CONFIG_PM */
dee1b66c 203
7bfe059e
TI		 204static int align_buffer_size = -1;
205module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 206MODULE_PARM_DESC(align_buffer_size,
207 "Force buffer and period sizes to be multiple of 128 bytes.");
208
27fe48d9 209#ifdef CONFIG_X86
7c732015
TI		 210static int hda_snoop = -1;
211module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 212MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 213#else
214#define hda_snoop true
27fe48d9
TI		 215#endif
216
217
1da177e4
LT		 218MODULE_LICENSE("GPL");
219MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
220 "{Intel, ICH6M},"
2f1b3818 221 "{Intel, ICH7},"
f5d40b30 222 "{Intel, ESB2},"
d2981393 223 "{Intel, ICH8},"
f9cc8a8b 224 "{Intel, ICH9},"
c34f5a04 225 "{Intel, ICH10},"
b29c2360 226 "{Intel, PCH},"
d2f2fcd2 227 "{Intel, CPT},"
d2edeb7c 228 "{Intel, PPT},"
8bc039a1 229 "{Intel, LPT},"
144dad99 230 "{Intel, LPT_LP},"
4eeca499 231 "{Intel, WPT_LP},"
c8b00fd2 232 "{Intel, SPT},"
b4565913 233 "{Intel, SPT_LP},"
e926f2c8 234 "{Intel, HPT},"
cea310e8 235 "{Intel, PBG},"
4979bca9 236 "{Intel, SCH},"
fc20a562 237 "{ATI, SB450},"
89be83f8 238 "{ATI, SB600},"
778b6e1b 239 "{ATI, RS600},"
5b15c95f 240 "{ATI, RS690},"
e6db1119
WL		 241 "{ATI, RS780},"
242 "{ATI, R600},"
2797f724
HRK		 243 "{ATI, RV630},"
244 "{ATI, RV610},"
27da1834
WL		 245 "{ATI, RV670},"
246 "{ATI, RV635},"
247 "{ATI, RV620},"
248 "{ATI, RV770},"
fc20a562 249 "{VIA, VT8251},"
47672310 250 "{VIA, VT8237A},"
07e4ca50
TI		 251 "{SiS, SIS966},"
252 "{ULI, M5461}}");
1da177e4
LT		 253MODULE_DESCRIPTION("Intel HDA driver");
254
a82d51ed 255#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 256#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 257#define SUPPORT_VGA_SWITCHEROO
258#endif
259#endif
260
261
1da177e4 262/*
1da177e4 263 */
1da177e4 264
07e4ca50
TI		 265/* driver types */
266enum {
267 AZX_DRIVER_ICH,
32679f95 268 AZX_DRIVER_PCH,
4979bca9 269 AZX_DRIVER_SCH,
a4b4793f 270 AZX_DRIVER_SKL,
fab1285a 271 AZX_DRIVER_HDMI,
07e4ca50 272 AZX_DRIVER_ATI,
778b6e1b 273 AZX_DRIVER_ATIHDMI,
1815b34a 274 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 275 AZX_DRIVER_VIA,
276 AZX_DRIVER_SIS,
277 AZX_DRIVER_ULI,
da3fca21 278 AZX_DRIVER_NVIDIA,
f269002e 279 AZX_DRIVER_TERA,
14d34f16 280 AZX_DRIVER_CTX,
5ae763b1 281 AZX_DRIVER_CTHDA,
c563f473 282 AZX_DRIVER_CMEDIA,
c4da29ca 283 AZX_DRIVER_GENERIC,
2f5983f2 284 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 285};
286
37e661ee
TI		 287#define azx_get_snoop_type(chip) \
288 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
289#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
290
b42b4afb
TI		 291/* quirks for old Intel chipsets */
292#define AZX_DCAPS_INTEL_ICH \
103884a3 293 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 294
2ea3c6a2 295/* quirks for Intel PCH */
6603249d 296#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 297 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
bcb337d1 298 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 299
dba9b7b6 300/* PCH up to IVB; no runtime PM; bind with i915 gfx */
6603249d 301#define AZX_DCAPS_INTEL_PCH_NOPM \
dba9b7b6 302 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
6603249d 303
55913110 304/* PCH for HSW/BDW; with runtime PM */
dba9b7b6 305/* no i915 binding for this as HSW/BDW has another controller for HDMI */
d7dab4db 306#define AZX_DCAPS_INTEL_PCH \
6603249d 307 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 308
6603249d 309/* HSW HDMI */
33499a15 310#define AZX_DCAPS_INTEL_HASWELL \
103884a3 311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
dba9b7b6
TI		 312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
313 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 314
54a0405d
LY		 315/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
316#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 317 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
dba9b7b6
TI		 318 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
319 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 320
40cc2392 321#define AZX_DCAPS_INTEL_BAYTRAIL \
dba9b7b6
TI		 322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
323 AZX_DCAPS_I915_POWERWELL)
40cc2392 324
2d846c74 325#define AZX_DCAPS_INTEL_BRASWELL \
dba9b7b6
TI		 326 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
327 AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
2d846c74 328
d6795827 329#define AZX_DCAPS_INTEL_SKYLAKE \
dba9b7b6
TI		 330 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
331 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
2d846c74 332 AZX_DCAPS_I915_POWERWELL)
d6795827 333
c87693da 334#define AZX_DCAPS_INTEL_BROXTON \
dba9b7b6
TI		 335 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
336 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
c87693da
LH		 337 AZX_DCAPS_I915_POWERWELL)
338
9477c58e
TI		 339/* quirks for ATI SB / AMD Hudson */
340#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 341 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
342 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 343
344/* quirks for ATI/AMD HDMI */
345#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 346 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
347 AZX_DCAPS_NO_MSI64)
9477c58e 348
37e661ee
TI		 349/* quirks for ATI HDMI with snoop off */
350#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
351 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
352
9477c58e
TI		 353/* quirks for Nvidia */
354#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 355 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 356 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 357
5ae763b1 358#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 359 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 360 AZX_DCAPS_NO_64BIT |\
37e661ee 361 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 362
a82d51ed 363/*
2b760d88 364 * vga_switcheroo support
a82d51ed
TI		 365 */
366#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 367#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
368#else
369#define use_vga_switcheroo(chip) 0
370#endif
371
03b135ce
LY		 372#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
373 ((pci)->device == 0x0c0c) || \
374 ((pci)->device == 0x0d0c) || \
375 ((pci)->device == 0x160c))
376
7e31a015 377#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
12a3616f 378#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
7c23b7c1 379
48c8b0eb 380static char *driver_short_names[] = {
07e4ca50 381 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 382 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 383 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 384 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 385 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 386 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 387 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 388 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 389 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
390 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 391 [AZX_DRIVER_ULI] = "HDA ULI M5461",
392 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 393 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 394 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 395 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 396 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 397 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 398};
399
27fe48d9 400#ifdef CONFIG_X86
9ddf1aeb 401static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 402{
9ddf1aeb
TI		 403 int pages;
404
27fe48d9
TI		 405 if (azx_snoop(chip))
406 return;
9ddf1aeb
TI		 407 if (!dmab || !dmab->area || !dmab->bytes)
408 return;
409
410#ifdef CONFIG_SND_DMA_SGBUF
411 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
412 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 413 if (chip->driver_type == AZX_DRIVER_CMEDIA)
414 return; /* deal with only CORB/RIRB buffers */
27fe48d9 415 if (on)
9ddf1aeb 416 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 417 else
9ddf1aeb
TI		 418 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
419 return;
27fe48d9 420 }
9ddf1aeb
TI		 421#endif
422
423 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
424 if (on)
425 set_memory_wc((unsigned long)dmab->area, pages);
426 else
427 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 428}
429
430static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
431 bool on)
432{
9ddf1aeb 433 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 434}
435static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 436 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 437{
438 if (azx_dev->wc_marked != on) {
9ddf1aeb 439 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 440 azx_dev->wc_marked = on;
441 }
442}
443#else
444/* NOP for other archs */
445static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
446 bool on)
447{
448}
449static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 450 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 451{
452}
453#endif
454
68e7fffc 455static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 456
cb53c626
TI		 457/*
458 * initialize the PCI registers
459 */
460/* update bits in a PCI register byte */
461static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
462 unsigned char mask, unsigned char val)
463{
464 unsigned char data;
465
466 pci_read_config_byte(pci, reg, &data);
467 data &= ~mask;
468 data |= (val & mask);
469 pci_write_config_byte(pci, reg, data);
470}
471
472static void azx_init_pci(struct azx *chip)
473{
37e661ee
TI		 474 int snoop_type = azx_get_snoop_type(chip);
475
cb53c626
TI		 476 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
477 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
478 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 479 * codecs.
480 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 481 */
46f2cc80 482 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 483 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 484 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 485 }
cb53c626 486
9477c58e
TI		 487 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
488 * we need to enable snoop.
489 */
37e661ee 490 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 491 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
492 azx_snoop(chip));
cb53c626 493 update_pci_byte(chip->pci,
27fe48d9
TI		 494 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
495 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 496 }
497
498 /* For NVIDIA HDA, enable snoop */
37e661ee 499 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 500 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
501 azx_snoop(chip));
cb53c626
TI		 502 update_pci_byte(chip->pci,
503 NVIDIA_HDA_TRANSREG_ADDR,
504 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 505 update_pci_byte(chip->pci,
506 NVIDIA_HDA_ISTRM_COH,
507 0x01, NVIDIA_HDA_ENABLE_COHBIT);
508 update_pci_byte(chip->pci,
509 NVIDIA_HDA_OSTRM_COH,
510 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 511 }
512
513 /* Enable SCH/PCH snoop if needed */
37e661ee 514 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 515 unsigned short snoop;
90a5ad52 516 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 517 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
518 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
519 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
520 if (!azx_snoop(chip))
521 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
522 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 523 pci_read_config_word(chip->pci,
524 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 525 }
4e76a883
TI		 526 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
527 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
528 "Disabled" : "Enabled");
da3fca21 529 }
1da177e4
LT		 530}
531
7c23b7c1
LH		 532/*
533 * In BXT-P A0, HD-Audio DMA requests is later than expected,
534 * and makes an audio stream sensitive to system latencies when
535 * 24/32 bits are playing.
536 * Adjusting threshold of DMA fifo to force the DMA request
537 * sooner to improve latency tolerance at the expense of power.
538 */
539static void bxt_reduce_dma_latency(struct azx *chip)
540{
541 u32 val;
542
70eafad8 543 val = azx_readl(chip, VS_EM4L);
7c23b7c1 544 val &= (0x3 << 20);
70eafad8 545 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 546}
547
1f9d3d98
LY		 548/*
549 * ML_LCAP bits:
550 * bit 0: 6 MHz Supported
551 * bit 1: 12 MHz Supported
552 * bit 2: 24 MHz Supported
553 * bit 3: 48 MHz Supported
554 * bit 4: 96 MHz Supported
555 * bit 5: 192 MHz Supported
556 */
557static int intel_get_lctl_scf(struct azx *chip)
558{
559 struct hdac_bus *bus = azx_bus(chip);
560 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
561 u32 val, t;
562 int i;
563
564 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
565
566 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
567 t = preferred_bits[i];
568 if (val & (1 << t))
569 return t;
570 }
571
572 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
573 return 0;
574}
575
576static int intel_ml_lctl_set_power(struct azx *chip, int state)
577{
578 struct hdac_bus *bus = azx_bus(chip);
579 u32 val;
580 int timeout;
581
582 /*
583 * the codecs are sharing the first link setting by default
584 * If other links are enabled for stream, they need similar fix
585 */
586 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
587 val &= ~AZX_MLCTL_SPA;
588 val |= state << AZX_MLCTL_SPA_SHIFT;
589 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
590 /* wait for CPA */
591 timeout = 50;
592 while (timeout) {
593 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
594 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
595 return 0;
596 timeout--;
597 udelay(10);
598 }
599
600 return -1;
601}
602
603static void intel_init_lctl(struct azx *chip)
604{
605 struct hdac_bus *bus = azx_bus(chip);
606 u32 val;
607 int ret;
608
609 /* 0. check lctl register value is correct or not */
610 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
611 /* if SCF is already set, let's use it */
612 if ((val & ML_LCTL_SCF_MASK) != 0)
613 return;
614
615 /*
616 * Before operating on SPA, CPA must match SPA.
617 * Any deviation may result in undefined behavior.
618 */
619 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
620 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
621 return;
622
623 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
624 ret = intel_ml_lctl_set_power(chip, 0);
625 udelay(100);
626 if (ret)
627 goto set_spa;
628
629 /* 2. update SCF to select a properly audio clock*/
630 val &= ~ML_LCTL_SCF_MASK;
631 val |= intel_get_lctl_scf(chip);
632 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
633
634set_spa:
635 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
636 intel_ml_lctl_set_power(chip, 1);
637 udelay(100);
638}
639
0a673521
LH		 640static void hda_intel_init_chip(struct azx *chip, bool full_reset)
641{
98d8fc6c 642 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 643 struct pci_dev *pci = chip->pci;
6639484d 644 u32 val;
0a673521
LH		 645
646 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 647 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 648 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 649 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
650 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
651 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
652 }
0a673521 653 azx_init_chip(chip, full_reset);
a4b4793f 654 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 655 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
656 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
657 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
658 }
0a673521 659 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 660 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 661
662 /* reduce dma latency to avoid noise */
7e31a015 663 if (IS_BXT(pci))
7c23b7c1 664 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 665
666 if (bus->mlcap != NULL)
667 intel_init_lctl(chip);
0a673521
LH		 668}
669
b6050ef6
TI		 670/* calculate runtime delay from LPIB */
671static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
672 unsigned int pos)
673{
7833c3f8 674 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 675 int stream = substream->stream;
676 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
677 int delay;
678
679 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
680 delay = pos - lpib_pos;
681 else
682 delay = lpib_pos - pos;
683 if (delay < 0) {
7833c3f8 684 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 685 delay = 0;
686 else
7833c3f8 687 delay += azx_dev->core.bufsize;
b6050ef6
TI		 688 }
689
7833c3f8 690 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 691 dev_info(chip->card->dev,
692 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 693 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 694 delay = 0;
695 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
696 chip->get_delay[stream] = NULL;
697 }
698
699 return bytes_to_frames(substream->runtime, delay);
700}
701
9ad593f6
TI		 702static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
703
7ca954a8
DR		 704/* called from IRQ */
705static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
706{
9a34af4a 707 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 708 int ok;
709
710 ok = azx_position_ok(chip, azx_dev);
711 if (ok == 1) {
712 azx_dev->irq_pending = 0;
713 return ok;
2f35c630 714 } else if (ok == 0) {
7ca954a8
DR		 715 /* bogus IRQ, process it later */
716 azx_dev->irq_pending = 1;
2f35c630 717 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 718 }
719 return 0;
720}
721
17eccb27
ML		 722/* Enable/disable i915 display power for the link */
723static int azx_intel_link_power(struct azx *chip, bool enable)
724{
98d8fc6c 725 struct hdac_bus *bus = azx_bus(chip);
17eccb27 726
98d8fc6c 727 return snd_hdac_display_power(bus, enable);
17eccb27
ML		 728}
729
9ad593f6
TI		 730/*
731 * Check whether the current DMA position is acceptable for updating
732 * periods. Returns non-zero if it's OK.
733 *
734 * Many HD-audio controllers appear pretty inaccurate about
735 * the update-IRQ timing. The IRQ is issued before actually the
736 * data is processed. So, we need to process it afterwords in a
737 * workqueue.
738 */
739static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
740{
7833c3f8 741 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 742 int stream = substream->stream;
e5463720 743 u32 wallclk;
9ad593f6
TI		 744 unsigned int pos;
745
7833c3f8
TI		 746 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
747 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 748 return -1; /* bogus (too early) interrupt */
fa00e046 749
b6050ef6
TI		 750 if (chip->get_position[stream])
751 pos = chip->get_position[stream](chip, azx_dev);
752 else { /* use the position buffer as default */
753 pos = azx_get_pos_posbuf(chip, azx_dev);
754 if (!pos || pos == (u32)-1) {
755 dev_info(chip->card->dev,
756 "Invalid position buffer, using LPIB read method instead.\n");
757 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 758 if (chip->get_position[0] == azx_get_pos_lpib &&
759 chip->get_position[1] == azx_get_pos_lpib)
760 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 761 pos = azx_get_pos_lpib(chip, azx_dev);
762 chip->get_delay[stream] = NULL;
763 } else {
764 chip->get_position[stream] = azx_get_pos_posbuf;
765 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
766 chip->get_delay[stream] = azx_get_delay_from_lpib;
767 }
768 }
769
7833c3f8 770 if (pos >= azx_dev->core.bufsize)
b6050ef6 771 pos = 0;
9ad593f6 772
7833c3f8 773 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 774 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 775 return -1; /* this shouldn't happen! */
7833c3f8
TI		 776 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
777 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 778 /* NG - it's below the first next period boundary */
4f0189be 779 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 780 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 781 return 1; /* OK, it's fine */
782}
783
784/*
785 * The work for pending PCM period updates.
786 */
787static void azx_irq_pending_work(struct work_struct *work)
788{
9a34af4a
TI		 789 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
790 struct azx *chip = &hda->chip;
7833c3f8
TI		 791 struct hdac_bus *bus = azx_bus(chip);
792 struct hdac_stream *s;
793 int pending, ok;
9ad593f6 794
9a34af4a 795 if (!hda->irq_pending_warned) {
4e76a883
TI		 796 dev_info(chip->card->dev,
797 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
798 chip->card->number);
9a34af4a 799 hda->irq_pending_warned = 1;
a6a950a8
TI		 800 }
801
9ad593f6
TI		 802 for (;;) {
803 pending = 0;
a41d1224 804 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 805 list_for_each_entry(s, &bus->stream_list, list) {
806 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 807 if (!azx_dev->irq_pending ||
7833c3f8
TI		 808 !s->substream ||
809 !s->running)
9ad593f6 810 continue;
e5463720
JK		 811 ok = azx_position_ok(chip, azx_dev);
812 if (ok > 0) {
9ad593f6 813 azx_dev->irq_pending = 0;
a41d1224 814 spin_unlock(&bus->reg_lock);
7833c3f8 815 snd_pcm_period_elapsed(s->substream);
a41d1224 816 spin_lock(&bus->reg_lock);
e5463720
JK		 817 } else if (ok < 0) {
818 pending = 0; /* too early */
9ad593f6
TI		 819 } else
820 pending++;
821 }
a41d1224 822 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 823 if (!pending)
824 return;
08af495f 825 msleep(1);
9ad593f6
TI		 826 }
827}
828
829/* clear irq_pending flags and assure no on-going workq */
830static void azx_clear_irq_pending(struct azx *chip)
831{
7833c3f8
TI		 832 struct hdac_bus *bus = azx_bus(chip);
833 struct hdac_stream *s;
9ad593f6 834
a41d1224 835 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 836 list_for_each_entry(s, &bus->stream_list, list) {
837 struct azx_dev *azx_dev = stream_to_azx_dev(s);
838 azx_dev->irq_pending = 0;
839 }
a41d1224 840 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 841}
842
68e7fffc
TI		 843static int azx_acquire_irq(struct azx *chip, int do_disconnect)
844{
a41d1224
TI		 845 struct hdac_bus *bus = azx_bus(chip);
846
437a5a46
TI		 847 if (request_irq(chip->pci->irq, azx_interrupt,
848 chip->msi ? 0 : IRQF_SHARED,
de65360b 849 chip->card->irq_descr, chip)) {
4e76a883
TI		 850 dev_err(chip->card->dev,
851 "unable to grab IRQ %d, disabling device\n",
852 chip->pci->irq);
68e7fffc
TI		 853 if (do_disconnect)
854 snd_card_disconnect(chip->card);
855 return -1;
856 }
a41d1224 857 bus->irq = chip->pci->irq;
69e13418 858 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 859 return 0;
860}
861
b6050ef6
TI		 862/* get the current DMA position with correction on VIA chips */
863static unsigned int azx_via_get_position(struct azx *chip,
864 struct azx_dev *azx_dev)
865{
866 unsigned int link_pos, mini_pos, bound_pos;
867 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
868 unsigned int fifo_size;
869
1604eeee 870 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 871 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 872 /* Playback, no problem using link position */
873 return link_pos;
874 }
875
876 /* Capture */
877 /* For new chipset,
878 * use mod to get the DMA position just like old chipset
879 */
7833c3f8
TI		 880 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
881 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 882
883 /* azx_dev->fifo_size can't get FIFO size of in stream.
884 * Get from base address + offset.
885 */
a41d1224
TI		 886 fifo_size = readw(azx_bus(chip)->remap_addr +
887 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 888
889 if (azx_dev->insufficient) {
890 /* Link position never gather than FIFO size */
891 if (link_pos <= fifo_size)
892 return 0;
893
894 azx_dev->insufficient = 0;
895 }
896
897 if (link_pos <= fifo_size)
7833c3f8 898 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 899 else
900 mini_pos = link_pos - fifo_size;
901
902 /* Find nearest previous boudary */
7833c3f8
TI		 903 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
904 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 905 if (mod_link_pos >= fifo_size)
906 bound_pos = link_pos - mod_link_pos;
907 else if (mod_dma_pos >= mod_mini_pos)
908 bound_pos = mini_pos - mod_mini_pos;
909 else {
7833c3f8
TI		 910 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
911 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 912 bound_pos = 0;
913 }
914
915 /* Calculate real DMA position we want */
916 return bound_pos + mod_dma_pos;
917}
918
f87e7f25
TI		 919static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
920 struct azx_dev *azx_dev)
921{
922 return _snd_hdac_chip_readl(azx_bus(chip),
923 AZX_REG_VS_SDXDPIB_XBASE +
924 (AZX_REG_VS_SDXDPIB_XINTERVAL *
925 azx_dev->core.index));
926}
927
928/* get the current DMA position with correction on SKL+ chips */
929static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
930{
931 /* DPIB register gives a more accurate position for playback */
932 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
933 return azx_skl_get_dpib_pos(chip, azx_dev);
934
935 /* For capture, we need to read posbuf, but it requires a delay
936 * for the possible boundary overlap; the read of DPIB fetches the
937 * actual posbuf
938 */
939 udelay(20);
940 azx_skl_get_dpib_pos(chip, azx_dev);
941 return azx_get_pos_posbuf(chip, azx_dev);
942}
943
83012a7c 944#ifdef CONFIG_PM
65fcd41d
TI		 945static DEFINE_MUTEX(card_list_lock);
946static LIST_HEAD(card_list);
947
948static void azx_add_card_list(struct azx *chip)
949{
9a34af4a 950 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 951 mutex_lock(&card_list_lock);
9a34af4a 952 list_add(&hda->list, &card_list);
65fcd41d
TI		 953 mutex_unlock(&card_list_lock);
954}
955
956static void azx_del_card_list(struct azx *chip)
957{
9a34af4a 958 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 959 mutex_lock(&card_list_lock);
9a34af4a 960 list_del_init(&hda->list);
65fcd41d
TI		 961 mutex_unlock(&card_list_lock);
962}
963
964/* trigger power-save check at writing parameter */
965static int param_set_xint(const char *val, const struct kernel_param *kp)
966{
9a34af4a 967 struct hda_intel *hda;
65fcd41d 968 struct azx *chip;
65fcd41d
TI		 969 int prev = power_save;
970 int ret = param_set_int(val, kp);
971
972 if (ret || prev == power_save)
973 return ret;
974
975 mutex_lock(&card_list_lock);
9a34af4a
TI		 976 list_for_each_entry(hda, &card_list, list) {
977 chip = &hda->chip;
a41d1224 978 if (!hda->probe_continued || chip->disabled)
65fcd41d 979 continue;
a41d1224 980 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 981 }
982 mutex_unlock(&card_list_lock);
983 return 0;
984}
985#else
986#define azx_add_card_list(chip) /* NOP */
987#define azx_del_card_list(chip) /* NOP */
83012a7c 988#endif /* CONFIG_PM */
5c0b9bec 989
7ccbde57 990#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 991/*
992 * power management
993 */
68cb2b55 994static int azx_suspend(struct device *dev)
1da177e4 995{
68cb2b55 996 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 997 struct azx *chip;
998 struct hda_intel *hda;
a41d1224 999 struct hdac_bus *bus;
1da177e4 1000
2d9772ef
TI		 1001 if (!card)
1002 return 0;
1003
1004 chip = card->private_data;
1005 hda = container_of(chip, struct hda_intel, chip);
342e8449 1006 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 1007 return 0;
1008
a41d1224 1009 bus = azx_bus(chip);
421a1252 1010 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 1011 azx_clear_irq_pending(chip);
cb53c626 1012 azx_stop_chip(chip);
7295b264 1013 azx_enter_link_reset(chip);
a41d1224
TI		 1014 if (bus->irq >= 0) {
1015 free_irq(bus->irq, chip);
1016 bus->irq = -1;
30b35399 1017 }
a07187c9 1018
68e7fffc 1019 if (chip->msi)
43001c95 1020 pci_disable_msi(chip->pci);
dba9b7b6 1021 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
795614dd 1022 && hda->need_i915_power)
98d8fc6c 1023 snd_hdac_display_power(bus, false);
785d8c4b
LY		 1024
1025 trace_azx_suspend(chip);
1da177e4
LT		 1026 return 0;
1027}
1028
68cb2b55 1029static int azx_resume(struct device *dev)
1da177e4 1030{
68cb2b55
TI		 1031 struct pci_dev *pci = to_pci_dev(dev);
1032 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1033 struct azx *chip;
1034 struct hda_intel *hda;
a52ff34e 1035 struct hdac_bus *bus;
2d9772ef
TI		 1036
1037 if (!card)
1038 return 0;
1da177e4 1039
2d9772ef
TI		 1040 chip = card->private_data;
1041 hda = container_of(chip, struct hda_intel, chip);
a52ff34e 1042 bus = azx_bus(chip);
342e8449 1043 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 1044 return 0;
1045
a52ff34e
TI		 1046 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1047 snd_hdac_display_power(bus, true);
1048 if (hda->need_i915_power)
1049 snd_hdac_i915_set_bclk(bus);
a07187c9 1050 }
a52ff34e 1051
68e7fffc
TI		 1052 if (chip->msi)
1053 if (pci_enable_msi(pci) < 0)
1054 chip->msi = 0;
1055 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1056 return -EIO;
cb53c626 1057 azx_init_pci(chip);
d804ad92 1058
0a673521 1059 hda_intel_init_chip(chip, true);
d804ad92 1060
a52ff34e
TI		 1061 /* power down again for link-controlled chips */
1062 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1063 !hda->need_i915_power)
1064 snd_hdac_display_power(bus, false);
1065
421a1252 1066 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 1067
1068 trace_azx_resume(chip);
1da177e4
LT		 1069 return 0;
1070}
b8dfc462
ML		 1071#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1072
3e6db33a
XZ		 1073#ifdef CONFIG_PM_SLEEP
1074/* put codec down to D3 at hibernation for Intel SKL+;
1075 * otherwise BIOS may still access the codec and screw up the driver
1076 */
3e6db33a
XZ		 1077static int azx_freeze_noirq(struct device *dev)
1078{
a4b4793f
TI		 1079 struct snd_card *card = dev_get_drvdata(dev);
1080 struct azx *chip = card->private_data;
3e6db33a
XZ		 1081 struct pci_dev *pci = to_pci_dev(dev);
1082
a4b4793f 1083 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1084 pci_set_power_state(pci, PCI_D3hot);
1085
1086 return 0;
1087}
1088
1089static int azx_thaw_noirq(struct device *dev)
1090{
a4b4793f
TI		 1091 struct snd_card *card = dev_get_drvdata(dev);
1092 struct azx *chip = card->private_data;
3e6db33a
XZ		 1093 struct pci_dev *pci = to_pci_dev(dev);
1094
a4b4793f 1095 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1096 pci_set_power_state(pci, PCI_D0);
1097
1098 return 0;
1099}
1100#endif /* CONFIG_PM_SLEEP */
1101
641d334b 1102#ifdef CONFIG_PM
b8dfc462
ML		 1103static int azx_runtime_suspend(struct device *dev)
1104{
1105 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1106 struct azx *chip;
1107 struct hda_intel *hda;
b8dfc462 1108
2d9772ef
TI		 1109 if (!card)
1110 return 0;
1111
1112 chip = card->private_data;
1113 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1114 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1115 return 0;
1116
364aa716 1117 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1118 return 0;
1119
7d4f606c
WX		 1120 /* enable controller wake up event */
1121 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1122 STATESTS_INT_MASK);
1123
b8dfc462 1124 azx_stop_chip(chip);
873ce8ad 1125 azx_enter_link_reset(chip);
b8dfc462 1126 azx_clear_irq_pending(chip);
dba9b7b6 1127 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
795614dd 1128 && hda->need_i915_power)
98d8fc6c 1129 snd_hdac_display_power(azx_bus(chip), false);
e4d9e513 1130
785d8c4b 1131 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1132 return 0;
1133}
1134
1135static int azx_runtime_resume(struct device *dev)
1136{
1137 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1138 struct azx *chip;
1139 struct hda_intel *hda;
98d8fc6c 1140 struct hdac_bus *bus;
7d4f606c
WX		 1141 struct hda_codec *codec;
1142 int status;
b8dfc462 1143
2d9772ef
TI		 1144 if (!card)
1145 return 0;
1146
1147 chip = card->private_data;
1148 hda = container_of(chip, struct hda_intel, chip);
a52ff34e 1149 bus = azx_bus(chip);
1618e84a 1150 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1151 return 0;
1152
364aa716 1153 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1154 return 0;
1155
033ea349 1156 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
a52ff34e
TI		 1157 snd_hdac_display_power(bus, true);
1158 if (hda->need_i915_power)
bb03ed21 1159 snd_hdac_i915_set_bclk(bus);
a07187c9 1160 }
7d4f606c
WX		 1161
1162 /* Read STATESTS before controller reset */
1163 status = azx_readw(chip, STATESTS);
1164
b8dfc462 1165 azx_init_pci(chip);
0a673521 1166 hda_intel_init_chip(chip, true);
7d4f606c 1167
a41d1224
TI		 1168 if (status) {
1169 list_for_each_codec(codec, &chip->bus)
7d4f606c 1170 if (status & (1 << codec->addr))
2f35c630
TI		 1171 schedule_delayed_work(&codec->jackpoll_work,
1172 codec->jackpoll_interval);
7d4f606c
WX		 1173 }
1174
1175 /* disable controller Wake Up event*/
1176 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1177 ~STATESTS_INT_MASK);
1178
a52ff34e
TI		 1179 /* power down again for link-controlled chips */
1180 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1181 !hda->need_i915_power)
1182 snd_hdac_display_power(bus, false);
1183
785d8c4b 1184 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1185 return 0;
1186}
6eb827d2
TI		 1187
1188static int azx_runtime_idle(struct device *dev)
1189{
1190 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1191 struct azx *chip;
1192 struct hda_intel *hda;
1193
1194 if (!card)
1195 return 0;
6eb827d2 1196
2d9772ef
TI		 1197 chip = card->private_data;
1198 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1199 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1200 return 0;
1201
55ed9cd1 1202 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1203 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1204 return -EBUSY;
1205
1206 return 0;
1207}
1208
b8dfc462
ML		 1209static const struct dev_pm_ops azx_pm = {
1210 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1211#ifdef CONFIG_PM_SLEEP
1212 .freeze_noirq = azx_freeze_noirq,
1213 .thaw_noirq = azx_thaw_noirq,
1214#endif
6eb827d2 1215 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1216};
1217
68cb2b55
TI		 1218#define AZX_PM_OPS &azx_pm
1219#else
68cb2b55 1220#define AZX_PM_OPS NULL
b8dfc462 1221#endif /* CONFIG_PM */
1da177e4
LT		 1222
1223
48c8b0eb 1224static int azx_probe_continue(struct azx *chip);
a82d51ed 1225
8393ec4a 1226#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1227static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1228
a82d51ed
TI		 1229static void azx_vs_set_state(struct pci_dev *pci,
1230 enum vga_switcheroo_state state)
1231{
1232 struct snd_card *card = pci_get_drvdata(pci);
1233 struct azx *chip = card->private_data;
9a34af4a 1234 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1235 bool disabled;
1236
9a34af4a
TI		 1237 wait_for_completion(&hda->probe_wait);
1238 if (hda->init_failed)
a82d51ed
TI		 1239 return;
1240
1241 disabled = (state == VGA_SWITCHEROO_OFF);
1242 if (chip->disabled == disabled)
1243 return;
1244
a41d1224 1245 if (!hda->probe_continued) {
a82d51ed
TI		 1246 chip->disabled = disabled;
1247 if (!disabled) {
4e76a883
TI		 1248 dev_info(chip->card->dev,
1249 "Start delayed initialization\n");
5c90680e 1250 if (azx_probe_continue(chip) < 0) {
4e76a883 1251 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1252 hda->init_failed = true;
a82d51ed
TI		 1253 }
1254 }
1255 } else {
2b760d88 1256 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1257 disabled ? "Disabling" : "Enabling");
a82d51ed 1258 if (disabled) {
8928756d
DR		 1259 pm_runtime_put_sync_suspend(card->dev);
1260 azx_suspend(card->dev);
2b760d88 1261 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1262 * however we have no ACPI handle, so pci/acpi can't put us there,
1263 * put ourselves there */
1264 pci->current_state = PCI_D3cold;
a82d51ed 1265 chip->disabled = true;
a41d1224 1266 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1267 dev_warn(chip->card->dev,
1268 "Cannot lock devices!\n");
a82d51ed 1269 } else {
a41d1224 1270 snd_hda_unlock_devices(&chip->bus);
8928756d 1271 pm_runtime_get_noresume(card->dev);
a82d51ed 1272 chip->disabled = false;
8928756d 1273 azx_resume(card->dev);
a82d51ed
TI		 1274 }
1275 }
1276}
1277
1278static bool azx_vs_can_switch(struct pci_dev *pci)
1279{
1280 struct snd_card *card = pci_get_drvdata(pci);
1281 struct azx *chip = card->private_data;
9a34af4a 1282 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1283
9a34af4a
TI		 1284 wait_for_completion(&hda->probe_wait);
1285 if (hda->init_failed)
a82d51ed 1286 return false;
a41d1224 1287 if (chip->disabled || !hda->probe_continued)
a82d51ed 1288 return true;
a41d1224 1289 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1290 return false;
a41d1224 1291 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1292 return true;
1293}
1294
e23e7a14 1295static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1296{
9a34af4a 1297 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1298 struct pci_dev *p = get_bound_vga(chip->pci);
1299 if (p) {
4e76a883 1300 dev_info(chip->card->dev,
2b760d88 1301 "Handle vga_switcheroo audio client\n");
9a34af4a 1302 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1303 pci_dev_put(p);
1304 }
1305}
1306
1307static const struct vga_switcheroo_client_ops azx_vs_ops = {
1308 .set_gpu_state = azx_vs_set_state,
1309 .can_switch = azx_vs_can_switch,
1310};
1311
e23e7a14 1312static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1313{
9a34af4a 1314 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
ff291221 1315 struct pci_dev *p;
128960a9
TI		 1316 int err;
1317
9a34af4a 1318 if (!hda->use_vga_switcheroo)
a82d51ed 1319 return 0;
ff291221
JQ		 1320
1321 p = get_bound_vga(chip->pci);
1322 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1323 pci_dev_put(p);
1324
128960a9
TI		 1325 if (err < 0)
1326 return err;
9a34af4a 1327 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1328
1329 /* register as an optimus hdmi audio power domain */
8928756d 1330 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1331 &hda->hdmi_pm_domain);
128960a9 1332 return 0;
a82d51ed
TI		 1333}
1334#else
1335#define init_vga_switcheroo(chip) /* NOP */
1336#define register_vga_switcheroo(chip) 0
8393ec4a 1337#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1338#endif /* SUPPORT_VGA_SWITCHER */
1339
1da177e4
LT		 1340/*
1341 * destructor
1342 */
a98f90fd 1343static int azx_free(struct azx *chip)
1da177e4 1344{
c67e2228 1345 struct pci_dev *pci = chip->pci;
a07187c9 1346 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1347 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1348
364aa716 1349 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1350 pm_runtime_get_noresume(&pci->dev);
1351
65fcd41d
TI		 1352 azx_del_card_list(chip);
1353
9a34af4a
TI		 1354 hda->init_failed = 1; /* to be sure */
1355 complete_all(&hda->probe_wait);
f4c482a4 1356
9a34af4a 1357 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1358 if (chip->disabled && hda->probe_continued)
1359 snd_hda_unlock_devices(&chip->bus);
ab58d8cc 1360 if (hda->vga_switcheroo_registered) {
128960a9 1361 vga_switcheroo_unregister_client(chip->pci);
ab58d8cc
PW		 1362 vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1363 }
a82d51ed
TI		 1364 }
1365
a41d1224 1366 if (bus->chip_init) {
9ad593f6 1367 azx_clear_irq_pending(chip);
7833c3f8 1368 azx_stop_all_streams(chip);
cb53c626 1369 azx_stop_chip(chip);
1da177e4
LT		 1370 }
1371
a41d1224
TI		 1372 if (bus->irq >= 0)
1373 free_irq(bus->irq, (void*)chip);
68e7fffc 1374 if (chip->msi)
30b35399 1375 pci_disable_msi(chip->pci);
a41d1224 1376 iounmap(bus->remap_addr);
1da177e4 1377
67908994 1378 azx_free_stream_pages(chip);
a41d1224
TI		 1379 azx_free_streams(chip);
1380 snd_hdac_bus_exit(bus);
1381
a82d51ed
TI		 1382 if (chip->region_requested)
1383 pci_release_regions(chip->pci);
a41d1224 1384
1da177e4 1385 pci_disable_device(chip->pci);
4918cdab 1386#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1387 release_firmware(chip->fw);
4918cdab 1388#endif
98d8fc6c 1389
99a2008d 1390 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
795614dd 1391 if (hda->need_i915_power)
98d8fc6c 1392 snd_hdac_display_power(bus, false);
99a2008d 1393 }
fc18282c 1394 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
fcc88d91 1395 snd_hdac_i915_exit(bus);
a07187c9 1396 kfree(hda);
1da177e4
LT		 1397
1398 return 0;
1399}
1400
a41d1224
TI		 1401static int azx_dev_disconnect(struct snd_device *device)
1402{
1403 struct azx *chip = device->device_data;
1404
1405 chip->bus.shutdown = 1;
1406 return 0;
1407}
1408
a98f90fd 1409static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1410{
1411 return azx_free(device->device_data);
1412}
1413
8393ec4a 1414#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1415/*
2b760d88 1416 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1417 */
e23e7a14 1418static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1419{
1420 struct pci_dev *p;
1421
1422 /* check only discrete GPU */
1423 switch (pci->vendor) {
1424 case PCI_VENDOR_ID_ATI:
1425 case PCI_VENDOR_ID_AMD:
1426 case PCI_VENDOR_ID_NVIDIA:
1427 if (pci->devfn == 1) {
1428 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1429 pci->bus->number, 0);
1430 if (p) {
f03220fb 1431 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
9121947d
TI		 1432 return p;
1433 pci_dev_put(p);
1434 }
1435 }
1436 break;
1437 }
1438 return NULL;
1439}
1440
e23e7a14 1441static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1442{
1443 bool vga_inactive = false;
1444 struct pci_dev *p = get_bound_vga(pci);
1445
1446 if (p) {
12b78a7f 1447 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1448 vga_inactive = true;
1449 pci_dev_put(p);
1450 }
1451 return vga_inactive;
1452}
8393ec4a 1453#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1454
3372a153
TI		 1455/*
1456 * white/black-listing for position_fix
1457 */
e23e7a14 1458static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1459 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1460 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1461 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1462 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1463 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1464 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1465 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1466 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1467 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1468 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1469 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1470 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1471 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1472 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1473 {}
1474};
1475
e23e7a14 1476static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1477{
1478 const struct snd_pci_quirk *q;
1479
c673ba1c 1480 switch (fix) {
1dac6695 1481 case POS_FIX_AUTO:
c673ba1c
TI		 1482 case POS_FIX_LPIB:
1483 case POS_FIX_POSBUF:
4cb36310 1484 case POS_FIX_VIACOMBO:
a6f2fd55 1485 case POS_FIX_COMBO:
f87e7f25 1486 case POS_FIX_SKL:
c673ba1c
TI		 1487 return fix;
1488 }
1489
c673ba1c
TI		 1490 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1491 if (q) {
4e76a883
TI		 1492 dev_info(chip->card->dev,
1493 "position_fix set to %d for device %04x:%04x\n",
1494 q->value, q->subvendor, q->subdevice);
c673ba1c 1495 return q->value;
3372a153 1496 }
bdd9ef24
DH		 1497
1498 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1499 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1500 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1501 return POS_FIX_VIACOMBO;
9477c58e
TI		 1502 }
1503 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1504 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1505 return POS_FIX_LPIB;
bdd9ef24 1506 }
a4b4793f 1507 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1508 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1509 return POS_FIX_SKL;
1510 }
c673ba1c 1511 return POS_FIX_AUTO;
3372a153
TI		 1512}
1513
b6050ef6
TI		 1514static void assign_position_fix(struct azx *chip, int fix)
1515{
1516 static azx_get_pos_callback_t callbacks[] = {
1517 [POS_FIX_AUTO] = NULL,
1518 [POS_FIX_LPIB] = azx_get_pos_lpib,
1519 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1520 [POS_FIX_VIACOMBO] = azx_via_get_position,
1521 [POS_FIX_COMBO] = azx_get_pos_lpib,
f87e7f25 1522 [POS_FIX_SKL] = azx_get_pos_skl,
b6050ef6
TI		 1523 };
1524
1525 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1526
1527 /* combo mode uses LPIB only for playback */
1528 if (fix == POS_FIX_COMBO)
1529 chip->get_position[1] = NULL;
1530
f87e7f25 1531 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1532 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1533 chip->get_delay[0] = chip->get_delay[1] =
1534 azx_get_delay_from_lpib;
1535 }
1536
1537}
1538
669ba27a
TI		 1539/*
1540 * black-lists for probe_mask
1541 */
e23e7a14 1542static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1543 /* Thinkpad often breaks the controller communication when accessing
1544 * to the non-working (or non-existing) modem codec slot.
1545 */
1546 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1547 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1548 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1549 /* broken BIOS */
1550 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1551 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1552 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1553 /* forced codec slots */
93574844 1554 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1555 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1556 /* WinFast VP200 H (Teradici) user reported broken communication */
1557 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1558 {}
1559};
1560
f1eaaeec
TI		 1561#define AZX_FORCE_CODEC_MASK 0x100
1562
e23e7a14 1563static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1564{
1565 const struct snd_pci_quirk *q;
1566
f1eaaeec
TI		 1567 chip->codec_probe_mask = probe_mask[dev];
1568 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1569 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1570 if (q) {
4e76a883
TI		 1571 dev_info(chip->card->dev,
1572 "probe_mask set to 0x%x for device %04x:%04x\n",
1573 q->value, q->subvendor, q->subdevice);
f1eaaeec 1574 chip->codec_probe_mask = q->value;
669ba27a
TI		 1575 }
1576 }
f1eaaeec
TI		 1577
1578 /* check forced option */
1579 if (chip->codec_probe_mask != -1 &&
1580 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1581 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1582 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1583 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1584 }
669ba27a
TI		 1585}
1586
4d8e22e0 1587/*
71623855 1588 * white/black-list for enable_msi
4d8e22e0 1589 */
e23e7a14 1590static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1591 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1592 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1593 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1594 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1595 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1596 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1597 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1598 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1599 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1600 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1601 {}
1602};
1603
e23e7a14 1604static void check_msi(struct azx *chip)
4d8e22e0
TI		 1605{
1606 const struct snd_pci_quirk *q;
1607
71623855
TI		 1608 if (enable_msi >= 0) {
1609 chip->msi = !!enable_msi;
4d8e22e0 1610 return;
71623855
TI		 1611 }
1612 chip->msi = 1; /* enable MSI as default */
1613 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1614 if (q) {
4e76a883
TI		 1615 dev_info(chip->card->dev,
1616 "msi for device %04x:%04x set to %d\n",
1617 q->subvendor, q->subdevice, q->value);
4d8e22e0 1618 chip->msi = q->value;
80c43ed7
TI		 1619 return;
1620 }
1621
1622 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1623 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1624 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1625 chip->msi = 0;
4d8e22e0
TI		 1626 }
1627}
1628
a1585d76 1629/* check the snoop mode availability */
e23e7a14 1630static void azx_check_snoop_available(struct azx *chip)
a1585d76 1631{
7c732015 1632 int snoop = hda_snoop;
a1585d76 1633
7c732015
TI		 1634 if (snoop >= 0) {
1635 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1636 snoop ? "snoop" : "non-snoop");
1637 chip->snoop = snoop;
1638 return;
1639 }
1640
1641 snoop = true;
37e661ee
TI		 1642 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1643 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1644 /* force to non-snoop mode for a new VIA controller
1645 * when BIOS is set
1646 */
7c732015
TI		 1647 u8 val;
1648 pci_read_config_byte(chip->pci, 0x42, &val);
6d6e4cf8
DW		 1649 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1650 chip->pci->revision == 0x20))
7c732015 1651 snoop = false;
a1585d76
TI		 1652 }
1653
37e661ee
TI		 1654 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1655 snoop = false;
1656
7c732015
TI		 1657 chip->snoop = snoop;
1658 if (!snoop)
1659 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1660}
669ba27a 1661
99a2008d
WX		 1662static void azx_probe_work(struct work_struct *work)
1663{
9a34af4a
TI		 1664 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1665 azx_probe_continue(&hda->chip);
99a2008d 1666}
99a2008d 1667
4f0189be
TI		 1668static int default_bdl_pos_adj(struct azx *chip)
1669{
2cf721db
TI		 1670 /* some exceptions: Atoms seem problematic with value 1 */
1671 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1672 switch (chip->pci->device) {
1673 case 0x0f04: /* Baytrail */
1674 case 0x2284: /* Braswell */
1675 return 32;
1676 }
1677 }
1678
4f0189be
TI		 1679 switch (chip->driver_type) {
1680 case AZX_DRIVER_ICH:
1681 case AZX_DRIVER_PCH:
1682 return 1;
1683 default:
1684 return 32;
1685 }
1686}
1687
1da177e4
LT		 1688/*
1689 * constructor
1690 */
a43ff5ba
TI		 1691static const struct hdac_io_ops pci_hda_io_ops;
1692static const struct hda_controller_ops pci_hda_ops;
1693
e23e7a14
BP		 1694static int azx_create(struct snd_card *card, struct pci_dev *pci,
1695 int dev, unsigned int driver_caps,
1696 struct azx **rchip)
1da177e4 1697{
a98f90fd 1698 static struct snd_device_ops ops = {
a41d1224 1699 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1700 .dev_free = azx_dev_free,
1701 };
a07187c9 1702 struct hda_intel *hda;
a82d51ed
TI		 1703 struct azx *chip;
1704 int err;
1da177e4
LT		 1705
1706 *rchip = NULL;
bcd72003 1707
927fc866
PM		 1708 err = pci_enable_device(pci);
1709 if (err < 0)
1da177e4
LT		 1710 return err;
1711
a07187c9
ML		 1712 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1713 if (!hda) {
1da177e4
LT		 1714 pci_disable_device(pci);
1715 return -ENOMEM;
1716 }
1717
a07187c9 1718 chip = &hda->chip;
62932df8 1719 mutex_init(&chip->open_mutex);
1da177e4
LT		 1720 chip->card = card;
1721 chip->pci = pci;
a43ff5ba 1722 chip->ops = &pci_hda_ops;
9477c58e
TI		 1723 chip->driver_caps = driver_caps;
1724 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1725 check_msi(chip);
555e219f 1726 chip->dev_index = dev;
749ee287 1727 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1728 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1729 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1730 INIT_LIST_HEAD(&hda->list);
a82d51ed 1731 init_vga_switcheroo(chip);
9a34af4a 1732 init_completion(&hda->probe_wait);
1da177e4 1733
b6050ef6 1734 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1735
5aba4f8e 1736 check_probe_mask(chip, dev);
3372a153 1737
41438f13
TI		 1738 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1739 chip->fallback_to_single_cmd = 1;
1740 else /* explicitly set to single_cmd or not */
1741 chip->single_cmd = single_cmd;
1742
a1585d76 1743 azx_check_snoop_available(chip);
c74db86b 1744
4f0189be
TI		 1745 if (bdl_pos_adj[dev] < 0)
1746 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1747 else
1748 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1749
12a3616f
TI		 1750 /* Workaround for a communication error on CFL (bko#199007) */
1751 if (IS_CFL(pci))
1752 chip->polling_mode = 1;
1753
a41d1224
TI		 1754 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1755 if (err < 0) {
1756 kfree(hda);
1757 pci_disable_device(pci);
1758 return err;
1759 }
1760
7d9a1808
TI		 1761 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1762 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1763 chip->bus.needs_damn_long_delay = 1;
1764 }
1765
a82d51ed
TI		 1766 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1767 if (err < 0) {
4e76a883 1768 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1769 azx_free(chip);
1770 return err;
1771 }
1772
99a2008d 1773 /* continue probing in work context as may trigger request module */
9a34af4a 1774 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1775
a82d51ed 1776 *rchip = chip;
99a2008d 1777
a82d51ed
TI		 1778 return 0;
1779}
1780
48c8b0eb 1781static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1782{
1783 int dev = chip->dev_index;
1784 struct pci_dev *pci = chip->pci;
1785 struct snd_card *card = chip->card;
a41d1224 1786 struct hdac_bus *bus = azx_bus(chip);
67908994 1787 int err;
a82d51ed 1788 unsigned short gcap;
413cbf46 1789 unsigned int dma_bits = 64;
a82d51ed 1790
07e4ca50
TI		 1791#if BITS_PER_LONG != 64
1792 /* Fix up base address on ULI M5461 */
1793 if (chip->driver_type == AZX_DRIVER_ULI) {
1794 u16 tmp3;
1795 pci_read_config_word(pci, 0x40, &tmp3);
1796 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1797 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1798 }
1799#endif
1800
927fc866 1801 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1802 if (err < 0)
1da177e4 1803 return err;
a82d51ed 1804 chip->region_requested = 1;
1da177e4 1805
a41d1224
TI		 1806 bus->addr = pci_resource_start(pci, 0);
1807 bus->remap_addr = pci_ioremap_bar(pci, 0);
1808 if (bus->remap_addr == NULL) {
4e76a883 1809 dev_err(card->dev, "ioremap error\n");
a82d51ed 1810 return -ENXIO;
1da177e4
LT		 1811 }
1812
a4b4793f 1813 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1814 snd_hdac_bus_parse_capabilities(bus);
1815
1816 /*
1817 * Some Intel CPUs has always running timer (ART) feature and
1818 * controller may have Global time sync reporting capability, so
1819 * check both of these before declaring synchronized time reporting
1820 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1821 */
1822 chip->gts_present = false;
1823
1824#ifdef CONFIG_X86
1825 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1826 chip->gts_present = true;
1827#endif
1828
db79afa1
BH		 1829 if (chip->msi) {
1830 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1831 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1832 pci->no_64bit_msi = true;
1833 }
68e7fffc
TI		 1834 if (pci_enable_msi(pci) < 0)
1835 chip->msi = 0;
db79afa1 1836 }
7376d013 1837
a82d51ed
TI		 1838 if (azx_acquire_irq(chip, 0) < 0)
1839 return -EBUSY;
1da177e4
LT		 1840
1841 pci_set_master(pci);
a41d1224 1842 synchronize_irq(bus->irq);
1da177e4 1843
bcd72003 1844 gcap = azx_readw(chip, GCAP);
4e76a883 1845 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1846
413cbf46
TI		 1847 /* AMD devices support 40 or 48bit DMA, take the safe one */
1848 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1849 dma_bits = 40;
1850
dc4c2e6b 1851 /* disable SB600 64bit support for safety */
9477c58e 1852 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1853 struct pci_dev *p_smbus;
413cbf46 1854 dma_bits = 40;
dc4c2e6b
AB		 1855 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1856 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1857 NULL);
1858 if (p_smbus) {
1859 if (p_smbus->revision < 0x30)
fb1d8ac2 1860 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1861 pci_dev_put(p_smbus);
1862 }
1863 }
09240cf4 1864
3ab7511e
AB		 1865 /* NVidia hardware normally only supports up to 40 bits of DMA */
1866 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1867 dma_bits = 40;
1868
9477c58e
TI		 1869 /* disable 64bit DMA address on some devices */
1870 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1871 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1872 gcap &= ~AZX_GCAP_64OK;
9477c58e 1873 }
396087ea 1874
2ae66c26 1875 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1876 if (align_buffer_size >= 0)
1877 chip->align_buffer_size = !!align_buffer_size;
1878 else {
103884a3 1879 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1880 chip->align_buffer_size = 0;
7bfe059e
TI		 1881 else
1882 chip->align_buffer_size = 1;
1883 }
2ae66c26 1884
cf7aaca8 1885 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1886 if (!(gcap & AZX_GCAP_64OK))
1887 dma_bits = 32;
412b979c
QL		 1888 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1889 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1890 } else {
412b979c
QL		 1891 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1892 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1893 }
cf7aaca8 1894
8b6ed8e7
TI		 1895 /* read number of streams from GCAP register instead of using
1896 * hardcoded value
1897 */
1898 chip->capture_streams = (gcap >> 8) & 0x0f;
1899 chip->playback_streams = (gcap >> 12) & 0x0f;
1900 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1901 /* gcap didn't give any info, switching to old method */
1902
1903 switch (chip->driver_type) {
1904 case AZX_DRIVER_ULI:
1905 chip->playback_streams = ULI_NUM_PLAYBACK;
1906 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1907 break;
1908 case AZX_DRIVER_ATIHDMI:
1815b34a 1909 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1910 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1911 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1912 break;
c4da29ca 1913 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1914 default:
1915 chip->playback_streams = ICH6_NUM_PLAYBACK;
1916 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1917 break;
1918 }
07e4ca50 1919 }
8b6ed8e7
TI		 1920 chip->capture_index_offset = 0;
1921 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1922 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1923
df56c3db
JK		 1924 /* sanity check for the SDxCTL.STRM field overflow */
1925 if (chip->num_streams > 15 &&
1926 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1927 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1928 "forcing separate stream tags", chip->num_streams);
1929 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1930 }
1931
a41d1224
TI		 1932 /* initialize streams */
1933 err = azx_init_streams(chip);
81740861 1934 if (err < 0)
a82d51ed 1935 return err;
1da177e4 1936
a41d1224
TI		 1937 err = azx_alloc_stream_pages(chip);
1938 if (err < 0)
1939 return err;
1da177e4
LT		 1940
1941 /* initialize chip */
cb53c626 1942 azx_init_pci(chip);
e4d9e513 1943
bb03ed21
TI		 1944 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1945 snd_hdac_i915_set_bclk(bus);
e4d9e513 1946
0a673521 1947 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1948
1949 /* codec detection */
a41d1224 1950 if (!azx_bus(chip)->codec_mask) {
4e76a883 1951 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1952 return -ENODEV;
1da177e4
LT		 1953 }
1954
07e4ca50 1955 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1956 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1957 sizeof(card->shortname));
1958 snprintf(card->longname, sizeof(card->longname),
1959 "%s at 0x%lx irq %i",
a41d1224 1960 card->shortname, bus->addr, bus->irq);
07e4ca50 1961
1da177e4 1962 return 0;
1da177e4
LT		 1963}
1964
97c6a3d1 1965#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1966/* callback from request_firmware_nowait() */
1967static void azx_firmware_cb(const struct firmware *fw, void *context)
1968{
1969 struct snd_card *card = context;
1970 struct azx *chip = card->private_data;
1971 struct pci_dev *pci = chip->pci;
1972
1973 if (!fw) {
4e76a883 1974 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1975 goto error;
1976 }
1977
1978 chip->fw = fw;
1979 if (!chip->disabled) {
1980 /* continue probing */
1981 if (azx_probe_continue(chip))
1982 goto error;
1983 }
1984 return; /* OK */
1985
1986 error:
1987 snd_card_free(card);
1988 pci_set_drvdata(pci, NULL);
1989}
97c6a3d1 1990#endif
5cb543db 1991
40830813
DR		 1992/*
1993 * HDA controller ops.
1994 */
1995
1996/* PCI register access. */
db291e36 1997static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1998{
1999 writel(value, addr);
2000}
2001
db291e36 2002static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 2003{
2004 return readl(addr);
2005}
2006
db291e36 2007static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 2008{
2009 writew(value, addr);
2010}
2011
db291e36 2012static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 2013{
2014 return readw(addr);
2015}
2016
db291e36 2017static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 2018{
2019 writeb(value, addr);
2020}
2021
db291e36 2022static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 2023{
2024 return readb(addr);
2025}
2026
f46ea609
DR		 2027static int disable_msi_reset_irq(struct azx *chip)
2028{
a41d1224 2029 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 2030 int err;
2031
a41d1224
TI		 2032 free_irq(bus->irq, chip);
2033 bus->irq = -1;
f46ea609
DR		 2034 pci_disable_msi(chip->pci);
2035 chip->msi = 0;
2036 err = azx_acquire_irq(chip, 1);
2037 if (err < 0)
2038 return err;
2039
2040 return 0;
2041}
2042
b419b35b 2043/* DMA page allocation helpers. */
a43ff5ba 2044static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 2045 int type,
2046 size_t size,
2047 struct snd_dma_buffer *buf)
2048{
a41d1224 2049 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 2050 int err;
2051
2052 err = snd_dma_alloc_pages(type,
a43ff5ba 2053 bus->dev,
b419b35b
DR		 2054 size, buf);
2055 if (err < 0)
2056 return err;
2057 mark_pages_wc(chip, buf, true);
2058 return 0;
2059}
2060
a43ff5ba 2061static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 2062{
a41d1224 2063 struct azx *chip = bus_to_azx(bus);
a43ff5ba 2064
b419b35b
DR		 2065 mark_pages_wc(chip, buf, false);
2066 snd_dma_free_pages(buf);
2067}
2068
2069static int substream_alloc_pages(struct azx *chip,
2070 struct snd_pcm_substream *substream,
2071 size_t size)
2072{
2073 struct azx_dev *azx_dev = get_azx_dev(substream);
2074 int ret;
2075
2076 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 2077 ret = snd_pcm_lib_malloc_pages(substream, size);
2078 if (ret < 0)
2079 return ret;
2080 mark_runtime_wc(chip, azx_dev, substream, true);
2081 return 0;
2082}
2083
2084static int substream_free_pages(struct azx *chip,
2085 struct snd_pcm_substream *substream)
2086{
2087 struct azx_dev *azx_dev = get_azx_dev(substream);
2088 mark_runtime_wc(chip, azx_dev, substream, false);
2089 return snd_pcm_lib_free_pages(substream);
2090}
2091
8769b278
DR		 2092static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2093 struct vm_area_struct *area)
2094{
2095#ifdef CONFIG_X86
2096 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2097 struct azx *chip = apcm->chip;
3b70bdba 2098 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 2099 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2100#endif
2101}
2102
a43ff5ba 2103static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 2104 .reg_writel = pci_azx_writel,
2105 .reg_readl = pci_azx_readl,
2106 .reg_writew = pci_azx_writew,
2107 .reg_readw = pci_azx_readw,
2108 .reg_writeb = pci_azx_writeb,
2109 .reg_readb = pci_azx_readb,
b419b35b
DR		 2110 .dma_alloc_pages = dma_alloc_pages,
2111 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 2112};
2113
2114static const struct hda_controller_ops pci_hda_ops = {
2115 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 2116 .substream_alloc_pages = substream_alloc_pages,
2117 .substream_free_pages = substream_free_pages,
8769b278 2118 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 2119 .position_check = azx_position_check,
17eccb27 2120 .link_power = azx_intel_link_power,
40830813
DR		 2121};
2122
e23e7a14
BP		 2123static int azx_probe(struct pci_dev *pci,
2124 const struct pci_device_id *pci_id)
1da177e4 2125{
5aba4f8e 2126 static int dev;
a98f90fd 2127 struct snd_card *card;
9a34af4a 2128 struct hda_intel *hda;
a98f90fd 2129 struct azx *chip;
aad730d0 2130 bool schedule_probe;
927fc866 2131 int err;
1da177e4 2132
5aba4f8e
TI		 2133 if (dev >= SNDRV_CARDS)
2134 return -ENODEV;
2135 if (!enable[dev]) {
2136 dev++;
2137 return -ENOENT;
2138 }
2139
60c5772b
TI		 2140 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2141 0, &card);
e58de7ba 2142 if (err < 0) {
4e76a883 2143 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2144 return err;
1da177e4
LT		 2145 }
2146
a43ff5ba 2147 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2148 if (err < 0)
2149 goto out_free;
421a1252 2150 card->private_data = chip;
9a34af4a 2151 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2152
2153 pci_set_drvdata(pci, card);
2154
2155 err = register_vga_switcheroo(chip);
2156 if (err < 0) {
2b760d88 2157 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2158 goto out_free;
2159 }
2160
2161 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2162 dev_info(card->dev, "VGA controller is disabled\n");
2163 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2164 chip->disabled = true;
2165 }
2166
aad730d0 2167 schedule_probe = !chip->disabled;
1da177e4 2168
4918cdab
TI		 2169#ifdef CONFIG_SND_HDA_PATCH_LOADER
2170 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2171 dev_info(card->dev, "Applying patch firmware '%s'\n",
2172 patch[dev]);
5cb543db
TI		 2173 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2174 &pci->dev, GFP_KERNEL, card,
2175 azx_firmware_cb);
4918cdab
TI		 2176 if (err < 0)
2177 goto out_free;
aad730d0 2178 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2179 }
2180#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2181
aad730d0 2182#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2183 if (CONTROLLER_IN_GPU(pci))
2184 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2185#endif
99a2008d 2186
aad730d0 2187 if (schedule_probe)
9a34af4a 2188 schedule_work(&hda->probe_work);
a82d51ed 2189
a82d51ed 2190 dev++;
88d071fc 2191 if (chip->disabled)
9a34af4a 2192 complete_all(&hda->probe_wait);
a82d51ed
TI		 2193 return 0;
2194
2195out_free:
2196 snd_card_free(card);
2197 return err;
2198}
2199
a187e92b
HG		 2200#ifdef CONFIG_PM
2201/* On some boards setting power_save to a non 0 value leads to clicking /
2202 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2203 * figure out how to avoid these sounds, but that is not always feasible.
2204 * So we keep a list of devices where we disable powersaving as its known
2205 * to causes problems on these devices.
2206 */
2207static struct snd_pci_quirk power_save_blacklist[] = {
2208 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2209 SND_PCI_QUIRK(0x1849, 0x0c0c, "Asrock B85M-ITX", 0),
2210 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2211 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
7c3434ab
HW		 2212 /* https://bugs.launchpad.net/bugs/1821663 */
2213 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
6a777d05
HG		 2214 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2215 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
a187e92b
HG		 2216 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2217 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2129b6fe
JK		 2218 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2219 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2220 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2221 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
7c3434ab
HW		 2222 /* https://bugs.launchpad.net/bugs/1821663 */
2223 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
a187e92b
HG		 2224 {}
2225};
2226#endif /* CONFIG_PM */
2227
e62a42ae
DR		 2228/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2229static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2230 [AZX_DRIVER_NVIDIA] = 8,
2231 [AZX_DRIVER_TERA] = 1,
2232};
2233
48c8b0eb 2234static int azx_probe_continue(struct azx *chip)
a82d51ed 2235{
9a34af4a 2236 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2237 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2238 struct pci_dev *pci = chip->pci;
a82d51ed 2239 int dev = chip->dev_index;
a187e92b 2240 int val;
a82d51ed
TI		 2241 int err;
2242
a41d1224 2243 hda->probe_continued = 1;
795614dd 2244
fcc88d91 2245 /* bind with i915 if needed */
dba9b7b6 2246 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
98d8fc6c 2247 err = snd_hdac_i915_init(bus);
535115b5
TI		 2248 if (err < 0) {
2249 /* if the controller is bound only with HDMI/DP
2250 * (for HSW and BDW), we need to abort the probe;
2251 * for other chips, still continue probing as other
2252 * codecs can be on the same link.
2253 */
bed2e98e
TI		 2254 if (CONTROLLER_IN_GPU(pci)) {
2255 dev_err(chip->card->dev,
2256 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2257 goto out_free;
fcc88d91
TI		 2258 } else {
2259 /* don't bother any longer */
dba9b7b6
TI		 2260 chip->driver_caps &=
2261 ~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL);
fcc88d91 2262 }
535115b5 2263 }
fcc88d91
TI		 2264 }
2265
2266 /* Request display power well for the HDA controller or codec. For
2267 * Haswell/Broadwell, both the display HDA controller and codec need
2268 * this power. For other platforms, like Baytrail/Braswell, only the
2269 * display codec needs the power and it can be released after probe.
2270 */
2271 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2272 /* HSW/BDW controllers need this power */
2273 if (CONTROLLER_IN_GPU(pci))
2274 hda->need_i915_power = 1;
795614dd 2275
98d8fc6c 2276 err = snd_hdac_display_power(bus, true);
74b0c2d7
TI		 2277 if (err < 0) {
2278 dev_err(chip->card->dev,
2279 "Cannot turn on display power on i915\n");
795614dd 2280 goto i915_power_fail;
74b0c2d7 2281 }
99a2008d
WX		 2282 }
2283
5c90680e
TI		 2284 err = azx_first_init(chip);
2285 if (err < 0)
2286 goto out_free;
2287
2dca0bba
JK		 2288#ifdef CONFIG_SND_HDA_INPUT_BEEP
2289 chip->beep_mode = beep_mode[dev];
2290#endif
2291
1da177e4 2292 /* create codec instances */
96d2bd6e 2293 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2294 if (err < 0)
2295 goto out_free;
96d2bd6e 2296
4ea6fbc8 2297#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2298 if (chip->fw) {
a41d1224 2299 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2300 chip->fw->data);
4ea6fbc8
TI		 2301 if (err < 0)
2302 goto out_free;
e39ae856 2303#ifndef CONFIG_PM
4918cdab
TI		 2304 release_firmware(chip->fw); /* no longer needed */
2305 chip->fw = NULL;
e39ae856 2306#endif
4ea6fbc8
TI		 2307 }
2308#endif
10e77dda 2309 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2310 err = azx_codec_configure(chip);
2311 if (err < 0)
2312 goto out_free;
2313 }
1da177e4 2314
a82d51ed 2315 err = snd_card_register(chip->card);
41dda0fd
WF		 2316 if (err < 0)
2317 goto out_free;
1da177e4 2318
cb53c626 2319 chip->running = 1;
65fcd41d 2320 azx_add_card_list(chip);
a187e92b
HG		 2321
2322 val = power_save;
2323#ifdef CONFIG_PM
027ac1e7 2324 if (pm_blacklist) {
a187e92b
HG		 2325 const struct snd_pci_quirk *q;
2326
a187e92b
HG		 2327 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2328 if (q && val) {
2329 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2330 q->subvendor, q->subdevice);
2331 val = 0;
2332 }
2333 }
2334#endif /* CONFIG_PM */
2335 snd_hda_set_power_save(&chip->bus, val * 1000);
364aa716 2336 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
30ff5957 2337 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2338
41dda0fd 2339out_free:
dba9b7b6 2340 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
795614dd 2341 && !hda->need_i915_power)
98d8fc6c 2342 snd_hdac_display_power(bus, false);
795614dd
ML		 2343
2344i915_power_fail:
88d071fc 2345 if (err < 0)
9a34af4a
TI		 2346 hda->init_failed = 1;
2347 complete_all(&hda->probe_wait);
41dda0fd 2348 return err;
1da177e4
LT		 2349}
2350
e23e7a14 2351static void azx_remove(struct pci_dev *pci)
1da177e4 2352{
9121947d 2353 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2354 struct azx *chip;
2355 struct hda_intel *hda;
2356
2357 if (card) {
0b8c8219 2358 /* cancel the pending probing work */
991f86d7
TI		 2359 chip = card->private_data;
2360 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2361 /* FIXME: below is an ugly workaround.
2362 * Both device_release_driver() and driver_probe_device()
2363 * take *both* the device's and its parent's lock before
2364 * calling the remove() and probe() callbacks. The codec
2365 * probe takes the locks of both the codec itself and its
2366 * parent, i.e. the PCI controller dev. Meanwhile, when
2367 * the PCI controller is unbound, it takes its lock, too
2368 * ==> ouch, a deadlock!
2369 * As a workaround, we unlock temporarily here the controller
2370 * device during cancel_work_sync() call.
2371 */
2372 device_unlock(&pci->dev);
0b8c8219 2373 cancel_work_sync(&hda->probe_work);
ab949d51 2374 device_lock(&pci->dev);
b8dfc462 2375
9121947d 2376 snd_card_free(card);
991f86d7 2377 }
1da177e4
LT		 2378}
2379
b2a0bafa
TI		 2380static void azx_shutdown(struct pci_dev *pci)
2381{
2382 struct snd_card *card = pci_get_drvdata(pci);
2383 struct azx *chip;
2384
2385 if (!card)
2386 return;
2387 chip = card->private_data;
2388 if (chip && chip->running)
2389 azx_stop_chip(chip);
2390}
2391
1da177e4 2392/* PCI IDs */
6f51f6cf 2393static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2394 /* CPT */
9477c58e 2395 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2396 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2397 /* PBG */
9477c58e 2398 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2399 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2400 /* Panther Point */
9477c58e 2401 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2402 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2403 /* Lynx Point */
2404 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2405 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2406 /* 9 Series */
2407 { PCI_DEVICE(0x8086, 0x8ca0),
2408 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2409 /* Wellsburg */
2410 { PCI_DEVICE(0x8086, 0x8d20),
2411 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2412 { PCI_DEVICE(0x8086, 0x8d21),
2413 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2414 /* Lewisburg */
2415 { PCI_DEVICE(0x8086, 0xa1f0),
e7480b34 2416 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
5cf92c8b 2417 { PCI_DEVICE(0x8086, 0xa270),
e7480b34 2418 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
144dad99
JR		 2419 /* Lynx Point-LP */
2420 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2421 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2422 /* Lynx Point-LP */
2423 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2424 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2425 /* Wildcat Point-LP */
2426 { PCI_DEVICE(0x8086, 0x9ca0),
2427 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2428 /* Sunrise Point */
2429 { PCI_DEVICE(0x8086, 0xa170),
a4b4793f 2430 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2431 /* Sunrise Point-LP */
2432 { PCI_DEVICE(0x8086, 0x9d70),
a4b4793f 2433 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2434 /* Kabylake */
2435 { PCI_DEVICE(0x8086, 0xa171),
a4b4793f 2436 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2437 /* Kabylake-LP */
2438 { PCI_DEVICE(0x8086, 0x9d71),
a4b4793f 2439 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2440 /* Kabylake-H */
2441 { PCI_DEVICE(0x8086, 0xa2f0),
a4b4793f 2442 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
e79b0006
MD		 2443 /* Coffelake */
2444 { PCI_DEVICE(0x8086, 0xa348),
a4b4793f 2445 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2357f6f0
GS		 2446 /* Cannonlake */
2447 { PCI_DEVICE(0x8086, 0x9dc8),
2448 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
401f42d9
PLB		 2449 /* CometLake-LP */
2450 { PCI_DEVICE(0x8086, 0x02C8),
2451 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2452 /* CometLake-H */
2453 { PCI_DEVICE(0x8086, 0x06C8),
2454 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
772a7584
GS		 2455 /* Icelake */
2456 { PCI_DEVICE(0x8086, 0x34c8),
2457 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
c87693da
LH		 2458 /* Broxton-P(Apollolake) */
2459 { PCI_DEVICE(0x8086, 0x5a98),
a4b4793f 2460 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2461 /* Broxton-T */
2462 { PCI_DEVICE(0x8086, 0x1a98),
a4b4793f 2463 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
44b46d73
VK		 2464 /* Gemini-Lake */
2465 { PCI_DEVICE(0x8086, 0x3198),
a4b4793f 2466 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2467 /* Haswell */
4a7c516b 2468 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2469 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2470 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2471 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2472 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2473 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2474 /* Broadwell */
2475 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2476 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2477 /* 5 Series/3400 */
2478 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2479 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2480 /* Poulsbo */
9477c58e 2481 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2482 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2483 /* Oaktrail */
09904b95 2484 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2485 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2486 /* BayTrail */
2487 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2488 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2489 /* Braswell */
2490 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2491 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2492 /* ICH6 */
8b0bd226 2493 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2494 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2495 /* ICH7 */
8b0bd226 2496 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2497 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2498 /* ESB2 */
8b0bd226 2499 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2500 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2501 /* ICH8 */
8b0bd226 2502 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2503 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2504 /* ICH9 */
8b0bd226 2505 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2506 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2507 /* ICH9 */
8b0bd226 2508 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2509 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2510 /* ICH10 */
8b0bd226 2511 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2512 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2513 /* ICH10 */
8b0bd226 2514 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2515 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2516 /* Generic Intel */
2517 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2518 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2519 .class_mask = 0xffffff,
103884a3 2520 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2521 /* ATI SB 450/600/700/800/900 */
2522 { PCI_DEVICE(0x1002, 0x437b),
2523 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2524 { PCI_DEVICE(0x1002, 0x4383),
2525 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2526 /* AMD Hudson */
2527 { PCI_DEVICE(0x1022, 0x780d),
2528 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
9ceace3c
VM		 2529 /* AMD Raven */
2530 { PCI_DEVICE(0x1022, 0x15e3),
f5cb1626
KHF		 2531 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2532 AZX_DCAPS_PM_RUNTIME },
87218e9c 2533 /* ATI HDMI */
fd48331f
MSB		 2534 { PCI_DEVICE(0x1002, 0x0002),
2535 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
650474fb
AD		 2536 { PCI_DEVICE(0x1002, 0x1308),
2537 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2538 { PCI_DEVICE(0x1002, 0x157a),
2539 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
d716fb03
AB		 2540 { PCI_DEVICE(0x1002, 0x15b3),
2541 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2542 { PCI_DEVICE(0x1002, 0x793b),
2543 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2544 { PCI_DEVICE(0x1002, 0x7919),
2545 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2546 { PCI_DEVICE(0x1002, 0x960f),
2547 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2548 { PCI_DEVICE(0x1002, 0x970f),
2549 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2550 { PCI_DEVICE(0x1002, 0x9840),
2551 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2552 { PCI_DEVICE(0x1002, 0xaa00),
2553 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2554 { PCI_DEVICE(0x1002, 0xaa08),
2555 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2556 { PCI_DEVICE(0x1002, 0xaa10),
2557 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2558 { PCI_DEVICE(0x1002, 0xaa18),
2559 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2560 { PCI_DEVICE(0x1002, 0xaa20),
2561 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2562 { PCI_DEVICE(0x1002, 0xaa28),
2563 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2564 { PCI_DEVICE(0x1002, 0xaa30),
2565 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2566 { PCI_DEVICE(0x1002, 0xaa38),
2567 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2568 { PCI_DEVICE(0x1002, 0xaa40),
2569 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2570 { PCI_DEVICE(0x1002, 0xaa48),
2571 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2572 { PCI_DEVICE(0x1002, 0xaa50),
2573 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2574 { PCI_DEVICE(0x1002, 0xaa58),
2575 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2576 { PCI_DEVICE(0x1002, 0xaa60),
2577 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2578 { PCI_DEVICE(0x1002, 0xaa68),
2579 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2580 { PCI_DEVICE(0x1002, 0xaa80),
2581 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2582 { PCI_DEVICE(0x1002, 0xaa88),
2583 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2584 { PCI_DEVICE(0x1002, 0xaa90),
2585 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2586 { PCI_DEVICE(0x1002, 0xaa98),
2587 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2588 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2589 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2590 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2591 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2592 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2593 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2594 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2595 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2596 { PCI_DEVICE(0x1002, 0xaac0),
2597 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2598 { PCI_DEVICE(0x1002, 0xaac8),
2599 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2600 { PCI_DEVICE(0x1002, 0xaad8),
2601 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2602 { PCI_DEVICE(0x1002, 0xaae8),
2603 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
8eb22214
MSB		 2604 { PCI_DEVICE(0x1002, 0xaae0),
2605 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2606 { PCI_DEVICE(0x1002, 0xaaf0),
2607 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2608 /* VIA VT8251/VT8237A */
26f05717 2609 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2610 /* VIA GFX VT7122/VX900 */
2611 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2612 /* VIA GFX VT6122/VX11 */
2613 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2614 /* SIS966 */
2615 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2616 /* ULI M5461 */
2617 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2618 /* NVIDIA MCP */
0c2fd1bf
TI		 2619 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2620 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2621 .class_mask = 0xffffff,
9477c58e 2622 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2623 /* Teradici */
9477c58e
TI		 2624 { PCI_DEVICE(0x6549, 0x1200),
2625 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2626 { PCI_DEVICE(0x6549, 0x2200),
2627 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2628 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2629 /* CTHDA chips */
2630 { PCI_DEVICE(0x1102, 0x0010),
2631 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2632 { PCI_DEVICE(0x1102, 0x0012),
2633 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2634#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2635 /* the following entry conflicts with snd-ctxfi driver,
2636 * as ctxfi driver mutates from HD-audio to native mode with
2637 * a special command sequence.
2638 */
4e01f54b
TI		 2639 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2640 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2641 .class_mask = 0xffffff,
9477c58e 2642 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2643 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2644#else
2645 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2646 { PCI_DEVICE(0x1102, 0x0009),
2647 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2648 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2649#endif
c563f473
TI		 2650 /* CM8888 */
2651 { PCI_DEVICE(0x13f6, 0x5011),
2652 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2653 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2654 /* Vortex86MX */
2655 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2656 /* VMware HDAudio */
2657 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2658 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2659 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2660 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2661 .class_mask = 0xffffff,
9477c58e 2662 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2663 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2664 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2665 .class_mask = 0xffffff,
9477c58e 2666 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2667 { 0, }
2668};
2669MODULE_DEVICE_TABLE(pci, azx_ids);
2670
2671/* pci_driver definition */
e9f66d9b 2672static struct pci_driver azx_driver = {
3733e424 2673 .name = KBUILD_MODNAME,
1da177e4
LT		 2674 .id_table = azx_ids,
2675 .probe = azx_probe,
e23e7a14 2676 .remove = azx_remove,
b2a0bafa 2677 .shutdown = azx_shutdown,
68cb2b55
TI		 2678 .driver = {
2679 .pm = AZX_PM_OPS,
2680 },
1da177e4
LT		 2681};
2682
e9f66d9b 2683module_pci_driver(azx_driver);
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