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ALSA: hda - Remove superfluous MAX_AZX_DEV
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4 64#include "hda_codec.h"
99a2008d 65#include "hda_i915.h"
05e84878 66#include "hda_controller.h"
2538a4f5 67#include "hda_priv.h"
1da177e4
LT		 68
69
5aba4f8e
TI		 70static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
71static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 72static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 73static char *model[SNDRV_CARDS];
1dac6695 74static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 75static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 76static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 77static int probe_only[SNDRV_CARDS];
26a6cb6c 78static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 79static bool single_cmd;
71623855 80static int enable_msi = -1;
4ea6fbc8
TI		 81#ifdef CONFIG_SND_HDA_PATCH_LOADER
82static char *patch[SNDRV_CARDS];
83#endif
2dca0bba 84#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 85static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 86 CONFIG_SND_HDA_INPUT_BEEP_MODE};
87#endif
1da177e4 88
5aba4f8e 89module_param_array(index, int, NULL, 0444);
1da177e4 90MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 91module_param_array(id, charp, NULL, 0444);
1da177e4 92MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 93module_param_array(enable, bool, NULL, 0444);
94MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
95module_param_array(model, charp, NULL, 0444);
1da177e4 96MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 97module_param_array(position_fix, int, NULL, 0444);
4cb36310 98MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 99 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 100module_param_array(bdl_pos_adj, int, NULL, 0644);
101MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 102module_param_array(probe_mask, int, NULL, 0444);
606ad75f 103MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 104module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 105MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 106module_param_array(jackpoll_ms, int, NULL, 0444);
107MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 108module_param(single_cmd, bool, 0444);
d01ce99f
TI		 109MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
110 "(for debugging only).");
ac9ef6cf 111module_param(enable_msi, bint, 0444);
134a11f0 112MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 113#ifdef CONFIG_SND_HDA_PATCH_LOADER
114module_param_array(patch, charp, NULL, 0444);
115MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
116#endif
2dca0bba 117#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 118module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 119MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 120 "(0=off, 1=on) (default=1).");
2dca0bba 121#endif
606ad75f 122
83012a7c 123#ifdef CONFIG_PM
65fcd41d
TI		 124static int param_set_xint(const char *val, const struct kernel_param *kp);
125static struct kernel_param_ops param_ops_xint = {
126 .set = param_set_xint,
127 .get = param_get_int,
128};
129#define param_check_xint param_check_int
130
fee2fba3 131static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
e62a42ae 132static int *power_save_addr = &power_save;
65fcd41d 133module_param(power_save, xint, 0644);
fee2fba3
TI		 134MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
135 "(in second, 0 = disable).");
1da177e4 136
dee1b66c
TI		 137/* reset the HD-audio controller in power save mode.
138 * this may give more power-saving, but will take longer time to
139 * wake up.
140 */
8fc24426
TI		 141static bool power_save_controller = 1;
142module_param(power_save_controller, bool, 0644);
dee1b66c 143MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae
DR		 144#else
145static int *power_save_addr;
83012a7c 146#endif /* CONFIG_PM */
dee1b66c 147
7bfe059e
TI		 148static int align_buffer_size = -1;
149module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 150MODULE_PARM_DESC(align_buffer_size,
151 "Force buffer and period sizes to be multiple of 128 bytes.");
152
27fe48d9
TI		 153#ifdef CONFIG_X86
154static bool hda_snoop = true;
155module_param_named(snoop, hda_snoop, bool, 0444);
156MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 157#else
158#define hda_snoop true
27fe48d9
TI		 159#endif
160
161
1da177e4
LT		 162MODULE_LICENSE("GPL");
163MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
164 "{Intel, ICH6M},"
2f1b3818 165 "{Intel, ICH7},"
f5d40b30 166 "{Intel, ESB2},"
d2981393 167 "{Intel, ICH8},"
f9cc8a8b 168 "{Intel, ICH9},"
c34f5a04 169 "{Intel, ICH10},"
b29c2360 170 "{Intel, PCH},"
d2f2fcd2 171 "{Intel, CPT},"
d2edeb7c 172 "{Intel, PPT},"
8bc039a1 173 "{Intel, LPT},"
144dad99 174 "{Intel, LPT_LP},"
4eeca499 175 "{Intel, WPT_LP},"
e926f2c8 176 "{Intel, HPT},"
cea310e8 177 "{Intel, PBG},"
4979bca9 178 "{Intel, SCH},"
fc20a562 179 "{ATI, SB450},"
89be83f8 180 "{ATI, SB600},"
778b6e1b 181 "{ATI, RS600},"
5b15c95f 182 "{ATI, RS690},"
e6db1119
WL		 183 "{ATI, RS780},"
184 "{ATI, R600},"
2797f724
HRK		 185 "{ATI, RV630},"
186 "{ATI, RV610},"
27da1834
WL		 187 "{ATI, RV670},"
188 "{ATI, RV635},"
189 "{ATI, RV620},"
190 "{ATI, RV770},"
fc20a562 191 "{VIA, VT8251},"
47672310 192 "{VIA, VT8237A},"
07e4ca50
TI		 193 "{SiS, SIS966},"
194 "{ULI, M5461}}");
1da177e4
LT		 195MODULE_DESCRIPTION("Intel HDA driver");
196
a82d51ed 197#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 198#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 199#define SUPPORT_VGA_SWITCHEROO
200#endif
201#endif
202
203
1da177e4 204/*
1da177e4 205 */
1da177e4 206
07e4ca50
TI		 207/* driver types */
208enum {
209 AZX_DRIVER_ICH,
32679f95 210 AZX_DRIVER_PCH,
4979bca9 211 AZX_DRIVER_SCH,
fab1285a 212 AZX_DRIVER_HDMI,
07e4ca50 213 AZX_DRIVER_ATI,
778b6e1b 214 AZX_DRIVER_ATIHDMI,
1815b34a 215 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 216 AZX_DRIVER_VIA,
217 AZX_DRIVER_SIS,
218 AZX_DRIVER_ULI,
da3fca21 219 AZX_DRIVER_NVIDIA,
f269002e 220 AZX_DRIVER_TERA,
14d34f16 221 AZX_DRIVER_CTX,
5ae763b1 222 AZX_DRIVER_CTHDA,
c4da29ca 223 AZX_DRIVER_GENERIC,
2f5983f2 224 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 225};
226
2ea3c6a2 227/* quirks for Intel PCH */
d7dab4db 228#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 229 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 230 AZX_DCAPS_COUNT_LPIB_DELAY)
231
232#define AZX_DCAPS_INTEL_PCH \
233 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 234
33499a15
TI		 235#define AZX_DCAPS_INTEL_HASWELL \
236 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
237 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
238 AZX_DCAPS_I915_POWERWELL)
239
54a0405d
LY		 240/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
241#define AZX_DCAPS_INTEL_BROADWELL \
242 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
243 AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_PM_RUNTIME | \
244 AZX_DCAPS_I915_POWERWELL)
245
9477c58e
TI		 246/* quirks for ATI SB / AMD Hudson */
247#define AZX_DCAPS_PRESET_ATI_SB \
248 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
249 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
250
251/* quirks for ATI/AMD HDMI */
252#define AZX_DCAPS_PRESET_ATI_HDMI \
253 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
254
255/* quirks for Nvidia */
256#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 257 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
6ba736dd
TI		 258 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT |\
259 AZX_DCAPS_CORBRP_SELF_CLEAR)
9477c58e 260
5ae763b1
TI		 261#define AZX_DCAPS_PRESET_CTHDA \
262 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
263
a82d51ed
TI		 264/*
265 * VGA-switcher support
266 */
267#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 268#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
269#else
270#define use_vga_switcheroo(chip) 0
271#endif
272
48c8b0eb 273static char *driver_short_names[] = {
07e4ca50 274 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 275 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 276 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 277 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 278 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 279 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 280 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 281 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
282 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 283 [AZX_DRIVER_ULI] = "HDA ULI M5461",
284 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 285 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 286 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 287 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 288 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 289};
290
a07187c9
ML		 291
292/* Intel HSW/BDW display HDA controller Extended Mode registers.
293 * EM4 (M value) and EM5 (N Value) are used to convert CDClk (Core Display
294 * Clock) to 24MHz BCLK: BCLK = CDCLK * M / N
295 * The values will be lost when the display power well is disabled.
296 */
297#define ICH6_REG_EM4 0x100c
298#define ICH6_REG_EM5 0x1010
299
300struct hda_intel {
301 struct azx chip;
302
303 /* HSW/BDW display HDA controller to restore BCLK from CDCLK */
304 unsigned int bclk_m;
305 unsigned int bclk_n;
306};
307
308
27fe48d9 309#ifdef CONFIG_X86
9ddf1aeb 310static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 311{
9ddf1aeb
TI		 312 int pages;
313
27fe48d9
TI		 314 if (azx_snoop(chip))
315 return;
9ddf1aeb
TI		 316 if (!dmab || !dmab->area || !dmab->bytes)
317 return;
318
319#ifdef CONFIG_SND_DMA_SGBUF
320 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
321 struct snd_sg_buf *sgbuf = dmab->private_data;
27fe48d9 322 if (on)
9ddf1aeb 323 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 324 else
9ddf1aeb
TI		 325 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
326 return;
27fe48d9 327 }
9ddf1aeb
TI		 328#endif
329
330 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
331 if (on)
332 set_memory_wc((unsigned long)dmab->area, pages);
333 else
334 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 335}
336
337static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
338 bool on)
339{
9ddf1aeb 340 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 341}
342static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 343 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 344{
345 if (azx_dev->wc_marked != on) {
9ddf1aeb 346 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 347 azx_dev->wc_marked = on;
348 }
349}
350#else
351/* NOP for other archs */
352static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
353 bool on)
354{
355}
356static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 357 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 358{
359}
360#endif
361
68e7fffc 362static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 363
cb53c626
TI		 364/*
365 * initialize the PCI registers
366 */
367/* update bits in a PCI register byte */
368static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
369 unsigned char mask, unsigned char val)
370{
371 unsigned char data;
372
373 pci_read_config_byte(pci, reg, &data);
374 data &= ~mask;
375 data |= (val & mask);
376 pci_write_config_byte(pci, reg, data);
377}
378
379static void azx_init_pci(struct azx *chip)
380{
381 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
382 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
383 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 384 * codecs.
385 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 386 */
46f2cc80 387 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 388 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
a09e89f6 389 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 390 }
cb53c626 391
9477c58e
TI		 392 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
393 * we need to enable snoop.
394 */
395 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
4e76a883
TI		 396 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
397 azx_snoop(chip));
cb53c626 398 update_pci_byte(chip->pci,
27fe48d9
TI		 399 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
400 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 401 }
402
403 /* For NVIDIA HDA, enable snoop */
404 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
4e76a883
TI		 405 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
406 azx_snoop(chip));
cb53c626
TI		 407 update_pci_byte(chip->pci,
408 NVIDIA_HDA_TRANSREG_ADDR,
409 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 410 update_pci_byte(chip->pci,
411 NVIDIA_HDA_ISTRM_COH,
412 0x01, NVIDIA_HDA_ENABLE_COHBIT);
413 update_pci_byte(chip->pci,
414 NVIDIA_HDA_OSTRM_COH,
415 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 416 }
417
418 /* Enable SCH/PCH snoop if needed */
419 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 420 unsigned short snoop;
90a5ad52 421 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 422 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
423 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
424 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
425 if (!azx_snoop(chip))
426 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
427 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 428 pci_read_config_word(chip->pci,
429 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 430 }
4e76a883
TI		 431 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
432 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
433 "Disabled" : "Enabled");
da3fca21 434 }
1da177e4
LT		 435}
436
9ad593f6
TI		 437static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
438
7ca954a8
DR		 439/* called from IRQ */
440static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
441{
442 int ok;
443
444 ok = azx_position_ok(chip, azx_dev);
445 if (ok == 1) {
446 azx_dev->irq_pending = 0;
447 return ok;
448 } else if (ok == 0 && chip->bus && chip->bus->workq) {
449 /* bogus IRQ, process it later */
450 azx_dev->irq_pending = 1;
451 queue_work(chip->bus->workq, &chip->irq_pending_work);
452 }
453 return 0;
454}
455
9ad593f6
TI		 456/*
457 * Check whether the current DMA position is acceptable for updating
458 * periods. Returns non-zero if it's OK.
459 *
460 * Many HD-audio controllers appear pretty inaccurate about
461 * the update-IRQ timing. The IRQ is issued before actually the
462 * data is processed. So, we need to process it afterwords in a
463 * workqueue.
464 */
465static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
466{
e5463720 467 u32 wallclk;
9ad593f6
TI		 468 unsigned int pos;
469
f48f606d
JK		 470 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
471 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 472 return -1; /* bogus (too early) interrupt */
fa00e046 473
798cb7e8 474 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 475
d6d8bf54
TI		 476 if (WARN_ONCE(!azx_dev->period_bytes,
477 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 478 return -1; /* this shouldn't happen! */
edb39935 479 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 480 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
481 /* NG - it's below the first next period boundary */
9cdc0115 482 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 483 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 484 return 1; /* OK, it's fine */
485}
486
487/*
488 * The work for pending PCM period updates.
489 */
490static void azx_irq_pending_work(struct work_struct *work)
491{
492 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 493 int i, pending, ok;
9ad593f6 494
a6a950a8 495 if (!chip->irq_pending_warned) {
4e76a883
TI		 496 dev_info(chip->card->dev,
497 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
498 chip->card->number);
a6a950a8
TI		 499 chip->irq_pending_warned = 1;
500 }
501
9ad593f6
TI		 502 for (;;) {
503 pending = 0;
504 spin_lock_irq(&chip->reg_lock);
505 for (i = 0; i < chip->num_streams; i++) {
506 struct azx_dev *azx_dev = &chip->azx_dev[i];
507 if (!azx_dev->irq_pending ||
508 !azx_dev->substream ||
509 !azx_dev->running)
510 continue;
e5463720
JK		 511 ok = azx_position_ok(chip, azx_dev);
512 if (ok > 0) {
9ad593f6
TI		 513 azx_dev->irq_pending = 0;
514 spin_unlock(&chip->reg_lock);
515 snd_pcm_period_elapsed(azx_dev->substream);
516 spin_lock(&chip->reg_lock);
e5463720
JK		 517 } else if (ok < 0) {
518 pending = 0; /* too early */
9ad593f6
TI		 519 } else
520 pending++;
521 }
522 spin_unlock_irq(&chip->reg_lock);
523 if (!pending)
524 return;
08af495f 525 msleep(1);
9ad593f6
TI		 526 }
527}
528
529/* clear irq_pending flags and assure no on-going workq */
530static void azx_clear_irq_pending(struct azx *chip)
531{
532 int i;
533
534 spin_lock_irq(&chip->reg_lock);
535 for (i = 0; i < chip->num_streams; i++)
536 chip->azx_dev[i].irq_pending = 0;
537 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 538}
539
68e7fffc
TI		 540static int azx_acquire_irq(struct azx *chip, int do_disconnect)
541{
437a5a46
TI		 542 if (request_irq(chip->pci->irq, azx_interrupt,
543 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 544 KBUILD_MODNAME, chip)) {
4e76a883
TI		 545 dev_err(chip->card->dev,
546 "unable to grab IRQ %d, disabling device\n",
547 chip->pci->irq);
68e7fffc
TI		 548 if (do_disconnect)
549 snd_card_disconnect(chip->card);
550 return -1;
551 }
552 chip->irq = chip->pci->irq;
69e13418 553 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 554 return 0;
555}
556
83012a7c 557#ifdef CONFIG_PM
65fcd41d
TI		 558static DEFINE_MUTEX(card_list_lock);
559static LIST_HEAD(card_list);
560
561static void azx_add_card_list(struct azx *chip)
562{
563 mutex_lock(&card_list_lock);
564 list_add(&chip->list, &card_list);
565 mutex_unlock(&card_list_lock);
566}
567
568static void azx_del_card_list(struct azx *chip)
569{
570 mutex_lock(&card_list_lock);
571 list_del_init(&chip->list);
572 mutex_unlock(&card_list_lock);
573}
574
575/* trigger power-save check at writing parameter */
576static int param_set_xint(const char *val, const struct kernel_param *kp)
577{
578 struct azx *chip;
579 struct hda_codec *c;
580 int prev = power_save;
581 int ret = param_set_int(val, kp);
582
583 if (ret || prev == power_save)
584 return ret;
585
586 mutex_lock(&card_list_lock);
587 list_for_each_entry(chip, &card_list, list) {
588 if (!chip->bus || chip->disabled)
589 continue;
590 list_for_each_entry(c, &chip->bus->codec_list, list)
591 snd_hda_power_sync(c);
592 }
593 mutex_unlock(&card_list_lock);
594 return 0;
595}
596#else
597#define azx_add_card_list(chip) /* NOP */
598#define azx_del_card_list(chip) /* NOP */
83012a7c 599#endif /* CONFIG_PM */
5c0b9bec 600
a07187c9
ML		 601static void haswell_save_bclk(struct azx *chip)
602{
603 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
604
605 hda->bclk_m = azx_readw(chip, EM4);
606 hda->bclk_n = azx_readw(chip, EM5);
607}
608
609static void haswell_restore_bclk(struct azx *chip)
610{
611 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
612
613 azx_writew(chip, EM4, hda->bclk_m);
614 azx_writew(chip, EM5, hda->bclk_n);
615}
616
7ccbde57 617#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 618/*
619 * power management
620 */
68cb2b55 621static int azx_suspend(struct device *dev)
1da177e4 622{
68cb2b55
TI		 623 struct pci_dev *pci = to_pci_dev(dev);
624 struct snd_card *card = dev_get_drvdata(dev);
421a1252 625 struct azx *chip = card->private_data;
01b65bfb 626 struct azx_pcm *p;
1da177e4 627
c5c21523
TI		 628 if (chip->disabled)
629 return 0;
630
421a1252 631 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 632 azx_clear_irq_pending(chip);
01b65bfb
TI		 633 list_for_each_entry(p, &chip->pcm_list, list)
634 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 635 if (chip->initialized)
8dd78330 636 snd_hda_suspend(chip->bus);
cb53c626 637 azx_stop_chip(chip);
7295b264 638 azx_enter_link_reset(chip);
30b35399 639 if (chip->irq >= 0) {
43001c95 640 free_irq(chip->irq, chip);
30b35399
TI		 641 chip->irq = -1;
642 }
a07187c9
ML		 643
644 /* Save BCLK M/N values before they become invalid in D3.
645 * Will test if display power well can be released now.
646 */
647 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
648 haswell_save_bclk(chip);
649
68e7fffc 650 if (chip->msi)
43001c95 651 pci_disable_msi(chip->pci);
421a1252
TI		 652 pci_disable_device(pci);
653 pci_save_state(pci);
68cb2b55 654 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 655 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
656 hda_display_power(false);
1da177e4
LT		 657 return 0;
658}
659
68cb2b55 660static int azx_resume(struct device *dev)
1da177e4 661{
68cb2b55
TI		 662 struct pci_dev *pci = to_pci_dev(dev);
663 struct snd_card *card = dev_get_drvdata(dev);
421a1252 664 struct azx *chip = card->private_data;
1da177e4 665
c5c21523
TI		 666 if (chip->disabled)
667 return 0;
668
a07187c9 669 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
99a2008d 670 hda_display_power(true);
a07187c9
ML		 671 haswell_restore_bclk(chip);
672 }
d14a7e0b
TI		 673 pci_set_power_state(pci, PCI_D0);
674 pci_restore_state(pci);
30b35399 675 if (pci_enable_device(pci) < 0) {
4e76a883
TI		 676 dev_err(chip->card->dev,
677 "pci_enable_device failed, disabling device\n");
30b35399
TI		 678 snd_card_disconnect(card);
679 return -EIO;
680 }
681 pci_set_master(pci);
68e7fffc
TI		 682 if (chip->msi)
683 if (pci_enable_msi(pci) < 0)
684 chip->msi = 0;
685 if (azx_acquire_irq(chip, 1) < 0)
30b35399 686 return -EIO;
cb53c626 687 azx_init_pci(chip);
d804ad92 688
17c3ad03 689 azx_init_chip(chip, true);
d804ad92 690
1da177e4 691 snd_hda_resume(chip->bus);
421a1252 692 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 693 return 0;
694}
b8dfc462
ML		 695#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
696
697#ifdef CONFIG_PM_RUNTIME
698static int azx_runtime_suspend(struct device *dev)
699{
700 struct snd_card *card = dev_get_drvdata(dev);
701 struct azx *chip = card->private_data;
702
246efa4a
DA		 703 if (chip->disabled)
704 return 0;
705
706 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
707 return 0;
708
7d4f606c
WX		 709 /* enable controller wake up event */
710 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
711 STATESTS_INT_MASK);
712
b8dfc462 713 azx_stop_chip(chip);
873ce8ad 714 azx_enter_link_reset(chip);
b8dfc462 715 azx_clear_irq_pending(chip);
a07187c9
ML		 716 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
717 haswell_save_bclk(chip);
99a2008d 718 hda_display_power(false);
a07187c9 719 }
b8dfc462
ML		 720 return 0;
721}
722
723static int azx_runtime_resume(struct device *dev)
724{
725 struct snd_card *card = dev_get_drvdata(dev);
726 struct azx *chip = card->private_data;
7d4f606c
WX		 727 struct hda_bus *bus;
728 struct hda_codec *codec;
729 int status;
b8dfc462 730
246efa4a
DA		 731 if (chip->disabled)
732 return 0;
733
734 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
735 return 0;
736
a07187c9 737 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
99a2008d 738 hda_display_power(true);
a07187c9
ML		 739 haswell_restore_bclk(chip);
740 }
7d4f606c
WX		 741
742 /* Read STATESTS before controller reset */
743 status = azx_readw(chip, STATESTS);
744
b8dfc462 745 azx_init_pci(chip);
17c3ad03 746 azx_init_chip(chip, true);
7d4f606c
WX		 747
748 bus = chip->bus;
749 if (status && bus) {
750 list_for_each_entry(codec, &bus->codec_list, list)
751 if (status & (1 << codec->addr))
752 queue_delayed_work(codec->bus->workq,
753 &codec->jackpoll_work, codec->jackpoll_interval);
754 }
755
756 /* disable controller Wake Up event*/
757 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
758 ~STATESTS_INT_MASK);
759
b8dfc462
ML		 760 return 0;
761}
6eb827d2
TI		 762
763static int azx_runtime_idle(struct device *dev)
764{
765 struct snd_card *card = dev_get_drvdata(dev);
766 struct azx *chip = card->private_data;
767
246efa4a
DA		 768 if (chip->disabled)
769 return 0;
770
6eb827d2
TI		 771 if (!power_save_controller ||
772 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
773 return -EBUSY;
774
775 return 0;
776}
777
b8dfc462
ML		 778#endif /* CONFIG_PM_RUNTIME */
779
780#ifdef CONFIG_PM
781static const struct dev_pm_ops azx_pm = {
782 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 783 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 784};
785
68cb2b55
TI		 786#define AZX_PM_OPS &azx_pm
787#else
68cb2b55 788#define AZX_PM_OPS NULL
b8dfc462 789#endif /* CONFIG_PM */
1da177e4
LT		 790
791
0cbf0098
TI		 792/*
793 * reboot notifier for hang-up problem at power-down
794 */
795static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
796{
797 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 798 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 799 azx_stop_chip(chip);
800 return NOTIFY_OK;
801}
802
803static void azx_notifier_register(struct azx *chip)
804{
805 chip->reboot_notifier.notifier_call = azx_halt;
806 register_reboot_notifier(&chip->reboot_notifier);
807}
808
809static void azx_notifier_unregister(struct azx *chip)
810{
811 if (chip->reboot_notifier.notifier_call)
812 unregister_reboot_notifier(&chip->reboot_notifier);
813}
814
48c8b0eb 815static int azx_probe_continue(struct azx *chip);
a82d51ed 816
8393ec4a 817#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 818static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 819
a82d51ed
TI		 820static void azx_vs_set_state(struct pci_dev *pci,
821 enum vga_switcheroo_state state)
822{
823 struct snd_card *card = pci_get_drvdata(pci);
824 struct azx *chip = card->private_data;
825 bool disabled;
826
f4c482a4 827 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 828 if (chip->init_failed)
829 return;
830
831 disabled = (state == VGA_SWITCHEROO_OFF);
832 if (chip->disabled == disabled)
833 return;
834
835 if (!chip->bus) {
836 chip->disabled = disabled;
837 if (!disabled) {
4e76a883
TI		 838 dev_info(chip->card->dev,
839 "Start delayed initialization\n");
5c90680e 840 if (azx_probe_continue(chip) < 0) {
4e76a883 841 dev_err(chip->card->dev, "initialization error\n");
a82d51ed
TI		 842 chip->init_failed = true;
843 }
844 }
845 } else {
4e76a883
TI		 846 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
847 disabled ? "Disabling" : "Enabling");
a82d51ed 848 if (disabled) {
8928756d
DR		 849 pm_runtime_put_sync_suspend(card->dev);
850 azx_suspend(card->dev);
246efa4a
DA		 851 /* when we get suspended by vga switcheroo we end up in D3cold,
852 * however we have no ACPI handle, so pci/acpi can't put us there,
853 * put ourselves there */
854 pci->current_state = PCI_D3cold;
a82d51ed 855 chip->disabled = true;
128960a9 856 if (snd_hda_lock_devices(chip->bus))
4e76a883
TI		 857 dev_warn(chip->card->dev,
858 "Cannot lock devices!\n");
a82d51ed
TI		 859 } else {
860 snd_hda_unlock_devices(chip->bus);
8928756d 861 pm_runtime_get_noresume(card->dev);
a82d51ed 862 chip->disabled = false;
8928756d 863 azx_resume(card->dev);
a82d51ed
TI		 864 }
865 }
866}
867
868static bool azx_vs_can_switch(struct pci_dev *pci)
869{
870 struct snd_card *card = pci_get_drvdata(pci);
871 struct azx *chip = card->private_data;
872
f4c482a4 873 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 874 if (chip->init_failed)
875 return false;
876 if (chip->disabled || !chip->bus)
877 return true;
878 if (snd_hda_lock_devices(chip->bus))
879 return false;
880 snd_hda_unlock_devices(chip->bus);
881 return true;
882}
883
e23e7a14 884static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 885{
886 struct pci_dev *p = get_bound_vga(chip->pci);
887 if (p) {
4e76a883
TI		 888 dev_info(chip->card->dev,
889 "Handle VGA-switcheroo audio client\n");
a82d51ed
TI		 890 chip->use_vga_switcheroo = 1;
891 pci_dev_put(p);
892 }
893}
894
895static const struct vga_switcheroo_client_ops azx_vs_ops = {
896 .set_gpu_state = azx_vs_set_state,
897 .can_switch = azx_vs_can_switch,
898};
899
e23e7a14 900static int register_vga_switcheroo(struct azx *chip)
a82d51ed 901{
128960a9
TI		 902 int err;
903
a82d51ed
TI		 904 if (!chip->use_vga_switcheroo)
905 return 0;
906 /* FIXME: currently only handling DIS controller
907 * is there any machine with two switchable HDMI audio controllers?
908 */
128960a9 909 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 910 VGA_SWITCHEROO_DIS,
911 chip->bus != NULL);
128960a9
TI		 912 if (err < 0)
913 return err;
914 chip->vga_switcheroo_registered = 1;
246efa4a
DA		 915
916 /* register as an optimus hdmi audio power domain */
8928756d
DR		 917 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
918 &chip->hdmi_pm_domain);
128960a9 919 return 0;
a82d51ed
TI		 920}
921#else
922#define init_vga_switcheroo(chip) /* NOP */
923#define register_vga_switcheroo(chip) 0
8393ec4a 924#define check_hdmi_disabled(pci) false
a82d51ed
TI		 925#endif /* SUPPORT_VGA_SWITCHER */
926
1da177e4
LT		 927/*
928 * destructor
929 */
a98f90fd 930static int azx_free(struct azx *chip)
1da177e4 931{
c67e2228 932 struct pci_dev *pci = chip->pci;
a07187c9
ML		 933 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
934
4ce107b9
TI		 935 int i;
936
c67e2228
WX		 937 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
938 && chip->running)
939 pm_runtime_get_noresume(&pci->dev);
940
65fcd41d
TI		 941 azx_del_card_list(chip);
942
0cbf0098
TI		 943 azx_notifier_unregister(chip);
944
f4c482a4 945 chip->init_failed = 1; /* to be sure */
44728e97 946 complete_all(&chip->probe_wait);
f4c482a4 947
a82d51ed
TI		 948 if (use_vga_switcheroo(chip)) {
949 if (chip->disabled && chip->bus)
950 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 951 if (chip->vga_switcheroo_registered)
952 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 953 }
954
ce43fbae 955 if (chip->initialized) {
9ad593f6 956 azx_clear_irq_pending(chip);
07e4ca50 957 for (i = 0; i < chip->num_streams; i++)
1da177e4 958 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 959 azx_stop_chip(chip);
1da177e4
LT		 960 }
961
f000fd80 962 if (chip->irq >= 0)
1da177e4 963 free_irq(chip->irq, (void*)chip);
68e7fffc 964 if (chip->msi)
30b35399 965 pci_disable_msi(chip->pci);
f079c25a
TI		 966 if (chip->remap_addr)
967 iounmap(chip->remap_addr);
1da177e4 968
67908994 969 azx_free_stream_pages(chip);
a82d51ed
TI		 970 if (chip->region_requested)
971 pci_release_regions(chip->pci);
1da177e4 972 pci_disable_device(chip->pci);
07e4ca50 973 kfree(chip->azx_dev);
4918cdab
TI		 974#ifdef CONFIG_SND_HDA_PATCH_LOADER
975 if (chip->fw)
976 release_firmware(chip->fw);
977#endif
99a2008d
WX		 978 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
979 hda_display_power(false);
980 hda_i915_exit();
981 }
a07187c9 982 kfree(hda);
1da177e4
LT		 983
984 return 0;
985}
986
a98f90fd 987static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 988{
989 return azx_free(device->device_data);
990}
991
8393ec4a 992#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 993/*
994 * Check of disabled HDMI controller by vga-switcheroo
995 */
e23e7a14 996static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 997{
998 struct pci_dev *p;
999
1000 /* check only discrete GPU */
1001 switch (pci->vendor) {
1002 case PCI_VENDOR_ID_ATI:
1003 case PCI_VENDOR_ID_AMD:
1004 case PCI_VENDOR_ID_NVIDIA:
1005 if (pci->devfn == 1) {
1006 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1007 pci->bus->number, 0);
1008 if (p) {
1009 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1010 return p;
1011 pci_dev_put(p);
1012 }
1013 }
1014 break;
1015 }
1016 return NULL;
1017}
1018
e23e7a14 1019static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1020{
1021 bool vga_inactive = false;
1022 struct pci_dev *p = get_bound_vga(pci);
1023
1024 if (p) {
12b78a7f 1025 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1026 vga_inactive = true;
1027 pci_dev_put(p);
1028 }
1029 return vga_inactive;
1030}
8393ec4a 1031#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1032
3372a153
TI		 1033/*
1034 * white/black-listing for position_fix
1035 */
e23e7a14 1036static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1037 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1038 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1039 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1040 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1041 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1042 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1043 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1044 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1045 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1046 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1047 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1048 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1049 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1050 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1051 {}
1052};
1053
e23e7a14 1054static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1055{
1056 const struct snd_pci_quirk *q;
1057
c673ba1c 1058 switch (fix) {
1dac6695 1059 case POS_FIX_AUTO:
c673ba1c
TI		 1060 case POS_FIX_LPIB:
1061 case POS_FIX_POSBUF:
4cb36310 1062 case POS_FIX_VIACOMBO:
a6f2fd55 1063 case POS_FIX_COMBO:
c673ba1c
TI		 1064 return fix;
1065 }
1066
c673ba1c
TI		 1067 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1068 if (q) {
4e76a883
TI		 1069 dev_info(chip->card->dev,
1070 "position_fix set to %d for device %04x:%04x\n",
1071 q->value, q->subvendor, q->subdevice);
c673ba1c 1072 return q->value;
3372a153 1073 }
bdd9ef24
DH		 1074
1075 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1076 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1077 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1078 return POS_FIX_VIACOMBO;
9477c58e
TI		 1079 }
1080 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1081 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1082 return POS_FIX_LPIB;
bdd9ef24 1083 }
c673ba1c 1084 return POS_FIX_AUTO;
3372a153
TI		 1085}
1086
669ba27a
TI		 1087/*
1088 * black-lists for probe_mask
1089 */
e23e7a14 1090static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1091 /* Thinkpad often breaks the controller communication when accessing
1092 * to the non-working (or non-existing) modem codec slot.
1093 */
1094 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1095 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1096 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1097 /* broken BIOS */
1098 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1099 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1100 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1101 /* forced codec slots */
93574844 1102 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1103 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1104 /* WinFast VP200 H (Teradici) user reported broken communication */
1105 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1106 {}
1107};
1108
f1eaaeec
TI		 1109#define AZX_FORCE_CODEC_MASK 0x100
1110
e23e7a14 1111static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1112{
1113 const struct snd_pci_quirk *q;
1114
f1eaaeec
TI		 1115 chip->codec_probe_mask = probe_mask[dev];
1116 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1117 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1118 if (q) {
4e76a883
TI		 1119 dev_info(chip->card->dev,
1120 "probe_mask set to 0x%x for device %04x:%04x\n",
1121 q->value, q->subvendor, q->subdevice);
f1eaaeec 1122 chip->codec_probe_mask = q->value;
669ba27a
TI		 1123 }
1124 }
f1eaaeec
TI		 1125
1126 /* check forced option */
1127 if (chip->codec_probe_mask != -1 &&
1128 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1129 chip->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883
TI		 1130 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1131 chip->codec_mask);
f1eaaeec 1132 }
669ba27a
TI		 1133}
1134
4d8e22e0 1135/*
71623855 1136 * white/black-list for enable_msi
4d8e22e0 1137 */
e23e7a14 1138static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1139 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1140 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1141 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1142 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1143 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1144 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1145 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1146 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1147 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1148 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1149 {}
1150};
1151
e23e7a14 1152static void check_msi(struct azx *chip)
4d8e22e0
TI		 1153{
1154 const struct snd_pci_quirk *q;
1155
71623855
TI		 1156 if (enable_msi >= 0) {
1157 chip->msi = !!enable_msi;
4d8e22e0 1158 return;
71623855
TI		 1159 }
1160 chip->msi = 1; /* enable MSI as default */
1161 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1162 if (q) {
4e76a883
TI		 1163 dev_info(chip->card->dev,
1164 "msi for device %04x:%04x set to %d\n",
1165 q->subvendor, q->subdevice, q->value);
4d8e22e0 1166 chip->msi = q->value;
80c43ed7
TI		 1167 return;
1168 }
1169
1170 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1171 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1172 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1173 chip->msi = 0;
4d8e22e0
TI		 1174 }
1175}
1176
a1585d76 1177/* check the snoop mode availability */
e23e7a14 1178static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 1179{
1180 bool snoop = chip->snoop;
1181
1182 switch (chip->driver_type) {
1183 case AZX_DRIVER_VIA:
1184 /* force to non-snoop mode for a new VIA controller
1185 * when BIOS is set
1186 */
1187 if (snoop) {
1188 u8 val;
1189 pci_read_config_byte(chip->pci, 0x42, &val);
1190 if (!(val & 0x80) && chip->pci->revision == 0x30)
1191 snoop = false;
1192 }
1193 break;
1194 case AZX_DRIVER_ATIHDMI_NS:
1195 /* new ATI HDMI requires non-snoop */
1196 snoop = false;
1197 break;
c1279f87
TI		 1198 case AZX_DRIVER_CTHDA:
1199 snoop = false;
1200 break;
a1585d76
TI		 1201 }
1202
1203 if (snoop != chip->snoop) {
4e76a883
TI		 1204 dev_info(chip->card->dev, "Force to %s mode\n",
1205 snoop ? "snoop" : "non-snoop");
a1585d76
TI		 1206 chip->snoop = snoop;
1207 }
1208}
669ba27a 1209
99a2008d
WX		 1210static void azx_probe_work(struct work_struct *work)
1211{
1212 azx_probe_continue(container_of(work, struct azx, probe_work));
1213}
99a2008d 1214
1da177e4
LT		 1215/*
1216 * constructor
1217 */
e23e7a14
BP		 1218static int azx_create(struct snd_card *card, struct pci_dev *pci,
1219 int dev, unsigned int driver_caps,
40830813 1220 const struct hda_controller_ops *hda_ops,
e23e7a14 1221 struct azx **rchip)
1da177e4 1222{
a98f90fd 1223 static struct snd_device_ops ops = {
1da177e4
LT		 1224 .dev_free = azx_dev_free,
1225 };
a07187c9 1226 struct hda_intel *hda;
a82d51ed
TI		 1227 struct azx *chip;
1228 int err;
1da177e4
LT		 1229
1230 *rchip = NULL;
bcd72003 1231
927fc866
PM		 1232 err = pci_enable_device(pci);
1233 if (err < 0)
1da177e4
LT		 1234 return err;
1235
a07187c9
ML		 1236 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1237 if (!hda) {
1238 dev_err(card->dev, "Cannot allocate hda\n");
1da177e4
LT		 1239 pci_disable_device(pci);
1240 return -ENOMEM;
1241 }
1242
a07187c9 1243 chip = &hda->chip;
1da177e4 1244 spin_lock_init(&chip->reg_lock);
62932df8 1245 mutex_init(&chip->open_mutex);
1da177e4
LT		 1246 chip->card = card;
1247 chip->pci = pci;
40830813 1248 chip->ops = hda_ops;
1da177e4 1249 chip->irq = -1;
9477c58e
TI		 1250 chip->driver_caps = driver_caps;
1251 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1252 check_msi(chip);
555e219f 1253 chip->dev_index = dev;
749ee287 1254 chip->jackpoll_ms = jackpoll_ms;
9ad593f6 1255 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 1256 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 1257 INIT_LIST_HEAD(&chip->list);
a82d51ed 1258 init_vga_switcheroo(chip);
f4c482a4 1259 init_completion(&chip->probe_wait);
1da177e4 1260
beaffc39
SG		 1261 chip->position_fix[0] = chip->position_fix[1] =
1262 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 1263 /* combo mode uses LPIB for playback */
1264 if (chip->position_fix[0] == POS_FIX_COMBO) {
1265 chip->position_fix[0] = POS_FIX_LPIB;
1266 chip->position_fix[1] = POS_FIX_AUTO;
1267 }
1268
5aba4f8e 1269 check_probe_mask(chip, dev);
3372a153 1270
27346166 1271 chip->single_cmd = single_cmd;
27fe48d9 1272 chip->snoop = hda_snoop;
a1585d76 1273 azx_check_snoop_available(chip);
c74db86b 1274
5c0d7bc1
TI		 1275 if (bdl_pos_adj[dev] < 0) {
1276 switch (chip->driver_type) {
0c6341ac 1277 case AZX_DRIVER_ICH:
32679f95 1278 case AZX_DRIVER_PCH:
0c6341ac 1279 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1280 break;
1281 default:
0c6341ac 1282 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1283 break;
1284 }
1285 }
9cdc0115 1286 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1287
a82d51ed
TI		 1288 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1289 if (err < 0) {
4e76a883 1290 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1291 azx_free(chip);
1292 return err;
1293 }
1294
99a2008d
WX		 1295 /* continue probing in work context as may trigger request module */
1296 INIT_WORK(&chip->probe_work, azx_probe_work);
99a2008d 1297
a82d51ed 1298 *rchip = chip;
99a2008d 1299
a82d51ed
TI		 1300 return 0;
1301}
1302
48c8b0eb 1303static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1304{
1305 int dev = chip->dev_index;
1306 struct pci_dev *pci = chip->pci;
1307 struct snd_card *card = chip->card;
67908994 1308 int err;
a82d51ed
TI		 1309 unsigned short gcap;
1310
07e4ca50
TI		 1311#if BITS_PER_LONG != 64
1312 /* Fix up base address on ULI M5461 */
1313 if (chip->driver_type == AZX_DRIVER_ULI) {
1314 u16 tmp3;
1315 pci_read_config_word(pci, 0x40, &tmp3);
1316 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1317 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1318 }
1319#endif
1320
927fc866 1321 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1322 if (err < 0)
1da177e4 1323 return err;
a82d51ed 1324 chip->region_requested = 1;
1da177e4 1325
927fc866 1326 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 1327 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 1328 if (chip->remap_addr == NULL) {
4e76a883 1329 dev_err(card->dev, "ioremap error\n");
a82d51ed 1330 return -ENXIO;
1da177e4
LT		 1331 }
1332
68e7fffc
TI		 1333 if (chip->msi)
1334 if (pci_enable_msi(pci) < 0)
1335 chip->msi = 0;
7376d013 1336
a82d51ed
TI		 1337 if (azx_acquire_irq(chip, 0) < 0)
1338 return -EBUSY;
1da177e4
LT		 1339
1340 pci_set_master(pci);
1341 synchronize_irq(chip->irq);
1342
bcd72003 1343 gcap = azx_readw(chip, GCAP);
4e76a883 1344 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1345
dc4c2e6b 1346 /* disable SB600 64bit support for safety */
9477c58e 1347 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 1348 struct pci_dev *p_smbus;
1349 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1350 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1351 NULL);
1352 if (p_smbus) {
1353 if (p_smbus->revision < 0x30)
1354 gcap &= ~ICH6_GCAP_64OK;
1355 pci_dev_put(p_smbus);
1356 }
1357 }
09240cf4 1358
9477c58e
TI		 1359 /* disable 64bit DMA address on some devices */
1360 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1361 dev_dbg(card->dev, "Disabling 64bit DMA\n");
396087ea 1362 gcap &= ~ICH6_GCAP_64OK;
9477c58e 1363 }
396087ea 1364
2ae66c26 1365 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1366 if (align_buffer_size >= 0)
1367 chip->align_buffer_size = !!align_buffer_size;
1368 else {
1369 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
1370 chip->align_buffer_size = 0;
1371 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
1372 chip->align_buffer_size = 1;
1373 else
1374 chip->align_buffer_size = 1;
1375 }
2ae66c26 1376
cf7aaca8 1377 /* allow 64bit DMA address if supported by H/W */
b21fadb9 1378 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 1379 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 1380 else {
e930438c
YH		 1381 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1382 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 1383 }
cf7aaca8 1384
8b6ed8e7
TI		 1385 /* read number of streams from GCAP register instead of using
1386 * hardcoded value
1387 */
1388 chip->capture_streams = (gcap >> 8) & 0x0f;
1389 chip->playback_streams = (gcap >> 12) & 0x0f;
1390 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1391 /* gcap didn't give any info, switching to old method */
1392
1393 switch (chip->driver_type) {
1394 case AZX_DRIVER_ULI:
1395 chip->playback_streams = ULI_NUM_PLAYBACK;
1396 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1397 break;
1398 case AZX_DRIVER_ATIHDMI:
1815b34a 1399 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1400 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1401 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1402 break;
c4da29ca 1403 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1404 default:
1405 chip->playback_streams = ICH6_NUM_PLAYBACK;
1406 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1407 break;
1408 }
07e4ca50 1409 }
8b6ed8e7
TI		 1410 chip->capture_index_offset = 0;
1411 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1412 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 1413 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1414 GFP_KERNEL);
927fc866 1415 if (!chip->azx_dev) {
4e76a883 1416 dev_err(card->dev, "cannot malloc azx_dev\n");
a82d51ed 1417 return -ENOMEM;
07e4ca50
TI		 1418 }
1419
67908994 1420 err = azx_alloc_stream_pages(chip);
81740861 1421 if (err < 0)
a82d51ed 1422 return err;
1da177e4
LT		 1423
1424 /* initialize streams */
1425 azx_init_stream(chip);
1426
1427 /* initialize chip */
cb53c626 1428 azx_init_pci(chip);
10e77dda 1429 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1430
1431 /* codec detection */
927fc866 1432 if (!chip->codec_mask) {
4e76a883 1433 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1434 return -ENODEV;
1da177e4
LT		 1435 }
1436
07e4ca50 1437 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1438 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1439 sizeof(card->shortname));
1440 snprintf(card->longname, sizeof(card->longname),
1441 "%s at 0x%lx irq %i",
1442 card->shortname, chip->addr, chip->irq);
07e4ca50 1443
1da177e4 1444 return 0;
1da177e4
LT		 1445}
1446
cb53c626
TI		 1447static void power_down_all_codecs(struct azx *chip)
1448{
83012a7c 1449#ifdef CONFIG_PM
cb53c626
TI		 1450 /* The codecs were powered up in snd_hda_codec_new().
1451 * Now all initialization done, so turn them down if possible
1452 */
1453 struct hda_codec *codec;
1454 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1455 snd_hda_power_down(codec);
1456 }
1457#endif
1458}
1459
97c6a3d1 1460#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1461/* callback from request_firmware_nowait() */
1462static void azx_firmware_cb(const struct firmware *fw, void *context)
1463{
1464 struct snd_card *card = context;
1465 struct azx *chip = card->private_data;
1466 struct pci_dev *pci = chip->pci;
1467
1468 if (!fw) {
4e76a883 1469 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1470 goto error;
1471 }
1472
1473 chip->fw = fw;
1474 if (!chip->disabled) {
1475 /* continue probing */
1476 if (azx_probe_continue(chip))
1477 goto error;
1478 }
1479 return; /* OK */
1480
1481 error:
1482 snd_card_free(card);
1483 pci_set_drvdata(pci, NULL);
1484}
97c6a3d1 1485#endif
5cb543db 1486
40830813
DR		 1487/*
1488 * HDA controller ops.
1489 */
1490
1491/* PCI register access. */
db291e36 1492static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1493{
1494 writel(value, addr);
1495}
1496
db291e36 1497static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1498{
1499 return readl(addr);
1500}
1501
db291e36 1502static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1503{
1504 writew(value, addr);
1505}
1506
db291e36 1507static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1508{
1509 return readw(addr);
1510}
1511
db291e36 1512static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1513{
1514 writeb(value, addr);
1515}
1516
db291e36 1517static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1518{
1519 return readb(addr);
1520}
1521
f46ea609
DR		 1522static int disable_msi_reset_irq(struct azx *chip)
1523{
1524 int err;
1525
1526 free_irq(chip->irq, chip);
1527 chip->irq = -1;
1528 pci_disable_msi(chip->pci);
1529 chip->msi = 0;
1530 err = azx_acquire_irq(chip, 1);
1531 if (err < 0)
1532 return err;
1533
1534 return 0;
1535}
1536
b419b35b
DR		 1537/* DMA page allocation helpers. */
1538static int dma_alloc_pages(struct azx *chip,
1539 int type,
1540 size_t size,
1541 struct snd_dma_buffer *buf)
1542{
1543 int err;
1544
1545 err = snd_dma_alloc_pages(type,
1546 chip->card->dev,
1547 size, buf);
1548 if (err < 0)
1549 return err;
1550 mark_pages_wc(chip, buf, true);
1551 return 0;
1552}
1553
1554static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1555{
1556 mark_pages_wc(chip, buf, false);
1557 snd_dma_free_pages(buf);
1558}
1559
1560static int substream_alloc_pages(struct azx *chip,
1561 struct snd_pcm_substream *substream,
1562 size_t size)
1563{
1564 struct azx_dev *azx_dev = get_azx_dev(substream);
1565 int ret;
1566
1567 mark_runtime_wc(chip, azx_dev, substream, false);
1568 azx_dev->bufsize = 0;
1569 azx_dev->period_bytes = 0;
1570 azx_dev->format_val = 0;
1571 ret = snd_pcm_lib_malloc_pages(substream, size);
1572 if (ret < 0)
1573 return ret;
1574 mark_runtime_wc(chip, azx_dev, substream, true);
1575 return 0;
1576}
1577
1578static int substream_free_pages(struct azx *chip,
1579 struct snd_pcm_substream *substream)
1580{
1581 struct azx_dev *azx_dev = get_azx_dev(substream);
1582 mark_runtime_wc(chip, azx_dev, substream, false);
1583 return snd_pcm_lib_free_pages(substream);
1584}
1585
8769b278
DR		 1586static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1587 struct vm_area_struct *area)
1588{
1589#ifdef CONFIG_X86
1590 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1591 struct azx *chip = apcm->chip;
1592 if (!azx_snoop(chip))
1593 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1594#endif
1595}
1596
40830813 1597static const struct hda_controller_ops pci_hda_ops = {
778bde6f
DR		 1598 .reg_writel = pci_azx_writel,
1599 .reg_readl = pci_azx_readl,
1600 .reg_writew = pci_azx_writew,
1601 .reg_readw = pci_azx_readw,
1602 .reg_writeb = pci_azx_writeb,
1603 .reg_readb = pci_azx_readb,
f46ea609 1604 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1605 .dma_alloc_pages = dma_alloc_pages,
1606 .dma_free_pages = dma_free_pages,
1607 .substream_alloc_pages = substream_alloc_pages,
1608 .substream_free_pages = substream_free_pages,
8769b278 1609 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1610 .position_check = azx_position_check,
40830813
DR		 1611};
1612
e23e7a14
BP		 1613static int azx_probe(struct pci_dev *pci,
1614 const struct pci_device_id *pci_id)
1da177e4 1615{
5aba4f8e 1616 static int dev;
a98f90fd
TI		 1617 struct snd_card *card;
1618 struct azx *chip;
aad730d0 1619 bool schedule_probe;
927fc866 1620 int err;
1da177e4 1621
5aba4f8e
TI		 1622 if (dev >= SNDRV_CARDS)
1623 return -ENODEV;
1624 if (!enable[dev]) {
1625 dev++;
1626 return -ENOENT;
1627 }
1628
60c5772b
TI		 1629 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1630 0, &card);
e58de7ba 1631 if (err < 0) {
4e76a883 1632 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1633 return err;
1da177e4
LT		 1634 }
1635
40830813
DR		 1636 err = azx_create(card, pci, dev, pci_id->driver_data,
1637 &pci_hda_ops, &chip);
41dda0fd
WF		 1638 if (err < 0)
1639 goto out_free;
421a1252 1640 card->private_data = chip;
f4c482a4
TI		 1641
1642 pci_set_drvdata(pci, card);
1643
1644 err = register_vga_switcheroo(chip);
1645 if (err < 0) {
4e76a883 1646 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1647 goto out_free;
1648 }
1649
1650 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1651 dev_info(card->dev, "VGA controller is disabled\n");
1652 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1653 chip->disabled = true;
1654 }
1655
aad730d0 1656 schedule_probe = !chip->disabled;
1da177e4 1657
4918cdab
TI		 1658#ifdef CONFIG_SND_HDA_PATCH_LOADER
1659 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1660 dev_info(card->dev, "Applying patch firmware '%s'\n",
1661 patch[dev]);
5cb543db
TI		 1662 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1663 &pci->dev, GFP_KERNEL, card,
1664 azx_firmware_cb);
4918cdab
TI		 1665 if (err < 0)
1666 goto out_free;
aad730d0 1667 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1668 }
1669#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1670
aad730d0
TI		 1671#ifndef CONFIG_SND_HDA_I915
1672 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1673 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1674#endif
99a2008d 1675
aad730d0
TI		 1676 if (schedule_probe)
1677 schedule_work(&chip->probe_work);
a82d51ed 1678
a82d51ed 1679 dev++;
88d071fc
TI		 1680 if (chip->disabled)
1681 complete_all(&chip->probe_wait);
a82d51ed
TI		 1682 return 0;
1683
1684out_free:
1685 snd_card_free(card);
1686 return err;
1687}
1688
e62a42ae
DR		 1689/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1690static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1691 [AZX_DRIVER_NVIDIA] = 8,
1692 [AZX_DRIVER_TERA] = 1,
1693};
1694
48c8b0eb 1695static int azx_probe_continue(struct azx *chip)
a82d51ed 1696{
c67e2228 1697 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1698 int dev = chip->dev_index;
1699 int err;
1700
99a2008d
WX		 1701 /* Request power well for Haswell HDA controller and codec */
1702 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 1703#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 1704 err = hda_i915_init();
1705 if (err < 0) {
4e76a883
TI		 1706 dev_err(chip->card->dev,
1707 "Error request power-well from i915\n");
99a2008d
WX		 1708 goto out_free;
1709 }
74b0c2d7
TI		 1710 err = hda_display_power(true);
1711 if (err < 0) {
1712 dev_err(chip->card->dev,
1713 "Cannot turn on display power on i915\n");
1714 goto out_free;
1715 }
c841ad2a 1716#endif
99a2008d
WX		 1717 }
1718
5c90680e
TI		 1719 err = azx_first_init(chip);
1720 if (err < 0)
1721 goto out_free;
1722
2dca0bba
JK		 1723#ifdef CONFIG_SND_HDA_INPUT_BEEP
1724 chip->beep_mode = beep_mode[dev];
1725#endif
1726
1da177e4 1727 /* create codec instances */
e62a42ae
DR		 1728 err = azx_codec_create(chip, model[dev],
1729 azx_max_codecs[chip->driver_type],
1730 power_save_addr);
1731
41dda0fd
WF		 1732 if (err < 0)
1733 goto out_free;
4ea6fbc8 1734#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 1735 if (chip->fw) {
1736 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1737 chip->fw->data);
4ea6fbc8
TI		 1738 if (err < 0)
1739 goto out_free;
e39ae856 1740#ifndef CONFIG_PM
4918cdab
TI		 1741 release_firmware(chip->fw); /* no longer needed */
1742 chip->fw = NULL;
e39ae856 1743#endif
4ea6fbc8
TI		 1744 }
1745#endif
10e77dda 1746 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 1747 err = azx_codec_configure(chip);
1748 if (err < 0)
1749 goto out_free;
1750 }
1da177e4
LT		 1751
1752 /* create PCM streams */
176d5335 1753 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 1754 if (err < 0)
1755 goto out_free;
1da177e4
LT		 1756
1757 /* create mixer controls */
d01ce99f 1758 err = azx_mixer_create(chip);
41dda0fd
WF		 1759 if (err < 0)
1760 goto out_free;
1da177e4 1761
a82d51ed 1762 err = snd_card_register(chip->card);
41dda0fd
WF		 1763 if (err < 0)
1764 goto out_free;
1da177e4 1765
cb53c626
TI		 1766 chip->running = 1;
1767 power_down_all_codecs(chip);
0cbf0098 1768 azx_notifier_register(chip);
65fcd41d 1769 azx_add_card_list(chip);
246efa4a 1770 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
c67e2228 1771 pm_runtime_put_noidle(&pci->dev);
1da177e4 1772
41dda0fd 1773out_free:
88d071fc
TI		 1774 if (err < 0)
1775 chip->init_failed = 1;
1776 complete_all(&chip->probe_wait);
41dda0fd 1777 return err;
1da177e4
LT		 1778}
1779
e23e7a14 1780static void azx_remove(struct pci_dev *pci)
1da177e4 1781{
9121947d 1782 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 1783
9121947d
TI		 1784 if (card)
1785 snd_card_free(card);
1da177e4
LT		 1786}
1787
1788/* PCI IDs */
6f51f6cf 1789static const struct pci_device_id azx_ids[] = {
d2f2fcd2 1790 /* CPT */
9477c58e 1791 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 1792 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 1793 /* PBG */
9477c58e 1794 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 1795 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 1796 /* Panther Point */
9477c58e 1797 { PCI_DEVICE(0x8086, 0x1e20),
b1920c21 1798 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 1799 /* Lynx Point */
1800 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 1801 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 1802 /* 9 Series */
1803 { PCI_DEVICE(0x8086, 0x8ca0),
1804 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 1805 /* Wellsburg */
1806 { PCI_DEVICE(0x8086, 0x8d20),
1807 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1808 { PCI_DEVICE(0x8086, 0x8d21),
1809 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1810 /* Lynx Point-LP */
1811 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 1812 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1813 /* Lynx Point-LP */
1814 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 1815 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 1816 /* Wildcat Point-LP */
1817 { PCI_DEVICE(0x8086, 0x9ca0),
1818 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 1819 /* Haswell */
4a7c516b 1820 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 1821 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 1822 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 1823 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 1824 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 1825 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 1826 /* Broadwell */
1827 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 1828 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 1829 /* 5 Series/3400 */
1830 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 1831 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 1832 /* Poulsbo */
9477c58e 1833 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 1834 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
1835 /* Oaktrail */
09904b95 1836 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 1837 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 1838 /* BayTrail */
1839 { PCI_DEVICE(0x8086, 0x0f04),
1840 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
645e9035 1841 /* ICH */
8b0bd226 1842 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 1843 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1844 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 1845 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 1846 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1847 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 1848 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 1849 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1850 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 1851 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 1852 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1853 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 1854 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 1855 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1856 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 1857 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 1858 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1859 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 1860 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 1861 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1862 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 1863 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 1864 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1865 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 1866 /* Generic Intel */
1867 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
1868 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1869 .class_mask = 0xffffff,
2ae66c26 1870 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 1871 /* ATI SB 450/600/700/800/900 */
1872 { PCI_DEVICE(0x1002, 0x437b),
1873 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
1874 { PCI_DEVICE(0x1002, 0x4383),
1875 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
1876 /* AMD Hudson */
1877 { PCI_DEVICE(0x1022, 0x780d),
1878 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 1879 /* ATI HDMI */
9477c58e
TI		 1880 { PCI_DEVICE(0x1002, 0x793b),
1881 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1882 { PCI_DEVICE(0x1002, 0x7919),
1883 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1884 { PCI_DEVICE(0x1002, 0x960f),
1885 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1886 { PCI_DEVICE(0x1002, 0x970f),
1887 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1888 { PCI_DEVICE(0x1002, 0xaa00),
1889 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1890 { PCI_DEVICE(0x1002, 0xaa08),
1891 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1892 { PCI_DEVICE(0x1002, 0xaa10),
1893 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1894 { PCI_DEVICE(0x1002, 0xaa18),
1895 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1896 { PCI_DEVICE(0x1002, 0xaa20),
1897 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1898 { PCI_DEVICE(0x1002, 0xaa28),
1899 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1900 { PCI_DEVICE(0x1002, 0xaa30),
1901 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1902 { PCI_DEVICE(0x1002, 0xaa38),
1903 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1904 { PCI_DEVICE(0x1002, 0xaa40),
1905 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1906 { PCI_DEVICE(0x1002, 0xaa48),
1907 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 1908 { PCI_DEVICE(0x1002, 0xaa50),
1909 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1910 { PCI_DEVICE(0x1002, 0xaa58),
1911 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1912 { PCI_DEVICE(0x1002, 0xaa60),
1913 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1914 { PCI_DEVICE(0x1002, 0xaa68),
1915 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1916 { PCI_DEVICE(0x1002, 0xaa80),
1917 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1918 { PCI_DEVICE(0x1002, 0xaa88),
1919 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1920 { PCI_DEVICE(0x1002, 0xaa90),
1921 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1922 { PCI_DEVICE(0x1002, 0xaa98),
1923 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 1924 { PCI_DEVICE(0x1002, 0x9902),
1925 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1926 { PCI_DEVICE(0x1002, 0xaaa0),
1927 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1928 { PCI_DEVICE(0x1002, 0xaaa8),
1929 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1930 { PCI_DEVICE(0x1002, 0xaab0),
1931 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 1932 /* VIA VT8251/VT8237A */
9477c58e
TI		 1933 { PCI_DEVICE(0x1106, 0x3288),
1934 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 1935 /* VIA GFX VT7122/VX900 */
1936 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
1937 /* VIA GFX VT6122/VX11 */
1938 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 1939 /* SIS966 */
1940 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
1941 /* ULI M5461 */
1942 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
1943 /* NVIDIA MCP */
0c2fd1bf
TI		 1944 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1945 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1946 .class_mask = 0xffffff,
9477c58e 1947 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 1948 /* Teradici */
9477c58e
TI		 1949 { PCI_DEVICE(0x6549, 0x1200),
1950 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 1951 { PCI_DEVICE(0x6549, 0x2200),
1952 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 1953 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 1954 /* CTHDA chips */
1955 { PCI_DEVICE(0x1102, 0x0010),
1956 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
1957 { PCI_DEVICE(0x1102, 0x0012),
1958 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 1959#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 1960 /* the following entry conflicts with snd-ctxfi driver,
1961 * as ctxfi driver mutates from HD-audio to native mode with
1962 * a special command sequence.
1963 */
4e01f54b
TI		 1964 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
1965 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1966 .class_mask = 0xffffff,
9477c58e 1967 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 1968 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 1969#else
1970 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 1971 { PCI_DEVICE(0x1102, 0x0009),
1972 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 1973 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 1974#endif
e35d4b11
OS		 1975 /* Vortex86MX */
1976 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 1977 /* VMware HDAudio */
1978 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 1979 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 1980 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
1981 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1982 .class_mask = 0xffffff,
9477c58e 1983 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 1984 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
1985 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1986 .class_mask = 0xffffff,
9477c58e 1987 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 1988 { 0, }
1989};
1990MODULE_DEVICE_TABLE(pci, azx_ids);
1991
1992/* pci_driver definition */
e9f66d9b 1993static struct pci_driver azx_driver = {
3733e424 1994 .name = KBUILD_MODNAME,
1da177e4
LT		 1995 .id_table = azx_ids,
1996 .probe = azx_probe,
e23e7a14 1997 .remove = azx_remove,
68cb2b55
TI		 1998 .driver = {
1999 .pm = AZX_PM_OPS,
2000 },
1da177e4
LT		 2001};
2002
e9f66d9b 2003module_pci_driver(azx_driver);
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