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ALSA: hda - Fix DMA mask for ATI controllers
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
362775e2 40#include <linux/kernel.h>
1da177e4 41#include <linux/module.h>
24982c5f 42#include <linux/dma-mapping.h>
1da177e4
LT		 43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
62932df8 47#include <linux/mutex.h>
0cbf0098 48#include <linux/reboot.h>
1da177e4
LT		 49#include <sound/core.h>
50#include <sound/initval.h>
51#include "hda_codec.h"
52
53
5aba4f8e
TI		 54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57static char *model[SNDRV_CARDS];
58static int position_fix[SNDRV_CARDS];
5c0d7bc1 59static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 60static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 61static int probe_only[SNDRV_CARDS];
27346166 62static int single_cmd;
134a11f0 63static int enable_msi;
1da177e4 64
5aba4f8e 65module_param_array(index, int, NULL, 0444);
1da177e4 66MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 67module_param_array(id, charp, NULL, 0444);
1da177e4 68MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 69module_param_array(enable, bool, NULL, 0444);
70MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
71module_param_array(model, charp, NULL, 0444);
1da177e4 72MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 73module_param_array(position_fix, int, NULL, 0444);
d01ce99f 74MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
d2e1c973 75 "(0 = auto, 1 = none, 2 = POSBUF).");
555e219f
TI		 76module_param_array(bdl_pos_adj, int, NULL, 0644);
77MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 78module_param_array(probe_mask, int, NULL, 0444);
606ad75f 79MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
d4d9cd03
TI		 80module_param_array(probe_only, bool, NULL, 0444);
81MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 82module_param(single_cmd, bool, 0444);
d01ce99f
TI		 83MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
84 "(for debugging only).");
5aba4f8e 85module_param(enable_msi, int, 0444);
134a11f0 86MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
606ad75f 87
dee1b66c 88#ifdef CONFIG_SND_HDA_POWER_SAVE
fee2fba3
TI		 89static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
90module_param(power_save, int, 0644);
91MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
92 "(in second, 0 = disable).");
1da177e4 93
dee1b66c
TI		 94/* reset the HD-audio controller in power save mode.
95 * this may give more power-saving, but will take longer time to
96 * wake up.
97 */
98static int power_save_controller = 1;
99module_param(power_save_controller, bool, 0644);
100MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
101#endif
102
1da177e4
LT		 103MODULE_LICENSE("GPL");
104MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
105 "{Intel, ICH6M},"
2f1b3818 106 "{Intel, ICH7},"
f5d40b30 107 "{Intel, ESB2},"
d2981393 108 "{Intel, ICH8},"
f9cc8a8b 109 "{Intel, ICH9},"
c34f5a04 110 "{Intel, ICH10},"
b29c2360 111 "{Intel, PCH},"
4979bca9 112 "{Intel, SCH},"
fc20a562 113 "{ATI, SB450},"
89be83f8 114 "{ATI, SB600},"
778b6e1b 115 "{ATI, RS600},"
5b15c95f 116 "{ATI, RS690},"
e6db1119
WL		 117 "{ATI, RS780},"
118 "{ATI, R600},"
2797f724
HRK		 119 "{ATI, RV630},"
120 "{ATI, RV610},"
27da1834
WL		 121 "{ATI, RV670},"
122 "{ATI, RV635},"
123 "{ATI, RV620},"
124 "{ATI, RV770},"
fc20a562 125 "{VIA, VT8251},"
47672310 126 "{VIA, VT8237A},"
07e4ca50
TI		 127 "{SiS, SIS966},"
128 "{ULI, M5461}}");
1da177e4
LT		 129MODULE_DESCRIPTION("Intel HDA driver");
130
131#define SFX "hda-intel: "
132
cb53c626 133
1da177e4
LT		 134/*
135 * registers
136 */
137#define ICH6_REG_GCAP 0x00
138#define ICH6_REG_VMIN 0x02
139#define ICH6_REG_VMAJ 0x03
140#define ICH6_REG_OUTPAY 0x04
141#define ICH6_REG_INPAY 0x06
142#define ICH6_REG_GCTL 0x08
143#define ICH6_REG_WAKEEN 0x0c
144#define ICH6_REG_STATESTS 0x0e
145#define ICH6_REG_GSTS 0x10
146#define ICH6_REG_INTCTL 0x20
147#define ICH6_REG_INTSTS 0x24
148#define ICH6_REG_WALCLK 0x30
149#define ICH6_REG_SYNC 0x34
150#define ICH6_REG_CORBLBASE 0x40
151#define ICH6_REG_CORBUBASE 0x44
152#define ICH6_REG_CORBWP 0x48
153#define ICH6_REG_CORBRP 0x4A
154#define ICH6_REG_CORBCTL 0x4c
155#define ICH6_REG_CORBSTS 0x4d
156#define ICH6_REG_CORBSIZE 0x4e
157
158#define ICH6_REG_RIRBLBASE 0x50
159#define ICH6_REG_RIRBUBASE 0x54
160#define ICH6_REG_RIRBWP 0x58
161#define ICH6_REG_RINTCNT 0x5a
162#define ICH6_REG_RIRBCTL 0x5c
163#define ICH6_REG_RIRBSTS 0x5d
164#define ICH6_REG_RIRBSIZE 0x5e
165
166#define ICH6_REG_IC 0x60
167#define ICH6_REG_IR 0x64
168#define ICH6_REG_IRS 0x68
169#define ICH6_IRS_VALID (1<<1)
170#define ICH6_IRS_BUSY (1<<0)
171
172#define ICH6_REG_DPLBASE 0x70
173#define ICH6_REG_DPUBASE 0x74
174#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
175
176/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
177enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
178
179/* stream register offsets from stream base */
180#define ICH6_REG_SD_CTL 0x00
181#define ICH6_REG_SD_STS 0x03
182#define ICH6_REG_SD_LPIB 0x04
183#define ICH6_REG_SD_CBL 0x08
184#define ICH6_REG_SD_LVI 0x0c
185#define ICH6_REG_SD_FIFOW 0x0e
186#define ICH6_REG_SD_FIFOSIZE 0x10
187#define ICH6_REG_SD_FORMAT 0x12
188#define ICH6_REG_SD_BDLPL 0x18
189#define ICH6_REG_SD_BDLPU 0x1c
190
191/* PCI space */
192#define ICH6_PCIREG_TCSEL 0x44
193
194/*
195 * other constants
196 */
197
198/* max number of SDs */
07e4ca50 199/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 200#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 201#define ICH6_NUM_PLAYBACK 4
202
203/* ULI has 6 playback and 5 capture */
07e4ca50 204#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 205#define ULI_NUM_PLAYBACK 6
206
778b6e1b 207/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 208#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 209#define ATIHDMI_NUM_PLAYBACK 1
210
f269002e
KY		 211/* TERA has 4 playback and 3 capture */
212#define TERA_NUM_CAPTURE 3
213#define TERA_NUM_PLAYBACK 4
214
07e4ca50
TI		 215/* this number is statically defined for simplicity */
216#define MAX_AZX_DEV 16
217
1da177e4 218/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 219#define BDL_SIZE 4096
220#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
221#define AZX_MAX_FRAG 32
1da177e4
LT		 222/* max buffer size - no h/w limit, you can increase as you like */
223#define AZX_MAX_BUF_SIZE (1024*1024*1024)
224/* max number of PCM devics per card */
7ba72ba1 225#define AZX_MAX_PCMS 8
1da177e4
LT		 226
227/* RIRB int mask: overrun[2], response[0] */
228#define RIRB_INT_RESPONSE 0x01
229#define RIRB_INT_OVERRUN 0x04
230#define RIRB_INT_MASK 0x05
231
2f5983f2
TI		 232/* STATESTS int mask: S3,SD2,SD1,SD0 */
233#define AZX_MAX_CODECS 4
234#define STATESTS_INT_MASK 0x0f
1da177e4
LT		 235
236/* SD_CTL bits */
237#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
238#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 239#define SD_CTL_STRIPE (3 << 16) /* stripe control */
240#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
241#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 242#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
243#define SD_CTL_STREAM_TAG_SHIFT 20
244
245/* SD_CTL and SD_STS */
246#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
247#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
248#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 249#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
250 SD_INT_COMPLETE)
1da177e4
LT		 251
252/* SD_STS */
253#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
254
255/* INTCTL and INTSTS */
d01ce99f
TI		 256#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
257#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
258#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 259
41e2fce4
M		 260/* GCTL unsolicited response enable bit */
261#define ICH6_GCTL_UREN (1<<8)
262
1da177e4
LT		 263/* GCTL reset bit */
264#define ICH6_GCTL_RESET (1<<0)
265
266/* CORB/RIRB control, read/write pointer */
267#define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
268#define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
269#define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
270/* below are so far hardcoded - should read registers in future */
271#define ICH6_MAX_CORB_ENTRIES 256
272#define ICH6_MAX_RIRB_ENTRIES 256
273
c74db86b
TI		 274/* position fix mode */
275enum {
0be3b5d3 276 POS_FIX_AUTO,
d2e1c973 277 POS_FIX_LPIB,
0be3b5d3 278 POS_FIX_POSBUF,
c74db86b 279};
1da177e4 280
f5d40b30 281/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 282#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
283#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
284
da3fca21
V		 285/* Defines for Nvidia HDA support */
286#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
287#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 288#define NVIDIA_HDA_ISTRM_COH 0x4d
289#define NVIDIA_HDA_OSTRM_COH 0x4c
290#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 291
90a5ad52
TI		 292/* Defines for Intel SCH HDA snoop control */
293#define INTEL_SCH_HDA_DEVC 0x78
294#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
295
0e153474
JC		 296/* Define IN stream 0 FIFO size offset in VIA controller */
297#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
298/* Define VIA HD Audio Device ID*/
299#define VIA_HDAC_DEVICE_ID 0x3288
300
c4da29ca
YL		 301/* HD Audio class code */
302#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 303
1da177e4
LT		 304/*
305 */
306
a98f90fd 307struct azx_dev {
4ce107b9 308 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 309 u32 *posbuf; /* position buffer pointer */
1da177e4 310
d01ce99f 311 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 312 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 313 unsigned int frags; /* number for period in the play buffer */
314 unsigned int fifo_size; /* FIFO size */
1da177e4 315
d01ce99f 316 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 317
d01ce99f 318 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 319
320 /* pcm support */
d01ce99f
TI		 321 struct snd_pcm_substream *substream; /* assigned substream,
322 * set in PCM open
323 */
324 unsigned int format_val; /* format value to be set in the
325 * controller and the codec
326 */
1da177e4
LT		 327 unsigned char stream_tag; /* assigned stream */
328 unsigned char index; /* stream index */
329
927fc866
PM		 330 unsigned int opened :1;
331 unsigned int running :1;
675f25d4
TI		 332 unsigned int irq_pending :1;
333 unsigned int irq_ignore :1;
0e153474
JC		 334 /*
335 * For VIA:
336 * A flag to ensure DMA position is 0
337 * when link position is not greater than FIFO size
338 */
339 unsigned int insufficient :1;
1da177e4
LT		 340};
341
342/* CORB/RIRB */
a98f90fd 343struct azx_rb {
1da177e4
LT		 344 u32 *buf; /* CORB/RIRB buffer
345 * Each CORB entry is 4byte, RIRB is 8byte
346 */
347 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
348 /* for RIRB */
349 unsigned short rp, wp; /* read/write pointers */
350 int cmds; /* number of pending requests */
351 u32 res; /* last read value */
352};
353
a98f90fd
TI		 354struct azx {
355 struct snd_card *card;
1da177e4 356 struct pci_dev *pci;
555e219f 357 int dev_index;
1da177e4 358
07e4ca50
TI		 359 /* chip type specific */
360 int driver_type;
361 int playback_streams;
362 int playback_index_offset;
363 int capture_streams;
364 int capture_index_offset;
365 int num_streams;
366
1da177e4
LT		 367 /* pci resources */
368 unsigned long addr;
369 void __iomem *remap_addr;
370 int irq;
371
372 /* locks */
373 spinlock_t reg_lock;
62932df8 374 struct mutex open_mutex;
1da177e4 375
07e4ca50 376 /* streams (x num_streams) */
a98f90fd 377 struct azx_dev *azx_dev;
1da177e4
LT		 378
379 /* PCM */
a98f90fd 380 struct snd_pcm *pcm[AZX_MAX_PCMS];
1da177e4
LT		 381
382 /* HD codec */
383 unsigned short codec_mask;
384 struct hda_bus *bus;
385
386 /* CORB/RIRB */
a98f90fd
TI		 387 struct azx_rb corb;
388 struct azx_rb rirb;
1da177e4 389
4ce107b9 390 /* CORB/RIRB and position buffers */
1da177e4
LT		 391 struct snd_dma_buffer rb;
392 struct snd_dma_buffer posbuf;
c74db86b
TI		 393
394 /* flags */
395 int position_fix;
cb53c626 396 unsigned int running :1;
927fc866
PM		 397 unsigned int initialized :1;
398 unsigned int single_cmd :1;
399 unsigned int polling_mode :1;
68e7fffc 400 unsigned int msi :1;
a6a950a8 401 unsigned int irq_pending_warned :1;
0e153474 402 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
6ce4a3bc 403 unsigned int probing :1; /* codec probing phase */
43bbb6cc
TI		 404
405 /* for debugging */
406 unsigned int last_cmd; /* last issued command (to sync) */
9ad593f6
TI		 407
408 /* for pending irqs */
409 struct work_struct irq_pending_work;
0cbf0098
TI		 410
411 /* reboot notifier (for mysterious hangup problem at power-down) */
412 struct notifier_block reboot_notifier;
1da177e4
LT		 413};
414
07e4ca50
TI		 415/* driver types */
416enum {
417 AZX_DRIVER_ICH,
4979bca9 418 AZX_DRIVER_SCH,
07e4ca50 419 AZX_DRIVER_ATI,
778b6e1b 420 AZX_DRIVER_ATIHDMI,
07e4ca50
TI		 421 AZX_DRIVER_VIA,
422 AZX_DRIVER_SIS,
423 AZX_DRIVER_ULI,
da3fca21 424 AZX_DRIVER_NVIDIA,
f269002e 425 AZX_DRIVER_TERA,
c4da29ca 426 AZX_DRIVER_GENERIC,
2f5983f2 427 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 428};
429
430static char *driver_short_names[] __devinitdata = {
431 [AZX_DRIVER_ICH] = "HDA Intel",
4979bca9 432 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 433 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 434 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI		 435 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
436 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 437 [AZX_DRIVER_ULI] = "HDA ULI M5461",
438 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 439 [AZX_DRIVER_TERA] = "HDA Teradici",
c4da29ca 440 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 441};
442
1da177e4
LT		 443/*
444 * macros for easy use
445 */
446#define azx_writel(chip,reg,value) \
447 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
448#define azx_readl(chip,reg) \
449 readl((chip)->remap_addr + ICH6_REG_##reg)
450#define azx_writew(chip,reg,value) \
451 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
452#define azx_readw(chip,reg) \
453 readw((chip)->remap_addr + ICH6_REG_##reg)
454#define azx_writeb(chip,reg,value) \
455 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
456#define azx_readb(chip,reg) \
457 readb((chip)->remap_addr + ICH6_REG_##reg)
458
459#define azx_sd_writel(dev,reg,value) \
460 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
461#define azx_sd_readl(dev,reg) \
462 readl((dev)->sd_addr + ICH6_REG_##reg)
463#define azx_sd_writew(dev,reg,value) \
464 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
465#define azx_sd_readw(dev,reg) \
466 readw((dev)->sd_addr + ICH6_REG_##reg)
467#define azx_sd_writeb(dev,reg,value) \
468 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
469#define azx_sd_readb(dev,reg) \
470 readb((dev)->sd_addr + ICH6_REG_##reg)
471
472/* for pcm support */
a98f90fd 473#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 474
68e7fffc 475static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1da177e4
LT		 476
477/*
478 * Interface for HD codec
479 */
480
1da177e4
LT		 481/*
482 * CORB / RIRB interface
483 */
a98f90fd 484static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 485{
486 int err;
487
488 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 489 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
490 snd_dma_pci_data(chip->pci),
1da177e4
LT		 491 PAGE_SIZE, &chip->rb);
492 if (err < 0) {
493 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
494 return err;
495 }
496 return 0;
497}
498
a98f90fd 499static void azx_init_cmd_io(struct azx *chip)
1da177e4
LT		 500{
501 /* CORB set up */
502 chip->corb.addr = chip->rb.addr;
503 chip->corb.buf = (u32 *)chip->rb.area;
504 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 505 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 506
07e4ca50
TI		 507 /* set the corb size to 256 entries (ULI requires explicitly) */
508 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 509 /* set the corb write pointer to 0 */
510 azx_writew(chip, CORBWP, 0);
511 /* reset the corb hw read pointer */
512 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
513 /* enable corb dma */
514 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
515
516 /* RIRB set up */
517 chip->rirb.addr = chip->rb.addr + 2048;
518 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
519 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 520 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 521
07e4ca50
TI		 522 /* set the rirb size to 256 entries (ULI requires explicitly) */
523 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4
LT		 524 /* reset the rirb hw write pointer */
525 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
526 /* set N=1, get RIRB response interrupt for new entry */
527 azx_writew(chip, RINTCNT, 1);
528 /* enable rirb dma and response irq */
1da177e4 529 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
1da177e4
LT		 530 chip->rirb.rp = chip->rirb.cmds = 0;
531}
532
a98f90fd 533static void azx_free_cmd_io(struct azx *chip)
1da177e4
LT		 534{
535 /* disable ringbuffer DMAs */
536 azx_writeb(chip, RIRBCTL, 0);
537 azx_writeb(chip, CORBCTL, 0);
538}
539
540/* send a command */
33fa35ed 541static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 542{
33fa35ed 543 struct azx *chip = bus->private_data;
1da177e4 544 unsigned int wp;
1da177e4
LT		 545
546 /* add command to corb */
547 wp = azx_readb(chip, CORBWP);
548 wp++;
549 wp %= ICH6_MAX_CORB_ENTRIES;
550
551 spin_lock_irq(&chip->reg_lock);
552 chip->rirb.cmds++;
553 chip->corb.buf[wp] = cpu_to_le32(val);
554 azx_writel(chip, CORBWP, wp);
555 spin_unlock_irq(&chip->reg_lock);
556
557 return 0;
558}
559
560#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
561
562/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 563static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 564{
565 unsigned int rp, wp;
566 u32 res, res_ex;
567
568 wp = azx_readb(chip, RIRBWP);
569 if (wp == chip->rirb.wp)
570 return;
571 chip->rirb.wp = wp;
572
573 while (chip->rirb.rp != wp) {
574 chip->rirb.rp++;
575 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
576
577 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
578 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
579 res = le32_to_cpu(chip->rirb.buf[rp]);
580 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
581 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
582 else if (chip->rirb.cmds) {
1da177e4 583 chip->rirb.res = res;
2add9b92
TI		 584 smp_wmb();
585 chip->rirb.cmds--;
1da177e4
LT		 586 }
587 }
588}
589
590/* receive a response */
33fa35ed 591static unsigned int azx_rirb_get_response(struct hda_bus *bus)
1da177e4 592{
33fa35ed 593 struct azx *chip = bus->private_data;
5c79b1f8 594 unsigned long timeout;
1da177e4 595
5c79b1f8
TI		 596 again:
597 timeout = jiffies + msecs_to_jiffies(1000);
28a0d9df 598 for (;;) {
e96224ae
TI		 599 if (chip->polling_mode) {
600 spin_lock_irq(&chip->reg_lock);
601 azx_update_rirb(chip);
602 spin_unlock_irq(&chip->reg_lock);
603 }
2add9b92
TI		 604 if (!chip->rirb.cmds) {
605 smp_rmb();
5c79b1f8 606 return chip->rirb.res; /* the last value */
2add9b92 607 }
28a0d9df
TI		 608 if (time_after(jiffies, timeout))
609 break;
33fa35ed 610 if (bus->needs_damn_long_delay)
52987656
TI		 611 msleep(2); /* temporary workaround */
612 else {
613 udelay(10);
614 cond_resched();
615 }
28a0d9df 616 }
5c79b1f8 617
68e7fffc
TI		 618 if (chip->msi) {
619 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
43bbb6cc 620 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
68e7fffc
TI		 621 free_irq(chip->irq, chip);
622 chip->irq = -1;
623 pci_disable_msi(chip->pci);
624 chip->msi = 0;
625 if (azx_acquire_irq(chip, 1) < 0)
626 return -1;
627 goto again;
628 }
629
5c79b1f8
TI		 630 if (!chip->polling_mode) {
631 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
43bbb6cc
TI		 632 "switching to polling mode: last cmd=0x%08x\n",
633 chip->last_cmd);
5c79b1f8
TI		 634 chip->polling_mode = 1;
635 goto again;
1da177e4 636 }
5c79b1f8 637
6ce4a3bc
TI		 638 if (chip->probing) {
639 /* If this critical timeout happens during the codec probing
640 * phase, this is likely an access to a non-existing codec
641 * slot. Better to return an error and reset the system.
642 */
643 return -1;
644 }
645
5c79b1f8 646 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
43bbb6cc
TI		 647 "switching to single_cmd mode: last cmd=0x%08x\n",
648 chip->last_cmd);
5c79b1f8
TI		 649 chip->rirb.rp = azx_readb(chip, RIRBWP);
650 chip->rirb.cmds = 0;
651 /* switch to single_cmd mode */
652 chip->single_cmd = 1;
653 azx_free_cmd_io(chip);
654 return -1;
1da177e4
LT		 655}
656
1da177e4
LT		 657/*
658 * Use the single immediate command instead of CORB/RIRB for simplicity
659 *
660 * Note: according to Intel, this is not preferred use. The command was
661 * intended for the BIOS only, and may get confused with unsolicited
662 * responses. So, we shouldn't use it for normal operation from the
663 * driver.
664 * I left the codes, however, for debugging/testing purposes.
665 */
666
1da177e4 667/* send a command */
33fa35ed 668static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 669{
33fa35ed 670 struct azx *chip = bus->private_data;
1da177e4
LT		 671 int timeout = 50;
672
1da177e4
LT		 673 while (timeout--) {
674 /* check ICB busy bit */
d01ce99f 675 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 676 /* Clear IRV valid bit */
d01ce99f
TI		 677 azx_writew(chip, IRS, azx_readw(chip, IRS) |
678 ICH6_IRS_VALID);
1da177e4 679 azx_writel(chip, IC, val);
d01ce99f
TI		 680 azx_writew(chip, IRS, azx_readw(chip, IRS) |
681 ICH6_IRS_BUSY);
1da177e4
LT		 682 return 0;
683 }
684 udelay(1);
685 }
1cfd52bc
MB		 686 if (printk_ratelimit())
687 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
688 azx_readw(chip, IRS), val);
1da177e4
LT		 689 return -EIO;
690}
691
692/* receive a response */
33fa35ed 693static unsigned int azx_single_get_response(struct hda_bus *bus)
1da177e4 694{
33fa35ed 695 struct azx *chip = bus->private_data;
1da177e4
LT		 696 int timeout = 50;
697
698 while (timeout--) {
699 /* check IRV busy bit */
700 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
701 return azx_readl(chip, IR);
702 udelay(1);
703 }
1cfd52bc
MB		 704 if (printk_ratelimit())
705 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
706 azx_readw(chip, IRS));
1da177e4
LT		 707 return (unsigned int)-1;
708}
709
111d3af5
TI		 710/*
711 * The below are the main callbacks from hda_codec.
712 *
713 * They are just the skeleton to call sub-callbacks according to the
714 * current setting of chip->single_cmd.
715 */
716
717/* send a command */
33fa35ed 718static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 719{
33fa35ed 720 struct azx *chip = bus->private_data;
43bbb6cc 721
33fa35ed 722 chip->last_cmd = val;
111d3af5 723 if (chip->single_cmd)
33fa35ed 724 return azx_single_send_cmd(bus, val);
111d3af5 725 else
33fa35ed 726 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 727}
728
729/* get a response */
33fa35ed 730static unsigned int azx_get_response(struct hda_bus *bus)
111d3af5 731{
33fa35ed 732 struct azx *chip = bus->private_data;
111d3af5 733 if (chip->single_cmd)
33fa35ed 734 return azx_single_get_response(bus);
111d3af5 735 else
33fa35ed 736 return azx_rirb_get_response(bus);
111d3af5
TI		 737}
738
cb53c626 739#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 740static void azx_power_notify(struct hda_bus *bus);
cb53c626 741#endif
111d3af5 742
1da177e4 743/* reset codec link */
a98f90fd 744static int azx_reset(struct azx *chip)
1da177e4
LT		 745{
746 int count;
747
e8a7f136
DT		 748 /* clear STATESTS */
749 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
750
1da177e4
LT		 751 /* reset controller */
752 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
753
754 count = 50;
755 while (azx_readb(chip, GCTL) && --count)
756 msleep(1);
757
758 /* delay for >= 100us for codec PLL to settle per spec
759 * Rev 0.9 section 5.5.1
760 */
761 msleep(1);
762
763 /* Bring controller out of reset */
764 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
765
766 count = 50;
927fc866 767 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 768 msleep(1);
769
927fc866 770 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 771 msleep(1);
772
773 /* check to see if controller is ready */
927fc866 774 if (!azx_readb(chip, GCTL)) {
1da177e4
LT		 775 snd_printd("azx_reset: controller not ready!\n");
776 return -EBUSY;
777 }
778
41e2fce4
M		 779 /* Accept unsolicited responses */
780 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
781
1da177e4 782 /* detect codecs */
927fc866 783 if (!chip->codec_mask) {
1da177e4
LT		 784 chip->codec_mask = azx_readw(chip, STATESTS);
785 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
786 }
787
788 return 0;
789}
790
791
792/*
793 * Lowlevel interface
794 */
795
796/* enable interrupts */
a98f90fd 797static void azx_int_enable(struct azx *chip)
1da177e4
LT		 798{
799 /* enable controller CIE and GIE */
800 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
801 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
802}
803
804/* disable interrupts */
a98f90fd 805static void azx_int_disable(struct azx *chip)
1da177e4
LT		 806{
807 int i;
808
809 /* disable interrupts in stream descriptor */
07e4ca50 810 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 811 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 812 azx_sd_writeb(azx_dev, SD_CTL,
813 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
814 }
815
816 /* disable SIE for all streams */
817 azx_writeb(chip, INTCTL, 0);
818
819 /* disable controller CIE and GIE */
820 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
821 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
822}
823
824/* clear interrupts */
a98f90fd 825static void azx_int_clear(struct azx *chip)
1da177e4
LT		 826{
827 int i;
828
829 /* clear stream status */
07e4ca50 830 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 831 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 832 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
833 }
834
835 /* clear STATESTS */
836 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
837
838 /* clear rirb status */
839 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
840
841 /* clear int status */
842 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
843}
844
845/* start a stream */
a98f90fd 846static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 847{
0e153474
JC		 848 /*
849 * Before stream start, initialize parameter
850 */
851 azx_dev->insufficient = 1;
852
1da177e4
LT		 853 /* enable SIE */
854 azx_writeb(chip, INTCTL,
855 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
856 /* set DMA start and interrupt mask */
857 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
858 SD_CTL_DMA_START | SD_INT_MASK);
859}
860
861/* stop a stream */
a98f90fd 862static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 863{
864 /* stop DMA */
865 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
866 ~(SD_CTL_DMA_START | SD_INT_MASK));
867 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
868 /* disable SIE */
869 azx_writeb(chip, INTCTL,
870 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
871}
872
873
874/*
cb53c626 875 * reset and start the controller registers
1da177e4 876 */
a98f90fd 877static void azx_init_chip(struct azx *chip)
1da177e4 878{
cb53c626
TI		 879 if (chip->initialized)
880 return;
1da177e4
LT		 881
882 /* reset controller */
883 azx_reset(chip);
884
885 /* initialize interrupts */
886 azx_int_clear(chip);
887 azx_int_enable(chip);
888
889 /* initialize the codec command I/O */
927fc866 890 if (!chip->single_cmd)
27346166 891 azx_init_cmd_io(chip);
1da177e4 892
0be3b5d3
TI		 893 /* program the position buffer */
894 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 895 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 896
cb53c626
TI		 897 chip->initialized = 1;
898}
899
900/*
901 * initialize the PCI registers
902 */
903/* update bits in a PCI register byte */
904static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
905 unsigned char mask, unsigned char val)
906{
907 unsigned char data;
908
909 pci_read_config_byte(pci, reg, &data);
910 data &= ~mask;
911 data |= (val & mask);
912 pci_write_config_byte(pci, reg, data);
913}
914
915static void azx_init_pci(struct azx *chip)
916{
90a5ad52
TI		 917 unsigned short snoop;
918
cb53c626
TI		 919 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
920 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
921 * Ensuring these bits are 0 clears playback static on some HD Audio
922 * codecs
923 */
924 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
925
da3fca21
V		 926 switch (chip->driver_type) {
927 case AZX_DRIVER_ATI:
928 /* For ATI SB450 azalia HD audio, we need to enable snoop */
cb53c626
TI		 929 update_pci_byte(chip->pci,
930 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
931 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
da3fca21
V		 932 break;
933 case AZX_DRIVER_NVIDIA:
934 /* For NVIDIA HDA, enable snoop */
cb53c626
TI		 935 update_pci_byte(chip->pci,
936 NVIDIA_HDA_TRANSREG_ADDR,
937 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 938 update_pci_byte(chip->pci,
939 NVIDIA_HDA_ISTRM_COH,
940 0x01, NVIDIA_HDA_ENABLE_COHBIT);
941 update_pci_byte(chip->pci,
942 NVIDIA_HDA_OSTRM_COH,
943 0x01, NVIDIA_HDA_ENABLE_COHBIT);
da3fca21 944 break;
90a5ad52
TI		 945 case AZX_DRIVER_SCH:
946 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
947 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
948 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
949 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
950 pci_read_config_word(chip->pci,
951 INTEL_SCH_HDA_DEVC, &snoop);
952 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
953 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
954 ? "Failed" : "OK");
955 }
956 break;
957
da3fca21 958 }
1da177e4
LT		 959}
960
961
9ad593f6
TI		 962static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
963
1da177e4
LT		 964/*
965 * interrupt handler
966 */
7d12e780 967static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 968{
a98f90fd
TI		 969 struct azx *chip = dev_id;
970 struct azx_dev *azx_dev;
1da177e4
LT		 971 u32 status;
972 int i;
973
974 spin_lock(&chip->reg_lock);
975
976 status = azx_readl(chip, INTSTS);
977 if (status == 0) {
978 spin_unlock(&chip->reg_lock);
979 return IRQ_NONE;
980 }
981
07e4ca50 982 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 983 azx_dev = &chip->azx_dev[i];
984 if (status & azx_dev->sd_int_sta_mask) {
985 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ad593f6
TI		 986 if (!azx_dev->substream || !azx_dev->running)
987 continue;
675f25d4
TI		 988 /* ignore the first dummy IRQ (due to pos_adj) */
989 if (azx_dev->irq_ignore) {
990 azx_dev->irq_ignore = 0;
991 continue;
992 }
9ad593f6
TI		 993 /* check whether this IRQ is really acceptable */
994 if (azx_position_ok(chip, azx_dev)) {
995 azx_dev->irq_pending = 0;
1da177e4
LT		 996 spin_unlock(&chip->reg_lock);
997 snd_pcm_period_elapsed(azx_dev->substream);
998 spin_lock(&chip->reg_lock);
6acaed38 999 } else if (chip->bus && chip->bus->workq) {
9ad593f6
TI		 1000 /* bogus IRQ, process it later */
1001 azx_dev->irq_pending = 1;
6acaed38
TI		 1002 queue_work(chip->bus->workq,
1003 &chip->irq_pending_work);
1da177e4
LT		 1004 }
1005 }
1006 }
1007
1008 /* clear rirb int */
1009 status = azx_readb(chip, RIRBSTS);
1010 if (status & RIRB_INT_MASK) {
d01ce99f 1011 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
1da177e4
LT		 1012 azx_update_rirb(chip);
1013 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1014 }
1015
1016#if 0
1017 /* clear state status int */
1018 if (azx_readb(chip, STATESTS) & 0x04)
1019 azx_writeb(chip, STATESTS, 0x04);
1020#endif
1021 spin_unlock(&chip->reg_lock);
1022
1023 return IRQ_HANDLED;
1024}
1025
1026
675f25d4
TI		 1027/*
1028 * set up a BDL entry
1029 */
1030static int setup_bdle(struct snd_pcm_substream *substream,
1031 struct azx_dev *azx_dev, u32 **bdlp,
1032 int ofs, int size, int with_ioc)
1033{
675f25d4
TI		 1034 u32 *bdl = *bdlp;
1035
1036 while (size > 0) {
1037 dma_addr_t addr;
1038 int chunk;
1039
1040 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1041 return -EINVAL;
1042
77a23f26 1043 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1044 /* program the address field of the BDL entry */
1045 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1046 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1047 /* program the size field of the BDL entry */
fc4abee8 1048 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
675f25d4
TI		 1049 bdl[2] = cpu_to_le32(chunk);
1050 /* program the IOC to enable interrupt
1051 * only when the whole fragment is processed
1052 */
1053 size -= chunk;
1054 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1055 bdl += 4;
1056 azx_dev->frags++;
1057 ofs += chunk;
1058 }
1059 *bdlp = bdl;
1060 return ofs;
1061}
1062
1da177e4
LT		 1063/*
1064 * set up BDL entries
1065 */
555e219f
TI		 1066static int azx_setup_periods(struct azx *chip,
1067 struct snd_pcm_substream *substream,
4ce107b9 1068 struct azx_dev *azx_dev)
1da177e4 1069{
4ce107b9
TI		 1070 u32 *bdl;
1071 int i, ofs, periods, period_bytes;
555e219f 1072 int pos_adj;
1da177e4
LT		 1073
1074 /* reset BDL address */
1075 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1076 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1077
4ce107b9 1078 period_bytes = snd_pcm_lib_period_bytes(substream);
9ad593f6 1079 azx_dev->period_bytes = period_bytes;
4ce107b9
TI		 1080 periods = azx_dev->bufsize / period_bytes;
1081
1da177e4 1082 /* program the initial BDL entries */
4ce107b9
TI		 1083 bdl = (u32 *)azx_dev->bdl.area;
1084 ofs = 0;
1085 azx_dev->frags = 0;
675f25d4 1086 azx_dev->irq_ignore = 0;
555e219f
TI		 1087 pos_adj = bdl_pos_adj[chip->dev_index];
1088 if (pos_adj > 0) {
675f25d4 1089 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1090 int pos_align = pos_adj;
555e219f 1091 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1092 if (!pos_adj)
e785d3d8
TI		 1093 pos_adj = pos_align;
1094 else
1095 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1096 pos_align;
675f25d4
TI		 1097 pos_adj = frames_to_bytes(runtime, pos_adj);
1098 if (pos_adj >= period_bytes) {
1099 snd_printk(KERN_WARNING "Too big adjustment %d\n",
555e219f 1100 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1101 pos_adj = 0;
1102 } else {
1103 ofs = setup_bdle(substream, azx_dev,
1104 &bdl, ofs, pos_adj, 1);
1105 if (ofs < 0)
1106 goto error;
1107 azx_dev->irq_ignore = 1;
4ce107b9 1108 }
555e219f
TI		 1109 } else
1110 pos_adj = 0;
675f25d4
TI		 1111 for (i = 0; i < periods; i++) {
1112 if (i == periods - 1 && pos_adj)
1113 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1114 period_bytes - pos_adj, 0);
1115 else
1116 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1117 period_bytes, 1);
1118 if (ofs < 0)
1119 goto error;
1da177e4 1120 }
4ce107b9 1121 return 0;
675f25d4
TI		 1122
1123 error:
1124 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1125 azx_dev->bufsize, period_bytes);
1126 /* reset */
1127 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1128 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1129 return -EINVAL;
1da177e4
LT		 1130}
1131
1132/*
1133 * set up the SD for streaming
1134 */
a98f90fd 1135static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1136{
1137 unsigned char val;
1138 int timeout;
1139
1140 /* make sure the run bit is zero for SD */
d01ce99f
TI		 1141 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1142 ~SD_CTL_DMA_START);
1da177e4 1143 /* reset stream */
d01ce99f
TI		 1144 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1145 SD_CTL_STREAM_RESET);
1da177e4
LT		 1146 udelay(3);
1147 timeout = 300;
1148 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1149 --timeout)
1150 ;
1151 val &= ~SD_CTL_STREAM_RESET;
1152 azx_sd_writeb(azx_dev, SD_CTL, val);
1153 udelay(3);
1154
1155 timeout = 300;
1156 /* waiting for hardware to report that the stream is out of reset */
1157 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1158 --timeout)
1159 ;
1160
1161 /* program the stream_tag */
1162 azx_sd_writel(azx_dev, SD_CTL,
d01ce99f 1163 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1da177e4
LT		 1164 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1165
1166 /* program the length of samples in cyclic buffer */
1167 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1168
1169 /* program the stream format */
1170 /* this value needs to be the same as the one programmed */
1171 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1172
1173 /* program the stream LVI (last valid index) of the BDL */
1174 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1175
1176 /* program the BDL address */
1177 /* lower BDL address */
4ce107b9 1178 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1179 /* upper BDL address */
766979e0 1180 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1181
0be3b5d3 1182 /* enable the position buffer */
ee9d6b9a 1183 if (chip->position_fix == POS_FIX_POSBUF ||
0e153474
JC		 1184 chip->position_fix == POS_FIX_AUTO ||
1185 chip->via_dmapos_patch) {
ee9d6b9a
TI		 1186 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1187 azx_writel(chip, DPLBASE,
1188 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1189 }
c74db86b 1190
1da177e4 1191 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1192 azx_sd_writel(azx_dev, SD_CTL,
1193 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1194
1195 return 0;
1196}
1197
6ce4a3bc
TI		 1198/*
1199 * Probe the given codec address
1200 */
1201static int probe_codec(struct azx *chip, int addr)
1202{
1203 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1204 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1205 unsigned int res;
1206
1207 chip->probing = 1;
1208 azx_send_cmd(chip->bus, cmd);
1209 res = azx_get_response(chip->bus);
1210 chip->probing = 0;
1211 if (res == -1)
1212 return -EIO;
1213 snd_printdd("hda_intel: codec #%d probed OK\n", addr);
1214 return 0;
1215}
1216
33fa35ed
TI		 1217static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1218 struct hda_pcm *cpcm);
6ce4a3bc 1219static void azx_stop_chip(struct azx *chip);
1da177e4
LT		 1220
1221/*
1222 * Codec initialization
1223 */
1224
2f5983f2
TI		 1225/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1226static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
f269002e 1227 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1228};
1229
5aba4f8e 1230static int __devinit azx_codec_create(struct azx *chip, const char *model,
d4d9cd03
TI		 1231 unsigned int codec_probe_mask,
1232 int no_init)
1da177e4
LT		 1233{
1234 struct hda_bus_template bus_temp;
34c25350
TI		 1235 int c, codecs, err;
1236 int max_slots;
1da177e4
LT		 1237
1238 memset(&bus_temp, 0, sizeof(bus_temp));
1239 bus_temp.private_data = chip;
1240 bus_temp.modelname = model;
1241 bus_temp.pci = chip->pci;
111d3af5
TI		 1242 bus_temp.ops.command = azx_send_cmd;
1243 bus_temp.ops.get_response = azx_get_response;
176d5335 1244 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
cb53c626 1245#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1246 bus_temp.power_save = &power_save;
cb53c626
TI		 1247 bus_temp.ops.pm_notify = azx_power_notify;
1248#endif
1da177e4 1249
d01ce99f
TI		 1250 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1251 if (err < 0)
1da177e4
LT		 1252 return err;
1253
dc9c8e21
WN		 1254 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1255 chip->bus->needs_damn_long_delay = 1;
1256
34c25350 1257 codecs = 0;
2f5983f2
TI		 1258 max_slots = azx_max_codecs[chip->driver_type];
1259 if (!max_slots)
1260 max_slots = AZX_MAX_CODECS;
6ce4a3bc
TI		 1261
1262 /* First try to probe all given codec slots */
1263 for (c = 0; c < max_slots; c++) {
1264 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1265 if (probe_codec(chip, c) < 0) {
1266 /* Some BIOSen give you wrong codec addresses
1267 * that don't exist
1268 */
1269 snd_printk(KERN_WARNING
1270 "hda_intel: Codec #%d probe error; "
1271 "disabling it...\n", c);
1272 chip->codec_mask &= ~(1 << c);
1273 /* More badly, accessing to a non-existing
1274 * codec often screws up the controller chip,
1275 * and distrubs the further communications.
1276 * Thus if an error occurs during probing,
1277 * better to reset the controller chip to
1278 * get back to the sanity state.
1279 */
1280 azx_stop_chip(chip);
1281 azx_init_chip(chip);
1282 }
1283 }
1284 }
1285
1286 /* Then create codec instances */
34c25350 1287 for (c = 0; c < max_slots; c++) {
5aba4f8e 1288 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
bccad14e 1289 struct hda_codec *codec;
d4d9cd03 1290 err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1da177e4
LT		 1291 if (err < 0)
1292 continue;
1293 codecs++;
19a982b6
TI		 1294 }
1295 }
1296 if (!codecs) {
1da177e4
LT		 1297 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1298 return -ENXIO;
1299 }
1300
1301 return 0;
1302}
1303
1304
1305/*
1306 * PCM support
1307 */
1308
1309/* assign a stream for the PCM */
a98f90fd 1310static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1da177e4 1311{
07e4ca50
TI		 1312 int dev, i, nums;
1313 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1314 dev = chip->playback_index_offset;
1315 nums = chip->playback_streams;
1316 } else {
1317 dev = chip->capture_index_offset;
1318 nums = chip->capture_streams;
1319 }
1320 for (i = 0; i < nums; i++, dev++)
d01ce99f 1321 if (!chip->azx_dev[dev].opened) {
1da177e4
LT		 1322 chip->azx_dev[dev].opened = 1;
1323 return &chip->azx_dev[dev];
1324 }
1325 return NULL;
1326}
1327
1328/* release the assigned stream */
a98f90fd 1329static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1330{
1331 azx_dev->opened = 0;
1332}
1333
a98f90fd 1334static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1335 .info = (SNDRV_PCM_INFO_MMAP |
1336 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1337 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1338 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1339 /* No full-resume yet implemented */
1340 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52
TI		 1341 SNDRV_PCM_INFO_PAUSE |
1342 SNDRV_PCM_INFO_SYNC_START),
1da177e4
LT		 1343 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1344 .rates = SNDRV_PCM_RATE_48000,
1345 .rate_min = 48000,
1346 .rate_max = 48000,
1347 .channels_min = 2,
1348 .channels_max = 2,
1349 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1350 .period_bytes_min = 128,
1351 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1352 .periods_min = 2,
1353 .periods_max = AZX_MAX_FRAG,
1354 .fifo_size = 0,
1355};
1356
1357struct azx_pcm {
a98f90fd 1358 struct azx *chip;
1da177e4
LT		 1359 struct hda_codec *codec;
1360 struct hda_pcm_stream *hinfo[2];
1361};
1362
a98f90fd 1363static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1364{
1365 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1366 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1367 struct azx *chip = apcm->chip;
1368 struct azx_dev *azx_dev;
1369 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1370 unsigned long flags;
1371 int err;
1372
62932df8 1373 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1374 azx_dev = azx_assign_device(chip, substream->stream);
1375 if (azx_dev == NULL) {
62932df8 1376 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1377 return -EBUSY;
1378 }
1379 runtime->hw = azx_pcm_hw;
1380 runtime->hw.channels_min = hinfo->channels_min;
1381 runtime->hw.channels_max = hinfo->channels_max;
1382 runtime->hw.formats = hinfo->formats;
1383 runtime->hw.rates = hinfo->rates;
1384 snd_pcm_limit_hw_rates(runtime);
1385 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5f1545bc
JD		 1386 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1387 128);
1388 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1389 128);
cb53c626 1390 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1391 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1392 if (err < 0) {
1da177e4 1393 azx_release_device(azx_dev);
cb53c626 1394 snd_hda_power_down(apcm->codec);
62932df8 1395 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1396 return err;
1397 }
1398 spin_lock_irqsave(&chip->reg_lock, flags);
1399 azx_dev->substream = substream;
1400 azx_dev->running = 0;
1401 spin_unlock_irqrestore(&chip->reg_lock, flags);
1402
1403 runtime->private_data = azx_dev;
850f0e52 1404 snd_pcm_set_sync(substream);
62932df8 1405 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1406 return 0;
1407}
1408
a98f90fd 1409static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1410{
1411 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1412 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1413 struct azx *chip = apcm->chip;
1414 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1415 unsigned long flags;
1416
62932df8 1417 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1418 spin_lock_irqsave(&chip->reg_lock, flags);
1419 azx_dev->substream = NULL;
1420 azx_dev->running = 0;
1421 spin_unlock_irqrestore(&chip->reg_lock, flags);
1422 azx_release_device(azx_dev);
1423 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1424 snd_hda_power_down(apcm->codec);
62932df8 1425 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1426 return 0;
1427}
1428
d01ce99f
TI		 1429static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1430 struct snd_pcm_hw_params *hw_params)
1da177e4 1431{
d01ce99f
TI		 1432 return snd_pcm_lib_malloc_pages(substream,
1433 params_buffer_bytes(hw_params));
1da177e4
LT		 1434}
1435
a98f90fd 1436static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1437{
1438 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1439 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1440 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1441
1442 /* reset BDL address */
1443 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1444 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1445 azx_sd_writel(azx_dev, SD_CTL, 0);
1446
1447 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1448
1449 return snd_pcm_lib_free_pages(substream);
1450}
1451
a98f90fd 1452static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1453{
1454 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1455 struct azx *chip = apcm->chip;
1456 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1457 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1458 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1459
1460 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1da177e4
LT		 1461 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1462 runtime->channels,
1463 runtime->format,
1464 hinfo->maxbps);
d01ce99f
TI		 1465 if (!azx_dev->format_val) {
1466 snd_printk(KERN_ERR SFX
1467 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1468 runtime->rate, runtime->channels, runtime->format);
1469 return -EINVAL;
1470 }
1471
21c7b081
TI		 1472 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1473 azx_dev->bufsize, azx_dev->format_val);
555e219f 1474 if (azx_setup_periods(chip, substream, azx_dev) < 0)
4ce107b9 1475 return -EINVAL;
1da177e4
LT		 1476 azx_setup_controller(chip, azx_dev);
1477 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1478 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1479 else
1480 azx_dev->fifo_size = 0;
1481
1482 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1483 azx_dev->format_val, substream);
1484}
1485
a98f90fd 1486static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1487{
1488 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1489 struct azx *chip = apcm->chip;
850f0e52
TI		 1490 struct azx_dev *azx_dev;
1491 struct snd_pcm_substream *s;
1492 int start, nsync = 0, sbits = 0;
1493 int nwait, timeout;
1da177e4 1494
1da177e4
LT		 1495 switch (cmd) {
1496 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1497 case SNDRV_PCM_TRIGGER_RESUME:
1498 case SNDRV_PCM_TRIGGER_START:
850f0e52 1499 start = 1;
1da177e4
LT		 1500 break;
1501 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1502 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1503 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1504 start = 0;
1da177e4
LT		 1505 break;
1506 default:
850f0e52
TI		 1507 return -EINVAL;
1508 }
1509
1510 snd_pcm_group_for_each_entry(s, substream) {
1511 if (s->pcm->card != substream->pcm->card)
1512 continue;
1513 azx_dev = get_azx_dev(s);
1514 sbits |= 1 << azx_dev->index;
1515 nsync++;
1516 snd_pcm_trigger_done(s, substream);
1517 }
1518
1519 spin_lock(&chip->reg_lock);
1520 if (nsync > 1) {
1521 /* first, set SYNC bits of corresponding streams */
1522 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1523 }
1524 snd_pcm_group_for_each_entry(s, substream) {
1525 if (s->pcm->card != substream->pcm->card)
1526 continue;
1527 azx_dev = get_azx_dev(s);
1528 if (start)
1529 azx_stream_start(chip, azx_dev);
1530 else
1531 azx_stream_stop(chip, azx_dev);
1532 azx_dev->running = start;
1da177e4
LT		 1533 }
1534 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1535 if (start) {
1536 if (nsync == 1)
1537 return 0;
1538 /* wait until all FIFOs get ready */
1539 for (timeout = 5000; timeout; timeout--) {
1540 nwait = 0;
1541 snd_pcm_group_for_each_entry(s, substream) {
1542 if (s->pcm->card != substream->pcm->card)
1543 continue;
1544 azx_dev = get_azx_dev(s);
1545 if (!(azx_sd_readb(azx_dev, SD_STS) &
1546 SD_STS_FIFO_READY))
1547 nwait++;
1548 }
1549 if (!nwait)
1550 break;
1551 cpu_relax();
1552 }
1553 } else {
1554 /* wait until all RUN bits are cleared */
1555 for (timeout = 5000; timeout; timeout--) {
1556 nwait = 0;
1557 snd_pcm_group_for_each_entry(s, substream) {
1558 if (s->pcm->card != substream->pcm->card)
1559 continue;
1560 azx_dev = get_azx_dev(s);
1561 if (azx_sd_readb(azx_dev, SD_CTL) &
1562 SD_CTL_DMA_START)
1563 nwait++;
1564 }
1565 if (!nwait)
1566 break;
1567 cpu_relax();
1568 }
1da177e4 1569 }
850f0e52
TI		 1570 if (nsync > 1) {
1571 spin_lock(&chip->reg_lock);
1572 /* reset SYNC bits */
1573 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1574 spin_unlock(&chip->reg_lock);
1575 }
1576 return 0;
1da177e4
LT		 1577}
1578
0e153474
JC		 1579/* get the current DMA position with correction on VIA chips */
1580static unsigned int azx_via_get_position(struct azx *chip,
1581 struct azx_dev *azx_dev)
1582{
1583 unsigned int link_pos, mini_pos, bound_pos;
1584 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1585 unsigned int fifo_size;
1586
1587 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1588 if (azx_dev->index >= 4) {
1589 /* Playback, no problem using link position */
1590 return link_pos;
1591 }
1592
1593 /* Capture */
1594 /* For new chipset,
1595 * use mod to get the DMA position just like old chipset
1596 */
1597 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1598 mod_dma_pos %= azx_dev->period_bytes;
1599
1600 /* azx_dev->fifo_size can't get FIFO size of in stream.
1601 * Get from base address + offset.
1602 */
1603 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1604
1605 if (azx_dev->insufficient) {
1606 /* Link position never gather than FIFO size */
1607 if (link_pos <= fifo_size)
1608 return 0;
1609
1610 azx_dev->insufficient = 0;
1611 }
1612
1613 if (link_pos <= fifo_size)
1614 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1615 else
1616 mini_pos = link_pos - fifo_size;
1617
1618 /* Find nearest previous boudary */
1619 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1620 mod_link_pos = link_pos % azx_dev->period_bytes;
1621 if (mod_link_pos >= fifo_size)
1622 bound_pos = link_pos - mod_link_pos;
1623 else if (mod_dma_pos >= mod_mini_pos)
1624 bound_pos = mini_pos - mod_mini_pos;
1625 else {
1626 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1627 if (bound_pos >= azx_dev->bufsize)
1628 bound_pos = 0;
1629 }
1630
1631 /* Calculate real DMA position we want */
1632 return bound_pos + mod_dma_pos;
1633}
1634
9ad593f6
TI		 1635static unsigned int azx_get_position(struct azx *chip,
1636 struct azx_dev *azx_dev)
1da177e4 1637{
1da177e4
LT		 1638 unsigned int pos;
1639
0e153474
JC		 1640 if (chip->via_dmapos_patch)
1641 pos = azx_via_get_position(chip, azx_dev);
1642 else if (chip->position_fix == POS_FIX_POSBUF ||
1643 chip->position_fix == POS_FIX_AUTO) {
c74db86b 1644 /* use the position buffer */
929861c6 1645 pos = le32_to_cpu(*azx_dev->posbuf);
c74db86b
TI		 1646 } else {
1647 /* read LPIB */
1648 pos = azx_sd_readl(azx_dev, SD_LPIB);
c74db86b 1649 }
1da177e4
LT		 1650 if (pos >= azx_dev->bufsize)
1651 pos = 0;
9ad593f6
TI		 1652 return pos;
1653}
1654
1655static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1656{
1657 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1658 struct azx *chip = apcm->chip;
1659 struct azx_dev *azx_dev = get_azx_dev(substream);
1660 return bytes_to_frames(substream->runtime,
1661 azx_get_position(chip, azx_dev));
1662}
1663
1664/*
1665 * Check whether the current DMA position is acceptable for updating
1666 * periods. Returns non-zero if it's OK.
1667 *
1668 * Many HD-audio controllers appear pretty inaccurate about
1669 * the update-IRQ timing. The IRQ is issued before actually the
1670 * data is processed. So, we need to process it afterwords in a
1671 * workqueue.
1672 */
1673static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1674{
1675 unsigned int pos;
1676
1677 pos = azx_get_position(chip, azx_dev);
1678 if (chip->position_fix == POS_FIX_AUTO) {
1679 if (!pos) {
1680 printk(KERN_WARNING
1681 "hda-intel: Invalid position buffer, "
1682 "using LPIB read method instead.\n");
d2e1c973 1683 chip->position_fix = POS_FIX_LPIB;
9ad593f6
TI		 1684 pos = azx_get_position(chip, azx_dev);
1685 } else
1686 chip->position_fix = POS_FIX_POSBUF;
1687 }
1688
a62741cf
TI		 1689 if (!bdl_pos_adj[chip->dev_index])
1690 return 1; /* no delayed ack */
9ad593f6
TI		 1691 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1692 return 0; /* NG - it's below the period boundary */
1693 return 1; /* OK, it's fine */
1694}
1695
1696/*
1697 * The work for pending PCM period updates.
1698 */
1699static void azx_irq_pending_work(struct work_struct *work)
1700{
1701 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1702 int i, pending;
1703
a6a950a8
TI		 1704 if (!chip->irq_pending_warned) {
1705 printk(KERN_WARNING
1706 "hda-intel: IRQ timing workaround is activated "
1707 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1708 chip->card->number);
1709 chip->irq_pending_warned = 1;
1710 }
1711
9ad593f6
TI		 1712 for (;;) {
1713 pending = 0;
1714 spin_lock_irq(&chip->reg_lock);
1715 for (i = 0; i < chip->num_streams; i++) {
1716 struct azx_dev *azx_dev = &chip->azx_dev[i];
1717 if (!azx_dev->irq_pending ||
1718 !azx_dev->substream ||
1719 !azx_dev->running)
1720 continue;
1721 if (azx_position_ok(chip, azx_dev)) {
1722 azx_dev->irq_pending = 0;
1723 spin_unlock(&chip->reg_lock);
1724 snd_pcm_period_elapsed(azx_dev->substream);
1725 spin_lock(&chip->reg_lock);
1726 } else
1727 pending++;
1728 }
1729 spin_unlock_irq(&chip->reg_lock);
1730 if (!pending)
1731 return;
1732 cond_resched();
1733 }
1734}
1735
1736/* clear irq_pending flags and assure no on-going workq */
1737static void azx_clear_irq_pending(struct azx *chip)
1738{
1739 int i;
1740
1741 spin_lock_irq(&chip->reg_lock);
1742 for (i = 0; i < chip->num_streams; i++)
1743 chip->azx_dev[i].irq_pending = 0;
1744 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1745}
1746
a98f90fd 1747static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 1748 .open = azx_pcm_open,
1749 .close = azx_pcm_close,
1750 .ioctl = snd_pcm_lib_ioctl,
1751 .hw_params = azx_pcm_hw_params,
1752 .hw_free = azx_pcm_hw_free,
1753 .prepare = azx_pcm_prepare,
1754 .trigger = azx_pcm_trigger,
1755 .pointer = azx_pcm_pointer,
4ce107b9 1756 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 1757};
1758
a98f90fd 1759static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 1760{
176d5335
TI		 1761 struct azx_pcm *apcm = pcm->private_data;
1762 if (apcm) {
1763 apcm->chip->pcm[pcm->device] = NULL;
1764 kfree(apcm);
1765 }
1da177e4
LT		 1766}
1767
176d5335 1768static int
33fa35ed
TI		 1769azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1770 struct hda_pcm *cpcm)
1da177e4 1771{
33fa35ed 1772 struct azx *chip = bus->private_data;
a98f90fd 1773 struct snd_pcm *pcm;
1da177e4 1774 struct azx_pcm *apcm;
176d5335
TI		 1775 int pcm_dev = cpcm->device;
1776 int s, err;
1da177e4 1777
176d5335
TI		 1778 if (pcm_dev >= AZX_MAX_PCMS) {
1779 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1780 pcm_dev);
da3cec35 1781 return -EINVAL;
176d5335
TI		 1782 }
1783 if (chip->pcm[pcm_dev]) {
1784 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1785 return -EBUSY;
1786 }
1787 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1788 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1789 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 1790 &pcm);
1791 if (err < 0)
1792 return err;
1793 strcpy(pcm->name, cpcm->name);
176d5335 1794 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 1795 if (apcm == NULL)
1796 return -ENOMEM;
1797 apcm->chip = chip;
1798 apcm->codec = codec;
1da177e4
LT		 1799 pcm->private_data = apcm;
1800 pcm->private_free = azx_pcm_free;
176d5335
TI		 1801 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1802 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1803 chip->pcm[pcm_dev] = pcm;
1804 cpcm->pcm = pcm;
1805 for (s = 0; s < 2; s++) {
1806 apcm->hinfo[s] = &cpcm->stream[s];
1807 if (cpcm->stream[s].substreams)
1808 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1809 }
1810 /* buffer pre-allocation */
4ce107b9 1811 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 1812 snd_dma_pci_data(chip->pci),
fc4abee8 1813 1024 * 64, 32 * 1024 * 1024);
1da177e4
LT		 1814 return 0;
1815}
1816
1817/*
1818 * mixer creation - all stuff is implemented in hda module
1819 */
a98f90fd 1820static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 1821{
1822 return snd_hda_build_controls(chip->bus);
1823}
1824
1825
1826/*
1827 * initialize SD streams
1828 */
a98f90fd 1829static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 1830{
1831 int i;
1832
1833 /* initialize each stream (aka device)
d01ce99f
TI		 1834 * assign the starting bdl address to each stream (device)
1835 * and initialize
1da177e4 1836 */
07e4ca50 1837 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1838 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 1839 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 1840 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1841 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1842 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1843 azx_dev->sd_int_sta_mask = 1 << i;
1844 /* stream tag: must be non-zero and unique */
1845 azx_dev->index = i;
1846 azx_dev->stream_tag = i + 1;
1847 }
1848
1849 return 0;
1850}
1851
68e7fffc
TI		 1852static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1853{
437a5a46
TI		 1854 if (request_irq(chip->pci->irq, azx_interrupt,
1855 chip->msi ? 0 : IRQF_SHARED,
68e7fffc
TI		 1856 "HDA Intel", chip)) {
1857 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1858 "disabling device\n", chip->pci->irq);
1859 if (do_disconnect)
1860 snd_card_disconnect(chip->card);
1861 return -1;
1862 }
1863 chip->irq = chip->pci->irq;
69e13418 1864 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 1865 return 0;
1866}
1867
1da177e4 1868
cb53c626
TI		 1869static void azx_stop_chip(struct azx *chip)
1870{
95e99fda 1871 if (!chip->initialized)
cb53c626
TI		 1872 return;
1873
1874 /* disable interrupts */
1875 azx_int_disable(chip);
1876 azx_int_clear(chip);
1877
1878 /* disable CORB/RIRB */
1879 azx_free_cmd_io(chip);
1880
1881 /* disable position buffer */
1882 azx_writel(chip, DPLBASE, 0);
1883 azx_writel(chip, DPUBASE, 0);
1884
1885 chip->initialized = 0;
1886}
1887
1888#ifdef CONFIG_SND_HDA_POWER_SAVE
1889/* power-up/down the controller */
33fa35ed 1890static void azx_power_notify(struct hda_bus *bus)
cb53c626 1891{
33fa35ed 1892 struct azx *chip = bus->private_data;
cb53c626
TI		 1893 struct hda_codec *c;
1894 int power_on = 0;
1895
33fa35ed 1896 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 1897 if (c->power_on) {
1898 power_on = 1;
1899 break;
1900 }
1901 }
1902 if (power_on)
1903 azx_init_chip(chip);
dee1b66c 1904 else if (chip->running && power_save_controller)
cb53c626 1905 azx_stop_chip(chip);
cb53c626 1906}
5c0b9bec
TI		 1907#endif /* CONFIG_SND_HDA_POWER_SAVE */
1908
1909#ifdef CONFIG_PM
1910/*
1911 * power management
1912 */
986862bd
TI		 1913
1914static int snd_hda_codecs_inuse(struct hda_bus *bus)
1915{
1916 struct hda_codec *codec;
1917
1918 list_for_each_entry(codec, &bus->codec_list, list) {
1919 if (snd_hda_codec_needs_resume(codec))
1920 return 1;
1921 }
1922 return 0;
1923}
cb53c626 1924
421a1252 1925static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 1926{
421a1252
TI		 1927 struct snd_card *card = pci_get_drvdata(pci);
1928 struct azx *chip = card->private_data;
1da177e4
LT		 1929 int i;
1930
421a1252 1931 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 1932 azx_clear_irq_pending(chip);
7ba72ba1 1933 for (i = 0; i < AZX_MAX_PCMS; i++)
421a1252 1934 snd_pcm_suspend_all(chip->pcm[i]);
0b7a2e9c
TI		 1935 if (chip->initialized)
1936 snd_hda_suspend(chip->bus, state);
cb53c626 1937 azx_stop_chip(chip);
30b35399 1938 if (chip->irq >= 0) {
43001c95 1939 free_irq(chip->irq, chip);
30b35399
TI		 1940 chip->irq = -1;
1941 }
68e7fffc 1942 if (chip->msi)
43001c95 1943 pci_disable_msi(chip->pci);
421a1252
TI		 1944 pci_disable_device(pci);
1945 pci_save_state(pci);
30b35399 1946 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 1947 return 0;
1948}
1949
421a1252 1950static int azx_resume(struct pci_dev *pci)
1da177e4 1951{
421a1252
TI		 1952 struct snd_card *card = pci_get_drvdata(pci);
1953 struct azx *chip = card->private_data;
1da177e4 1954
d14a7e0b
TI		 1955 pci_set_power_state(pci, PCI_D0);
1956 pci_restore_state(pci);
30b35399
TI		 1957 if (pci_enable_device(pci) < 0) {
1958 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1959 "disabling device\n");
1960 snd_card_disconnect(card);
1961 return -EIO;
1962 }
1963 pci_set_master(pci);
68e7fffc
TI		 1964 if (chip->msi)
1965 if (pci_enable_msi(pci) < 0)
1966 chip->msi = 0;
1967 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1968 return -EIO;
cb53c626 1969 azx_init_pci(chip);
d804ad92
ML		 1970
1971 if (snd_hda_codecs_inuse(chip->bus))
1972 azx_init_chip(chip);
1973
1da177e4 1974 snd_hda_resume(chip->bus);
421a1252 1975 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 1976 return 0;
1977}
1978#endif /* CONFIG_PM */
1979
1980
0cbf0098
TI		 1981/*
1982 * reboot notifier for hang-up problem at power-down
1983 */
1984static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
1985{
1986 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
1987 azx_stop_chip(chip);
1988 return NOTIFY_OK;
1989}
1990
1991static void azx_notifier_register(struct azx *chip)
1992{
1993 chip->reboot_notifier.notifier_call = azx_halt;
1994 register_reboot_notifier(&chip->reboot_notifier);
1995}
1996
1997static void azx_notifier_unregister(struct azx *chip)
1998{
1999 if (chip->reboot_notifier.notifier_call)
2000 unregister_reboot_notifier(&chip->reboot_notifier);
2001}
2002
1da177e4
LT		 2003/*
2004 * destructor
2005 */
a98f90fd 2006static int azx_free(struct azx *chip)
1da177e4 2007{
4ce107b9
TI		 2008 int i;
2009
0cbf0098
TI		 2010 azx_notifier_unregister(chip);
2011
ce43fbae 2012 if (chip->initialized) {
9ad593f6 2013 azx_clear_irq_pending(chip);
07e4ca50 2014 for (i = 0; i < chip->num_streams; i++)
1da177e4 2015 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2016 azx_stop_chip(chip);
1da177e4
LT		 2017 }
2018
f000fd80 2019 if (chip->irq >= 0)
1da177e4 2020 free_irq(chip->irq, (void*)chip);
68e7fffc 2021 if (chip->msi)
30b35399 2022 pci_disable_msi(chip->pci);
f079c25a
TI		 2023 if (chip->remap_addr)
2024 iounmap(chip->remap_addr);
1da177e4 2025
4ce107b9
TI		 2026 if (chip->azx_dev) {
2027 for (i = 0; i < chip->num_streams; i++)
2028 if (chip->azx_dev[i].bdl.area)
2029 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2030 }
1da177e4
LT		 2031 if (chip->rb.area)
2032 snd_dma_free_pages(&chip->rb);
1da177e4
LT		 2033 if (chip->posbuf.area)
2034 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT		 2035 pci_release_regions(chip->pci);
2036 pci_disable_device(chip->pci);
07e4ca50 2037 kfree(chip->azx_dev);
1da177e4
LT		 2038 kfree(chip);
2039
2040 return 0;
2041}
2042
a98f90fd 2043static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2044{
2045 return azx_free(device->device_data);
2046}
2047
3372a153
TI		 2048/*
2049 * white/black-listing for position_fix
2050 */
623ec047 2051static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2052 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2053 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2054 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3372a153
TI		 2055 {}
2056};
2057
2058static int __devinit check_position_fix(struct azx *chip, int fix)
2059{
2060 const struct snd_pci_quirk *q;
2061
0e153474
JC		 2062 /* Check VIA HD Audio Controller exist */
2063 if (chip->pci->vendor == PCI_VENDOR_ID_VIA &&
2064 chip->pci->device == VIA_HDAC_DEVICE_ID) {
2065 chip->via_dmapos_patch = 1;
2066 /* Use link position directly, avoid any transfer problem. */
2067 return POS_FIX_LPIB;
2068 }
2069 chip->via_dmapos_patch = 0;
2070
3372a153
TI		 2071 if (fix == POS_FIX_AUTO) {
2072 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2073 if (q) {
669ba27a 2074 printk(KERN_INFO
3372a153
TI		 2075 "hda_intel: position_fix set to %d "
2076 "for device %04x:%04x\n",
2077 q->value, q->subvendor, q->subdevice);
2078 return q->value;
2079 }
2080 }
2081 return fix;
2082}
2083
669ba27a
TI		 2084/*
2085 * black-lists for probe_mask
2086 */
2087static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2088 /* Thinkpad often breaks the controller communication when accessing
2089 * to the non-working (or non-existing) modem codec slot.
2090 */
2091 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2092 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2093 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2094 /* broken BIOS */
2095 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2096 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2097 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
38f1df27
TI		 2098 /* conflict of ALC268 in slot#3 (digital I/O); a temporary fix */
2099 SND_PCI_QUIRK(0x1179, 0xff00, "Toshiba laptop", 0x03),
669ba27a
TI		 2100 {}
2101};
2102
5aba4f8e 2103static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2104{
2105 const struct snd_pci_quirk *q;
2106
5aba4f8e 2107 if (probe_mask[dev] == -1) {
669ba27a
TI		 2108 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2109 if (q) {
2110 printk(KERN_INFO
2111 "hda_intel: probe_mask set to 0x%x "
2112 "for device %04x:%04x\n",
2113 q->value, q->subvendor, q->subdevice);
5aba4f8e 2114 probe_mask[dev] = q->value;
669ba27a
TI		 2115 }
2116 }
2117}
2118
2119
1da177e4
LT		 2120/*
2121 * constructor
2122 */
a98f90fd 2123static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
5aba4f8e 2124 int dev, int driver_type,
a98f90fd 2125 struct azx **rchip)
1da177e4 2126{
a98f90fd 2127 struct azx *chip;
4ce107b9 2128 int i, err;
bcd72003 2129 unsigned short gcap;
a98f90fd 2130 static struct snd_device_ops ops = {
1da177e4
LT		 2131 .dev_free = azx_dev_free,
2132 };
2133
2134 *rchip = NULL;
bcd72003 2135
927fc866
PM		 2136 err = pci_enable_device(pci);
2137 if (err < 0)
1da177e4
LT		 2138 return err;
2139
e560d8d8 2140 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2141 if (!chip) {
1da177e4
LT		 2142 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2143 pci_disable_device(pci);
2144 return -ENOMEM;
2145 }
2146
2147 spin_lock_init(&chip->reg_lock);
62932df8 2148 mutex_init(&chip->open_mutex);
1da177e4
LT		 2149 chip->card = card;
2150 chip->pci = pci;
2151 chip->irq = -1;
07e4ca50 2152 chip->driver_type = driver_type;
134a11f0 2153 chip->msi = enable_msi;
555e219f 2154 chip->dev_index = dev;
9ad593f6 2155 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1da177e4 2156
5aba4f8e
TI		 2157 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2158 check_probe_mask(chip, dev);
3372a153 2159
27346166 2160 chip->single_cmd = single_cmd;
c74db86b 2161
5c0d7bc1
TI		 2162 if (bdl_pos_adj[dev] < 0) {
2163 switch (chip->driver_type) {
0c6341ac
TI		 2164 case AZX_DRIVER_ICH:
2165 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2166 break;
2167 default:
0c6341ac 2168 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2169 break;
2170 }
2171 }
2172
07e4ca50
TI		 2173#if BITS_PER_LONG != 64
2174 /* Fix up base address on ULI M5461 */
2175 if (chip->driver_type == AZX_DRIVER_ULI) {
2176 u16 tmp3;
2177 pci_read_config_word(pci, 0x40, &tmp3);
2178 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2179 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2180 }
2181#endif
2182
927fc866
PM		 2183 err = pci_request_regions(pci, "ICH HD audio");
2184 if (err < 0) {
1da177e4
LT		 2185 kfree(chip);
2186 pci_disable_device(pci);
2187 return err;
2188 }
2189
927fc866 2190 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 2191 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 2192 if (chip->remap_addr == NULL) {
2193 snd_printk(KERN_ERR SFX "ioremap error\n");
2194 err = -ENXIO;
2195 goto errout;
2196 }
2197
68e7fffc
TI		 2198 if (chip->msi)
2199 if (pci_enable_msi(pci) < 0)
2200 chip->msi = 0;
7376d013 2201
68e7fffc 2202 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT		 2203 err = -EBUSY;
2204 goto errout;
2205 }
1da177e4
LT		 2206
2207 pci_set_master(pci);
2208 synchronize_irq(chip->irq);
2209
bcd72003
TD		 2210 gcap = azx_readw(chip, GCAP);
2211 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2212
09240cf4
TI		 2213 /* ATI chips seems buggy about 64bit DMA addresses */
2214 if (chip->driver_type == AZX_DRIVER_ATI)
2215 gcap &= ~0x01;
2216
cf7aaca8
TI		 2217 /* allow 64bit DMA address if supported by H/W */
2218 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2219 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
09240cf4
TI		 2220 else {
2221 pci_set_dma_mask(pci, DMA_32BIT_MASK);
2222 pci_set_consistent_dma_mask(pci, DMA_32BIT_MASK);
2223 }
cf7aaca8 2224
8b6ed8e7
TI		 2225 /* read number of streams from GCAP register instead of using
2226 * hardcoded value
2227 */
2228 chip->capture_streams = (gcap >> 8) & 0x0f;
2229 chip->playback_streams = (gcap >> 12) & 0x0f;
2230 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 2231 /* gcap didn't give any info, switching to old method */
2232
2233 switch (chip->driver_type) {
2234 case AZX_DRIVER_ULI:
2235 chip->playback_streams = ULI_NUM_PLAYBACK;
2236 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 2237 break;
2238 case AZX_DRIVER_ATIHDMI:
2239 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2240 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 2241 break;
c4da29ca 2242 case AZX_DRIVER_GENERIC:
bcd72003
TD		 2243 default:
2244 chip->playback_streams = ICH6_NUM_PLAYBACK;
2245 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 2246 break;
2247 }
07e4ca50 2248 }
8b6ed8e7
TI		 2249 chip->capture_index_offset = 0;
2250 chip->playback_index_offset = chip->capture_streams;
07e4ca50 2251 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 2252 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2253 GFP_KERNEL);
927fc866 2254 if (!chip->azx_dev) {
07e4ca50
TI		 2255 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2256 goto errout;
2257 }
2258
4ce107b9
TI		 2259 for (i = 0; i < chip->num_streams; i++) {
2260 /* allocate memory for the BDL for each stream */
2261 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2262 snd_dma_pci_data(chip->pci),
2263 BDL_SIZE, &chip->azx_dev[i].bdl);
2264 if (err < 0) {
2265 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2266 goto errout;
2267 }
1da177e4 2268 }
0be3b5d3 2269 /* allocate memory for the position buffer */
d01ce99f
TI		 2270 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2271 snd_dma_pci_data(chip->pci),
2272 chip->num_streams * 8, &chip->posbuf);
2273 if (err < 0) {
0be3b5d3
TI		 2274 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2275 goto errout;
1da177e4 2276 }
1da177e4 2277 /* allocate CORB/RIRB */
d01ce99f
TI		 2278 if (!chip->single_cmd) {
2279 err = azx_alloc_cmd_io(chip);
2280 if (err < 0)
27346166 2281 goto errout;
d01ce99f 2282 }
1da177e4
LT		 2283
2284 /* initialize streams */
2285 azx_init_stream(chip);
2286
2287 /* initialize chip */
cb53c626 2288 azx_init_pci(chip);
1da177e4
LT		 2289 azx_init_chip(chip);
2290
2291 /* codec detection */
927fc866 2292 if (!chip->codec_mask) {
1da177e4
LT		 2293 snd_printk(KERN_ERR SFX "no codecs found!\n");
2294 err = -ENODEV;
2295 goto errout;
2296 }
2297
d01ce99f
TI		 2298 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2299 if (err <0) {
1da177e4
LT		 2300 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2301 goto errout;
2302 }
2303
07e4ca50
TI		 2304 strcpy(card->driver, "HDA-Intel");
2305 strcpy(card->shortname, driver_short_names[chip->driver_type]);
d01ce99f
TI		 2306 sprintf(card->longname, "%s at 0x%lx irq %i",
2307 card->shortname, chip->addr, chip->irq);
07e4ca50 2308
1da177e4
LT		 2309 *rchip = chip;
2310 return 0;
2311
2312 errout:
2313 azx_free(chip);
2314 return err;
2315}
2316
cb53c626
TI		 2317static void power_down_all_codecs(struct azx *chip)
2318{
2319#ifdef CONFIG_SND_HDA_POWER_SAVE
2320 /* The codecs were powered up in snd_hda_codec_new().
2321 * Now all initialization done, so turn them down if possible
2322 */
2323 struct hda_codec *codec;
2324 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2325 snd_hda_power_down(codec);
2326 }
2327#endif
2328}
2329
d01ce99f
TI		 2330static int __devinit azx_probe(struct pci_dev *pci,
2331 const struct pci_device_id *pci_id)
1da177e4 2332{
5aba4f8e 2333 static int dev;
a98f90fd
TI		 2334 struct snd_card *card;
2335 struct azx *chip;
927fc866 2336 int err;
1da177e4 2337
5aba4f8e
TI		 2338 if (dev >= SNDRV_CARDS)
2339 return -ENODEV;
2340 if (!enable[dev]) {
2341 dev++;
2342 return -ENOENT;
2343 }
2344
2345 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
927fc866 2346 if (!card) {
1da177e4
LT		 2347 snd_printk(KERN_ERR SFX "Error creating card!\n");
2348 return -ENOMEM;
2349 }
2350
5aba4f8e 2351 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2352 if (err < 0)
2353 goto out_free;
421a1252 2354 card->private_data = chip;
1da177e4 2355
1da177e4 2356 /* create codec instances */
d4d9cd03
TI		 2357 err = azx_codec_create(chip, model[dev], probe_mask[dev],
2358 probe_only[dev]);
41dda0fd
WF		 2359 if (err < 0)
2360 goto out_free;
1da177e4
LT		 2361
2362 /* create PCM streams */
176d5335 2363 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 2364 if (err < 0)
2365 goto out_free;
1da177e4
LT		 2366
2367 /* create mixer controls */
d01ce99f 2368 err = azx_mixer_create(chip);
41dda0fd
WF		 2369 if (err < 0)
2370 goto out_free;
1da177e4 2371
1da177e4
LT		 2372 snd_card_set_dev(card, &pci->dev);
2373
d01ce99f 2374 err = snd_card_register(card);
41dda0fd
WF		 2375 if (err < 0)
2376 goto out_free;
1da177e4
LT		 2377
2378 pci_set_drvdata(pci, card);
cb53c626
TI		 2379 chip->running = 1;
2380 power_down_all_codecs(chip);
0cbf0098 2381 azx_notifier_register(chip);
1da177e4 2382
e25bcdba 2383 dev++;
1da177e4 2384 return err;
41dda0fd
WF		 2385out_free:
2386 snd_card_free(card);
2387 return err;
1da177e4
LT		 2388}
2389
2390static void __devexit azx_remove(struct pci_dev *pci)
2391{
2392 snd_card_free(pci_get_drvdata(pci));
2393 pci_set_drvdata(pci, NULL);
2394}
2395
2396/* PCI IDs */
f40b6890 2397static struct pci_device_id azx_ids[] = {
87218e9c
TI		 2398 /* ICH 6..10 */
2399 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2400 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2401 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2402 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
abbc9d1b 2403 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2404 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2405 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2406 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2407 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
b29c2360
SH		 2408 /* PCH */
2409 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2410 /* SCH */
2411 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2412 /* ATI SB 450/600 */
2413 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2414 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2415 /* ATI HDMI */
2416 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2417 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2418 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
9e6dd47b 2419 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
87218e9c
TI		 2420 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2421 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2422 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2423 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2424 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2425 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2426 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2427 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2428 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2429 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2430 /* VIA VT8251/VT8237A */
2431 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2432 /* SIS966 */
2433 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2434 /* ULI M5461 */
2435 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2436 /* NVIDIA MCP */
2437 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2438 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2439 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2440 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2441 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2442 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2443 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2444 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2445 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2446 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2447 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2448 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2449 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2450 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2451 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2452 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2453 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2454 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
487145a1
PC		 2455 { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2456 { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2457 { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2458 { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
f269002e
KY		 2459 /* Teradici */
2460 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
c4da29ca
YL		 2461 /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2462 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2463 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2464 .class_mask = 0xffffff,
2465 .driver_data = AZX_DRIVER_GENERIC },
1da177e4
LT		 2466 { 0, }
2467};
2468MODULE_DEVICE_TABLE(pci, azx_ids);
2469
2470/* pci_driver definition */
2471static struct pci_driver driver = {
2472 .name = "HDA Intel",
2473 .id_table = azx_ids,
2474 .probe = azx_probe,
2475 .remove = __devexit_p(azx_remove),
421a1252
TI		 2476#ifdef CONFIG_PM
2477 .suspend = azx_suspend,
2478 .resume = azx_resume,
2479#endif
1da177e4
LT		 2480};
2481
2482static int __init alsa_card_azx_init(void)
2483{
01d25d46 2484 return pci_register_driver(&driver);
1da177e4
LT		 2485}
2486
2487static void __exit alsa_card_azx_exit(void)
2488{
2489 pci_unregister_driver(&driver);
2490}
2491
2492module_init(alsa_card_azx_init)
2493module_exit(alsa_card_azx_exit)
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