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Merge branch 'fix/hda' into topic/hda
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
362775e2 40#include <linux/kernel.h>
1da177e4 41#include <linux/module.h>
24982c5f 42#include <linux/dma-mapping.h>
1da177e4
LT		 43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
62932df8 47#include <linux/mutex.h>
0cbf0098 48#include <linux/reboot.h>
1da177e4
LT		 49#include <sound/core.h>
50#include <sound/initval.h>
51#include "hda_codec.h"
52
53
5aba4f8e
TI		 54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57static char *model[SNDRV_CARDS];
58static int position_fix[SNDRV_CARDS];
5c0d7bc1 59static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 60static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 61static int probe_only[SNDRV_CARDS];
27346166 62static int single_cmd;
134a11f0 63static int enable_msi;
1da177e4 64
5aba4f8e 65module_param_array(index, int, NULL, 0444);
1da177e4 66MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 67module_param_array(id, charp, NULL, 0444);
1da177e4 68MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 69module_param_array(enable, bool, NULL, 0444);
70MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
71module_param_array(model, charp, NULL, 0444);
1da177e4 72MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 73module_param_array(position_fix, int, NULL, 0444);
d01ce99f 74MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
d2e1c973 75 "(0 = auto, 1 = none, 2 = POSBUF).");
555e219f
TI		 76module_param_array(bdl_pos_adj, int, NULL, 0644);
77MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 78module_param_array(probe_mask, int, NULL, 0444);
606ad75f 79MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
d4d9cd03
TI		 80module_param_array(probe_only, bool, NULL, 0444);
81MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 82module_param(single_cmd, bool, 0444);
d01ce99f
TI		 83MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
84 "(for debugging only).");
5aba4f8e 85module_param(enable_msi, int, 0444);
134a11f0 86MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
606ad75f 87
dee1b66c 88#ifdef CONFIG_SND_HDA_POWER_SAVE
fee2fba3
TI		 89static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
90module_param(power_save, int, 0644);
91MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
92 "(in second, 0 = disable).");
1da177e4 93
dee1b66c
TI		 94/* reset the HD-audio controller in power save mode.
95 * this may give more power-saving, but will take longer time to
96 * wake up.
97 */
98static int power_save_controller = 1;
99module_param(power_save_controller, bool, 0644);
100MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
101#endif
102
1da177e4
LT		 103MODULE_LICENSE("GPL");
104MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
105 "{Intel, ICH6M},"
2f1b3818 106 "{Intel, ICH7},"
f5d40b30 107 "{Intel, ESB2},"
d2981393 108 "{Intel, ICH8},"
f9cc8a8b 109 "{Intel, ICH9},"
c34f5a04 110 "{Intel, ICH10},"
b29c2360 111 "{Intel, PCH},"
4979bca9 112 "{Intel, SCH},"
fc20a562 113 "{ATI, SB450},"
89be83f8 114 "{ATI, SB600},"
778b6e1b 115 "{ATI, RS600},"
5b15c95f 116 "{ATI, RS690},"
e6db1119
WL		 117 "{ATI, RS780},"
118 "{ATI, R600},"
2797f724
HRK		 119 "{ATI, RV630},"
120 "{ATI, RV610},"
27da1834
WL		 121 "{ATI, RV670},"
122 "{ATI, RV635},"
123 "{ATI, RV620},"
124 "{ATI, RV770},"
fc20a562 125 "{VIA, VT8251},"
47672310 126 "{VIA, VT8237A},"
07e4ca50
TI		 127 "{SiS, SIS966},"
128 "{ULI, M5461}}");
1da177e4
LT		 129MODULE_DESCRIPTION("Intel HDA driver");
130
4abc1cc2
TI		 131#ifdef CONFIG_SND_VERBOSE_PRINTK
132#define SFX /* nop */
133#else
1da177e4 134#define SFX "hda-intel: "
4abc1cc2 135#endif
cb53c626 136
1da177e4
LT		 137/*
138 * registers
139 */
140#define ICH6_REG_GCAP 0x00
141#define ICH6_REG_VMIN 0x02
142#define ICH6_REG_VMAJ 0x03
143#define ICH6_REG_OUTPAY 0x04
144#define ICH6_REG_INPAY 0x06
145#define ICH6_REG_GCTL 0x08
146#define ICH6_REG_WAKEEN 0x0c
147#define ICH6_REG_STATESTS 0x0e
148#define ICH6_REG_GSTS 0x10
149#define ICH6_REG_INTCTL 0x20
150#define ICH6_REG_INTSTS 0x24
151#define ICH6_REG_WALCLK 0x30
152#define ICH6_REG_SYNC 0x34
153#define ICH6_REG_CORBLBASE 0x40
154#define ICH6_REG_CORBUBASE 0x44
155#define ICH6_REG_CORBWP 0x48
156#define ICH6_REG_CORBRP 0x4A
157#define ICH6_REG_CORBCTL 0x4c
158#define ICH6_REG_CORBSTS 0x4d
159#define ICH6_REG_CORBSIZE 0x4e
160
161#define ICH6_REG_RIRBLBASE 0x50
162#define ICH6_REG_RIRBUBASE 0x54
163#define ICH6_REG_RIRBWP 0x58
164#define ICH6_REG_RINTCNT 0x5a
165#define ICH6_REG_RIRBCTL 0x5c
166#define ICH6_REG_RIRBSTS 0x5d
167#define ICH6_REG_RIRBSIZE 0x5e
168
169#define ICH6_REG_IC 0x60
170#define ICH6_REG_IR 0x64
171#define ICH6_REG_IRS 0x68
172#define ICH6_IRS_VALID (1<<1)
173#define ICH6_IRS_BUSY (1<<0)
174
175#define ICH6_REG_DPLBASE 0x70
176#define ICH6_REG_DPUBASE 0x74
177#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
178
179/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
180enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
181
182/* stream register offsets from stream base */
183#define ICH6_REG_SD_CTL 0x00
184#define ICH6_REG_SD_STS 0x03
185#define ICH6_REG_SD_LPIB 0x04
186#define ICH6_REG_SD_CBL 0x08
187#define ICH6_REG_SD_LVI 0x0c
188#define ICH6_REG_SD_FIFOW 0x0e
189#define ICH6_REG_SD_FIFOSIZE 0x10
190#define ICH6_REG_SD_FORMAT 0x12
191#define ICH6_REG_SD_BDLPL 0x18
192#define ICH6_REG_SD_BDLPU 0x1c
193
194/* PCI space */
195#define ICH6_PCIREG_TCSEL 0x44
196
197/*
198 * other constants
199 */
200
201/* max number of SDs */
07e4ca50 202/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 203#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 204#define ICH6_NUM_PLAYBACK 4
205
206/* ULI has 6 playback and 5 capture */
07e4ca50 207#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 208#define ULI_NUM_PLAYBACK 6
209
778b6e1b 210/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 211#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 212#define ATIHDMI_NUM_PLAYBACK 1
213
f269002e
KY		 214/* TERA has 4 playback and 3 capture */
215#define TERA_NUM_CAPTURE 3
216#define TERA_NUM_PLAYBACK 4
217
07e4ca50
TI		 218/* this number is statically defined for simplicity */
219#define MAX_AZX_DEV 16
220
1da177e4 221/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 222#define BDL_SIZE 4096
223#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
224#define AZX_MAX_FRAG 32
1da177e4
LT		 225/* max buffer size - no h/w limit, you can increase as you like */
226#define AZX_MAX_BUF_SIZE (1024*1024*1024)
227/* max number of PCM devics per card */
7ba72ba1 228#define AZX_MAX_PCMS 8
1da177e4
LT		 229
230/* RIRB int mask: overrun[2], response[0] */
231#define RIRB_INT_RESPONSE 0x01
232#define RIRB_INT_OVERRUN 0x04
233#define RIRB_INT_MASK 0x05
234
2f5983f2
TI		 235/* STATESTS int mask: S3,SD2,SD1,SD0 */
236#define AZX_MAX_CODECS 4
237#define STATESTS_INT_MASK 0x0f
1da177e4
LT		 238
239/* SD_CTL bits */
240#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
241#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 242#define SD_CTL_STRIPE (3 << 16) /* stripe control */
243#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
244#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 245#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
246#define SD_CTL_STREAM_TAG_SHIFT 20
247
248/* SD_CTL and SD_STS */
249#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
250#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
251#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 252#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
253 SD_INT_COMPLETE)
1da177e4
LT		 254
255/* SD_STS */
256#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
257
258/* INTCTL and INTSTS */
d01ce99f
TI		 259#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
260#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
261#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 262
41e2fce4
M		 263/* GCTL unsolicited response enable bit */
264#define ICH6_GCTL_UREN (1<<8)
265
1da177e4
LT		 266/* GCTL reset bit */
267#define ICH6_GCTL_RESET (1<<0)
268
269/* CORB/RIRB control, read/write pointer */
270#define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
271#define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
272#define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
273/* below are so far hardcoded - should read registers in future */
274#define ICH6_MAX_CORB_ENTRIES 256
275#define ICH6_MAX_RIRB_ENTRIES 256
276
c74db86b
TI		 277/* position fix mode */
278enum {
0be3b5d3 279 POS_FIX_AUTO,
d2e1c973 280 POS_FIX_LPIB,
0be3b5d3 281 POS_FIX_POSBUF,
c74db86b 282};
1da177e4 283
f5d40b30 284/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 285#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
286#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
287
da3fca21
V		 288/* Defines for Nvidia HDA support */
289#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
290#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 291#define NVIDIA_HDA_ISTRM_COH 0x4d
292#define NVIDIA_HDA_OSTRM_COH 0x4c
293#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 294
90a5ad52
TI		 295/* Defines for Intel SCH HDA snoop control */
296#define INTEL_SCH_HDA_DEVC 0x78
297#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
298
0e153474
JC		 299/* Define IN stream 0 FIFO size offset in VIA controller */
300#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
301/* Define VIA HD Audio Device ID*/
302#define VIA_HDAC_DEVICE_ID 0x3288
303
c4da29ca
YL		 304/* HD Audio class code */
305#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 306
1da177e4
LT		 307/*
308 */
309
a98f90fd 310struct azx_dev {
4ce107b9 311 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 312 u32 *posbuf; /* position buffer pointer */
1da177e4 313
d01ce99f 314 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 315 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 316 unsigned int frags; /* number for period in the play buffer */
317 unsigned int fifo_size; /* FIFO size */
fa00e046
JK		 318 unsigned long start_jiffies; /* start + minimum jiffies */
319 unsigned long min_jiffies; /* minimum jiffies before position is valid */
1da177e4 320
d01ce99f 321 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 322
d01ce99f 323 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 324
325 /* pcm support */
d01ce99f
TI		 326 struct snd_pcm_substream *substream; /* assigned substream,
327 * set in PCM open
328 */
329 unsigned int format_val; /* format value to be set in the
330 * controller and the codec
331 */
1da177e4
LT		 332 unsigned char stream_tag; /* assigned stream */
333 unsigned char index; /* stream index */
334
927fc866
PM		 335 unsigned int opened :1;
336 unsigned int running :1;
675f25d4 337 unsigned int irq_pending :1;
d523b0c8 338 unsigned int start_flag: 1; /* stream full start flag */
0e153474
JC		 339 /*
340 * For VIA:
341 * A flag to ensure DMA position is 0
342 * when link position is not greater than FIFO size
343 */
344 unsigned int insufficient :1;
1da177e4
LT		 345};
346
347/* CORB/RIRB */
a98f90fd 348struct azx_rb {
1da177e4
LT		 349 u32 *buf; /* CORB/RIRB buffer
350 * Each CORB entry is 4byte, RIRB is 8byte
351 */
352 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
353 /* for RIRB */
354 unsigned short rp, wp; /* read/write pointers */
355 int cmds; /* number of pending requests */
356 u32 res; /* last read value */
357};
358
a98f90fd
TI		 359struct azx {
360 struct snd_card *card;
1da177e4 361 struct pci_dev *pci;
555e219f 362 int dev_index;
1da177e4 363
07e4ca50
TI		 364 /* chip type specific */
365 int driver_type;
366 int playback_streams;
367 int playback_index_offset;
368 int capture_streams;
369 int capture_index_offset;
370 int num_streams;
371
1da177e4
LT		 372 /* pci resources */
373 unsigned long addr;
374 void __iomem *remap_addr;
375 int irq;
376
377 /* locks */
378 spinlock_t reg_lock;
62932df8 379 struct mutex open_mutex;
1da177e4 380
07e4ca50 381 /* streams (x num_streams) */
a98f90fd 382 struct azx_dev *azx_dev;
1da177e4
LT		 383
384 /* PCM */
a98f90fd 385 struct snd_pcm *pcm[AZX_MAX_PCMS];
1da177e4
LT		 386
387 /* HD codec */
388 unsigned short codec_mask;
f1eaaeec 389 int codec_probe_mask; /* copied from probe_mask option */
1da177e4
LT		 390 struct hda_bus *bus;
391
392 /* CORB/RIRB */
a98f90fd
TI		 393 struct azx_rb corb;
394 struct azx_rb rirb;
1da177e4 395
4ce107b9 396 /* CORB/RIRB and position buffers */
1da177e4
LT		 397 struct snd_dma_buffer rb;
398 struct snd_dma_buffer posbuf;
c74db86b
TI		 399
400 /* flags */
401 int position_fix;
cb53c626 402 unsigned int running :1;
927fc866
PM		 403 unsigned int initialized :1;
404 unsigned int single_cmd :1;
405 unsigned int polling_mode :1;
68e7fffc 406 unsigned int msi :1;
a6a950a8 407 unsigned int irq_pending_warned :1;
0e153474 408 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
6ce4a3bc 409 unsigned int probing :1; /* codec probing phase */
43bbb6cc
TI		 410
411 /* for debugging */
412 unsigned int last_cmd; /* last issued command (to sync) */
9ad593f6
TI		 413
414 /* for pending irqs */
415 struct work_struct irq_pending_work;
0cbf0098
TI		 416
417 /* reboot notifier (for mysterious hangup problem at power-down) */
418 struct notifier_block reboot_notifier;
1da177e4
LT		 419};
420
07e4ca50
TI		 421/* driver types */
422enum {
423 AZX_DRIVER_ICH,
4979bca9 424 AZX_DRIVER_SCH,
07e4ca50 425 AZX_DRIVER_ATI,
778b6e1b 426 AZX_DRIVER_ATIHDMI,
07e4ca50
TI		 427 AZX_DRIVER_VIA,
428 AZX_DRIVER_SIS,
429 AZX_DRIVER_ULI,
da3fca21 430 AZX_DRIVER_NVIDIA,
f269002e 431 AZX_DRIVER_TERA,
c4da29ca 432 AZX_DRIVER_GENERIC,
2f5983f2 433 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 434};
435
436static char *driver_short_names[] __devinitdata = {
437 [AZX_DRIVER_ICH] = "HDA Intel",
4979bca9 438 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 439 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 440 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI		 441 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
442 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 443 [AZX_DRIVER_ULI] = "HDA ULI M5461",
444 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 445 [AZX_DRIVER_TERA] = "HDA Teradici",
c4da29ca 446 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 447};
448
1da177e4
LT		 449/*
450 * macros for easy use
451 */
452#define azx_writel(chip,reg,value) \
453 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
454#define azx_readl(chip,reg) \
455 readl((chip)->remap_addr + ICH6_REG_##reg)
456#define azx_writew(chip,reg,value) \
457 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
458#define azx_readw(chip,reg) \
459 readw((chip)->remap_addr + ICH6_REG_##reg)
460#define azx_writeb(chip,reg,value) \
461 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
462#define azx_readb(chip,reg) \
463 readb((chip)->remap_addr + ICH6_REG_##reg)
464
465#define azx_sd_writel(dev,reg,value) \
466 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
467#define azx_sd_readl(dev,reg) \
468 readl((dev)->sd_addr + ICH6_REG_##reg)
469#define azx_sd_writew(dev,reg,value) \
470 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
471#define azx_sd_readw(dev,reg) \
472 readw((dev)->sd_addr + ICH6_REG_##reg)
473#define azx_sd_writeb(dev,reg,value) \
474 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
475#define azx_sd_readb(dev,reg) \
476 readb((dev)->sd_addr + ICH6_REG_##reg)
477
478/* for pcm support */
a98f90fd 479#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 480
68e7fffc 481static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1da177e4
LT		 482
483/*
484 * Interface for HD codec
485 */
486
1da177e4
LT		 487/*
488 * CORB / RIRB interface
489 */
a98f90fd 490static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 491{
492 int err;
493
494 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 495 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
496 snd_dma_pci_data(chip->pci),
1da177e4
LT		 497 PAGE_SIZE, &chip->rb);
498 if (err < 0) {
499 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
500 return err;
501 }
502 return 0;
503}
504
a98f90fd 505static void azx_init_cmd_io(struct azx *chip)
1da177e4
LT		 506{
507 /* CORB set up */
508 chip->corb.addr = chip->rb.addr;
509 chip->corb.buf = (u32 *)chip->rb.area;
510 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 511 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 512
07e4ca50
TI		 513 /* set the corb size to 256 entries (ULI requires explicitly) */
514 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 515 /* set the corb write pointer to 0 */
516 azx_writew(chip, CORBWP, 0);
517 /* reset the corb hw read pointer */
518 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
519 /* enable corb dma */
520 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
521
522 /* RIRB set up */
523 chip->rirb.addr = chip->rb.addr + 2048;
524 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
4fcd3920 525 chip->rirb.wp = chip->rirb.rp = chip->rirb.cmds = 0;
1da177e4 526 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 527 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 528
07e4ca50
TI		 529 /* set the rirb size to 256 entries (ULI requires explicitly) */
530 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4
LT		 531 /* reset the rirb hw write pointer */
532 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
533 /* set N=1, get RIRB response interrupt for new entry */
534 azx_writew(chip, RINTCNT, 1);
535 /* enable rirb dma and response irq */
1da177e4 536 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
1da177e4
LT		 537}
538
a98f90fd 539static void azx_free_cmd_io(struct azx *chip)
1da177e4
LT		 540{
541 /* disable ringbuffer DMAs */
542 azx_writeb(chip, RIRBCTL, 0);
543 azx_writeb(chip, CORBCTL, 0);
544}
545
546/* send a command */
33fa35ed 547static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 548{
33fa35ed 549 struct azx *chip = bus->private_data;
1da177e4 550 unsigned int wp;
1da177e4
LT		 551
552 /* add command to corb */
553 wp = azx_readb(chip, CORBWP);
554 wp++;
555 wp %= ICH6_MAX_CORB_ENTRIES;
556
557 spin_lock_irq(&chip->reg_lock);
558 chip->rirb.cmds++;
559 chip->corb.buf[wp] = cpu_to_le32(val);
560 azx_writel(chip, CORBWP, wp);
561 spin_unlock_irq(&chip->reg_lock);
562
563 return 0;
564}
565
566#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
567
568/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 569static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 570{
571 unsigned int rp, wp;
572 u32 res, res_ex;
573
574 wp = azx_readb(chip, RIRBWP);
575 if (wp == chip->rirb.wp)
576 return;
577 chip->rirb.wp = wp;
578
579 while (chip->rirb.rp != wp) {
580 chip->rirb.rp++;
581 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
582
583 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
584 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
585 res = le32_to_cpu(chip->rirb.buf[rp]);
586 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
587 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
588 else if (chip->rirb.cmds) {
1da177e4 589 chip->rirb.res = res;
2add9b92
TI		 590 smp_wmb();
591 chip->rirb.cmds--;
1da177e4
LT		 592 }
593 }
594}
595
596/* receive a response */
33fa35ed 597static unsigned int azx_rirb_get_response(struct hda_bus *bus)
1da177e4 598{
33fa35ed 599 struct azx *chip = bus->private_data;
5c79b1f8 600 unsigned long timeout;
1da177e4 601
5c79b1f8
TI		 602 again:
603 timeout = jiffies + msecs_to_jiffies(1000);
28a0d9df 604 for (;;) {
e96224ae
TI		 605 if (chip->polling_mode) {
606 spin_lock_irq(&chip->reg_lock);
607 azx_update_rirb(chip);
608 spin_unlock_irq(&chip->reg_lock);
609 }
2add9b92
TI		 610 if (!chip->rirb.cmds) {
611 smp_rmb();
b613291f 612 bus->rirb_error = 0;
5c79b1f8 613 return chip->rirb.res; /* the last value */
2add9b92 614 }
28a0d9df
TI		 615 if (time_after(jiffies, timeout))
616 break;
33fa35ed 617 if (bus->needs_damn_long_delay)
52987656
TI		 618 msleep(2); /* temporary workaround */
619 else {
620 udelay(10);
621 cond_resched();
622 }
28a0d9df 623 }
5c79b1f8 624
68e7fffc 625 if (chip->msi) {
4abc1cc2 626 snd_printk(KERN_WARNING SFX "No response from codec, "
43bbb6cc 627 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
68e7fffc
TI		 628 free_irq(chip->irq, chip);
629 chip->irq = -1;
630 pci_disable_msi(chip->pci);
631 chip->msi = 0;
b613291f
TI		 632 if (azx_acquire_irq(chip, 1) < 0) {
633 bus->rirb_error = 1;
68e7fffc 634 return -1;
b613291f 635 }
68e7fffc
TI		 636 goto again;
637 }
638
5c79b1f8 639 if (!chip->polling_mode) {
4abc1cc2 640 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
43bbb6cc
TI		 641 "switching to polling mode: last cmd=0x%08x\n",
642 chip->last_cmd);
5c79b1f8
TI		 643 chip->polling_mode = 1;
644 goto again;
1da177e4 645 }
5c79b1f8 646
6ce4a3bc
TI		 647 if (chip->probing) {
648 /* If this critical timeout happens during the codec probing
649 * phase, this is likely an access to a non-existing codec
650 * slot. Better to return an error and reset the system.
651 */
652 return -1;
653 }
654
4abc1cc2 655 snd_printk(KERN_ERR SFX "azx_get_response timeout (ERROR): "
b613291f 656 "last cmd=0x%08x\n", chip->last_cmd);
4fcd3920 657 /* re-initialize CORB/RIRB */
b613291f 658 spin_lock_irq(&chip->reg_lock);
b613291f 659 bus->rirb_error = 1;
4fcd3920
TI		 660 azx_free_cmd_io(chip);
661 azx_init_cmd_io(chip);
b613291f 662 spin_unlock_irq(&chip->reg_lock);
5c79b1f8 663 return -1;
1da177e4
LT		 664}
665
1da177e4
LT		 666/*
667 * Use the single immediate command instead of CORB/RIRB for simplicity
668 *
669 * Note: according to Intel, this is not preferred use. The command was
670 * intended for the BIOS only, and may get confused with unsolicited
671 * responses. So, we shouldn't use it for normal operation from the
672 * driver.
673 * I left the codes, however, for debugging/testing purposes.
674 */
675
1da177e4 676/* send a command */
33fa35ed 677static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 678{
33fa35ed 679 struct azx *chip = bus->private_data;
1da177e4
LT		 680 int timeout = 50;
681
1da177e4
LT		 682 while (timeout--) {
683 /* check ICB busy bit */
d01ce99f 684 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 685 /* Clear IRV valid bit */
d01ce99f
TI		 686 azx_writew(chip, IRS, azx_readw(chip, IRS) |
687 ICH6_IRS_VALID);
1da177e4 688 azx_writel(chip, IC, val);
d01ce99f
TI		 689 azx_writew(chip, IRS, azx_readw(chip, IRS) |
690 ICH6_IRS_BUSY);
1da177e4
LT		 691 return 0;
692 }
693 udelay(1);
694 }
1cfd52bc
MB		 695 if (printk_ratelimit())
696 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
697 azx_readw(chip, IRS), val);
1da177e4
LT		 698 return -EIO;
699}
700
701/* receive a response */
33fa35ed 702static unsigned int azx_single_get_response(struct hda_bus *bus)
1da177e4 703{
33fa35ed 704 struct azx *chip = bus->private_data;
1da177e4
LT		 705 int timeout = 50;
706
707 while (timeout--) {
708 /* check IRV busy bit */
709 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
710 return azx_readl(chip, IR);
711 udelay(1);
712 }
1cfd52bc
MB		 713 if (printk_ratelimit())
714 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
715 azx_readw(chip, IRS));
1da177e4
LT		 716 return (unsigned int)-1;
717}
718
111d3af5
TI		 719/*
720 * The below are the main callbacks from hda_codec.
721 *
722 * They are just the skeleton to call sub-callbacks according to the
723 * current setting of chip->single_cmd.
724 */
725
726/* send a command */
33fa35ed 727static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 728{
33fa35ed 729 struct azx *chip = bus->private_data;
43bbb6cc 730
33fa35ed 731 chip->last_cmd = val;
111d3af5 732 if (chip->single_cmd)
33fa35ed 733 return azx_single_send_cmd(bus, val);
111d3af5 734 else
33fa35ed 735 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 736}
737
738/* get a response */
33fa35ed 739static unsigned int azx_get_response(struct hda_bus *bus)
111d3af5 740{
33fa35ed 741 struct azx *chip = bus->private_data;
111d3af5 742 if (chip->single_cmd)
33fa35ed 743 return azx_single_get_response(bus);
111d3af5 744 else
33fa35ed 745 return azx_rirb_get_response(bus);
111d3af5
TI		 746}
747
cb53c626 748#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 749static void azx_power_notify(struct hda_bus *bus);
cb53c626 750#endif
111d3af5 751
1da177e4 752/* reset codec link */
a98f90fd 753static int azx_reset(struct azx *chip)
1da177e4
LT		 754{
755 int count;
756
e8a7f136
DT		 757 /* clear STATESTS */
758 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
759
1da177e4
LT		 760 /* reset controller */
761 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
762
763 count = 50;
764 while (azx_readb(chip, GCTL) && --count)
765 msleep(1);
766
767 /* delay for >= 100us for codec PLL to settle per spec
768 * Rev 0.9 section 5.5.1
769 */
770 msleep(1);
771
772 /* Bring controller out of reset */
773 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
774
775 count = 50;
927fc866 776 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 777 msleep(1);
778
927fc866 779 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 780 msleep(1);
781
782 /* check to see if controller is ready */
927fc866 783 if (!azx_readb(chip, GCTL)) {
4abc1cc2 784 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 785 return -EBUSY;
786 }
787
41e2fce4
M		 788 /* Accept unsolicited responses */
789 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
790
1da177e4 791 /* detect codecs */
927fc866 792 if (!chip->codec_mask) {
1da177e4 793 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 794 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 795 }
796
797 return 0;
798}
799
800
801/*
802 * Lowlevel interface
803 */
804
805/* enable interrupts */
a98f90fd 806static void azx_int_enable(struct azx *chip)
1da177e4
LT		 807{
808 /* enable controller CIE and GIE */
809 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
810 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
811}
812
813/* disable interrupts */
a98f90fd 814static void azx_int_disable(struct azx *chip)
1da177e4
LT		 815{
816 int i;
817
818 /* disable interrupts in stream descriptor */
07e4ca50 819 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 820 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 821 azx_sd_writeb(azx_dev, SD_CTL,
822 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
823 }
824
825 /* disable SIE for all streams */
826 azx_writeb(chip, INTCTL, 0);
827
828 /* disable controller CIE and GIE */
829 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
830 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
831}
832
833/* clear interrupts */
a98f90fd 834static void azx_int_clear(struct azx *chip)
1da177e4
LT		 835{
836 int i;
837
838 /* clear stream status */
07e4ca50 839 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 840 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 841 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
842 }
843
844 /* clear STATESTS */
845 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
846
847 /* clear rirb status */
848 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
849
850 /* clear int status */
851 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
852}
853
854/* start a stream */
a98f90fd 855static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 856{
0e153474
JC		 857 /*
858 * Before stream start, initialize parameter
859 */
860 azx_dev->insufficient = 1;
861
1da177e4
LT		 862 /* enable SIE */
863 azx_writeb(chip, INTCTL,
864 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
865 /* set DMA start and interrupt mask */
866 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
867 SD_CTL_DMA_START | SD_INT_MASK);
868}
869
1dddab40
TI		 870/* stop DMA */
871static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 872{
1da177e4
LT		 873 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
874 ~(SD_CTL_DMA_START | SD_INT_MASK));
875 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 876}
877
878/* stop a stream */
879static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
880{
881 azx_stream_clear(chip, azx_dev);
1da177e4
LT		 882 /* disable SIE */
883 azx_writeb(chip, INTCTL,
884 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
885}
886
887
888/*
cb53c626 889 * reset and start the controller registers
1da177e4 890 */
a98f90fd 891static void azx_init_chip(struct azx *chip)
1da177e4 892{
cb53c626
TI		 893 if (chip->initialized)
894 return;
1da177e4
LT		 895
896 /* reset controller */
897 azx_reset(chip);
898
899 /* initialize interrupts */
900 azx_int_clear(chip);
901 azx_int_enable(chip);
902
903 /* initialize the codec command I/O */
927fc866 904 if (!chip->single_cmd)
27346166 905 azx_init_cmd_io(chip);
1da177e4 906
0be3b5d3
TI		 907 /* program the position buffer */
908 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 909 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 910
cb53c626
TI		 911 chip->initialized = 1;
912}
913
914/*
915 * initialize the PCI registers
916 */
917/* update bits in a PCI register byte */
918static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
919 unsigned char mask, unsigned char val)
920{
921 unsigned char data;
922
923 pci_read_config_byte(pci, reg, &data);
924 data &= ~mask;
925 data |= (val & mask);
926 pci_write_config_byte(pci, reg, data);
927}
928
929static void azx_init_pci(struct azx *chip)
930{
90a5ad52
TI		 931 unsigned short snoop;
932
cb53c626
TI		 933 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
934 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
935 * Ensuring these bits are 0 clears playback static on some HD Audio
936 * codecs
937 */
938 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
939
da3fca21
V		 940 switch (chip->driver_type) {
941 case AZX_DRIVER_ATI:
942 /* For ATI SB450 azalia HD audio, we need to enable snoop */
cb53c626
TI		 943 update_pci_byte(chip->pci,
944 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
945 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
da3fca21
V		 946 break;
947 case AZX_DRIVER_NVIDIA:
948 /* For NVIDIA HDA, enable snoop */
cb53c626
TI		 949 update_pci_byte(chip->pci,
950 NVIDIA_HDA_TRANSREG_ADDR,
951 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 952 update_pci_byte(chip->pci,
953 NVIDIA_HDA_ISTRM_COH,
954 0x01, NVIDIA_HDA_ENABLE_COHBIT);
955 update_pci_byte(chip->pci,
956 NVIDIA_HDA_OSTRM_COH,
957 0x01, NVIDIA_HDA_ENABLE_COHBIT);
da3fca21 958 break;
90a5ad52
TI		 959 case AZX_DRIVER_SCH:
960 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
961 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
4abc1cc2 962 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
90a5ad52
TI		 963 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
964 pci_read_config_word(chip->pci,
965 INTEL_SCH_HDA_DEVC, &snoop);
4abc1cc2
TI		 966 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
967 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
90a5ad52
TI		 968 ? "Failed" : "OK");
969 }
970 break;
971
da3fca21 972 }
1da177e4
LT		 973}
974
975
9ad593f6
TI		 976static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
977
1da177e4
LT		 978/*
979 * interrupt handler
980 */
7d12e780 981static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 982{
a98f90fd
TI		 983 struct azx *chip = dev_id;
984 struct azx_dev *azx_dev;
1da177e4 985 u32 status;
fa00e046 986 int i, ok;
1da177e4
LT		 987
988 spin_lock(&chip->reg_lock);
989
990 status = azx_readl(chip, INTSTS);
991 if (status == 0) {
992 spin_unlock(&chip->reg_lock);
993 return IRQ_NONE;
994 }
995
07e4ca50 996 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 997 azx_dev = &chip->azx_dev[i];
998 if (status & azx_dev->sd_int_sta_mask) {
999 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ad593f6
TI		 1000 if (!azx_dev->substream || !azx_dev->running)
1001 continue;
1002 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1003 ok = azx_position_ok(chip, azx_dev);
1004 if (ok == 1) {
9ad593f6 1005 azx_dev->irq_pending = 0;
1da177e4
LT		 1006 spin_unlock(&chip->reg_lock);
1007 snd_pcm_period_elapsed(azx_dev->substream);
1008 spin_lock(&chip->reg_lock);
fa00e046 1009 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1010 /* bogus IRQ, process it later */
1011 azx_dev->irq_pending = 1;
6acaed38
TI		 1012 queue_work(chip->bus->workq,
1013 &chip->irq_pending_work);
1da177e4
LT		 1014 }
1015 }
1016 }
1017
1018 /* clear rirb int */
1019 status = azx_readb(chip, RIRBSTS);
1020 if (status & RIRB_INT_MASK) {
d01ce99f 1021 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
1da177e4
LT		 1022 azx_update_rirb(chip);
1023 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1024 }
1025
1026#if 0
1027 /* clear state status int */
1028 if (azx_readb(chip, STATESTS) & 0x04)
1029 azx_writeb(chip, STATESTS, 0x04);
1030#endif
1031 spin_unlock(&chip->reg_lock);
1032
1033 return IRQ_HANDLED;
1034}
1035
1036
675f25d4
TI		 1037/*
1038 * set up a BDL entry
1039 */
1040static int setup_bdle(struct snd_pcm_substream *substream,
1041 struct azx_dev *azx_dev, u32 **bdlp,
1042 int ofs, int size, int with_ioc)
1043{
675f25d4
TI		 1044 u32 *bdl = *bdlp;
1045
1046 while (size > 0) {
1047 dma_addr_t addr;
1048 int chunk;
1049
1050 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1051 return -EINVAL;
1052
77a23f26 1053 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1054 /* program the address field of the BDL entry */
1055 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1056 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1057 /* program the size field of the BDL entry */
fc4abee8 1058 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
675f25d4
TI		 1059 bdl[2] = cpu_to_le32(chunk);
1060 /* program the IOC to enable interrupt
1061 * only when the whole fragment is processed
1062 */
1063 size -= chunk;
1064 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1065 bdl += 4;
1066 azx_dev->frags++;
1067 ofs += chunk;
1068 }
1069 *bdlp = bdl;
1070 return ofs;
1071}
1072
1da177e4
LT		 1073/*
1074 * set up BDL entries
1075 */
555e219f
TI		 1076static int azx_setup_periods(struct azx *chip,
1077 struct snd_pcm_substream *substream,
4ce107b9 1078 struct azx_dev *azx_dev)
1da177e4 1079{
4ce107b9
TI		 1080 u32 *bdl;
1081 int i, ofs, periods, period_bytes;
555e219f 1082 int pos_adj;
1da177e4
LT		 1083
1084 /* reset BDL address */
1085 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1086 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1087
97b71c94 1088 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1089 periods = azx_dev->bufsize / period_bytes;
1090
1da177e4 1091 /* program the initial BDL entries */
4ce107b9
TI		 1092 bdl = (u32 *)azx_dev->bdl.area;
1093 ofs = 0;
1094 azx_dev->frags = 0;
555e219f
TI		 1095 pos_adj = bdl_pos_adj[chip->dev_index];
1096 if (pos_adj > 0) {
675f25d4 1097 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1098 int pos_align = pos_adj;
555e219f 1099 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1100 if (!pos_adj)
e785d3d8
TI		 1101 pos_adj = pos_align;
1102 else
1103 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1104 pos_align;
675f25d4
TI		 1105 pos_adj = frames_to_bytes(runtime, pos_adj);
1106 if (pos_adj >= period_bytes) {
4abc1cc2 1107 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1108 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1109 pos_adj = 0;
1110 } else {
1111 ofs = setup_bdle(substream, azx_dev,
1112 &bdl, ofs, pos_adj, 1);
1113 if (ofs < 0)
1114 goto error;
4ce107b9 1115 }
555e219f
TI		 1116 } else
1117 pos_adj = 0;
675f25d4
TI		 1118 for (i = 0; i < periods; i++) {
1119 if (i == periods - 1 && pos_adj)
1120 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1121 period_bytes - pos_adj, 0);
1122 else
1123 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1124 period_bytes, 1);
1125 if (ofs < 0)
1126 goto error;
1da177e4 1127 }
4ce107b9 1128 return 0;
675f25d4
TI		 1129
1130 error:
4abc1cc2 1131 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1132 azx_dev->bufsize, period_bytes);
675f25d4 1133 return -EINVAL;
1da177e4
LT		 1134}
1135
1dddab40
TI		 1136/* reset stream */
1137static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1138{
1139 unsigned char val;
1140 int timeout;
1141
1dddab40
TI		 1142 azx_stream_clear(chip, azx_dev);
1143
d01ce99f
TI		 1144 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1145 SD_CTL_STREAM_RESET);
1da177e4
LT		 1146 udelay(3);
1147 timeout = 300;
1148 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1149 --timeout)
1150 ;
1151 val &= ~SD_CTL_STREAM_RESET;
1152 azx_sd_writeb(azx_dev, SD_CTL, val);
1153 udelay(3);
1154
1155 timeout = 300;
1156 /* waiting for hardware to report that the stream is out of reset */
1157 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1158 --timeout)
1159 ;
fa00e046
JK		 1160
1161 /* reset first position - may not be synced with hw at this time */
1162 *azx_dev->posbuf = 0;
1dddab40 1163}
1da177e4 1164
1dddab40
TI		 1165/*
1166 * set up the SD for streaming
1167 */
1168static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1169{
1170 /* make sure the run bit is zero for SD */
1171 azx_stream_clear(chip, azx_dev);
1da177e4
LT		 1172 /* program the stream_tag */
1173 azx_sd_writel(azx_dev, SD_CTL,
d01ce99f 1174 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1da177e4
LT		 1175 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1176
1177 /* program the length of samples in cyclic buffer */
1178 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1179
1180 /* program the stream format */
1181 /* this value needs to be the same as the one programmed */
1182 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1183
1184 /* program the stream LVI (last valid index) of the BDL */
1185 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1186
1187 /* program the BDL address */
1188 /* lower BDL address */
4ce107b9 1189 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1190 /* upper BDL address */
766979e0 1191 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1192
0be3b5d3 1193 /* enable the position buffer */
ee9d6b9a 1194 if (chip->position_fix == POS_FIX_POSBUF ||
0e153474
JC		 1195 chip->position_fix == POS_FIX_AUTO ||
1196 chip->via_dmapos_patch) {
ee9d6b9a
TI		 1197 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1198 azx_writel(chip, DPLBASE,
1199 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1200 }
c74db86b 1201
1da177e4 1202 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1203 azx_sd_writel(azx_dev, SD_CTL,
1204 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1205
1206 return 0;
1207}
1208
6ce4a3bc
TI		 1209/*
1210 * Probe the given codec address
1211 */
1212static int probe_codec(struct azx *chip, int addr)
1213{
1214 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1215 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1216 unsigned int res;
1217
1218 chip->probing = 1;
1219 azx_send_cmd(chip->bus, cmd);
1220 res = azx_get_response(chip->bus);
1221 chip->probing = 0;
1222 if (res == -1)
1223 return -EIO;
4abc1cc2 1224 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1225 return 0;
1226}
1227
33fa35ed
TI		 1228static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1229 struct hda_pcm *cpcm);
6ce4a3bc 1230static void azx_stop_chip(struct azx *chip);
1da177e4
LT		 1231
1232/*
1233 * Codec initialization
1234 */
1235
2f5983f2
TI		 1236/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1237static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
f269002e 1238 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1239};
1240
5aba4f8e 1241static int __devinit azx_codec_create(struct azx *chip, const char *model,
d4d9cd03 1242 int no_init)
1da177e4
LT		 1243{
1244 struct hda_bus_template bus_temp;
34c25350
TI		 1245 int c, codecs, err;
1246 int max_slots;
1da177e4
LT		 1247
1248 memset(&bus_temp, 0, sizeof(bus_temp));
1249 bus_temp.private_data = chip;
1250 bus_temp.modelname = model;
1251 bus_temp.pci = chip->pci;
111d3af5
TI		 1252 bus_temp.ops.command = azx_send_cmd;
1253 bus_temp.ops.get_response = azx_get_response;
176d5335 1254 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
cb53c626 1255#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1256 bus_temp.power_save = &power_save;
cb53c626
TI		 1257 bus_temp.ops.pm_notify = azx_power_notify;
1258#endif
1da177e4 1259
d01ce99f
TI		 1260 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1261 if (err < 0)
1da177e4
LT		 1262 return err;
1263
dc9c8e21
WN		 1264 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1265 chip->bus->needs_damn_long_delay = 1;
1266
34c25350 1267 codecs = 0;
2f5983f2
TI		 1268 max_slots = azx_max_codecs[chip->driver_type];
1269 if (!max_slots)
1270 max_slots = AZX_MAX_CODECS;
6ce4a3bc
TI		 1271
1272 /* First try to probe all given codec slots */
1273 for (c = 0; c < max_slots; c++) {
f1eaaeec 1274 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1275 if (probe_codec(chip, c) < 0) {
1276 /* Some BIOSen give you wrong codec addresses
1277 * that don't exist
1278 */
4abc1cc2
TI		 1279 snd_printk(KERN_WARNING SFX
1280 "Codec #%d probe error; "
6ce4a3bc
TI		 1281 "disabling it...\n", c);
1282 chip->codec_mask &= ~(1 << c);
1283 /* More badly, accessing to a non-existing
1284 * codec often screws up the controller chip,
1285 * and distrubs the further communications.
1286 * Thus if an error occurs during probing,
1287 * better to reset the controller chip to
1288 * get back to the sanity state.
1289 */
1290 azx_stop_chip(chip);
1291 azx_init_chip(chip);
1292 }
1293 }
1294 }
1295
1296 /* Then create codec instances */
34c25350 1297 for (c = 0; c < max_slots; c++) {
f1eaaeec 1298 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1299 struct hda_codec *codec;
d4d9cd03 1300 err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1da177e4
LT		 1301 if (err < 0)
1302 continue;
1303 codecs++;
19a982b6
TI		 1304 }
1305 }
1306 if (!codecs) {
1da177e4
LT		 1307 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1308 return -ENXIO;
1309 }
1310
1311 return 0;
1312}
1313
1314
1315/*
1316 * PCM support
1317 */
1318
1319/* assign a stream for the PCM */
a98f90fd 1320static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1da177e4 1321{
07e4ca50
TI		 1322 int dev, i, nums;
1323 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1324 dev = chip->playback_index_offset;
1325 nums = chip->playback_streams;
1326 } else {
1327 dev = chip->capture_index_offset;
1328 nums = chip->capture_streams;
1329 }
1330 for (i = 0; i < nums; i++, dev++)
d01ce99f 1331 if (!chip->azx_dev[dev].opened) {
1da177e4
LT		 1332 chip->azx_dev[dev].opened = 1;
1333 return &chip->azx_dev[dev];
1334 }
1335 return NULL;
1336}
1337
1338/* release the assigned stream */
a98f90fd 1339static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1340{
1341 azx_dev->opened = 0;
1342}
1343
a98f90fd 1344static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1345 .info = (SNDRV_PCM_INFO_MMAP |
1346 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1347 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1348 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1349 /* No full-resume yet implemented */
1350 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52
TI		 1351 SNDRV_PCM_INFO_PAUSE |
1352 SNDRV_PCM_INFO_SYNC_START),
1da177e4
LT		 1353 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1354 .rates = SNDRV_PCM_RATE_48000,
1355 .rate_min = 48000,
1356 .rate_max = 48000,
1357 .channels_min = 2,
1358 .channels_max = 2,
1359 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1360 .period_bytes_min = 128,
1361 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1362 .periods_min = 2,
1363 .periods_max = AZX_MAX_FRAG,
1364 .fifo_size = 0,
1365};
1366
1367struct azx_pcm {
a98f90fd 1368 struct azx *chip;
1da177e4
LT		 1369 struct hda_codec *codec;
1370 struct hda_pcm_stream *hinfo[2];
1371};
1372
a98f90fd 1373static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1374{
1375 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1376 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1377 struct azx *chip = apcm->chip;
1378 struct azx_dev *azx_dev;
1379 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1380 unsigned long flags;
1381 int err;
1382
62932df8 1383 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1384 azx_dev = azx_assign_device(chip, substream->stream);
1385 if (azx_dev == NULL) {
62932df8 1386 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1387 return -EBUSY;
1388 }
1389 runtime->hw = azx_pcm_hw;
1390 runtime->hw.channels_min = hinfo->channels_min;
1391 runtime->hw.channels_max = hinfo->channels_max;
1392 runtime->hw.formats = hinfo->formats;
1393 runtime->hw.rates = hinfo->rates;
1394 snd_pcm_limit_hw_rates(runtime);
1395 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5f1545bc
JD		 1396 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1397 128);
1398 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1399 128);
cb53c626 1400 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1401 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1402 if (err < 0) {
1da177e4 1403 azx_release_device(azx_dev);
cb53c626 1404 snd_hda_power_down(apcm->codec);
62932df8 1405 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1406 return err;
1407 }
1408 spin_lock_irqsave(&chip->reg_lock, flags);
1409 azx_dev->substream = substream;
1410 azx_dev->running = 0;
1411 spin_unlock_irqrestore(&chip->reg_lock, flags);
1412
1413 runtime->private_data = azx_dev;
850f0e52 1414 snd_pcm_set_sync(substream);
62932df8 1415 mutex_unlock(&chip->open_mutex);
1dddab40 1416
1da177e4
LT		 1417 return 0;
1418}
1419
a98f90fd 1420static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1421{
1422 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1423 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1424 struct azx *chip = apcm->chip;
1425 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1426 unsigned long flags;
1427
62932df8 1428 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1429 spin_lock_irqsave(&chip->reg_lock, flags);
1430 azx_dev->substream = NULL;
1431 azx_dev->running = 0;
1432 spin_unlock_irqrestore(&chip->reg_lock, flags);
1433 azx_release_device(azx_dev);
1434 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1435 snd_hda_power_down(apcm->codec);
62932df8 1436 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1437 return 0;
1438}
1439
d01ce99f
TI		 1440static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1441 struct snd_pcm_hw_params *hw_params)
1da177e4 1442{
97b71c94
TI		 1443 struct azx_dev *azx_dev = get_azx_dev(substream);
1444
1445 azx_dev->bufsize = 0;
1446 azx_dev->period_bytes = 0;
1447 azx_dev->format_val = 0;
d01ce99f
TI		 1448 return snd_pcm_lib_malloc_pages(substream,
1449 params_buffer_bytes(hw_params));
1da177e4
LT		 1450}
1451
a98f90fd 1452static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1453{
1454 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1455 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1456 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1457
1458 /* reset BDL address */
1459 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1460 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1461 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1462 azx_dev->bufsize = 0;
1463 azx_dev->period_bytes = 0;
1464 azx_dev->format_val = 0;
1da177e4
LT		 1465
1466 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1467
1468 return snd_pcm_lib_free_pages(substream);
1469}
1470
a98f90fd 1471static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1472{
1473 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1474 struct azx *chip = apcm->chip;
1475 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1476 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1477 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94
TI		 1478 unsigned int bufsize, period_bytes, format_val;
1479 int err;
1da177e4 1480
fa00e046 1481 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1482 format_val = snd_hda_calc_stream_format(runtime->rate,
1483 runtime->channels,
1484 runtime->format,
1485 hinfo->maxbps);
1486 if (!format_val) {
d01ce99f
TI		 1487 snd_printk(KERN_ERR SFX
1488 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1489 runtime->rate, runtime->channels, runtime->format);
1490 return -EINVAL;
1491 }
1492
97b71c94
TI		 1493 bufsize = snd_pcm_lib_buffer_bytes(substream);
1494 period_bytes = snd_pcm_lib_period_bytes(substream);
1495
4abc1cc2 1496 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1497 bufsize, format_val);
1498
1499 if (bufsize != azx_dev->bufsize ||
1500 period_bytes != azx_dev->period_bytes ||
1501 format_val != azx_dev->format_val) {
1502 azx_dev->bufsize = bufsize;
1503 azx_dev->period_bytes = period_bytes;
1504 azx_dev->format_val = format_val;
1505 err = azx_setup_periods(chip, substream, azx_dev);
1506 if (err < 0)
1507 return err;
1508 }
1509
fa00e046
JK		 1510 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1511 (runtime->rate * 2);
1da177e4
LT		 1512 azx_setup_controller(chip, azx_dev);
1513 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1514 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1515 else
1516 azx_dev->fifo_size = 0;
1517
1518 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1519 azx_dev->format_val, substream);
1520}
1521
a98f90fd 1522static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1523{
1524 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1525 struct azx *chip = apcm->chip;
850f0e52
TI		 1526 struct azx_dev *azx_dev;
1527 struct snd_pcm_substream *s;
fa00e046 1528 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1529 int nwait, timeout;
1da177e4 1530
1da177e4 1531 switch (cmd) {
fa00e046
JK		 1532 case SNDRV_PCM_TRIGGER_START:
1533 rstart = 1;
1da177e4
LT		 1534 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1535 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1536 start = 1;
1da177e4
LT		 1537 break;
1538 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1539 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1540 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1541 start = 0;
1da177e4
LT		 1542 break;
1543 default:
850f0e52
TI		 1544 return -EINVAL;
1545 }
1546
1547 snd_pcm_group_for_each_entry(s, substream) {
1548 if (s->pcm->card != substream->pcm->card)
1549 continue;
1550 azx_dev = get_azx_dev(s);
1551 sbits |= 1 << azx_dev->index;
1552 nsync++;
1553 snd_pcm_trigger_done(s, substream);
1554 }
1555
1556 spin_lock(&chip->reg_lock);
1557 if (nsync > 1) {
1558 /* first, set SYNC bits of corresponding streams */
1559 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1560 }
1561 snd_pcm_group_for_each_entry(s, substream) {
1562 if (s->pcm->card != substream->pcm->card)
1563 continue;
1564 azx_dev = get_azx_dev(s);
fa00e046
JK		 1565 if (rstart) {
1566 azx_dev->start_flag = 1;
1567 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1568 }
850f0e52
TI		 1569 if (start)
1570 azx_stream_start(chip, azx_dev);
1571 else
1572 azx_stream_stop(chip, azx_dev);
1573 azx_dev->running = start;
1da177e4
LT		 1574 }
1575 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1576 if (start) {
1577 if (nsync == 1)
1578 return 0;
1579 /* wait until all FIFOs get ready */
1580 for (timeout = 5000; timeout; timeout--) {
1581 nwait = 0;
1582 snd_pcm_group_for_each_entry(s, substream) {
1583 if (s->pcm->card != substream->pcm->card)
1584 continue;
1585 azx_dev = get_azx_dev(s);
1586 if (!(azx_sd_readb(azx_dev, SD_STS) &
1587 SD_STS_FIFO_READY))
1588 nwait++;
1589 }
1590 if (!nwait)
1591 break;
1592 cpu_relax();
1593 }
1594 } else {
1595 /* wait until all RUN bits are cleared */
1596 for (timeout = 5000; timeout; timeout--) {
1597 nwait = 0;
1598 snd_pcm_group_for_each_entry(s, substream) {
1599 if (s->pcm->card != substream->pcm->card)
1600 continue;
1601 azx_dev = get_azx_dev(s);
1602 if (azx_sd_readb(azx_dev, SD_CTL) &
1603 SD_CTL_DMA_START)
1604 nwait++;
1605 }
1606 if (!nwait)
1607 break;
1608 cpu_relax();
1609 }
1da177e4 1610 }
850f0e52
TI		 1611 if (nsync > 1) {
1612 spin_lock(&chip->reg_lock);
1613 /* reset SYNC bits */
1614 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1615 spin_unlock(&chip->reg_lock);
1616 }
1617 return 0;
1da177e4
LT		 1618}
1619
0e153474
JC		 1620/* get the current DMA position with correction on VIA chips */
1621static unsigned int azx_via_get_position(struct azx *chip,
1622 struct azx_dev *azx_dev)
1623{
1624 unsigned int link_pos, mini_pos, bound_pos;
1625 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1626 unsigned int fifo_size;
1627
1628 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1629 if (azx_dev->index >= 4) {
1630 /* Playback, no problem using link position */
1631 return link_pos;
1632 }
1633
1634 /* Capture */
1635 /* For new chipset,
1636 * use mod to get the DMA position just like old chipset
1637 */
1638 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1639 mod_dma_pos %= azx_dev->period_bytes;
1640
1641 /* azx_dev->fifo_size can't get FIFO size of in stream.
1642 * Get from base address + offset.
1643 */
1644 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1645
1646 if (azx_dev->insufficient) {
1647 /* Link position never gather than FIFO size */
1648 if (link_pos <= fifo_size)
1649 return 0;
1650
1651 azx_dev->insufficient = 0;
1652 }
1653
1654 if (link_pos <= fifo_size)
1655 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1656 else
1657 mini_pos = link_pos - fifo_size;
1658
1659 /* Find nearest previous boudary */
1660 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1661 mod_link_pos = link_pos % azx_dev->period_bytes;
1662 if (mod_link_pos >= fifo_size)
1663 bound_pos = link_pos - mod_link_pos;
1664 else if (mod_dma_pos >= mod_mini_pos)
1665 bound_pos = mini_pos - mod_mini_pos;
1666 else {
1667 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1668 if (bound_pos >= azx_dev->bufsize)
1669 bound_pos = 0;
1670 }
1671
1672 /* Calculate real DMA position we want */
1673 return bound_pos + mod_dma_pos;
1674}
1675
9ad593f6
TI		 1676static unsigned int azx_get_position(struct azx *chip,
1677 struct azx_dev *azx_dev)
1da177e4 1678{
1da177e4
LT		 1679 unsigned int pos;
1680
0e153474
JC		 1681 if (chip->via_dmapos_patch)
1682 pos = azx_via_get_position(chip, azx_dev);
1683 else if (chip->position_fix == POS_FIX_POSBUF ||
1684 chip->position_fix == POS_FIX_AUTO) {
c74db86b 1685 /* use the position buffer */
929861c6 1686 pos = le32_to_cpu(*azx_dev->posbuf);
c74db86b
TI		 1687 } else {
1688 /* read LPIB */
1689 pos = azx_sd_readl(azx_dev, SD_LPIB);
c74db86b 1690 }
1da177e4
LT		 1691 if (pos >= azx_dev->bufsize)
1692 pos = 0;
9ad593f6
TI		 1693 return pos;
1694}
1695
1696static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1697{
1698 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1699 struct azx *chip = apcm->chip;
1700 struct azx_dev *azx_dev = get_azx_dev(substream);
1701 return bytes_to_frames(substream->runtime,
1702 azx_get_position(chip, azx_dev));
1703}
1704
1705/*
1706 * Check whether the current DMA position is acceptable for updating
1707 * periods. Returns non-zero if it's OK.
1708 *
1709 * Many HD-audio controllers appear pretty inaccurate about
1710 * the update-IRQ timing. The IRQ is issued before actually the
1711 * data is processed. So, we need to process it afterwords in a
1712 * workqueue.
1713 */
1714static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1715{
1716 unsigned int pos;
1717
fa00e046
JK		 1718 if (azx_dev->start_flag &&
1719 time_before_eq(jiffies, azx_dev->start_jiffies))
1720 return -1; /* bogus (too early) interrupt */
1721 azx_dev->start_flag = 0;
1722
9ad593f6
TI		 1723 pos = azx_get_position(chip, azx_dev);
1724 if (chip->position_fix == POS_FIX_AUTO) {
1725 if (!pos) {
1726 printk(KERN_WARNING
1727 "hda-intel: Invalid position buffer, "
1728 "using LPIB read method instead.\n");
d2e1c973 1729 chip->position_fix = POS_FIX_LPIB;
9ad593f6
TI		 1730 pos = azx_get_position(chip, azx_dev);
1731 } else
1732 chip->position_fix = POS_FIX_POSBUF;
1733 }
1734
a62741cf
TI		 1735 if (!bdl_pos_adj[chip->dev_index])
1736 return 1; /* no delayed ack */
9ad593f6
TI		 1737 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1738 return 0; /* NG - it's below the period boundary */
1739 return 1; /* OK, it's fine */
1740}
1741
1742/*
1743 * The work for pending PCM period updates.
1744 */
1745static void azx_irq_pending_work(struct work_struct *work)
1746{
1747 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1748 int i, pending;
1749
a6a950a8
TI		 1750 if (!chip->irq_pending_warned) {
1751 printk(KERN_WARNING
1752 "hda-intel: IRQ timing workaround is activated "
1753 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1754 chip->card->number);
1755 chip->irq_pending_warned = 1;
1756 }
1757
9ad593f6
TI		 1758 for (;;) {
1759 pending = 0;
1760 spin_lock_irq(&chip->reg_lock);
1761 for (i = 0; i < chip->num_streams; i++) {
1762 struct azx_dev *azx_dev = &chip->azx_dev[i];
1763 if (!azx_dev->irq_pending ||
1764 !azx_dev->substream ||
1765 !azx_dev->running)
1766 continue;
1767 if (azx_position_ok(chip, azx_dev)) {
1768 azx_dev->irq_pending = 0;
1769 spin_unlock(&chip->reg_lock);
1770 snd_pcm_period_elapsed(azx_dev->substream);
1771 spin_lock(&chip->reg_lock);
1772 } else
1773 pending++;
1774 }
1775 spin_unlock_irq(&chip->reg_lock);
1776 if (!pending)
1777 return;
1778 cond_resched();
1779 }
1780}
1781
1782/* clear irq_pending flags and assure no on-going workq */
1783static void azx_clear_irq_pending(struct azx *chip)
1784{
1785 int i;
1786
1787 spin_lock_irq(&chip->reg_lock);
1788 for (i = 0; i < chip->num_streams; i++)
1789 chip->azx_dev[i].irq_pending = 0;
1790 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1791}
1792
a98f90fd 1793static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 1794 .open = azx_pcm_open,
1795 .close = azx_pcm_close,
1796 .ioctl = snd_pcm_lib_ioctl,
1797 .hw_params = azx_pcm_hw_params,
1798 .hw_free = azx_pcm_hw_free,
1799 .prepare = azx_pcm_prepare,
1800 .trigger = azx_pcm_trigger,
1801 .pointer = azx_pcm_pointer,
4ce107b9 1802 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 1803};
1804
a98f90fd 1805static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 1806{
176d5335
TI		 1807 struct azx_pcm *apcm = pcm->private_data;
1808 if (apcm) {
1809 apcm->chip->pcm[pcm->device] = NULL;
1810 kfree(apcm);
1811 }
1da177e4
LT		 1812}
1813
176d5335 1814static int
33fa35ed
TI		 1815azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1816 struct hda_pcm *cpcm)
1da177e4 1817{
33fa35ed 1818 struct azx *chip = bus->private_data;
a98f90fd 1819 struct snd_pcm *pcm;
1da177e4 1820 struct azx_pcm *apcm;
176d5335
TI		 1821 int pcm_dev = cpcm->device;
1822 int s, err;
1da177e4 1823
176d5335
TI		 1824 if (pcm_dev >= AZX_MAX_PCMS) {
1825 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1826 pcm_dev);
da3cec35 1827 return -EINVAL;
176d5335
TI		 1828 }
1829 if (chip->pcm[pcm_dev]) {
1830 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1831 return -EBUSY;
1832 }
1833 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1834 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1835 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 1836 &pcm);
1837 if (err < 0)
1838 return err;
18cb7109 1839 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 1840 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 1841 if (apcm == NULL)
1842 return -ENOMEM;
1843 apcm->chip = chip;
1844 apcm->codec = codec;
1da177e4
LT		 1845 pcm->private_data = apcm;
1846 pcm->private_free = azx_pcm_free;
176d5335
TI		 1847 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1848 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1849 chip->pcm[pcm_dev] = pcm;
1850 cpcm->pcm = pcm;
1851 for (s = 0; s < 2; s++) {
1852 apcm->hinfo[s] = &cpcm->stream[s];
1853 if (cpcm->stream[s].substreams)
1854 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1855 }
1856 /* buffer pre-allocation */
4ce107b9 1857 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 1858 snd_dma_pci_data(chip->pci),
fc4abee8 1859 1024 * 64, 32 * 1024 * 1024);
1da177e4
LT		 1860 return 0;
1861}
1862
1863/*
1864 * mixer creation - all stuff is implemented in hda module
1865 */
a98f90fd 1866static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 1867{
1868 return snd_hda_build_controls(chip->bus);
1869}
1870
1871
1872/*
1873 * initialize SD streams
1874 */
a98f90fd 1875static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 1876{
1877 int i;
1878
1879 /* initialize each stream (aka device)
d01ce99f
TI		 1880 * assign the starting bdl address to each stream (device)
1881 * and initialize
1da177e4 1882 */
07e4ca50 1883 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1884 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 1885 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 1886 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1887 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1888 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1889 azx_dev->sd_int_sta_mask = 1 << i;
1890 /* stream tag: must be non-zero and unique */
1891 azx_dev->index = i;
1892 azx_dev->stream_tag = i + 1;
1893 }
1894
1895 return 0;
1896}
1897
68e7fffc
TI		 1898static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1899{
437a5a46
TI		 1900 if (request_irq(chip->pci->irq, azx_interrupt,
1901 chip->msi ? 0 : IRQF_SHARED,
68e7fffc
TI		 1902 "HDA Intel", chip)) {
1903 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1904 "disabling device\n", chip->pci->irq);
1905 if (do_disconnect)
1906 snd_card_disconnect(chip->card);
1907 return -1;
1908 }
1909 chip->irq = chip->pci->irq;
69e13418 1910 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 1911 return 0;
1912}
1913
1da177e4 1914
cb53c626
TI		 1915static void azx_stop_chip(struct azx *chip)
1916{
95e99fda 1917 if (!chip->initialized)
cb53c626
TI		 1918 return;
1919
1920 /* disable interrupts */
1921 azx_int_disable(chip);
1922 azx_int_clear(chip);
1923
1924 /* disable CORB/RIRB */
1925 azx_free_cmd_io(chip);
1926
1927 /* disable position buffer */
1928 azx_writel(chip, DPLBASE, 0);
1929 azx_writel(chip, DPUBASE, 0);
1930
1931 chip->initialized = 0;
1932}
1933
1934#ifdef CONFIG_SND_HDA_POWER_SAVE
1935/* power-up/down the controller */
33fa35ed 1936static void azx_power_notify(struct hda_bus *bus)
cb53c626 1937{
33fa35ed 1938 struct azx *chip = bus->private_data;
cb53c626
TI		 1939 struct hda_codec *c;
1940 int power_on = 0;
1941
33fa35ed 1942 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 1943 if (c->power_on) {
1944 power_on = 1;
1945 break;
1946 }
1947 }
1948 if (power_on)
1949 azx_init_chip(chip);
dee1b66c 1950 else if (chip->running && power_save_controller)
cb53c626 1951 azx_stop_chip(chip);
cb53c626 1952}
5c0b9bec
TI		 1953#endif /* CONFIG_SND_HDA_POWER_SAVE */
1954
1955#ifdef CONFIG_PM
1956/*
1957 * power management
1958 */
986862bd
TI		 1959
1960static int snd_hda_codecs_inuse(struct hda_bus *bus)
1961{
1962 struct hda_codec *codec;
1963
1964 list_for_each_entry(codec, &bus->codec_list, list) {
1965 if (snd_hda_codec_needs_resume(codec))
1966 return 1;
1967 }
1968 return 0;
1969}
cb53c626 1970
421a1252 1971static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 1972{
421a1252
TI		 1973 struct snd_card *card = pci_get_drvdata(pci);
1974 struct azx *chip = card->private_data;
1da177e4
LT		 1975 int i;
1976
421a1252 1977 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 1978 azx_clear_irq_pending(chip);
7ba72ba1 1979 for (i = 0; i < AZX_MAX_PCMS; i++)
421a1252 1980 snd_pcm_suspend_all(chip->pcm[i]);
0b7a2e9c
TI		 1981 if (chip->initialized)
1982 snd_hda_suspend(chip->bus, state);
cb53c626 1983 azx_stop_chip(chip);
30b35399 1984 if (chip->irq >= 0) {
43001c95 1985 free_irq(chip->irq, chip);
30b35399
TI		 1986 chip->irq = -1;
1987 }
68e7fffc 1988 if (chip->msi)
43001c95 1989 pci_disable_msi(chip->pci);
421a1252
TI		 1990 pci_disable_device(pci);
1991 pci_save_state(pci);
30b35399 1992 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 1993 return 0;
1994}
1995
421a1252 1996static int azx_resume(struct pci_dev *pci)
1da177e4 1997{
421a1252
TI		 1998 struct snd_card *card = pci_get_drvdata(pci);
1999 struct azx *chip = card->private_data;
1da177e4 2000
d14a7e0b
TI		 2001 pci_set_power_state(pci, PCI_D0);
2002 pci_restore_state(pci);
30b35399
TI		 2003 if (pci_enable_device(pci) < 0) {
2004 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2005 "disabling device\n");
2006 snd_card_disconnect(card);
2007 return -EIO;
2008 }
2009 pci_set_master(pci);
68e7fffc
TI		 2010 if (chip->msi)
2011 if (pci_enable_msi(pci) < 0)
2012 chip->msi = 0;
2013 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2014 return -EIO;
cb53c626 2015 azx_init_pci(chip);
d804ad92
ML		 2016
2017 if (snd_hda_codecs_inuse(chip->bus))
2018 azx_init_chip(chip);
2019
1da177e4 2020 snd_hda_resume(chip->bus);
421a1252 2021 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2022 return 0;
2023}
2024#endif /* CONFIG_PM */
2025
2026
0cbf0098
TI		 2027/*
2028 * reboot notifier for hang-up problem at power-down
2029 */
2030static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2031{
2032 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2033 azx_stop_chip(chip);
2034 return NOTIFY_OK;
2035}
2036
2037static void azx_notifier_register(struct azx *chip)
2038{
2039 chip->reboot_notifier.notifier_call = azx_halt;
2040 register_reboot_notifier(&chip->reboot_notifier);
2041}
2042
2043static void azx_notifier_unregister(struct azx *chip)
2044{
2045 if (chip->reboot_notifier.notifier_call)
2046 unregister_reboot_notifier(&chip->reboot_notifier);
2047}
2048
1da177e4
LT		 2049/*
2050 * destructor
2051 */
a98f90fd 2052static int azx_free(struct azx *chip)
1da177e4 2053{
4ce107b9
TI		 2054 int i;
2055
0cbf0098
TI		 2056 azx_notifier_unregister(chip);
2057
ce43fbae 2058 if (chip->initialized) {
9ad593f6 2059 azx_clear_irq_pending(chip);
07e4ca50 2060 for (i = 0; i < chip->num_streams; i++)
1da177e4 2061 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2062 azx_stop_chip(chip);
1da177e4
LT		 2063 }
2064
f000fd80 2065 if (chip->irq >= 0)
1da177e4 2066 free_irq(chip->irq, (void*)chip);
68e7fffc 2067 if (chip->msi)
30b35399 2068 pci_disable_msi(chip->pci);
f079c25a
TI		 2069 if (chip->remap_addr)
2070 iounmap(chip->remap_addr);
1da177e4 2071
4ce107b9
TI		 2072 if (chip->azx_dev) {
2073 for (i = 0; i < chip->num_streams; i++)
2074 if (chip->azx_dev[i].bdl.area)
2075 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2076 }
1da177e4
LT		 2077 if (chip->rb.area)
2078 snd_dma_free_pages(&chip->rb);
1da177e4
LT		 2079 if (chip->posbuf.area)
2080 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT		 2081 pci_release_regions(chip->pci);
2082 pci_disable_device(chip->pci);
07e4ca50 2083 kfree(chip->azx_dev);
1da177e4
LT		 2084 kfree(chip);
2085
2086 return 0;
2087}
2088
a98f90fd 2089static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2090{
2091 return azx_free(device->device_data);
2092}
2093
3372a153
TI		 2094/*
2095 * white/black-listing for position_fix
2096 */
623ec047 2097static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2098 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2099 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2100 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3372a153
TI		 2101 {}
2102};
2103
2104static int __devinit check_position_fix(struct azx *chip, int fix)
2105{
2106 const struct snd_pci_quirk *q;
2107
c673ba1c
TI		 2108 switch (fix) {
2109 case POS_FIX_LPIB:
2110 case POS_FIX_POSBUF:
2111 return fix;
2112 }
2113
2114 /* Check VIA/ATI HD Audio Controller exist */
2115 switch (chip->driver_type) {
2116 case AZX_DRIVER_VIA:
2117 case AZX_DRIVER_ATI:
0e153474
JC		 2118 chip->via_dmapos_patch = 1;
2119 /* Use link position directly, avoid any transfer problem. */
2120 return POS_FIX_LPIB;
2121 }
2122 chip->via_dmapos_patch = 0;
2123
c673ba1c
TI		 2124 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2125 if (q) {
2126 printk(KERN_INFO
2127 "hda_intel: position_fix set to %d "
2128 "for device %04x:%04x\n",
2129 q->value, q->subvendor, q->subdevice);
2130 return q->value;
3372a153 2131 }
c673ba1c 2132 return POS_FIX_AUTO;
3372a153
TI		 2133}
2134
669ba27a
TI		 2135/*
2136 * black-lists for probe_mask
2137 */
2138static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2139 /* Thinkpad often breaks the controller communication when accessing
2140 * to the non-working (or non-existing) modem codec slot.
2141 */
2142 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2143 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2144 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2145 /* broken BIOS */
2146 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2147 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2148 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2149 /* forced codec slots */
93574844 2150 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2151 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
669ba27a
TI		 2152 {}
2153};
2154
f1eaaeec
TI		 2155#define AZX_FORCE_CODEC_MASK 0x100
2156
5aba4f8e 2157static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2158{
2159 const struct snd_pci_quirk *q;
2160
f1eaaeec
TI		 2161 chip->codec_probe_mask = probe_mask[dev];
2162 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2163 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2164 if (q) {
2165 printk(KERN_INFO
2166 "hda_intel: probe_mask set to 0x%x "
2167 "for device %04x:%04x\n",
2168 q->value, q->subvendor, q->subdevice);
f1eaaeec 2169 chip->codec_probe_mask = q->value;
669ba27a
TI		 2170 }
2171 }
f1eaaeec
TI		 2172
2173 /* check forced option */
2174 if (chip->codec_probe_mask != -1 &&
2175 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2176 chip->codec_mask = chip->codec_probe_mask & 0xff;
2177 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2178 chip->codec_mask);
2179 }
669ba27a
TI		 2180}
2181
2182
1da177e4
LT		 2183/*
2184 * constructor
2185 */
a98f90fd 2186static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
5aba4f8e 2187 int dev, int driver_type,
a98f90fd 2188 struct azx **rchip)
1da177e4 2189{
a98f90fd 2190 struct azx *chip;
4ce107b9 2191 int i, err;
bcd72003 2192 unsigned short gcap;
a98f90fd 2193 static struct snd_device_ops ops = {
1da177e4
LT		 2194 .dev_free = azx_dev_free,
2195 };
2196
2197 *rchip = NULL;
bcd72003 2198
927fc866
PM		 2199 err = pci_enable_device(pci);
2200 if (err < 0)
1da177e4
LT		 2201 return err;
2202
e560d8d8 2203 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2204 if (!chip) {
1da177e4
LT		 2205 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2206 pci_disable_device(pci);
2207 return -ENOMEM;
2208 }
2209
2210 spin_lock_init(&chip->reg_lock);
62932df8 2211 mutex_init(&chip->open_mutex);
1da177e4
LT		 2212 chip->card = card;
2213 chip->pci = pci;
2214 chip->irq = -1;
07e4ca50 2215 chip->driver_type = driver_type;
134a11f0 2216 chip->msi = enable_msi;
555e219f 2217 chip->dev_index = dev;
9ad593f6 2218 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1da177e4 2219
5aba4f8e
TI		 2220 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2221 check_probe_mask(chip, dev);
3372a153 2222
27346166 2223 chip->single_cmd = single_cmd;
c74db86b 2224
5c0d7bc1
TI		 2225 if (bdl_pos_adj[dev] < 0) {
2226 switch (chip->driver_type) {
0c6341ac
TI		 2227 case AZX_DRIVER_ICH:
2228 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2229 break;
2230 default:
0c6341ac 2231 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2232 break;
2233 }
2234 }
2235
07e4ca50
TI		 2236#if BITS_PER_LONG != 64
2237 /* Fix up base address on ULI M5461 */
2238 if (chip->driver_type == AZX_DRIVER_ULI) {
2239 u16 tmp3;
2240 pci_read_config_word(pci, 0x40, &tmp3);
2241 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2242 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2243 }
2244#endif
2245
927fc866
PM		 2246 err = pci_request_regions(pci, "ICH HD audio");
2247 if (err < 0) {
1da177e4
LT		 2248 kfree(chip);
2249 pci_disable_device(pci);
2250 return err;
2251 }
2252
927fc866 2253 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 2254 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 2255 if (chip->remap_addr == NULL) {
2256 snd_printk(KERN_ERR SFX "ioremap error\n");
2257 err = -ENXIO;
2258 goto errout;
2259 }
2260
68e7fffc
TI		 2261 if (chip->msi)
2262 if (pci_enable_msi(pci) < 0)
2263 chip->msi = 0;
7376d013 2264
68e7fffc 2265 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT		 2266 err = -EBUSY;
2267 goto errout;
2268 }
1da177e4
LT		 2269
2270 pci_set_master(pci);
2271 synchronize_irq(chip->irq);
2272
bcd72003 2273 gcap = azx_readw(chip, GCAP);
4abc1cc2 2274 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 2275
09240cf4
TI		 2276 /* ATI chips seems buggy about 64bit DMA addresses */
2277 if (chip->driver_type == AZX_DRIVER_ATI)
2278 gcap &= ~0x01;
2279
cf7aaca8 2280 /* allow 64bit DMA address if supported by H/W */
e930438c
YH		 2281 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2282 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 2283 else {
e930438c
YH		 2284 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2285 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 2286 }
cf7aaca8 2287
8b6ed8e7
TI		 2288 /* read number of streams from GCAP register instead of using
2289 * hardcoded value
2290 */
2291 chip->capture_streams = (gcap >> 8) & 0x0f;
2292 chip->playback_streams = (gcap >> 12) & 0x0f;
2293 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 2294 /* gcap didn't give any info, switching to old method */
2295
2296 switch (chip->driver_type) {
2297 case AZX_DRIVER_ULI:
2298 chip->playback_streams = ULI_NUM_PLAYBACK;
2299 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 2300 break;
2301 case AZX_DRIVER_ATIHDMI:
2302 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2303 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 2304 break;
c4da29ca 2305 case AZX_DRIVER_GENERIC:
bcd72003
TD		 2306 default:
2307 chip->playback_streams = ICH6_NUM_PLAYBACK;
2308 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 2309 break;
2310 }
07e4ca50 2311 }
8b6ed8e7
TI		 2312 chip->capture_index_offset = 0;
2313 chip->playback_index_offset = chip->capture_streams;
07e4ca50 2314 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 2315 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2316 GFP_KERNEL);
927fc866 2317 if (!chip->azx_dev) {
4abc1cc2 2318 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
07e4ca50
TI		 2319 goto errout;
2320 }
2321
4ce107b9
TI		 2322 for (i = 0; i < chip->num_streams; i++) {
2323 /* allocate memory for the BDL for each stream */
2324 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2325 snd_dma_pci_data(chip->pci),
2326 BDL_SIZE, &chip->azx_dev[i].bdl);
2327 if (err < 0) {
2328 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2329 goto errout;
2330 }
1da177e4 2331 }
0be3b5d3 2332 /* allocate memory for the position buffer */
d01ce99f
TI		 2333 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2334 snd_dma_pci_data(chip->pci),
2335 chip->num_streams * 8, &chip->posbuf);
2336 if (err < 0) {
0be3b5d3
TI		 2337 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2338 goto errout;
1da177e4 2339 }
1da177e4 2340 /* allocate CORB/RIRB */
d01ce99f
TI		 2341 if (!chip->single_cmd) {
2342 err = azx_alloc_cmd_io(chip);
2343 if (err < 0)
27346166 2344 goto errout;
d01ce99f 2345 }
1da177e4
LT		 2346
2347 /* initialize streams */
2348 azx_init_stream(chip);
2349
2350 /* initialize chip */
cb53c626 2351 azx_init_pci(chip);
1da177e4
LT		 2352 azx_init_chip(chip);
2353
2354 /* codec detection */
927fc866 2355 if (!chip->codec_mask) {
1da177e4
LT		 2356 snd_printk(KERN_ERR SFX "no codecs found!\n");
2357 err = -ENODEV;
2358 goto errout;
2359 }
2360
d01ce99f
TI		 2361 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2362 if (err <0) {
1da177e4
LT		 2363 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2364 goto errout;
2365 }
2366
07e4ca50 2367 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 2368 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2369 sizeof(card->shortname));
2370 snprintf(card->longname, sizeof(card->longname),
2371 "%s at 0x%lx irq %i",
2372 card->shortname, chip->addr, chip->irq);
07e4ca50 2373
1da177e4
LT		 2374 *rchip = chip;
2375 return 0;
2376
2377 errout:
2378 azx_free(chip);
2379 return err;
2380}
2381
cb53c626
TI		 2382static void power_down_all_codecs(struct azx *chip)
2383{
2384#ifdef CONFIG_SND_HDA_POWER_SAVE
2385 /* The codecs were powered up in snd_hda_codec_new().
2386 * Now all initialization done, so turn them down if possible
2387 */
2388 struct hda_codec *codec;
2389 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2390 snd_hda_power_down(codec);
2391 }
2392#endif
2393}
2394
d01ce99f
TI		 2395static int __devinit azx_probe(struct pci_dev *pci,
2396 const struct pci_device_id *pci_id)
1da177e4 2397{
5aba4f8e 2398 static int dev;
a98f90fd
TI		 2399 struct snd_card *card;
2400 struct azx *chip;
927fc866 2401 int err;
1da177e4 2402
5aba4f8e
TI		 2403 if (dev >= SNDRV_CARDS)
2404 return -ENODEV;
2405 if (!enable[dev]) {
2406 dev++;
2407 return -ENOENT;
2408 }
2409
e58de7ba
TI		 2410 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2411 if (err < 0) {
1da177e4 2412 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 2413 return err;
1da177e4
LT		 2414 }
2415
5aba4f8e 2416 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2417 if (err < 0)
2418 goto out_free;
421a1252 2419 card->private_data = chip;
1da177e4 2420
1da177e4 2421 /* create codec instances */
f1eaaeec 2422 err = azx_codec_create(chip, model[dev], probe_only[dev]);
41dda0fd
WF		 2423 if (err < 0)
2424 goto out_free;
1da177e4
LT		 2425
2426 /* create PCM streams */
176d5335 2427 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 2428 if (err < 0)
2429 goto out_free;
1da177e4
LT		 2430
2431 /* create mixer controls */
d01ce99f 2432 err = azx_mixer_create(chip);
41dda0fd
WF		 2433 if (err < 0)
2434 goto out_free;
1da177e4 2435
1da177e4
LT		 2436 snd_card_set_dev(card, &pci->dev);
2437
d01ce99f 2438 err = snd_card_register(card);
41dda0fd
WF		 2439 if (err < 0)
2440 goto out_free;
1da177e4
LT		 2441
2442 pci_set_drvdata(pci, card);
cb53c626
TI		 2443 chip->running = 1;
2444 power_down_all_codecs(chip);
0cbf0098 2445 azx_notifier_register(chip);
1da177e4 2446
e25bcdba 2447 dev++;
1da177e4 2448 return err;
41dda0fd
WF		 2449out_free:
2450 snd_card_free(card);
2451 return err;
1da177e4
LT		 2452}
2453
2454static void __devexit azx_remove(struct pci_dev *pci)
2455{
2456 snd_card_free(pci_get_drvdata(pci));
2457 pci_set_drvdata(pci, NULL);
2458}
2459
2460/* PCI IDs */
f40b6890 2461static struct pci_device_id azx_ids[] = {
87218e9c
TI		 2462 /* ICH 6..10 */
2463 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2464 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2465 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2466 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
abbc9d1b 2467 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2468 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2469 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2470 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2471 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
b29c2360
SH		 2472 /* PCH */
2473 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2474 /* SCH */
2475 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2476 /* ATI SB 450/600 */
2477 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2478 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2479 /* ATI HDMI */
2480 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2481 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2482 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
9e6dd47b 2483 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
87218e9c
TI		 2484 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2485 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2486 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2487 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2488 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2489 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2490 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2491 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2492 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2493 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2494 /* VIA VT8251/VT8237A */
2495 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2496 /* SIS966 */
2497 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2498 /* ULI M5461 */
2499 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2500 /* NVIDIA MCP */
2501 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2502 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2503 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2504 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2505 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2506 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2507 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2508 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2509 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2510 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2511 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2512 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2513 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2514 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2515 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2516 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2517 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2518 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
bedfcebb 2519 { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2520 { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2521 { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2522 { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
f269002e
KY		 2523 /* Teradici */
2524 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
4e01f54b 2525 /* Creative X-Fi (CA0110-IBG) */
313f6e2d
TI		 2526#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2527 /* the following entry conflicts with snd-ctxfi driver,
2528 * as ctxfi driver mutates from HD-audio to native mode with
2529 * a special command sequence.
2530 */
4e01f54b
TI		 2531 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2532 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2533 .class_mask = 0xffffff,
2534 .driver_data = AZX_DRIVER_GENERIC },
313f6e2d
TI		 2535#else
2536 /* this entry seems still valid -- i.e. without emu20kx chip */
2537 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2538#endif
c4da29ca
YL		 2539 /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2540 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2541 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2542 .class_mask = 0xffffff,
2543 .driver_data = AZX_DRIVER_GENERIC },
1da177e4
LT		 2544 { 0, }
2545};
2546MODULE_DEVICE_TABLE(pci, azx_ids);
2547
2548/* pci_driver definition */
2549static struct pci_driver driver = {
2550 .name = "HDA Intel",
2551 .id_table = azx_ids,
2552 .probe = azx_probe,
2553 .remove = __devexit_p(azx_remove),
421a1252
TI		 2554#ifdef CONFIG_PM
2555 .suspend = azx_suspend,
2556 .resume = azx_resume,
2557#endif
1da177e4
LT		 2558};
2559
2560static int __init alsa_card_azx_init(void)
2561{
01d25d46 2562 return pci_register_driver(&driver);
1da177e4
LT		 2563}
2564
2565static void __exit alsa_card_azx_exit(void)
2566{
2567 pci_unregister_driver(&driver);
2568}
2569
2570module_init(alsa_card_azx_init)
2571module_exit(alsa_card_azx_exit)
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