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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * | |
d01ce99f TI |
3 | * hda_intel.c - Implementation of primary alsa driver code base |
4 | * for Intel HD Audio. | |
1da177e4 LT |
5 | * |
6 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | |
7 | * | |
8 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
9 | * PeiSen Hou <pshou@realtek.com.tw> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the Free | |
13 | * Software Foundation; either version 2 of the License, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
19 | * more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along with | |
22 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
23 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
24 | * | |
25 | * CONTACTS: | |
26 | * | |
27 | * Matt Jared matt.jared@intel.com | |
28 | * Andy Kopp andy.kopp@intel.com | |
29 | * Dan Kogan dan.d.kogan@intel.com | |
30 | * | |
31 | * CHANGES: | |
32 | * | |
33 | * 2004.12.01 Major rewrite by tiwai, merged the work of pshou | |
34 | * | |
35 | */ | |
36 | ||
1da177e4 LT |
37 | #include <linux/delay.h> |
38 | #include <linux/interrupt.h> | |
362775e2 | 39 | #include <linux/kernel.h> |
1da177e4 | 40 | #include <linux/module.h> |
24982c5f | 41 | #include <linux/dma-mapping.h> |
1da177e4 LT |
42 | #include <linux/moduleparam.h> |
43 | #include <linux/init.h> | |
44 | #include <linux/slab.h> | |
45 | #include <linux/pci.h> | |
62932df8 | 46 | #include <linux/mutex.h> |
0cbf0098 | 47 | #include <linux/reboot.h> |
27fe48d9 | 48 | #include <linux/io.h> |
b8dfc462 | 49 | #include <linux/pm_runtime.h> |
5d890f59 PLB |
50 | #include <linux/clocksource.h> |
51 | #include <linux/time.h> | |
f4c482a4 | 52 | #include <linux/completion.h> |
5d890f59 | 53 | |
27fe48d9 TI |
54 | #ifdef CONFIG_X86 |
55 | /* for snoop control */ | |
56 | #include <asm/pgtable.h> | |
57 | #include <asm/cacheflush.h> | |
58 | #endif | |
1da177e4 LT |
59 | #include <sound/core.h> |
60 | #include <sound/initval.h> | |
9121947d | 61 | #include <linux/vgaarb.h> |
a82d51ed | 62 | #include <linux/vga_switcheroo.h> |
4918cdab | 63 | #include <linux/firmware.h> |
1da177e4 | 64 | #include "hda_codec.h" |
99a2008d | 65 | #include "hda_i915.h" |
1da177e4 LT |
66 | |
67 | ||
5aba4f8e TI |
68 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; |
69 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; | |
a67ff6a5 | 70 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; |
5aba4f8e | 71 | static char *model[SNDRV_CARDS]; |
1dac6695 | 72 | static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
5c0d7bc1 | 73 | static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
5aba4f8e | 74 | static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
d4d9cd03 | 75 | static int probe_only[SNDRV_CARDS]; |
26a6cb6c | 76 | static int jackpoll_ms[SNDRV_CARDS]; |
a67ff6a5 | 77 | static bool single_cmd; |
71623855 | 78 | static int enable_msi = -1; |
4ea6fbc8 TI |
79 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
80 | static char *patch[SNDRV_CARDS]; | |
81 | #endif | |
2dca0bba | 82 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
0920c9b4 | 83 | static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = |
2dca0bba JK |
84 | CONFIG_SND_HDA_INPUT_BEEP_MODE}; |
85 | #endif | |
1da177e4 | 86 | |
5aba4f8e | 87 | module_param_array(index, int, NULL, 0444); |
1da177e4 | 88 | MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); |
5aba4f8e | 89 | module_param_array(id, charp, NULL, 0444); |
1da177e4 | 90 | MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); |
5aba4f8e TI |
91 | module_param_array(enable, bool, NULL, 0444); |
92 | MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); | |
93 | module_param_array(model, charp, NULL, 0444); | |
1da177e4 | 94 | MODULE_PARM_DESC(model, "Use the given board model."); |
5aba4f8e | 95 | module_param_array(position_fix, int, NULL, 0444); |
4cb36310 | 96 | MODULE_PARM_DESC(position_fix, "DMA pointer read method." |
1dac6695 | 97 | "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); |
555e219f TI |
98 | module_param_array(bdl_pos_adj, int, NULL, 0644); |
99 | MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); | |
5aba4f8e | 100 | module_param_array(probe_mask, int, NULL, 0444); |
606ad75f | 101 | MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); |
079e683e | 102 | module_param_array(probe_only, int, NULL, 0444); |
d4d9cd03 | 103 | MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); |
26a6cb6c DH |
104 | module_param_array(jackpoll_ms, int, NULL, 0444); |
105 | MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); | |
27346166 | 106 | module_param(single_cmd, bool, 0444); |
d01ce99f TI |
107 | MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " |
108 | "(for debugging only)."); | |
ac9ef6cf | 109 | module_param(enable_msi, bint, 0444); |
134a11f0 | 110 | MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); |
4ea6fbc8 TI |
111 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
112 | module_param_array(patch, charp, NULL, 0444); | |
113 | MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); | |
114 | #endif | |
2dca0bba | 115 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
0920c9b4 | 116 | module_param_array(beep_mode, bool, NULL, 0444); |
2dca0bba | 117 | MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " |
0920c9b4 | 118 | "(0=off, 1=on) (default=1)."); |
2dca0bba | 119 | #endif |
606ad75f | 120 | |
83012a7c | 121 | #ifdef CONFIG_PM |
65fcd41d TI |
122 | static int param_set_xint(const char *val, const struct kernel_param *kp); |
123 | static struct kernel_param_ops param_ops_xint = { | |
124 | .set = param_set_xint, | |
125 | .get = param_get_int, | |
126 | }; | |
127 | #define param_check_xint param_check_int | |
128 | ||
fee2fba3 | 129 | static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; |
65fcd41d | 130 | module_param(power_save, xint, 0644); |
fee2fba3 TI |
131 | MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " |
132 | "(in second, 0 = disable)."); | |
1da177e4 | 133 | |
dee1b66c TI |
134 | /* reset the HD-audio controller in power save mode. |
135 | * this may give more power-saving, but will take longer time to | |
136 | * wake up. | |
137 | */ | |
8fc24426 TI |
138 | static bool power_save_controller = 1; |
139 | module_param(power_save_controller, bool, 0644); | |
dee1b66c | 140 | MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); |
83012a7c | 141 | #endif /* CONFIG_PM */ |
dee1b66c | 142 | |
7bfe059e TI |
143 | static int align_buffer_size = -1; |
144 | module_param(align_buffer_size, bint, 0644); | |
2ae66c26 PLB |
145 | MODULE_PARM_DESC(align_buffer_size, |
146 | "Force buffer and period sizes to be multiple of 128 bytes."); | |
147 | ||
27fe48d9 TI |
148 | #ifdef CONFIG_X86 |
149 | static bool hda_snoop = true; | |
150 | module_param_named(snoop, hda_snoop, bool, 0444); | |
151 | MODULE_PARM_DESC(snoop, "Enable/disable snooping"); | |
152 | #define azx_snoop(chip) (chip)->snoop | |
153 | #else | |
154 | #define hda_snoop true | |
155 | #define azx_snoop(chip) true | |
156 | #endif | |
157 | ||
158 | ||
1da177e4 LT |
159 | MODULE_LICENSE("GPL"); |
160 | MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," | |
161 | "{Intel, ICH6M}," | |
2f1b3818 | 162 | "{Intel, ICH7}," |
f5d40b30 | 163 | "{Intel, ESB2}," |
d2981393 | 164 | "{Intel, ICH8}," |
f9cc8a8b | 165 | "{Intel, ICH9}," |
c34f5a04 | 166 | "{Intel, ICH10}," |
b29c2360 | 167 | "{Intel, PCH}," |
d2f2fcd2 | 168 | "{Intel, CPT}," |
d2edeb7c | 169 | "{Intel, PPT}," |
8bc039a1 | 170 | "{Intel, LPT}," |
144dad99 | 171 | "{Intel, LPT_LP}," |
e926f2c8 | 172 | "{Intel, HPT}," |
cea310e8 | 173 | "{Intel, PBG}," |
4979bca9 | 174 | "{Intel, SCH}," |
fc20a562 | 175 | "{ATI, SB450}," |
89be83f8 | 176 | "{ATI, SB600}," |
778b6e1b | 177 | "{ATI, RS600}," |
5b15c95f | 178 | "{ATI, RS690}," |
e6db1119 WL |
179 | "{ATI, RS780}," |
180 | "{ATI, R600}," | |
2797f724 HRK |
181 | "{ATI, RV630}," |
182 | "{ATI, RV610}," | |
27da1834 WL |
183 | "{ATI, RV670}," |
184 | "{ATI, RV635}," | |
185 | "{ATI, RV620}," | |
186 | "{ATI, RV770}," | |
fc20a562 | 187 | "{VIA, VT8251}," |
47672310 | 188 | "{VIA, VT8237A}," |
07e4ca50 TI |
189 | "{SiS, SIS966}," |
190 | "{ULI, M5461}}"); | |
1da177e4 LT |
191 | MODULE_DESCRIPTION("Intel HDA driver"); |
192 | ||
4abc1cc2 TI |
193 | #ifdef CONFIG_SND_VERBOSE_PRINTK |
194 | #define SFX /* nop */ | |
195 | #else | |
445a51b3 | 196 | #define SFX "hda-intel " |
4abc1cc2 | 197 | #endif |
cb53c626 | 198 | |
a82d51ed TI |
199 | #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) |
200 | #ifdef CONFIG_SND_HDA_CODEC_HDMI | |
201 | #define SUPPORT_VGA_SWITCHEROO | |
202 | #endif | |
203 | #endif | |
204 | ||
205 | ||
1da177e4 LT |
206 | /* |
207 | * registers | |
208 | */ | |
209 | #define ICH6_REG_GCAP 0x00 | |
b21fadb9 TI |
210 | #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */ |
211 | #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */ | |
212 | #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */ | |
213 | #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */ | |
214 | #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */ | |
1da177e4 LT |
215 | #define ICH6_REG_VMIN 0x02 |
216 | #define ICH6_REG_VMAJ 0x03 | |
217 | #define ICH6_REG_OUTPAY 0x04 | |
218 | #define ICH6_REG_INPAY 0x06 | |
219 | #define ICH6_REG_GCTL 0x08 | |
8a933ece | 220 | #define ICH6_GCTL_RESET (1 << 0) /* controller reset */ |
b21fadb9 TI |
221 | #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */ |
222 | #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ | |
1da177e4 LT |
223 | #define ICH6_REG_WAKEEN 0x0c |
224 | #define ICH6_REG_STATESTS 0x0e | |
225 | #define ICH6_REG_GSTS 0x10 | |
b21fadb9 | 226 | #define ICH6_GSTS_FSTS (1 << 1) /* flush status */ |
1da177e4 LT |
227 | #define ICH6_REG_INTCTL 0x20 |
228 | #define ICH6_REG_INTSTS 0x24 | |
e5463720 | 229 | #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */ |
8b0bd226 TI |
230 | #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */ |
231 | #define ICH6_REG_SSYNC 0x38 | |
1da177e4 LT |
232 | #define ICH6_REG_CORBLBASE 0x40 |
233 | #define ICH6_REG_CORBUBASE 0x44 | |
234 | #define ICH6_REG_CORBWP 0x48 | |
b21fadb9 TI |
235 | #define ICH6_REG_CORBRP 0x4a |
236 | #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */ | |
1da177e4 | 237 | #define ICH6_REG_CORBCTL 0x4c |
b21fadb9 TI |
238 | #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */ |
239 | #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ | |
1da177e4 | 240 | #define ICH6_REG_CORBSTS 0x4d |
b21fadb9 | 241 | #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */ |
1da177e4 LT |
242 | #define ICH6_REG_CORBSIZE 0x4e |
243 | ||
244 | #define ICH6_REG_RIRBLBASE 0x50 | |
245 | #define ICH6_REG_RIRBUBASE 0x54 | |
246 | #define ICH6_REG_RIRBWP 0x58 | |
b21fadb9 | 247 | #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */ |
1da177e4 LT |
248 | #define ICH6_REG_RINTCNT 0x5a |
249 | #define ICH6_REG_RIRBCTL 0x5c | |
b21fadb9 TI |
250 | #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ |
251 | #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */ | |
252 | #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ | |
1da177e4 | 253 | #define ICH6_REG_RIRBSTS 0x5d |
b21fadb9 TI |
254 | #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */ |
255 | #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */ | |
1da177e4 LT |
256 | #define ICH6_REG_RIRBSIZE 0x5e |
257 | ||
258 | #define ICH6_REG_IC 0x60 | |
259 | #define ICH6_REG_IR 0x64 | |
260 | #define ICH6_REG_IRS 0x68 | |
261 | #define ICH6_IRS_VALID (1<<1) | |
262 | #define ICH6_IRS_BUSY (1<<0) | |
263 | ||
264 | #define ICH6_REG_DPLBASE 0x70 | |
265 | #define ICH6_REG_DPUBASE 0x74 | |
266 | #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ | |
267 | ||
268 | /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ | |
269 | enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; | |
270 | ||
271 | /* stream register offsets from stream base */ | |
272 | #define ICH6_REG_SD_CTL 0x00 | |
273 | #define ICH6_REG_SD_STS 0x03 | |
274 | #define ICH6_REG_SD_LPIB 0x04 | |
275 | #define ICH6_REG_SD_CBL 0x08 | |
276 | #define ICH6_REG_SD_LVI 0x0c | |
277 | #define ICH6_REG_SD_FIFOW 0x0e | |
278 | #define ICH6_REG_SD_FIFOSIZE 0x10 | |
279 | #define ICH6_REG_SD_FORMAT 0x12 | |
280 | #define ICH6_REG_SD_BDLPL 0x18 | |
281 | #define ICH6_REG_SD_BDLPU 0x1c | |
282 | ||
283 | /* PCI space */ | |
284 | #define ICH6_PCIREG_TCSEL 0x44 | |
285 | ||
286 | /* | |
287 | * other constants | |
288 | */ | |
289 | ||
290 | /* max number of SDs */ | |
07e4ca50 | 291 | /* ICH, ATI and VIA have 4 playback and 4 capture */ |
07e4ca50 | 292 | #define ICH6_NUM_CAPTURE 4 |
07e4ca50 TI |
293 | #define ICH6_NUM_PLAYBACK 4 |
294 | ||
295 | /* ULI has 6 playback and 5 capture */ | |
07e4ca50 | 296 | #define ULI_NUM_CAPTURE 5 |
07e4ca50 TI |
297 | #define ULI_NUM_PLAYBACK 6 |
298 | ||
778b6e1b | 299 | /* ATI HDMI has 1 playback and 0 capture */ |
778b6e1b | 300 | #define ATIHDMI_NUM_CAPTURE 0 |
778b6e1b FK |
301 | #define ATIHDMI_NUM_PLAYBACK 1 |
302 | ||
f269002e KY |
303 | /* TERA has 4 playback and 3 capture */ |
304 | #define TERA_NUM_CAPTURE 3 | |
305 | #define TERA_NUM_PLAYBACK 4 | |
306 | ||
07e4ca50 TI |
307 | /* this number is statically defined for simplicity */ |
308 | #define MAX_AZX_DEV 16 | |
309 | ||
1da177e4 | 310 | /* max number of fragments - we may use more if allocating more pages for BDL */ |
4ce107b9 TI |
311 | #define BDL_SIZE 4096 |
312 | #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) | |
313 | #define AZX_MAX_FRAG 32 | |
1da177e4 LT |
314 | /* max buffer size - no h/w limit, you can increase as you like */ |
315 | #define AZX_MAX_BUF_SIZE (1024*1024*1024) | |
1da177e4 LT |
316 | |
317 | /* RIRB int mask: overrun[2], response[0] */ | |
318 | #define RIRB_INT_RESPONSE 0x01 | |
319 | #define RIRB_INT_OVERRUN 0x04 | |
320 | #define RIRB_INT_MASK 0x05 | |
321 | ||
2f5983f2 | 322 | /* STATESTS int mask: S3,SD2,SD1,SD0 */ |
7445dfc1 WN |
323 | #define AZX_MAX_CODECS 8 |
324 | #define AZX_DEFAULT_CODECS 4 | |
deadff16 | 325 | #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) |
1da177e4 LT |
326 | |
327 | /* SD_CTL bits */ | |
328 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ | |
329 | #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ | |
850f0e52 TI |
330 | #define SD_CTL_STRIPE (3 << 16) /* stripe control */ |
331 | #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ | |
332 | #define SD_CTL_DIR (1 << 19) /* bi-directional stream */ | |
1da177e4 LT |
333 | #define SD_CTL_STREAM_TAG_MASK (0xf << 20) |
334 | #define SD_CTL_STREAM_TAG_SHIFT 20 | |
335 | ||
336 | /* SD_CTL and SD_STS */ | |
337 | #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ | |
338 | #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ | |
339 | #define SD_INT_COMPLETE 0x04 /* completion interrupt */ | |
d01ce99f TI |
340 | #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ |
341 | SD_INT_COMPLETE) | |
1da177e4 LT |
342 | |
343 | /* SD_STS */ | |
344 | #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ | |
345 | ||
346 | /* INTCTL and INTSTS */ | |
d01ce99f TI |
347 | #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ |
348 | #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ | |
349 | #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ | |
1da177e4 | 350 | |
1da177e4 LT |
351 | /* below are so far hardcoded - should read registers in future */ |
352 | #define ICH6_MAX_CORB_ENTRIES 256 | |
353 | #define ICH6_MAX_RIRB_ENTRIES 256 | |
354 | ||
c74db86b TI |
355 | /* position fix mode */ |
356 | enum { | |
0be3b5d3 | 357 | POS_FIX_AUTO, |
d2e1c973 | 358 | POS_FIX_LPIB, |
0be3b5d3 | 359 | POS_FIX_POSBUF, |
4cb36310 | 360 | POS_FIX_VIACOMBO, |
a6f2fd55 | 361 | POS_FIX_COMBO, |
c74db86b | 362 | }; |
1da177e4 | 363 | |
f5d40b30 | 364 | /* Defines for ATI HD Audio support in SB450 south bridge */ |
f5d40b30 FL |
365 | #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 |
366 | #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 | |
367 | ||
da3fca21 V |
368 | /* Defines for Nvidia HDA support */ |
369 | #define NVIDIA_HDA_TRANSREG_ADDR 0x4e | |
370 | #define NVIDIA_HDA_ENABLE_COHBITS 0x0f | |
320dcc30 PC |
371 | #define NVIDIA_HDA_ISTRM_COH 0x4d |
372 | #define NVIDIA_HDA_OSTRM_COH 0x4c | |
373 | #define NVIDIA_HDA_ENABLE_COHBIT 0x01 | |
f5d40b30 | 374 | |
90a5ad52 TI |
375 | /* Defines for Intel SCH HDA snoop control */ |
376 | #define INTEL_SCH_HDA_DEVC 0x78 | |
377 | #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) | |
378 | ||
0e153474 JC |
379 | /* Define IN stream 0 FIFO size offset in VIA controller */ |
380 | #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 | |
381 | /* Define VIA HD Audio Device ID*/ | |
382 | #define VIA_HDAC_DEVICE_ID 0x3288 | |
383 | ||
c4da29ca YL |
384 | /* HD Audio class code */ |
385 | #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 | |
90a5ad52 | 386 | |
1da177e4 LT |
387 | /* |
388 | */ | |
389 | ||
a98f90fd | 390 | struct azx_dev { |
4ce107b9 | 391 | struct snd_dma_buffer bdl; /* BDL buffer */ |
d01ce99f | 392 | u32 *posbuf; /* position buffer pointer */ |
1da177e4 | 393 | |
d01ce99f | 394 | unsigned int bufsize; /* size of the play buffer in bytes */ |
9ad593f6 | 395 | unsigned int period_bytes; /* size of the period in bytes */ |
d01ce99f TI |
396 | unsigned int frags; /* number for period in the play buffer */ |
397 | unsigned int fifo_size; /* FIFO size */ | |
e5463720 JK |
398 | unsigned long start_wallclk; /* start + minimum wallclk */ |
399 | unsigned long period_wallclk; /* wallclk for period */ | |
1da177e4 | 400 | |
d01ce99f | 401 | void __iomem *sd_addr; /* stream descriptor pointer */ |
1da177e4 | 402 | |
d01ce99f | 403 | u32 sd_int_sta_mask; /* stream int status mask */ |
1da177e4 LT |
404 | |
405 | /* pcm support */ | |
d01ce99f TI |
406 | struct snd_pcm_substream *substream; /* assigned substream, |
407 | * set in PCM open | |
408 | */ | |
409 | unsigned int format_val; /* format value to be set in the | |
410 | * controller and the codec | |
411 | */ | |
1da177e4 LT |
412 | unsigned char stream_tag; /* assigned stream */ |
413 | unsigned char index; /* stream index */ | |
d5cf9911 | 414 | int assigned_key; /* last device# key assigned to */ |
1da177e4 | 415 | |
927fc866 PM |
416 | unsigned int opened :1; |
417 | unsigned int running :1; | |
675f25d4 | 418 | unsigned int irq_pending :1; |
eb49faa6 TI |
419 | unsigned int prepared:1; |
420 | unsigned int locked:1; | |
0e153474 JC |
421 | /* |
422 | * For VIA: | |
423 | * A flag to ensure DMA position is 0 | |
424 | * when link position is not greater than FIFO size | |
425 | */ | |
426 | unsigned int insufficient :1; | |
27fe48d9 | 427 | unsigned int wc_marked:1; |
915bf29e | 428 | unsigned int no_period_wakeup:1; |
5d890f59 PLB |
429 | |
430 | struct timecounter azx_tc; | |
431 | struct cyclecounter azx_cc; | |
eb49faa6 TI |
432 | |
433 | #ifdef CONFIG_SND_HDA_DSP_LOADER | |
434 | struct mutex dsp_mutex; | |
435 | #endif | |
1da177e4 LT |
436 | }; |
437 | ||
eb49faa6 TI |
438 | /* DSP lock helpers */ |
439 | #ifdef CONFIG_SND_HDA_DSP_LOADER | |
440 | #define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) | |
441 | #define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) | |
442 | #define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) | |
443 | #define dsp_is_locked(dev) ((dev)->locked) | |
444 | #else | |
445 | #define dsp_lock_init(dev) do {} while (0) | |
446 | #define dsp_lock(dev) do {} while (0) | |
447 | #define dsp_unlock(dev) do {} while (0) | |
448 | #define dsp_is_locked(dev) 0 | |
449 | #endif | |
450 | ||
1da177e4 | 451 | /* CORB/RIRB */ |
a98f90fd | 452 | struct azx_rb { |
1da177e4 LT |
453 | u32 *buf; /* CORB/RIRB buffer |
454 | * Each CORB entry is 4byte, RIRB is 8byte | |
455 | */ | |
456 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | |
457 | /* for RIRB */ | |
458 | unsigned short rp, wp; /* read/write pointers */ | |
deadff16 WF |
459 | int cmds[AZX_MAX_CODECS]; /* number of pending requests */ |
460 | u32 res[AZX_MAX_CODECS]; /* last read value */ | |
1da177e4 LT |
461 | }; |
462 | ||
01b65bfb TI |
463 | struct azx_pcm { |
464 | struct azx *chip; | |
465 | struct snd_pcm *pcm; | |
466 | struct hda_codec *codec; | |
467 | struct hda_pcm_stream *hinfo[2]; | |
468 | struct list_head list; | |
469 | }; | |
470 | ||
a98f90fd TI |
471 | struct azx { |
472 | struct snd_card *card; | |
1da177e4 | 473 | struct pci_dev *pci; |
555e219f | 474 | int dev_index; |
1da177e4 | 475 | |
07e4ca50 TI |
476 | /* chip type specific */ |
477 | int driver_type; | |
9477c58e | 478 | unsigned int driver_caps; |
07e4ca50 TI |
479 | int playback_streams; |
480 | int playback_index_offset; | |
481 | int capture_streams; | |
482 | int capture_index_offset; | |
483 | int num_streams; | |
484 | ||
1da177e4 LT |
485 | /* pci resources */ |
486 | unsigned long addr; | |
487 | void __iomem *remap_addr; | |
488 | int irq; | |
489 | ||
490 | /* locks */ | |
491 | spinlock_t reg_lock; | |
62932df8 | 492 | struct mutex open_mutex; |
f4c482a4 | 493 | struct completion probe_wait; |
1da177e4 | 494 | |
07e4ca50 | 495 | /* streams (x num_streams) */ |
a98f90fd | 496 | struct azx_dev *azx_dev; |
1da177e4 LT |
497 | |
498 | /* PCM */ | |
01b65bfb | 499 | struct list_head pcm_list; /* azx_pcm list */ |
1da177e4 LT |
500 | |
501 | /* HD codec */ | |
502 | unsigned short codec_mask; | |
f1eaaeec | 503 | int codec_probe_mask; /* copied from probe_mask option */ |
1da177e4 | 504 | struct hda_bus *bus; |
2dca0bba | 505 | unsigned int beep_mode; |
1da177e4 LT |
506 | |
507 | /* CORB/RIRB */ | |
a98f90fd TI |
508 | struct azx_rb corb; |
509 | struct azx_rb rirb; | |
1da177e4 | 510 | |
4ce107b9 | 511 | /* CORB/RIRB and position buffers */ |
1da177e4 LT |
512 | struct snd_dma_buffer rb; |
513 | struct snd_dma_buffer posbuf; | |
c74db86b | 514 | |
4918cdab TI |
515 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
516 | const struct firmware *fw; | |
517 | #endif | |
518 | ||
c74db86b | 519 | /* flags */ |
beaffc39 | 520 | int position_fix[2]; /* for both playback/capture streams */ |
1eb6dc7d | 521 | int poll_count; |
cb53c626 | 522 | unsigned int running :1; |
927fc866 PM |
523 | unsigned int initialized :1; |
524 | unsigned int single_cmd :1; | |
525 | unsigned int polling_mode :1; | |
68e7fffc | 526 | unsigned int msi :1; |
a6a950a8 | 527 | unsigned int irq_pending_warned :1; |
6ce4a3bc | 528 | unsigned int probing :1; /* codec probing phase */ |
27fe48d9 | 529 | unsigned int snoop:1; |
52409aa6 | 530 | unsigned int align_buffer_size:1; |
a82d51ed TI |
531 | unsigned int region_requested:1; |
532 | ||
533 | /* VGA-switcheroo setup */ | |
534 | unsigned int use_vga_switcheroo:1; | |
128960a9 | 535 | unsigned int vga_switcheroo_registered:1; |
a82d51ed TI |
536 | unsigned int init_failed:1; /* delayed init failed */ |
537 | unsigned int disabled:1; /* disabled by VGA-switcher */ | |
43bbb6cc TI |
538 | |
539 | /* for debugging */ | |
feb27340 | 540 | unsigned int last_cmd[AZX_MAX_CODECS]; |
9ad593f6 TI |
541 | |
542 | /* for pending irqs */ | |
543 | struct work_struct irq_pending_work; | |
0cbf0098 | 544 | |
99a2008d WX |
545 | #ifdef CONFIG_SND_HDA_I915 |
546 | struct work_struct probe_work; | |
547 | #endif | |
548 | ||
0cbf0098 TI |
549 | /* reboot notifier (for mysterious hangup problem at power-down) */ |
550 | struct notifier_block reboot_notifier; | |
65fcd41d TI |
551 | |
552 | /* card list (for power_save trigger) */ | |
553 | struct list_head list; | |
eb49faa6 TI |
554 | |
555 | #ifdef CONFIG_SND_HDA_DSP_LOADER | |
556 | struct azx_dev saved_azx_dev; | |
557 | #endif | |
246efa4a DA |
558 | |
559 | /* secondary power domain for hdmi audio under vga device */ | |
560 | struct dev_pm_domain hdmi_pm_domain; | |
1da177e4 LT |
561 | }; |
562 | ||
1a8506d4 TI |
563 | #define CREATE_TRACE_POINTS |
564 | #include "hda_intel_trace.h" | |
565 | ||
07e4ca50 TI |
566 | /* driver types */ |
567 | enum { | |
568 | AZX_DRIVER_ICH, | |
32679f95 | 569 | AZX_DRIVER_PCH, |
4979bca9 | 570 | AZX_DRIVER_SCH, |
07e4ca50 | 571 | AZX_DRIVER_ATI, |
778b6e1b | 572 | AZX_DRIVER_ATIHDMI, |
1815b34a | 573 | AZX_DRIVER_ATIHDMI_NS, |
07e4ca50 TI |
574 | AZX_DRIVER_VIA, |
575 | AZX_DRIVER_SIS, | |
576 | AZX_DRIVER_ULI, | |
da3fca21 | 577 | AZX_DRIVER_NVIDIA, |
f269002e | 578 | AZX_DRIVER_TERA, |
14d34f16 | 579 | AZX_DRIVER_CTX, |
5ae763b1 | 580 | AZX_DRIVER_CTHDA, |
c4da29ca | 581 | AZX_DRIVER_GENERIC, |
2f5983f2 | 582 | AZX_NUM_DRIVERS, /* keep this as last entry */ |
07e4ca50 TI |
583 | }; |
584 | ||
9477c58e TI |
585 | /* driver quirks (capabilities) */ |
586 | /* bits 0-7 are used for indicating driver type */ | |
587 | #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */ | |
588 | #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */ | |
589 | #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */ | |
590 | #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */ | |
591 | #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */ | |
592 | #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */ | |
593 | #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */ | |
594 | #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */ | |
595 | #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */ | |
596 | #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */ | |
597 | #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */ | |
598 | #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */ | |
8b0bd226 | 599 | #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */ |
2ae66c26 | 600 | #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */ |
7bfe059e | 601 | #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */ |
5ae763b1 | 602 | #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */ |
90accc58 | 603 | #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */ |
2ea3c6a2 | 604 | #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */ |
99a2008d | 605 | #define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 power well support */ |
2ea3c6a2 TI |
606 | |
607 | /* quirks for Intel PCH */ | |
d7dab4db | 608 | #define AZX_DCAPS_INTEL_PCH_NOPM \ |
2ea3c6a2 | 609 | (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \ |
d7dab4db TI |
610 | AZX_DCAPS_COUNT_LPIB_DELAY) |
611 | ||
612 | #define AZX_DCAPS_INTEL_PCH \ | |
613 | (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME) | |
9477c58e TI |
614 | |
615 | /* quirks for ATI SB / AMD Hudson */ | |
616 | #define AZX_DCAPS_PRESET_ATI_SB \ | |
617 | (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \ | |
618 | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) | |
619 | ||
620 | /* quirks for ATI/AMD HDMI */ | |
621 | #define AZX_DCAPS_PRESET_ATI_HDMI \ | |
622 | (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) | |
623 | ||
624 | /* quirks for Nvidia */ | |
625 | #define AZX_DCAPS_PRESET_NVIDIA \ | |
7bfe059e | 626 | (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\ |
49d9e77e | 627 | AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT) |
9477c58e | 628 | |
5ae763b1 TI |
629 | #define AZX_DCAPS_PRESET_CTHDA \ |
630 | (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY) | |
631 | ||
a82d51ed TI |
632 | /* |
633 | * VGA-switcher support | |
634 | */ | |
635 | #ifdef SUPPORT_VGA_SWITCHEROO | |
5cb543db TI |
636 | #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) |
637 | #else | |
638 | #define use_vga_switcheroo(chip) 0 | |
639 | #endif | |
640 | ||
48c8b0eb | 641 | static char *driver_short_names[] = { |
07e4ca50 | 642 | [AZX_DRIVER_ICH] = "HDA Intel", |
32679f95 | 643 | [AZX_DRIVER_PCH] = "HDA Intel PCH", |
4979bca9 | 644 | [AZX_DRIVER_SCH] = "HDA Intel MID", |
07e4ca50 | 645 | [AZX_DRIVER_ATI] = "HDA ATI SB", |
778b6e1b | 646 | [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", |
1815b34a | 647 | [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", |
07e4ca50 TI |
648 | [AZX_DRIVER_VIA] = "HDA VIA VT82xx", |
649 | [AZX_DRIVER_SIS] = "HDA SIS966", | |
da3fca21 V |
650 | [AZX_DRIVER_ULI] = "HDA ULI M5461", |
651 | [AZX_DRIVER_NVIDIA] = "HDA NVidia", | |
f269002e | 652 | [AZX_DRIVER_TERA] = "HDA Teradici", |
14d34f16 | 653 | [AZX_DRIVER_CTX] = "HDA Creative", |
5ae763b1 | 654 | [AZX_DRIVER_CTHDA] = "HDA Creative", |
c4da29ca | 655 | [AZX_DRIVER_GENERIC] = "HD-Audio Generic", |
07e4ca50 TI |
656 | }; |
657 | ||
1da177e4 LT |
658 | /* |
659 | * macros for easy use | |
660 | */ | |
661 | #define azx_writel(chip,reg,value) \ | |
662 | writel(value, (chip)->remap_addr + ICH6_REG_##reg) | |
663 | #define azx_readl(chip,reg) \ | |
664 | readl((chip)->remap_addr + ICH6_REG_##reg) | |
665 | #define azx_writew(chip,reg,value) \ | |
666 | writew(value, (chip)->remap_addr + ICH6_REG_##reg) | |
667 | #define azx_readw(chip,reg) \ | |
668 | readw((chip)->remap_addr + ICH6_REG_##reg) | |
669 | #define azx_writeb(chip,reg,value) \ | |
670 | writeb(value, (chip)->remap_addr + ICH6_REG_##reg) | |
671 | #define azx_readb(chip,reg) \ | |
672 | readb((chip)->remap_addr + ICH6_REG_##reg) | |
673 | ||
674 | #define azx_sd_writel(dev,reg,value) \ | |
675 | writel(value, (dev)->sd_addr + ICH6_REG_##reg) | |
676 | #define azx_sd_readl(dev,reg) \ | |
677 | readl((dev)->sd_addr + ICH6_REG_##reg) | |
678 | #define azx_sd_writew(dev,reg,value) \ | |
679 | writew(value, (dev)->sd_addr + ICH6_REG_##reg) | |
680 | #define azx_sd_readw(dev,reg) \ | |
681 | readw((dev)->sd_addr + ICH6_REG_##reg) | |
682 | #define azx_sd_writeb(dev,reg,value) \ | |
683 | writeb(value, (dev)->sd_addr + ICH6_REG_##reg) | |
684 | #define azx_sd_readb(dev,reg) \ | |
685 | readb((dev)->sd_addr + ICH6_REG_##reg) | |
686 | ||
687 | /* for pcm support */ | |
a98f90fd | 688 | #define get_azx_dev(substream) (substream->runtime->private_data) |
1da177e4 | 689 | |
27fe48d9 | 690 | #ifdef CONFIG_X86 |
9ddf1aeb | 691 | static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) |
27fe48d9 | 692 | { |
9ddf1aeb TI |
693 | int pages; |
694 | ||
27fe48d9 TI |
695 | if (azx_snoop(chip)) |
696 | return; | |
9ddf1aeb TI |
697 | if (!dmab || !dmab->area || !dmab->bytes) |
698 | return; | |
699 | ||
700 | #ifdef CONFIG_SND_DMA_SGBUF | |
701 | if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { | |
702 | struct snd_sg_buf *sgbuf = dmab->private_data; | |
27fe48d9 | 703 | if (on) |
9ddf1aeb | 704 | set_pages_array_wc(sgbuf->page_table, sgbuf->pages); |
27fe48d9 | 705 | else |
9ddf1aeb TI |
706 | set_pages_array_wb(sgbuf->page_table, sgbuf->pages); |
707 | return; | |
27fe48d9 | 708 | } |
9ddf1aeb TI |
709 | #endif |
710 | ||
711 | pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; | |
712 | if (on) | |
713 | set_memory_wc((unsigned long)dmab->area, pages); | |
714 | else | |
715 | set_memory_wb((unsigned long)dmab->area, pages); | |
27fe48d9 TI |
716 | } |
717 | ||
718 | static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, | |
719 | bool on) | |
720 | { | |
9ddf1aeb | 721 | __mark_pages_wc(chip, buf, on); |
27fe48d9 TI |
722 | } |
723 | static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, | |
9ddf1aeb | 724 | struct snd_pcm_substream *substream, bool on) |
27fe48d9 TI |
725 | { |
726 | if (azx_dev->wc_marked != on) { | |
9ddf1aeb | 727 | __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); |
27fe48d9 TI |
728 | azx_dev->wc_marked = on; |
729 | } | |
730 | } | |
731 | #else | |
732 | /* NOP for other archs */ | |
733 | static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, | |
734 | bool on) | |
735 | { | |
736 | } | |
737 | static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, | |
9ddf1aeb | 738 | struct snd_pcm_substream *substream, bool on) |
27fe48d9 TI |
739 | { |
740 | } | |
741 | #endif | |
742 | ||
68e7fffc | 743 | static int azx_acquire_irq(struct azx *chip, int do_disconnect); |
1eb6dc7d | 744 | static int azx_send_cmd(struct hda_bus *bus, unsigned int val); |
1da177e4 LT |
745 | /* |
746 | * Interface for HD codec | |
747 | */ | |
748 | ||
1da177e4 LT |
749 | /* |
750 | * CORB / RIRB interface | |
751 | */ | |
a98f90fd | 752 | static int azx_alloc_cmd_io(struct azx *chip) |
1da177e4 LT |
753 | { |
754 | int err; | |
755 | ||
756 | /* single page (at least 4096 bytes) must suffice for both ringbuffes */ | |
d01ce99f TI |
757 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, |
758 | snd_dma_pci_data(chip->pci), | |
1da177e4 LT |
759 | PAGE_SIZE, &chip->rb); |
760 | if (err < 0) { | |
445a51b3 | 761 | snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci)); |
1da177e4 LT |
762 | return err; |
763 | } | |
27fe48d9 | 764 | mark_pages_wc(chip, &chip->rb, true); |
1da177e4 LT |
765 | return 0; |
766 | } | |
767 | ||
a98f90fd | 768 | static void azx_init_cmd_io(struct azx *chip) |
1da177e4 | 769 | { |
cdb1fbf2 | 770 | spin_lock_irq(&chip->reg_lock); |
1da177e4 LT |
771 | /* CORB set up */ |
772 | chip->corb.addr = chip->rb.addr; | |
773 | chip->corb.buf = (u32 *)chip->rb.area; | |
774 | azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); | |
766979e0 | 775 | azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); |
1da177e4 | 776 | |
07e4ca50 TI |
777 | /* set the corb size to 256 entries (ULI requires explicitly) */ |
778 | azx_writeb(chip, CORBSIZE, 0x02); | |
1da177e4 LT |
779 | /* set the corb write pointer to 0 */ |
780 | azx_writew(chip, CORBWP, 0); | |
781 | /* reset the corb hw read pointer */ | |
b21fadb9 | 782 | azx_writew(chip, CORBRP, ICH6_CORBRP_RST); |
1da177e4 | 783 | /* enable corb dma */ |
b21fadb9 | 784 | azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); |
1da177e4 LT |
785 | |
786 | /* RIRB set up */ | |
787 | chip->rirb.addr = chip->rb.addr + 2048; | |
788 | chip->rirb.buf = (u32 *)(chip->rb.area + 2048); | |
deadff16 WF |
789 | chip->rirb.wp = chip->rirb.rp = 0; |
790 | memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); | |
1da177e4 | 791 | azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); |
766979e0 | 792 | azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); |
1da177e4 | 793 | |
07e4ca50 TI |
794 | /* set the rirb size to 256 entries (ULI requires explicitly) */ |
795 | azx_writeb(chip, RIRBSIZE, 0x02); | |
1da177e4 | 796 | /* reset the rirb hw write pointer */ |
b21fadb9 | 797 | azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); |
1da177e4 | 798 | /* set N=1, get RIRB response interrupt for new entry */ |
9477c58e | 799 | if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) |
14d34f16 TI |
800 | azx_writew(chip, RINTCNT, 0xc0); |
801 | else | |
802 | azx_writew(chip, RINTCNT, 1); | |
1da177e4 | 803 | /* enable rirb dma and response irq */ |
1da177e4 | 804 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); |
cdb1fbf2 | 805 | spin_unlock_irq(&chip->reg_lock); |
1da177e4 LT |
806 | } |
807 | ||
a98f90fd | 808 | static void azx_free_cmd_io(struct azx *chip) |
1da177e4 | 809 | { |
cdb1fbf2 | 810 | spin_lock_irq(&chip->reg_lock); |
1da177e4 LT |
811 | /* disable ringbuffer DMAs */ |
812 | azx_writeb(chip, RIRBCTL, 0); | |
813 | azx_writeb(chip, CORBCTL, 0); | |
cdb1fbf2 | 814 | spin_unlock_irq(&chip->reg_lock); |
1da177e4 LT |
815 | } |
816 | ||
deadff16 WF |
817 | static unsigned int azx_command_addr(u32 cmd) |
818 | { | |
819 | unsigned int addr = cmd >> 28; | |
820 | ||
821 | if (addr >= AZX_MAX_CODECS) { | |
822 | snd_BUG(); | |
823 | addr = 0; | |
824 | } | |
825 | ||
826 | return addr; | |
827 | } | |
828 | ||
829 | static unsigned int azx_response_addr(u32 res) | |
830 | { | |
831 | unsigned int addr = res & 0xf; | |
832 | ||
833 | if (addr >= AZX_MAX_CODECS) { | |
834 | snd_BUG(); | |
835 | addr = 0; | |
836 | } | |
837 | ||
838 | return addr; | |
1da177e4 LT |
839 | } |
840 | ||
841 | /* send a command */ | |
33fa35ed | 842 | static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) |
1da177e4 | 843 | { |
33fa35ed | 844 | struct azx *chip = bus->private_data; |
deadff16 | 845 | unsigned int addr = azx_command_addr(val); |
3bcce5c0 | 846 | unsigned int wp, rp; |
1da177e4 | 847 | |
c32649fe WF |
848 | spin_lock_irq(&chip->reg_lock); |
849 | ||
1da177e4 | 850 | /* add command to corb */ |
cc5ede3e TI |
851 | wp = azx_readw(chip, CORBWP); |
852 | if (wp == 0xffff) { | |
853 | /* something wrong, controller likely turned to D3 */ | |
854 | spin_unlock_irq(&chip->reg_lock); | |
3bcce5c0 | 855 | return -EIO; |
cc5ede3e | 856 | } |
1da177e4 LT |
857 | wp++; |
858 | wp %= ICH6_MAX_CORB_ENTRIES; | |
859 | ||
3bcce5c0 TI |
860 | rp = azx_readw(chip, CORBRP); |
861 | if (wp == rp) { | |
862 | /* oops, it's full */ | |
863 | spin_unlock_irq(&chip->reg_lock); | |
864 | return -EAGAIN; | |
865 | } | |
866 | ||
deadff16 | 867 | chip->rirb.cmds[addr]++; |
1da177e4 LT |
868 | chip->corb.buf[wp] = cpu_to_le32(val); |
869 | azx_writel(chip, CORBWP, wp); | |
c32649fe | 870 | |
1da177e4 LT |
871 | spin_unlock_irq(&chip->reg_lock); |
872 | ||
873 | return 0; | |
874 | } | |
875 | ||
876 | #define ICH6_RIRB_EX_UNSOL_EV (1<<4) | |
877 | ||
878 | /* retrieve RIRB entry - called from interrupt handler */ | |
a98f90fd | 879 | static void azx_update_rirb(struct azx *chip) |
1da177e4 LT |
880 | { |
881 | unsigned int rp, wp; | |
deadff16 | 882 | unsigned int addr; |
1da177e4 LT |
883 | u32 res, res_ex; |
884 | ||
cc5ede3e TI |
885 | wp = azx_readw(chip, RIRBWP); |
886 | if (wp == 0xffff) { | |
887 | /* something wrong, controller likely turned to D3 */ | |
888 | return; | |
889 | } | |
890 | ||
1da177e4 LT |
891 | if (wp == chip->rirb.wp) |
892 | return; | |
893 | chip->rirb.wp = wp; | |
deadff16 | 894 | |
1da177e4 LT |
895 | while (chip->rirb.rp != wp) { |
896 | chip->rirb.rp++; | |
897 | chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; | |
898 | ||
899 | rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ | |
900 | res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); | |
901 | res = le32_to_cpu(chip->rirb.buf[rp]); | |
deadff16 | 902 | addr = azx_response_addr(res_ex); |
1da177e4 LT |
903 | if (res_ex & ICH6_RIRB_EX_UNSOL_EV) |
904 | snd_hda_queue_unsol_event(chip->bus, res, res_ex); | |
deadff16 WF |
905 | else if (chip->rirb.cmds[addr]) { |
906 | chip->rirb.res[addr] = res; | |
2add9b92 | 907 | smp_wmb(); |
deadff16 | 908 | chip->rirb.cmds[addr]--; |
e310bb06 | 909 | } else |
9e3d352b | 910 | snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, " |
e310bb06 | 911 | "last cmd=%#08x\n", |
9e3d352b | 912 | pci_name(chip->pci), |
e310bb06 WF |
913 | res, res_ex, |
914 | chip->last_cmd[addr]); | |
1da177e4 LT |
915 | } |
916 | } | |
917 | ||
918 | /* receive a response */ | |
deadff16 WF |
919 | static unsigned int azx_rirb_get_response(struct hda_bus *bus, |
920 | unsigned int addr) | |
1da177e4 | 921 | { |
33fa35ed | 922 | struct azx *chip = bus->private_data; |
5c79b1f8 | 923 | unsigned long timeout; |
32cf4023 | 924 | unsigned long loopcounter; |
1eb6dc7d | 925 | int do_poll = 0; |
1da177e4 | 926 | |
5c79b1f8 TI |
927 | again: |
928 | timeout = jiffies + msecs_to_jiffies(1000); | |
32cf4023 DH |
929 | |
930 | for (loopcounter = 0;; loopcounter++) { | |
1eb6dc7d | 931 | if (chip->polling_mode || do_poll) { |
e96224ae TI |
932 | spin_lock_irq(&chip->reg_lock); |
933 | azx_update_rirb(chip); | |
934 | spin_unlock_irq(&chip->reg_lock); | |
935 | } | |
deadff16 | 936 | if (!chip->rirb.cmds[addr]) { |
2add9b92 | 937 | smp_rmb(); |
b613291f | 938 | bus->rirb_error = 0; |
1eb6dc7d ML |
939 | |
940 | if (!do_poll) | |
941 | chip->poll_count = 0; | |
deadff16 | 942 | return chip->rirb.res[addr]; /* the last value */ |
2add9b92 | 943 | } |
28a0d9df TI |
944 | if (time_after(jiffies, timeout)) |
945 | break; | |
32cf4023 | 946 | if (bus->needs_damn_long_delay || loopcounter > 3000) |
52987656 TI |
947 | msleep(2); /* temporary workaround */ |
948 | else { | |
949 | udelay(10); | |
950 | cond_resched(); | |
951 | } | |
28a0d9df | 952 | } |
5c79b1f8 | 953 | |
63e51fd7 TI |
954 | if (!bus->no_response_fallback) |
955 | return -1; | |
956 | ||
1eb6dc7d | 957 | if (!chip->polling_mode && chip->poll_count < 2) { |
445a51b3 | 958 | snd_printdd(SFX "%s: azx_get_response timeout, " |
1eb6dc7d | 959 | "polling the codec once: last cmd=0x%08x\n", |
445a51b3 | 960 | pci_name(chip->pci), chip->last_cmd[addr]); |
1eb6dc7d ML |
961 | do_poll = 1; |
962 | chip->poll_count++; | |
963 | goto again; | |
964 | } | |
965 | ||
966 | ||
23c4a881 | 967 | if (!chip->polling_mode) { |
445a51b3 | 968 | snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, " |
23c4a881 | 969 | "switching to polling mode: last cmd=0x%08x\n", |
445a51b3 | 970 | pci_name(chip->pci), chip->last_cmd[addr]); |
23c4a881 TI |
971 | chip->polling_mode = 1; |
972 | goto again; | |
973 | } | |
974 | ||
68e7fffc | 975 | if (chip->msi) { |
445a51b3 | 976 | snd_printk(KERN_WARNING SFX "%s: No response from codec, " |
feb27340 | 977 | "disabling MSI: last cmd=0x%08x\n", |
445a51b3 | 978 | pci_name(chip->pci), chip->last_cmd[addr]); |
68e7fffc TI |
979 | free_irq(chip->irq, chip); |
980 | chip->irq = -1; | |
981 | pci_disable_msi(chip->pci); | |
982 | chip->msi = 0; | |
b613291f TI |
983 | if (azx_acquire_irq(chip, 1) < 0) { |
984 | bus->rirb_error = 1; | |
68e7fffc | 985 | return -1; |
b613291f | 986 | } |
68e7fffc TI |
987 | goto again; |
988 | } | |
989 | ||
6ce4a3bc TI |
990 | if (chip->probing) { |
991 | /* If this critical timeout happens during the codec probing | |
992 | * phase, this is likely an access to a non-existing codec | |
993 | * slot. Better to return an error and reset the system. | |
994 | */ | |
995 | return -1; | |
996 | } | |
997 | ||
8dd78330 TI |
998 | /* a fatal communication error; need either to reset or to fallback |
999 | * to the single_cmd mode | |
1000 | */ | |
b613291f | 1001 | bus->rirb_error = 1; |
b20f3b83 | 1002 | if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { |
8dd78330 TI |
1003 | bus->response_reset = 1; |
1004 | return -1; /* give a chance to retry */ | |
1005 | } | |
1006 | ||
1007 | snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " | |
1008 | "switching to single_cmd mode: last cmd=0x%08x\n", | |
feb27340 | 1009 | chip->last_cmd[addr]); |
8dd78330 TI |
1010 | chip->single_cmd = 1; |
1011 | bus->response_reset = 0; | |
1a696978 | 1012 | /* release CORB/RIRB */ |
4fcd3920 | 1013 | azx_free_cmd_io(chip); |
1a696978 TI |
1014 | /* disable unsolicited responses */ |
1015 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); | |
5c79b1f8 | 1016 | return -1; |
1da177e4 LT |
1017 | } |
1018 | ||
1da177e4 LT |
1019 | /* |
1020 | * Use the single immediate command instead of CORB/RIRB for simplicity | |
1021 | * | |
1022 | * Note: according to Intel, this is not preferred use. The command was | |
1023 | * intended for the BIOS only, and may get confused with unsolicited | |
1024 | * responses. So, we shouldn't use it for normal operation from the | |
1025 | * driver. | |
1026 | * I left the codes, however, for debugging/testing purposes. | |
1027 | */ | |
1028 | ||
b05a7d4f | 1029 | /* receive a response */ |
deadff16 | 1030 | static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) |
b05a7d4f TI |
1031 | { |
1032 | int timeout = 50; | |
1033 | ||
1034 | while (timeout--) { | |
1035 | /* check IRV busy bit */ | |
1036 | if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { | |
1037 | /* reuse rirb.res as the response return value */ | |
deadff16 | 1038 | chip->rirb.res[addr] = azx_readl(chip, IR); |
b05a7d4f TI |
1039 | return 0; |
1040 | } | |
1041 | udelay(1); | |
1042 | } | |
1043 | if (printk_ratelimit()) | |
445a51b3 DB |
1044 | snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n", |
1045 | pci_name(chip->pci), azx_readw(chip, IRS)); | |
deadff16 | 1046 | chip->rirb.res[addr] = -1; |
b05a7d4f TI |
1047 | return -EIO; |
1048 | } | |
1049 | ||
1da177e4 | 1050 | /* send a command */ |
33fa35ed | 1051 | static int azx_single_send_cmd(struct hda_bus *bus, u32 val) |
1da177e4 | 1052 | { |
33fa35ed | 1053 | struct azx *chip = bus->private_data; |
deadff16 | 1054 | unsigned int addr = azx_command_addr(val); |
1da177e4 LT |
1055 | int timeout = 50; |
1056 | ||
8dd78330 | 1057 | bus->rirb_error = 0; |
1da177e4 LT |
1058 | while (timeout--) { |
1059 | /* check ICB busy bit */ | |
d01ce99f | 1060 | if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { |
1da177e4 | 1061 | /* Clear IRV valid bit */ |
d01ce99f TI |
1062 | azx_writew(chip, IRS, azx_readw(chip, IRS) | |
1063 | ICH6_IRS_VALID); | |
1da177e4 | 1064 | azx_writel(chip, IC, val); |
d01ce99f TI |
1065 | azx_writew(chip, IRS, azx_readw(chip, IRS) | |
1066 | ICH6_IRS_BUSY); | |
deadff16 | 1067 | return azx_single_wait_for_response(chip, addr); |
1da177e4 LT |
1068 | } |
1069 | udelay(1); | |
1070 | } | |
1cfd52bc | 1071 | if (printk_ratelimit()) |
445a51b3 DB |
1072 | snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n", |
1073 | pci_name(chip->pci), azx_readw(chip, IRS), val); | |
1da177e4 LT |
1074 | return -EIO; |
1075 | } | |
1076 | ||
1077 | /* receive a response */ | |
deadff16 WF |
1078 | static unsigned int azx_single_get_response(struct hda_bus *bus, |
1079 | unsigned int addr) | |
1da177e4 | 1080 | { |
33fa35ed | 1081 | struct azx *chip = bus->private_data; |
deadff16 | 1082 | return chip->rirb.res[addr]; |
1da177e4 LT |
1083 | } |
1084 | ||
111d3af5 TI |
1085 | /* |
1086 | * The below are the main callbacks from hda_codec. | |
1087 | * | |
1088 | * They are just the skeleton to call sub-callbacks according to the | |
1089 | * current setting of chip->single_cmd. | |
1090 | */ | |
1091 | ||
1092 | /* send a command */ | |
33fa35ed | 1093 | static int azx_send_cmd(struct hda_bus *bus, unsigned int val) |
111d3af5 | 1094 | { |
33fa35ed | 1095 | struct azx *chip = bus->private_data; |
43bbb6cc | 1096 | |
a82d51ed TI |
1097 | if (chip->disabled) |
1098 | return 0; | |
feb27340 | 1099 | chip->last_cmd[azx_command_addr(val)] = val; |
111d3af5 | 1100 | if (chip->single_cmd) |
33fa35ed | 1101 | return azx_single_send_cmd(bus, val); |
111d3af5 | 1102 | else |
33fa35ed | 1103 | return azx_corb_send_cmd(bus, val); |
111d3af5 TI |
1104 | } |
1105 | ||
1106 | /* get a response */ | |
deadff16 WF |
1107 | static unsigned int azx_get_response(struct hda_bus *bus, |
1108 | unsigned int addr) | |
111d3af5 | 1109 | { |
33fa35ed | 1110 | struct azx *chip = bus->private_data; |
a82d51ed TI |
1111 | if (chip->disabled) |
1112 | return 0; | |
111d3af5 | 1113 | if (chip->single_cmd) |
deadff16 | 1114 | return azx_single_get_response(bus, addr); |
111d3af5 | 1115 | else |
deadff16 | 1116 | return azx_rirb_get_response(bus, addr); |
111d3af5 TI |
1117 | } |
1118 | ||
83012a7c | 1119 | #ifdef CONFIG_PM |
68467f51 | 1120 | static void azx_power_notify(struct hda_bus *bus, bool power_up); |
cb53c626 | 1121 | #endif |
111d3af5 | 1122 | |
1d1a4564 TI |
1123 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
1124 | static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format, | |
1125 | unsigned int byte_size, | |
1126 | struct snd_dma_buffer *bufp); | |
1127 | static void azx_load_dsp_trigger(struct hda_bus *bus, bool start); | |
1128 | static void azx_load_dsp_cleanup(struct hda_bus *bus, | |
1129 | struct snd_dma_buffer *dmab); | |
1130 | #endif | |
1131 | ||
3af3f356 | 1132 | /* enter link reset */ |
7295b264 | 1133 | static void azx_enter_link_reset(struct azx *chip) |
3af3f356 ML |
1134 | { |
1135 | unsigned long timeout; | |
1136 | ||
1137 | /* reset controller */ | |
1138 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); | |
1139 | ||
1140 | timeout = jiffies + msecs_to_jiffies(100); | |
1141 | while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) && | |
1142 | time_before(jiffies, timeout)) | |
1143 | usleep_range(500, 1000); | |
1144 | } | |
1145 | ||
7295b264 ML |
1146 | /* exit link reset */ |
1147 | static void azx_exit_link_reset(struct azx *chip) | |
1da177e4 | 1148 | { |
fa348da5 | 1149 | unsigned long timeout; |
1da177e4 | 1150 | |
7295b264 ML |
1151 | azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); |
1152 | ||
1153 | timeout = jiffies + msecs_to_jiffies(100); | |
1154 | while (!azx_readb(chip, GCTL) && | |
1155 | time_before(jiffies, timeout)) | |
1156 | usleep_range(500, 1000); | |
1157 | } | |
1158 | ||
1159 | /* reset codec link */ | |
1160 | static int azx_reset(struct azx *chip, int full_reset) | |
1161 | { | |
cd508fe5 JK |
1162 | if (!full_reset) |
1163 | goto __skip; | |
1164 | ||
e8a7f136 | 1165 | /* clear STATESTS */ |
da7db6ad | 1166 | azx_writew(chip, STATESTS, STATESTS_INT_MASK); |
e8a7f136 | 1167 | |
1da177e4 | 1168 | /* reset controller */ |
7295b264 | 1169 | azx_enter_link_reset(chip); |
1da177e4 LT |
1170 | |
1171 | /* delay for >= 100us for codec PLL to settle per spec | |
1172 | * Rev 0.9 section 5.5.1 | |
1173 | */ | |
fa348da5 | 1174 | usleep_range(500, 1000); |
1da177e4 LT |
1175 | |
1176 | /* Bring controller out of reset */ | |
7295b264 | 1177 | azx_exit_link_reset(chip); |
1da177e4 | 1178 | |
927fc866 | 1179 | /* Brent Chartrand said to wait >= 540us for codecs to initialize */ |
fa348da5 | 1180 | usleep_range(1000, 1200); |
1da177e4 | 1181 | |
cd508fe5 | 1182 | __skip: |
1da177e4 | 1183 | /* check to see if controller is ready */ |
927fc866 | 1184 | if (!azx_readb(chip, GCTL)) { |
445a51b3 | 1185 | snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci)); |
1da177e4 LT |
1186 | return -EBUSY; |
1187 | } | |
1188 | ||
41e2fce4 | 1189 | /* Accept unsolicited responses */ |
1a696978 TI |
1190 | if (!chip->single_cmd) |
1191 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) | | |
1192 | ICH6_GCTL_UNSOL); | |
41e2fce4 | 1193 | |
1da177e4 | 1194 | /* detect codecs */ |
927fc866 | 1195 | if (!chip->codec_mask) { |
1da177e4 | 1196 | chip->codec_mask = azx_readw(chip, STATESTS); |
445a51b3 | 1197 | snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask); |
1da177e4 LT |
1198 | } |
1199 | ||
1200 | return 0; | |
1201 | } | |
1202 | ||
1203 | ||
1204 | /* | |
1205 | * Lowlevel interface | |
1206 | */ | |
1207 | ||
1208 | /* enable interrupts */ | |
a98f90fd | 1209 | static void azx_int_enable(struct azx *chip) |
1da177e4 LT |
1210 | { |
1211 | /* enable controller CIE and GIE */ | |
1212 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | | |
1213 | ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); | |
1214 | } | |
1215 | ||
1216 | /* disable interrupts */ | |
a98f90fd | 1217 | static void azx_int_disable(struct azx *chip) |
1da177e4 LT |
1218 | { |
1219 | int i; | |
1220 | ||
1221 | /* disable interrupts in stream descriptor */ | |
07e4ca50 | 1222 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 1223 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
1224 | azx_sd_writeb(azx_dev, SD_CTL, |
1225 | azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); | |
1226 | } | |
1227 | ||
1228 | /* disable SIE for all streams */ | |
1229 | azx_writeb(chip, INTCTL, 0); | |
1230 | ||
1231 | /* disable controller CIE and GIE */ | |
1232 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & | |
1233 | ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); | |
1234 | } | |
1235 | ||
1236 | /* clear interrupts */ | |
a98f90fd | 1237 | static void azx_int_clear(struct azx *chip) |
1da177e4 LT |
1238 | { |
1239 | int i; | |
1240 | ||
1241 | /* clear stream status */ | |
07e4ca50 | 1242 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 1243 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
1244 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); |
1245 | } | |
1246 | ||
1247 | /* clear STATESTS */ | |
da7db6ad | 1248 | azx_writew(chip, STATESTS, STATESTS_INT_MASK); |
1da177e4 LT |
1249 | |
1250 | /* clear rirb status */ | |
1251 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
1252 | ||
1253 | /* clear int status */ | |
1254 | azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); | |
1255 | } | |
1256 | ||
1257 | /* start a stream */ | |
a98f90fd | 1258 | static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) |
1da177e4 | 1259 | { |
0e153474 JC |
1260 | /* |
1261 | * Before stream start, initialize parameter | |
1262 | */ | |
1263 | azx_dev->insufficient = 1; | |
1264 | ||
1da177e4 | 1265 | /* enable SIE */ |
ccc5df05 WN |
1266 | azx_writel(chip, INTCTL, |
1267 | azx_readl(chip, INTCTL) | (1 << azx_dev->index)); | |
1da177e4 LT |
1268 | /* set DMA start and interrupt mask */ |
1269 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | | |
1270 | SD_CTL_DMA_START | SD_INT_MASK); | |
1271 | } | |
1272 | ||
1dddab40 TI |
1273 | /* stop DMA */ |
1274 | static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) | |
1da177e4 | 1275 | { |
1da177e4 LT |
1276 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & |
1277 | ~(SD_CTL_DMA_START | SD_INT_MASK)); | |
1278 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | |
1dddab40 TI |
1279 | } |
1280 | ||
1281 | /* stop a stream */ | |
1282 | static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) | |
1283 | { | |
1284 | azx_stream_clear(chip, azx_dev); | |
1da177e4 | 1285 | /* disable SIE */ |
ccc5df05 WN |
1286 | azx_writel(chip, INTCTL, |
1287 | azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); | |
1da177e4 LT |
1288 | } |
1289 | ||
1290 | ||
1291 | /* | |
cb53c626 | 1292 | * reset and start the controller registers |
1da177e4 | 1293 | */ |
cd508fe5 | 1294 | static void azx_init_chip(struct azx *chip, int full_reset) |
1da177e4 | 1295 | { |
cb53c626 TI |
1296 | if (chip->initialized) |
1297 | return; | |
1da177e4 LT |
1298 | |
1299 | /* reset controller */ | |
cd508fe5 | 1300 | azx_reset(chip, full_reset); |
1da177e4 LT |
1301 | |
1302 | /* initialize interrupts */ | |
1303 | azx_int_clear(chip); | |
1304 | azx_int_enable(chip); | |
1305 | ||
1306 | /* initialize the codec command I/O */ | |
1a696978 TI |
1307 | if (!chip->single_cmd) |
1308 | azx_init_cmd_io(chip); | |
1da177e4 | 1309 | |
0be3b5d3 TI |
1310 | /* program the position buffer */ |
1311 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); | |
766979e0 | 1312 | azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); |
f5d40b30 | 1313 | |
cb53c626 TI |
1314 | chip->initialized = 1; |
1315 | } | |
1316 | ||
1317 | /* | |
1318 | * initialize the PCI registers | |
1319 | */ | |
1320 | /* update bits in a PCI register byte */ | |
1321 | static void update_pci_byte(struct pci_dev *pci, unsigned int reg, | |
1322 | unsigned char mask, unsigned char val) | |
1323 | { | |
1324 | unsigned char data; | |
1325 | ||
1326 | pci_read_config_byte(pci, reg, &data); | |
1327 | data &= ~mask; | |
1328 | data |= (val & mask); | |
1329 | pci_write_config_byte(pci, reg, data); | |
1330 | } | |
1331 | ||
1332 | static void azx_init_pci(struct azx *chip) | |
1333 | { | |
1334 | /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) | |
1335 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | |
1336 | * Ensuring these bits are 0 clears playback static on some HD Audio | |
a09e89f6 AL |
1337 | * codecs. |
1338 | * The PCI register TCSEL is defined in the Intel manuals. | |
cb53c626 | 1339 | */ |
46f2cc80 | 1340 | if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { |
445a51b3 | 1341 | snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci)); |
a09e89f6 | 1342 | update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0); |
9477c58e | 1343 | } |
cb53c626 | 1344 | |
9477c58e TI |
1345 | /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, |
1346 | * we need to enable snoop. | |
1347 | */ | |
1348 | if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) { | |
445a51b3 | 1349 | snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip)); |
cb53c626 | 1350 | update_pci_byte(chip->pci, |
27fe48d9 TI |
1351 | ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, |
1352 | azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); | |
9477c58e TI |
1353 | } |
1354 | ||
1355 | /* For NVIDIA HDA, enable snoop */ | |
1356 | if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) { | |
445a51b3 | 1357 | snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip)); |
cb53c626 TI |
1358 | update_pci_byte(chip->pci, |
1359 | NVIDIA_HDA_TRANSREG_ADDR, | |
1360 | 0x0f, NVIDIA_HDA_ENABLE_COHBITS); | |
320dcc30 PC |
1361 | update_pci_byte(chip->pci, |
1362 | NVIDIA_HDA_ISTRM_COH, | |
1363 | 0x01, NVIDIA_HDA_ENABLE_COHBIT); | |
1364 | update_pci_byte(chip->pci, | |
1365 | NVIDIA_HDA_OSTRM_COH, | |
1366 | 0x01, NVIDIA_HDA_ENABLE_COHBIT); | |
9477c58e TI |
1367 | } |
1368 | ||
1369 | /* Enable SCH/PCH snoop if needed */ | |
1370 | if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) { | |
27fe48d9 | 1371 | unsigned short snoop; |
90a5ad52 | 1372 | pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); |
27fe48d9 TI |
1373 | if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || |
1374 | (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { | |
1375 | snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; | |
1376 | if (!azx_snoop(chip)) | |
1377 | snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; | |
1378 | pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); | |
90a5ad52 TI |
1379 | pci_read_config_word(chip->pci, |
1380 | INTEL_SCH_HDA_DEVC, &snoop); | |
90a5ad52 | 1381 | } |
445a51b3 DB |
1382 | snd_printdd(SFX "%s: SCH snoop: %s\n", |
1383 | pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) | |
27fe48d9 | 1384 | ? "Disabled" : "Enabled"); |
da3fca21 | 1385 | } |
1da177e4 LT |
1386 | } |
1387 | ||
1388 | ||
9ad593f6 TI |
1389 | static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); |
1390 | ||
1da177e4 LT |
1391 | /* |
1392 | * interrupt handler | |
1393 | */ | |
7d12e780 | 1394 | static irqreturn_t azx_interrupt(int irq, void *dev_id) |
1da177e4 | 1395 | { |
a98f90fd TI |
1396 | struct azx *chip = dev_id; |
1397 | struct azx_dev *azx_dev; | |
1da177e4 | 1398 | u32 status; |
9ef04066 | 1399 | u8 sd_status; |
fa00e046 | 1400 | int i, ok; |
1da177e4 | 1401 | |
b8dfc462 | 1402 | #ifdef CONFIG_PM_RUNTIME |
246efa4a DA |
1403 | if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME) |
1404 | if (chip->pci->dev.power.runtime_status != RPM_ACTIVE) | |
1405 | return IRQ_NONE; | |
b8dfc462 ML |
1406 | #endif |
1407 | ||
1da177e4 LT |
1408 | spin_lock(&chip->reg_lock); |
1409 | ||
60911062 DC |
1410 | if (chip->disabled) { |
1411 | spin_unlock(&chip->reg_lock); | |
a82d51ed | 1412 | return IRQ_NONE; |
60911062 | 1413 | } |
a82d51ed | 1414 | |
1da177e4 | 1415 | status = azx_readl(chip, INTSTS); |
246efa4a | 1416 | if (status == 0 || status == 0xffffffff) { |
1da177e4 LT |
1417 | spin_unlock(&chip->reg_lock); |
1418 | return IRQ_NONE; | |
1419 | } | |
1420 | ||
07e4ca50 | 1421 | for (i = 0; i < chip->num_streams; i++) { |
1da177e4 LT |
1422 | azx_dev = &chip->azx_dev[i]; |
1423 | if (status & azx_dev->sd_int_sta_mask) { | |
9ef04066 | 1424 | sd_status = azx_sd_readb(azx_dev, SD_STS); |
1da177e4 | 1425 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); |
9ef04066 CL |
1426 | if (!azx_dev->substream || !azx_dev->running || |
1427 | !(sd_status & SD_INT_COMPLETE)) | |
9ad593f6 TI |
1428 | continue; |
1429 | /* check whether this IRQ is really acceptable */ | |
fa00e046 JK |
1430 | ok = azx_position_ok(chip, azx_dev); |
1431 | if (ok == 1) { | |
9ad593f6 | 1432 | azx_dev->irq_pending = 0; |
1da177e4 LT |
1433 | spin_unlock(&chip->reg_lock); |
1434 | snd_pcm_period_elapsed(azx_dev->substream); | |
1435 | spin_lock(&chip->reg_lock); | |
fa00e046 | 1436 | } else if (ok == 0 && chip->bus && chip->bus->workq) { |
9ad593f6 TI |
1437 | /* bogus IRQ, process it later */ |
1438 | azx_dev->irq_pending = 1; | |
6acaed38 TI |
1439 | queue_work(chip->bus->workq, |
1440 | &chip->irq_pending_work); | |
1da177e4 LT |
1441 | } |
1442 | } | |
1443 | } | |
1444 | ||
1445 | /* clear rirb int */ | |
1446 | status = azx_readb(chip, RIRBSTS); | |
1447 | if (status & RIRB_INT_MASK) { | |
14d34f16 | 1448 | if (status & RIRB_INT_RESPONSE) { |
9477c58e | 1449 | if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY) |
14d34f16 | 1450 | udelay(80); |
1da177e4 | 1451 | azx_update_rirb(chip); |
14d34f16 | 1452 | } |
1da177e4 LT |
1453 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); |
1454 | } | |
1455 | ||
1456 | #if 0 | |
1457 | /* clear state status int */ | |
da7db6ad WX |
1458 | if (azx_readw(chip, STATESTS) & 0x04) |
1459 | azx_writew(chip, STATESTS, 0x04); | |
1da177e4 LT |
1460 | #endif |
1461 | spin_unlock(&chip->reg_lock); | |
1462 | ||
1463 | return IRQ_HANDLED; | |
1464 | } | |
1465 | ||
1466 | ||
675f25d4 TI |
1467 | /* |
1468 | * set up a BDL entry | |
1469 | */ | |
5ae763b1 | 1470 | static int setup_bdle(struct azx *chip, |
1d1a4564 | 1471 | struct snd_dma_buffer *dmab, |
675f25d4 TI |
1472 | struct azx_dev *azx_dev, u32 **bdlp, |
1473 | int ofs, int size, int with_ioc) | |
1474 | { | |
675f25d4 TI |
1475 | u32 *bdl = *bdlp; |
1476 | ||
1477 | while (size > 0) { | |
1478 | dma_addr_t addr; | |
1479 | int chunk; | |
1480 | ||
1481 | if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) | |
1482 | return -EINVAL; | |
1483 | ||
1d1a4564 | 1484 | addr = snd_sgbuf_get_addr(dmab, ofs); |
675f25d4 TI |
1485 | /* program the address field of the BDL entry */ |
1486 | bdl[0] = cpu_to_le32((u32)addr); | |
766979e0 | 1487 | bdl[1] = cpu_to_le32(upper_32_bits(addr)); |
675f25d4 | 1488 | /* program the size field of the BDL entry */ |
1d1a4564 | 1489 | chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); |
5ae763b1 TI |
1490 | /* one BDLE cannot cross 4K boundary on CTHDA chips */ |
1491 | if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) { | |
1492 | u32 remain = 0x1000 - (ofs & 0xfff); | |
1493 | if (chunk > remain) | |
1494 | chunk = remain; | |
1495 | } | |
675f25d4 TI |
1496 | bdl[2] = cpu_to_le32(chunk); |
1497 | /* program the IOC to enable interrupt | |
1498 | * only when the whole fragment is processed | |
1499 | */ | |
1500 | size -= chunk; | |
1501 | bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); | |
1502 | bdl += 4; | |
1503 | azx_dev->frags++; | |
1504 | ofs += chunk; | |
1505 | } | |
1506 | *bdlp = bdl; | |
1507 | return ofs; | |
1508 | } | |
1509 | ||
1da177e4 LT |
1510 | /* |
1511 | * set up BDL entries | |
1512 | */ | |
555e219f TI |
1513 | static int azx_setup_periods(struct azx *chip, |
1514 | struct snd_pcm_substream *substream, | |
4ce107b9 | 1515 | struct azx_dev *azx_dev) |
1da177e4 | 1516 | { |
4ce107b9 TI |
1517 | u32 *bdl; |
1518 | int i, ofs, periods, period_bytes; | |
555e219f | 1519 | int pos_adj; |
1da177e4 LT |
1520 | |
1521 | /* reset BDL address */ | |
1522 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
1523 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
1524 | ||
97b71c94 | 1525 | period_bytes = azx_dev->period_bytes; |
4ce107b9 TI |
1526 | periods = azx_dev->bufsize / period_bytes; |
1527 | ||
1da177e4 | 1528 | /* program the initial BDL entries */ |
4ce107b9 TI |
1529 | bdl = (u32 *)azx_dev->bdl.area; |
1530 | ofs = 0; | |
1531 | azx_dev->frags = 0; | |
555e219f | 1532 | pos_adj = bdl_pos_adj[chip->dev_index]; |
915bf29e | 1533 | if (!azx_dev->no_period_wakeup && pos_adj > 0) { |
675f25d4 | 1534 | struct snd_pcm_runtime *runtime = substream->runtime; |
e785d3d8 | 1535 | int pos_align = pos_adj; |
555e219f | 1536 | pos_adj = (pos_adj * runtime->rate + 47999) / 48000; |
675f25d4 | 1537 | if (!pos_adj) |
e785d3d8 TI |
1538 | pos_adj = pos_align; |
1539 | else | |
1540 | pos_adj = ((pos_adj + pos_align - 1) / pos_align) * | |
1541 | pos_align; | |
675f25d4 TI |
1542 | pos_adj = frames_to_bytes(runtime, pos_adj); |
1543 | if (pos_adj >= period_bytes) { | |
445a51b3 DB |
1544 | snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n", |
1545 | pci_name(chip->pci), bdl_pos_adj[chip->dev_index]); | |
675f25d4 TI |
1546 | pos_adj = 0; |
1547 | } else { | |
1d1a4564 TI |
1548 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), |
1549 | azx_dev, | |
915bf29e | 1550 | &bdl, ofs, pos_adj, true); |
675f25d4 TI |
1551 | if (ofs < 0) |
1552 | goto error; | |
4ce107b9 | 1553 | } |
555e219f TI |
1554 | } else |
1555 | pos_adj = 0; | |
675f25d4 TI |
1556 | for (i = 0; i < periods; i++) { |
1557 | if (i == periods - 1 && pos_adj) | |
1d1a4564 TI |
1558 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), |
1559 | azx_dev, &bdl, ofs, | |
675f25d4 TI |
1560 | period_bytes - pos_adj, 0); |
1561 | else | |
1d1a4564 TI |
1562 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), |
1563 | azx_dev, &bdl, ofs, | |
7bb8fb70 | 1564 | period_bytes, |
915bf29e | 1565 | !azx_dev->no_period_wakeup); |
675f25d4 TI |
1566 | if (ofs < 0) |
1567 | goto error; | |
1da177e4 | 1568 | } |
4ce107b9 | 1569 | return 0; |
675f25d4 TI |
1570 | |
1571 | error: | |
445a51b3 DB |
1572 | snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n", |
1573 | pci_name(chip->pci), azx_dev->bufsize, period_bytes); | |
675f25d4 | 1574 | return -EINVAL; |
1da177e4 LT |
1575 | } |
1576 | ||
1dddab40 TI |
1577 | /* reset stream */ |
1578 | static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) | |
1da177e4 LT |
1579 | { |
1580 | unsigned char val; | |
1581 | int timeout; | |
1582 | ||
1dddab40 TI |
1583 | azx_stream_clear(chip, azx_dev); |
1584 | ||
d01ce99f TI |
1585 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | |
1586 | SD_CTL_STREAM_RESET); | |
1da177e4 LT |
1587 | udelay(3); |
1588 | timeout = 300; | |
1589 | while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
1590 | --timeout) | |
1591 | ; | |
1592 | val &= ~SD_CTL_STREAM_RESET; | |
1593 | azx_sd_writeb(azx_dev, SD_CTL, val); | |
1594 | udelay(3); | |
1595 | ||
1596 | timeout = 300; | |
1597 | /* waiting for hardware to report that the stream is out of reset */ | |
1598 | while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
1599 | --timeout) | |
1600 | ; | |
fa00e046 JK |
1601 | |
1602 | /* reset first position - may not be synced with hw at this time */ | |
1603 | *azx_dev->posbuf = 0; | |
1dddab40 | 1604 | } |
1da177e4 | 1605 | |
1dddab40 TI |
1606 | /* |
1607 | * set up the SD for streaming | |
1608 | */ | |
1609 | static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) | |
1610 | { | |
27fe48d9 | 1611 | unsigned int val; |
1dddab40 TI |
1612 | /* make sure the run bit is zero for SD */ |
1613 | azx_stream_clear(chip, azx_dev); | |
1da177e4 | 1614 | /* program the stream_tag */ |
27fe48d9 TI |
1615 | val = azx_sd_readl(azx_dev, SD_CTL); |
1616 | val = (val & ~SD_CTL_STREAM_TAG_MASK) | | |
1617 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); | |
1618 | if (!azx_snoop(chip)) | |
1619 | val |= SD_CTL_TRAFFIC_PRIO; | |
1620 | azx_sd_writel(azx_dev, SD_CTL, val); | |
1da177e4 LT |
1621 | |
1622 | /* program the length of samples in cyclic buffer */ | |
1623 | azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); | |
1624 | ||
1625 | /* program the stream format */ | |
1626 | /* this value needs to be the same as the one programmed */ | |
1627 | azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); | |
1628 | ||
1629 | /* program the stream LVI (last valid index) of the BDL */ | |
1630 | azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); | |
1631 | ||
1632 | /* program the BDL address */ | |
1633 | /* lower BDL address */ | |
4ce107b9 | 1634 | azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); |
1da177e4 | 1635 | /* upper BDL address */ |
766979e0 | 1636 | azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr)); |
1da177e4 | 1637 | |
0be3b5d3 | 1638 | /* enable the position buffer */ |
4cb36310 DH |
1639 | if (chip->position_fix[0] != POS_FIX_LPIB || |
1640 | chip->position_fix[1] != POS_FIX_LPIB) { | |
ee9d6b9a TI |
1641 | if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) |
1642 | azx_writel(chip, DPLBASE, | |
1643 | (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); | |
1644 | } | |
c74db86b | 1645 | |
1da177e4 | 1646 | /* set the interrupt enable bits in the descriptor control register */ |
d01ce99f TI |
1647 | azx_sd_writel(azx_dev, SD_CTL, |
1648 | azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); | |
1da177e4 LT |
1649 | |
1650 | return 0; | |
1651 | } | |
1652 | ||
6ce4a3bc TI |
1653 | /* |
1654 | * Probe the given codec address | |
1655 | */ | |
1656 | static int probe_codec(struct azx *chip, int addr) | |
1657 | { | |
1658 | unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | | |
1659 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; | |
1660 | unsigned int res; | |
1661 | ||
a678cdee | 1662 | mutex_lock(&chip->bus->cmd_mutex); |
6ce4a3bc TI |
1663 | chip->probing = 1; |
1664 | azx_send_cmd(chip->bus, cmd); | |
deadff16 | 1665 | res = azx_get_response(chip->bus, addr); |
6ce4a3bc | 1666 | chip->probing = 0; |
a678cdee | 1667 | mutex_unlock(&chip->bus->cmd_mutex); |
6ce4a3bc TI |
1668 | if (res == -1) |
1669 | return -EIO; | |
445a51b3 | 1670 | snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr); |
6ce4a3bc TI |
1671 | return 0; |
1672 | } | |
1673 | ||
33fa35ed TI |
1674 | static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, |
1675 | struct hda_pcm *cpcm); | |
6ce4a3bc | 1676 | static void azx_stop_chip(struct azx *chip); |
1da177e4 | 1677 | |
8dd78330 TI |
1678 | static void azx_bus_reset(struct hda_bus *bus) |
1679 | { | |
1680 | struct azx *chip = bus->private_data; | |
8dd78330 TI |
1681 | |
1682 | bus->in_reset = 1; | |
1683 | azx_stop_chip(chip); | |
cd508fe5 | 1684 | azx_init_chip(chip, 1); |
65f75983 | 1685 | #ifdef CONFIG_PM |
8dd78330 | 1686 | if (chip->initialized) { |
01b65bfb TI |
1687 | struct azx_pcm *p; |
1688 | list_for_each_entry(p, &chip->pcm_list, list) | |
1689 | snd_pcm_suspend_all(p->pcm); | |
8dd78330 TI |
1690 | snd_hda_suspend(chip->bus); |
1691 | snd_hda_resume(chip->bus); | |
1692 | } | |
65f75983 | 1693 | #endif |
8dd78330 TI |
1694 | bus->in_reset = 0; |
1695 | } | |
1696 | ||
26a6cb6c DH |
1697 | static int get_jackpoll_interval(struct azx *chip) |
1698 | { | |
1699 | int i = jackpoll_ms[chip->dev_index]; | |
1700 | unsigned int j; | |
1701 | if (i == 0) | |
1702 | return 0; | |
1703 | if (i < 50 || i > 60000) | |
1704 | j = 0; | |
1705 | else | |
1706 | j = msecs_to_jiffies(i); | |
1707 | if (j == 0) | |
1708 | snd_printk(KERN_WARNING SFX | |
1709 | "jackpoll_ms value out of range: %d\n", i); | |
1710 | return j; | |
1711 | } | |
1712 | ||
1da177e4 LT |
1713 | /* |
1714 | * Codec initialization | |
1715 | */ | |
1716 | ||
2f5983f2 | 1717 | /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ |
48c8b0eb | 1718 | static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { |
7445dfc1 | 1719 | [AZX_DRIVER_NVIDIA] = 8, |
f269002e | 1720 | [AZX_DRIVER_TERA] = 1, |
a9995a35 TI |
1721 | }; |
1722 | ||
48c8b0eb | 1723 | static int azx_codec_create(struct azx *chip, const char *model) |
1da177e4 LT |
1724 | { |
1725 | struct hda_bus_template bus_temp; | |
34c25350 TI |
1726 | int c, codecs, err; |
1727 | int max_slots; | |
1da177e4 LT |
1728 | |
1729 | memset(&bus_temp, 0, sizeof(bus_temp)); | |
1730 | bus_temp.private_data = chip; | |
1731 | bus_temp.modelname = model; | |
1732 | bus_temp.pci = chip->pci; | |
111d3af5 TI |
1733 | bus_temp.ops.command = azx_send_cmd; |
1734 | bus_temp.ops.get_response = azx_get_response; | |
176d5335 | 1735 | bus_temp.ops.attach_pcm = azx_attach_pcm_stream; |
8dd78330 | 1736 | bus_temp.ops.bus_reset = azx_bus_reset; |
83012a7c | 1737 | #ifdef CONFIG_PM |
11cd41b8 | 1738 | bus_temp.power_save = &power_save; |
cb53c626 TI |
1739 | bus_temp.ops.pm_notify = azx_power_notify; |
1740 | #endif | |
1d1a4564 TI |
1741 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
1742 | bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare; | |
1743 | bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger; | |
1744 | bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup; | |
1745 | #endif | |
1da177e4 | 1746 | |
d01ce99f TI |
1747 | err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus); |
1748 | if (err < 0) | |
1da177e4 LT |
1749 | return err; |
1750 | ||
9477c58e | 1751 | if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) { |
445a51b3 | 1752 | snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci)); |
dc9c8e21 | 1753 | chip->bus->needs_damn_long_delay = 1; |
9477c58e | 1754 | } |
dc9c8e21 | 1755 | |
34c25350 | 1756 | codecs = 0; |
2f5983f2 TI |
1757 | max_slots = azx_max_codecs[chip->driver_type]; |
1758 | if (!max_slots) | |
7445dfc1 | 1759 | max_slots = AZX_DEFAULT_CODECS; |
6ce4a3bc TI |
1760 | |
1761 | /* First try to probe all given codec slots */ | |
1762 | for (c = 0; c < max_slots; c++) { | |
f1eaaeec | 1763 | if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
6ce4a3bc TI |
1764 | if (probe_codec(chip, c) < 0) { |
1765 | /* Some BIOSen give you wrong codec addresses | |
1766 | * that don't exist | |
1767 | */ | |
4abc1cc2 | 1768 | snd_printk(KERN_WARNING SFX |
445a51b3 DB |
1769 | "%s: Codec #%d probe error; " |
1770 | "disabling it...\n", pci_name(chip->pci), c); | |
6ce4a3bc TI |
1771 | chip->codec_mask &= ~(1 << c); |
1772 | /* More badly, accessing to a non-existing | |
1773 | * codec often screws up the controller chip, | |
2448158e | 1774 | * and disturbs the further communications. |
6ce4a3bc TI |
1775 | * Thus if an error occurs during probing, |
1776 | * better to reset the controller chip to | |
1777 | * get back to the sanity state. | |
1778 | */ | |
1779 | azx_stop_chip(chip); | |
cd508fe5 | 1780 | azx_init_chip(chip, 1); |
6ce4a3bc TI |
1781 | } |
1782 | } | |
1783 | } | |
1784 | ||
d507cd66 TI |
1785 | /* AMD chipsets often cause the communication stalls upon certain |
1786 | * sequence like the pin-detection. It seems that forcing the synced | |
1787 | * access works around the stall. Grrr... | |
1788 | */ | |
9477c58e | 1789 | if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) { |
445a51b3 DB |
1790 | snd_printd(SFX "%s: Enable sync_write for stable communication\n", |
1791 | pci_name(chip->pci)); | |
d507cd66 TI |
1792 | chip->bus->sync_write = 1; |
1793 | chip->bus->allow_bus_reset = 1; | |
1794 | } | |
1795 | ||
6ce4a3bc | 1796 | /* Then create codec instances */ |
34c25350 | 1797 | for (c = 0; c < max_slots; c++) { |
f1eaaeec | 1798 | if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
bccad14e | 1799 | struct hda_codec *codec; |
a1e21c90 | 1800 | err = snd_hda_codec_new(chip->bus, c, &codec); |
1da177e4 LT |
1801 | if (err < 0) |
1802 | continue; | |
26a6cb6c | 1803 | codec->jackpoll_interval = get_jackpoll_interval(chip); |
2dca0bba | 1804 | codec->beep_mode = chip->beep_mode; |
1da177e4 | 1805 | codecs++; |
19a982b6 TI |
1806 | } |
1807 | } | |
1808 | if (!codecs) { | |
445a51b3 | 1809 | snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci)); |
1da177e4 LT |
1810 | return -ENXIO; |
1811 | } | |
a1e21c90 TI |
1812 | return 0; |
1813 | } | |
1da177e4 | 1814 | |
a1e21c90 | 1815 | /* configure each codec instance */ |
e23e7a14 | 1816 | static int azx_codec_configure(struct azx *chip) |
a1e21c90 TI |
1817 | { |
1818 | struct hda_codec *codec; | |
1819 | list_for_each_entry(codec, &chip->bus->codec_list, list) { | |
1820 | snd_hda_codec_configure(codec); | |
1821 | } | |
1da177e4 LT |
1822 | return 0; |
1823 | } | |
1824 | ||
1825 | ||
1826 | /* | |
1827 | * PCM support | |
1828 | */ | |
1829 | ||
1830 | /* assign a stream for the PCM */ | |
ef18bede WF |
1831 | static inline struct azx_dev * |
1832 | azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) | |
1da177e4 | 1833 | { |
07e4ca50 | 1834 | int dev, i, nums; |
ef18bede | 1835 | struct azx_dev *res = NULL; |
d5cf9911 TI |
1836 | /* make a non-zero unique key for the substream */ |
1837 | int key = (substream->pcm->device << 16) | (substream->number << 2) | | |
1838 | (substream->stream + 1); | |
ef18bede WF |
1839 | |
1840 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
07e4ca50 TI |
1841 | dev = chip->playback_index_offset; |
1842 | nums = chip->playback_streams; | |
1843 | } else { | |
1844 | dev = chip->capture_index_offset; | |
1845 | nums = chip->capture_streams; | |
1846 | } | |
eb49faa6 TI |
1847 | for (i = 0; i < nums; i++, dev++) { |
1848 | struct azx_dev *azx_dev = &chip->azx_dev[dev]; | |
1849 | dsp_lock(azx_dev); | |
1850 | if (!azx_dev->opened && !dsp_is_locked(azx_dev)) { | |
1851 | res = azx_dev; | |
1852 | if (res->assigned_key == key) { | |
1853 | res->opened = 1; | |
1854 | res->assigned_key = key; | |
1855 | dsp_unlock(azx_dev); | |
1856 | return azx_dev; | |
1857 | } | |
1da177e4 | 1858 | } |
eb49faa6 TI |
1859 | dsp_unlock(azx_dev); |
1860 | } | |
ef18bede | 1861 | if (res) { |
eb49faa6 | 1862 | dsp_lock(res); |
ef18bede | 1863 | res->opened = 1; |
d5cf9911 | 1864 | res->assigned_key = key; |
eb49faa6 | 1865 | dsp_unlock(res); |
ef18bede WF |
1866 | } |
1867 | return res; | |
1da177e4 LT |
1868 | } |
1869 | ||
1870 | /* release the assigned stream */ | |
a98f90fd | 1871 | static inline void azx_release_device(struct azx_dev *azx_dev) |
1da177e4 LT |
1872 | { |
1873 | azx_dev->opened = 0; | |
1874 | } | |
1875 | ||
5d890f59 PLB |
1876 | static cycle_t azx_cc_read(const struct cyclecounter *cc) |
1877 | { | |
1878 | struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc); | |
1879 | struct snd_pcm_substream *substream = azx_dev->substream; | |
1880 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1881 | struct azx *chip = apcm->chip; | |
1882 | ||
1883 | return azx_readl(chip, WALLCLK); | |
1884 | } | |
1885 | ||
1886 | static void azx_timecounter_init(struct snd_pcm_substream *substream, | |
1887 | bool force, cycle_t last) | |
1888 | { | |
1889 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1890 | struct timecounter *tc = &azx_dev->azx_tc; | |
1891 | struct cyclecounter *cc = &azx_dev->azx_cc; | |
1892 | u64 nsec; | |
1893 | ||
1894 | cc->read = azx_cc_read; | |
1895 | cc->mask = CLOCKSOURCE_MASK(32); | |
1896 | ||
1897 | /* | |
1898 | * Converting from 24 MHz to ns means applying a 125/3 factor. | |
1899 | * To avoid any saturation issues in intermediate operations, | |
1900 | * the 125 factor is applied first. The division is applied | |
1901 | * last after reading the timecounter value. | |
1902 | * Applying the 1/3 factor as part of the multiplication | |
1903 | * requires at least 20 bits for a decent precision, however | |
1904 | * overflows occur after about 4 hours or less, not a option. | |
1905 | */ | |
1906 | ||
1907 | cc->mult = 125; /* saturation after 195 years */ | |
1908 | cc->shift = 0; | |
1909 | ||
1910 | nsec = 0; /* audio time is elapsed time since trigger */ | |
1911 | timecounter_init(tc, cc, nsec); | |
1912 | if (force) | |
1913 | /* | |
1914 | * force timecounter to use predefined value, | |
1915 | * used for synchronized starts | |
1916 | */ | |
1917 | tc->cycle_last = last; | |
1918 | } | |
1919 | ||
ae03bbb8 | 1920 | static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream, |
78daea29 DR |
1921 | u64 nsec) |
1922 | { | |
1923 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1924 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
1925 | u64 codec_frames, codec_nsecs; | |
1926 | ||
1927 | if (!hinfo->ops.get_delay) | |
1928 | return nsec; | |
1929 | ||
1930 | codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream); | |
1931 | codec_nsecs = div_u64(codec_frames * 1000000000LL, | |
1932 | substream->runtime->rate); | |
1933 | ||
ae03bbb8 DR |
1934 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
1935 | return nsec + codec_nsecs; | |
1936 | ||
78daea29 DR |
1937 | return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; |
1938 | } | |
1939 | ||
5d890f59 PLB |
1940 | static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream, |
1941 | struct timespec *ts) | |
1942 | { | |
1943 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1944 | u64 nsec; | |
1945 | ||
1946 | nsec = timecounter_read(&azx_dev->azx_tc); | |
1947 | nsec = div_u64(nsec, 3); /* can be optimized */ | |
ae03bbb8 | 1948 | nsec = azx_adjust_codec_delay(substream, nsec); |
5d890f59 PLB |
1949 | |
1950 | *ts = ns_to_timespec(nsec); | |
1951 | ||
1952 | return 0; | |
1953 | } | |
1954 | ||
a98f90fd | 1955 | static struct snd_pcm_hardware azx_pcm_hw = { |
d01ce99f TI |
1956 | .info = (SNDRV_PCM_INFO_MMAP | |
1957 | SNDRV_PCM_INFO_INTERLEAVED | | |
1da177e4 LT |
1958 | SNDRV_PCM_INFO_BLOCK_TRANSFER | |
1959 | SNDRV_PCM_INFO_MMAP_VALID | | |
927fc866 PM |
1960 | /* No full-resume yet implemented */ |
1961 | /* SNDRV_PCM_INFO_RESUME |*/ | |
850f0e52 | 1962 | SNDRV_PCM_INFO_PAUSE | |
7bb8fb70 | 1963 | SNDRV_PCM_INFO_SYNC_START | |
5d890f59 | 1964 | SNDRV_PCM_INFO_HAS_WALL_CLOCK | |
7bb8fb70 | 1965 | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), |
1da177e4 LT |
1966 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
1967 | .rates = SNDRV_PCM_RATE_48000, | |
1968 | .rate_min = 48000, | |
1969 | .rate_max = 48000, | |
1970 | .channels_min = 2, | |
1971 | .channels_max = 2, | |
1972 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, | |
1973 | .period_bytes_min = 128, | |
1974 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | |
1975 | .periods_min = 2, | |
1976 | .periods_max = AZX_MAX_FRAG, | |
1977 | .fifo_size = 0, | |
1978 | }; | |
1979 | ||
a98f90fd | 1980 | static int azx_pcm_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
1981 | { |
1982 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1983 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
a98f90fd TI |
1984 | struct azx *chip = apcm->chip; |
1985 | struct azx_dev *azx_dev; | |
1986 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1987 | unsigned long flags; |
1988 | int err; | |
2ae66c26 | 1989 | int buff_step; |
1da177e4 | 1990 | |
62932df8 | 1991 | mutex_lock(&chip->open_mutex); |
ef18bede | 1992 | azx_dev = azx_assign_device(chip, substream); |
1da177e4 | 1993 | if (azx_dev == NULL) { |
62932df8 | 1994 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1995 | return -EBUSY; |
1996 | } | |
1997 | runtime->hw = azx_pcm_hw; | |
1998 | runtime->hw.channels_min = hinfo->channels_min; | |
1999 | runtime->hw.channels_max = hinfo->channels_max; | |
2000 | runtime->hw.formats = hinfo->formats; | |
2001 | runtime->hw.rates = hinfo->rates; | |
2002 | snd_pcm_limit_hw_rates(runtime); | |
2003 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | |
5d890f59 PLB |
2004 | |
2005 | /* avoid wrap-around with wall-clock */ | |
2006 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, | |
2007 | 20, | |
2008 | 178000000); | |
2009 | ||
52409aa6 | 2010 | if (chip->align_buffer_size) |
2ae66c26 PLB |
2011 | /* constrain buffer sizes to be multiple of 128 |
2012 | bytes. This is more efficient in terms of memory | |
2013 | access but isn't required by the HDA spec and | |
2014 | prevents users from specifying exact period/buffer | |
2015 | sizes. For example for 44.1kHz, a period size set | |
2016 | to 20ms will be rounded to 19.59ms. */ | |
2017 | buff_step = 128; | |
2018 | else | |
2019 | /* Don't enforce steps on buffer sizes, still need to | |
2020 | be multiple of 4 bytes (HDA spec). Tested on Intel | |
2021 | HDA controllers, may not work on all devices where | |
2022 | option needs to be disabled */ | |
2023 | buff_step = 4; | |
2024 | ||
5f1545bc | 2025 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, |
2ae66c26 | 2026 | buff_step); |
5f1545bc | 2027 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, |
2ae66c26 | 2028 | buff_step); |
b4a91cf0 | 2029 | snd_hda_power_up_d3wait(apcm->codec); |
d01ce99f TI |
2030 | err = hinfo->ops.open(hinfo, apcm->codec, substream); |
2031 | if (err < 0) { | |
1da177e4 | 2032 | azx_release_device(azx_dev); |
cb53c626 | 2033 | snd_hda_power_down(apcm->codec); |
62932df8 | 2034 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
2035 | return err; |
2036 | } | |
70d321e6 | 2037 | snd_pcm_limit_hw_rates(runtime); |
aba66536 TI |
2038 | /* sanity check */ |
2039 | if (snd_BUG_ON(!runtime->hw.channels_min) || | |
2040 | snd_BUG_ON(!runtime->hw.channels_max) || | |
2041 | snd_BUG_ON(!runtime->hw.formats) || | |
2042 | snd_BUG_ON(!runtime->hw.rates)) { | |
2043 | azx_release_device(azx_dev); | |
2044 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
2045 | snd_hda_power_down(apcm->codec); | |
2046 | mutex_unlock(&chip->open_mutex); | |
2047 | return -EINVAL; | |
2048 | } | |
5d890f59 PLB |
2049 | |
2050 | /* disable WALLCLOCK timestamps for capture streams | |
2051 | until we figure out how to handle digital inputs */ | |
2052 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
2053 | runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; | |
2054 | ||
1da177e4 LT |
2055 | spin_lock_irqsave(&chip->reg_lock, flags); |
2056 | azx_dev->substream = substream; | |
2057 | azx_dev->running = 0; | |
2058 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
2059 | ||
2060 | runtime->private_data = azx_dev; | |
850f0e52 | 2061 | snd_pcm_set_sync(substream); |
62932df8 | 2062 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
2063 | return 0; |
2064 | } | |
2065 | ||
a98f90fd | 2066 | static int azx_pcm_close(struct snd_pcm_substream *substream) |
1da177e4 LT |
2067 | { |
2068 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
2069 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
a98f90fd TI |
2070 | struct azx *chip = apcm->chip; |
2071 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 LT |
2072 | unsigned long flags; |
2073 | ||
62932df8 | 2074 | mutex_lock(&chip->open_mutex); |
1da177e4 LT |
2075 | spin_lock_irqsave(&chip->reg_lock, flags); |
2076 | azx_dev->substream = NULL; | |
2077 | azx_dev->running = 0; | |
2078 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
2079 | azx_release_device(azx_dev); | |
2080 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
cb53c626 | 2081 | snd_hda_power_down(apcm->codec); |
62932df8 | 2082 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
2083 | return 0; |
2084 | } | |
2085 | ||
d01ce99f TI |
2086 | static int azx_pcm_hw_params(struct snd_pcm_substream *substream, |
2087 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 | 2088 | { |
27fe48d9 TI |
2089 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
2090 | struct azx *chip = apcm->chip; | |
97b71c94 | 2091 | struct azx_dev *azx_dev = get_azx_dev(substream); |
27fe48d9 | 2092 | int ret; |
97b71c94 | 2093 | |
eb49faa6 TI |
2094 | dsp_lock(azx_dev); |
2095 | if (dsp_is_locked(azx_dev)) { | |
2096 | ret = -EBUSY; | |
2097 | goto unlock; | |
2098 | } | |
2099 | ||
9ddf1aeb | 2100 | mark_runtime_wc(chip, azx_dev, substream, false); |
97b71c94 TI |
2101 | azx_dev->bufsize = 0; |
2102 | azx_dev->period_bytes = 0; | |
2103 | azx_dev->format_val = 0; | |
27fe48d9 | 2104 | ret = snd_pcm_lib_malloc_pages(substream, |
d01ce99f | 2105 | params_buffer_bytes(hw_params)); |
27fe48d9 | 2106 | if (ret < 0) |
eb49faa6 | 2107 | goto unlock; |
9ddf1aeb | 2108 | mark_runtime_wc(chip, azx_dev, substream, true); |
eb49faa6 TI |
2109 | unlock: |
2110 | dsp_unlock(azx_dev); | |
27fe48d9 | 2111 | return ret; |
1da177e4 LT |
2112 | } |
2113 | ||
a98f90fd | 2114 | static int azx_pcm_hw_free(struct snd_pcm_substream *substream) |
1da177e4 LT |
2115 | { |
2116 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd | 2117 | struct azx_dev *azx_dev = get_azx_dev(substream); |
27fe48d9 | 2118 | struct azx *chip = apcm->chip; |
1da177e4 LT |
2119 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
2120 | ||
2121 | /* reset BDL address */ | |
eb49faa6 TI |
2122 | dsp_lock(azx_dev); |
2123 | if (!dsp_is_locked(azx_dev)) { | |
2124 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
2125 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
2126 | azx_sd_writel(azx_dev, SD_CTL, 0); | |
2127 | azx_dev->bufsize = 0; | |
2128 | azx_dev->period_bytes = 0; | |
2129 | azx_dev->format_val = 0; | |
2130 | } | |
1da177e4 | 2131 | |
eb541337 | 2132 | snd_hda_codec_cleanup(apcm->codec, hinfo, substream); |
1da177e4 | 2133 | |
9ddf1aeb | 2134 | mark_runtime_wc(chip, azx_dev, substream, false); |
eb49faa6 TI |
2135 | azx_dev->prepared = 0; |
2136 | dsp_unlock(azx_dev); | |
1da177e4 LT |
2137 | return snd_pcm_lib_free_pages(substream); |
2138 | } | |
2139 | ||
a98f90fd | 2140 | static int azx_pcm_prepare(struct snd_pcm_substream *substream) |
1da177e4 LT |
2141 | { |
2142 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd TI |
2143 | struct azx *chip = apcm->chip; |
2144 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 | 2145 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
a98f90fd | 2146 | struct snd_pcm_runtime *runtime = substream->runtime; |
62b7e5e0 | 2147 | unsigned int bufsize, period_bytes, format_val, stream_tag; |
97b71c94 | 2148 | int err; |
7c935976 SW |
2149 | struct hda_spdif_out *spdif = |
2150 | snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid); | |
2151 | unsigned short ctls = spdif ? spdif->ctls : 0; | |
1da177e4 | 2152 | |
eb49faa6 TI |
2153 | dsp_lock(azx_dev); |
2154 | if (dsp_is_locked(azx_dev)) { | |
2155 | err = -EBUSY; | |
2156 | goto unlock; | |
2157 | } | |
2158 | ||
fa00e046 | 2159 | azx_stream_reset(chip, azx_dev); |
97b71c94 TI |
2160 | format_val = snd_hda_calc_stream_format(runtime->rate, |
2161 | runtime->channels, | |
2162 | runtime->format, | |
32c168c8 | 2163 | hinfo->maxbps, |
7c935976 | 2164 | ctls); |
97b71c94 | 2165 | if (!format_val) { |
d01ce99f | 2166 | snd_printk(KERN_ERR SFX |
445a51b3 DB |
2167 | "%s: invalid format_val, rate=%d, ch=%d, format=%d\n", |
2168 | pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format); | |
eb49faa6 TI |
2169 | err = -EINVAL; |
2170 | goto unlock; | |
1da177e4 LT |
2171 | } |
2172 | ||
97b71c94 TI |
2173 | bufsize = snd_pcm_lib_buffer_bytes(substream); |
2174 | period_bytes = snd_pcm_lib_period_bytes(substream); | |
2175 | ||
445a51b3 DB |
2176 | snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", |
2177 | pci_name(chip->pci), bufsize, format_val); | |
97b71c94 TI |
2178 | |
2179 | if (bufsize != azx_dev->bufsize || | |
2180 | period_bytes != azx_dev->period_bytes || | |
915bf29e TI |
2181 | format_val != azx_dev->format_val || |
2182 | runtime->no_period_wakeup != azx_dev->no_period_wakeup) { | |
97b71c94 TI |
2183 | azx_dev->bufsize = bufsize; |
2184 | azx_dev->period_bytes = period_bytes; | |
2185 | azx_dev->format_val = format_val; | |
915bf29e | 2186 | azx_dev->no_period_wakeup = runtime->no_period_wakeup; |
97b71c94 TI |
2187 | err = azx_setup_periods(chip, substream, azx_dev); |
2188 | if (err < 0) | |
eb49faa6 | 2189 | goto unlock; |
97b71c94 TI |
2190 | } |
2191 | ||
e5463720 JK |
2192 | /* wallclk has 24Mhz clock source */ |
2193 | azx_dev->period_wallclk = (((runtime->period_size * 24000) / | |
2194 | runtime->rate) * 1000); | |
1da177e4 LT |
2195 | azx_setup_controller(chip, azx_dev); |
2196 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
2197 | azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; | |
2198 | else | |
2199 | azx_dev->fifo_size = 0; | |
2200 | ||
62b7e5e0 TI |
2201 | stream_tag = azx_dev->stream_tag; |
2202 | /* CA-IBG chips need the playback stream starting from 1 */ | |
9477c58e | 2203 | if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) && |
62b7e5e0 TI |
2204 | stream_tag > chip->capture_streams) |
2205 | stream_tag -= chip->capture_streams; | |
eb49faa6 | 2206 | err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, |
eb541337 | 2207 | azx_dev->format_val, substream); |
eb49faa6 TI |
2208 | |
2209 | unlock: | |
2210 | if (!err) | |
2211 | azx_dev->prepared = 1; | |
2212 | dsp_unlock(azx_dev); | |
2213 | return err; | |
1da177e4 LT |
2214 | } |
2215 | ||
a98f90fd | 2216 | static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 LT |
2217 | { |
2218 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd | 2219 | struct azx *chip = apcm->chip; |
850f0e52 TI |
2220 | struct azx_dev *azx_dev; |
2221 | struct snd_pcm_substream *s; | |
fa00e046 | 2222 | int rstart = 0, start, nsync = 0, sbits = 0; |
850f0e52 | 2223 | int nwait, timeout; |
1da177e4 | 2224 | |
1a8506d4 TI |
2225 | azx_dev = get_azx_dev(substream); |
2226 | trace_azx_pcm_trigger(chip, azx_dev, cmd); | |
2227 | ||
eb49faa6 TI |
2228 | if (dsp_is_locked(azx_dev) || !azx_dev->prepared) |
2229 | return -EPIPE; | |
2230 | ||
1da177e4 | 2231 | switch (cmd) { |
fa00e046 JK |
2232 | case SNDRV_PCM_TRIGGER_START: |
2233 | rstart = 1; | |
1da177e4 LT |
2234 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
2235 | case SNDRV_PCM_TRIGGER_RESUME: | |
850f0e52 | 2236 | start = 1; |
1da177e4 LT |
2237 | break; |
2238 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
47123197 | 2239 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1da177e4 | 2240 | case SNDRV_PCM_TRIGGER_STOP: |
850f0e52 | 2241 | start = 0; |
1da177e4 LT |
2242 | break; |
2243 | default: | |
850f0e52 TI |
2244 | return -EINVAL; |
2245 | } | |
2246 | ||
2247 | snd_pcm_group_for_each_entry(s, substream) { | |
2248 | if (s->pcm->card != substream->pcm->card) | |
2249 | continue; | |
2250 | azx_dev = get_azx_dev(s); | |
2251 | sbits |= 1 << azx_dev->index; | |
2252 | nsync++; | |
2253 | snd_pcm_trigger_done(s, substream); | |
2254 | } | |
2255 | ||
2256 | spin_lock(&chip->reg_lock); | |
172d3b20 PLB |
2257 | |
2258 | /* first, set SYNC bits of corresponding streams */ | |
2259 | if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) | |
2260 | azx_writel(chip, OLD_SSYNC, | |
2261 | azx_readl(chip, OLD_SSYNC) | sbits); | |
2262 | else | |
2263 | azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits); | |
2264 | ||
850f0e52 TI |
2265 | snd_pcm_group_for_each_entry(s, substream) { |
2266 | if (s->pcm->card != substream->pcm->card) | |
2267 | continue; | |
2268 | azx_dev = get_azx_dev(s); | |
e5463720 JK |
2269 | if (start) { |
2270 | azx_dev->start_wallclk = azx_readl(chip, WALLCLK); | |
2271 | if (!rstart) | |
2272 | azx_dev->start_wallclk -= | |
2273 | azx_dev->period_wallclk; | |
850f0e52 | 2274 | azx_stream_start(chip, azx_dev); |
e5463720 | 2275 | } else { |
850f0e52 | 2276 | azx_stream_stop(chip, azx_dev); |
e5463720 | 2277 | } |
850f0e52 | 2278 | azx_dev->running = start; |
1da177e4 LT |
2279 | } |
2280 | spin_unlock(&chip->reg_lock); | |
850f0e52 | 2281 | if (start) { |
850f0e52 TI |
2282 | /* wait until all FIFOs get ready */ |
2283 | for (timeout = 5000; timeout; timeout--) { | |
2284 | nwait = 0; | |
2285 | snd_pcm_group_for_each_entry(s, substream) { | |
2286 | if (s->pcm->card != substream->pcm->card) | |
2287 | continue; | |
2288 | azx_dev = get_azx_dev(s); | |
2289 | if (!(azx_sd_readb(azx_dev, SD_STS) & | |
2290 | SD_STS_FIFO_READY)) | |
2291 | nwait++; | |
2292 | } | |
2293 | if (!nwait) | |
2294 | break; | |
2295 | cpu_relax(); | |
2296 | } | |
2297 | } else { | |
2298 | /* wait until all RUN bits are cleared */ | |
2299 | for (timeout = 5000; timeout; timeout--) { | |
2300 | nwait = 0; | |
2301 | snd_pcm_group_for_each_entry(s, substream) { | |
2302 | if (s->pcm->card != substream->pcm->card) | |
2303 | continue; | |
2304 | azx_dev = get_azx_dev(s); | |
2305 | if (azx_sd_readb(azx_dev, SD_CTL) & | |
2306 | SD_CTL_DMA_START) | |
2307 | nwait++; | |
2308 | } | |
2309 | if (!nwait) | |
2310 | break; | |
2311 | cpu_relax(); | |
2312 | } | |
1da177e4 | 2313 | } |
172d3b20 PLB |
2314 | spin_lock(&chip->reg_lock); |
2315 | /* reset SYNC bits */ | |
2316 | if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) | |
2317 | azx_writel(chip, OLD_SSYNC, | |
2318 | azx_readl(chip, OLD_SSYNC) & ~sbits); | |
2319 | else | |
2320 | azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits); | |
5d890f59 PLB |
2321 | if (start) { |
2322 | azx_timecounter_init(substream, 0, 0); | |
2323 | if (nsync > 1) { | |
2324 | cycle_t cycle_last; | |
2325 | ||
2326 | /* same start cycle for master and group */ | |
2327 | azx_dev = get_azx_dev(substream); | |
2328 | cycle_last = azx_dev->azx_tc.cycle_last; | |
2329 | ||
2330 | snd_pcm_group_for_each_entry(s, substream) { | |
2331 | if (s->pcm->card != substream->pcm->card) | |
2332 | continue; | |
2333 | azx_timecounter_init(s, 1, cycle_last); | |
2334 | } | |
2335 | } | |
2336 | } | |
172d3b20 | 2337 | spin_unlock(&chip->reg_lock); |
850f0e52 | 2338 | return 0; |
1da177e4 LT |
2339 | } |
2340 | ||
0e153474 JC |
2341 | /* get the current DMA position with correction on VIA chips */ |
2342 | static unsigned int azx_via_get_position(struct azx *chip, | |
2343 | struct azx_dev *azx_dev) | |
2344 | { | |
2345 | unsigned int link_pos, mini_pos, bound_pos; | |
2346 | unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; | |
2347 | unsigned int fifo_size; | |
2348 | ||
2349 | link_pos = azx_sd_readl(azx_dev, SD_LPIB); | |
b4a655e8 | 2350 | if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
0e153474 JC |
2351 | /* Playback, no problem using link position */ |
2352 | return link_pos; | |
2353 | } | |
2354 | ||
2355 | /* Capture */ | |
2356 | /* For new chipset, | |
2357 | * use mod to get the DMA position just like old chipset | |
2358 | */ | |
2359 | mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); | |
2360 | mod_dma_pos %= azx_dev->period_bytes; | |
2361 | ||
2362 | /* azx_dev->fifo_size can't get FIFO size of in stream. | |
2363 | * Get from base address + offset. | |
2364 | */ | |
2365 | fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); | |
2366 | ||
2367 | if (azx_dev->insufficient) { | |
2368 | /* Link position never gather than FIFO size */ | |
2369 | if (link_pos <= fifo_size) | |
2370 | return 0; | |
2371 | ||
2372 | azx_dev->insufficient = 0; | |
2373 | } | |
2374 | ||
2375 | if (link_pos <= fifo_size) | |
2376 | mini_pos = azx_dev->bufsize + link_pos - fifo_size; | |
2377 | else | |
2378 | mini_pos = link_pos - fifo_size; | |
2379 | ||
2380 | /* Find nearest previous boudary */ | |
2381 | mod_mini_pos = mini_pos % azx_dev->period_bytes; | |
2382 | mod_link_pos = link_pos % azx_dev->period_bytes; | |
2383 | if (mod_link_pos >= fifo_size) | |
2384 | bound_pos = link_pos - mod_link_pos; | |
2385 | else if (mod_dma_pos >= mod_mini_pos) | |
2386 | bound_pos = mini_pos - mod_mini_pos; | |
2387 | else { | |
2388 | bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; | |
2389 | if (bound_pos >= azx_dev->bufsize) | |
2390 | bound_pos = 0; | |
2391 | } | |
2392 | ||
2393 | /* Calculate real DMA position we want */ | |
2394 | return bound_pos + mod_dma_pos; | |
2395 | } | |
2396 | ||
9ad593f6 | 2397 | static unsigned int azx_get_position(struct azx *chip, |
798cb7e8 TI |
2398 | struct azx_dev *azx_dev, |
2399 | bool with_check) | |
1da177e4 | 2400 | { |
21229613 TI |
2401 | struct snd_pcm_substream *substream = azx_dev->substream; |
2402 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1da177e4 | 2403 | unsigned int pos; |
21229613 TI |
2404 | int stream = substream->stream; |
2405 | struct hda_pcm_stream *hinfo = apcm->hinfo[stream]; | |
1a8506d4 | 2406 | int delay = 0; |
1da177e4 | 2407 | |
4cb36310 DH |
2408 | switch (chip->position_fix[stream]) { |
2409 | case POS_FIX_LPIB: | |
2410 | /* read LPIB */ | |
2411 | pos = azx_sd_readl(azx_dev, SD_LPIB); | |
2412 | break; | |
2413 | case POS_FIX_VIACOMBO: | |
0e153474 | 2414 | pos = azx_via_get_position(chip, azx_dev); |
4cb36310 DH |
2415 | break; |
2416 | default: | |
2417 | /* use the position buffer */ | |
2418 | pos = le32_to_cpu(*azx_dev->posbuf); | |
798cb7e8 | 2419 | if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) { |
a810364a TI |
2420 | if (!pos || pos == (u32)-1) { |
2421 | printk(KERN_WARNING | |
2422 | "hda-intel: Invalid position buffer, " | |
2423 | "using LPIB read method instead.\n"); | |
2424 | chip->position_fix[stream] = POS_FIX_LPIB; | |
2425 | pos = azx_sd_readl(azx_dev, SD_LPIB); | |
2426 | } else | |
2427 | chip->position_fix[stream] = POS_FIX_POSBUF; | |
2428 | } | |
2429 | break; | |
c74db86b | 2430 | } |
4cb36310 | 2431 | |
1da177e4 LT |
2432 | if (pos >= azx_dev->bufsize) |
2433 | pos = 0; | |
90accc58 PLB |
2434 | |
2435 | /* calculate runtime delay from LPIB */ | |
21229613 | 2436 | if (substream->runtime && |
90accc58 PLB |
2437 | chip->position_fix[stream] == POS_FIX_POSBUF && |
2438 | (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { | |
2439 | unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB); | |
90accc58 PLB |
2440 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
2441 | delay = pos - lpib_pos; | |
2442 | else | |
2443 | delay = lpib_pos - pos; | |
2444 | if (delay < 0) | |
2445 | delay += azx_dev->bufsize; | |
2446 | if (delay >= azx_dev->period_bytes) { | |
1f04661f | 2447 | snd_printk(KERN_WARNING SFX |
445a51b3 | 2448 | "%s: Unstable LPIB (%d >= %d); " |
1f04661f | 2449 | "disabling LPIB delay counting\n", |
445a51b3 | 2450 | pci_name(chip->pci), delay, azx_dev->period_bytes); |
1f04661f TI |
2451 | delay = 0; |
2452 | chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; | |
90accc58 | 2453 | } |
21229613 | 2454 | delay = bytes_to_frames(substream->runtime, delay); |
90accc58 | 2455 | } |
21229613 TI |
2456 | |
2457 | if (substream->runtime) { | |
2458 | if (hinfo->ops.get_delay) | |
2459 | delay += hinfo->ops.get_delay(hinfo, apcm->codec, | |
2460 | substream); | |
2461 | substream->runtime->delay = delay; | |
2462 | } | |
2463 | ||
1a8506d4 | 2464 | trace_azx_get_position(chip, azx_dev, pos, delay); |
9ad593f6 TI |
2465 | return pos; |
2466 | } | |
2467 | ||
2468 | static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) | |
2469 | { | |
2470 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
2471 | struct azx *chip = apcm->chip; | |
2472 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
2473 | return bytes_to_frames(substream->runtime, | |
798cb7e8 | 2474 | azx_get_position(chip, azx_dev, false)); |
9ad593f6 TI |
2475 | } |
2476 | ||
2477 | /* | |
2478 | * Check whether the current DMA position is acceptable for updating | |
2479 | * periods. Returns non-zero if it's OK. | |
2480 | * | |
2481 | * Many HD-audio controllers appear pretty inaccurate about | |
2482 | * the update-IRQ timing. The IRQ is issued before actually the | |
2483 | * data is processed. So, we need to process it afterwords in a | |
2484 | * workqueue. | |
2485 | */ | |
2486 | static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) | |
2487 | { | |
e5463720 | 2488 | u32 wallclk; |
9ad593f6 TI |
2489 | unsigned int pos; |
2490 | ||
f48f606d JK |
2491 | wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; |
2492 | if (wallclk < (azx_dev->period_wallclk * 2) / 3) | |
fa00e046 | 2493 | return -1; /* bogus (too early) interrupt */ |
fa00e046 | 2494 | |
798cb7e8 | 2495 | pos = azx_get_position(chip, azx_dev, true); |
9ad593f6 | 2496 | |
d6d8bf54 TI |
2497 | if (WARN_ONCE(!azx_dev->period_bytes, |
2498 | "hda-intel: zero azx_dev->period_bytes")) | |
f48f606d | 2499 | return -1; /* this shouldn't happen! */ |
edb39935 | 2500 | if (wallclk < (azx_dev->period_wallclk * 5) / 4 && |
f48f606d JK |
2501 | pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) |
2502 | /* NG - it's below the first next period boundary */ | |
2503 | return bdl_pos_adj[chip->dev_index] ? 0 : -1; | |
edb39935 | 2504 | azx_dev->start_wallclk += wallclk; |
9ad593f6 TI |
2505 | return 1; /* OK, it's fine */ |
2506 | } | |
2507 | ||
2508 | /* | |
2509 | * The work for pending PCM period updates. | |
2510 | */ | |
2511 | static void azx_irq_pending_work(struct work_struct *work) | |
2512 | { | |
2513 | struct azx *chip = container_of(work, struct azx, irq_pending_work); | |
e5463720 | 2514 | int i, pending, ok; |
9ad593f6 | 2515 | |
a6a950a8 TI |
2516 | if (!chip->irq_pending_warned) { |
2517 | printk(KERN_WARNING | |
2518 | "hda-intel: IRQ timing workaround is activated " | |
2519 | "for card #%d. Suggest a bigger bdl_pos_adj.\n", | |
2520 | chip->card->number); | |
2521 | chip->irq_pending_warned = 1; | |
2522 | } | |
2523 | ||
9ad593f6 TI |
2524 | for (;;) { |
2525 | pending = 0; | |
2526 | spin_lock_irq(&chip->reg_lock); | |
2527 | for (i = 0; i < chip->num_streams; i++) { | |
2528 | struct azx_dev *azx_dev = &chip->azx_dev[i]; | |
2529 | if (!azx_dev->irq_pending || | |
2530 | !azx_dev->substream || | |
2531 | !azx_dev->running) | |
2532 | continue; | |
e5463720 JK |
2533 | ok = azx_position_ok(chip, azx_dev); |
2534 | if (ok > 0) { | |
9ad593f6 TI |
2535 | azx_dev->irq_pending = 0; |
2536 | spin_unlock(&chip->reg_lock); | |
2537 | snd_pcm_period_elapsed(azx_dev->substream); | |
2538 | spin_lock(&chip->reg_lock); | |
e5463720 JK |
2539 | } else if (ok < 0) { |
2540 | pending = 0; /* too early */ | |
9ad593f6 TI |
2541 | } else |
2542 | pending++; | |
2543 | } | |
2544 | spin_unlock_irq(&chip->reg_lock); | |
2545 | if (!pending) | |
2546 | return; | |
08af495f | 2547 | msleep(1); |
9ad593f6 TI |
2548 | } |
2549 | } | |
2550 | ||
2551 | /* clear irq_pending flags and assure no on-going workq */ | |
2552 | static void azx_clear_irq_pending(struct azx *chip) | |
2553 | { | |
2554 | int i; | |
2555 | ||
2556 | spin_lock_irq(&chip->reg_lock); | |
2557 | for (i = 0; i < chip->num_streams; i++) | |
2558 | chip->azx_dev[i].irq_pending = 0; | |
2559 | spin_unlock_irq(&chip->reg_lock); | |
1da177e4 LT |
2560 | } |
2561 | ||
27fe48d9 TI |
2562 | #ifdef CONFIG_X86 |
2563 | static int azx_pcm_mmap(struct snd_pcm_substream *substream, | |
2564 | struct vm_area_struct *area) | |
2565 | { | |
2566 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
2567 | struct azx *chip = apcm->chip; | |
2568 | if (!azx_snoop(chip)) | |
2569 | area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); | |
2570 | return snd_pcm_lib_default_mmap(substream, area); | |
2571 | } | |
2572 | #else | |
2573 | #define azx_pcm_mmap NULL | |
2574 | #endif | |
2575 | ||
a98f90fd | 2576 | static struct snd_pcm_ops azx_pcm_ops = { |
1da177e4 LT |
2577 | .open = azx_pcm_open, |
2578 | .close = azx_pcm_close, | |
2579 | .ioctl = snd_pcm_lib_ioctl, | |
2580 | .hw_params = azx_pcm_hw_params, | |
2581 | .hw_free = azx_pcm_hw_free, | |
2582 | .prepare = azx_pcm_prepare, | |
2583 | .trigger = azx_pcm_trigger, | |
2584 | .pointer = azx_pcm_pointer, | |
5d890f59 | 2585 | .wall_clock = azx_get_wallclock_tstamp, |
27fe48d9 | 2586 | .mmap = azx_pcm_mmap, |
4ce107b9 | 2587 | .page = snd_pcm_sgbuf_ops_page, |
1da177e4 LT |
2588 | }; |
2589 | ||
a98f90fd | 2590 | static void azx_pcm_free(struct snd_pcm *pcm) |
1da177e4 | 2591 | { |
176d5335 TI |
2592 | struct azx_pcm *apcm = pcm->private_data; |
2593 | if (apcm) { | |
01b65bfb | 2594 | list_del(&apcm->list); |
176d5335 TI |
2595 | kfree(apcm); |
2596 | } | |
1da177e4 LT |
2597 | } |
2598 | ||
acfa634f TI |
2599 | #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) |
2600 | ||
176d5335 | 2601 | static int |
33fa35ed TI |
2602 | azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, |
2603 | struct hda_pcm *cpcm) | |
1da177e4 | 2604 | { |
33fa35ed | 2605 | struct azx *chip = bus->private_data; |
a98f90fd | 2606 | struct snd_pcm *pcm; |
1da177e4 | 2607 | struct azx_pcm *apcm; |
176d5335 | 2608 | int pcm_dev = cpcm->device; |
acfa634f | 2609 | unsigned int size; |
176d5335 | 2610 | int s, err; |
1da177e4 | 2611 | |
01b65bfb TI |
2612 | list_for_each_entry(apcm, &chip->pcm_list, list) { |
2613 | if (apcm->pcm->device == pcm_dev) { | |
445a51b3 DB |
2614 | snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n", |
2615 | pci_name(chip->pci), pcm_dev); | |
01b65bfb TI |
2616 | return -EBUSY; |
2617 | } | |
176d5335 TI |
2618 | } |
2619 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, | |
2620 | cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, | |
2621 | cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, | |
1da177e4 LT |
2622 | &pcm); |
2623 | if (err < 0) | |
2624 | return err; | |
18cb7109 | 2625 | strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); |
176d5335 | 2626 | apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); |
1da177e4 LT |
2627 | if (apcm == NULL) |
2628 | return -ENOMEM; | |
2629 | apcm->chip = chip; | |
01b65bfb | 2630 | apcm->pcm = pcm; |
1da177e4 | 2631 | apcm->codec = codec; |
1da177e4 LT |
2632 | pcm->private_data = apcm; |
2633 | pcm->private_free = azx_pcm_free; | |
176d5335 TI |
2634 | if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) |
2635 | pcm->dev_class = SNDRV_PCM_CLASS_MODEM; | |
01b65bfb | 2636 | list_add_tail(&apcm->list, &chip->pcm_list); |
176d5335 TI |
2637 | cpcm->pcm = pcm; |
2638 | for (s = 0; s < 2; s++) { | |
2639 | apcm->hinfo[s] = &cpcm->stream[s]; | |
2640 | if (cpcm->stream[s].substreams) | |
2641 | snd_pcm_set_ops(pcm, s, &azx_pcm_ops); | |
2642 | } | |
2643 | /* buffer pre-allocation */ | |
acfa634f TI |
2644 | size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; |
2645 | if (size > MAX_PREALLOC_SIZE) | |
2646 | size = MAX_PREALLOC_SIZE; | |
4ce107b9 | 2647 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, |
1da177e4 | 2648 | snd_dma_pci_data(chip->pci), |
acfa634f | 2649 | size, MAX_PREALLOC_SIZE); |
1da177e4 LT |
2650 | return 0; |
2651 | } | |
2652 | ||
2653 | /* | |
2654 | * mixer creation - all stuff is implemented in hda module | |
2655 | */ | |
e23e7a14 | 2656 | static int azx_mixer_create(struct azx *chip) |
1da177e4 LT |
2657 | { |
2658 | return snd_hda_build_controls(chip->bus); | |
2659 | } | |
2660 | ||
2661 | ||
2662 | /* | |
2663 | * initialize SD streams | |
2664 | */ | |
e23e7a14 | 2665 | static int azx_init_stream(struct azx *chip) |
1da177e4 LT |
2666 | { |
2667 | int i; | |
2668 | ||
2669 | /* initialize each stream (aka device) | |
d01ce99f TI |
2670 | * assign the starting bdl address to each stream (device) |
2671 | * and initialize | |
1da177e4 | 2672 | */ |
07e4ca50 | 2673 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 2674 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
929861c6 | 2675 | azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); |
1da177e4 LT |
2676 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
2677 | azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); | |
2678 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ | |
2679 | azx_dev->sd_int_sta_mask = 1 << i; | |
2680 | /* stream tag: must be non-zero and unique */ | |
2681 | azx_dev->index = i; | |
2682 | azx_dev->stream_tag = i + 1; | |
2683 | } | |
2684 | ||
2685 | return 0; | |
2686 | } | |
2687 | ||
68e7fffc TI |
2688 | static int azx_acquire_irq(struct azx *chip, int do_disconnect) |
2689 | { | |
437a5a46 TI |
2690 | if (request_irq(chip->pci->irq, azx_interrupt, |
2691 | chip->msi ? 0 : IRQF_SHARED, | |
934c2b6d | 2692 | KBUILD_MODNAME, chip)) { |
68e7fffc TI |
2693 | printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " |
2694 | "disabling device\n", chip->pci->irq); | |
2695 | if (do_disconnect) | |
2696 | snd_card_disconnect(chip->card); | |
2697 | return -1; | |
2698 | } | |
2699 | chip->irq = chip->pci->irq; | |
69e13418 | 2700 | pci_intx(chip->pci, !chip->msi); |
68e7fffc TI |
2701 | return 0; |
2702 | } | |
2703 | ||
1da177e4 | 2704 | |
cb53c626 TI |
2705 | static void azx_stop_chip(struct azx *chip) |
2706 | { | |
95e99fda | 2707 | if (!chip->initialized) |
cb53c626 TI |
2708 | return; |
2709 | ||
2710 | /* disable interrupts */ | |
2711 | azx_int_disable(chip); | |
2712 | azx_int_clear(chip); | |
2713 | ||
2714 | /* disable CORB/RIRB */ | |
2715 | azx_free_cmd_io(chip); | |
2716 | ||
2717 | /* disable position buffer */ | |
2718 | azx_writel(chip, DPLBASE, 0); | |
2719 | azx_writel(chip, DPUBASE, 0); | |
2720 | ||
2721 | chip->initialized = 0; | |
2722 | } | |
2723 | ||
1d1a4564 TI |
2724 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
2725 | /* | |
2726 | * DSP loading code (e.g. for CA0132) | |
2727 | */ | |
2728 | ||
2729 | /* use the first stream for loading DSP */ | |
2730 | static struct azx_dev * | |
2731 | azx_get_dsp_loader_dev(struct azx *chip) | |
2732 | { | |
2733 | return &chip->azx_dev[chip->playback_index_offset]; | |
2734 | } | |
2735 | ||
2736 | static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format, | |
2737 | unsigned int byte_size, | |
2738 | struct snd_dma_buffer *bufp) | |
2739 | { | |
2740 | u32 *bdl; | |
2741 | struct azx *chip = bus->private_data; | |
2742 | struct azx_dev *azx_dev; | |
2743 | int err; | |
2744 | ||
eb49faa6 TI |
2745 | azx_dev = azx_get_dsp_loader_dev(chip); |
2746 | ||
2747 | dsp_lock(azx_dev); | |
2748 | spin_lock_irq(&chip->reg_lock); | |
2749 | if (azx_dev->running || azx_dev->locked) { | |
2750 | spin_unlock_irq(&chip->reg_lock); | |
2751 | err = -EBUSY; | |
2752 | goto unlock; | |
2753 | } | |
2754 | azx_dev->prepared = 0; | |
2755 | chip->saved_azx_dev = *azx_dev; | |
2756 | azx_dev->locked = 1; | |
2757 | spin_unlock_irq(&chip->reg_lock); | |
1d1a4564 TI |
2758 | |
2759 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, | |
2760 | snd_dma_pci_data(chip->pci), | |
2761 | byte_size, bufp); | |
2762 | if (err < 0) | |
eb49faa6 | 2763 | goto err_alloc; |
1d1a4564 | 2764 | |
b3667bd7 | 2765 | mark_pages_wc(chip, bufp, true); |
1d1a4564 TI |
2766 | azx_dev->bufsize = byte_size; |
2767 | azx_dev->period_bytes = byte_size; | |
2768 | azx_dev->format_val = format; | |
2769 | ||
2770 | azx_stream_reset(chip, azx_dev); | |
2771 | ||
2772 | /* reset BDL address */ | |
2773 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
2774 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
2775 | ||
2776 | azx_dev->frags = 0; | |
2777 | bdl = (u32 *)azx_dev->bdl.area; | |
2778 | err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0); | |
2779 | if (err < 0) | |
2780 | goto error; | |
2781 | ||
2782 | azx_setup_controller(chip, azx_dev); | |
eb49faa6 | 2783 | dsp_unlock(azx_dev); |
1d1a4564 TI |
2784 | return azx_dev->stream_tag; |
2785 | ||
2786 | error: | |
b3667bd7 TI |
2787 | mark_pages_wc(chip, bufp, false); |
2788 | snd_dma_free_pages(bufp); | |
eb49faa6 TI |
2789 | err_alloc: |
2790 | spin_lock_irq(&chip->reg_lock); | |
2791 | if (azx_dev->opened) | |
2792 | *azx_dev = chip->saved_azx_dev; | |
2793 | azx_dev->locked = 0; | |
2794 | spin_unlock_irq(&chip->reg_lock); | |
2795 | unlock: | |
2796 | dsp_unlock(azx_dev); | |
1d1a4564 TI |
2797 | return err; |
2798 | } | |
2799 | ||
2800 | static void azx_load_dsp_trigger(struct hda_bus *bus, bool start) | |
2801 | { | |
2802 | struct azx *chip = bus->private_data; | |
2803 | struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); | |
2804 | ||
2805 | if (start) | |
2806 | azx_stream_start(chip, azx_dev); | |
2807 | else | |
2808 | azx_stream_stop(chip, azx_dev); | |
2809 | azx_dev->running = start; | |
2810 | } | |
2811 | ||
2812 | static void azx_load_dsp_cleanup(struct hda_bus *bus, | |
2813 | struct snd_dma_buffer *dmab) | |
2814 | { | |
2815 | struct azx *chip = bus->private_data; | |
2816 | struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); | |
2817 | ||
eb49faa6 | 2818 | if (!dmab->area || !azx_dev->locked) |
b3667bd7 TI |
2819 | return; |
2820 | ||
eb49faa6 | 2821 | dsp_lock(azx_dev); |
1d1a4564 TI |
2822 | /* reset BDL address */ |
2823 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
2824 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
2825 | azx_sd_writel(azx_dev, SD_CTL, 0); | |
2826 | azx_dev->bufsize = 0; | |
2827 | azx_dev->period_bytes = 0; | |
2828 | azx_dev->format_val = 0; | |
2829 | ||
b3667bd7 | 2830 | mark_pages_wc(chip, dmab, false); |
1d1a4564 | 2831 | snd_dma_free_pages(dmab); |
b3667bd7 | 2832 | dmab->area = NULL; |
1d1a4564 | 2833 | |
eb49faa6 TI |
2834 | spin_lock_irq(&chip->reg_lock); |
2835 | if (azx_dev->opened) | |
2836 | *azx_dev = chip->saved_azx_dev; | |
2837 | azx_dev->locked = 0; | |
2838 | spin_unlock_irq(&chip->reg_lock); | |
2839 | dsp_unlock(azx_dev); | |
1d1a4564 TI |
2840 | } |
2841 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ | |
2842 | ||
83012a7c | 2843 | #ifdef CONFIG_PM |
cb53c626 | 2844 | /* power-up/down the controller */ |
68467f51 | 2845 | static void azx_power_notify(struct hda_bus *bus, bool power_up) |
cb53c626 | 2846 | { |
33fa35ed | 2847 | struct azx *chip = bus->private_data; |
cb53c626 | 2848 | |
2ea3c6a2 TI |
2849 | if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) |
2850 | return; | |
2851 | ||
68467f51 | 2852 | if (power_up) |
b8dfc462 ML |
2853 | pm_runtime_get_sync(&chip->pci->dev); |
2854 | else | |
2855 | pm_runtime_put_sync(&chip->pci->dev); | |
cb53c626 | 2856 | } |
65fcd41d TI |
2857 | |
2858 | static DEFINE_MUTEX(card_list_lock); | |
2859 | static LIST_HEAD(card_list); | |
2860 | ||
2861 | static void azx_add_card_list(struct azx *chip) | |
2862 | { | |
2863 | mutex_lock(&card_list_lock); | |
2864 | list_add(&chip->list, &card_list); | |
2865 | mutex_unlock(&card_list_lock); | |
2866 | } | |
2867 | ||
2868 | static void azx_del_card_list(struct azx *chip) | |
2869 | { | |
2870 | mutex_lock(&card_list_lock); | |
2871 | list_del_init(&chip->list); | |
2872 | mutex_unlock(&card_list_lock); | |
2873 | } | |
2874 | ||
2875 | /* trigger power-save check at writing parameter */ | |
2876 | static int param_set_xint(const char *val, const struct kernel_param *kp) | |
2877 | { | |
2878 | struct azx *chip; | |
2879 | struct hda_codec *c; | |
2880 | int prev = power_save; | |
2881 | int ret = param_set_int(val, kp); | |
2882 | ||
2883 | if (ret || prev == power_save) | |
2884 | return ret; | |
2885 | ||
2886 | mutex_lock(&card_list_lock); | |
2887 | list_for_each_entry(chip, &card_list, list) { | |
2888 | if (!chip->bus || chip->disabled) | |
2889 | continue; | |
2890 | list_for_each_entry(c, &chip->bus->codec_list, list) | |
2891 | snd_hda_power_sync(c); | |
2892 | } | |
2893 | mutex_unlock(&card_list_lock); | |
2894 | return 0; | |
2895 | } | |
2896 | #else | |
2897 | #define azx_add_card_list(chip) /* NOP */ | |
2898 | #define azx_del_card_list(chip) /* NOP */ | |
83012a7c | 2899 | #endif /* CONFIG_PM */ |
5c0b9bec | 2900 | |
7ccbde57 | 2901 | #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) |
5c0b9bec TI |
2902 | /* |
2903 | * power management | |
2904 | */ | |
68cb2b55 | 2905 | static int azx_suspend(struct device *dev) |
1da177e4 | 2906 | { |
68cb2b55 TI |
2907 | struct pci_dev *pci = to_pci_dev(dev); |
2908 | struct snd_card *card = dev_get_drvdata(dev); | |
421a1252 | 2909 | struct azx *chip = card->private_data; |
01b65bfb | 2910 | struct azx_pcm *p; |
1da177e4 | 2911 | |
c5c21523 TI |
2912 | if (chip->disabled) |
2913 | return 0; | |
2914 | ||
421a1252 | 2915 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
9ad593f6 | 2916 | azx_clear_irq_pending(chip); |
01b65bfb TI |
2917 | list_for_each_entry(p, &chip->pcm_list, list) |
2918 | snd_pcm_suspend_all(p->pcm); | |
0b7a2e9c | 2919 | if (chip->initialized) |
8dd78330 | 2920 | snd_hda_suspend(chip->bus); |
cb53c626 | 2921 | azx_stop_chip(chip); |
7295b264 | 2922 | azx_enter_link_reset(chip); |
30b35399 | 2923 | if (chip->irq >= 0) { |
43001c95 | 2924 | free_irq(chip->irq, chip); |
30b35399 TI |
2925 | chip->irq = -1; |
2926 | } | |
68e7fffc | 2927 | if (chip->msi) |
43001c95 | 2928 | pci_disable_msi(chip->pci); |
421a1252 TI |
2929 | pci_disable_device(pci); |
2930 | pci_save_state(pci); | |
68cb2b55 | 2931 | pci_set_power_state(pci, PCI_D3hot); |
99a2008d WX |
2932 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) |
2933 | hda_display_power(false); | |
1da177e4 LT |
2934 | return 0; |
2935 | } | |
2936 | ||
68cb2b55 | 2937 | static int azx_resume(struct device *dev) |
1da177e4 | 2938 | { |
68cb2b55 TI |
2939 | struct pci_dev *pci = to_pci_dev(dev); |
2940 | struct snd_card *card = dev_get_drvdata(dev); | |
421a1252 | 2941 | struct azx *chip = card->private_data; |
1da177e4 | 2942 | |
c5c21523 TI |
2943 | if (chip->disabled) |
2944 | return 0; | |
2945 | ||
99a2008d WX |
2946 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) |
2947 | hda_display_power(true); | |
d14a7e0b TI |
2948 | pci_set_power_state(pci, PCI_D0); |
2949 | pci_restore_state(pci); | |
30b35399 TI |
2950 | if (pci_enable_device(pci) < 0) { |
2951 | printk(KERN_ERR "hda-intel: pci_enable_device failed, " | |
2952 | "disabling device\n"); | |
2953 | snd_card_disconnect(card); | |
2954 | return -EIO; | |
2955 | } | |
2956 | pci_set_master(pci); | |
68e7fffc TI |
2957 | if (chip->msi) |
2958 | if (pci_enable_msi(pci) < 0) | |
2959 | chip->msi = 0; | |
2960 | if (azx_acquire_irq(chip, 1) < 0) | |
30b35399 | 2961 | return -EIO; |
cb53c626 | 2962 | azx_init_pci(chip); |
d804ad92 | 2963 | |
7f30830b | 2964 | azx_init_chip(chip, 1); |
d804ad92 | 2965 | |
1da177e4 | 2966 | snd_hda_resume(chip->bus); |
421a1252 | 2967 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
1da177e4 LT |
2968 | return 0; |
2969 | } | |
b8dfc462 ML |
2970 | #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ |
2971 | ||
2972 | #ifdef CONFIG_PM_RUNTIME | |
2973 | static int azx_runtime_suspend(struct device *dev) | |
2974 | { | |
2975 | struct snd_card *card = dev_get_drvdata(dev); | |
2976 | struct azx *chip = card->private_data; | |
2977 | ||
246efa4a DA |
2978 | if (chip->disabled) |
2979 | return 0; | |
2980 | ||
2981 | if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) | |
2982 | return 0; | |
2983 | ||
7d4f606c WX |
2984 | /* enable controller wake up event */ |
2985 | azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | | |
2986 | STATESTS_INT_MASK); | |
2987 | ||
b8dfc462 | 2988 | azx_stop_chip(chip); |
95f74c41 TI |
2989 | if (!chip->bus->avoid_link_reset) |
2990 | azx_enter_link_reset(chip); | |
b8dfc462 | 2991 | azx_clear_irq_pending(chip); |
99a2008d WX |
2992 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) |
2993 | hda_display_power(false); | |
b8dfc462 ML |
2994 | return 0; |
2995 | } | |
2996 | ||
2997 | static int azx_runtime_resume(struct device *dev) | |
2998 | { | |
2999 | struct snd_card *card = dev_get_drvdata(dev); | |
3000 | struct azx *chip = card->private_data; | |
7d4f606c WX |
3001 | struct hda_bus *bus; |
3002 | struct hda_codec *codec; | |
3003 | int status; | |
b8dfc462 | 3004 | |
246efa4a DA |
3005 | if (chip->disabled) |
3006 | return 0; | |
3007 | ||
3008 | if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) | |
3009 | return 0; | |
3010 | ||
99a2008d WX |
3011 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) |
3012 | hda_display_power(true); | |
7d4f606c WX |
3013 | |
3014 | /* Read STATESTS before controller reset */ | |
3015 | status = azx_readw(chip, STATESTS); | |
3016 | ||
b8dfc462 ML |
3017 | azx_init_pci(chip); |
3018 | azx_init_chip(chip, 1); | |
7d4f606c WX |
3019 | |
3020 | bus = chip->bus; | |
3021 | if (status && bus) { | |
3022 | list_for_each_entry(codec, &bus->codec_list, list) | |
3023 | if (status & (1 << codec->addr)) | |
3024 | queue_delayed_work(codec->bus->workq, | |
3025 | &codec->jackpoll_work, codec->jackpoll_interval); | |
3026 | } | |
3027 | ||
3028 | /* disable controller Wake Up event*/ | |
3029 | azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & | |
3030 | ~STATESTS_INT_MASK); | |
3031 | ||
b8dfc462 ML |
3032 | return 0; |
3033 | } | |
6eb827d2 TI |
3034 | |
3035 | static int azx_runtime_idle(struct device *dev) | |
3036 | { | |
3037 | struct snd_card *card = dev_get_drvdata(dev); | |
3038 | struct azx *chip = card->private_data; | |
3039 | ||
246efa4a DA |
3040 | if (chip->disabled) |
3041 | return 0; | |
3042 | ||
6eb827d2 TI |
3043 | if (!power_save_controller || |
3044 | !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) | |
3045 | return -EBUSY; | |
3046 | ||
3047 | return 0; | |
3048 | } | |
3049 | ||
b8dfc462 ML |
3050 | #endif /* CONFIG_PM_RUNTIME */ |
3051 | ||
3052 | #ifdef CONFIG_PM | |
3053 | static const struct dev_pm_ops azx_pm = { | |
3054 | SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) | |
6eb827d2 | 3055 | SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) |
b8dfc462 ML |
3056 | }; |
3057 | ||
68cb2b55 TI |
3058 | #define AZX_PM_OPS &azx_pm |
3059 | #else | |
68cb2b55 | 3060 | #define AZX_PM_OPS NULL |
b8dfc462 | 3061 | #endif /* CONFIG_PM */ |
1da177e4 LT |
3062 | |
3063 | ||
0cbf0098 TI |
3064 | /* |
3065 | * reboot notifier for hang-up problem at power-down | |
3066 | */ | |
3067 | static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf) | |
3068 | { | |
3069 | struct azx *chip = container_of(nb, struct azx, reboot_notifier); | |
fb8d1a34 | 3070 | snd_hda_bus_reboot_notify(chip->bus); |
0cbf0098 TI |
3071 | azx_stop_chip(chip); |
3072 | return NOTIFY_OK; | |
3073 | } | |
3074 | ||
3075 | static void azx_notifier_register(struct azx *chip) | |
3076 | { | |
3077 | chip->reboot_notifier.notifier_call = azx_halt; | |
3078 | register_reboot_notifier(&chip->reboot_notifier); | |
3079 | } | |
3080 | ||
3081 | static void azx_notifier_unregister(struct azx *chip) | |
3082 | { | |
3083 | if (chip->reboot_notifier.notifier_call) | |
3084 | unregister_reboot_notifier(&chip->reboot_notifier); | |
3085 | } | |
3086 | ||
48c8b0eb | 3087 | static int azx_probe_continue(struct azx *chip); |
a82d51ed | 3088 | |
8393ec4a | 3089 | #ifdef SUPPORT_VGA_SWITCHEROO |
e23e7a14 | 3090 | static struct pci_dev *get_bound_vga(struct pci_dev *pci); |
a82d51ed | 3091 | |
a82d51ed TI |
3092 | static void azx_vs_set_state(struct pci_dev *pci, |
3093 | enum vga_switcheroo_state state) | |
3094 | { | |
3095 | struct snd_card *card = pci_get_drvdata(pci); | |
3096 | struct azx *chip = card->private_data; | |
3097 | bool disabled; | |
3098 | ||
f4c482a4 | 3099 | wait_for_completion(&chip->probe_wait); |
a82d51ed TI |
3100 | if (chip->init_failed) |
3101 | return; | |
3102 | ||
3103 | disabled = (state == VGA_SWITCHEROO_OFF); | |
3104 | if (chip->disabled == disabled) | |
3105 | return; | |
3106 | ||
3107 | if (!chip->bus) { | |
3108 | chip->disabled = disabled; | |
3109 | if (!disabled) { | |
3110 | snd_printk(KERN_INFO SFX | |
3111 | "%s: Start delayed initialization\n", | |
3112 | pci_name(chip->pci)); | |
5c90680e | 3113 | if (azx_probe_continue(chip) < 0) { |
a82d51ed TI |
3114 | snd_printk(KERN_ERR SFX |
3115 | "%s: initialization error\n", | |
3116 | pci_name(chip->pci)); | |
3117 | chip->init_failed = true; | |
3118 | } | |
3119 | } | |
3120 | } else { | |
3121 | snd_printk(KERN_INFO SFX | |
445a51b3 DB |
3122 | "%s: %s via VGA-switcheroo\n", pci_name(chip->pci), |
3123 | disabled ? "Disabling" : "Enabling"); | |
a82d51ed | 3124 | if (disabled) { |
246efa4a | 3125 | pm_runtime_put_sync_suspend(&pci->dev); |
68cb2b55 | 3126 | azx_suspend(&pci->dev); |
246efa4a DA |
3127 | /* when we get suspended by vga switcheroo we end up in D3cold, |
3128 | * however we have no ACPI handle, so pci/acpi can't put us there, | |
3129 | * put ourselves there */ | |
3130 | pci->current_state = PCI_D3cold; | |
a82d51ed | 3131 | chip->disabled = true; |
128960a9 | 3132 | if (snd_hda_lock_devices(chip->bus)) |
445a51b3 DB |
3133 | snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n", |
3134 | pci_name(chip->pci)); | |
a82d51ed TI |
3135 | } else { |
3136 | snd_hda_unlock_devices(chip->bus); | |
246efa4a | 3137 | pm_runtime_get_noresume(&pci->dev); |
a82d51ed | 3138 | chip->disabled = false; |
68cb2b55 | 3139 | azx_resume(&pci->dev); |
a82d51ed TI |
3140 | } |
3141 | } | |
3142 | } | |
3143 | ||
3144 | static bool azx_vs_can_switch(struct pci_dev *pci) | |
3145 | { | |
3146 | struct snd_card *card = pci_get_drvdata(pci); | |
3147 | struct azx *chip = card->private_data; | |
3148 | ||
f4c482a4 | 3149 | wait_for_completion(&chip->probe_wait); |
a82d51ed TI |
3150 | if (chip->init_failed) |
3151 | return false; | |
3152 | if (chip->disabled || !chip->bus) | |
3153 | return true; | |
3154 | if (snd_hda_lock_devices(chip->bus)) | |
3155 | return false; | |
3156 | snd_hda_unlock_devices(chip->bus); | |
3157 | return true; | |
3158 | } | |
3159 | ||
e23e7a14 | 3160 | static void init_vga_switcheroo(struct azx *chip) |
a82d51ed TI |
3161 | { |
3162 | struct pci_dev *p = get_bound_vga(chip->pci); | |
3163 | if (p) { | |
3164 | snd_printk(KERN_INFO SFX | |
3165 | "%s: Handle VGA-switcheroo audio client\n", | |
3166 | pci_name(chip->pci)); | |
3167 | chip->use_vga_switcheroo = 1; | |
3168 | pci_dev_put(p); | |
3169 | } | |
3170 | } | |
3171 | ||
3172 | static const struct vga_switcheroo_client_ops azx_vs_ops = { | |
3173 | .set_gpu_state = azx_vs_set_state, | |
3174 | .can_switch = azx_vs_can_switch, | |
3175 | }; | |
3176 | ||
e23e7a14 | 3177 | static int register_vga_switcheroo(struct azx *chip) |
a82d51ed | 3178 | { |
128960a9 TI |
3179 | int err; |
3180 | ||
a82d51ed TI |
3181 | if (!chip->use_vga_switcheroo) |
3182 | return 0; | |
3183 | /* FIXME: currently only handling DIS controller | |
3184 | * is there any machine with two switchable HDMI audio controllers? | |
3185 | */ | |
128960a9 | 3186 | err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, |
a82d51ed TI |
3187 | VGA_SWITCHEROO_DIS, |
3188 | chip->bus != NULL); | |
128960a9 TI |
3189 | if (err < 0) |
3190 | return err; | |
3191 | chip->vga_switcheroo_registered = 1; | |
246efa4a DA |
3192 | |
3193 | /* register as an optimus hdmi audio power domain */ | |
3194 | vga_switcheroo_init_domain_pm_optimus_hdmi_audio(&chip->pci->dev, &chip->hdmi_pm_domain); | |
128960a9 | 3195 | return 0; |
a82d51ed TI |
3196 | } |
3197 | #else | |
3198 | #define init_vga_switcheroo(chip) /* NOP */ | |
3199 | #define register_vga_switcheroo(chip) 0 | |
8393ec4a | 3200 | #define check_hdmi_disabled(pci) false |
a82d51ed TI |
3201 | #endif /* SUPPORT_VGA_SWITCHER */ |
3202 | ||
1da177e4 LT |
3203 | /* |
3204 | * destructor | |
3205 | */ | |
a98f90fd | 3206 | static int azx_free(struct azx *chip) |
1da177e4 | 3207 | { |
c67e2228 | 3208 | struct pci_dev *pci = chip->pci; |
4ce107b9 TI |
3209 | int i; |
3210 | ||
c67e2228 WX |
3211 | if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) |
3212 | && chip->running) | |
3213 | pm_runtime_get_noresume(&pci->dev); | |
3214 | ||
65fcd41d TI |
3215 | azx_del_card_list(chip); |
3216 | ||
0cbf0098 TI |
3217 | azx_notifier_unregister(chip); |
3218 | ||
f4c482a4 | 3219 | chip->init_failed = 1; /* to be sure */ |
44728e97 | 3220 | complete_all(&chip->probe_wait); |
f4c482a4 | 3221 | |
a82d51ed TI |
3222 | if (use_vga_switcheroo(chip)) { |
3223 | if (chip->disabled && chip->bus) | |
3224 | snd_hda_unlock_devices(chip->bus); | |
128960a9 TI |
3225 | if (chip->vga_switcheroo_registered) |
3226 | vga_switcheroo_unregister_client(chip->pci); | |
a82d51ed TI |
3227 | } |
3228 | ||
ce43fbae | 3229 | if (chip->initialized) { |
9ad593f6 | 3230 | azx_clear_irq_pending(chip); |
07e4ca50 | 3231 | for (i = 0; i < chip->num_streams; i++) |
1da177e4 | 3232 | azx_stream_stop(chip, &chip->azx_dev[i]); |
cb53c626 | 3233 | azx_stop_chip(chip); |
1da177e4 LT |
3234 | } |
3235 | ||
f000fd80 | 3236 | if (chip->irq >= 0) |
1da177e4 | 3237 | free_irq(chip->irq, (void*)chip); |
68e7fffc | 3238 | if (chip->msi) |
30b35399 | 3239 | pci_disable_msi(chip->pci); |
f079c25a TI |
3240 | if (chip->remap_addr) |
3241 | iounmap(chip->remap_addr); | |
1da177e4 | 3242 | |
4ce107b9 TI |
3243 | if (chip->azx_dev) { |
3244 | for (i = 0; i < chip->num_streams; i++) | |
27fe48d9 TI |
3245 | if (chip->azx_dev[i].bdl.area) { |
3246 | mark_pages_wc(chip, &chip->azx_dev[i].bdl, false); | |
4ce107b9 | 3247 | snd_dma_free_pages(&chip->azx_dev[i].bdl); |
27fe48d9 | 3248 | } |
4ce107b9 | 3249 | } |
27fe48d9 TI |
3250 | if (chip->rb.area) { |
3251 | mark_pages_wc(chip, &chip->rb, false); | |
1da177e4 | 3252 | snd_dma_free_pages(&chip->rb); |
27fe48d9 TI |
3253 | } |
3254 | if (chip->posbuf.area) { | |
3255 | mark_pages_wc(chip, &chip->posbuf, false); | |
1da177e4 | 3256 | snd_dma_free_pages(&chip->posbuf); |
27fe48d9 | 3257 | } |
a82d51ed TI |
3258 | if (chip->region_requested) |
3259 | pci_release_regions(chip->pci); | |
1da177e4 | 3260 | pci_disable_device(chip->pci); |
07e4ca50 | 3261 | kfree(chip->azx_dev); |
4918cdab TI |
3262 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
3263 | if (chip->fw) | |
3264 | release_firmware(chip->fw); | |
3265 | #endif | |
99a2008d WX |
3266 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { |
3267 | hda_display_power(false); | |
3268 | hda_i915_exit(); | |
3269 | } | |
1da177e4 LT |
3270 | kfree(chip); |
3271 | ||
3272 | return 0; | |
3273 | } | |
3274 | ||
a98f90fd | 3275 | static int azx_dev_free(struct snd_device *device) |
1da177e4 LT |
3276 | { |
3277 | return azx_free(device->device_data); | |
3278 | } | |
3279 | ||
8393ec4a | 3280 | #ifdef SUPPORT_VGA_SWITCHEROO |
9121947d TI |
3281 | /* |
3282 | * Check of disabled HDMI controller by vga-switcheroo | |
3283 | */ | |
e23e7a14 | 3284 | static struct pci_dev *get_bound_vga(struct pci_dev *pci) |
9121947d TI |
3285 | { |
3286 | struct pci_dev *p; | |
3287 | ||
3288 | /* check only discrete GPU */ | |
3289 | switch (pci->vendor) { | |
3290 | case PCI_VENDOR_ID_ATI: | |
3291 | case PCI_VENDOR_ID_AMD: | |
3292 | case PCI_VENDOR_ID_NVIDIA: | |
3293 | if (pci->devfn == 1) { | |
3294 | p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), | |
3295 | pci->bus->number, 0); | |
3296 | if (p) { | |
3297 | if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) | |
3298 | return p; | |
3299 | pci_dev_put(p); | |
3300 | } | |
3301 | } | |
3302 | break; | |
3303 | } | |
3304 | return NULL; | |
3305 | } | |
3306 | ||
e23e7a14 | 3307 | static bool check_hdmi_disabled(struct pci_dev *pci) |
9121947d TI |
3308 | { |
3309 | bool vga_inactive = false; | |
3310 | struct pci_dev *p = get_bound_vga(pci); | |
3311 | ||
3312 | if (p) { | |
12b78a7f | 3313 | if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) |
9121947d TI |
3314 | vga_inactive = true; |
3315 | pci_dev_put(p); | |
3316 | } | |
3317 | return vga_inactive; | |
3318 | } | |
8393ec4a | 3319 | #endif /* SUPPORT_VGA_SWITCHEROO */ |
9121947d | 3320 | |
3372a153 TI |
3321 | /* |
3322 | * white/black-listing for position_fix | |
3323 | */ | |
e23e7a14 | 3324 | static struct snd_pci_quirk position_fix_list[] = { |
d2e1c973 TI |
3325 | SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), |
3326 | SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), | |
2f703e7a | 3327 | SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), |
d2e1c973 | 3328 | SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), |
dd37f8e8 | 3329 | SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), |
9f75c1b1 | 3330 | SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), |
e96d3127 | 3331 | SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), |
b01de4fb | 3332 | SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), |
61bb42c3 | 3333 | SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), |
9ec8ddad | 3334 | SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), |
45d4ebf1 | 3335 | SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), |
8815cd03 | 3336 | SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), |
b90c0764 | 3337 | SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), |
0e0280dc | 3338 | SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), |
3372a153 TI |
3339 | {} |
3340 | }; | |
3341 | ||
e23e7a14 | 3342 | static int check_position_fix(struct azx *chip, int fix) |
3372a153 TI |
3343 | { |
3344 | const struct snd_pci_quirk *q; | |
3345 | ||
c673ba1c | 3346 | switch (fix) { |
1dac6695 | 3347 | case POS_FIX_AUTO: |
c673ba1c TI |
3348 | case POS_FIX_LPIB: |
3349 | case POS_FIX_POSBUF: | |
4cb36310 | 3350 | case POS_FIX_VIACOMBO: |
a6f2fd55 | 3351 | case POS_FIX_COMBO: |
c673ba1c TI |
3352 | return fix; |
3353 | } | |
3354 | ||
c673ba1c TI |
3355 | q = snd_pci_quirk_lookup(chip->pci, position_fix_list); |
3356 | if (q) { | |
3357 | printk(KERN_INFO | |
3358 | "hda_intel: position_fix set to %d " | |
3359 | "for device %04x:%04x\n", | |
3360 | q->value, q->subvendor, q->subdevice); | |
3361 | return q->value; | |
3372a153 | 3362 | } |
bdd9ef24 DH |
3363 | |
3364 | /* Check VIA/ATI HD Audio Controller exist */ | |
9477c58e | 3365 | if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) { |
445a51b3 | 3366 | snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci)); |
bdd9ef24 | 3367 | return POS_FIX_VIACOMBO; |
9477c58e TI |
3368 | } |
3369 | if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { | |
445a51b3 | 3370 | snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci)); |
50e3bbf9 | 3371 | return POS_FIX_LPIB; |
bdd9ef24 | 3372 | } |
c673ba1c | 3373 | return POS_FIX_AUTO; |
3372a153 TI |
3374 | } |
3375 | ||
669ba27a TI |
3376 | /* |
3377 | * black-lists for probe_mask | |
3378 | */ | |
e23e7a14 | 3379 | static struct snd_pci_quirk probe_mask_list[] = { |
669ba27a TI |
3380 | /* Thinkpad often breaks the controller communication when accessing |
3381 | * to the non-working (or non-existing) modem codec slot. | |
3382 | */ | |
3383 | SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), | |
3384 | SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), | |
3385 | SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), | |
0edb9454 TI |
3386 | /* broken BIOS */ |
3387 | SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), | |
ef1681d8 TI |
3388 | /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ |
3389 | SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), | |
20db7cb0 | 3390 | /* forced codec slots */ |
93574844 | 3391 | SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), |
20db7cb0 | 3392 | SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), |
f3af9051 JK |
3393 | /* WinFast VP200 H (Teradici) user reported broken communication */ |
3394 | SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), | |
669ba27a TI |
3395 | {} |
3396 | }; | |
3397 | ||
f1eaaeec TI |
3398 | #define AZX_FORCE_CODEC_MASK 0x100 |
3399 | ||
e23e7a14 | 3400 | static void check_probe_mask(struct azx *chip, int dev) |
669ba27a TI |
3401 | { |
3402 | const struct snd_pci_quirk *q; | |
3403 | ||
f1eaaeec TI |
3404 | chip->codec_probe_mask = probe_mask[dev]; |
3405 | if (chip->codec_probe_mask == -1) { | |
669ba27a TI |
3406 | q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); |
3407 | if (q) { | |
3408 | printk(KERN_INFO | |
3409 | "hda_intel: probe_mask set to 0x%x " | |
3410 | "for device %04x:%04x\n", | |
3411 | q->value, q->subvendor, q->subdevice); | |
f1eaaeec | 3412 | chip->codec_probe_mask = q->value; |
669ba27a TI |
3413 | } |
3414 | } | |
f1eaaeec TI |
3415 | |
3416 | /* check forced option */ | |
3417 | if (chip->codec_probe_mask != -1 && | |
3418 | (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { | |
3419 | chip->codec_mask = chip->codec_probe_mask & 0xff; | |
3420 | printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n", | |
3421 | chip->codec_mask); | |
3422 | } | |
669ba27a TI |
3423 | } |
3424 | ||
4d8e22e0 | 3425 | /* |
71623855 | 3426 | * white/black-list for enable_msi |
4d8e22e0 | 3427 | */ |
e23e7a14 | 3428 | static struct snd_pci_quirk msi_black_list[] = { |
9dc8398b | 3429 | SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ |
0a27fcfa | 3430 | SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ |
ecd21626 | 3431 | SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ |
83f72151 | 3432 | SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ |
4193d13b | 3433 | SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ |
3815595e | 3434 | SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ |
4d8e22e0 TI |
3435 | {} |
3436 | }; | |
3437 | ||
e23e7a14 | 3438 | static void check_msi(struct azx *chip) |
4d8e22e0 TI |
3439 | { |
3440 | const struct snd_pci_quirk *q; | |
3441 | ||
71623855 TI |
3442 | if (enable_msi >= 0) { |
3443 | chip->msi = !!enable_msi; | |
4d8e22e0 | 3444 | return; |
71623855 TI |
3445 | } |
3446 | chip->msi = 1; /* enable MSI as default */ | |
3447 | q = snd_pci_quirk_lookup(chip->pci, msi_black_list); | |
4d8e22e0 TI |
3448 | if (q) { |
3449 | printk(KERN_INFO | |
3450 | "hda_intel: msi for device %04x:%04x set to %d\n", | |
3451 | q->subvendor, q->subdevice, q->value); | |
3452 | chip->msi = q->value; | |
80c43ed7 TI |
3453 | return; |
3454 | } | |
3455 | ||
3456 | /* NVidia chipsets seem to cause troubles with MSI */ | |
9477c58e TI |
3457 | if (chip->driver_caps & AZX_DCAPS_NO_MSI) { |
3458 | printk(KERN_INFO "hda_intel: Disabling MSI\n"); | |
80c43ed7 | 3459 | chip->msi = 0; |
4d8e22e0 TI |
3460 | } |
3461 | } | |
3462 | ||
a1585d76 | 3463 | /* check the snoop mode availability */ |
e23e7a14 | 3464 | static void azx_check_snoop_available(struct azx *chip) |
a1585d76 TI |
3465 | { |
3466 | bool snoop = chip->snoop; | |
3467 | ||
3468 | switch (chip->driver_type) { | |
3469 | case AZX_DRIVER_VIA: | |
3470 | /* force to non-snoop mode for a new VIA controller | |
3471 | * when BIOS is set | |
3472 | */ | |
3473 | if (snoop) { | |
3474 | u8 val; | |
3475 | pci_read_config_byte(chip->pci, 0x42, &val); | |
3476 | if (!(val & 0x80) && chip->pci->revision == 0x30) | |
3477 | snoop = false; | |
3478 | } | |
3479 | break; | |
3480 | case AZX_DRIVER_ATIHDMI_NS: | |
3481 | /* new ATI HDMI requires non-snoop */ | |
3482 | snoop = false; | |
3483 | break; | |
c1279f87 TI |
3484 | case AZX_DRIVER_CTHDA: |
3485 | snoop = false; | |
3486 | break; | |
a1585d76 TI |
3487 | } |
3488 | ||
3489 | if (snoop != chip->snoop) { | |
445a51b3 DB |
3490 | snd_printk(KERN_INFO SFX "%s: Force to %s mode\n", |
3491 | pci_name(chip->pci), snoop ? "snoop" : "non-snoop"); | |
a1585d76 TI |
3492 | chip->snoop = snoop; |
3493 | } | |
3494 | } | |
669ba27a | 3495 | |
99a2008d WX |
3496 | #ifdef CONFIG_SND_HDA_I915 |
3497 | static void azx_probe_work(struct work_struct *work) | |
3498 | { | |
3499 | azx_probe_continue(container_of(work, struct azx, probe_work)); | |
3500 | } | |
3501 | #endif | |
3502 | ||
1da177e4 LT |
3503 | /* |
3504 | * constructor | |
3505 | */ | |
e23e7a14 BP |
3506 | static int azx_create(struct snd_card *card, struct pci_dev *pci, |
3507 | int dev, unsigned int driver_caps, | |
3508 | struct azx **rchip) | |
1da177e4 | 3509 | { |
a98f90fd | 3510 | static struct snd_device_ops ops = { |
1da177e4 LT |
3511 | .dev_free = azx_dev_free, |
3512 | }; | |
a82d51ed TI |
3513 | struct azx *chip; |
3514 | int err; | |
1da177e4 LT |
3515 | |
3516 | *rchip = NULL; | |
bcd72003 | 3517 | |
927fc866 PM |
3518 | err = pci_enable_device(pci); |
3519 | if (err < 0) | |
1da177e4 LT |
3520 | return err; |
3521 | ||
e560d8d8 | 3522 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
927fc866 | 3523 | if (!chip) { |
445a51b3 | 3524 | snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci)); |
1da177e4 LT |
3525 | pci_disable_device(pci); |
3526 | return -ENOMEM; | |
3527 | } | |
3528 | ||
3529 | spin_lock_init(&chip->reg_lock); | |
62932df8 | 3530 | mutex_init(&chip->open_mutex); |
1da177e4 LT |
3531 | chip->card = card; |
3532 | chip->pci = pci; | |
3533 | chip->irq = -1; | |
9477c58e TI |
3534 | chip->driver_caps = driver_caps; |
3535 | chip->driver_type = driver_caps & 0xff; | |
4d8e22e0 | 3536 | check_msi(chip); |
555e219f | 3537 | chip->dev_index = dev; |
9ad593f6 | 3538 | INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work); |
01b65bfb | 3539 | INIT_LIST_HEAD(&chip->pcm_list); |
65fcd41d | 3540 | INIT_LIST_HEAD(&chip->list); |
a82d51ed | 3541 | init_vga_switcheroo(chip); |
f4c482a4 | 3542 | init_completion(&chip->probe_wait); |
1da177e4 | 3543 | |
beaffc39 SG |
3544 | chip->position_fix[0] = chip->position_fix[1] = |
3545 | check_position_fix(chip, position_fix[dev]); | |
a6f2fd55 TI |
3546 | /* combo mode uses LPIB for playback */ |
3547 | if (chip->position_fix[0] == POS_FIX_COMBO) { | |
3548 | chip->position_fix[0] = POS_FIX_LPIB; | |
3549 | chip->position_fix[1] = POS_FIX_AUTO; | |
3550 | } | |
3551 | ||
5aba4f8e | 3552 | check_probe_mask(chip, dev); |
3372a153 | 3553 | |
27346166 | 3554 | chip->single_cmd = single_cmd; |
27fe48d9 | 3555 | chip->snoop = hda_snoop; |
a1585d76 | 3556 | azx_check_snoop_available(chip); |
c74db86b | 3557 | |
5c0d7bc1 TI |
3558 | if (bdl_pos_adj[dev] < 0) { |
3559 | switch (chip->driver_type) { | |
0c6341ac | 3560 | case AZX_DRIVER_ICH: |
32679f95 | 3561 | case AZX_DRIVER_PCH: |
0c6341ac | 3562 | bdl_pos_adj[dev] = 1; |
5c0d7bc1 TI |
3563 | break; |
3564 | default: | |
0c6341ac | 3565 | bdl_pos_adj[dev] = 32; |
5c0d7bc1 TI |
3566 | break; |
3567 | } | |
3568 | } | |
3569 | ||
a82d51ed TI |
3570 | err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); |
3571 | if (err < 0) { | |
445a51b3 DB |
3572 | snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n", |
3573 | pci_name(chip->pci)); | |
a82d51ed TI |
3574 | azx_free(chip); |
3575 | return err; | |
3576 | } | |
3577 | ||
99a2008d WX |
3578 | #ifdef CONFIG_SND_HDA_I915 |
3579 | /* continue probing in work context as may trigger request module */ | |
3580 | INIT_WORK(&chip->probe_work, azx_probe_work); | |
3581 | #endif | |
3582 | ||
a82d51ed | 3583 | *rchip = chip; |
99a2008d | 3584 | |
a82d51ed TI |
3585 | return 0; |
3586 | } | |
3587 | ||
48c8b0eb | 3588 | static int azx_first_init(struct azx *chip) |
a82d51ed TI |
3589 | { |
3590 | int dev = chip->dev_index; | |
3591 | struct pci_dev *pci = chip->pci; | |
3592 | struct snd_card *card = chip->card; | |
3593 | int i, err; | |
3594 | unsigned short gcap; | |
3595 | ||
07e4ca50 TI |
3596 | #if BITS_PER_LONG != 64 |
3597 | /* Fix up base address on ULI M5461 */ | |
3598 | if (chip->driver_type == AZX_DRIVER_ULI) { | |
3599 | u16 tmp3; | |
3600 | pci_read_config_word(pci, 0x40, &tmp3); | |
3601 | pci_write_config_word(pci, 0x40, tmp3 | 0x10); | |
3602 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); | |
3603 | } | |
3604 | #endif | |
3605 | ||
927fc866 | 3606 | err = pci_request_regions(pci, "ICH HD audio"); |
a82d51ed | 3607 | if (err < 0) |
1da177e4 | 3608 | return err; |
a82d51ed | 3609 | chip->region_requested = 1; |
1da177e4 | 3610 | |
927fc866 | 3611 | chip->addr = pci_resource_start(pci, 0); |
2f5ad54e | 3612 | chip->remap_addr = pci_ioremap_bar(pci, 0); |
1da177e4 | 3613 | if (chip->remap_addr == NULL) { |
445a51b3 | 3614 | snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci)); |
a82d51ed | 3615 | return -ENXIO; |
1da177e4 LT |
3616 | } |
3617 | ||
68e7fffc TI |
3618 | if (chip->msi) |
3619 | if (pci_enable_msi(pci) < 0) | |
3620 | chip->msi = 0; | |
7376d013 | 3621 | |
a82d51ed TI |
3622 | if (azx_acquire_irq(chip, 0) < 0) |
3623 | return -EBUSY; | |
1da177e4 LT |
3624 | |
3625 | pci_set_master(pci); | |
3626 | synchronize_irq(chip->irq); | |
3627 | ||
bcd72003 | 3628 | gcap = azx_readw(chip, GCAP); |
445a51b3 | 3629 | snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap); |
bcd72003 | 3630 | |
dc4c2e6b | 3631 | /* disable SB600 64bit support for safety */ |
9477c58e | 3632 | if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { |
dc4c2e6b AB |
3633 | struct pci_dev *p_smbus; |
3634 | p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, | |
3635 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
3636 | NULL); | |
3637 | if (p_smbus) { | |
3638 | if (p_smbus->revision < 0x30) | |
3639 | gcap &= ~ICH6_GCAP_64OK; | |
3640 | pci_dev_put(p_smbus); | |
3641 | } | |
3642 | } | |
09240cf4 | 3643 | |
9477c58e TI |
3644 | /* disable 64bit DMA address on some devices */ |
3645 | if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { | |
445a51b3 | 3646 | snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci)); |
396087ea | 3647 | gcap &= ~ICH6_GCAP_64OK; |
9477c58e | 3648 | } |
396087ea | 3649 | |
2ae66c26 | 3650 | /* disable buffer size rounding to 128-byte multiples if supported */ |
7bfe059e TI |
3651 | if (align_buffer_size >= 0) |
3652 | chip->align_buffer_size = !!align_buffer_size; | |
3653 | else { | |
3654 | if (chip->driver_caps & AZX_DCAPS_BUFSIZE) | |
3655 | chip->align_buffer_size = 0; | |
3656 | else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE) | |
3657 | chip->align_buffer_size = 1; | |
3658 | else | |
3659 | chip->align_buffer_size = 1; | |
3660 | } | |
2ae66c26 | 3661 | |
cf7aaca8 | 3662 | /* allow 64bit DMA address if supported by H/W */ |
b21fadb9 | 3663 | if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) |
e930438c | 3664 | pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); |
09240cf4 | 3665 | else { |
e930438c YH |
3666 | pci_set_dma_mask(pci, DMA_BIT_MASK(32)); |
3667 | pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); | |
09240cf4 | 3668 | } |
cf7aaca8 | 3669 | |
8b6ed8e7 TI |
3670 | /* read number of streams from GCAP register instead of using |
3671 | * hardcoded value | |
3672 | */ | |
3673 | chip->capture_streams = (gcap >> 8) & 0x0f; | |
3674 | chip->playback_streams = (gcap >> 12) & 0x0f; | |
3675 | if (!chip->playback_streams && !chip->capture_streams) { | |
bcd72003 TD |
3676 | /* gcap didn't give any info, switching to old method */ |
3677 | ||
3678 | switch (chip->driver_type) { | |
3679 | case AZX_DRIVER_ULI: | |
3680 | chip->playback_streams = ULI_NUM_PLAYBACK; | |
3681 | chip->capture_streams = ULI_NUM_CAPTURE; | |
bcd72003 TD |
3682 | break; |
3683 | case AZX_DRIVER_ATIHDMI: | |
1815b34a | 3684 | case AZX_DRIVER_ATIHDMI_NS: |
bcd72003 TD |
3685 | chip->playback_streams = ATIHDMI_NUM_PLAYBACK; |
3686 | chip->capture_streams = ATIHDMI_NUM_CAPTURE; | |
bcd72003 | 3687 | break; |
c4da29ca | 3688 | case AZX_DRIVER_GENERIC: |
bcd72003 TD |
3689 | default: |
3690 | chip->playback_streams = ICH6_NUM_PLAYBACK; | |
3691 | chip->capture_streams = ICH6_NUM_CAPTURE; | |
bcd72003 TD |
3692 | break; |
3693 | } | |
07e4ca50 | 3694 | } |
8b6ed8e7 TI |
3695 | chip->capture_index_offset = 0; |
3696 | chip->playback_index_offset = chip->capture_streams; | |
07e4ca50 | 3697 | chip->num_streams = chip->playback_streams + chip->capture_streams; |
d01ce99f TI |
3698 | chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), |
3699 | GFP_KERNEL); | |
927fc866 | 3700 | if (!chip->azx_dev) { |
445a51b3 | 3701 | snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci)); |
a82d51ed | 3702 | return -ENOMEM; |
07e4ca50 TI |
3703 | } |
3704 | ||
4ce107b9 | 3705 | for (i = 0; i < chip->num_streams; i++) { |
eb49faa6 | 3706 | dsp_lock_init(&chip->azx_dev[i]); |
4ce107b9 TI |
3707 | /* allocate memory for the BDL for each stream */ |
3708 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, | |
3709 | snd_dma_pci_data(chip->pci), | |
3710 | BDL_SIZE, &chip->azx_dev[i].bdl); | |
3711 | if (err < 0) { | |
445a51b3 | 3712 | snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci)); |
a82d51ed | 3713 | return -ENOMEM; |
4ce107b9 | 3714 | } |
27fe48d9 | 3715 | mark_pages_wc(chip, &chip->azx_dev[i].bdl, true); |
1da177e4 | 3716 | } |
0be3b5d3 | 3717 | /* allocate memory for the position buffer */ |
d01ce99f TI |
3718 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, |
3719 | snd_dma_pci_data(chip->pci), | |
3720 | chip->num_streams * 8, &chip->posbuf); | |
3721 | if (err < 0) { | |
445a51b3 | 3722 | snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci)); |
a82d51ed | 3723 | return -ENOMEM; |
1da177e4 | 3724 | } |
27fe48d9 | 3725 | mark_pages_wc(chip, &chip->posbuf, true); |
1da177e4 | 3726 | /* allocate CORB/RIRB */ |
81740861 TI |
3727 | err = azx_alloc_cmd_io(chip); |
3728 | if (err < 0) | |
a82d51ed | 3729 | return err; |
1da177e4 LT |
3730 | |
3731 | /* initialize streams */ | |
3732 | azx_init_stream(chip); | |
3733 | ||
3734 | /* initialize chip */ | |
cb53c626 | 3735 | azx_init_pci(chip); |
10e77dda | 3736 | azx_init_chip(chip, (probe_only[dev] & 2) == 0); |
1da177e4 LT |
3737 | |
3738 | /* codec detection */ | |
927fc866 | 3739 | if (!chip->codec_mask) { |
445a51b3 | 3740 | snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci)); |
a82d51ed | 3741 | return -ENODEV; |
1da177e4 LT |
3742 | } |
3743 | ||
07e4ca50 | 3744 | strcpy(card->driver, "HDA-Intel"); |
18cb7109 TI |
3745 | strlcpy(card->shortname, driver_short_names[chip->driver_type], |
3746 | sizeof(card->shortname)); | |
3747 | snprintf(card->longname, sizeof(card->longname), | |
3748 | "%s at 0x%lx irq %i", | |
3749 | card->shortname, chip->addr, chip->irq); | |
07e4ca50 | 3750 | |
1da177e4 | 3751 | return 0; |
1da177e4 LT |
3752 | } |
3753 | ||
cb53c626 TI |
3754 | static void power_down_all_codecs(struct azx *chip) |
3755 | { | |
83012a7c | 3756 | #ifdef CONFIG_PM |
cb53c626 TI |
3757 | /* The codecs were powered up in snd_hda_codec_new(). |
3758 | * Now all initialization done, so turn them down if possible | |
3759 | */ | |
3760 | struct hda_codec *codec; | |
3761 | list_for_each_entry(codec, &chip->bus->codec_list, list) { | |
3762 | snd_hda_power_down(codec); | |
3763 | } | |
3764 | #endif | |
3765 | } | |
3766 | ||
97c6a3d1 | 3767 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
5cb543db TI |
3768 | /* callback from request_firmware_nowait() */ |
3769 | static void azx_firmware_cb(const struct firmware *fw, void *context) | |
3770 | { | |
3771 | struct snd_card *card = context; | |
3772 | struct azx *chip = card->private_data; | |
3773 | struct pci_dev *pci = chip->pci; | |
3774 | ||
3775 | if (!fw) { | |
445a51b3 DB |
3776 | snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n", |
3777 | pci_name(chip->pci)); | |
5cb543db TI |
3778 | goto error; |
3779 | } | |
3780 | ||
3781 | chip->fw = fw; | |
3782 | if (!chip->disabled) { | |
3783 | /* continue probing */ | |
3784 | if (azx_probe_continue(chip)) | |
3785 | goto error; | |
3786 | } | |
3787 | return; /* OK */ | |
3788 | ||
3789 | error: | |
3790 | snd_card_free(card); | |
3791 | pci_set_drvdata(pci, NULL); | |
3792 | } | |
97c6a3d1 | 3793 | #endif |
5cb543db | 3794 | |
e23e7a14 BP |
3795 | static int azx_probe(struct pci_dev *pci, |
3796 | const struct pci_device_id *pci_id) | |
1da177e4 | 3797 | { |
5aba4f8e | 3798 | static int dev; |
a98f90fd TI |
3799 | struct snd_card *card; |
3800 | struct azx *chip; | |
5cb543db | 3801 | bool probe_now; |
927fc866 | 3802 | int err; |
1da177e4 | 3803 | |
5aba4f8e TI |
3804 | if (dev >= SNDRV_CARDS) |
3805 | return -ENODEV; | |
3806 | if (!enable[dev]) { | |
3807 | dev++; | |
3808 | return -ENOENT; | |
3809 | } | |
3810 | ||
e58de7ba TI |
3811 | err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); |
3812 | if (err < 0) { | |
445a51b3 | 3813 | snd_printk(KERN_ERR "hda-intel: Error creating card!\n"); |
e58de7ba | 3814 | return err; |
1da177e4 LT |
3815 | } |
3816 | ||
4ea6fbc8 TI |
3817 | snd_card_set_dev(card, &pci->dev); |
3818 | ||
5aba4f8e | 3819 | err = azx_create(card, pci, dev, pci_id->driver_data, &chip); |
41dda0fd WF |
3820 | if (err < 0) |
3821 | goto out_free; | |
421a1252 | 3822 | card->private_data = chip; |
f4c482a4 TI |
3823 | |
3824 | pci_set_drvdata(pci, card); | |
3825 | ||
3826 | err = register_vga_switcheroo(chip); | |
3827 | if (err < 0) { | |
3828 | snd_printk(KERN_ERR SFX | |
445a51b3 | 3829 | "%s: Error registering VGA-switcheroo client\n", pci_name(pci)); |
f4c482a4 TI |
3830 | goto out_free; |
3831 | } | |
3832 | ||
3833 | if (check_hdmi_disabled(pci)) { | |
445a51b3 | 3834 | snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n", |
f4c482a4 | 3835 | pci_name(pci)); |
445a51b3 | 3836 | snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci)); |
f4c482a4 TI |
3837 | chip->disabled = true; |
3838 | } | |
3839 | ||
5cb543db | 3840 | probe_now = !chip->disabled; |
1da177e4 | 3841 | |
4918cdab TI |
3842 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
3843 | if (patch[dev] && *patch[dev]) { | |
445a51b3 DB |
3844 | snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n", |
3845 | pci_name(pci), patch[dev]); | |
5cb543db TI |
3846 | err = request_firmware_nowait(THIS_MODULE, true, patch[dev], |
3847 | &pci->dev, GFP_KERNEL, card, | |
3848 | azx_firmware_cb); | |
4918cdab TI |
3849 | if (err < 0) |
3850 | goto out_free; | |
5cb543db | 3851 | probe_now = false; /* continued in azx_firmware_cb() */ |
4918cdab TI |
3852 | } |
3853 | #endif /* CONFIG_SND_HDA_PATCH_LOADER */ | |
3854 | ||
99a2008d WX |
3855 | /* continue probing in work context, avoid request_module deadlock */ |
3856 | if (probe_now && (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)) { | |
3857 | #ifdef CONFIG_SND_HDA_I915 | |
3858 | probe_now = false; | |
3859 | schedule_work(&chip->probe_work); | |
3860 | #else | |
3861 | snd_printk(KERN_ERR SFX "Haswell must build in CONFIG_SND_HDA_I915\n"); | |
3862 | #endif | |
3863 | } | |
3864 | ||
5cb543db | 3865 | if (probe_now) { |
a82d51ed TI |
3866 | err = azx_probe_continue(chip); |
3867 | if (err < 0) | |
3868 | goto out_free; | |
3869 | } | |
3870 | ||
a82d51ed | 3871 | dev++; |
44728e97 | 3872 | complete_all(&chip->probe_wait); |
a82d51ed TI |
3873 | return 0; |
3874 | ||
3875 | out_free: | |
3876 | snd_card_free(card); | |
3877 | return err; | |
3878 | } | |
3879 | ||
48c8b0eb | 3880 | static int azx_probe_continue(struct azx *chip) |
a82d51ed | 3881 | { |
c67e2228 | 3882 | struct pci_dev *pci = chip->pci; |
a82d51ed TI |
3883 | int dev = chip->dev_index; |
3884 | int err; | |
3885 | ||
99a2008d WX |
3886 | /* Request power well for Haswell HDA controller and codec */ |
3887 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { | |
c841ad2a | 3888 | #ifdef CONFIG_SND_HDA_I915 |
99a2008d WX |
3889 | err = hda_i915_init(); |
3890 | if (err < 0) { | |
3891 | snd_printk(KERN_ERR SFX "Error request power-well from i915\n"); | |
3892 | goto out_free; | |
3893 | } | |
c841ad2a | 3894 | #endif |
99a2008d WX |
3895 | hda_display_power(true); |
3896 | } | |
3897 | ||
5c90680e TI |
3898 | err = azx_first_init(chip); |
3899 | if (err < 0) | |
3900 | goto out_free; | |
3901 | ||
2dca0bba JK |
3902 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
3903 | chip->beep_mode = beep_mode[dev]; | |
3904 | #endif | |
3905 | ||
1da177e4 | 3906 | /* create codec instances */ |
a1e21c90 | 3907 | err = azx_codec_create(chip, model[dev]); |
41dda0fd WF |
3908 | if (err < 0) |
3909 | goto out_free; | |
4ea6fbc8 | 3910 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
4918cdab TI |
3911 | if (chip->fw) { |
3912 | err = snd_hda_load_patch(chip->bus, chip->fw->size, | |
3913 | chip->fw->data); | |
4ea6fbc8 TI |
3914 | if (err < 0) |
3915 | goto out_free; | |
e39ae856 | 3916 | #ifndef CONFIG_PM |
4918cdab TI |
3917 | release_firmware(chip->fw); /* no longer needed */ |
3918 | chip->fw = NULL; | |
e39ae856 | 3919 | #endif |
4ea6fbc8 TI |
3920 | } |
3921 | #endif | |
10e77dda | 3922 | if ((probe_only[dev] & 1) == 0) { |
a1e21c90 TI |
3923 | err = azx_codec_configure(chip); |
3924 | if (err < 0) | |
3925 | goto out_free; | |
3926 | } | |
1da177e4 LT |
3927 | |
3928 | /* create PCM streams */ | |
176d5335 | 3929 | err = snd_hda_build_pcms(chip->bus); |
41dda0fd WF |
3930 | if (err < 0) |
3931 | goto out_free; | |
1da177e4 LT |
3932 | |
3933 | /* create mixer controls */ | |
d01ce99f | 3934 | err = azx_mixer_create(chip); |
41dda0fd WF |
3935 | if (err < 0) |
3936 | goto out_free; | |
1da177e4 | 3937 | |
a82d51ed | 3938 | err = snd_card_register(chip->card); |
41dda0fd WF |
3939 | if (err < 0) |
3940 | goto out_free; | |
1da177e4 | 3941 | |
cb53c626 TI |
3942 | chip->running = 1; |
3943 | power_down_all_codecs(chip); | |
0cbf0098 | 3944 | azx_notifier_register(chip); |
65fcd41d | 3945 | azx_add_card_list(chip); |
246efa4a | 3946 | if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo) |
c67e2228 | 3947 | pm_runtime_put_noidle(&pci->dev); |
1da177e4 | 3948 | |
9121947d TI |
3949 | return 0; |
3950 | ||
41dda0fd | 3951 | out_free: |
a82d51ed | 3952 | chip->init_failed = 1; |
41dda0fd | 3953 | return err; |
1da177e4 LT |
3954 | } |
3955 | ||
e23e7a14 | 3956 | static void azx_remove(struct pci_dev *pci) |
1da177e4 | 3957 | { |
9121947d | 3958 | struct snd_card *card = pci_get_drvdata(pci); |
b8dfc462 | 3959 | |
9121947d TI |
3960 | if (card) |
3961 | snd_card_free(card); | |
1da177e4 LT |
3962 | } |
3963 | ||
3964 | /* PCI IDs */ | |
cebe41d4 | 3965 | static DEFINE_PCI_DEVICE_TABLE(azx_ids) = { |
d2f2fcd2 | 3966 | /* CPT */ |
9477c58e | 3967 | { PCI_DEVICE(0x8086, 0x1c20), |
d7dab4db | 3968 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
cea310e8 | 3969 | /* PBG */ |
9477c58e | 3970 | { PCI_DEVICE(0x8086, 0x1d20), |
d7dab4db | 3971 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
d2edeb7c | 3972 | /* Panther Point */ |
9477c58e | 3973 | { PCI_DEVICE(0x8086, 0x1e20), |
d7dab4db | 3974 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
8bc039a1 SH |
3975 | /* Lynx Point */ |
3976 | { PCI_DEVICE(0x8086, 0x8c20), | |
2ea3c6a2 | 3977 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
884b088f JR |
3978 | /* Wellsburg */ |
3979 | { PCI_DEVICE(0x8086, 0x8d20), | |
3980 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, | |
3981 | { PCI_DEVICE(0x8086, 0x8d21), | |
3982 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, | |
144dad99 JR |
3983 | /* Lynx Point-LP */ |
3984 | { PCI_DEVICE(0x8086, 0x9c20), | |
2ea3c6a2 | 3985 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
144dad99 JR |
3986 | /* Lynx Point-LP */ |
3987 | { PCI_DEVICE(0x8086, 0x9c21), | |
2ea3c6a2 | 3988 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
e926f2c8 | 3989 | /* Haswell */ |
4a7c516b | 3990 | { PCI_DEVICE(0x8086, 0x0a0c), |
99a2008d WX |
3991 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH | |
3992 | AZX_DCAPS_I915_POWERWELL }, | |
e926f2c8 | 3993 | { PCI_DEVICE(0x8086, 0x0c0c), |
99a2008d WX |
3994 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH | |
3995 | AZX_DCAPS_I915_POWERWELL }, | |
d279fae8 | 3996 | { PCI_DEVICE(0x8086, 0x0d0c), |
99a2008d WX |
3997 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH | |
3998 | AZX_DCAPS_I915_POWERWELL }, | |
99df18b3 PLB |
3999 | /* 5 Series/3400 */ |
4000 | { PCI_DEVICE(0x8086, 0x3b56), | |
2c1350fd | 4001 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
f748abcc | 4002 | /* Poulsbo */ |
9477c58e | 4003 | { PCI_DEVICE(0x8086, 0x811b), |
f748abcc TI |
4004 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
4005 | /* Oaktrail */ | |
09904b95 | 4006 | { PCI_DEVICE(0x8086, 0x080a), |
f748abcc | 4007 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
e44007e0 CCE |
4008 | /* BayTrail */ |
4009 | { PCI_DEVICE(0x8086, 0x0f04), | |
4010 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, | |
645e9035 | 4011 | /* ICH */ |
8b0bd226 | 4012 | { PCI_DEVICE(0x8086, 0x2668), |
2ae66c26 PLB |
4013 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
4014 | AZX_DCAPS_BUFSIZE }, /* ICH6 */ | |
8b0bd226 | 4015 | { PCI_DEVICE(0x8086, 0x27d8), |
2ae66c26 PLB |
4016 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
4017 | AZX_DCAPS_BUFSIZE }, /* ICH7 */ | |
8b0bd226 | 4018 | { PCI_DEVICE(0x8086, 0x269a), |
2ae66c26 PLB |
4019 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
4020 | AZX_DCAPS_BUFSIZE }, /* ESB2 */ | |
8b0bd226 | 4021 | { PCI_DEVICE(0x8086, 0x284b), |
2ae66c26 PLB |
4022 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
4023 | AZX_DCAPS_BUFSIZE }, /* ICH8 */ | |
8b0bd226 | 4024 | { PCI_DEVICE(0x8086, 0x293e), |
2ae66c26 PLB |
4025 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
4026 | AZX_DCAPS_BUFSIZE }, /* ICH9 */ | |
8b0bd226 | 4027 | { PCI_DEVICE(0x8086, 0x293f), |
2ae66c26 PLB |
4028 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
4029 | AZX_DCAPS_BUFSIZE }, /* ICH9 */ | |
8b0bd226 | 4030 | { PCI_DEVICE(0x8086, 0x3a3e), |
2ae66c26 PLB |
4031 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
4032 | AZX_DCAPS_BUFSIZE }, /* ICH10 */ | |
8b0bd226 | 4033 | { PCI_DEVICE(0x8086, 0x3a6e), |
2ae66c26 PLB |
4034 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
4035 | AZX_DCAPS_BUFSIZE }, /* ICH10 */ | |
b6864535 TI |
4036 | /* Generic Intel */ |
4037 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), | |
4038 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
4039 | .class_mask = 0xffffff, | |
2ae66c26 | 4040 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE }, |
9477c58e TI |
4041 | /* ATI SB 450/600/700/800/900 */ |
4042 | { PCI_DEVICE(0x1002, 0x437b), | |
4043 | .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, | |
4044 | { PCI_DEVICE(0x1002, 0x4383), | |
4045 | .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, | |
4046 | /* AMD Hudson */ | |
4047 | { PCI_DEVICE(0x1022, 0x780d), | |
4048 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, | |
87218e9c | 4049 | /* ATI HDMI */ |
9477c58e TI |
4050 | { PCI_DEVICE(0x1002, 0x793b), |
4051 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4052 | { PCI_DEVICE(0x1002, 0x7919), | |
4053 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4054 | { PCI_DEVICE(0x1002, 0x960f), | |
4055 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4056 | { PCI_DEVICE(0x1002, 0x970f), | |
4057 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4058 | { PCI_DEVICE(0x1002, 0xaa00), | |
4059 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4060 | { PCI_DEVICE(0x1002, 0xaa08), | |
4061 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4062 | { PCI_DEVICE(0x1002, 0xaa10), | |
4063 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4064 | { PCI_DEVICE(0x1002, 0xaa18), | |
4065 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4066 | { PCI_DEVICE(0x1002, 0xaa20), | |
4067 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4068 | { PCI_DEVICE(0x1002, 0xaa28), | |
4069 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4070 | { PCI_DEVICE(0x1002, 0xaa30), | |
4071 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4072 | { PCI_DEVICE(0x1002, 0xaa38), | |
4073 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4074 | { PCI_DEVICE(0x1002, 0xaa40), | |
4075 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4076 | { PCI_DEVICE(0x1002, 0xaa48), | |
4077 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
1815b34a AX |
4078 | { PCI_DEVICE(0x1002, 0x9902), |
4079 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4080 | { PCI_DEVICE(0x1002, 0xaaa0), | |
4081 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4082 | { PCI_DEVICE(0x1002, 0xaaa8), | |
4083 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, | |
4084 | { PCI_DEVICE(0x1002, 0xaab0), | |
4085 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, | |
87218e9c | 4086 | /* VIA VT8251/VT8237A */ |
9477c58e TI |
4087 | { PCI_DEVICE(0x1106, 0x3288), |
4088 | .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA }, | |
754fdff8 AL |
4089 | /* VIA GFX VT7122/VX900 */ |
4090 | { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, | |
4091 | /* VIA GFX VT6122/VX11 */ | |
4092 | { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, | |
87218e9c TI |
4093 | /* SIS966 */ |
4094 | { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, | |
4095 | /* ULI M5461 */ | |
4096 | { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, | |
4097 | /* NVIDIA MCP */ | |
0c2fd1bf TI |
4098 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), |
4099 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
4100 | .class_mask = 0xffffff, | |
9477c58e | 4101 | .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, |
f269002e | 4102 | /* Teradici */ |
9477c58e TI |
4103 | { PCI_DEVICE(0x6549, 0x1200), |
4104 | .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, | |
f0b3da98 LD |
4105 | { PCI_DEVICE(0x6549, 0x2200), |
4106 | .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, | |
4e01f54b | 4107 | /* Creative X-Fi (CA0110-IBG) */ |
f2a8ecaf TI |
4108 | /* CTHDA chips */ |
4109 | { PCI_DEVICE(0x1102, 0x0010), | |
4110 | .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, | |
4111 | { PCI_DEVICE(0x1102, 0x0012), | |
4112 | .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, | |
313f6e2d TI |
4113 | #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE) |
4114 | /* the following entry conflicts with snd-ctxfi driver, | |
4115 | * as ctxfi driver mutates from HD-audio to native mode with | |
4116 | * a special command sequence. | |
4117 | */ | |
4e01f54b TI |
4118 | { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), |
4119 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
4120 | .class_mask = 0xffffff, | |
9477c58e | 4121 | .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | |
69f9ba9b | 4122 | AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, |
313f6e2d TI |
4123 | #else |
4124 | /* this entry seems still valid -- i.e. without emu20kx chip */ | |
9477c58e TI |
4125 | { PCI_DEVICE(0x1102, 0x0009), |
4126 | .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | | |
69f9ba9b | 4127 | AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, |
313f6e2d | 4128 | #endif |
e35d4b11 OS |
4129 | /* Vortex86MX */ |
4130 | { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, | |
0f0714c5 BB |
4131 | /* VMware HDAudio */ |
4132 | { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, | |
9176b672 | 4133 | /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ |
c4da29ca YL |
4134 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), |
4135 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
4136 | .class_mask = 0xffffff, | |
9477c58e | 4137 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, |
9176b672 AB |
4138 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), |
4139 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
4140 | .class_mask = 0xffffff, | |
9477c58e | 4141 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, |
1da177e4 LT |
4142 | { 0, } |
4143 | }; | |
4144 | MODULE_DEVICE_TABLE(pci, azx_ids); | |
4145 | ||
4146 | /* pci_driver definition */ | |
e9f66d9b | 4147 | static struct pci_driver azx_driver = { |
3733e424 | 4148 | .name = KBUILD_MODNAME, |
1da177e4 LT |
4149 | .id_table = azx_ids, |
4150 | .probe = azx_probe, | |
e23e7a14 | 4151 | .remove = azx_remove, |
68cb2b55 TI |
4152 | .driver = { |
4153 | .pm = AZX_PM_OPS, | |
4154 | }, | |
1da177e4 LT |
4155 | }; |
4156 | ||
e9f66d9b | 4157 | module_pci_driver(azx_driver); |