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ALSA: hda - Force buffer alignment for Haswell HDMI controllers
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4 64#include "hda_codec.h"
99a2008d 65#include "hda_i915.h"
1da177e4
LT		 66
67
5aba4f8e
TI		 68static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
69static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 70static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 71static char *model[SNDRV_CARDS];
1dac6695 72static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 73static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 74static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 75static int probe_only[SNDRV_CARDS];
26a6cb6c 76static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 77static bool single_cmd;
71623855 78static int enable_msi = -1;
4ea6fbc8
TI		 79#ifdef CONFIG_SND_HDA_PATCH_LOADER
80static char *patch[SNDRV_CARDS];
81#endif
2dca0bba 82#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 83static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 84 CONFIG_SND_HDA_INPUT_BEEP_MODE};
85#endif
1da177e4 86
5aba4f8e 87module_param_array(index, int, NULL, 0444);
1da177e4 88MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 89module_param_array(id, charp, NULL, 0444);
1da177e4 90MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 91module_param_array(enable, bool, NULL, 0444);
92MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
93module_param_array(model, charp, NULL, 0444);
1da177e4 94MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 95module_param_array(position_fix, int, NULL, 0444);
4cb36310 96MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 97 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 98module_param_array(bdl_pos_adj, int, NULL, 0644);
99MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 100module_param_array(probe_mask, int, NULL, 0444);
606ad75f 101MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 102module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 103MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 104module_param_array(jackpoll_ms, int, NULL, 0444);
105MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 106module_param(single_cmd, bool, 0444);
d01ce99f
TI		 107MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
108 "(for debugging only).");
ac9ef6cf 109module_param(enable_msi, bint, 0444);
134a11f0 110MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 111#ifdef CONFIG_SND_HDA_PATCH_LOADER
112module_param_array(patch, charp, NULL, 0444);
113MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
114#endif
2dca0bba 115#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 116module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 117MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 118 "(0=off, 1=on) (default=1).");
2dca0bba 119#endif
606ad75f 120
83012a7c 121#ifdef CONFIG_PM
65fcd41d
TI		 122static int param_set_xint(const char *val, const struct kernel_param *kp);
123static struct kernel_param_ops param_ops_xint = {
124 .set = param_set_xint,
125 .get = param_get_int,
126};
127#define param_check_xint param_check_int
128
fee2fba3 129static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 130module_param(power_save, xint, 0644);
fee2fba3
TI		 131MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
132 "(in second, 0 = disable).");
1da177e4 133
dee1b66c
TI		 134/* reset the HD-audio controller in power save mode.
135 * this may give more power-saving, but will take longer time to
136 * wake up.
137 */
8fc24426
TI		 138static bool power_save_controller = 1;
139module_param(power_save_controller, bool, 0644);
dee1b66c 140MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
83012a7c 141#endif /* CONFIG_PM */
dee1b66c 142
7bfe059e
TI		 143static int align_buffer_size = -1;
144module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 145MODULE_PARM_DESC(align_buffer_size,
146 "Force buffer and period sizes to be multiple of 128 bytes.");
147
27fe48d9
TI		 148#ifdef CONFIG_X86
149static bool hda_snoop = true;
150module_param_named(snoop, hda_snoop, bool, 0444);
151MODULE_PARM_DESC(snoop, "Enable/disable snooping");
152#define azx_snoop(chip) (chip)->snoop
153#else
154#define hda_snoop true
155#define azx_snoop(chip) true
156#endif
157
158
1da177e4
LT		 159MODULE_LICENSE("GPL");
160MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
161 "{Intel, ICH6M},"
2f1b3818 162 "{Intel, ICH7},"
f5d40b30 163 "{Intel, ESB2},"
d2981393 164 "{Intel, ICH8},"
f9cc8a8b 165 "{Intel, ICH9},"
c34f5a04 166 "{Intel, ICH10},"
b29c2360 167 "{Intel, PCH},"
d2f2fcd2 168 "{Intel, CPT},"
d2edeb7c 169 "{Intel, PPT},"
8bc039a1 170 "{Intel, LPT},"
144dad99 171 "{Intel, LPT_LP},"
4eeca499 172 "{Intel, WPT_LP},"
e926f2c8 173 "{Intel, HPT},"
cea310e8 174 "{Intel, PBG},"
4979bca9 175 "{Intel, SCH},"
fc20a562 176 "{ATI, SB450},"
89be83f8 177 "{ATI, SB600},"
778b6e1b 178 "{ATI, RS600},"
5b15c95f 179 "{ATI, RS690},"
e6db1119
WL		 180 "{ATI, RS780},"
181 "{ATI, R600},"
2797f724
HRK		 182 "{ATI, RV630},"
183 "{ATI, RV610},"
27da1834
WL		 184 "{ATI, RV670},"
185 "{ATI, RV635},"
186 "{ATI, RV620},"
187 "{ATI, RV770},"
fc20a562 188 "{VIA, VT8251},"
47672310 189 "{VIA, VT8237A},"
07e4ca50
TI		 190 "{SiS, SIS966},"
191 "{ULI, M5461}}");
1da177e4
LT		 192MODULE_DESCRIPTION("Intel HDA driver");
193
4abc1cc2
TI		 194#ifdef CONFIG_SND_VERBOSE_PRINTK
195#define SFX /* nop */
196#else
445a51b3 197#define SFX "hda-intel "
4abc1cc2 198#endif
cb53c626 199
a82d51ed
TI		 200#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
201#ifdef CONFIG_SND_HDA_CODEC_HDMI
202#define SUPPORT_VGA_SWITCHEROO
203#endif
204#endif
205
206
1da177e4
LT		 207/*
208 * registers
209 */
210#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 211#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
212#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
213#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
214#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
215#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 216#define ICH6_REG_VMIN 0x02
217#define ICH6_REG_VMAJ 0x03
218#define ICH6_REG_OUTPAY 0x04
219#define ICH6_REG_INPAY 0x06
220#define ICH6_REG_GCTL 0x08
8a933ece 221#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 222#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
223#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 224#define ICH6_REG_WAKEEN 0x0c
225#define ICH6_REG_STATESTS 0x0e
226#define ICH6_REG_GSTS 0x10
b21fadb9 227#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 228#define ICH6_REG_INTCTL 0x20
229#define ICH6_REG_INTSTS 0x24
e5463720 230#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 231#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
232#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 233#define ICH6_REG_CORBLBASE 0x40
234#define ICH6_REG_CORBUBASE 0x44
235#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 236#define ICH6_REG_CORBRP 0x4a
237#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 238#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 239#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
240#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 241#define ICH6_REG_CORBSTS 0x4d
b21fadb9 242#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 243#define ICH6_REG_CORBSIZE 0x4e
244
245#define ICH6_REG_RIRBLBASE 0x50
246#define ICH6_REG_RIRBUBASE 0x54
247#define ICH6_REG_RIRBWP 0x58
b21fadb9 248#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 249#define ICH6_REG_RINTCNT 0x5a
250#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 251#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
252#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
253#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 254#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 255#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
256#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 257#define ICH6_REG_RIRBSIZE 0x5e
258
259#define ICH6_REG_IC 0x60
260#define ICH6_REG_IR 0x64
261#define ICH6_REG_IRS 0x68
262#define ICH6_IRS_VALID (1<<1)
263#define ICH6_IRS_BUSY (1<<0)
264
265#define ICH6_REG_DPLBASE 0x70
266#define ICH6_REG_DPUBASE 0x74
267#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
268
269/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
270enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
271
272/* stream register offsets from stream base */
273#define ICH6_REG_SD_CTL 0x00
274#define ICH6_REG_SD_STS 0x03
275#define ICH6_REG_SD_LPIB 0x04
276#define ICH6_REG_SD_CBL 0x08
277#define ICH6_REG_SD_LVI 0x0c
278#define ICH6_REG_SD_FIFOW 0x0e
279#define ICH6_REG_SD_FIFOSIZE 0x10
280#define ICH6_REG_SD_FORMAT 0x12
281#define ICH6_REG_SD_BDLPL 0x18
282#define ICH6_REG_SD_BDLPU 0x1c
283
284/* PCI space */
285#define ICH6_PCIREG_TCSEL 0x44
286
287/*
288 * other constants
289 */
290
291/* max number of SDs */
07e4ca50 292/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 293#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 294#define ICH6_NUM_PLAYBACK 4
295
296/* ULI has 6 playback and 5 capture */
07e4ca50 297#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 298#define ULI_NUM_PLAYBACK 6
299
778b6e1b 300/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 301#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 302#define ATIHDMI_NUM_PLAYBACK 1
303
f269002e
KY		 304/* TERA has 4 playback and 3 capture */
305#define TERA_NUM_CAPTURE 3
306#define TERA_NUM_PLAYBACK 4
307
07e4ca50
TI		 308/* this number is statically defined for simplicity */
309#define MAX_AZX_DEV 16
310
1da177e4 311/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 312#define BDL_SIZE 4096
313#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
314#define AZX_MAX_FRAG 32
1da177e4
LT		 315/* max buffer size - no h/w limit, you can increase as you like */
316#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 317
318/* RIRB int mask: overrun[2], response[0] */
319#define RIRB_INT_RESPONSE 0x01
320#define RIRB_INT_OVERRUN 0x04
321#define RIRB_INT_MASK 0x05
322
2f5983f2 323/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 324#define AZX_MAX_CODECS 8
325#define AZX_DEFAULT_CODECS 4
deadff16 326#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 327
328/* SD_CTL bits */
329#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
330#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 331#define SD_CTL_STRIPE (3 << 16) /* stripe control */
332#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
333#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 334#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
335#define SD_CTL_STREAM_TAG_SHIFT 20
336
337/* SD_CTL and SD_STS */
338#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
339#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
340#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 341#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
342 SD_INT_COMPLETE)
1da177e4
LT		 343
344/* SD_STS */
345#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
346
347/* INTCTL and INTSTS */
d01ce99f
TI		 348#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
349#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
350#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 351
1da177e4
LT		 352/* below are so far hardcoded - should read registers in future */
353#define ICH6_MAX_CORB_ENTRIES 256
354#define ICH6_MAX_RIRB_ENTRIES 256
355
c74db86b
TI		 356/* position fix mode */
357enum {
0be3b5d3 358 POS_FIX_AUTO,
d2e1c973 359 POS_FIX_LPIB,
0be3b5d3 360 POS_FIX_POSBUF,
4cb36310 361 POS_FIX_VIACOMBO,
a6f2fd55 362 POS_FIX_COMBO,
c74db86b 363};
1da177e4 364
f5d40b30 365/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 366#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
367#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
368
da3fca21
V		 369/* Defines for Nvidia HDA support */
370#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
371#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 372#define NVIDIA_HDA_ISTRM_COH 0x4d
373#define NVIDIA_HDA_OSTRM_COH 0x4c
374#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 375
90a5ad52
TI		 376/* Defines for Intel SCH HDA snoop control */
377#define INTEL_SCH_HDA_DEVC 0x78
378#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
379
0e153474
JC		 380/* Define IN stream 0 FIFO size offset in VIA controller */
381#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
382/* Define VIA HD Audio Device ID*/
383#define VIA_HDAC_DEVICE_ID 0x3288
384
c4da29ca
YL		 385/* HD Audio class code */
386#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 387
1da177e4
LT		 388/*
389 */
390
a98f90fd 391struct azx_dev {
4ce107b9 392 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 393 u32 *posbuf; /* position buffer pointer */
1da177e4 394
d01ce99f 395 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 396 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 397 unsigned int frags; /* number for period in the play buffer */
398 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 399 unsigned long start_wallclk; /* start + minimum wallclk */
400 unsigned long period_wallclk; /* wallclk for period */
1da177e4 401
d01ce99f 402 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 403
d01ce99f 404 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 405
406 /* pcm support */
d01ce99f
TI		 407 struct snd_pcm_substream *substream; /* assigned substream,
408 * set in PCM open
409 */
410 unsigned int format_val; /* format value to be set in the
411 * controller and the codec
412 */
1da177e4
LT		 413 unsigned char stream_tag; /* assigned stream */
414 unsigned char index; /* stream index */
d5cf9911 415 int assigned_key; /* last device# key assigned to */
1da177e4 416
927fc866
PM		 417 unsigned int opened :1;
418 unsigned int running :1;
675f25d4 419 unsigned int irq_pending :1;
eb49faa6
TI		 420 unsigned int prepared:1;
421 unsigned int locked:1;
0e153474
JC		 422 /*
423 * For VIA:
424 * A flag to ensure DMA position is 0
425 * when link position is not greater than FIFO size
426 */
427 unsigned int insufficient :1;
27fe48d9 428 unsigned int wc_marked:1;
915bf29e 429 unsigned int no_period_wakeup:1;
5d890f59
PLB		 430
431 struct timecounter azx_tc;
432 struct cyclecounter azx_cc;
eb49faa6
TI		 433
434#ifdef CONFIG_SND_HDA_DSP_LOADER
435 struct mutex dsp_mutex;
436#endif
1da177e4
LT		 437};
438
eb49faa6
TI		 439/* DSP lock helpers */
440#ifdef CONFIG_SND_HDA_DSP_LOADER
441#define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
442#define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
443#define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
444#define dsp_is_locked(dev) ((dev)->locked)
445#else
446#define dsp_lock_init(dev) do {} while (0)
447#define dsp_lock(dev) do {} while (0)
448#define dsp_unlock(dev) do {} while (0)
449#define dsp_is_locked(dev) 0
450#endif
451
1da177e4 452/* CORB/RIRB */
a98f90fd 453struct azx_rb {
1da177e4
LT		 454 u32 *buf; /* CORB/RIRB buffer
455 * Each CORB entry is 4byte, RIRB is 8byte
456 */
457 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
458 /* for RIRB */
459 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 460 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
461 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 462};
463
01b65bfb
TI		 464struct azx_pcm {
465 struct azx *chip;
466 struct snd_pcm *pcm;
467 struct hda_codec *codec;
468 struct hda_pcm_stream *hinfo[2];
469 struct list_head list;
470};
471
a98f90fd
TI		 472struct azx {
473 struct snd_card *card;
1da177e4 474 struct pci_dev *pci;
555e219f 475 int dev_index;
1da177e4 476
07e4ca50
TI		 477 /* chip type specific */
478 int driver_type;
9477c58e 479 unsigned int driver_caps;
07e4ca50
TI		 480 int playback_streams;
481 int playback_index_offset;
482 int capture_streams;
483 int capture_index_offset;
484 int num_streams;
485
1da177e4
LT		 486 /* pci resources */
487 unsigned long addr;
488 void __iomem *remap_addr;
489 int irq;
490
491 /* locks */
492 spinlock_t reg_lock;
62932df8 493 struct mutex open_mutex;
f4c482a4 494 struct completion probe_wait;
1da177e4 495
07e4ca50 496 /* streams (x num_streams) */
a98f90fd 497 struct azx_dev *azx_dev;
1da177e4
LT		 498
499 /* PCM */
01b65bfb 500 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 501
502 /* HD codec */
503 unsigned short codec_mask;
f1eaaeec 504 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 505 struct hda_bus *bus;
2dca0bba 506 unsigned int beep_mode;
1da177e4
LT		 507
508 /* CORB/RIRB */
a98f90fd
TI		 509 struct azx_rb corb;
510 struct azx_rb rirb;
1da177e4 511
4ce107b9 512 /* CORB/RIRB and position buffers */
1da177e4
LT		 513 struct snd_dma_buffer rb;
514 struct snd_dma_buffer posbuf;
c74db86b 515
4918cdab
TI		 516#ifdef CONFIG_SND_HDA_PATCH_LOADER
517 const struct firmware *fw;
518#endif
519
c74db86b 520 /* flags */
beaffc39 521 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 522 int poll_count;
cb53c626 523 unsigned int running :1;
927fc866
PM		 524 unsigned int initialized :1;
525 unsigned int single_cmd :1;
526 unsigned int polling_mode :1;
68e7fffc 527 unsigned int msi :1;
a6a950a8 528 unsigned int irq_pending_warned :1;
6ce4a3bc 529 unsigned int probing :1; /* codec probing phase */
27fe48d9 530 unsigned int snoop:1;
52409aa6 531 unsigned int align_buffer_size:1;
a82d51ed
TI		 532 unsigned int region_requested:1;
533
534 /* VGA-switcheroo setup */
535 unsigned int use_vga_switcheroo:1;
128960a9 536 unsigned int vga_switcheroo_registered:1;
a82d51ed
TI		 537 unsigned int init_failed:1; /* delayed init failed */
538 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 539
540 /* for debugging */
feb27340 541 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 542
543 /* for pending irqs */
544 struct work_struct irq_pending_work;
0cbf0098 545
99a2008d
WX		 546#ifdef CONFIG_SND_HDA_I915
547 struct work_struct probe_work;
548#endif
549
0cbf0098
TI		 550 /* reboot notifier (for mysterious hangup problem at power-down) */
551 struct notifier_block reboot_notifier;
65fcd41d
TI		 552
553 /* card list (for power_save trigger) */
554 struct list_head list;
eb49faa6
TI		 555
556#ifdef CONFIG_SND_HDA_DSP_LOADER
557 struct azx_dev saved_azx_dev;
558#endif
246efa4a
DA		 559
560 /* secondary power domain for hdmi audio under vga device */
561 struct dev_pm_domain hdmi_pm_domain;
1da177e4
LT		 562};
563
1a8506d4
TI		 564#define CREATE_TRACE_POINTS
565#include "hda_intel_trace.h"
566
07e4ca50
TI		 567/* driver types */
568enum {
569 AZX_DRIVER_ICH,
32679f95 570 AZX_DRIVER_PCH,
4979bca9 571 AZX_DRIVER_SCH,
07e4ca50 572 AZX_DRIVER_ATI,
778b6e1b 573 AZX_DRIVER_ATIHDMI,
1815b34a 574 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 575 AZX_DRIVER_VIA,
576 AZX_DRIVER_SIS,
577 AZX_DRIVER_ULI,
da3fca21 578 AZX_DRIVER_NVIDIA,
f269002e 579 AZX_DRIVER_TERA,
14d34f16 580 AZX_DRIVER_CTX,
5ae763b1 581 AZX_DRIVER_CTHDA,
c4da29ca 582 AZX_DRIVER_GENERIC,
2f5983f2 583 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 584};
585
9477c58e
TI		 586/* driver quirks (capabilities) */
587/* bits 0-7 are used for indicating driver type */
588#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
589#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
590#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
591#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
592#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
593#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
594#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
595#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
596#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
597#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
598#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
599#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 600#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 601#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 602#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 603#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
90accc58 604#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
2ea3c6a2 605#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
99a2008d 606#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 power well support */
2ea3c6a2
TI		 607
608/* quirks for Intel PCH */
d7dab4db 609#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 610 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 611 AZX_DCAPS_COUNT_LPIB_DELAY)
612
613#define AZX_DCAPS_INTEL_PCH \
614 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 615
33499a15
TI		 616#define AZX_DCAPS_INTEL_HASWELL \
617 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
618 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
619 AZX_DCAPS_I915_POWERWELL)
620
9477c58e
TI		 621/* quirks for ATI SB / AMD Hudson */
622#define AZX_DCAPS_PRESET_ATI_SB \
623 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
624 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
625
626/* quirks for ATI/AMD HDMI */
627#define AZX_DCAPS_PRESET_ATI_HDMI \
628 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
629
630/* quirks for Nvidia */
631#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 632 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
49d9e77e 633 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
9477c58e 634
5ae763b1
TI		 635#define AZX_DCAPS_PRESET_CTHDA \
636 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
637
a82d51ed
TI		 638/*
639 * VGA-switcher support
640 */
641#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 642#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
643#else
644#define use_vga_switcheroo(chip) 0
645#endif
646
48c8b0eb 647static char *driver_short_names[] = {
07e4ca50 648 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 649 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 650 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 651 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 652 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 653 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 654 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
655 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 656 [AZX_DRIVER_ULI] = "HDA ULI M5461",
657 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 658 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 659 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 660 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 661 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 662};
663
1da177e4
LT		 664/*
665 * macros for easy use
666 */
667#define azx_writel(chip,reg,value) \
668 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
669#define azx_readl(chip,reg) \
670 readl((chip)->remap_addr + ICH6_REG_##reg)
671#define azx_writew(chip,reg,value) \
672 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
673#define azx_readw(chip,reg) \
674 readw((chip)->remap_addr + ICH6_REG_##reg)
675#define azx_writeb(chip,reg,value) \
676 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
677#define azx_readb(chip,reg) \
678 readb((chip)->remap_addr + ICH6_REG_##reg)
679
680#define azx_sd_writel(dev,reg,value) \
681 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
682#define azx_sd_readl(dev,reg) \
683 readl((dev)->sd_addr + ICH6_REG_##reg)
684#define azx_sd_writew(dev,reg,value) \
685 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
686#define azx_sd_readw(dev,reg) \
687 readw((dev)->sd_addr + ICH6_REG_##reg)
688#define azx_sd_writeb(dev,reg,value) \
689 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
690#define azx_sd_readb(dev,reg) \
691 readb((dev)->sd_addr + ICH6_REG_##reg)
692
693/* for pcm support */
a98f90fd 694#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 695
27fe48d9 696#ifdef CONFIG_X86
9ddf1aeb 697static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 698{
9ddf1aeb
TI		 699 int pages;
700
27fe48d9
TI		 701 if (azx_snoop(chip))
702 return;
9ddf1aeb
TI		 703 if (!dmab || !dmab->area || !dmab->bytes)
704 return;
705
706#ifdef CONFIG_SND_DMA_SGBUF
707 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
708 struct snd_sg_buf *sgbuf = dmab->private_data;
27fe48d9 709 if (on)
9ddf1aeb 710 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 711 else
9ddf1aeb
TI		 712 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
713 return;
27fe48d9 714 }
9ddf1aeb
TI		 715#endif
716
717 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
718 if (on)
719 set_memory_wc((unsigned long)dmab->area, pages);
720 else
721 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 722}
723
724static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
725 bool on)
726{
9ddf1aeb 727 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 728}
729static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 730 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 731{
732 if (azx_dev->wc_marked != on) {
9ddf1aeb 733 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 734 azx_dev->wc_marked = on;
735 }
736}
737#else
738/* NOP for other archs */
739static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
740 bool on)
741{
742}
743static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 744 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 745{
746}
747#endif
748
68e7fffc 749static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 750static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 751/*
752 * Interface for HD codec
753 */
754
1da177e4
LT		 755/*
756 * CORB / RIRB interface
757 */
a98f90fd 758static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 759{
760 int err;
761
762 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 763 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
764 snd_dma_pci_data(chip->pci),
1da177e4
LT		 765 PAGE_SIZE, &chip->rb);
766 if (err < 0) {
445a51b3 767 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
1da177e4
LT		 768 return err;
769 }
27fe48d9 770 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 771 return 0;
772}
773
a98f90fd 774static void azx_init_cmd_io(struct azx *chip)
1da177e4 775{
cdb1fbf2 776 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 777 /* CORB set up */
778 chip->corb.addr = chip->rb.addr;
779 chip->corb.buf = (u32 *)chip->rb.area;
780 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 781 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 782
07e4ca50
TI		 783 /* set the corb size to 256 entries (ULI requires explicitly) */
784 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 785 /* set the corb write pointer to 0 */
786 azx_writew(chip, CORBWP, 0);
787 /* reset the corb hw read pointer */
b21fadb9 788 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 789 /* enable corb dma */
b21fadb9 790 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 791
792 /* RIRB set up */
793 chip->rirb.addr = chip->rb.addr + 2048;
794 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 795 chip->rirb.wp = chip->rirb.rp = 0;
796 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 797 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 798 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 799
07e4ca50
TI		 800 /* set the rirb size to 256 entries (ULI requires explicitly) */
801 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 802 /* reset the rirb hw write pointer */
b21fadb9 803 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 804 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 805 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 806 azx_writew(chip, RINTCNT, 0xc0);
807 else
808 azx_writew(chip, RINTCNT, 1);
1da177e4 809 /* enable rirb dma and response irq */
1da177e4 810 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 811 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 812}
813
a98f90fd 814static void azx_free_cmd_io(struct azx *chip)
1da177e4 815{
cdb1fbf2 816 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 817 /* disable ringbuffer DMAs */
818 azx_writeb(chip, RIRBCTL, 0);
819 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 820 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 821}
822
deadff16
WF		 823static unsigned int azx_command_addr(u32 cmd)
824{
825 unsigned int addr = cmd >> 28;
826
827 if (addr >= AZX_MAX_CODECS) {
828 snd_BUG();
829 addr = 0;
830 }
831
832 return addr;
833}
834
835static unsigned int azx_response_addr(u32 res)
836{
837 unsigned int addr = res & 0xf;
838
839 if (addr >= AZX_MAX_CODECS) {
840 snd_BUG();
841 addr = 0;
842 }
843
844 return addr;
1da177e4
LT		 845}
846
847/* send a command */
33fa35ed 848static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 849{
33fa35ed 850 struct azx *chip = bus->private_data;
deadff16 851 unsigned int addr = azx_command_addr(val);
3bcce5c0 852 unsigned int wp, rp;
1da177e4 853
c32649fe
WF		 854 spin_lock_irq(&chip->reg_lock);
855
1da177e4 856 /* add command to corb */
cc5ede3e
TI		 857 wp = azx_readw(chip, CORBWP);
858 if (wp == 0xffff) {
859 /* something wrong, controller likely turned to D3 */
860 spin_unlock_irq(&chip->reg_lock);
3bcce5c0 861 return -EIO;
cc5ede3e 862 }
1da177e4
LT		 863 wp++;
864 wp %= ICH6_MAX_CORB_ENTRIES;
865
3bcce5c0
TI		 866 rp = azx_readw(chip, CORBRP);
867 if (wp == rp) {
868 /* oops, it's full */
869 spin_unlock_irq(&chip->reg_lock);
870 return -EAGAIN;
871 }
872
deadff16 873 chip->rirb.cmds[addr]++;
1da177e4
LT		 874 chip->corb.buf[wp] = cpu_to_le32(val);
875 azx_writel(chip, CORBWP, wp);
c32649fe 876
1da177e4
LT		 877 spin_unlock_irq(&chip->reg_lock);
878
879 return 0;
880}
881
882#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
883
884/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 885static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 886{
887 unsigned int rp, wp;
deadff16 888 unsigned int addr;
1da177e4
LT		 889 u32 res, res_ex;
890
cc5ede3e
TI		 891 wp = azx_readw(chip, RIRBWP);
892 if (wp == 0xffff) {
893 /* something wrong, controller likely turned to D3 */
894 return;
895 }
896
1da177e4
LT		 897 if (wp == chip->rirb.wp)
898 return;
899 chip->rirb.wp = wp;
deadff16 900
1da177e4
LT		 901 while (chip->rirb.rp != wp) {
902 chip->rirb.rp++;
903 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
904
905 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
906 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
907 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 908 addr = azx_response_addr(res_ex);
1da177e4
LT		 909 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
910 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 911 else if (chip->rirb.cmds[addr]) {
912 chip->rirb.res[addr] = res;
2add9b92 913 smp_wmb();
deadff16 914 chip->rirb.cmds[addr]--;
e310bb06 915 } else
9e3d352b 916 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
e310bb06 917 "last cmd=%#08x\n",
9e3d352b 918 pci_name(chip->pci),
e310bb06
WF		 919 res, res_ex,
920 chip->last_cmd[addr]);
1da177e4
LT		 921 }
922}
923
924/* receive a response */
deadff16
WF		 925static unsigned int azx_rirb_get_response(struct hda_bus *bus,
926 unsigned int addr)
1da177e4 927{
33fa35ed 928 struct azx *chip = bus->private_data;
5c79b1f8 929 unsigned long timeout;
32cf4023 930 unsigned long loopcounter;
1eb6dc7d 931 int do_poll = 0;
1da177e4 932
5c79b1f8
TI		 933 again:
934 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 935
936 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 937 if (chip->polling_mode || do_poll) {
e96224ae
TI		 938 spin_lock_irq(&chip->reg_lock);
939 azx_update_rirb(chip);
940 spin_unlock_irq(&chip->reg_lock);
941 }
deadff16 942 if (!chip->rirb.cmds[addr]) {
2add9b92 943 smp_rmb();
b613291f 944 bus->rirb_error = 0;
1eb6dc7d
ML		 945
946 if (!do_poll)
947 chip->poll_count = 0;
deadff16 948 return chip->rirb.res[addr]; /* the last value */
2add9b92 949 }
28a0d9df
TI		 950 if (time_after(jiffies, timeout))
951 break;
32cf4023 952 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 953 msleep(2); /* temporary workaround */
954 else {
955 udelay(10);
956 cond_resched();
957 }
28a0d9df 958 }
5c79b1f8 959
63e51fd7
TI		 960 if (!bus->no_response_fallback)
961 return -1;
962
1eb6dc7d 963 if (!chip->polling_mode && chip->poll_count < 2) {
445a51b3 964 snd_printdd(SFX "%s: azx_get_response timeout, "
1eb6dc7d 965 "polling the codec once: last cmd=0x%08x\n",
445a51b3 966 pci_name(chip->pci), chip->last_cmd[addr]);
1eb6dc7d
ML		 967 do_poll = 1;
968 chip->poll_count++;
969 goto again;
970 }
971
972
23c4a881 973 if (!chip->polling_mode) {
445a51b3 974 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
23c4a881 975 "switching to polling mode: last cmd=0x%08x\n",
445a51b3 976 pci_name(chip->pci), chip->last_cmd[addr]);
23c4a881
TI		 977 chip->polling_mode = 1;
978 goto again;
979 }
980
68e7fffc 981 if (chip->msi) {
445a51b3 982 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
feb27340 983 "disabling MSI: last cmd=0x%08x\n",
445a51b3 984 pci_name(chip->pci), chip->last_cmd[addr]);
68e7fffc
TI		 985 free_irq(chip->irq, chip);
986 chip->irq = -1;
987 pci_disable_msi(chip->pci);
988 chip->msi = 0;
b613291f
TI		 989 if (azx_acquire_irq(chip, 1) < 0) {
990 bus->rirb_error = 1;
68e7fffc 991 return -1;
b613291f 992 }
68e7fffc
TI		 993 goto again;
994 }
995
6ce4a3bc
TI		 996 if (chip->probing) {
997 /* If this critical timeout happens during the codec probing
998 * phase, this is likely an access to a non-existing codec
999 * slot. Better to return an error and reset the system.
1000 */
1001 return -1;
1002 }
1003
8dd78330
TI		 1004 /* a fatal communication error; need either to reset or to fallback
1005 * to the single_cmd mode
1006 */
b613291f 1007 bus->rirb_error = 1;
b20f3b83 1008 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 1009 bus->response_reset = 1;
1010 return -1; /* give a chance to retry */
1011 }
1012
1013 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
1014 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 1015 chip->last_cmd[addr]);
8dd78330
TI		 1016 chip->single_cmd = 1;
1017 bus->response_reset = 0;
1a696978 1018 /* release CORB/RIRB */
4fcd3920 1019 azx_free_cmd_io(chip);
1a696978
TI		 1020 /* disable unsolicited responses */
1021 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 1022 return -1;
1da177e4
LT		 1023}
1024
1da177e4
LT		 1025/*
1026 * Use the single immediate command instead of CORB/RIRB for simplicity
1027 *
1028 * Note: according to Intel, this is not preferred use. The command was
1029 * intended for the BIOS only, and may get confused with unsolicited
1030 * responses. So, we shouldn't use it for normal operation from the
1031 * driver.
1032 * I left the codes, however, for debugging/testing purposes.
1033 */
1034
b05a7d4f 1035/* receive a response */
deadff16 1036static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 1037{
1038 int timeout = 50;
1039
1040 while (timeout--) {
1041 /* check IRV busy bit */
1042 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1043 /* reuse rirb.res as the response return value */
deadff16 1044 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 1045 return 0;
1046 }
1047 udelay(1);
1048 }
1049 if (printk_ratelimit())
445a51b3
DB		 1050 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1051 pci_name(chip->pci), azx_readw(chip, IRS));
deadff16 1052 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 1053 return -EIO;
1054}
1055
1da177e4 1056/* send a command */
33fa35ed 1057static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 1058{
33fa35ed 1059 struct azx *chip = bus->private_data;
deadff16 1060 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 1061 int timeout = 50;
1062
8dd78330 1063 bus->rirb_error = 0;
1da177e4
LT		 1064 while (timeout--) {
1065 /* check ICB busy bit */
d01ce99f 1066 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 1067 /* Clear IRV valid bit */
d01ce99f
TI		 1068 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1069 ICH6_IRS_VALID);
1da177e4 1070 azx_writel(chip, IC, val);
d01ce99f
TI		 1071 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1072 ICH6_IRS_BUSY);
deadff16 1073 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 1074 }
1075 udelay(1);
1076 }
1cfd52bc 1077 if (printk_ratelimit())
445a51b3
DB		 1078 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1079 pci_name(chip->pci), azx_readw(chip, IRS), val);
1da177e4
LT		 1080 return -EIO;
1081}
1082
1083/* receive a response */
deadff16
WF		 1084static unsigned int azx_single_get_response(struct hda_bus *bus,
1085 unsigned int addr)
1da177e4 1086{
33fa35ed 1087 struct azx *chip = bus->private_data;
deadff16 1088 return chip->rirb.res[addr];
1da177e4
LT		 1089}
1090
111d3af5
TI		 1091/*
1092 * The below are the main callbacks from hda_codec.
1093 *
1094 * They are just the skeleton to call sub-callbacks according to the
1095 * current setting of chip->single_cmd.
1096 */
1097
1098/* send a command */
33fa35ed 1099static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 1100{
33fa35ed 1101 struct azx *chip = bus->private_data;
43bbb6cc 1102
a82d51ed
TI		 1103 if (chip->disabled)
1104 return 0;
feb27340 1105 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 1106 if (chip->single_cmd)
33fa35ed 1107 return azx_single_send_cmd(bus, val);
111d3af5 1108 else
33fa35ed 1109 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 1110}
1111
1112/* get a response */
deadff16
WF		 1113static unsigned int azx_get_response(struct hda_bus *bus,
1114 unsigned int addr)
111d3af5 1115{
33fa35ed 1116 struct azx *chip = bus->private_data;
a82d51ed
TI		 1117 if (chip->disabled)
1118 return 0;
111d3af5 1119 if (chip->single_cmd)
deadff16 1120 return azx_single_get_response(bus, addr);
111d3af5 1121 else
deadff16 1122 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1123}
1124
83012a7c 1125#ifdef CONFIG_PM
68467f51 1126static void azx_power_notify(struct hda_bus *bus, bool power_up);
cb53c626 1127#endif
111d3af5 1128
1d1a4564
TI		 1129#ifdef CONFIG_SND_HDA_DSP_LOADER
1130static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1131 unsigned int byte_size,
1132 struct snd_dma_buffer *bufp);
1133static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1134static void azx_load_dsp_cleanup(struct hda_bus *bus,
1135 struct snd_dma_buffer *dmab);
1136#endif
1137
3af3f356 1138/* enter link reset */
7295b264 1139static void azx_enter_link_reset(struct azx *chip)
3af3f356
ML		 1140{
1141 unsigned long timeout;
1142
1143 /* reset controller */
1144 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1145
1146 timeout = jiffies + msecs_to_jiffies(100);
1147 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
1148 time_before(jiffies, timeout))
1149 usleep_range(500, 1000);
1150}
1151
7295b264
ML		 1152/* exit link reset */
1153static void azx_exit_link_reset(struct azx *chip)
1da177e4 1154{
fa348da5 1155 unsigned long timeout;
1da177e4 1156
7295b264
ML		 1157 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1158
1159 timeout = jiffies + msecs_to_jiffies(100);
1160 while (!azx_readb(chip, GCTL) &&
1161 time_before(jiffies, timeout))
1162 usleep_range(500, 1000);
1163}
1164
1165/* reset codec link */
1166static int azx_reset(struct azx *chip, int full_reset)
1167{
cd508fe5
JK		 1168 if (!full_reset)
1169 goto __skip;
1170
e8a7f136 1171 /* clear STATESTS */
da7db6ad 1172 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
e8a7f136 1173
1da177e4 1174 /* reset controller */
7295b264 1175 azx_enter_link_reset(chip);
1da177e4
LT		 1176
1177 /* delay for >= 100us for codec PLL to settle per spec
1178 * Rev 0.9 section 5.5.1
1179 */
fa348da5 1180 usleep_range(500, 1000);
1da177e4
LT		 1181
1182 /* Bring controller out of reset */
7295b264 1183 azx_exit_link_reset(chip);
1da177e4 1184
927fc866 1185 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
fa348da5 1186 usleep_range(1000, 1200);
1da177e4 1187
cd508fe5 1188 __skip:
1da177e4 1189 /* check to see if controller is ready */
927fc866 1190 if (!azx_readb(chip, GCTL)) {
445a51b3 1191 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1da177e4
LT		 1192 return -EBUSY;
1193 }
1194
41e2fce4 1195 /* Accept unsolicited responses */
1a696978
TI		 1196 if (!chip->single_cmd)
1197 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1198 ICH6_GCTL_UNSOL);
41e2fce4 1199
1da177e4 1200 /* detect codecs */
927fc866 1201 if (!chip->codec_mask) {
1da177e4 1202 chip->codec_mask = azx_readw(chip, STATESTS);
445a51b3 1203 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1da177e4
LT		 1204 }
1205
1206 return 0;
1207}
1208
1209
1210/*
1211 * Lowlevel interface
1212 */
1213
1214/* enable interrupts */
a98f90fd 1215static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1216{
1217 /* enable controller CIE and GIE */
1218 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1219 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1220}
1221
1222/* disable interrupts */
a98f90fd 1223static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1224{
1225 int i;
1226
1227 /* disable interrupts in stream descriptor */
07e4ca50 1228 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1229 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1230 azx_sd_writeb(azx_dev, SD_CTL,
1231 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1232 }
1233
1234 /* disable SIE for all streams */
1235 azx_writeb(chip, INTCTL, 0);
1236
1237 /* disable controller CIE and GIE */
1238 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1239 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1240}
1241
1242/* clear interrupts */
a98f90fd 1243static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1244{
1245 int i;
1246
1247 /* clear stream status */
07e4ca50 1248 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1249 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1250 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1251 }
1252
1253 /* clear STATESTS */
da7db6ad 1254 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1da177e4
LT		 1255
1256 /* clear rirb status */
1257 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1258
1259 /* clear int status */
1260 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1261}
1262
1263/* start a stream */
a98f90fd 1264static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1265{
0e153474
JC		 1266 /*
1267 * Before stream start, initialize parameter
1268 */
1269 azx_dev->insufficient = 1;
1270
1da177e4 1271 /* enable SIE */
ccc5df05
WN		 1272 azx_writel(chip, INTCTL,
1273 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1274 /* set DMA start and interrupt mask */
1275 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1276 SD_CTL_DMA_START | SD_INT_MASK);
1277}
1278
1dddab40
TI		 1279/* stop DMA */
1280static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1281{
1da177e4
LT		 1282 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1283 ~(SD_CTL_DMA_START | SD_INT_MASK));
1284 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1285}
1286
1287/* stop a stream */
1288static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1289{
1290 azx_stream_clear(chip, azx_dev);
1da177e4 1291 /* disable SIE */
ccc5df05
WN		 1292 azx_writel(chip, INTCTL,
1293 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1294}
1295
1296
1297/*
cb53c626 1298 * reset and start the controller registers
1da177e4 1299 */
cd508fe5 1300static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1301{
cb53c626
TI		 1302 if (chip->initialized)
1303 return;
1da177e4
LT		 1304
1305 /* reset controller */
cd508fe5 1306 azx_reset(chip, full_reset);
1da177e4
LT		 1307
1308 /* initialize interrupts */
1309 azx_int_clear(chip);
1310 azx_int_enable(chip);
1311
1312 /* initialize the codec command I/O */
1a696978
TI		 1313 if (!chip->single_cmd)
1314 azx_init_cmd_io(chip);
1da177e4 1315
0be3b5d3
TI		 1316 /* program the position buffer */
1317 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1318 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1319
cb53c626
TI		 1320 chip->initialized = 1;
1321}
1322
1323/*
1324 * initialize the PCI registers
1325 */
1326/* update bits in a PCI register byte */
1327static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1328 unsigned char mask, unsigned char val)
1329{
1330 unsigned char data;
1331
1332 pci_read_config_byte(pci, reg, &data);
1333 data &= ~mask;
1334 data |= (val & mask);
1335 pci_write_config_byte(pci, reg, data);
1336}
1337
1338static void azx_init_pci(struct azx *chip)
1339{
1340 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1341 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1342 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1343 * codecs.
1344 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1345 */
46f2cc80 1346 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
445a51b3 1347 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
a09e89f6 1348 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1349 }
cb53c626 1350
9477c58e
TI		 1351 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1352 * we need to enable snoop.
1353 */
1354 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
445a51b3 1355 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626 1356 update_pci_byte(chip->pci,
27fe48d9
TI		 1357 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1358 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1359 }
1360
1361 /* For NVIDIA HDA, enable snoop */
1362 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
445a51b3 1363 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626
TI		 1364 update_pci_byte(chip->pci,
1365 NVIDIA_HDA_TRANSREG_ADDR,
1366 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1367 update_pci_byte(chip->pci,
1368 NVIDIA_HDA_ISTRM_COH,
1369 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1370 update_pci_byte(chip->pci,
1371 NVIDIA_HDA_OSTRM_COH,
1372 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1373 }
1374
1375 /* Enable SCH/PCH snoop if needed */
1376 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1377 unsigned short snoop;
90a5ad52 1378 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1379 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1380 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1381 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1382 if (!azx_snoop(chip))
1383 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1384 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1385 pci_read_config_word(chip->pci,
1386 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1387 }
445a51b3
DB		 1388 snd_printdd(SFX "%s: SCH snoop: %s\n",
1389 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
27fe48d9 1390 ? "Disabled" : "Enabled");
da3fca21 1391 }
1da177e4
LT		 1392}
1393
1394
9ad593f6
TI		 1395static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1396
1da177e4
LT		 1397/*
1398 * interrupt handler
1399 */
7d12e780 1400static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1401{
a98f90fd
TI		 1402 struct azx *chip = dev_id;
1403 struct azx_dev *azx_dev;
1da177e4 1404 u32 status;
9ef04066 1405 u8 sd_status;
fa00e046 1406 int i, ok;
1da177e4 1407
b8dfc462 1408#ifdef CONFIG_PM_RUNTIME
246efa4a
DA		 1409 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1410 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1411 return IRQ_NONE;
b8dfc462
ML		 1412#endif
1413
1da177e4
LT		 1414 spin_lock(&chip->reg_lock);
1415
60911062
DC		 1416 if (chip->disabled) {
1417 spin_unlock(&chip->reg_lock);
a82d51ed 1418 return IRQ_NONE;
60911062 1419 }
a82d51ed 1420
1da177e4 1421 status = azx_readl(chip, INTSTS);
246efa4a 1422 if (status == 0 || status == 0xffffffff) {
1da177e4
LT		 1423 spin_unlock(&chip->reg_lock);
1424 return IRQ_NONE;
1425 }
1426
07e4ca50 1427 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1428 azx_dev = &chip->azx_dev[i];
1429 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1430 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1431 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1432 if (!azx_dev->substream || !azx_dev->running ||
1433 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1434 continue;
1435 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1436 ok = azx_position_ok(chip, azx_dev);
1437 if (ok == 1) {
9ad593f6 1438 azx_dev->irq_pending = 0;
1da177e4
LT		 1439 spin_unlock(&chip->reg_lock);
1440 snd_pcm_period_elapsed(azx_dev->substream);
1441 spin_lock(&chip->reg_lock);
fa00e046 1442 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1443 /* bogus IRQ, process it later */
1444 azx_dev->irq_pending = 1;
6acaed38
TI		 1445 queue_work(chip->bus->workq,
1446 &chip->irq_pending_work);
1da177e4
LT		 1447 }
1448 }
1449 }
1450
1451 /* clear rirb int */
1452 status = azx_readb(chip, RIRBSTS);
1453 if (status & RIRB_INT_MASK) {
14d34f16 1454 if (status & RIRB_INT_RESPONSE) {
9477c58e 1455 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1456 udelay(80);
1da177e4 1457 azx_update_rirb(chip);
14d34f16 1458 }
1da177e4
LT		 1459 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1460 }
1461
1462#if 0
1463 /* clear state status int */
da7db6ad
WX		 1464 if (azx_readw(chip, STATESTS) & 0x04)
1465 azx_writew(chip, STATESTS, 0x04);
1da177e4
LT		 1466#endif
1467 spin_unlock(&chip->reg_lock);
1468
1469 return IRQ_HANDLED;
1470}
1471
1472
675f25d4
TI		 1473/*
1474 * set up a BDL entry
1475 */
5ae763b1 1476static int setup_bdle(struct azx *chip,
1d1a4564 1477 struct snd_dma_buffer *dmab,
675f25d4
TI		 1478 struct azx_dev *azx_dev, u32 **bdlp,
1479 int ofs, int size, int with_ioc)
1480{
675f25d4
TI		 1481 u32 *bdl = *bdlp;
1482
1483 while (size > 0) {
1484 dma_addr_t addr;
1485 int chunk;
1486
1487 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1488 return -EINVAL;
1489
1d1a4564 1490 addr = snd_sgbuf_get_addr(dmab, ofs);
675f25d4
TI		 1491 /* program the address field of the BDL entry */
1492 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1493 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1494 /* program the size field of the BDL entry */
1d1a4564 1495 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
5ae763b1
TI		 1496 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1497 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1498 u32 remain = 0x1000 - (ofs & 0xfff);
1499 if (chunk > remain)
1500 chunk = remain;
1501 }
675f25d4
TI		 1502 bdl[2] = cpu_to_le32(chunk);
1503 /* program the IOC to enable interrupt
1504 * only when the whole fragment is processed
1505 */
1506 size -= chunk;
1507 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1508 bdl += 4;
1509 azx_dev->frags++;
1510 ofs += chunk;
1511 }
1512 *bdlp = bdl;
1513 return ofs;
1514}
1515
1da177e4
LT		 1516/*
1517 * set up BDL entries
1518 */
555e219f
TI		 1519static int azx_setup_periods(struct azx *chip,
1520 struct snd_pcm_substream *substream,
4ce107b9 1521 struct azx_dev *azx_dev)
1da177e4 1522{
4ce107b9
TI		 1523 u32 *bdl;
1524 int i, ofs, periods, period_bytes;
555e219f 1525 int pos_adj;
1da177e4
LT		 1526
1527 /* reset BDL address */
1528 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1529 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1530
97b71c94 1531 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1532 periods = azx_dev->bufsize / period_bytes;
1533
1da177e4 1534 /* program the initial BDL entries */
4ce107b9
TI		 1535 bdl = (u32 *)azx_dev->bdl.area;
1536 ofs = 0;
1537 azx_dev->frags = 0;
555e219f 1538 pos_adj = bdl_pos_adj[chip->dev_index];
915bf29e 1539 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
675f25d4 1540 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1541 int pos_align = pos_adj;
555e219f 1542 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1543 if (!pos_adj)
e785d3d8
TI		 1544 pos_adj = pos_align;
1545 else
1546 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1547 pos_align;
675f25d4
TI		 1548 pos_adj = frames_to_bytes(runtime, pos_adj);
1549 if (pos_adj >= period_bytes) {
445a51b3
DB		 1550 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1551 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1552 pos_adj = 0;
1553 } else {
1d1a4564
TI		 1554 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1555 azx_dev,
915bf29e 1556 &bdl, ofs, pos_adj, true);
675f25d4
TI		 1557 if (ofs < 0)
1558 goto error;
4ce107b9 1559 }
555e219f
TI		 1560 } else
1561 pos_adj = 0;
675f25d4
TI		 1562 for (i = 0; i < periods; i++) {
1563 if (i == periods - 1 && pos_adj)
1d1a4564
TI		 1564 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1565 azx_dev, &bdl, ofs,
675f25d4
TI		 1566 period_bytes - pos_adj, 0);
1567 else
1d1a4564
TI		 1568 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1569 azx_dev, &bdl, ofs,
7bb8fb70 1570 period_bytes,
915bf29e 1571 !azx_dev->no_period_wakeup);
675f25d4
TI		 1572 if (ofs < 0)
1573 goto error;
1da177e4 1574 }
4ce107b9 1575 return 0;
675f25d4
TI		 1576
1577 error:
445a51b3
DB		 1578 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1579 pci_name(chip->pci), azx_dev->bufsize, period_bytes);
675f25d4 1580 return -EINVAL;
1da177e4
LT		 1581}
1582
1dddab40
TI		 1583/* reset stream */
1584static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1585{
1586 unsigned char val;
1587 int timeout;
1588
1dddab40
TI		 1589 azx_stream_clear(chip, azx_dev);
1590
d01ce99f
TI		 1591 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1592 SD_CTL_STREAM_RESET);
1da177e4
LT		 1593 udelay(3);
1594 timeout = 300;
1595 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1596 --timeout)
1597 ;
1598 val &= ~SD_CTL_STREAM_RESET;
1599 azx_sd_writeb(azx_dev, SD_CTL, val);
1600 udelay(3);
1601
1602 timeout = 300;
1603 /* waiting for hardware to report that the stream is out of reset */
1604 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1605 --timeout)
1606 ;
fa00e046
JK		 1607
1608 /* reset first position - may not be synced with hw at this time */
1609 *azx_dev->posbuf = 0;
1dddab40 1610}
1da177e4 1611
1dddab40
TI		 1612/*
1613 * set up the SD for streaming
1614 */
1615static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1616{
27fe48d9 1617 unsigned int val;
1dddab40
TI		 1618 /* make sure the run bit is zero for SD */
1619 azx_stream_clear(chip, azx_dev);
1da177e4 1620 /* program the stream_tag */
27fe48d9
TI		 1621 val = azx_sd_readl(azx_dev, SD_CTL);
1622 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1623 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1624 if (!azx_snoop(chip))
1625 val |= SD_CTL_TRAFFIC_PRIO;
1626 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1627
1628 /* program the length of samples in cyclic buffer */
1629 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1630
1631 /* program the stream format */
1632 /* this value needs to be the same as the one programmed */
1633 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1634
1635 /* program the stream LVI (last valid index) of the BDL */
1636 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1637
1638 /* program the BDL address */
1639 /* lower BDL address */
4ce107b9 1640 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1641 /* upper BDL address */
766979e0 1642 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1643
0be3b5d3 1644 /* enable the position buffer */
4cb36310
DH		 1645 if (chip->position_fix[0] != POS_FIX_LPIB ||
1646 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1647 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1648 azx_writel(chip, DPLBASE,
1649 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1650 }
c74db86b 1651
1da177e4 1652 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1653 azx_sd_writel(azx_dev, SD_CTL,
1654 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1655
1656 return 0;
1657}
1658
6ce4a3bc
TI		 1659/*
1660 * Probe the given codec address
1661 */
1662static int probe_codec(struct azx *chip, int addr)
1663{
1664 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1665 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1666 unsigned int res;
1667
a678cdee 1668 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1669 chip->probing = 1;
1670 azx_send_cmd(chip->bus, cmd);
deadff16 1671 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1672 chip->probing = 0;
a678cdee 1673 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1674 if (res == -1)
1675 return -EIO;
445a51b3 1676 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
6ce4a3bc
TI		 1677 return 0;
1678}
1679
33fa35ed
TI		 1680static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1681 struct hda_pcm *cpcm);
6ce4a3bc 1682static void azx_stop_chip(struct azx *chip);
1da177e4 1683
8dd78330
TI		 1684static void azx_bus_reset(struct hda_bus *bus)
1685{
1686 struct azx *chip = bus->private_data;
8dd78330
TI		 1687
1688 bus->in_reset = 1;
1689 azx_stop_chip(chip);
cd508fe5 1690 azx_init_chip(chip, 1);
65f75983 1691#ifdef CONFIG_PM
8dd78330 1692 if (chip->initialized) {
01b65bfb
TI		 1693 struct azx_pcm *p;
1694 list_for_each_entry(p, &chip->pcm_list, list)
1695 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1696 snd_hda_suspend(chip->bus);
1697 snd_hda_resume(chip->bus);
1698 }
65f75983 1699#endif
8dd78330
TI		 1700 bus->in_reset = 0;
1701}
1702
26a6cb6c
DH		 1703static int get_jackpoll_interval(struct azx *chip)
1704{
1705 int i = jackpoll_ms[chip->dev_index];
1706 unsigned int j;
1707 if (i == 0)
1708 return 0;
1709 if (i < 50 || i > 60000)
1710 j = 0;
1711 else
1712 j = msecs_to_jiffies(i);
1713 if (j == 0)
1714 snd_printk(KERN_WARNING SFX
1715 "jackpoll_ms value out of range: %d\n", i);
1716 return j;
1717}
1718
1da177e4
LT		 1719/*
1720 * Codec initialization
1721 */
1722
2f5983f2 1723/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
48c8b0eb 1724static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
7445dfc1 1725 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1726 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1727};
1728
48c8b0eb 1729static int azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1730{
1731 struct hda_bus_template bus_temp;
34c25350
TI		 1732 int c, codecs, err;
1733 int max_slots;
1da177e4
LT		 1734
1735 memset(&bus_temp, 0, sizeof(bus_temp));
1736 bus_temp.private_data = chip;
1737 bus_temp.modelname = model;
1738 bus_temp.pci = chip->pci;
111d3af5
TI		 1739 bus_temp.ops.command = azx_send_cmd;
1740 bus_temp.ops.get_response = azx_get_response;
176d5335 1741 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1742 bus_temp.ops.bus_reset = azx_bus_reset;
83012a7c 1743#ifdef CONFIG_PM
11cd41b8 1744 bus_temp.power_save = &power_save;
cb53c626
TI		 1745 bus_temp.ops.pm_notify = azx_power_notify;
1746#endif
1d1a4564
TI		 1747#ifdef CONFIG_SND_HDA_DSP_LOADER
1748 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1749 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1750 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1751#endif
1da177e4 1752
d01ce99f
TI		 1753 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1754 if (err < 0)
1da177e4
LT		 1755 return err;
1756
9477c58e 1757 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
445a51b3 1758 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
dc9c8e21 1759 chip->bus->needs_damn_long_delay = 1;
9477c58e 1760 }
dc9c8e21 1761
34c25350 1762 codecs = 0;
2f5983f2
TI		 1763 max_slots = azx_max_codecs[chip->driver_type];
1764 if (!max_slots)
7445dfc1 1765 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1766
1767 /* First try to probe all given codec slots */
1768 for (c = 0; c < max_slots; c++) {
f1eaaeec 1769 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1770 if (probe_codec(chip, c) < 0) {
1771 /* Some BIOSen give you wrong codec addresses
1772 * that don't exist
1773 */
4abc1cc2 1774 snd_printk(KERN_WARNING SFX
445a51b3
DB		 1775 "%s: Codec #%d probe error; "
1776 "disabling it...\n", pci_name(chip->pci), c);
6ce4a3bc
TI		 1777 chip->codec_mask &= ~(1 << c);
1778 /* More badly, accessing to a non-existing
1779 * codec often screws up the controller chip,
2448158e 1780 * and disturbs the further communications.
6ce4a3bc
TI		 1781 * Thus if an error occurs during probing,
1782 * better to reset the controller chip to
1783 * get back to the sanity state.
1784 */
1785 azx_stop_chip(chip);
cd508fe5 1786 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1787 }
1788 }
1789 }
1790
d507cd66
TI		 1791 /* AMD chipsets often cause the communication stalls upon certain
1792 * sequence like the pin-detection. It seems that forcing the synced
1793 * access works around the stall. Grrr...
1794 */
9477c58e 1795 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
445a51b3
DB		 1796 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1797 pci_name(chip->pci));
d507cd66
TI		 1798 chip->bus->sync_write = 1;
1799 chip->bus->allow_bus_reset = 1;
1800 }
1801
6ce4a3bc 1802 /* Then create codec instances */
34c25350 1803 for (c = 0; c < max_slots; c++) {
f1eaaeec 1804 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1805 struct hda_codec *codec;
a1e21c90 1806 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1807 if (err < 0)
1808 continue;
26a6cb6c 1809 codec->jackpoll_interval = get_jackpoll_interval(chip);
2dca0bba 1810 codec->beep_mode = chip->beep_mode;
1da177e4 1811 codecs++;
19a982b6
TI		 1812 }
1813 }
1814 if (!codecs) {
445a51b3 1815 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1da177e4
LT		 1816 return -ENXIO;
1817 }
a1e21c90
TI		 1818 return 0;
1819}
1da177e4 1820
a1e21c90 1821/* configure each codec instance */
e23e7a14 1822static int azx_codec_configure(struct azx *chip)
a1e21c90
TI		 1823{
1824 struct hda_codec *codec;
1825 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1826 snd_hda_codec_configure(codec);
1827 }
1da177e4
LT		 1828 return 0;
1829}
1830
1831
1832/*
1833 * PCM support
1834 */
1835
1836/* assign a stream for the PCM */
ef18bede
WF		 1837static inline struct azx_dev *
1838azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1839{
07e4ca50 1840 int dev, i, nums;
ef18bede 1841 struct azx_dev *res = NULL;
d5cf9911
TI		 1842 /* make a non-zero unique key for the substream */
1843 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1844 (substream->stream + 1);
ef18bede
WF		 1845
1846 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1847 dev = chip->playback_index_offset;
1848 nums = chip->playback_streams;
1849 } else {
1850 dev = chip->capture_index_offset;
1851 nums = chip->capture_streams;
1852 }
eb49faa6
TI		 1853 for (i = 0; i < nums; i++, dev++) {
1854 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1855 dsp_lock(azx_dev);
1856 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1857 res = azx_dev;
1858 if (res->assigned_key == key) {
1859 res->opened = 1;
1860 res->assigned_key = key;
1861 dsp_unlock(azx_dev);
1862 return azx_dev;
1863 }
1da177e4 1864 }
eb49faa6
TI		 1865 dsp_unlock(azx_dev);
1866 }
ef18bede 1867 if (res) {
eb49faa6 1868 dsp_lock(res);
ef18bede 1869 res->opened = 1;
d5cf9911 1870 res->assigned_key = key;
eb49faa6 1871 dsp_unlock(res);
ef18bede
WF		 1872 }
1873 return res;
1da177e4
LT		 1874}
1875
1876/* release the assigned stream */
a98f90fd 1877static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1878{
1879 azx_dev->opened = 0;
1880}
1881
5d890f59
PLB		 1882static cycle_t azx_cc_read(const struct cyclecounter *cc)
1883{
1884 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1885 struct snd_pcm_substream *substream = azx_dev->substream;
1886 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1887 struct azx *chip = apcm->chip;
1888
1889 return azx_readl(chip, WALLCLK);
1890}
1891
1892static void azx_timecounter_init(struct snd_pcm_substream *substream,
1893 bool force, cycle_t last)
1894{
1895 struct azx_dev *azx_dev = get_azx_dev(substream);
1896 struct timecounter *tc = &azx_dev->azx_tc;
1897 struct cyclecounter *cc = &azx_dev->azx_cc;
1898 u64 nsec;
1899
1900 cc->read = azx_cc_read;
1901 cc->mask = CLOCKSOURCE_MASK(32);
1902
1903 /*
1904 * Converting from 24 MHz to ns means applying a 125/3 factor.
1905 * To avoid any saturation issues in intermediate operations,
1906 * the 125 factor is applied first. The division is applied
1907 * last after reading the timecounter value.
1908 * Applying the 1/3 factor as part of the multiplication
1909 * requires at least 20 bits for a decent precision, however
1910 * overflows occur after about 4 hours or less, not a option.
1911 */
1912
1913 cc->mult = 125; /* saturation after 195 years */
1914 cc->shift = 0;
1915
1916 nsec = 0; /* audio time is elapsed time since trigger */
1917 timecounter_init(tc, cc, nsec);
1918 if (force)
1919 /*
1920 * force timecounter to use predefined value,
1921 * used for synchronized starts
1922 */
1923 tc->cycle_last = last;
1924}
1925
ae03bbb8 1926static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
78daea29
DR		 1927 u64 nsec)
1928{
1929 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1930 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1931 u64 codec_frames, codec_nsecs;
1932
1933 if (!hinfo->ops.get_delay)
1934 return nsec;
1935
1936 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1937 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1938 substream->runtime->rate);
1939
ae03bbb8
DR		 1940 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1941 return nsec + codec_nsecs;
1942
78daea29
DR		 1943 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1944}
1945
5d890f59
PLB		 1946static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1947 struct timespec *ts)
1948{
1949 struct azx_dev *azx_dev = get_azx_dev(substream);
1950 u64 nsec;
1951
1952 nsec = timecounter_read(&azx_dev->azx_tc);
1953 nsec = div_u64(nsec, 3); /* can be optimized */
ae03bbb8 1954 nsec = azx_adjust_codec_delay(substream, nsec);
5d890f59
PLB		 1955
1956 *ts = ns_to_timespec(nsec);
1957
1958 return 0;
1959}
1960
a98f90fd 1961static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1962 .info = (SNDRV_PCM_INFO_MMAP |
1963 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1964 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1965 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1966 /* No full-resume yet implemented */
1967 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1968 SNDRV_PCM_INFO_PAUSE |
7bb8fb70 1969 SNDRV_PCM_INFO_SYNC_START |
5d890f59 1970 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
7bb8fb70 1971 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1972 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1973 .rates = SNDRV_PCM_RATE_48000,
1974 .rate_min = 48000,
1975 .rate_max = 48000,
1976 .channels_min = 2,
1977 .channels_max = 2,
1978 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1979 .period_bytes_min = 128,
1980 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1981 .periods_min = 2,
1982 .periods_max = AZX_MAX_FRAG,
1983 .fifo_size = 0,
1984};
1985
a98f90fd 1986static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1987{
1988 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1989 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1990 struct azx *chip = apcm->chip;
1991 struct azx_dev *azx_dev;
1992 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1993 unsigned long flags;
1994 int err;
2ae66c26 1995 int buff_step;
1da177e4 1996
62932df8 1997 mutex_lock(&chip->open_mutex);
ef18bede 1998 azx_dev = azx_assign_device(chip, substream);
1da177e4 1999 if (azx_dev == NULL) {
62932df8 2000 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2001 return -EBUSY;
2002 }
2003 runtime->hw = azx_pcm_hw;
2004 runtime->hw.channels_min = hinfo->channels_min;
2005 runtime->hw.channels_max = hinfo->channels_max;
2006 runtime->hw.formats = hinfo->formats;
2007 runtime->hw.rates = hinfo->rates;
2008 snd_pcm_limit_hw_rates(runtime);
2009 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5d890f59
PLB		 2010
2011 /* avoid wrap-around with wall-clock */
2012 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
2013 20,
2014 178000000);
2015
52409aa6 2016 if (chip->align_buffer_size)
2ae66c26
PLB		 2017 /* constrain buffer sizes to be multiple of 128
2018 bytes. This is more efficient in terms of memory
2019 access but isn't required by the HDA spec and
2020 prevents users from specifying exact period/buffer
2021 sizes. For example for 44.1kHz, a period size set
2022 to 20ms will be rounded to 19.59ms. */
2023 buff_step = 128;
2024 else
2025 /* Don't enforce steps on buffer sizes, still need to
2026 be multiple of 4 bytes (HDA spec). Tested on Intel
2027 HDA controllers, may not work on all devices where
2028 option needs to be disabled */
2029 buff_step = 4;
2030
5f1545bc 2031 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 2032 buff_step);
5f1545bc 2033 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 2034 buff_step);
b4a91cf0 2035 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 2036 err = hinfo->ops.open(hinfo, apcm->codec, substream);
2037 if (err < 0) {
1da177e4 2038 azx_release_device(azx_dev);
cb53c626 2039 snd_hda_power_down(apcm->codec);
62932df8 2040 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2041 return err;
2042 }
70d321e6 2043 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 2044 /* sanity check */
2045 if (snd_BUG_ON(!runtime->hw.channels_min) ||
2046 snd_BUG_ON(!runtime->hw.channels_max) ||
2047 snd_BUG_ON(!runtime->hw.formats) ||
2048 snd_BUG_ON(!runtime->hw.rates)) {
2049 azx_release_device(azx_dev);
2050 hinfo->ops.close(hinfo, apcm->codec, substream);
2051 snd_hda_power_down(apcm->codec);
2052 mutex_unlock(&chip->open_mutex);
2053 return -EINVAL;
2054 }
5d890f59
PLB		 2055
2056 /* disable WALLCLOCK timestamps for capture streams
2057 until we figure out how to handle digital inputs */
2058 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2059 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2060
1da177e4
LT		 2061 spin_lock_irqsave(&chip->reg_lock, flags);
2062 azx_dev->substream = substream;
2063 azx_dev->running = 0;
2064 spin_unlock_irqrestore(&chip->reg_lock, flags);
2065
2066 runtime->private_data = azx_dev;
850f0e52 2067 snd_pcm_set_sync(substream);
62932df8 2068 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2069 return 0;
2070}
2071
a98f90fd 2072static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 2073{
2074 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2075 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 2076 struct azx *chip = apcm->chip;
2077 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 2078 unsigned long flags;
2079
62932df8 2080 mutex_lock(&chip->open_mutex);
1da177e4
LT		 2081 spin_lock_irqsave(&chip->reg_lock, flags);
2082 azx_dev->substream = NULL;
2083 azx_dev->running = 0;
2084 spin_unlock_irqrestore(&chip->reg_lock, flags);
2085 azx_release_device(azx_dev);
2086 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 2087 snd_hda_power_down(apcm->codec);
62932df8 2088 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2089 return 0;
2090}
2091
d01ce99f
TI		 2092static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2093 struct snd_pcm_hw_params *hw_params)
1da177e4 2094{
27fe48d9
TI		 2095 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2096 struct azx *chip = apcm->chip;
97b71c94 2097 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 2098 int ret;
97b71c94 2099
eb49faa6
TI		 2100 dsp_lock(azx_dev);
2101 if (dsp_is_locked(azx_dev)) {
2102 ret = -EBUSY;
2103 goto unlock;
2104 }
2105
9ddf1aeb 2106 mark_runtime_wc(chip, azx_dev, substream, false);
97b71c94
TI		 2107 azx_dev->bufsize = 0;
2108 azx_dev->period_bytes = 0;
2109 azx_dev->format_val = 0;
27fe48d9 2110 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 2111 params_buffer_bytes(hw_params));
27fe48d9 2112 if (ret < 0)
eb49faa6 2113 goto unlock;
9ddf1aeb 2114 mark_runtime_wc(chip, azx_dev, substream, true);
eb49faa6
TI		 2115 unlock:
2116 dsp_unlock(azx_dev);
27fe48d9 2117 return ret;
1da177e4
LT		 2118}
2119
a98f90fd 2120static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 2121{
2122 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2123 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 2124 struct azx *chip = apcm->chip;
1da177e4
LT		 2125 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2126
2127 /* reset BDL address */
eb49faa6
TI		 2128 dsp_lock(azx_dev);
2129 if (!dsp_is_locked(azx_dev)) {
2130 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2131 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2132 azx_sd_writel(azx_dev, SD_CTL, 0);
2133 azx_dev->bufsize = 0;
2134 azx_dev->period_bytes = 0;
2135 azx_dev->format_val = 0;
2136 }
1da177e4 2137
eb541337 2138 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 2139
9ddf1aeb 2140 mark_runtime_wc(chip, azx_dev, substream, false);
eb49faa6
TI		 2141 azx_dev->prepared = 0;
2142 dsp_unlock(azx_dev);
1da177e4
LT		 2143 return snd_pcm_lib_free_pages(substream);
2144}
2145
a98f90fd 2146static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 2147{
2148 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 2149 struct azx *chip = apcm->chip;
2150 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 2151 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 2152 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 2153 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 2154 int err;
7c935976
SW		 2155 struct hda_spdif_out *spdif =
2156 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2157 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 2158
eb49faa6
TI		 2159 dsp_lock(azx_dev);
2160 if (dsp_is_locked(azx_dev)) {
2161 err = -EBUSY;
2162 goto unlock;
2163 }
2164
fa00e046 2165 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 2166 format_val = snd_hda_calc_stream_format(runtime->rate,
2167 runtime->channels,
2168 runtime->format,
32c168c8 2169 hinfo->maxbps,
7c935976 2170 ctls);
97b71c94 2171 if (!format_val) {
d01ce99f 2172 snd_printk(KERN_ERR SFX
445a51b3
DB		 2173 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2174 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
eb49faa6
TI		 2175 err = -EINVAL;
2176 goto unlock;
1da177e4
LT		 2177 }
2178
97b71c94
TI		 2179 bufsize = snd_pcm_lib_buffer_bytes(substream);
2180 period_bytes = snd_pcm_lib_period_bytes(substream);
2181
445a51b3
DB		 2182 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2183 pci_name(chip->pci), bufsize, format_val);
97b71c94
TI		 2184
2185 if (bufsize != azx_dev->bufsize ||
2186 period_bytes != azx_dev->period_bytes ||
915bf29e
TI		 2187 format_val != azx_dev->format_val ||
2188 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
97b71c94
TI		 2189 azx_dev->bufsize = bufsize;
2190 azx_dev->period_bytes = period_bytes;
2191 azx_dev->format_val = format_val;
915bf29e 2192 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
97b71c94
TI		 2193 err = azx_setup_periods(chip, substream, azx_dev);
2194 if (err < 0)
eb49faa6 2195 goto unlock;
97b71c94
TI		 2196 }
2197
e5463720
JK		 2198 /* wallclk has 24Mhz clock source */
2199 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2200 runtime->rate) * 1000);
1da177e4
LT		 2201 azx_setup_controller(chip, azx_dev);
2202 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2203 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2204 else
2205 azx_dev->fifo_size = 0;
2206
62b7e5e0
TI		 2207 stream_tag = azx_dev->stream_tag;
2208 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 2209 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 2210 stream_tag > chip->capture_streams)
2211 stream_tag -= chip->capture_streams;
eb49faa6 2212 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 2213 azx_dev->format_val, substream);
eb49faa6
TI		 2214
2215 unlock:
2216 if (!err)
2217 azx_dev->prepared = 1;
2218 dsp_unlock(azx_dev);
2219 return err;
1da177e4
LT		 2220}
2221
a98f90fd 2222static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 2223{
2224 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2225 struct azx *chip = apcm->chip;
850f0e52
TI		 2226 struct azx_dev *azx_dev;
2227 struct snd_pcm_substream *s;
fa00e046 2228 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 2229 int nwait, timeout;
1da177e4 2230
1a8506d4
TI		 2231 azx_dev = get_azx_dev(substream);
2232 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2233
eb49faa6
TI		 2234 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2235 return -EPIPE;
2236
1da177e4 2237 switch (cmd) {
fa00e046
JK		 2238 case SNDRV_PCM_TRIGGER_START:
2239 rstart = 1;
1da177e4
LT		 2240 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2241 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 2242 start = 1;
1da177e4
LT		 2243 break;
2244 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 2245 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 2246 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 2247 start = 0;
1da177e4
LT		 2248 break;
2249 default:
850f0e52
TI		 2250 return -EINVAL;
2251 }
2252
2253 snd_pcm_group_for_each_entry(s, substream) {
2254 if (s->pcm->card != substream->pcm->card)
2255 continue;
2256 azx_dev = get_azx_dev(s);
2257 sbits |= 1 << azx_dev->index;
2258 nsync++;
2259 snd_pcm_trigger_done(s, substream);
2260 }
2261
2262 spin_lock(&chip->reg_lock);
172d3b20
PLB		 2263
2264 /* first, set SYNC bits of corresponding streams */
2265 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2266 azx_writel(chip, OLD_SSYNC,
2267 azx_readl(chip, OLD_SSYNC) | sbits);
2268 else
2269 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2270
850f0e52
TI		 2271 snd_pcm_group_for_each_entry(s, substream) {
2272 if (s->pcm->card != substream->pcm->card)
2273 continue;
2274 azx_dev = get_azx_dev(s);
e5463720
JK		 2275 if (start) {
2276 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2277 if (!rstart)
2278 azx_dev->start_wallclk -=
2279 azx_dev->period_wallclk;
850f0e52 2280 azx_stream_start(chip, azx_dev);
e5463720 2281 } else {
850f0e52 2282 azx_stream_stop(chip, azx_dev);
e5463720 2283 }
850f0e52 2284 azx_dev->running = start;
1da177e4
LT		 2285 }
2286 spin_unlock(&chip->reg_lock);
850f0e52 2287 if (start) {
850f0e52
TI		 2288 /* wait until all FIFOs get ready */
2289 for (timeout = 5000; timeout; timeout--) {
2290 nwait = 0;
2291 snd_pcm_group_for_each_entry(s, substream) {
2292 if (s->pcm->card != substream->pcm->card)
2293 continue;
2294 azx_dev = get_azx_dev(s);
2295 if (!(azx_sd_readb(azx_dev, SD_STS) &
2296 SD_STS_FIFO_READY))
2297 nwait++;
2298 }
2299 if (!nwait)
2300 break;
2301 cpu_relax();
2302 }
2303 } else {
2304 /* wait until all RUN bits are cleared */
2305 for (timeout = 5000; timeout; timeout--) {
2306 nwait = 0;
2307 snd_pcm_group_for_each_entry(s, substream) {
2308 if (s->pcm->card != substream->pcm->card)
2309 continue;
2310 azx_dev = get_azx_dev(s);
2311 if (azx_sd_readb(azx_dev, SD_CTL) &
2312 SD_CTL_DMA_START)
2313 nwait++;
2314 }
2315 if (!nwait)
2316 break;
2317 cpu_relax();
2318 }
1da177e4 2319 }
172d3b20
PLB		 2320 spin_lock(&chip->reg_lock);
2321 /* reset SYNC bits */
2322 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2323 azx_writel(chip, OLD_SSYNC,
2324 azx_readl(chip, OLD_SSYNC) & ~sbits);
2325 else
2326 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
5d890f59
PLB		 2327 if (start) {
2328 azx_timecounter_init(substream, 0, 0);
2329 if (nsync > 1) {
2330 cycle_t cycle_last;
2331
2332 /* same start cycle for master and group */
2333 azx_dev = get_azx_dev(substream);
2334 cycle_last = azx_dev->azx_tc.cycle_last;
2335
2336 snd_pcm_group_for_each_entry(s, substream) {
2337 if (s->pcm->card != substream->pcm->card)
2338 continue;
2339 azx_timecounter_init(s, 1, cycle_last);
2340 }
2341 }
2342 }
172d3b20 2343 spin_unlock(&chip->reg_lock);
850f0e52 2344 return 0;
1da177e4
LT		 2345}
2346
0e153474
JC		 2347/* get the current DMA position with correction on VIA chips */
2348static unsigned int azx_via_get_position(struct azx *chip,
2349 struct azx_dev *azx_dev)
2350{
2351 unsigned int link_pos, mini_pos, bound_pos;
2352 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2353 unsigned int fifo_size;
2354
2355 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2356 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2357 /* Playback, no problem using link position */
2358 return link_pos;
2359 }
2360
2361 /* Capture */
2362 /* For new chipset,
2363 * use mod to get the DMA position just like old chipset
2364 */
2365 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2366 mod_dma_pos %= azx_dev->period_bytes;
2367
2368 /* azx_dev->fifo_size can't get FIFO size of in stream.
2369 * Get from base address + offset.
2370 */
2371 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2372
2373 if (azx_dev->insufficient) {
2374 /* Link position never gather than FIFO size */
2375 if (link_pos <= fifo_size)
2376 return 0;
2377
2378 azx_dev->insufficient = 0;
2379 }
2380
2381 if (link_pos <= fifo_size)
2382 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2383 else
2384 mini_pos = link_pos - fifo_size;
2385
2386 /* Find nearest previous boudary */
2387 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2388 mod_link_pos = link_pos % azx_dev->period_bytes;
2389 if (mod_link_pos >= fifo_size)
2390 bound_pos = link_pos - mod_link_pos;
2391 else if (mod_dma_pos >= mod_mini_pos)
2392 bound_pos = mini_pos - mod_mini_pos;
2393 else {
2394 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2395 if (bound_pos >= azx_dev->bufsize)
2396 bound_pos = 0;
2397 }
2398
2399 /* Calculate real DMA position we want */
2400 return bound_pos + mod_dma_pos;
2401}
2402
9ad593f6 2403static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2404 struct azx_dev *azx_dev,
2405 bool with_check)
1da177e4 2406{
21229613
TI		 2407 struct snd_pcm_substream *substream = azx_dev->substream;
2408 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1da177e4 2409 unsigned int pos;
21229613
TI		 2410 int stream = substream->stream;
2411 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
1a8506d4 2412 int delay = 0;
1da177e4 2413
4cb36310
DH		 2414 switch (chip->position_fix[stream]) {
2415 case POS_FIX_LPIB:
2416 /* read LPIB */
2417 pos = azx_sd_readl(azx_dev, SD_LPIB);
2418 break;
2419 case POS_FIX_VIACOMBO:
0e153474 2420 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2421 break;
2422 default:
2423 /* use the position buffer */
2424 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2425 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2426 if (!pos || pos == (u32)-1) {
2427 printk(KERN_WARNING
2428 "hda-intel: Invalid position buffer, "
2429 "using LPIB read method instead.\n");
2430 chip->position_fix[stream] = POS_FIX_LPIB;
2431 pos = azx_sd_readl(azx_dev, SD_LPIB);
2432 } else
2433 chip->position_fix[stream] = POS_FIX_POSBUF;
2434 }
2435 break;
c74db86b 2436 }
4cb36310 2437
1da177e4
LT		 2438 if (pos >= azx_dev->bufsize)
2439 pos = 0;
90accc58
PLB		 2440
2441 /* calculate runtime delay from LPIB */
21229613 2442 if (substream->runtime &&
90accc58
PLB		 2443 chip->position_fix[stream] == POS_FIX_POSBUF &&
2444 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2445 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
90accc58
PLB		 2446 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2447 delay = pos - lpib_pos;
2448 else
2449 delay = lpib_pos - pos;
2450 if (delay < 0)
2451 delay += azx_dev->bufsize;
2452 if (delay >= azx_dev->period_bytes) {
1f04661f 2453 snd_printk(KERN_WARNING SFX
445a51b3 2454 "%s: Unstable LPIB (%d >= %d); "
1f04661f 2455 "disabling LPIB delay counting\n",
445a51b3 2456 pci_name(chip->pci), delay, azx_dev->period_bytes);
1f04661f
TI		 2457 delay = 0;
2458 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
90accc58 2459 }
21229613 2460 delay = bytes_to_frames(substream->runtime, delay);
90accc58 2461 }
21229613
TI		 2462
2463 if (substream->runtime) {
2464 if (hinfo->ops.get_delay)
2465 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2466 substream);
2467 substream->runtime->delay = delay;
2468 }
2469
1a8506d4 2470 trace_azx_get_position(chip, azx_dev, pos, delay);
9ad593f6
TI		 2471 return pos;
2472}
2473
2474static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2475{
2476 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2477 struct azx *chip = apcm->chip;
2478 struct azx_dev *azx_dev = get_azx_dev(substream);
2479 return bytes_to_frames(substream->runtime,
798cb7e8 2480 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2481}
2482
2483/*
2484 * Check whether the current DMA position is acceptable for updating
2485 * periods. Returns non-zero if it's OK.
2486 *
2487 * Many HD-audio controllers appear pretty inaccurate about
2488 * the update-IRQ timing. The IRQ is issued before actually the
2489 * data is processed. So, we need to process it afterwords in a
2490 * workqueue.
2491 */
2492static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2493{
e5463720 2494 u32 wallclk;
9ad593f6
TI		 2495 unsigned int pos;
2496
f48f606d
JK		 2497 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2498 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2499 return -1; /* bogus (too early) interrupt */
fa00e046 2500
798cb7e8 2501 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2502
d6d8bf54
TI		 2503 if (WARN_ONCE(!azx_dev->period_bytes,
2504 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2505 return -1; /* this shouldn't happen! */
edb39935 2506 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2507 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2508 /* NG - it's below the first next period boundary */
2509 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2510 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2511 return 1; /* OK, it's fine */
2512}
2513
2514/*
2515 * The work for pending PCM period updates.
2516 */
2517static void azx_irq_pending_work(struct work_struct *work)
2518{
2519 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2520 int i, pending, ok;
9ad593f6 2521
a6a950a8
TI		 2522 if (!chip->irq_pending_warned) {
2523 printk(KERN_WARNING
2524 "hda-intel: IRQ timing workaround is activated "
2525 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2526 chip->card->number);
2527 chip->irq_pending_warned = 1;
2528 }
2529
9ad593f6
TI		 2530 for (;;) {
2531 pending = 0;
2532 spin_lock_irq(&chip->reg_lock);
2533 for (i = 0; i < chip->num_streams; i++) {
2534 struct azx_dev *azx_dev = &chip->azx_dev[i];
2535 if (!azx_dev->irq_pending ||
2536 !azx_dev->substream ||
2537 !azx_dev->running)
2538 continue;
e5463720
JK		 2539 ok = azx_position_ok(chip, azx_dev);
2540 if (ok > 0) {
9ad593f6
TI		 2541 azx_dev->irq_pending = 0;
2542 spin_unlock(&chip->reg_lock);
2543 snd_pcm_period_elapsed(azx_dev->substream);
2544 spin_lock(&chip->reg_lock);
e5463720
JK		 2545 } else if (ok < 0) {
2546 pending = 0; /* too early */
9ad593f6
TI		 2547 } else
2548 pending++;
2549 }
2550 spin_unlock_irq(&chip->reg_lock);
2551 if (!pending)
2552 return;
08af495f 2553 msleep(1);
9ad593f6
TI		 2554 }
2555}
2556
2557/* clear irq_pending flags and assure no on-going workq */
2558static void azx_clear_irq_pending(struct azx *chip)
2559{
2560 int i;
2561
2562 spin_lock_irq(&chip->reg_lock);
2563 for (i = 0; i < chip->num_streams; i++)
2564 chip->azx_dev[i].irq_pending = 0;
2565 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2566}
2567
27fe48d9
TI		 2568#ifdef CONFIG_X86
2569static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2570 struct vm_area_struct *area)
2571{
2572 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2573 struct azx *chip = apcm->chip;
2574 if (!azx_snoop(chip))
2575 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2576 return snd_pcm_lib_default_mmap(substream, area);
2577}
2578#else
2579#define azx_pcm_mmap NULL
2580#endif
2581
a98f90fd 2582static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2583 .open = azx_pcm_open,
2584 .close = azx_pcm_close,
2585 .ioctl = snd_pcm_lib_ioctl,
2586 .hw_params = azx_pcm_hw_params,
2587 .hw_free = azx_pcm_hw_free,
2588 .prepare = azx_pcm_prepare,
2589 .trigger = azx_pcm_trigger,
2590 .pointer = azx_pcm_pointer,
5d890f59 2591 .wall_clock = azx_get_wallclock_tstamp,
27fe48d9 2592 .mmap = azx_pcm_mmap,
4ce107b9 2593 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2594};
2595
a98f90fd 2596static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2597{
176d5335
TI		 2598 struct azx_pcm *apcm = pcm->private_data;
2599 if (apcm) {
01b65bfb 2600 list_del(&apcm->list);
176d5335
TI		 2601 kfree(apcm);
2602 }
1da177e4
LT		 2603}
2604
acfa634f
TI		 2605#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2606
176d5335 2607static int
33fa35ed
TI		 2608azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2609 struct hda_pcm *cpcm)
1da177e4 2610{
33fa35ed 2611 struct azx *chip = bus->private_data;
a98f90fd 2612 struct snd_pcm *pcm;
1da177e4 2613 struct azx_pcm *apcm;
176d5335 2614 int pcm_dev = cpcm->device;
acfa634f 2615 unsigned int size;
176d5335 2616 int s, err;
1da177e4 2617
01b65bfb
TI		 2618 list_for_each_entry(apcm, &chip->pcm_list, list) {
2619 if (apcm->pcm->device == pcm_dev) {
445a51b3
DB		 2620 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2621 pci_name(chip->pci), pcm_dev);
01b65bfb
TI		 2622 return -EBUSY;
2623 }
176d5335
TI		 2624 }
2625 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2626 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2627 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2628 &pcm);
2629 if (err < 0)
2630 return err;
18cb7109 2631 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2632 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2633 if (apcm == NULL)
2634 return -ENOMEM;
2635 apcm->chip = chip;
01b65bfb 2636 apcm->pcm = pcm;
1da177e4 2637 apcm->codec = codec;
1da177e4
LT		 2638 pcm->private_data = apcm;
2639 pcm->private_free = azx_pcm_free;
176d5335
TI		 2640 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2641 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2642 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2643 cpcm->pcm = pcm;
2644 for (s = 0; s < 2; s++) {
2645 apcm->hinfo[s] = &cpcm->stream[s];
2646 if (cpcm->stream[s].substreams)
2647 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2648 }
2649 /* buffer pre-allocation */
acfa634f
TI		 2650 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2651 if (size > MAX_PREALLOC_SIZE)
2652 size = MAX_PREALLOC_SIZE;
4ce107b9 2653 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2654 snd_dma_pci_data(chip->pci),
acfa634f 2655 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2656 return 0;
2657}
2658
2659/*
2660 * mixer creation - all stuff is implemented in hda module
2661 */
e23e7a14 2662static int azx_mixer_create(struct azx *chip)
1da177e4
LT		 2663{
2664 return snd_hda_build_controls(chip->bus);
2665}
2666
2667
2668/*
2669 * initialize SD streams
2670 */
e23e7a14 2671static int azx_init_stream(struct azx *chip)
1da177e4
LT		 2672{
2673 int i;
2674
2675 /* initialize each stream (aka device)
d01ce99f
TI		 2676 * assign the starting bdl address to each stream (device)
2677 * and initialize
1da177e4 2678 */
07e4ca50 2679 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2680 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2681 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2682 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2683 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2684 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2685 azx_dev->sd_int_sta_mask = 1 << i;
2686 /* stream tag: must be non-zero and unique */
2687 azx_dev->index = i;
2688 azx_dev->stream_tag = i + 1;
2689 }
2690
2691 return 0;
2692}
2693
68e7fffc
TI		 2694static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2695{
437a5a46
TI		 2696 if (request_irq(chip->pci->irq, azx_interrupt,
2697 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2698 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2699 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2700 "disabling device\n", chip->pci->irq);
2701 if (do_disconnect)
2702 snd_card_disconnect(chip->card);
2703 return -1;
2704 }
2705 chip->irq = chip->pci->irq;
69e13418 2706 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2707 return 0;
2708}
2709
1da177e4 2710
cb53c626
TI		 2711static void azx_stop_chip(struct azx *chip)
2712{
95e99fda 2713 if (!chip->initialized)
cb53c626
TI		 2714 return;
2715
2716 /* disable interrupts */
2717 azx_int_disable(chip);
2718 azx_int_clear(chip);
2719
2720 /* disable CORB/RIRB */
2721 azx_free_cmd_io(chip);
2722
2723 /* disable position buffer */
2724 azx_writel(chip, DPLBASE, 0);
2725 azx_writel(chip, DPUBASE, 0);
2726
2727 chip->initialized = 0;
2728}
2729
1d1a4564
TI		 2730#ifdef CONFIG_SND_HDA_DSP_LOADER
2731/*
2732 * DSP loading code (e.g. for CA0132)
2733 */
2734
2735/* use the first stream for loading DSP */
2736static struct azx_dev *
2737azx_get_dsp_loader_dev(struct azx *chip)
2738{
2739 return &chip->azx_dev[chip->playback_index_offset];
2740}
2741
2742static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2743 unsigned int byte_size,
2744 struct snd_dma_buffer *bufp)
2745{
2746 u32 *bdl;
2747 struct azx *chip = bus->private_data;
2748 struct azx_dev *azx_dev;
2749 int err;
2750
eb49faa6
TI		 2751 azx_dev = azx_get_dsp_loader_dev(chip);
2752
2753 dsp_lock(azx_dev);
2754 spin_lock_irq(&chip->reg_lock);
2755 if (azx_dev->running || azx_dev->locked) {
2756 spin_unlock_irq(&chip->reg_lock);
2757 err = -EBUSY;
2758 goto unlock;
2759 }
2760 azx_dev->prepared = 0;
2761 chip->saved_azx_dev = *azx_dev;
2762 azx_dev->locked = 1;
2763 spin_unlock_irq(&chip->reg_lock);
1d1a4564
TI		 2764
2765 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2766 snd_dma_pci_data(chip->pci),
2767 byte_size, bufp);
2768 if (err < 0)
eb49faa6 2769 goto err_alloc;
1d1a4564 2770
b3667bd7 2771 mark_pages_wc(chip, bufp, true);
1d1a4564
TI		 2772 azx_dev->bufsize = byte_size;
2773 azx_dev->period_bytes = byte_size;
2774 azx_dev->format_val = format;
2775
2776 azx_stream_reset(chip, azx_dev);
2777
2778 /* reset BDL address */
2779 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2780 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2781
2782 azx_dev->frags = 0;
2783 bdl = (u32 *)azx_dev->bdl.area;
2784 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2785 if (err < 0)
2786 goto error;
2787
2788 azx_setup_controller(chip, azx_dev);
eb49faa6 2789 dsp_unlock(azx_dev);
1d1a4564
TI		 2790 return azx_dev->stream_tag;
2791
2792 error:
b3667bd7
TI		 2793 mark_pages_wc(chip, bufp, false);
2794 snd_dma_free_pages(bufp);
eb49faa6
TI		 2795 err_alloc:
2796 spin_lock_irq(&chip->reg_lock);
2797 if (azx_dev->opened)
2798 *azx_dev = chip->saved_azx_dev;
2799 azx_dev->locked = 0;
2800 spin_unlock_irq(&chip->reg_lock);
2801 unlock:
2802 dsp_unlock(azx_dev);
1d1a4564
TI		 2803 return err;
2804}
2805
2806static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2807{
2808 struct azx *chip = bus->private_data;
2809 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2810
2811 if (start)
2812 azx_stream_start(chip, azx_dev);
2813 else
2814 azx_stream_stop(chip, azx_dev);
2815 azx_dev->running = start;
2816}
2817
2818static void azx_load_dsp_cleanup(struct hda_bus *bus,
2819 struct snd_dma_buffer *dmab)
2820{
2821 struct azx *chip = bus->private_data;
2822 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2823
eb49faa6 2824 if (!dmab->area || !azx_dev->locked)
b3667bd7
TI		 2825 return;
2826
eb49faa6 2827 dsp_lock(azx_dev);
1d1a4564
TI		 2828 /* reset BDL address */
2829 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2830 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2831 azx_sd_writel(azx_dev, SD_CTL, 0);
2832 azx_dev->bufsize = 0;
2833 azx_dev->period_bytes = 0;
2834 azx_dev->format_val = 0;
2835
b3667bd7 2836 mark_pages_wc(chip, dmab, false);
1d1a4564 2837 snd_dma_free_pages(dmab);
b3667bd7 2838 dmab->area = NULL;
1d1a4564 2839
eb49faa6
TI		 2840 spin_lock_irq(&chip->reg_lock);
2841 if (azx_dev->opened)
2842 *azx_dev = chip->saved_azx_dev;
2843 azx_dev->locked = 0;
2844 spin_unlock_irq(&chip->reg_lock);
2845 dsp_unlock(azx_dev);
1d1a4564
TI		 2846}
2847#endif /* CONFIG_SND_HDA_DSP_LOADER */
2848
83012a7c 2849#ifdef CONFIG_PM
cb53c626 2850/* power-up/down the controller */
68467f51 2851static void azx_power_notify(struct hda_bus *bus, bool power_up)
cb53c626 2852{
33fa35ed 2853 struct azx *chip = bus->private_data;
cb53c626 2854
2ea3c6a2
TI		 2855 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2856 return;
2857
68467f51 2858 if (power_up)
b8dfc462
ML		 2859 pm_runtime_get_sync(&chip->pci->dev);
2860 else
2861 pm_runtime_put_sync(&chip->pci->dev);
cb53c626 2862}
65fcd41d
TI		 2863
2864static DEFINE_MUTEX(card_list_lock);
2865static LIST_HEAD(card_list);
2866
2867static void azx_add_card_list(struct azx *chip)
2868{
2869 mutex_lock(&card_list_lock);
2870 list_add(&chip->list, &card_list);
2871 mutex_unlock(&card_list_lock);
2872}
2873
2874static void azx_del_card_list(struct azx *chip)
2875{
2876 mutex_lock(&card_list_lock);
2877 list_del_init(&chip->list);
2878 mutex_unlock(&card_list_lock);
2879}
2880
2881/* trigger power-save check at writing parameter */
2882static int param_set_xint(const char *val, const struct kernel_param *kp)
2883{
2884 struct azx *chip;
2885 struct hda_codec *c;
2886 int prev = power_save;
2887 int ret = param_set_int(val, kp);
2888
2889 if (ret || prev == power_save)
2890 return ret;
2891
2892 mutex_lock(&card_list_lock);
2893 list_for_each_entry(chip, &card_list, list) {
2894 if (!chip->bus || chip->disabled)
2895 continue;
2896 list_for_each_entry(c, &chip->bus->codec_list, list)
2897 snd_hda_power_sync(c);
2898 }
2899 mutex_unlock(&card_list_lock);
2900 return 0;
2901}
2902#else
2903#define azx_add_card_list(chip) /* NOP */
2904#define azx_del_card_list(chip) /* NOP */
83012a7c 2905#endif /* CONFIG_PM */
5c0b9bec 2906
7ccbde57 2907#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 2908/*
2909 * power management
2910 */
68cb2b55 2911static int azx_suspend(struct device *dev)
1da177e4 2912{
68cb2b55
TI		 2913 struct pci_dev *pci = to_pci_dev(dev);
2914 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2915 struct azx *chip = card->private_data;
01b65bfb 2916 struct azx_pcm *p;
1da177e4 2917
c5c21523
TI		 2918 if (chip->disabled)
2919 return 0;
2920
421a1252 2921 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2922 azx_clear_irq_pending(chip);
01b65bfb
TI		 2923 list_for_each_entry(p, &chip->pcm_list, list)
2924 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2925 if (chip->initialized)
8dd78330 2926 snd_hda_suspend(chip->bus);
cb53c626 2927 azx_stop_chip(chip);
7295b264 2928 azx_enter_link_reset(chip);
30b35399 2929 if (chip->irq >= 0) {
43001c95 2930 free_irq(chip->irq, chip);
30b35399
TI		 2931 chip->irq = -1;
2932 }
68e7fffc 2933 if (chip->msi)
43001c95 2934 pci_disable_msi(chip->pci);
421a1252
TI		 2935 pci_disable_device(pci);
2936 pci_save_state(pci);
68cb2b55 2937 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 2938 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2939 hda_display_power(false);
1da177e4
LT		 2940 return 0;
2941}
2942
68cb2b55 2943static int azx_resume(struct device *dev)
1da177e4 2944{
68cb2b55
TI		 2945 struct pci_dev *pci = to_pci_dev(dev);
2946 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2947 struct azx *chip = card->private_data;
1da177e4 2948
c5c21523
TI		 2949 if (chip->disabled)
2950 return 0;
2951
99a2008d
WX		 2952 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2953 hda_display_power(true);
d14a7e0b
TI		 2954 pci_set_power_state(pci, PCI_D0);
2955 pci_restore_state(pci);
30b35399
TI		 2956 if (pci_enable_device(pci) < 0) {
2957 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2958 "disabling device\n");
2959 snd_card_disconnect(card);
2960 return -EIO;
2961 }
2962 pci_set_master(pci);
68e7fffc
TI		 2963 if (chip->msi)
2964 if (pci_enable_msi(pci) < 0)
2965 chip->msi = 0;
2966 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2967 return -EIO;
cb53c626 2968 azx_init_pci(chip);
d804ad92 2969
7f30830b 2970 azx_init_chip(chip, 1);
d804ad92 2971
1da177e4 2972 snd_hda_resume(chip->bus);
421a1252 2973 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2974 return 0;
2975}
b8dfc462
ML		 2976#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2977
2978#ifdef CONFIG_PM_RUNTIME
2979static int azx_runtime_suspend(struct device *dev)
2980{
2981 struct snd_card *card = dev_get_drvdata(dev);
2982 struct azx *chip = card->private_data;
2983
246efa4a
DA		 2984 if (chip->disabled)
2985 return 0;
2986
2987 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2988 return 0;
2989
7d4f606c
WX		 2990 /* enable controller wake up event */
2991 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
2992 STATESTS_INT_MASK);
2993
b8dfc462 2994 azx_stop_chip(chip);
95f74c41
TI		 2995 if (!chip->bus->avoid_link_reset)
2996 azx_enter_link_reset(chip);
b8dfc462 2997 azx_clear_irq_pending(chip);
99a2008d
WX		 2998 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2999 hda_display_power(false);
b8dfc462
ML		 3000 return 0;
3001}
3002
3003static int azx_runtime_resume(struct device *dev)
3004{
3005 struct snd_card *card = dev_get_drvdata(dev);
3006 struct azx *chip = card->private_data;
7d4f606c
WX		 3007 struct hda_bus *bus;
3008 struct hda_codec *codec;
3009 int status;
b8dfc462 3010
246efa4a
DA		 3011 if (chip->disabled)
3012 return 0;
3013
3014 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3015 return 0;
3016
99a2008d
WX		 3017 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3018 hda_display_power(true);
7d4f606c
WX		 3019
3020 /* Read STATESTS before controller reset */
3021 status = azx_readw(chip, STATESTS);
3022
b8dfc462
ML		 3023 azx_init_pci(chip);
3024 azx_init_chip(chip, 1);
7d4f606c
WX		 3025
3026 bus = chip->bus;
3027 if (status && bus) {
3028 list_for_each_entry(codec, &bus->codec_list, list)
3029 if (status & (1 << codec->addr))
3030 queue_delayed_work(codec->bus->workq,
3031 &codec->jackpoll_work, codec->jackpoll_interval);
3032 }
3033
3034 /* disable controller Wake Up event*/
3035 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
3036 ~STATESTS_INT_MASK);
3037
b8dfc462
ML		 3038 return 0;
3039}
6eb827d2
TI		 3040
3041static int azx_runtime_idle(struct device *dev)
3042{
3043 struct snd_card *card = dev_get_drvdata(dev);
3044 struct azx *chip = card->private_data;
3045
246efa4a
DA		 3046 if (chip->disabled)
3047 return 0;
3048
6eb827d2
TI		 3049 if (!power_save_controller ||
3050 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3051 return -EBUSY;
3052
3053 return 0;
3054}
3055
b8dfc462
ML		 3056#endif /* CONFIG_PM_RUNTIME */
3057
3058#ifdef CONFIG_PM
3059static const struct dev_pm_ops azx_pm = {
3060 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 3061 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 3062};
3063
68cb2b55
TI		 3064#define AZX_PM_OPS &azx_pm
3065#else
68cb2b55 3066#define AZX_PM_OPS NULL
b8dfc462 3067#endif /* CONFIG_PM */
1da177e4
LT		 3068
3069
0cbf0098
TI		 3070/*
3071 * reboot notifier for hang-up problem at power-down
3072 */
3073static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3074{
3075 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 3076 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 3077 azx_stop_chip(chip);
3078 return NOTIFY_OK;
3079}
3080
3081static void azx_notifier_register(struct azx *chip)
3082{
3083 chip->reboot_notifier.notifier_call = azx_halt;
3084 register_reboot_notifier(&chip->reboot_notifier);
3085}
3086
3087static void azx_notifier_unregister(struct azx *chip)
3088{
3089 if (chip->reboot_notifier.notifier_call)
3090 unregister_reboot_notifier(&chip->reboot_notifier);
3091}
3092
48c8b0eb 3093static int azx_probe_continue(struct azx *chip);
a82d51ed 3094
8393ec4a 3095#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 3096static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 3097
a82d51ed
TI		 3098static void azx_vs_set_state(struct pci_dev *pci,
3099 enum vga_switcheroo_state state)
3100{
3101 struct snd_card *card = pci_get_drvdata(pci);
3102 struct azx *chip = card->private_data;
3103 bool disabled;
3104
f4c482a4 3105 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 3106 if (chip->init_failed)
3107 return;
3108
3109 disabled = (state == VGA_SWITCHEROO_OFF);
3110 if (chip->disabled == disabled)
3111 return;
3112
3113 if (!chip->bus) {
3114 chip->disabled = disabled;
3115 if (!disabled) {
3116 snd_printk(KERN_INFO SFX
3117 "%s: Start delayed initialization\n",
3118 pci_name(chip->pci));
5c90680e 3119 if (azx_probe_continue(chip) < 0) {
a82d51ed
TI		 3120 snd_printk(KERN_ERR SFX
3121 "%s: initialization error\n",
3122 pci_name(chip->pci));
3123 chip->init_failed = true;
3124 }
3125 }
3126 } else {
3127 snd_printk(KERN_INFO SFX
445a51b3
DB		 3128 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3129 disabled ? "Disabling" : "Enabling");
a82d51ed 3130 if (disabled) {
246efa4a 3131 pm_runtime_put_sync_suspend(&pci->dev);
68cb2b55 3132 azx_suspend(&pci->dev);
246efa4a
DA		 3133 /* when we get suspended by vga switcheroo we end up in D3cold,
3134 * however we have no ACPI handle, so pci/acpi can't put us there,
3135 * put ourselves there */
3136 pci->current_state = PCI_D3cold;
a82d51ed 3137 chip->disabled = true;
128960a9 3138 if (snd_hda_lock_devices(chip->bus))
445a51b3
DB		 3139 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3140 pci_name(chip->pci));
a82d51ed
TI		 3141 } else {
3142 snd_hda_unlock_devices(chip->bus);
246efa4a 3143 pm_runtime_get_noresume(&pci->dev);
a82d51ed 3144 chip->disabled = false;
68cb2b55 3145 azx_resume(&pci->dev);
a82d51ed
TI		 3146 }
3147 }
3148}
3149
3150static bool azx_vs_can_switch(struct pci_dev *pci)
3151{
3152 struct snd_card *card = pci_get_drvdata(pci);
3153 struct azx *chip = card->private_data;
3154
f4c482a4 3155 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 3156 if (chip->init_failed)
3157 return false;
3158 if (chip->disabled || !chip->bus)
3159 return true;
3160 if (snd_hda_lock_devices(chip->bus))
3161 return false;
3162 snd_hda_unlock_devices(chip->bus);
3163 return true;
3164}
3165
e23e7a14 3166static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 3167{
3168 struct pci_dev *p = get_bound_vga(chip->pci);
3169 if (p) {
3170 snd_printk(KERN_INFO SFX
3171 "%s: Handle VGA-switcheroo audio client\n",
3172 pci_name(chip->pci));
3173 chip->use_vga_switcheroo = 1;
3174 pci_dev_put(p);
3175 }
3176}
3177
3178static const struct vga_switcheroo_client_ops azx_vs_ops = {
3179 .set_gpu_state = azx_vs_set_state,
3180 .can_switch = azx_vs_can_switch,
3181};
3182
e23e7a14 3183static int register_vga_switcheroo(struct azx *chip)
a82d51ed 3184{
128960a9
TI		 3185 int err;
3186
a82d51ed
TI		 3187 if (!chip->use_vga_switcheroo)
3188 return 0;
3189 /* FIXME: currently only handling DIS controller
3190 * is there any machine with two switchable HDMI audio controllers?
3191 */
128960a9 3192 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 3193 VGA_SWITCHEROO_DIS,
3194 chip->bus != NULL);
128960a9
TI		 3195 if (err < 0)
3196 return err;
3197 chip->vga_switcheroo_registered = 1;
246efa4a
DA		 3198
3199 /* register as an optimus hdmi audio power domain */
3200 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(&chip->pci->dev, &chip->hdmi_pm_domain);
128960a9 3201 return 0;
a82d51ed
TI		 3202}
3203#else
3204#define init_vga_switcheroo(chip) /* NOP */
3205#define register_vga_switcheroo(chip) 0
8393ec4a 3206#define check_hdmi_disabled(pci) false
a82d51ed
TI		 3207#endif /* SUPPORT_VGA_SWITCHER */
3208
1da177e4
LT		 3209/*
3210 * destructor
3211 */
a98f90fd 3212static int azx_free(struct azx *chip)
1da177e4 3213{
c67e2228 3214 struct pci_dev *pci = chip->pci;
4ce107b9
TI		 3215 int i;
3216
c67e2228
WX		 3217 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
3218 && chip->running)
3219 pm_runtime_get_noresume(&pci->dev);
3220
65fcd41d
TI		 3221 azx_del_card_list(chip);
3222
0cbf0098
TI		 3223 azx_notifier_unregister(chip);
3224
f4c482a4 3225 chip->init_failed = 1; /* to be sure */
44728e97 3226 complete_all(&chip->probe_wait);
f4c482a4 3227
a82d51ed
TI		 3228 if (use_vga_switcheroo(chip)) {
3229 if (chip->disabled && chip->bus)
3230 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 3231 if (chip->vga_switcheroo_registered)
3232 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 3233 }
3234
ce43fbae 3235 if (chip->initialized) {
9ad593f6 3236 azx_clear_irq_pending(chip);
07e4ca50 3237 for (i = 0; i < chip->num_streams; i++)
1da177e4 3238 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 3239 azx_stop_chip(chip);
1da177e4
LT		 3240 }
3241
f000fd80 3242 if (chip->irq >= 0)
1da177e4 3243 free_irq(chip->irq, (void*)chip);
68e7fffc 3244 if (chip->msi)
30b35399 3245 pci_disable_msi(chip->pci);
f079c25a
TI		 3246 if (chip->remap_addr)
3247 iounmap(chip->remap_addr);
1da177e4 3248
4ce107b9
TI		 3249 if (chip->azx_dev) {
3250 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 3251 if (chip->azx_dev[i].bdl.area) {
3252 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 3253 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 3254 }
4ce107b9 3255 }
27fe48d9
TI		 3256 if (chip->rb.area) {
3257 mark_pages_wc(chip, &chip->rb, false);
1da177e4 3258 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 3259 }
3260 if (chip->posbuf.area) {
3261 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 3262 snd_dma_free_pages(&chip->posbuf);
27fe48d9 3263 }
a82d51ed
TI		 3264 if (chip->region_requested)
3265 pci_release_regions(chip->pci);
1da177e4 3266 pci_disable_device(chip->pci);
07e4ca50 3267 kfree(chip->azx_dev);
4918cdab
TI		 3268#ifdef CONFIG_SND_HDA_PATCH_LOADER
3269 if (chip->fw)
3270 release_firmware(chip->fw);
3271#endif
99a2008d
WX		 3272 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3273 hda_display_power(false);
3274 hda_i915_exit();
3275 }
1da177e4
LT		 3276 kfree(chip);
3277
3278 return 0;
3279}
3280
a98f90fd 3281static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 3282{
3283 return azx_free(device->device_data);
3284}
3285
8393ec4a 3286#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 3287/*
3288 * Check of disabled HDMI controller by vga-switcheroo
3289 */
e23e7a14 3290static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 3291{
3292 struct pci_dev *p;
3293
3294 /* check only discrete GPU */
3295 switch (pci->vendor) {
3296 case PCI_VENDOR_ID_ATI:
3297 case PCI_VENDOR_ID_AMD:
3298 case PCI_VENDOR_ID_NVIDIA:
3299 if (pci->devfn == 1) {
3300 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3301 pci->bus->number, 0);
3302 if (p) {
3303 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3304 return p;
3305 pci_dev_put(p);
3306 }
3307 }
3308 break;
3309 }
3310 return NULL;
3311}
3312
e23e7a14 3313static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 3314{
3315 bool vga_inactive = false;
3316 struct pci_dev *p = get_bound_vga(pci);
3317
3318 if (p) {
12b78a7f 3319 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 3320 vga_inactive = true;
3321 pci_dev_put(p);
3322 }
3323 return vga_inactive;
3324}
8393ec4a 3325#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 3326
3372a153
TI		 3327/*
3328 * white/black-listing for position_fix
3329 */
e23e7a14 3330static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 3331 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3332 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 3333 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 3334 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 3335 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 3336 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 3337 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 3338 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 3339 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 3340 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 3341 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 3342 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 3343 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 3344 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 3345 {}
3346};
3347
e23e7a14 3348static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 3349{
3350 const struct snd_pci_quirk *q;
3351
c673ba1c 3352 switch (fix) {
1dac6695 3353 case POS_FIX_AUTO:
c673ba1c
TI		 3354 case POS_FIX_LPIB:
3355 case POS_FIX_POSBUF:
4cb36310 3356 case POS_FIX_VIACOMBO:
a6f2fd55 3357 case POS_FIX_COMBO:
c673ba1c
TI		 3358 return fix;
3359 }
3360
c673ba1c
TI		 3361 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3362 if (q) {
3363 printk(KERN_INFO
3364 "hda_intel: position_fix set to %d "
3365 "for device %04x:%04x\n",
3366 q->value, q->subvendor, q->subdevice);
3367 return q->value;
3372a153 3368 }
bdd9ef24
DH		 3369
3370 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 3371 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
445a51b3 3372 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
bdd9ef24 3373 return POS_FIX_VIACOMBO;
9477c58e
TI		 3374 }
3375 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
445a51b3 3376 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
50e3bbf9 3377 return POS_FIX_LPIB;
bdd9ef24 3378 }
c673ba1c 3379 return POS_FIX_AUTO;
3372a153
TI		 3380}
3381
669ba27a
TI		 3382/*
3383 * black-lists for probe_mask
3384 */
e23e7a14 3385static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 3386 /* Thinkpad often breaks the controller communication when accessing
3387 * to the non-working (or non-existing) modem codec slot.
3388 */
3389 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3390 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3391 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 3392 /* broken BIOS */
3393 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 3394 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3395 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 3396 /* forced codec slots */
93574844 3397 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 3398 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 3399 /* WinFast VP200 H (Teradici) user reported broken communication */
3400 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 3401 {}
3402};
3403
f1eaaeec
TI		 3404#define AZX_FORCE_CODEC_MASK 0x100
3405
e23e7a14 3406static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 3407{
3408 const struct snd_pci_quirk *q;
3409
f1eaaeec
TI		 3410 chip->codec_probe_mask = probe_mask[dev];
3411 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 3412 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3413 if (q) {
3414 printk(KERN_INFO
3415 "hda_intel: probe_mask set to 0x%x "
3416 "for device %04x:%04x\n",
3417 q->value, q->subvendor, q->subdevice);
f1eaaeec 3418 chip->codec_probe_mask = q->value;
669ba27a
TI		 3419 }
3420 }
f1eaaeec
TI		 3421
3422 /* check forced option */
3423 if (chip->codec_probe_mask != -1 &&
3424 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3425 chip->codec_mask = chip->codec_probe_mask & 0xff;
3426 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3427 chip->codec_mask);
3428 }
669ba27a
TI		 3429}
3430
4d8e22e0 3431/*
71623855 3432 * white/black-list for enable_msi
4d8e22e0 3433 */
e23e7a14 3434static struct snd_pci_quirk msi_black_list[] = {
9dc8398b 3435 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 3436 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 3437 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 3438 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 3439 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 3440 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 3441 {}
3442};
3443
e23e7a14 3444static void check_msi(struct azx *chip)
4d8e22e0
TI		 3445{
3446 const struct snd_pci_quirk *q;
3447
71623855
TI		 3448 if (enable_msi >= 0) {
3449 chip->msi = !!enable_msi;
4d8e22e0 3450 return;
71623855
TI		 3451 }
3452 chip->msi = 1; /* enable MSI as default */
3453 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 3454 if (q) {
3455 printk(KERN_INFO
3456 "hda_intel: msi for device %04x:%04x set to %d\n",
3457 q->subvendor, q->subdevice, q->value);
3458 chip->msi = q->value;
80c43ed7
TI		 3459 return;
3460 }
3461
3462 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 3463 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3464 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 3465 chip->msi = 0;
4d8e22e0
TI		 3466 }
3467}
3468
a1585d76 3469/* check the snoop mode availability */
e23e7a14 3470static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 3471{
3472 bool snoop = chip->snoop;
3473
3474 switch (chip->driver_type) {
3475 case AZX_DRIVER_VIA:
3476 /* force to non-snoop mode for a new VIA controller
3477 * when BIOS is set
3478 */
3479 if (snoop) {
3480 u8 val;
3481 pci_read_config_byte(chip->pci, 0x42, &val);
3482 if (!(val & 0x80) && chip->pci->revision == 0x30)
3483 snoop = false;
3484 }
3485 break;
3486 case AZX_DRIVER_ATIHDMI_NS:
3487 /* new ATI HDMI requires non-snoop */
3488 snoop = false;
3489 break;
c1279f87
TI		 3490 case AZX_DRIVER_CTHDA:
3491 snoop = false;
3492 break;
a1585d76
TI		 3493 }
3494
3495 if (snoop != chip->snoop) {
445a51b3
DB		 3496 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3497 pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
a1585d76
TI		 3498 chip->snoop = snoop;
3499 }
3500}
669ba27a 3501
99a2008d
WX		 3502#ifdef CONFIG_SND_HDA_I915
3503static void azx_probe_work(struct work_struct *work)
3504{
3505 azx_probe_continue(container_of(work, struct azx, probe_work));
3506}
3507#endif
3508
1da177e4
LT		 3509/*
3510 * constructor
3511 */
e23e7a14
BP		 3512static int azx_create(struct snd_card *card, struct pci_dev *pci,
3513 int dev, unsigned int driver_caps,
3514 struct azx **rchip)
1da177e4 3515{
a98f90fd 3516 static struct snd_device_ops ops = {
1da177e4
LT		 3517 .dev_free = azx_dev_free,
3518 };
a82d51ed
TI		 3519 struct azx *chip;
3520 int err;
1da177e4
LT		 3521
3522 *rchip = NULL;
bcd72003 3523
927fc866
PM		 3524 err = pci_enable_device(pci);
3525 if (err < 0)
1da177e4
LT		 3526 return err;
3527
e560d8d8 3528 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 3529 if (!chip) {
445a51b3 3530 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
1da177e4
LT		 3531 pci_disable_device(pci);
3532 return -ENOMEM;
3533 }
3534
3535 spin_lock_init(&chip->reg_lock);
62932df8 3536 mutex_init(&chip->open_mutex);
1da177e4
LT		 3537 chip->card = card;
3538 chip->pci = pci;
3539 chip->irq = -1;
9477c58e
TI		 3540 chip->driver_caps = driver_caps;
3541 chip->driver_type = driver_caps & 0xff;
4d8e22e0 3542 check_msi(chip);
555e219f 3543 chip->dev_index = dev;
9ad593f6 3544 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 3545 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 3546 INIT_LIST_HEAD(&chip->list);
a82d51ed 3547 init_vga_switcheroo(chip);
f4c482a4 3548 init_completion(&chip->probe_wait);
1da177e4 3549
beaffc39
SG		 3550 chip->position_fix[0] = chip->position_fix[1] =
3551 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 3552 /* combo mode uses LPIB for playback */
3553 if (chip->position_fix[0] == POS_FIX_COMBO) {
3554 chip->position_fix[0] = POS_FIX_LPIB;
3555 chip->position_fix[1] = POS_FIX_AUTO;
3556 }
3557
5aba4f8e 3558 check_probe_mask(chip, dev);
3372a153 3559
27346166 3560 chip->single_cmd = single_cmd;
27fe48d9 3561 chip->snoop = hda_snoop;
a1585d76 3562 azx_check_snoop_available(chip);
c74db86b 3563
5c0d7bc1
TI		 3564 if (bdl_pos_adj[dev] < 0) {
3565 switch (chip->driver_type) {
0c6341ac 3566 case AZX_DRIVER_ICH:
32679f95 3567 case AZX_DRIVER_PCH:
0c6341ac 3568 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 3569 break;
3570 default:
0c6341ac 3571 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 3572 break;
3573 }
3574 }
3575
a82d51ed
TI		 3576 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3577 if (err < 0) {
445a51b3
DB		 3578 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3579 pci_name(chip->pci));
a82d51ed
TI		 3580 azx_free(chip);
3581 return err;
3582 }
3583
99a2008d
WX		 3584#ifdef CONFIG_SND_HDA_I915
3585 /* continue probing in work context as may trigger request module */
3586 INIT_WORK(&chip->probe_work, azx_probe_work);
3587#endif
3588
a82d51ed 3589 *rchip = chip;
99a2008d 3590
a82d51ed
TI		 3591 return 0;
3592}
3593
48c8b0eb 3594static int azx_first_init(struct azx *chip)
a82d51ed
TI		 3595{
3596 int dev = chip->dev_index;
3597 struct pci_dev *pci = chip->pci;
3598 struct snd_card *card = chip->card;
3599 int i, err;
3600 unsigned short gcap;
3601
07e4ca50
TI		 3602#if BITS_PER_LONG != 64
3603 /* Fix up base address on ULI M5461 */
3604 if (chip->driver_type == AZX_DRIVER_ULI) {
3605 u16 tmp3;
3606 pci_read_config_word(pci, 0x40, &tmp3);
3607 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3608 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3609 }
3610#endif
3611
927fc866 3612 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 3613 if (err < 0)
1da177e4 3614 return err;
a82d51ed 3615 chip->region_requested = 1;
1da177e4 3616
927fc866 3617 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 3618 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 3619 if (chip->remap_addr == NULL) {
445a51b3 3620 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
a82d51ed 3621 return -ENXIO;
1da177e4
LT		 3622 }
3623
68e7fffc
TI		 3624 if (chip->msi)
3625 if (pci_enable_msi(pci) < 0)
3626 chip->msi = 0;
7376d013 3627
a82d51ed
TI		 3628 if (azx_acquire_irq(chip, 0) < 0)
3629 return -EBUSY;
1da177e4
LT		 3630
3631 pci_set_master(pci);
3632 synchronize_irq(chip->irq);
3633
bcd72003 3634 gcap = azx_readw(chip, GCAP);
445a51b3 3635 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
bcd72003 3636
dc4c2e6b 3637 /* disable SB600 64bit support for safety */
9477c58e 3638 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3639 struct pci_dev *p_smbus;
3640 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3641 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3642 NULL);
3643 if (p_smbus) {
3644 if (p_smbus->revision < 0x30)
3645 gcap &= ~ICH6_GCAP_64OK;
3646 pci_dev_put(p_smbus);
3647 }
3648 }
09240cf4 3649
9477c58e
TI		 3650 /* disable 64bit DMA address on some devices */
3651 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
445a51b3 3652 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
396087ea 3653 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3654 }
396087ea 3655
2ae66c26 3656 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3657 if (align_buffer_size >= 0)
3658 chip->align_buffer_size = !!align_buffer_size;
3659 else {
3660 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3661 chip->align_buffer_size = 0;
3662 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3663 chip->align_buffer_size = 1;
3664 else
3665 chip->align_buffer_size = 1;
3666 }
2ae66c26 3667
cf7aaca8 3668 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3669 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3670 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3671 else {
e930438c
YH		 3672 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3673 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3674 }
cf7aaca8 3675
8b6ed8e7
TI		 3676 /* read number of streams from GCAP register instead of using
3677 * hardcoded value
3678 */
3679 chip->capture_streams = (gcap >> 8) & 0x0f;
3680 chip->playback_streams = (gcap >> 12) & 0x0f;
3681 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3682 /* gcap didn't give any info, switching to old method */
3683
3684 switch (chip->driver_type) {
3685 case AZX_DRIVER_ULI:
3686 chip->playback_streams = ULI_NUM_PLAYBACK;
3687 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3688 break;
3689 case AZX_DRIVER_ATIHDMI:
1815b34a 3690 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3691 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3692 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3693 break;
c4da29ca 3694 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3695 default:
3696 chip->playback_streams = ICH6_NUM_PLAYBACK;
3697 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3698 break;
3699 }
07e4ca50 3700 }
8b6ed8e7
TI		 3701 chip->capture_index_offset = 0;
3702 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3703 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3704 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3705 GFP_KERNEL);
927fc866 3706 if (!chip->azx_dev) {
445a51b3 3707 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
a82d51ed 3708 return -ENOMEM;
07e4ca50
TI		 3709 }
3710
4ce107b9 3711 for (i = 0; i < chip->num_streams; i++) {
eb49faa6 3712 dsp_lock_init(&chip->azx_dev[i]);
4ce107b9
TI		 3713 /* allocate memory for the BDL for each stream */
3714 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3715 snd_dma_pci_data(chip->pci),
3716 BDL_SIZE, &chip->azx_dev[i].bdl);
3717 if (err < 0) {
445a51b3 3718 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
a82d51ed 3719 return -ENOMEM;
4ce107b9 3720 }
27fe48d9 3721 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3722 }
0be3b5d3 3723 /* allocate memory for the position buffer */
d01ce99f
TI		 3724 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3725 snd_dma_pci_data(chip->pci),
3726 chip->num_streams * 8, &chip->posbuf);
3727 if (err < 0) {
445a51b3 3728 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
a82d51ed 3729 return -ENOMEM;
1da177e4 3730 }
27fe48d9 3731 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3732 /* allocate CORB/RIRB */
81740861
TI		 3733 err = azx_alloc_cmd_io(chip);
3734 if (err < 0)
a82d51ed 3735 return err;
1da177e4
LT		 3736
3737 /* initialize streams */
3738 azx_init_stream(chip);
3739
3740 /* initialize chip */
cb53c626 3741 azx_init_pci(chip);
10e77dda 3742 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3743
3744 /* codec detection */
927fc866 3745 if (!chip->codec_mask) {
445a51b3 3746 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
a82d51ed 3747 return -ENODEV;
1da177e4
LT		 3748 }
3749
07e4ca50 3750 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3751 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3752 sizeof(card->shortname));
3753 snprintf(card->longname, sizeof(card->longname),
3754 "%s at 0x%lx irq %i",
3755 card->shortname, chip->addr, chip->irq);
07e4ca50 3756
1da177e4 3757 return 0;
1da177e4
LT		 3758}
3759
cb53c626
TI		 3760static void power_down_all_codecs(struct azx *chip)
3761{
83012a7c 3762#ifdef CONFIG_PM
cb53c626
TI		 3763 /* The codecs were powered up in snd_hda_codec_new().
3764 * Now all initialization done, so turn them down if possible
3765 */
3766 struct hda_codec *codec;
3767 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3768 snd_hda_power_down(codec);
3769 }
3770#endif
3771}
3772
97c6a3d1 3773#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 3774/* callback from request_firmware_nowait() */
3775static void azx_firmware_cb(const struct firmware *fw, void *context)
3776{
3777 struct snd_card *card = context;
3778 struct azx *chip = card->private_data;
3779 struct pci_dev *pci = chip->pci;
3780
3781 if (!fw) {
445a51b3
DB		 3782 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3783 pci_name(chip->pci));
5cb543db
TI		 3784 goto error;
3785 }
3786
3787 chip->fw = fw;
3788 if (!chip->disabled) {
3789 /* continue probing */
3790 if (azx_probe_continue(chip))
3791 goto error;
3792 }
3793 return; /* OK */
3794
3795 error:
3796 snd_card_free(card);
3797 pci_set_drvdata(pci, NULL);
3798}
97c6a3d1 3799#endif
5cb543db 3800
e23e7a14
BP		 3801static int azx_probe(struct pci_dev *pci,
3802 const struct pci_device_id *pci_id)
1da177e4 3803{
5aba4f8e 3804 static int dev;
a98f90fd
TI		 3805 struct snd_card *card;
3806 struct azx *chip;
5cb543db 3807 bool probe_now;
927fc866 3808 int err;
1da177e4 3809
5aba4f8e
TI		 3810 if (dev >= SNDRV_CARDS)
3811 return -ENODEV;
3812 if (!enable[dev]) {
3813 dev++;
3814 return -ENOENT;
3815 }
3816
e58de7ba
TI		 3817 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3818 if (err < 0) {
445a51b3 3819 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
e58de7ba 3820 return err;
1da177e4
LT		 3821 }
3822
4ea6fbc8
TI		 3823 snd_card_set_dev(card, &pci->dev);
3824
5aba4f8e 3825 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3826 if (err < 0)
3827 goto out_free;
421a1252 3828 card->private_data = chip;
f4c482a4
TI		 3829
3830 pci_set_drvdata(pci, card);
3831
3832 err = register_vga_switcheroo(chip);
3833 if (err < 0) {
3834 snd_printk(KERN_ERR SFX
445a51b3 3835 "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
f4c482a4
TI		 3836 goto out_free;
3837 }
3838
3839 if (check_hdmi_disabled(pci)) {
445a51b3 3840 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
f4c482a4 3841 pci_name(pci));
445a51b3 3842 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
f4c482a4
TI		 3843 chip->disabled = true;
3844 }
3845
5cb543db 3846 probe_now = !chip->disabled;
1da177e4 3847
4918cdab
TI		 3848#ifdef CONFIG_SND_HDA_PATCH_LOADER
3849 if (patch[dev] && *patch[dev]) {
445a51b3
DB		 3850 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3851 pci_name(pci), patch[dev]);
5cb543db
TI		 3852 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3853 &pci->dev, GFP_KERNEL, card,
3854 azx_firmware_cb);
4918cdab
TI		 3855 if (err < 0)
3856 goto out_free;
5cb543db 3857 probe_now = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 3858 }
3859#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3860
99a2008d
WX		 3861 /* continue probing in work context, avoid request_module deadlock */
3862 if (probe_now && (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)) {
3863#ifdef CONFIG_SND_HDA_I915
3864 probe_now = false;
3865 schedule_work(&chip->probe_work);
3866#else
3867 snd_printk(KERN_ERR SFX "Haswell must build in CONFIG_SND_HDA_I915\n");
3868#endif
3869 }
3870
5cb543db 3871 if (probe_now) {
a82d51ed
TI		 3872 err = azx_probe_continue(chip);
3873 if (err < 0)
3874 goto out_free;
3875 }
3876
a82d51ed 3877 dev++;
44728e97 3878 complete_all(&chip->probe_wait);
a82d51ed
TI		 3879 return 0;
3880
3881out_free:
3882 snd_card_free(card);
3883 return err;
3884}
3885
48c8b0eb 3886static int azx_probe_continue(struct azx *chip)
a82d51ed 3887{
c67e2228 3888 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 3889 int dev = chip->dev_index;
3890 int err;
3891
99a2008d
WX		 3892 /* Request power well for Haswell HDA controller and codec */
3893 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 3894#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 3895 err = hda_i915_init();
3896 if (err < 0) {
3897 snd_printk(KERN_ERR SFX "Error request power-well from i915\n");
3898 goto out_free;
3899 }
c841ad2a 3900#endif
99a2008d
WX		 3901 hda_display_power(true);
3902 }
3903
5c90680e
TI		 3904 err = azx_first_init(chip);
3905 if (err < 0)
3906 goto out_free;
3907
2dca0bba
JK		 3908#ifdef CONFIG_SND_HDA_INPUT_BEEP
3909 chip->beep_mode = beep_mode[dev];
3910#endif
3911
1da177e4 3912 /* create codec instances */
a1e21c90 3913 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3914 if (err < 0)
3915 goto out_free;
4ea6fbc8 3916#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 3917 if (chip->fw) {
3918 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3919 chip->fw->data);
4ea6fbc8
TI		 3920 if (err < 0)
3921 goto out_free;
e39ae856 3922#ifndef CONFIG_PM
4918cdab
TI		 3923 release_firmware(chip->fw); /* no longer needed */
3924 chip->fw = NULL;
e39ae856 3925#endif
4ea6fbc8
TI		 3926 }
3927#endif
10e77dda 3928 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3929 err = azx_codec_configure(chip);
3930 if (err < 0)
3931 goto out_free;
3932 }
1da177e4
LT		 3933
3934 /* create PCM streams */
176d5335 3935 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3936 if (err < 0)
3937 goto out_free;
1da177e4
LT		 3938
3939 /* create mixer controls */
d01ce99f 3940 err = azx_mixer_create(chip);
41dda0fd
WF		 3941 if (err < 0)
3942 goto out_free;
1da177e4 3943
a82d51ed 3944 err = snd_card_register(chip->card);
41dda0fd
WF		 3945 if (err < 0)
3946 goto out_free;
1da177e4 3947
cb53c626
TI		 3948 chip->running = 1;
3949 power_down_all_codecs(chip);
0cbf0098 3950 azx_notifier_register(chip);
65fcd41d 3951 azx_add_card_list(chip);
246efa4a 3952 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
c67e2228 3953 pm_runtime_put_noidle(&pci->dev);
1da177e4 3954
9121947d
TI		 3955 return 0;
3956
41dda0fd 3957out_free:
a82d51ed 3958 chip->init_failed = 1;
41dda0fd 3959 return err;
1da177e4
LT		 3960}
3961
e23e7a14 3962static void azx_remove(struct pci_dev *pci)
1da177e4 3963{
9121947d 3964 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 3965
9121947d
TI		 3966 if (card)
3967 snd_card_free(card);
1da177e4
LT		 3968}
3969
3970/* PCI IDs */
cebe41d4 3971static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3972 /* CPT */
9477c58e 3973 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 3974 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 3975 /* PBG */
9477c58e 3976 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 3977 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 3978 /* Panther Point */
9477c58e 3979 { PCI_DEVICE(0x8086, 0x1e20),
d7dab4db 3980 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 3981 /* Lynx Point */
3982 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 3983 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 3984 /* Wellsburg */
3985 { PCI_DEVICE(0x8086, 0x8d20),
3986 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3987 { PCI_DEVICE(0x8086, 0x8d21),
3988 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3989 /* Lynx Point-LP */
3990 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 3991 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3992 /* Lynx Point-LP */
3993 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 3994 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 3995 /* Wildcat Point-LP */
3996 { PCI_DEVICE(0x8086, 0x9ca0),
3997 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 3998 /* Haswell */
4a7c516b 3999 { PCI_DEVICE(0x8086, 0x0a0c),
33499a15 4000 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 4001 { PCI_DEVICE(0x8086, 0x0c0c),
33499a15 4002 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_HASWELL },
d279fae8 4003 { PCI_DEVICE(0x8086, 0x0d0c),
33499a15 4004 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_HASWELL },
99df18b3
PLB		 4005 /* 5 Series/3400 */
4006 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 4007 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 4008 /* Poulsbo */
9477c58e 4009 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 4010 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4011 /* Oaktrail */
09904b95 4012 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 4013 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 4014 /* BayTrail */
4015 { PCI_DEVICE(0x8086, 0x0f04),
4016 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
645e9035 4017 /* ICH */
8b0bd226 4018 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 4019 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4020 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 4021 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 4022 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4023 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 4024 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 4025 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4026 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 4027 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 4028 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4029 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 4030 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 4031 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4032 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 4033 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 4034 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4035 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 4036 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 4037 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4038 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 4039 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 4040 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4041 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 4042 /* Generic Intel */
4043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
4044 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4045 .class_mask = 0xffffff,
2ae66c26 4046 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 4047 /* ATI SB 450/600/700/800/900 */
4048 { PCI_DEVICE(0x1002, 0x437b),
4049 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4050 { PCI_DEVICE(0x1002, 0x4383),
4051 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4052 /* AMD Hudson */
4053 { PCI_DEVICE(0x1022, 0x780d),
4054 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 4055 /* ATI HDMI */
9477c58e
TI		 4056 { PCI_DEVICE(0x1002, 0x793b),
4057 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4058 { PCI_DEVICE(0x1002, 0x7919),
4059 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4060 { PCI_DEVICE(0x1002, 0x960f),
4061 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4062 { PCI_DEVICE(0x1002, 0x970f),
4063 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4064 { PCI_DEVICE(0x1002, 0xaa00),
4065 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4066 { PCI_DEVICE(0x1002, 0xaa08),
4067 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4068 { PCI_DEVICE(0x1002, 0xaa10),
4069 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4070 { PCI_DEVICE(0x1002, 0xaa18),
4071 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4072 { PCI_DEVICE(0x1002, 0xaa20),
4073 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4074 { PCI_DEVICE(0x1002, 0xaa28),
4075 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4076 { PCI_DEVICE(0x1002, 0xaa30),
4077 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4078 { PCI_DEVICE(0x1002, 0xaa38),
4079 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4080 { PCI_DEVICE(0x1002, 0xaa40),
4081 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4082 { PCI_DEVICE(0x1002, 0xaa48),
4083 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 4084 { PCI_DEVICE(0x1002, 0xaa50),
4085 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4086 { PCI_DEVICE(0x1002, 0xaa58),
4087 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4088 { PCI_DEVICE(0x1002, 0xaa60),
4089 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4090 { PCI_DEVICE(0x1002, 0xaa68),
4091 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4092 { PCI_DEVICE(0x1002, 0xaa80),
4093 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4094 { PCI_DEVICE(0x1002, 0xaa88),
4095 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4096 { PCI_DEVICE(0x1002, 0xaa90),
4097 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4098 { PCI_DEVICE(0x1002, 0xaa98),
4099 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 4100 { PCI_DEVICE(0x1002, 0x9902),
4101 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4102 { PCI_DEVICE(0x1002, 0xaaa0),
4103 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4104 { PCI_DEVICE(0x1002, 0xaaa8),
4105 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4106 { PCI_DEVICE(0x1002, 0xaab0),
4107 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 4108 /* VIA VT8251/VT8237A */
9477c58e
TI		 4109 { PCI_DEVICE(0x1106, 0x3288),
4110 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 4111 /* VIA GFX VT7122/VX900 */
4112 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
4113 /* VIA GFX VT6122/VX11 */
4114 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 4115 /* SIS966 */
4116 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
4117 /* ULI M5461 */
4118 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
4119 /* NVIDIA MCP */
0c2fd1bf
TI		 4120 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
4121 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4122 .class_mask = 0xffffff,
9477c58e 4123 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 4124 /* Teradici */
9477c58e
TI		 4125 { PCI_DEVICE(0x6549, 0x1200),
4126 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 4127 { PCI_DEVICE(0x6549, 0x2200),
4128 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 4129 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 4130 /* CTHDA chips */
4131 { PCI_DEVICE(0x1102, 0x0010),
4132 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4133 { PCI_DEVICE(0x1102, 0x0012),
4134 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
313f6e2d
TI		 4135#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
4136 /* the following entry conflicts with snd-ctxfi driver,
4137 * as ctxfi driver mutates from HD-audio to native mode with
4138 * a special command sequence.
4139 */
4e01f54b
TI		 4140 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4141 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4142 .class_mask = 0xffffff,
9477c58e 4143 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 4144 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 4145#else
4146 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 4147 { PCI_DEVICE(0x1102, 0x0009),
4148 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 4149 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 4150#endif
e35d4b11
OS		 4151 /* Vortex86MX */
4152 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 4153 /* VMware HDAudio */
4154 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 4155 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 4156 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4157 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4158 .class_mask = 0xffffff,
9477c58e 4159 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 4160 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4161 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4162 .class_mask = 0xffffff,
9477c58e 4163 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 4164 { 0, }
4165};
4166MODULE_DEVICE_TABLE(pci, azx_ids);
4167
4168/* pci_driver definition */
e9f66d9b 4169static struct pci_driver azx_driver = {
3733e424 4170 .name = KBUILD_MODNAME,
1da177e4
LT		 4171 .id_table = azx_ids,
4172 .probe = azx_probe,
e23e7a14 4173 .remove = azx_remove,
68cb2b55
TI		 4174 .driver = {
4175 .pm = AZX_PM_OPS,
4176 },
1da177e4
LT		 4177};
4178
e9f66d9b 4179module_pci_driver(azx_driver);
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