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ALSA: hda: Use ALC880_F1734 quirk for Fujitsu Siemens AMILO Xi 1526
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
362775e2 40#include <linux/kernel.h>
1da177e4 41#include <linux/module.h>
24982c5f 42#include <linux/dma-mapping.h>
1da177e4
LT		 43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
62932df8 47#include <linux/mutex.h>
0cbf0098 48#include <linux/reboot.h>
1da177e4
LT		 49#include <sound/core.h>
50#include <sound/initval.h>
51#include "hda_codec.h"
52
53
5aba4f8e
TI		 54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57static char *model[SNDRV_CARDS];
58static int position_fix[SNDRV_CARDS];
5c0d7bc1 59static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 60static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 61static int probe_only[SNDRV_CARDS];
27346166 62static int single_cmd;
71623855 63static int enable_msi = -1;
4ea6fbc8
TI		 64#ifdef CONFIG_SND_HDA_PATCH_LOADER
65static char *patch[SNDRV_CARDS];
66#endif
2dca0bba
JK		 67#ifdef CONFIG_SND_HDA_INPUT_BEEP
68static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
70#endif
1da177e4 71
5aba4f8e 72module_param_array(index, int, NULL, 0444);
1da177e4 73MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 74module_param_array(id, charp, NULL, 0444);
1da177e4 75MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 76module_param_array(enable, bool, NULL, 0444);
77MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78module_param_array(model, charp, NULL, 0444);
1da177e4 79MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 80module_param_array(position_fix, int, NULL, 0444);
d01ce99f 81MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
d2e1c973 82 "(0 = auto, 1 = none, 2 = POSBUF).");
555e219f
TI		 83module_param_array(bdl_pos_adj, int, NULL, 0644);
84MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 85module_param_array(probe_mask, int, NULL, 0444);
606ad75f 86MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
d4d9cd03
TI		 87module_param_array(probe_only, bool, NULL, 0444);
88MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 89module_param(single_cmd, bool, 0444);
d01ce99f
TI		 90MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
5aba4f8e 92module_param(enable_msi, int, 0444);
134a11f0 93MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 94#ifdef CONFIG_SND_HDA_PATCH_LOADER
95module_param_array(patch, charp, NULL, 0444);
96MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97#endif
2dca0bba
JK		 98#ifdef CONFIG_SND_HDA_INPUT_BEEP
99module_param_array(beep_mode, int, NULL, 0444);
100MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102#endif
606ad75f 103
dee1b66c 104#ifdef CONFIG_SND_HDA_POWER_SAVE
fee2fba3
TI		 105static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106module_param(power_save, int, 0644);
107MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
1da177e4 109
dee1b66c
TI		 110/* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
112 * wake up.
113 */
114static int power_save_controller = 1;
115module_param(power_save_controller, bool, 0644);
116MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117#endif
118
1da177e4
LT		 119MODULE_LICENSE("GPL");
120MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121 "{Intel, ICH6M},"
2f1b3818 122 "{Intel, ICH7},"
f5d40b30 123 "{Intel, ESB2},"
d2981393 124 "{Intel, ICH8},"
f9cc8a8b 125 "{Intel, ICH9},"
c34f5a04 126 "{Intel, ICH10},"
b29c2360 127 "{Intel, PCH},"
d2f2fcd2 128 "{Intel, CPT},"
4979bca9 129 "{Intel, SCH},"
fc20a562 130 "{ATI, SB450},"
89be83f8 131 "{ATI, SB600},"
778b6e1b 132 "{ATI, RS600},"
5b15c95f 133 "{ATI, RS690},"
e6db1119
WL		 134 "{ATI, RS780},"
135 "{ATI, R600},"
2797f724
HRK		 136 "{ATI, RV630},"
137 "{ATI, RV610},"
27da1834
WL		 138 "{ATI, RV670},"
139 "{ATI, RV635},"
140 "{ATI, RV620},"
141 "{ATI, RV770},"
fc20a562 142 "{VIA, VT8251},"
47672310 143 "{VIA, VT8237A},"
07e4ca50
TI		 144 "{SiS, SIS966},"
145 "{ULI, M5461}}");
1da177e4
LT		 146MODULE_DESCRIPTION("Intel HDA driver");
147
4abc1cc2
TI		 148#ifdef CONFIG_SND_VERBOSE_PRINTK
149#define SFX /* nop */
150#else
1da177e4 151#define SFX "hda-intel: "
4abc1cc2 152#endif
cb53c626 153
1da177e4
LT		 154/*
155 * registers
156 */
157#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 158#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
159#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
160#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
161#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
162#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 163#define ICH6_REG_VMIN 0x02
164#define ICH6_REG_VMAJ 0x03
165#define ICH6_REG_OUTPAY 0x04
166#define ICH6_REG_INPAY 0x06
167#define ICH6_REG_GCTL 0x08
8a933ece 168#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 169#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
170#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 171#define ICH6_REG_WAKEEN 0x0c
172#define ICH6_REG_STATESTS 0x0e
173#define ICH6_REG_GSTS 0x10
b21fadb9 174#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 175#define ICH6_REG_INTCTL 0x20
176#define ICH6_REG_INTSTS 0x24
177#define ICH6_REG_WALCLK 0x30
178#define ICH6_REG_SYNC 0x34
179#define ICH6_REG_CORBLBASE 0x40
180#define ICH6_REG_CORBUBASE 0x44
181#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 182#define ICH6_REG_CORBRP 0x4a
183#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 184#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 185#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
186#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 187#define ICH6_REG_CORBSTS 0x4d
b21fadb9 188#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 189#define ICH6_REG_CORBSIZE 0x4e
190
191#define ICH6_REG_RIRBLBASE 0x50
192#define ICH6_REG_RIRBUBASE 0x54
193#define ICH6_REG_RIRBWP 0x58
b21fadb9 194#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 195#define ICH6_REG_RINTCNT 0x5a
196#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 197#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
198#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
199#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 200#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 201#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
202#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 203#define ICH6_REG_RIRBSIZE 0x5e
204
205#define ICH6_REG_IC 0x60
206#define ICH6_REG_IR 0x64
207#define ICH6_REG_IRS 0x68
208#define ICH6_IRS_VALID (1<<1)
209#define ICH6_IRS_BUSY (1<<0)
210
211#define ICH6_REG_DPLBASE 0x70
212#define ICH6_REG_DPUBASE 0x74
213#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
214
215/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
216enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
217
218/* stream register offsets from stream base */
219#define ICH6_REG_SD_CTL 0x00
220#define ICH6_REG_SD_STS 0x03
221#define ICH6_REG_SD_LPIB 0x04
222#define ICH6_REG_SD_CBL 0x08
223#define ICH6_REG_SD_LVI 0x0c
224#define ICH6_REG_SD_FIFOW 0x0e
225#define ICH6_REG_SD_FIFOSIZE 0x10
226#define ICH6_REG_SD_FORMAT 0x12
227#define ICH6_REG_SD_BDLPL 0x18
228#define ICH6_REG_SD_BDLPU 0x1c
229
230/* PCI space */
231#define ICH6_PCIREG_TCSEL 0x44
232
233/*
234 * other constants
235 */
236
237/* max number of SDs */
07e4ca50 238/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 239#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 240#define ICH6_NUM_PLAYBACK 4
241
242/* ULI has 6 playback and 5 capture */
07e4ca50 243#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 244#define ULI_NUM_PLAYBACK 6
245
778b6e1b 246/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 247#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 248#define ATIHDMI_NUM_PLAYBACK 1
249
f269002e
KY		 250/* TERA has 4 playback and 3 capture */
251#define TERA_NUM_CAPTURE 3
252#define TERA_NUM_PLAYBACK 4
253
07e4ca50
TI		 254/* this number is statically defined for simplicity */
255#define MAX_AZX_DEV 16
256
1da177e4 257/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 258#define BDL_SIZE 4096
259#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
260#define AZX_MAX_FRAG 32
1da177e4
LT		 261/* max buffer size - no h/w limit, you can increase as you like */
262#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 263
264/* RIRB int mask: overrun[2], response[0] */
265#define RIRB_INT_RESPONSE 0x01
266#define RIRB_INT_OVERRUN 0x04
267#define RIRB_INT_MASK 0x05
268
2f5983f2 269/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 270#define AZX_MAX_CODECS 8
271#define AZX_DEFAULT_CODECS 4
deadff16 272#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 273
274/* SD_CTL bits */
275#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
276#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 277#define SD_CTL_STRIPE (3 << 16) /* stripe control */
278#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
279#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 280#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
281#define SD_CTL_STREAM_TAG_SHIFT 20
282
283/* SD_CTL and SD_STS */
284#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
285#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
286#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 287#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
288 SD_INT_COMPLETE)
1da177e4
LT		 289
290/* SD_STS */
291#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
292
293/* INTCTL and INTSTS */
d01ce99f
TI		 294#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
295#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
296#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 297
1da177e4
LT		 298/* below are so far hardcoded - should read registers in future */
299#define ICH6_MAX_CORB_ENTRIES 256
300#define ICH6_MAX_RIRB_ENTRIES 256
301
c74db86b
TI		 302/* position fix mode */
303enum {
0be3b5d3 304 POS_FIX_AUTO,
d2e1c973 305 POS_FIX_LPIB,
0be3b5d3 306 POS_FIX_POSBUF,
c74db86b 307};
1da177e4 308
f5d40b30 309/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 310#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
311#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
312
da3fca21
V		 313/* Defines for Nvidia HDA support */
314#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
315#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 316#define NVIDIA_HDA_ISTRM_COH 0x4d
317#define NVIDIA_HDA_OSTRM_COH 0x4c
318#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 319
90a5ad52
TI		 320/* Defines for Intel SCH HDA snoop control */
321#define INTEL_SCH_HDA_DEVC 0x78
322#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
323
0e153474
JC		 324/* Define IN stream 0 FIFO size offset in VIA controller */
325#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
326/* Define VIA HD Audio Device ID*/
327#define VIA_HDAC_DEVICE_ID 0x3288
328
c4da29ca
YL		 329/* HD Audio class code */
330#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 331
1da177e4
LT		 332/*
333 */
334
a98f90fd 335struct azx_dev {
4ce107b9 336 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 337 u32 *posbuf; /* position buffer pointer */
1da177e4 338
d01ce99f 339 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 340 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 341 unsigned int frags; /* number for period in the play buffer */
342 unsigned int fifo_size; /* FIFO size */
fa00e046
JK		 343 unsigned long start_jiffies; /* start + minimum jiffies */
344 unsigned long min_jiffies; /* minimum jiffies before position is valid */
1da177e4 345
d01ce99f 346 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 347
d01ce99f 348 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 349
350 /* pcm support */
d01ce99f
TI		 351 struct snd_pcm_substream *substream; /* assigned substream,
352 * set in PCM open
353 */
354 unsigned int format_val; /* format value to be set in the
355 * controller and the codec
356 */
1da177e4
LT		 357 unsigned char stream_tag; /* assigned stream */
358 unsigned char index; /* stream index */
ef18bede 359 int device; /* last device number assigned to */
1da177e4 360
927fc866
PM		 361 unsigned int opened :1;
362 unsigned int running :1;
675f25d4 363 unsigned int irq_pending :1;
d523b0c8 364 unsigned int start_flag: 1; /* stream full start flag */
0e153474
JC		 365 /*
366 * For VIA:
367 * A flag to ensure DMA position is 0
368 * when link position is not greater than FIFO size
369 */
370 unsigned int insufficient :1;
1da177e4
LT		 371};
372
373/* CORB/RIRB */
a98f90fd 374struct azx_rb {
1da177e4
LT		 375 u32 *buf; /* CORB/RIRB buffer
376 * Each CORB entry is 4byte, RIRB is 8byte
377 */
378 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
379 /* for RIRB */
380 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 381 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
382 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 383};
384
a98f90fd
TI		 385struct azx {
386 struct snd_card *card;
1da177e4 387 struct pci_dev *pci;
555e219f 388 int dev_index;
1da177e4 389
07e4ca50
TI		 390 /* chip type specific */
391 int driver_type;
392 int playback_streams;
393 int playback_index_offset;
394 int capture_streams;
395 int capture_index_offset;
396 int num_streams;
397
1da177e4
LT		 398 /* pci resources */
399 unsigned long addr;
400 void __iomem *remap_addr;
401 int irq;
402
403 /* locks */
404 spinlock_t reg_lock;
62932df8 405 struct mutex open_mutex;
1da177e4 406
07e4ca50 407 /* streams (x num_streams) */
a98f90fd 408 struct azx_dev *azx_dev;
1da177e4
LT		 409
410 /* PCM */
c8936222 411 struct snd_pcm *pcm[HDA_MAX_PCMS];
1da177e4
LT		 412
413 /* HD codec */
414 unsigned short codec_mask;
f1eaaeec 415 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 416 struct hda_bus *bus;
2dca0bba 417 unsigned int beep_mode;
1da177e4
LT		 418
419 /* CORB/RIRB */
a98f90fd
TI		 420 struct azx_rb corb;
421 struct azx_rb rirb;
1da177e4 422
4ce107b9 423 /* CORB/RIRB and position buffers */
1da177e4
LT		 424 struct snd_dma_buffer rb;
425 struct snd_dma_buffer posbuf;
c74db86b
TI		 426
427 /* flags */
428 int position_fix;
1eb6dc7d 429 int poll_count;
cb53c626 430 unsigned int running :1;
927fc866
PM		 431 unsigned int initialized :1;
432 unsigned int single_cmd :1;
433 unsigned int polling_mode :1;
68e7fffc 434 unsigned int msi :1;
a6a950a8 435 unsigned int irq_pending_warned :1;
0e153474 436 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
6ce4a3bc 437 unsigned int probing :1; /* codec probing phase */
43bbb6cc
TI		 438
439 /* for debugging */
feb27340 440 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 441
442 /* for pending irqs */
443 struct work_struct irq_pending_work;
0cbf0098
TI		 444
445 /* reboot notifier (for mysterious hangup problem at power-down) */
446 struct notifier_block reboot_notifier;
1da177e4
LT		 447};
448
07e4ca50
TI		 449/* driver types */
450enum {
451 AZX_DRIVER_ICH,
32679f95 452 AZX_DRIVER_PCH,
4979bca9 453 AZX_DRIVER_SCH,
07e4ca50 454 AZX_DRIVER_ATI,
778b6e1b 455 AZX_DRIVER_ATIHDMI,
07e4ca50
TI		 456 AZX_DRIVER_VIA,
457 AZX_DRIVER_SIS,
458 AZX_DRIVER_ULI,
da3fca21 459 AZX_DRIVER_NVIDIA,
f269002e 460 AZX_DRIVER_TERA,
c4da29ca 461 AZX_DRIVER_GENERIC,
2f5983f2 462 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 463};
464
465static char *driver_short_names[] __devinitdata = {
466 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 467 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 468 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 469 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 470 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI		 471 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
472 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 473 [AZX_DRIVER_ULI] = "HDA ULI M5461",
474 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 475 [AZX_DRIVER_TERA] = "HDA Teradici",
c4da29ca 476 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 477};
478
1da177e4
LT		 479/*
480 * macros for easy use
481 */
482#define azx_writel(chip,reg,value) \
483 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
484#define azx_readl(chip,reg) \
485 readl((chip)->remap_addr + ICH6_REG_##reg)
486#define azx_writew(chip,reg,value) \
487 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
488#define azx_readw(chip,reg) \
489 readw((chip)->remap_addr + ICH6_REG_##reg)
490#define azx_writeb(chip,reg,value) \
491 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
492#define azx_readb(chip,reg) \
493 readb((chip)->remap_addr + ICH6_REG_##reg)
494
495#define azx_sd_writel(dev,reg,value) \
496 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
497#define azx_sd_readl(dev,reg) \
498 readl((dev)->sd_addr + ICH6_REG_##reg)
499#define azx_sd_writew(dev,reg,value) \
500 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
501#define azx_sd_readw(dev,reg) \
502 readw((dev)->sd_addr + ICH6_REG_##reg)
503#define azx_sd_writeb(dev,reg,value) \
504 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
505#define azx_sd_readb(dev,reg) \
506 readb((dev)->sd_addr + ICH6_REG_##reg)
507
508/* for pcm support */
a98f90fd 509#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 510
68e7fffc 511static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 512static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 513/*
514 * Interface for HD codec
515 */
516
1da177e4
LT		 517/*
518 * CORB / RIRB interface
519 */
a98f90fd 520static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 521{
522 int err;
523
524 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 525 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
526 snd_dma_pci_data(chip->pci),
1da177e4
LT		 527 PAGE_SIZE, &chip->rb);
528 if (err < 0) {
529 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
530 return err;
531 }
532 return 0;
533}
534
a98f90fd 535static void azx_init_cmd_io(struct azx *chip)
1da177e4 536{
cdb1fbf2 537 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 538 /* CORB set up */
539 chip->corb.addr = chip->rb.addr;
540 chip->corb.buf = (u32 *)chip->rb.area;
541 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 542 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 543
07e4ca50
TI		 544 /* set the corb size to 256 entries (ULI requires explicitly) */
545 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 546 /* set the corb write pointer to 0 */
547 azx_writew(chip, CORBWP, 0);
548 /* reset the corb hw read pointer */
b21fadb9 549 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 550 /* enable corb dma */
b21fadb9 551 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 552
553 /* RIRB set up */
554 chip->rirb.addr = chip->rb.addr + 2048;
555 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 556 chip->rirb.wp = chip->rirb.rp = 0;
557 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 558 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 559 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 560
07e4ca50
TI		 561 /* set the rirb size to 256 entries (ULI requires explicitly) */
562 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 563 /* reset the rirb hw write pointer */
b21fadb9 564 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4
LT		 565 /* set N=1, get RIRB response interrupt for new entry */
566 azx_writew(chip, RINTCNT, 1);
567 /* enable rirb dma and response irq */
1da177e4 568 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 569 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 570}
571
a98f90fd 572static void azx_free_cmd_io(struct azx *chip)
1da177e4 573{
cdb1fbf2 574 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 575 /* disable ringbuffer DMAs */
576 azx_writeb(chip, RIRBCTL, 0);
577 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 578 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 579}
580
deadff16
WF		 581static unsigned int azx_command_addr(u32 cmd)
582{
583 unsigned int addr = cmd >> 28;
584
585 if (addr >= AZX_MAX_CODECS) {
586 snd_BUG();
587 addr = 0;
588 }
589
590 return addr;
591}
592
593static unsigned int azx_response_addr(u32 res)
594{
595 unsigned int addr = res & 0xf;
596
597 if (addr >= AZX_MAX_CODECS) {
598 snd_BUG();
599 addr = 0;
600 }
601
602 return addr;
1da177e4
LT		 603}
604
605/* send a command */
33fa35ed 606static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 607{
33fa35ed 608 struct azx *chip = bus->private_data;
deadff16 609 unsigned int addr = azx_command_addr(val);
1da177e4 610 unsigned int wp;
1da177e4 611
c32649fe
WF		 612 spin_lock_irq(&chip->reg_lock);
613
1da177e4
LT		 614 /* add command to corb */
615 wp = azx_readb(chip, CORBWP);
616 wp++;
617 wp %= ICH6_MAX_CORB_ENTRIES;
618
deadff16 619 chip->rirb.cmds[addr]++;
1da177e4
LT		 620 chip->corb.buf[wp] = cpu_to_le32(val);
621 azx_writel(chip, CORBWP, wp);
c32649fe 622
1da177e4
LT		 623 spin_unlock_irq(&chip->reg_lock);
624
625 return 0;
626}
627
628#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
629
630/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 631static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 632{
633 unsigned int rp, wp;
deadff16 634 unsigned int addr;
1da177e4
LT		 635 u32 res, res_ex;
636
637 wp = azx_readb(chip, RIRBWP);
638 if (wp == chip->rirb.wp)
639 return;
640 chip->rirb.wp = wp;
deadff16 641
1da177e4
LT		 642 while (chip->rirb.rp != wp) {
643 chip->rirb.rp++;
644 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
645
646 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
647 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
648 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 649 addr = azx_response_addr(res_ex);
1da177e4
LT		 650 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
651 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 652 else if (chip->rirb.cmds[addr]) {
653 chip->rirb.res[addr] = res;
2add9b92 654 smp_wmb();
deadff16 655 chip->rirb.cmds[addr]--;
e310bb06
WF		 656 } else
657 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
658 "last cmd=%#08x\n",
659 res, res_ex,
660 chip->last_cmd[addr]);
1da177e4
LT		 661 }
662}
663
664/* receive a response */
deadff16
WF		 665static unsigned int azx_rirb_get_response(struct hda_bus *bus,
666 unsigned int addr)
1da177e4 667{
33fa35ed 668 struct azx *chip = bus->private_data;
5c79b1f8 669 unsigned long timeout;
1eb6dc7d 670 int do_poll = 0;
1da177e4 671
5c79b1f8
TI		 672 again:
673 timeout = jiffies + msecs_to_jiffies(1000);
28a0d9df 674 for (;;) {
1eb6dc7d 675 if (chip->polling_mode || do_poll) {
e96224ae
TI		 676 spin_lock_irq(&chip->reg_lock);
677 azx_update_rirb(chip);
678 spin_unlock_irq(&chip->reg_lock);
679 }
deadff16 680 if (!chip->rirb.cmds[addr]) {
2add9b92 681 smp_rmb();
b613291f 682 bus->rirb_error = 0;
1eb6dc7d
ML		 683
684 if (!do_poll)
685 chip->poll_count = 0;
deadff16 686 return chip->rirb.res[addr]; /* the last value */
2add9b92 687 }
28a0d9df
TI		 688 if (time_after(jiffies, timeout))
689 break;
33fa35ed 690 if (bus->needs_damn_long_delay)
52987656
TI		 691 msleep(2); /* temporary workaround */
692 else {
693 udelay(10);
694 cond_resched();
695 }
28a0d9df 696 }
5c79b1f8 697
1eb6dc7d
ML		 698 if (!chip->polling_mode && chip->poll_count < 2) {
699 snd_printdd(SFX "azx_get_response timeout, "
700 "polling the codec once: last cmd=0x%08x\n",
701 chip->last_cmd[addr]);
702 do_poll = 1;
703 chip->poll_count++;
704 goto again;
705 }
706
707
23c4a881
TI		 708 if (!chip->polling_mode) {
709 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
710 "switching to polling mode: last cmd=0x%08x\n",
711 chip->last_cmd[addr]);
712 chip->polling_mode = 1;
713 goto again;
714 }
715
68e7fffc 716 if (chip->msi) {
4abc1cc2 717 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 718 "disabling MSI: last cmd=0x%08x\n",
719 chip->last_cmd[addr]);
68e7fffc
TI		 720 free_irq(chip->irq, chip);
721 chip->irq = -1;
722 pci_disable_msi(chip->pci);
723 chip->msi = 0;
b613291f
TI		 724 if (azx_acquire_irq(chip, 1) < 0) {
725 bus->rirb_error = 1;
68e7fffc 726 return -1;
b613291f 727 }
68e7fffc
TI		 728 goto again;
729 }
730
6ce4a3bc
TI		 731 if (chip->probing) {
732 /* If this critical timeout happens during the codec probing
733 * phase, this is likely an access to a non-existing codec
734 * slot. Better to return an error and reset the system.
735 */
736 return -1;
737 }
738
8dd78330
TI		 739 /* a fatal communication error; need either to reset or to fallback
740 * to the single_cmd mode
741 */
b613291f 742 bus->rirb_error = 1;
b20f3b83 743 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 744 bus->response_reset = 1;
745 return -1; /* give a chance to retry */
746 }
747
748 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
749 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 750 chip->last_cmd[addr]);
8dd78330
TI		 751 chip->single_cmd = 1;
752 bus->response_reset = 0;
1a696978 753 /* release CORB/RIRB */
4fcd3920 754 azx_free_cmd_io(chip);
1a696978
TI		 755 /* disable unsolicited responses */
756 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 757 return -1;
1da177e4
LT		 758}
759
1da177e4
LT		 760/*
761 * Use the single immediate command instead of CORB/RIRB for simplicity
762 *
763 * Note: according to Intel, this is not preferred use. The command was
764 * intended for the BIOS only, and may get confused with unsolicited
765 * responses. So, we shouldn't use it for normal operation from the
766 * driver.
767 * I left the codes, however, for debugging/testing purposes.
768 */
769
b05a7d4f 770/* receive a response */
deadff16 771static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 772{
773 int timeout = 50;
774
775 while (timeout--) {
776 /* check IRV busy bit */
777 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
778 /* reuse rirb.res as the response return value */
deadff16 779 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 780 return 0;
781 }
782 udelay(1);
783 }
784 if (printk_ratelimit())
785 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
786 azx_readw(chip, IRS));
deadff16 787 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 788 return -EIO;
789}
790
1da177e4 791/* send a command */
33fa35ed 792static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 793{
33fa35ed 794 struct azx *chip = bus->private_data;
deadff16 795 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 796 int timeout = 50;
797
8dd78330 798 bus->rirb_error = 0;
1da177e4
LT		 799 while (timeout--) {
800 /* check ICB busy bit */
d01ce99f 801 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 802 /* Clear IRV valid bit */
d01ce99f
TI		 803 azx_writew(chip, IRS, azx_readw(chip, IRS) |
804 ICH6_IRS_VALID);
1da177e4 805 azx_writel(chip, IC, val);
d01ce99f
TI		 806 azx_writew(chip, IRS, azx_readw(chip, IRS) |
807 ICH6_IRS_BUSY);
deadff16 808 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 809 }
810 udelay(1);
811 }
1cfd52bc
MB		 812 if (printk_ratelimit())
813 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
814 azx_readw(chip, IRS), val);
1da177e4
LT		 815 return -EIO;
816}
817
818/* receive a response */
deadff16
WF		 819static unsigned int azx_single_get_response(struct hda_bus *bus,
820 unsigned int addr)
1da177e4 821{
33fa35ed 822 struct azx *chip = bus->private_data;
deadff16 823 return chip->rirb.res[addr];
1da177e4
LT		 824}
825
111d3af5
TI		 826/*
827 * The below are the main callbacks from hda_codec.
828 *
829 * They are just the skeleton to call sub-callbacks according to the
830 * current setting of chip->single_cmd.
831 */
832
833/* send a command */
33fa35ed 834static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 835{
33fa35ed 836 struct azx *chip = bus->private_data;
43bbb6cc 837
feb27340 838 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 839 if (chip->single_cmd)
33fa35ed 840 return azx_single_send_cmd(bus, val);
111d3af5 841 else
33fa35ed 842 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 843}
844
845/* get a response */
deadff16
WF		 846static unsigned int azx_get_response(struct hda_bus *bus,
847 unsigned int addr)
111d3af5 848{
33fa35ed 849 struct azx *chip = bus->private_data;
111d3af5 850 if (chip->single_cmd)
deadff16 851 return azx_single_get_response(bus, addr);
111d3af5 852 else
deadff16 853 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 854}
855
cb53c626 856#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 857static void azx_power_notify(struct hda_bus *bus);
cb53c626 858#endif
111d3af5 859
1da177e4 860/* reset codec link */
a98f90fd 861static int azx_reset(struct azx *chip)
1da177e4
LT		 862{
863 int count;
864
e8a7f136
DT		 865 /* clear STATESTS */
866 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
867
1da177e4
LT		 868 /* reset controller */
869 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
870
871 count = 50;
872 while (azx_readb(chip, GCTL) && --count)
873 msleep(1);
874
875 /* delay for >= 100us for codec PLL to settle per spec
876 * Rev 0.9 section 5.5.1
877 */
878 msleep(1);
879
880 /* Bring controller out of reset */
881 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
882
883 count = 50;
927fc866 884 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 885 msleep(1);
886
927fc866 887 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 888 msleep(1);
889
890 /* check to see if controller is ready */
927fc866 891 if (!azx_readb(chip, GCTL)) {
4abc1cc2 892 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 893 return -EBUSY;
894 }
895
41e2fce4 896 /* Accept unsolicited responses */
1a696978
TI		 897 if (!chip->single_cmd)
898 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
899 ICH6_GCTL_UNSOL);
41e2fce4 900
1da177e4 901 /* detect codecs */
927fc866 902 if (!chip->codec_mask) {
1da177e4 903 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 904 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 905 }
906
907 return 0;
908}
909
910
911/*
912 * Lowlevel interface
913 */
914
915/* enable interrupts */
a98f90fd 916static void azx_int_enable(struct azx *chip)
1da177e4
LT		 917{
918 /* enable controller CIE and GIE */
919 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
920 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
921}
922
923/* disable interrupts */
a98f90fd 924static void azx_int_disable(struct azx *chip)
1da177e4
LT		 925{
926 int i;
927
928 /* disable interrupts in stream descriptor */
07e4ca50 929 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 930 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 931 azx_sd_writeb(azx_dev, SD_CTL,
932 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
933 }
934
935 /* disable SIE for all streams */
936 azx_writeb(chip, INTCTL, 0);
937
938 /* disable controller CIE and GIE */
939 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
940 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
941}
942
943/* clear interrupts */
a98f90fd 944static void azx_int_clear(struct azx *chip)
1da177e4
LT		 945{
946 int i;
947
948 /* clear stream status */
07e4ca50 949 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 950 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 951 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
952 }
953
954 /* clear STATESTS */
955 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
956
957 /* clear rirb status */
958 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
959
960 /* clear int status */
961 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
962}
963
964/* start a stream */
a98f90fd 965static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 966{
0e153474
JC		 967 /*
968 * Before stream start, initialize parameter
969 */
970 azx_dev->insufficient = 1;
971
1da177e4 972 /* enable SIE */
ccc5df05
WN		 973 azx_writel(chip, INTCTL,
974 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 975 /* set DMA start and interrupt mask */
976 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
977 SD_CTL_DMA_START | SD_INT_MASK);
978}
979
1dddab40
TI		 980/* stop DMA */
981static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 982{
1da177e4
LT		 983 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
984 ~(SD_CTL_DMA_START | SD_INT_MASK));
985 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 986}
987
988/* stop a stream */
989static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
990{
991 azx_stream_clear(chip, azx_dev);
1da177e4 992 /* disable SIE */
ccc5df05
WN		 993 azx_writel(chip, INTCTL,
994 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 995}
996
997
998/*
cb53c626 999 * reset and start the controller registers
1da177e4 1000 */
a98f90fd 1001static void azx_init_chip(struct azx *chip)
1da177e4 1002{
cb53c626
TI		 1003 if (chip->initialized)
1004 return;
1da177e4
LT		 1005
1006 /* reset controller */
1007 azx_reset(chip);
1008
1009 /* initialize interrupts */
1010 azx_int_clear(chip);
1011 azx_int_enable(chip);
1012
1013 /* initialize the codec command I/O */
1a696978
TI		 1014 if (!chip->single_cmd)
1015 azx_init_cmd_io(chip);
1da177e4 1016
0be3b5d3
TI		 1017 /* program the position buffer */
1018 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1019 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1020
cb53c626
TI		 1021 chip->initialized = 1;
1022}
1023
1024/*
1025 * initialize the PCI registers
1026 */
1027/* update bits in a PCI register byte */
1028static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1029 unsigned char mask, unsigned char val)
1030{
1031 unsigned char data;
1032
1033 pci_read_config_byte(pci, reg, &data);
1034 data &= ~mask;
1035 data |= (val & mask);
1036 pci_write_config_byte(pci, reg, data);
1037}
1038
1039static void azx_init_pci(struct azx *chip)
1040{
90a5ad52
TI		 1041 unsigned short snoop;
1042
cb53c626
TI		 1043 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1044 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1045 * Ensuring these bits are 0 clears playback static on some HD Audio
1046 * codecs
1047 */
1048 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1049
da3fca21
V		 1050 switch (chip->driver_type) {
1051 case AZX_DRIVER_ATI:
1052 /* For ATI SB450 azalia HD audio, we need to enable snoop */
cb53c626
TI		 1053 update_pci_byte(chip->pci,
1054 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1055 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
da3fca21
V		 1056 break;
1057 case AZX_DRIVER_NVIDIA:
1058 /* For NVIDIA HDA, enable snoop */
cb53c626
TI		 1059 update_pci_byte(chip->pci,
1060 NVIDIA_HDA_TRANSREG_ADDR,
1061 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1062 update_pci_byte(chip->pci,
1063 NVIDIA_HDA_ISTRM_COH,
1064 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1065 update_pci_byte(chip->pci,
1066 NVIDIA_HDA_OSTRM_COH,
1067 0x01, NVIDIA_HDA_ENABLE_COHBIT);
da3fca21 1068 break;
90a5ad52 1069 case AZX_DRIVER_SCH:
32679f95 1070 case AZX_DRIVER_PCH:
90a5ad52
TI		 1071 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1072 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
4abc1cc2 1073 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
90a5ad52
TI		 1074 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1075 pci_read_config_word(chip->pci,
1076 INTEL_SCH_HDA_DEVC, &snoop);
4abc1cc2
TI		 1077 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1078 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
90a5ad52
TI		 1079 ? "Failed" : "OK");
1080 }
1081 break;
1082
da3fca21 1083 }
1da177e4
LT		 1084}
1085
1086
9ad593f6
TI		 1087static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1088
1da177e4
LT		 1089/*
1090 * interrupt handler
1091 */
7d12e780 1092static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1093{
a98f90fd
TI		 1094 struct azx *chip = dev_id;
1095 struct azx_dev *azx_dev;
1da177e4 1096 u32 status;
fa00e046 1097 int i, ok;
1da177e4
LT		 1098
1099 spin_lock(&chip->reg_lock);
1100
1101 status = azx_readl(chip, INTSTS);
1102 if (status == 0) {
1103 spin_unlock(&chip->reg_lock);
1104 return IRQ_NONE;
1105 }
1106
07e4ca50 1107 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1108 azx_dev = &chip->azx_dev[i];
1109 if (status & azx_dev->sd_int_sta_mask) {
1110 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ad593f6
TI		 1111 if (!azx_dev->substream || !azx_dev->running)
1112 continue;
1113 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1114 ok = azx_position_ok(chip, azx_dev);
1115 if (ok == 1) {
9ad593f6 1116 azx_dev->irq_pending = 0;
1da177e4
LT		 1117 spin_unlock(&chip->reg_lock);
1118 snd_pcm_period_elapsed(azx_dev->substream);
1119 spin_lock(&chip->reg_lock);
fa00e046 1120 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1121 /* bogus IRQ, process it later */
1122 azx_dev->irq_pending = 1;
6acaed38
TI		 1123 queue_work(chip->bus->workq,
1124 &chip->irq_pending_work);
1da177e4
LT		 1125 }
1126 }
1127 }
1128
1129 /* clear rirb int */
1130 status = azx_readb(chip, RIRBSTS);
1131 if (status & RIRB_INT_MASK) {
81740861 1132 if (status & RIRB_INT_RESPONSE)
1da177e4
LT		 1133 azx_update_rirb(chip);
1134 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1135 }
1136
1137#if 0
1138 /* clear state status int */
1139 if (azx_readb(chip, STATESTS) & 0x04)
1140 azx_writeb(chip, STATESTS, 0x04);
1141#endif
1142 spin_unlock(&chip->reg_lock);
1143
1144 return IRQ_HANDLED;
1145}
1146
1147
675f25d4
TI		 1148/*
1149 * set up a BDL entry
1150 */
1151static int setup_bdle(struct snd_pcm_substream *substream,
1152 struct azx_dev *azx_dev, u32 **bdlp,
1153 int ofs, int size, int with_ioc)
1154{
675f25d4
TI		 1155 u32 *bdl = *bdlp;
1156
1157 while (size > 0) {
1158 dma_addr_t addr;
1159 int chunk;
1160
1161 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1162 return -EINVAL;
1163
77a23f26 1164 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1165 /* program the address field of the BDL entry */
1166 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1167 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1168 /* program the size field of the BDL entry */
fc4abee8 1169 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
675f25d4
TI		 1170 bdl[2] = cpu_to_le32(chunk);
1171 /* program the IOC to enable interrupt
1172 * only when the whole fragment is processed
1173 */
1174 size -= chunk;
1175 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1176 bdl += 4;
1177 azx_dev->frags++;
1178 ofs += chunk;
1179 }
1180 *bdlp = bdl;
1181 return ofs;
1182}
1183
1da177e4
LT		 1184/*
1185 * set up BDL entries
1186 */
555e219f
TI		 1187static int azx_setup_periods(struct azx *chip,
1188 struct snd_pcm_substream *substream,
4ce107b9 1189 struct azx_dev *azx_dev)
1da177e4 1190{
4ce107b9
TI		 1191 u32 *bdl;
1192 int i, ofs, periods, period_bytes;
555e219f 1193 int pos_adj;
1da177e4
LT		 1194
1195 /* reset BDL address */
1196 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1197 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1198
97b71c94 1199 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1200 periods = azx_dev->bufsize / period_bytes;
1201
1da177e4 1202 /* program the initial BDL entries */
4ce107b9
TI		 1203 bdl = (u32 *)azx_dev->bdl.area;
1204 ofs = 0;
1205 azx_dev->frags = 0;
555e219f
TI		 1206 pos_adj = bdl_pos_adj[chip->dev_index];
1207 if (pos_adj > 0) {
675f25d4 1208 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1209 int pos_align = pos_adj;
555e219f 1210 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1211 if (!pos_adj)
e785d3d8
TI		 1212 pos_adj = pos_align;
1213 else
1214 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1215 pos_align;
675f25d4
TI		 1216 pos_adj = frames_to_bytes(runtime, pos_adj);
1217 if (pos_adj >= period_bytes) {
4abc1cc2 1218 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1219 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1220 pos_adj = 0;
1221 } else {
1222 ofs = setup_bdle(substream, azx_dev,
1223 &bdl, ofs, pos_adj, 1);
1224 if (ofs < 0)
1225 goto error;
4ce107b9 1226 }
555e219f
TI		 1227 } else
1228 pos_adj = 0;
675f25d4
TI		 1229 for (i = 0; i < periods; i++) {
1230 if (i == periods - 1 && pos_adj)
1231 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1232 period_bytes - pos_adj, 0);
1233 else
1234 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1235 period_bytes, 1);
1236 if (ofs < 0)
1237 goto error;
1da177e4 1238 }
4ce107b9 1239 return 0;
675f25d4
TI		 1240
1241 error:
4abc1cc2 1242 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1243 azx_dev->bufsize, period_bytes);
675f25d4 1244 return -EINVAL;
1da177e4
LT		 1245}
1246
1dddab40
TI		 1247/* reset stream */
1248static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1249{
1250 unsigned char val;
1251 int timeout;
1252
1dddab40
TI		 1253 azx_stream_clear(chip, azx_dev);
1254
d01ce99f
TI		 1255 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1256 SD_CTL_STREAM_RESET);
1da177e4
LT		 1257 udelay(3);
1258 timeout = 300;
1259 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1260 --timeout)
1261 ;
1262 val &= ~SD_CTL_STREAM_RESET;
1263 azx_sd_writeb(azx_dev, SD_CTL, val);
1264 udelay(3);
1265
1266 timeout = 300;
1267 /* waiting for hardware to report that the stream is out of reset */
1268 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1269 --timeout)
1270 ;
fa00e046
JK		 1271
1272 /* reset first position - may not be synced with hw at this time */
1273 *azx_dev->posbuf = 0;
1dddab40 1274}
1da177e4 1275
1dddab40
TI		 1276/*
1277 * set up the SD for streaming
1278 */
1279static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1280{
1281 /* make sure the run bit is zero for SD */
1282 azx_stream_clear(chip, azx_dev);
1da177e4
LT		 1283 /* program the stream_tag */
1284 azx_sd_writel(azx_dev, SD_CTL,
d01ce99f 1285 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1da177e4
LT		 1286 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1287
1288 /* program the length of samples in cyclic buffer */
1289 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1290
1291 /* program the stream format */
1292 /* this value needs to be the same as the one programmed */
1293 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1294
1295 /* program the stream LVI (last valid index) of the BDL */
1296 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1297
1298 /* program the BDL address */
1299 /* lower BDL address */
4ce107b9 1300 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1301 /* upper BDL address */
766979e0 1302 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1303
0be3b5d3 1304 /* enable the position buffer */
ee9d6b9a 1305 if (chip->position_fix == POS_FIX_POSBUF ||
0e153474
JC		 1306 chip->position_fix == POS_FIX_AUTO ||
1307 chip->via_dmapos_patch) {
ee9d6b9a
TI		 1308 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1309 azx_writel(chip, DPLBASE,
1310 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1311 }
c74db86b 1312
1da177e4 1313 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1314 azx_sd_writel(azx_dev, SD_CTL,
1315 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1316
1317 return 0;
1318}
1319
6ce4a3bc
TI		 1320/*
1321 * Probe the given codec address
1322 */
1323static int probe_codec(struct azx *chip, int addr)
1324{
1325 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1326 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1327 unsigned int res;
1328
a678cdee 1329 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1330 chip->probing = 1;
1331 azx_send_cmd(chip->bus, cmd);
deadff16 1332 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1333 chip->probing = 0;
a678cdee 1334 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1335 if (res == -1)
1336 return -EIO;
4abc1cc2 1337 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1338 return 0;
1339}
1340
33fa35ed
TI		 1341static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1342 struct hda_pcm *cpcm);
6ce4a3bc 1343static void azx_stop_chip(struct azx *chip);
1da177e4 1344
8dd78330
TI		 1345static void azx_bus_reset(struct hda_bus *bus)
1346{
1347 struct azx *chip = bus->private_data;
8dd78330
TI		 1348
1349 bus->in_reset = 1;
1350 azx_stop_chip(chip);
1351 azx_init_chip(chip);
65f75983 1352#ifdef CONFIG_PM
8dd78330 1353 if (chip->initialized) {
65f75983
AB		 1354 int i;
1355
c8936222 1356 for (i = 0; i < HDA_MAX_PCMS; i++)
8dd78330
TI		 1357 snd_pcm_suspend_all(chip->pcm[i]);
1358 snd_hda_suspend(chip->bus);
1359 snd_hda_resume(chip->bus);
1360 }
65f75983 1361#endif
8dd78330
TI		 1362 bus->in_reset = 0;
1363}
1364
1da177e4
LT		 1365/*
1366 * Codec initialization
1367 */
1368
2f5983f2
TI		 1369/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1370static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
7445dfc1 1371 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1372 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1373};
1374
a1e21c90 1375static int __devinit azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1376{
1377 struct hda_bus_template bus_temp;
34c25350
TI		 1378 int c, codecs, err;
1379 int max_slots;
1da177e4
LT		 1380
1381 memset(&bus_temp, 0, sizeof(bus_temp));
1382 bus_temp.private_data = chip;
1383 bus_temp.modelname = model;
1384 bus_temp.pci = chip->pci;
111d3af5
TI		 1385 bus_temp.ops.command = azx_send_cmd;
1386 bus_temp.ops.get_response = azx_get_response;
176d5335 1387 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1388 bus_temp.ops.bus_reset = azx_bus_reset;
cb53c626 1389#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1390 bus_temp.power_save = &power_save;
cb53c626
TI		 1391 bus_temp.ops.pm_notify = azx_power_notify;
1392#endif
1da177e4 1393
d01ce99f
TI		 1394 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1395 if (err < 0)
1da177e4
LT		 1396 return err;
1397
dc9c8e21
WN		 1398 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1399 chip->bus->needs_damn_long_delay = 1;
1400
34c25350 1401 codecs = 0;
2f5983f2
TI		 1402 max_slots = azx_max_codecs[chip->driver_type];
1403 if (!max_slots)
7445dfc1 1404 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1405
1406 /* First try to probe all given codec slots */
1407 for (c = 0; c < max_slots; c++) {
f1eaaeec 1408 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1409 if (probe_codec(chip, c) < 0) {
1410 /* Some BIOSen give you wrong codec addresses
1411 * that don't exist
1412 */
4abc1cc2
TI		 1413 snd_printk(KERN_WARNING SFX
1414 "Codec #%d probe error; "
6ce4a3bc
TI		 1415 "disabling it...\n", c);
1416 chip->codec_mask &= ~(1 << c);
1417 /* More badly, accessing to a non-existing
1418 * codec often screws up the controller chip,
2448158e 1419 * and disturbs the further communications.
6ce4a3bc
TI		 1420 * Thus if an error occurs during probing,
1421 * better to reset the controller chip to
1422 * get back to the sanity state.
1423 */
1424 azx_stop_chip(chip);
1425 azx_init_chip(chip);
1426 }
1427 }
1428 }
1429
1430 /* Then create codec instances */
34c25350 1431 for (c = 0; c < max_slots; c++) {
f1eaaeec 1432 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1433 struct hda_codec *codec;
a1e21c90 1434 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1435 if (err < 0)
1436 continue;
2dca0bba 1437 codec->beep_mode = chip->beep_mode;
1da177e4 1438 codecs++;
19a982b6
TI		 1439 }
1440 }
1441 if (!codecs) {
1da177e4
LT		 1442 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1443 return -ENXIO;
1444 }
a1e21c90
TI		 1445 return 0;
1446}
1da177e4 1447
a1e21c90
TI		 1448/* configure each codec instance */
1449static int __devinit azx_codec_configure(struct azx *chip)
1450{
1451 struct hda_codec *codec;
1452 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1453 snd_hda_codec_configure(codec);
1454 }
1da177e4
LT		 1455 return 0;
1456}
1457
1458
1459/*
1460 * PCM support
1461 */
1462
1463/* assign a stream for the PCM */
ef18bede
WF		 1464static inline struct azx_dev *
1465azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1466{
07e4ca50 1467 int dev, i, nums;
ef18bede
WF		 1468 struct azx_dev *res = NULL;
1469
1470 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1471 dev = chip->playback_index_offset;
1472 nums = chip->playback_streams;
1473 } else {
1474 dev = chip->capture_index_offset;
1475 nums = chip->capture_streams;
1476 }
1477 for (i = 0; i < nums; i++, dev++)
d01ce99f 1478 if (!chip->azx_dev[dev].opened) {
ef18bede
WF		 1479 res = &chip->azx_dev[dev];
1480 if (res->device == substream->pcm->device)
1481 break;
1da177e4 1482 }
ef18bede
WF		 1483 if (res) {
1484 res->opened = 1;
1485 res->device = substream->pcm->device;
1486 }
1487 return res;
1da177e4
LT		 1488}
1489
1490/* release the assigned stream */
a98f90fd 1491static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1492{
1493 azx_dev->opened = 0;
1494}
1495
a98f90fd 1496static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1497 .info = (SNDRV_PCM_INFO_MMAP |
1498 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1499 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1500 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1501 /* No full-resume yet implemented */
1502 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52
TI		 1503 SNDRV_PCM_INFO_PAUSE |
1504 SNDRV_PCM_INFO_SYNC_START),
1da177e4
LT		 1505 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1506 .rates = SNDRV_PCM_RATE_48000,
1507 .rate_min = 48000,
1508 .rate_max = 48000,
1509 .channels_min = 2,
1510 .channels_max = 2,
1511 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1512 .period_bytes_min = 128,
1513 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1514 .periods_min = 2,
1515 .periods_max = AZX_MAX_FRAG,
1516 .fifo_size = 0,
1517};
1518
1519struct azx_pcm {
a98f90fd 1520 struct azx *chip;
1da177e4
LT		 1521 struct hda_codec *codec;
1522 struct hda_pcm_stream *hinfo[2];
1523};
1524
a98f90fd 1525static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1526{
1527 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1528 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1529 struct azx *chip = apcm->chip;
1530 struct azx_dev *azx_dev;
1531 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1532 unsigned long flags;
1533 int err;
1534
62932df8 1535 mutex_lock(&chip->open_mutex);
ef18bede 1536 azx_dev = azx_assign_device(chip, substream);
1da177e4 1537 if (azx_dev == NULL) {
62932df8 1538 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1539 return -EBUSY;
1540 }
1541 runtime->hw = azx_pcm_hw;
1542 runtime->hw.channels_min = hinfo->channels_min;
1543 runtime->hw.channels_max = hinfo->channels_max;
1544 runtime->hw.formats = hinfo->formats;
1545 runtime->hw.rates = hinfo->rates;
1546 snd_pcm_limit_hw_rates(runtime);
1547 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5f1545bc
JD		 1548 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1549 128);
1550 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1551 128);
cb53c626 1552 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1553 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1554 if (err < 0) {
1da177e4 1555 azx_release_device(azx_dev);
cb53c626 1556 snd_hda_power_down(apcm->codec);
62932df8 1557 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1558 return err;
1559 }
70d321e6 1560 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1561 /* sanity check */
1562 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1563 snd_BUG_ON(!runtime->hw.channels_max) ||
1564 snd_BUG_ON(!runtime->hw.formats) ||
1565 snd_BUG_ON(!runtime->hw.rates)) {
1566 azx_release_device(azx_dev);
1567 hinfo->ops.close(hinfo, apcm->codec, substream);
1568 snd_hda_power_down(apcm->codec);
1569 mutex_unlock(&chip->open_mutex);
1570 return -EINVAL;
1571 }
1da177e4
LT		 1572 spin_lock_irqsave(&chip->reg_lock, flags);
1573 azx_dev->substream = substream;
1574 azx_dev->running = 0;
1575 spin_unlock_irqrestore(&chip->reg_lock, flags);
1576
1577 runtime->private_data = azx_dev;
850f0e52 1578 snd_pcm_set_sync(substream);
62932df8 1579 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1580 return 0;
1581}
1582
a98f90fd 1583static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1584{
1585 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1586 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1587 struct azx *chip = apcm->chip;
1588 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1589 unsigned long flags;
1590
62932df8 1591 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1592 spin_lock_irqsave(&chip->reg_lock, flags);
1593 azx_dev->substream = NULL;
1594 azx_dev->running = 0;
1595 spin_unlock_irqrestore(&chip->reg_lock, flags);
1596 azx_release_device(azx_dev);
1597 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1598 snd_hda_power_down(apcm->codec);
62932df8 1599 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1600 return 0;
1601}
1602
d01ce99f
TI		 1603static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1604 struct snd_pcm_hw_params *hw_params)
1da177e4 1605{
97b71c94
TI		 1606 struct azx_dev *azx_dev = get_azx_dev(substream);
1607
1608 azx_dev->bufsize = 0;
1609 azx_dev->period_bytes = 0;
1610 azx_dev->format_val = 0;
d01ce99f
TI		 1611 return snd_pcm_lib_malloc_pages(substream,
1612 params_buffer_bytes(hw_params));
1da177e4
LT		 1613}
1614
a98f90fd 1615static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1616{
1617 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1618 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1619 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1620
1621 /* reset BDL address */
1622 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1623 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1624 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1625 azx_dev->bufsize = 0;
1626 azx_dev->period_bytes = 0;
1627 azx_dev->format_val = 0;
1da177e4
LT		 1628
1629 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1630
1631 return snd_pcm_lib_free_pages(substream);
1632}
1633
a98f90fd 1634static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1635{
1636 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1637 struct azx *chip = apcm->chip;
1638 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1639 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1640 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94
TI		 1641 unsigned int bufsize, period_bytes, format_val;
1642 int err;
1da177e4 1643
fa00e046 1644 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1645 format_val = snd_hda_calc_stream_format(runtime->rate,
1646 runtime->channels,
1647 runtime->format,
1648 hinfo->maxbps);
1649 if (!format_val) {
d01ce99f
TI		 1650 snd_printk(KERN_ERR SFX
1651 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1652 runtime->rate, runtime->channels, runtime->format);
1653 return -EINVAL;
1654 }
1655
97b71c94
TI		 1656 bufsize = snd_pcm_lib_buffer_bytes(substream);
1657 period_bytes = snd_pcm_lib_period_bytes(substream);
1658
4abc1cc2 1659 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1660 bufsize, format_val);
1661
1662 if (bufsize != azx_dev->bufsize ||
1663 period_bytes != azx_dev->period_bytes ||
1664 format_val != azx_dev->format_val) {
1665 azx_dev->bufsize = bufsize;
1666 azx_dev->period_bytes = period_bytes;
1667 azx_dev->format_val = format_val;
1668 err = azx_setup_periods(chip, substream, azx_dev);
1669 if (err < 0)
1670 return err;
1671 }
1672
fa00e046
JK		 1673 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1674 (runtime->rate * 2);
1da177e4
LT		 1675 azx_setup_controller(chip, azx_dev);
1676 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1677 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1678 else
1679 azx_dev->fifo_size = 0;
1680
1681 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1682 azx_dev->format_val, substream);
1683}
1684
a98f90fd 1685static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1686{
1687 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1688 struct azx *chip = apcm->chip;
850f0e52
TI		 1689 struct azx_dev *azx_dev;
1690 struct snd_pcm_substream *s;
fa00e046 1691 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1692 int nwait, timeout;
1da177e4 1693
1da177e4 1694 switch (cmd) {
fa00e046
JK		 1695 case SNDRV_PCM_TRIGGER_START:
1696 rstart = 1;
1da177e4
LT		 1697 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1698 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1699 start = 1;
1da177e4
LT		 1700 break;
1701 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1702 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1703 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1704 start = 0;
1da177e4
LT		 1705 break;
1706 default:
850f0e52
TI		 1707 return -EINVAL;
1708 }
1709
1710 snd_pcm_group_for_each_entry(s, substream) {
1711 if (s->pcm->card != substream->pcm->card)
1712 continue;
1713 azx_dev = get_azx_dev(s);
1714 sbits |= 1 << azx_dev->index;
1715 nsync++;
1716 snd_pcm_trigger_done(s, substream);
1717 }
1718
1719 spin_lock(&chip->reg_lock);
1720 if (nsync > 1) {
1721 /* first, set SYNC bits of corresponding streams */
1722 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1723 }
1724 snd_pcm_group_for_each_entry(s, substream) {
1725 if (s->pcm->card != substream->pcm->card)
1726 continue;
1727 azx_dev = get_azx_dev(s);
fa00e046
JK		 1728 if (rstart) {
1729 azx_dev->start_flag = 1;
1730 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1731 }
850f0e52
TI		 1732 if (start)
1733 azx_stream_start(chip, azx_dev);
1734 else
1735 azx_stream_stop(chip, azx_dev);
1736 azx_dev->running = start;
1da177e4
LT		 1737 }
1738 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1739 if (start) {
1740 if (nsync == 1)
1741 return 0;
1742 /* wait until all FIFOs get ready */
1743 for (timeout = 5000; timeout; timeout--) {
1744 nwait = 0;
1745 snd_pcm_group_for_each_entry(s, substream) {
1746 if (s->pcm->card != substream->pcm->card)
1747 continue;
1748 azx_dev = get_azx_dev(s);
1749 if (!(azx_sd_readb(azx_dev, SD_STS) &
1750 SD_STS_FIFO_READY))
1751 nwait++;
1752 }
1753 if (!nwait)
1754 break;
1755 cpu_relax();
1756 }
1757 } else {
1758 /* wait until all RUN bits are cleared */
1759 for (timeout = 5000; timeout; timeout--) {
1760 nwait = 0;
1761 snd_pcm_group_for_each_entry(s, substream) {
1762 if (s->pcm->card != substream->pcm->card)
1763 continue;
1764 azx_dev = get_azx_dev(s);
1765 if (azx_sd_readb(azx_dev, SD_CTL) &
1766 SD_CTL_DMA_START)
1767 nwait++;
1768 }
1769 if (!nwait)
1770 break;
1771 cpu_relax();
1772 }
1da177e4 1773 }
850f0e52
TI		 1774 if (nsync > 1) {
1775 spin_lock(&chip->reg_lock);
1776 /* reset SYNC bits */
1777 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1778 spin_unlock(&chip->reg_lock);
1779 }
1780 return 0;
1da177e4
LT		 1781}
1782
0e153474
JC		 1783/* get the current DMA position with correction on VIA chips */
1784static unsigned int azx_via_get_position(struct azx *chip,
1785 struct azx_dev *azx_dev)
1786{
1787 unsigned int link_pos, mini_pos, bound_pos;
1788 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1789 unsigned int fifo_size;
1790
1791 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1792 if (azx_dev->index >= 4) {
1793 /* Playback, no problem using link position */
1794 return link_pos;
1795 }
1796
1797 /* Capture */
1798 /* For new chipset,
1799 * use mod to get the DMA position just like old chipset
1800 */
1801 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1802 mod_dma_pos %= azx_dev->period_bytes;
1803
1804 /* azx_dev->fifo_size can't get FIFO size of in stream.
1805 * Get from base address + offset.
1806 */
1807 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1808
1809 if (azx_dev->insufficient) {
1810 /* Link position never gather than FIFO size */
1811 if (link_pos <= fifo_size)
1812 return 0;
1813
1814 azx_dev->insufficient = 0;
1815 }
1816
1817 if (link_pos <= fifo_size)
1818 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1819 else
1820 mini_pos = link_pos - fifo_size;
1821
1822 /* Find nearest previous boudary */
1823 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1824 mod_link_pos = link_pos % azx_dev->period_bytes;
1825 if (mod_link_pos >= fifo_size)
1826 bound_pos = link_pos - mod_link_pos;
1827 else if (mod_dma_pos >= mod_mini_pos)
1828 bound_pos = mini_pos - mod_mini_pos;
1829 else {
1830 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1831 if (bound_pos >= azx_dev->bufsize)
1832 bound_pos = 0;
1833 }
1834
1835 /* Calculate real DMA position we want */
1836 return bound_pos + mod_dma_pos;
1837}
1838
9ad593f6
TI		 1839static unsigned int azx_get_position(struct azx *chip,
1840 struct azx_dev *azx_dev)
1da177e4 1841{
1da177e4
LT		 1842 unsigned int pos;
1843
0e153474
JC		 1844 if (chip->via_dmapos_patch)
1845 pos = azx_via_get_position(chip, azx_dev);
1846 else if (chip->position_fix == POS_FIX_POSBUF ||
1847 chip->position_fix == POS_FIX_AUTO) {
c74db86b 1848 /* use the position buffer */
929861c6 1849 pos = le32_to_cpu(*azx_dev->posbuf);
c74db86b
TI		 1850 } else {
1851 /* read LPIB */
1852 pos = azx_sd_readl(azx_dev, SD_LPIB);
c74db86b 1853 }
1da177e4
LT		 1854 if (pos >= azx_dev->bufsize)
1855 pos = 0;
9ad593f6
TI		 1856 return pos;
1857}
1858
1859static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1860{
1861 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1862 struct azx *chip = apcm->chip;
1863 struct azx_dev *azx_dev = get_azx_dev(substream);
1864 return bytes_to_frames(substream->runtime,
1865 azx_get_position(chip, azx_dev));
1866}
1867
1868/*
1869 * Check whether the current DMA position is acceptable for updating
1870 * periods. Returns non-zero if it's OK.
1871 *
1872 * Many HD-audio controllers appear pretty inaccurate about
1873 * the update-IRQ timing. The IRQ is issued before actually the
1874 * data is processed. So, we need to process it afterwords in a
1875 * workqueue.
1876 */
1877static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1878{
1879 unsigned int pos;
1880
fa00e046
JK		 1881 if (azx_dev->start_flag &&
1882 time_before_eq(jiffies, azx_dev->start_jiffies))
1883 return -1; /* bogus (too early) interrupt */
1884 azx_dev->start_flag = 0;
1885
9ad593f6
TI		 1886 pos = azx_get_position(chip, azx_dev);
1887 if (chip->position_fix == POS_FIX_AUTO) {
1888 if (!pos) {
1889 printk(KERN_WARNING
1890 "hda-intel: Invalid position buffer, "
1891 "using LPIB read method instead.\n");
d2e1c973 1892 chip->position_fix = POS_FIX_LPIB;
9ad593f6
TI		 1893 pos = azx_get_position(chip, azx_dev);
1894 } else
1895 chip->position_fix = POS_FIX_POSBUF;
1896 }
1897
a62741cf
TI		 1898 if (!bdl_pos_adj[chip->dev_index])
1899 return 1; /* no delayed ack */
d6d8bf54
TI		 1900 if (WARN_ONCE(!azx_dev->period_bytes,
1901 "hda-intel: zero azx_dev->period_bytes"))
1902 return 0; /* this shouldn't happen! */
9ad593f6
TI		 1903 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1904 return 0; /* NG - it's below the period boundary */
1905 return 1; /* OK, it's fine */
1906}
1907
1908/*
1909 * The work for pending PCM period updates.
1910 */
1911static void azx_irq_pending_work(struct work_struct *work)
1912{
1913 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1914 int i, pending;
1915
a6a950a8
TI		 1916 if (!chip->irq_pending_warned) {
1917 printk(KERN_WARNING
1918 "hda-intel: IRQ timing workaround is activated "
1919 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1920 chip->card->number);
1921 chip->irq_pending_warned = 1;
1922 }
1923
9ad593f6
TI		 1924 for (;;) {
1925 pending = 0;
1926 spin_lock_irq(&chip->reg_lock);
1927 for (i = 0; i < chip->num_streams; i++) {
1928 struct azx_dev *azx_dev = &chip->azx_dev[i];
1929 if (!azx_dev->irq_pending ||
1930 !azx_dev->substream ||
1931 !azx_dev->running)
1932 continue;
1933 if (azx_position_ok(chip, azx_dev)) {
1934 azx_dev->irq_pending = 0;
1935 spin_unlock(&chip->reg_lock);
1936 snd_pcm_period_elapsed(azx_dev->substream);
1937 spin_lock(&chip->reg_lock);
1938 } else
1939 pending++;
1940 }
1941 spin_unlock_irq(&chip->reg_lock);
1942 if (!pending)
1943 return;
1944 cond_resched();
1945 }
1946}
1947
1948/* clear irq_pending flags and assure no on-going workq */
1949static void azx_clear_irq_pending(struct azx *chip)
1950{
1951 int i;
1952
1953 spin_lock_irq(&chip->reg_lock);
1954 for (i = 0; i < chip->num_streams; i++)
1955 chip->azx_dev[i].irq_pending = 0;
1956 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1957}
1958
a98f90fd 1959static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 1960 .open = azx_pcm_open,
1961 .close = azx_pcm_close,
1962 .ioctl = snd_pcm_lib_ioctl,
1963 .hw_params = azx_pcm_hw_params,
1964 .hw_free = azx_pcm_hw_free,
1965 .prepare = azx_pcm_prepare,
1966 .trigger = azx_pcm_trigger,
1967 .pointer = azx_pcm_pointer,
4ce107b9 1968 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 1969};
1970
a98f90fd 1971static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 1972{
176d5335
TI		 1973 struct azx_pcm *apcm = pcm->private_data;
1974 if (apcm) {
1975 apcm->chip->pcm[pcm->device] = NULL;
1976 kfree(apcm);
1977 }
1da177e4
LT		 1978}
1979
176d5335 1980static int
33fa35ed
TI		 1981azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1982 struct hda_pcm *cpcm)
1da177e4 1983{
33fa35ed 1984 struct azx *chip = bus->private_data;
a98f90fd 1985 struct snd_pcm *pcm;
1da177e4 1986 struct azx_pcm *apcm;
176d5335
TI		 1987 int pcm_dev = cpcm->device;
1988 int s, err;
1da177e4 1989
c8936222 1990 if (pcm_dev >= HDA_MAX_PCMS) {
176d5335
TI		 1991 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1992 pcm_dev);
da3cec35 1993 return -EINVAL;
176d5335
TI		 1994 }
1995 if (chip->pcm[pcm_dev]) {
1996 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1997 return -EBUSY;
1998 }
1999 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2000 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2001 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2002 &pcm);
2003 if (err < 0)
2004 return err;
18cb7109 2005 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2006 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2007 if (apcm == NULL)
2008 return -ENOMEM;
2009 apcm->chip = chip;
2010 apcm->codec = codec;
1da177e4
LT		 2011 pcm->private_data = apcm;
2012 pcm->private_free = azx_pcm_free;
176d5335
TI		 2013 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2014 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2015 chip->pcm[pcm_dev] = pcm;
2016 cpcm->pcm = pcm;
2017 for (s = 0; s < 2; s++) {
2018 apcm->hinfo[s] = &cpcm->stream[s];
2019 if (cpcm->stream[s].substreams)
2020 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2021 }
2022 /* buffer pre-allocation */
4ce107b9 2023 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2024 snd_dma_pci_data(chip->pci),
fc4abee8 2025 1024 * 64, 32 * 1024 * 1024);
1da177e4
LT		 2026 return 0;
2027}
2028
2029/*
2030 * mixer creation - all stuff is implemented in hda module
2031 */
a98f90fd 2032static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2033{
2034 return snd_hda_build_controls(chip->bus);
2035}
2036
2037
2038/*
2039 * initialize SD streams
2040 */
a98f90fd 2041static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2042{
2043 int i;
2044
2045 /* initialize each stream (aka device)
d01ce99f
TI		 2046 * assign the starting bdl address to each stream (device)
2047 * and initialize
1da177e4 2048 */
07e4ca50 2049 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2050 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2051 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2052 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2053 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2054 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2055 azx_dev->sd_int_sta_mask = 1 << i;
2056 /* stream tag: must be non-zero and unique */
2057 azx_dev->index = i;
2058 azx_dev->stream_tag = i + 1;
2059 }
2060
2061 return 0;
2062}
2063
68e7fffc
TI		 2064static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2065{
437a5a46
TI		 2066 if (request_irq(chip->pci->irq, azx_interrupt,
2067 chip->msi ? 0 : IRQF_SHARED,
9492837a 2068 "hda_intel", chip)) {
68e7fffc
TI		 2069 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2070 "disabling device\n", chip->pci->irq);
2071 if (do_disconnect)
2072 snd_card_disconnect(chip->card);
2073 return -1;
2074 }
2075 chip->irq = chip->pci->irq;
69e13418 2076 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2077 return 0;
2078}
2079
1da177e4 2080
cb53c626
TI		 2081static void azx_stop_chip(struct azx *chip)
2082{
95e99fda 2083 if (!chip->initialized)
cb53c626
TI		 2084 return;
2085
2086 /* disable interrupts */
2087 azx_int_disable(chip);
2088 azx_int_clear(chip);
2089
2090 /* disable CORB/RIRB */
2091 azx_free_cmd_io(chip);
2092
2093 /* disable position buffer */
2094 azx_writel(chip, DPLBASE, 0);
2095 azx_writel(chip, DPUBASE, 0);
2096
2097 chip->initialized = 0;
2098}
2099
2100#ifdef CONFIG_SND_HDA_POWER_SAVE
2101/* power-up/down the controller */
33fa35ed 2102static void azx_power_notify(struct hda_bus *bus)
cb53c626 2103{
33fa35ed 2104 struct azx *chip = bus->private_data;
cb53c626
TI		 2105 struct hda_codec *c;
2106 int power_on = 0;
2107
33fa35ed 2108 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 2109 if (c->power_on) {
2110 power_on = 1;
2111 break;
2112 }
2113 }
2114 if (power_on)
2115 azx_init_chip(chip);
0287d970
WF		 2116 else if (chip->running && power_save_controller &&
2117 !bus->power_keep_link_on)
cb53c626 2118 azx_stop_chip(chip);
cb53c626 2119}
5c0b9bec
TI		 2120#endif /* CONFIG_SND_HDA_POWER_SAVE */
2121
2122#ifdef CONFIG_PM
2123/*
2124 * power management
2125 */
986862bd
TI		 2126
2127static int snd_hda_codecs_inuse(struct hda_bus *bus)
2128{
2129 struct hda_codec *codec;
2130
2131 list_for_each_entry(codec, &bus->codec_list, list) {
2132 if (snd_hda_codec_needs_resume(codec))
2133 return 1;
2134 }
2135 return 0;
2136}
cb53c626 2137
421a1252 2138static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2139{
421a1252
TI		 2140 struct snd_card *card = pci_get_drvdata(pci);
2141 struct azx *chip = card->private_data;
1da177e4
LT		 2142 int i;
2143
421a1252 2144 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2145 azx_clear_irq_pending(chip);
c8936222 2146 for (i = 0; i < HDA_MAX_PCMS; i++)
421a1252 2147 snd_pcm_suspend_all(chip->pcm[i]);
0b7a2e9c 2148 if (chip->initialized)
8dd78330 2149 snd_hda_suspend(chip->bus);
cb53c626 2150 azx_stop_chip(chip);
30b35399 2151 if (chip->irq >= 0) {
43001c95 2152 free_irq(chip->irq, chip);
30b35399
TI		 2153 chip->irq = -1;
2154 }
68e7fffc 2155 if (chip->msi)
43001c95 2156 pci_disable_msi(chip->pci);
421a1252
TI		 2157 pci_disable_device(pci);
2158 pci_save_state(pci);
30b35399 2159 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 2160 return 0;
2161}
2162
421a1252 2163static int azx_resume(struct pci_dev *pci)
1da177e4 2164{
421a1252
TI		 2165 struct snd_card *card = pci_get_drvdata(pci);
2166 struct azx *chip = card->private_data;
1da177e4 2167
d14a7e0b
TI		 2168 pci_set_power_state(pci, PCI_D0);
2169 pci_restore_state(pci);
30b35399
TI		 2170 if (pci_enable_device(pci) < 0) {
2171 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2172 "disabling device\n");
2173 snd_card_disconnect(card);
2174 return -EIO;
2175 }
2176 pci_set_master(pci);
68e7fffc
TI		 2177 if (chip->msi)
2178 if (pci_enable_msi(pci) < 0)
2179 chip->msi = 0;
2180 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2181 return -EIO;
cb53c626 2182 azx_init_pci(chip);
d804ad92
ML		 2183
2184 if (snd_hda_codecs_inuse(chip->bus))
2185 azx_init_chip(chip);
2186
1da177e4 2187 snd_hda_resume(chip->bus);
421a1252 2188 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2189 return 0;
2190}
2191#endif /* CONFIG_PM */
2192
2193
0cbf0098
TI		 2194/*
2195 * reboot notifier for hang-up problem at power-down
2196 */
2197static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2198{
2199 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2200 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2201 azx_stop_chip(chip);
2202 return NOTIFY_OK;
2203}
2204
2205static void azx_notifier_register(struct azx *chip)
2206{
2207 chip->reboot_notifier.notifier_call = azx_halt;
2208 register_reboot_notifier(&chip->reboot_notifier);
2209}
2210
2211static void azx_notifier_unregister(struct azx *chip)
2212{
2213 if (chip->reboot_notifier.notifier_call)
2214 unregister_reboot_notifier(&chip->reboot_notifier);
2215}
2216
1da177e4
LT		 2217/*
2218 * destructor
2219 */
a98f90fd 2220static int azx_free(struct azx *chip)
1da177e4 2221{
4ce107b9
TI		 2222 int i;
2223
0cbf0098
TI		 2224 azx_notifier_unregister(chip);
2225
ce43fbae 2226 if (chip->initialized) {
9ad593f6 2227 azx_clear_irq_pending(chip);
07e4ca50 2228 for (i = 0; i < chip->num_streams; i++)
1da177e4 2229 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2230 azx_stop_chip(chip);
1da177e4
LT		 2231 }
2232
f000fd80 2233 if (chip->irq >= 0)
1da177e4 2234 free_irq(chip->irq, (void*)chip);
68e7fffc 2235 if (chip->msi)
30b35399 2236 pci_disable_msi(chip->pci);
f079c25a
TI		 2237 if (chip->remap_addr)
2238 iounmap(chip->remap_addr);
1da177e4 2239
4ce107b9
TI		 2240 if (chip->azx_dev) {
2241 for (i = 0; i < chip->num_streams; i++)
2242 if (chip->azx_dev[i].bdl.area)
2243 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2244 }
1da177e4
LT		 2245 if (chip->rb.area)
2246 snd_dma_free_pages(&chip->rb);
1da177e4
LT		 2247 if (chip->posbuf.area)
2248 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT		 2249 pci_release_regions(chip->pci);
2250 pci_disable_device(chip->pci);
07e4ca50 2251 kfree(chip->azx_dev);
1da177e4
LT		 2252 kfree(chip);
2253
2254 return 0;
2255}
2256
a98f90fd 2257static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2258{
2259 return azx_free(device->device_data);
2260}
2261
3372a153
TI		 2262/*
2263 * white/black-listing for position_fix
2264 */
623ec047 2265static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2266 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2267 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
9919c761 2268 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
2f703e7a 2269 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
0708cc58 2270 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
d2e1c973 2271 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
9ec8ddad 2272 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2273 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
0321b695 2274 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
8815cd03 2275 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
572c0e3c 2276 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
3372a153
TI		 2277 {}
2278};
2279
2280static int __devinit check_position_fix(struct azx *chip, int fix)
2281{
2282 const struct snd_pci_quirk *q;
2283
c673ba1c
TI		 2284 switch (fix) {
2285 case POS_FIX_LPIB:
2286 case POS_FIX_POSBUF:
2287 return fix;
2288 }
2289
2290 /* Check VIA/ATI HD Audio Controller exist */
2291 switch (chip->driver_type) {
2292 case AZX_DRIVER_VIA:
2293 case AZX_DRIVER_ATI:
0e153474
JC		 2294 chip->via_dmapos_patch = 1;
2295 /* Use link position directly, avoid any transfer problem. */
2296 return POS_FIX_LPIB;
2297 }
2298 chip->via_dmapos_patch = 0;
2299
c673ba1c
TI		 2300 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2301 if (q) {
2302 printk(KERN_INFO
2303 "hda_intel: position_fix set to %d "
2304 "for device %04x:%04x\n",
2305 q->value, q->subvendor, q->subdevice);
2306 return q->value;
3372a153 2307 }
c673ba1c 2308 return POS_FIX_AUTO;
3372a153
TI		 2309}
2310
669ba27a
TI		 2311/*
2312 * black-lists for probe_mask
2313 */
2314static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2315 /* Thinkpad often breaks the controller communication when accessing
2316 * to the non-working (or non-existing) modem codec slot.
2317 */
2318 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2319 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2320 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2321 /* broken BIOS */
2322 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2323 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2324 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2325 /* forced codec slots */
93574844 2326 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2327 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
669ba27a
TI		 2328 {}
2329};
2330
f1eaaeec
TI		 2331#define AZX_FORCE_CODEC_MASK 0x100
2332
5aba4f8e 2333static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2334{
2335 const struct snd_pci_quirk *q;
2336
f1eaaeec
TI		 2337 chip->codec_probe_mask = probe_mask[dev];
2338 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2339 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2340 if (q) {
2341 printk(KERN_INFO
2342 "hda_intel: probe_mask set to 0x%x "
2343 "for device %04x:%04x\n",
2344 q->value, q->subvendor, q->subdevice);
f1eaaeec 2345 chip->codec_probe_mask = q->value;
669ba27a
TI		 2346 }
2347 }
f1eaaeec
TI		 2348
2349 /* check forced option */
2350 if (chip->codec_probe_mask != -1 &&
2351 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2352 chip->codec_mask = chip->codec_probe_mask & 0xff;
2353 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2354 chip->codec_mask);
2355 }
669ba27a
TI		 2356}
2357
4d8e22e0 2358/*
71623855 2359 * white/black-list for enable_msi
4d8e22e0 2360 */
71623855 2361static struct snd_pci_quirk msi_black_list[] __devinitdata = {
9dc8398b 2362 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 2363 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 2364 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 2365 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 2366 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 2367 {}
2368};
2369
2370static void __devinit check_msi(struct azx *chip)
2371{
2372 const struct snd_pci_quirk *q;
2373
71623855
TI		 2374 if (enable_msi >= 0) {
2375 chip->msi = !!enable_msi;
4d8e22e0 2376 return;
71623855
TI		 2377 }
2378 chip->msi = 1; /* enable MSI as default */
2379 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 2380 if (q) {
2381 printk(KERN_INFO
2382 "hda_intel: msi for device %04x:%04x set to %d\n",
2383 q->subvendor, q->subdevice, q->value);
2384 chip->msi = q->value;
80c43ed7
TI		 2385 return;
2386 }
2387
2388 /* NVidia chipsets seem to cause troubles with MSI */
2389 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
2390 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n");
2391 chip->msi = 0;
4d8e22e0
TI		 2392 }
2393}
2394
669ba27a 2395
1da177e4
LT		 2396/*
2397 * constructor
2398 */
a98f90fd 2399static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
5aba4f8e 2400 int dev, int driver_type,
a98f90fd 2401 struct azx **rchip)
1da177e4 2402{
a98f90fd 2403 struct azx *chip;
4ce107b9 2404 int i, err;
bcd72003 2405 unsigned short gcap;
a98f90fd 2406 static struct snd_device_ops ops = {
1da177e4
LT		 2407 .dev_free = azx_dev_free,
2408 };
2409
2410 *rchip = NULL;
bcd72003 2411
927fc866
PM		 2412 err = pci_enable_device(pci);
2413 if (err < 0)
1da177e4
LT		 2414 return err;
2415
e560d8d8 2416 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2417 if (!chip) {
1da177e4
LT		 2418 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2419 pci_disable_device(pci);
2420 return -ENOMEM;
2421 }
2422
2423 spin_lock_init(&chip->reg_lock);
62932df8 2424 mutex_init(&chip->open_mutex);
1da177e4
LT		 2425 chip->card = card;
2426 chip->pci = pci;
2427 chip->irq = -1;
07e4ca50 2428 chip->driver_type = driver_type;
4d8e22e0 2429 check_msi(chip);
555e219f 2430 chip->dev_index = dev;
9ad593f6 2431 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1da177e4 2432
5aba4f8e
TI		 2433 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2434 check_probe_mask(chip, dev);
3372a153 2435
27346166 2436 chip->single_cmd = single_cmd;
c74db86b 2437
5c0d7bc1
TI		 2438 if (bdl_pos_adj[dev] < 0) {
2439 switch (chip->driver_type) {
0c6341ac 2440 case AZX_DRIVER_ICH:
32679f95 2441 case AZX_DRIVER_PCH:
0c6341ac 2442 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2443 break;
2444 default:
0c6341ac 2445 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2446 break;
2447 }
2448 }
2449
07e4ca50
TI		 2450#if BITS_PER_LONG != 64
2451 /* Fix up base address on ULI M5461 */
2452 if (chip->driver_type == AZX_DRIVER_ULI) {
2453 u16 tmp3;
2454 pci_read_config_word(pci, 0x40, &tmp3);
2455 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2456 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2457 }
2458#endif
2459
927fc866
PM		 2460 err = pci_request_regions(pci, "ICH HD audio");
2461 if (err < 0) {
1da177e4
LT		 2462 kfree(chip);
2463 pci_disable_device(pci);
2464 return err;
2465 }
2466
927fc866 2467 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 2468 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 2469 if (chip->remap_addr == NULL) {
2470 snd_printk(KERN_ERR SFX "ioremap error\n");
2471 err = -ENXIO;
2472 goto errout;
2473 }
2474
68e7fffc
TI		 2475 if (chip->msi)
2476 if (pci_enable_msi(pci) < 0)
2477 chip->msi = 0;
7376d013 2478
68e7fffc 2479 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT		 2480 err = -EBUSY;
2481 goto errout;
2482 }
1da177e4
LT		 2483
2484 pci_set_master(pci);
2485 synchronize_irq(chip->irq);
2486
bcd72003 2487 gcap = azx_readw(chip, GCAP);
4abc1cc2 2488 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 2489
dc4c2e6b
AB		 2490 /* disable SB600 64bit support for safety */
2491 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2492 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2493 struct pci_dev *p_smbus;
2494 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2495 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2496 NULL);
2497 if (p_smbus) {
2498 if (p_smbus->revision < 0x30)
2499 gcap &= ~ICH6_GCAP_64OK;
2500 pci_dev_put(p_smbus);
2501 }
2502 }
09240cf4 2503
396087ea
JK		 2504 /* disable 64bit DMA address for Teradici */
2505 /* it does not work with device 6549:1200 subsys e4a2:040b */
2506 if (chip->driver_type == AZX_DRIVER_TERA)
2507 gcap &= ~ICH6_GCAP_64OK;
2508
cf7aaca8 2509 /* allow 64bit DMA address if supported by H/W */
b21fadb9 2510 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 2511 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 2512 else {
e930438c
YH		 2513 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2514 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 2515 }
cf7aaca8 2516
8b6ed8e7
TI		 2517 /* read number of streams from GCAP register instead of using
2518 * hardcoded value
2519 */
2520 chip->capture_streams = (gcap >> 8) & 0x0f;
2521 chip->playback_streams = (gcap >> 12) & 0x0f;
2522 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 2523 /* gcap didn't give any info, switching to old method */
2524
2525 switch (chip->driver_type) {
2526 case AZX_DRIVER_ULI:
2527 chip->playback_streams = ULI_NUM_PLAYBACK;
2528 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 2529 break;
2530 case AZX_DRIVER_ATIHDMI:
2531 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2532 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 2533 break;
c4da29ca 2534 case AZX_DRIVER_GENERIC:
bcd72003
TD		 2535 default:
2536 chip->playback_streams = ICH6_NUM_PLAYBACK;
2537 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 2538 break;
2539 }
07e4ca50 2540 }
8b6ed8e7
TI		 2541 chip->capture_index_offset = 0;
2542 chip->playback_index_offset = chip->capture_streams;
07e4ca50 2543 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 2544 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2545 GFP_KERNEL);
927fc866 2546 if (!chip->azx_dev) {
4abc1cc2 2547 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
07e4ca50
TI		 2548 goto errout;
2549 }
2550
4ce107b9
TI		 2551 for (i = 0; i < chip->num_streams; i++) {
2552 /* allocate memory for the BDL for each stream */
2553 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2554 snd_dma_pci_data(chip->pci),
2555 BDL_SIZE, &chip->azx_dev[i].bdl);
2556 if (err < 0) {
2557 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2558 goto errout;
2559 }
1da177e4 2560 }
0be3b5d3 2561 /* allocate memory for the position buffer */
d01ce99f
TI		 2562 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2563 snd_dma_pci_data(chip->pci),
2564 chip->num_streams * 8, &chip->posbuf);
2565 if (err < 0) {
0be3b5d3
TI		 2566 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2567 goto errout;
1da177e4 2568 }
1da177e4 2569 /* allocate CORB/RIRB */
81740861
TI		 2570 err = azx_alloc_cmd_io(chip);
2571 if (err < 0)
2572 goto errout;
1da177e4
LT		 2573
2574 /* initialize streams */
2575 azx_init_stream(chip);
2576
2577 /* initialize chip */
cb53c626 2578 azx_init_pci(chip);
1da177e4
LT		 2579 azx_init_chip(chip);
2580
2581 /* codec detection */
927fc866 2582 if (!chip->codec_mask) {
1da177e4
LT		 2583 snd_printk(KERN_ERR SFX "no codecs found!\n");
2584 err = -ENODEV;
2585 goto errout;
2586 }
2587
d01ce99f
TI		 2588 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2589 if (err <0) {
1da177e4
LT		 2590 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2591 goto errout;
2592 }
2593
07e4ca50 2594 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 2595 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2596 sizeof(card->shortname));
2597 snprintf(card->longname, sizeof(card->longname),
2598 "%s at 0x%lx irq %i",
2599 card->shortname, chip->addr, chip->irq);
07e4ca50 2600
1da177e4
LT		 2601 *rchip = chip;
2602 return 0;
2603
2604 errout:
2605 azx_free(chip);
2606 return err;
2607}
2608
cb53c626
TI		 2609static void power_down_all_codecs(struct azx *chip)
2610{
2611#ifdef CONFIG_SND_HDA_POWER_SAVE
2612 /* The codecs were powered up in snd_hda_codec_new().
2613 * Now all initialization done, so turn them down if possible
2614 */
2615 struct hda_codec *codec;
2616 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2617 snd_hda_power_down(codec);
2618 }
2619#endif
2620}
2621
d01ce99f
TI		 2622static int __devinit azx_probe(struct pci_dev *pci,
2623 const struct pci_device_id *pci_id)
1da177e4 2624{
5aba4f8e 2625 static int dev;
a98f90fd
TI		 2626 struct snd_card *card;
2627 struct azx *chip;
927fc866 2628 int err;
1da177e4 2629
5aba4f8e
TI		 2630 if (dev >= SNDRV_CARDS)
2631 return -ENODEV;
2632 if (!enable[dev]) {
2633 dev++;
2634 return -ENOENT;
2635 }
2636
e58de7ba
TI		 2637 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2638 if (err < 0) {
1da177e4 2639 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 2640 return err;
1da177e4
LT		 2641 }
2642
4ea6fbc8
TI		 2643 /* set this here since it's referred in snd_hda_load_patch() */
2644 snd_card_set_dev(card, &pci->dev);
2645
5aba4f8e 2646 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2647 if (err < 0)
2648 goto out_free;
421a1252 2649 card->private_data = chip;
1da177e4 2650
2dca0bba
JK		 2651#ifdef CONFIG_SND_HDA_INPUT_BEEP
2652 chip->beep_mode = beep_mode[dev];
2653#endif
2654
1da177e4 2655 /* create codec instances */
a1e21c90 2656 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 2657 if (err < 0)
2658 goto out_free;
4ea6fbc8
TI		 2659#ifdef CONFIG_SND_HDA_PATCH_LOADER
2660 if (patch[dev]) {
2661 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2662 patch[dev]);
2663 err = snd_hda_load_patch(chip->bus, patch[dev]);
2664 if (err < 0)
2665 goto out_free;
2666 }
2667#endif
a1e21c90
TI		 2668 if (!probe_only[dev]) {
2669 err = azx_codec_configure(chip);
2670 if (err < 0)
2671 goto out_free;
2672 }
1da177e4
LT		 2673
2674 /* create PCM streams */
176d5335 2675 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 2676 if (err < 0)
2677 goto out_free;
1da177e4
LT		 2678
2679 /* create mixer controls */
d01ce99f 2680 err = azx_mixer_create(chip);
41dda0fd
WF		 2681 if (err < 0)
2682 goto out_free;
1da177e4 2683
d01ce99f 2684 err = snd_card_register(card);
41dda0fd
WF		 2685 if (err < 0)
2686 goto out_free;
1da177e4
LT		 2687
2688 pci_set_drvdata(pci, card);
cb53c626
TI		 2689 chip->running = 1;
2690 power_down_all_codecs(chip);
0cbf0098 2691 azx_notifier_register(chip);
1da177e4 2692
e25bcdba 2693 dev++;
1da177e4 2694 return err;
41dda0fd
WF		 2695out_free:
2696 snd_card_free(card);
2697 return err;
1da177e4
LT		 2698}
2699
2700static void __devexit azx_remove(struct pci_dev *pci)
2701{
2702 snd_card_free(pci_get_drvdata(pci));
2703 pci_set_drvdata(pci, NULL);
2704}
2705
2706/* PCI IDs */
cebe41d4 2707static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
87218e9c
TI		 2708 /* ICH 6..10 */
2709 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2710 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2711 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2712 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
abbc9d1b 2713 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2714 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2715 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2716 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2717 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
b29c2360
SH		 2718 /* PCH */
2719 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
c602c8ad 2720 { PCI_DEVICE(0x8086, 0x3b57), .driver_data = AZX_DRIVER_ICH },
d2f2fcd2 2721 /* CPT */
32679f95 2722 { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
87218e9c
TI		 2723 /* SCH */
2724 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2725 /* ATI SB 450/600 */
2726 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2727 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2728 /* ATI HDMI */
2729 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2730 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2731 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
9e6dd47b 2732 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
87218e9c
TI		 2733 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2734 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2735 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2736 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2737 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2738 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2739 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2740 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2741 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2742 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2743 /* VIA VT8251/VT8237A */
2744 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2745 /* SIS966 */
2746 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2747 /* ULI M5461 */
2748 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2749 /* NVIDIA MCP */
0c2fd1bf
TI		 2750 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2751 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2752 .class_mask = 0xffffff,
2753 .driver_data = AZX_DRIVER_NVIDIA },
f269002e
KY		 2754 /* Teradici */
2755 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
4e01f54b 2756 /* Creative X-Fi (CA0110-IBG) */
313f6e2d
TI		 2757#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2758 /* the following entry conflicts with snd-ctxfi driver,
2759 * as ctxfi driver mutates from HD-audio to native mode with
2760 * a special command sequence.
2761 */
4e01f54b
TI		 2762 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2763 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2764 .class_mask = 0xffffff,
2765 .driver_data = AZX_DRIVER_GENERIC },
313f6e2d
TI		 2766#else
2767 /* this entry seems still valid -- i.e. without emu20kx chip */
2768 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2769#endif
9176b672 2770 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2771 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2772 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2773 .class_mask = 0xffffff,
2774 .driver_data = AZX_DRIVER_GENERIC },
9176b672
AB		 2775 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2776 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2777 .class_mask = 0xffffff,
2778 .driver_data = AZX_DRIVER_GENERIC },
1da177e4
LT		 2779 { 0, }
2780};
2781MODULE_DEVICE_TABLE(pci, azx_ids);
2782
2783/* pci_driver definition */
2784static struct pci_driver driver = {
2785 .name = "HDA Intel",
2786 .id_table = azx_ids,
2787 .probe = azx_probe,
2788 .remove = __devexit_p(azx_remove),
421a1252
TI		 2789#ifdef CONFIG_PM
2790 .suspend = azx_suspend,
2791 .resume = azx_resume,
2792#endif
1da177e4
LT		 2793};
2794
2795static int __init alsa_card_azx_init(void)
2796{
01d25d46 2797 return pci_register_driver(&driver);
1da177e4
LT		 2798}
2799
2800static void __exit alsa_card_azx_exit(void)
2801{
2802 pci_unregister_driver(&driver);
2803}
2804
2805module_init(alsa_card_azx_init)
2806module_exit(alsa_card_azx_exit)
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