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ALSA: hda: export struct hda_intel
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
9121947d 60#include <linux/vgaarb.h>
a82d51ed 61#include <linux/vga_switcheroo.h>
4918cdab 62#include <linux/firmware.h>
1da177e4 63#include "hda_codec.h"
05e84878 64#include "hda_controller.h"
2538a4f5 65#include "hda_priv.h"
347de1f8 66#include "hda_intel.h"
1da177e4 67
b6050ef6
TI		 68/* position fix mode */
69enum {
70 POS_FIX_AUTO,
71 POS_FIX_LPIB,
72 POS_FIX_POSBUF,
73 POS_FIX_VIACOMBO,
74 POS_FIX_COMBO,
75};
76
9a34af4a
TI		 77/* Defines for ATI HD Audio support in SB450 south bridge */
78#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
79#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
80
81/* Defines for Nvidia HDA support */
82#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
83#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
84#define NVIDIA_HDA_ISTRM_COH 0x4d
85#define NVIDIA_HDA_OSTRM_COH 0x4c
86#define NVIDIA_HDA_ENABLE_COHBIT 0x01
87
88/* Defines for Intel SCH HDA snoop control */
89#define INTEL_SCH_HDA_DEVC 0x78
90#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
91
92/* Define IN stream 0 FIFO size offset in VIA controller */
93#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
94/* Define VIA HD Audio Device ID*/
95#define VIA_HDAC_DEVICE_ID 0x3288
96
33124929
TI		 97/* max number of SDs */
98/* ICH, ATI and VIA have 4 playback and 4 capture */
99#define ICH6_NUM_CAPTURE 4
100#define ICH6_NUM_PLAYBACK 4
101
102/* ULI has 6 playback and 5 capture */
103#define ULI_NUM_CAPTURE 5
104#define ULI_NUM_PLAYBACK 6
105
106/* ATI HDMI may have up to 8 playbacks and 0 capture */
107#define ATIHDMI_NUM_CAPTURE 0
108#define ATIHDMI_NUM_PLAYBACK 8
109
110/* TERA has 4 playback and 3 capture */
111#define TERA_NUM_CAPTURE 3
112#define TERA_NUM_PLAYBACK 4
113
1da177e4 114
5aba4f8e
TI		 115static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
116static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 117static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 118static char *model[SNDRV_CARDS];
1dac6695 119static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 120static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 121static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 122static int probe_only[SNDRV_CARDS];
26a6cb6c 123static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 124static bool single_cmd;
71623855 125static int enable_msi = -1;
4ea6fbc8
TI		 126#ifdef CONFIG_SND_HDA_PATCH_LOADER
127static char *patch[SNDRV_CARDS];
128#endif
2dca0bba 129#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 130static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 131 CONFIG_SND_HDA_INPUT_BEEP_MODE};
132#endif
1da177e4 133
5aba4f8e 134module_param_array(index, int, NULL, 0444);
1da177e4 135MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 136module_param_array(id, charp, NULL, 0444);
1da177e4 137MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 138module_param_array(enable, bool, NULL, 0444);
139MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
140module_param_array(model, charp, NULL, 0444);
1da177e4 141MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 142module_param_array(position_fix, int, NULL, 0444);
4cb36310 143MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 144 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 145module_param_array(bdl_pos_adj, int, NULL, 0644);
146MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 147module_param_array(probe_mask, int, NULL, 0444);
606ad75f 148MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 149module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 150MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 151module_param_array(jackpoll_ms, int, NULL, 0444);
152MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 153module_param(single_cmd, bool, 0444);
d01ce99f
TI		 154MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
155 "(for debugging only).");
ac9ef6cf 156module_param(enable_msi, bint, 0444);
134a11f0 157MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 158#ifdef CONFIG_SND_HDA_PATCH_LOADER
159module_param_array(patch, charp, NULL, 0444);
160MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
161#endif
2dca0bba 162#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 163module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 164MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 165 "(0=off, 1=on) (default=1).");
2dca0bba 166#endif
606ad75f 167
83012a7c 168#ifdef CONFIG_PM
65fcd41d
TI		 169static int param_set_xint(const char *val, const struct kernel_param *kp);
170static struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
173};
174#define param_check_xint param_check_int
175
fee2fba3 176static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
e62a42ae 177static int *power_save_addr = &power_save;
65fcd41d 178module_param(power_save, xint, 0644);
fee2fba3
TI		 179MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
180 "(in second, 0 = disable).");
1da177e4 181
dee1b66c
TI		 182/* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
8fc24426
TI		 186static bool power_save_controller = 1;
187module_param(power_save_controller, bool, 0644);
dee1b66c 188MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae
DR		 189#else
190static int *power_save_addr;
83012a7c 191#endif /* CONFIG_PM */
dee1b66c 192
7bfe059e
TI		 193static int align_buffer_size = -1;
194module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 195MODULE_PARM_DESC(align_buffer_size,
196 "Force buffer and period sizes to be multiple of 128 bytes.");
197
27fe48d9 198#ifdef CONFIG_X86
7c732015
TI		 199static int hda_snoop = -1;
200module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 201MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 202#else
203#define hda_snoop true
27fe48d9
TI		 204#endif
205
206
1da177e4
LT		 207MODULE_LICENSE("GPL");
208MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
209 "{Intel, ICH6M},"
2f1b3818 210 "{Intel, ICH7},"
f5d40b30 211 "{Intel, ESB2},"
d2981393 212 "{Intel, ICH8},"
f9cc8a8b 213 "{Intel, ICH9},"
c34f5a04 214 "{Intel, ICH10},"
b29c2360 215 "{Intel, PCH},"
d2f2fcd2 216 "{Intel, CPT},"
d2edeb7c 217 "{Intel, PPT},"
8bc039a1 218 "{Intel, LPT},"
144dad99 219 "{Intel, LPT_LP},"
4eeca499 220 "{Intel, WPT_LP},"
c8b00fd2 221 "{Intel, SPT},"
b4565913 222 "{Intel, SPT_LP},"
e926f2c8 223 "{Intel, HPT},"
cea310e8 224 "{Intel, PBG},"
4979bca9 225 "{Intel, SCH},"
fc20a562 226 "{ATI, SB450},"
89be83f8 227 "{ATI, SB600},"
778b6e1b 228 "{ATI, RS600},"
5b15c95f 229 "{ATI, RS690},"
e6db1119
WL		 230 "{ATI, RS780},"
231 "{ATI, R600},"
2797f724
HRK		 232 "{ATI, RV630},"
233 "{ATI, RV610},"
27da1834
WL		 234 "{ATI, RV670},"
235 "{ATI, RV635},"
236 "{ATI, RV620},"
237 "{ATI, RV770},"
fc20a562 238 "{VIA, VT8251},"
47672310 239 "{VIA, VT8237A},"
07e4ca50
TI		 240 "{SiS, SIS966},"
241 "{ULI, M5461}}");
1da177e4
LT		 242MODULE_DESCRIPTION("Intel HDA driver");
243
a82d51ed 244#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 245#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 246#define SUPPORT_VGA_SWITCHEROO
247#endif
248#endif
249
250
1da177e4 251/*
1da177e4 252 */
1da177e4 253
07e4ca50
TI		 254/* driver types */
255enum {
256 AZX_DRIVER_ICH,
32679f95 257 AZX_DRIVER_PCH,
4979bca9 258 AZX_DRIVER_SCH,
fab1285a 259 AZX_DRIVER_HDMI,
07e4ca50 260 AZX_DRIVER_ATI,
778b6e1b 261 AZX_DRIVER_ATIHDMI,
1815b34a 262 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 263 AZX_DRIVER_VIA,
264 AZX_DRIVER_SIS,
265 AZX_DRIVER_ULI,
da3fca21 266 AZX_DRIVER_NVIDIA,
f269002e 267 AZX_DRIVER_TERA,
14d34f16 268 AZX_DRIVER_CTX,
5ae763b1 269 AZX_DRIVER_CTHDA,
c563f473 270 AZX_DRIVER_CMEDIA,
c4da29ca 271 AZX_DRIVER_GENERIC,
2f5983f2 272 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 273};
274
37e661ee
TI		 275#define azx_get_snoop_type(chip) \
276 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
277#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
278
b42b4afb
TI		 279/* quirks for old Intel chipsets */
280#define AZX_DCAPS_INTEL_ICH \
103884a3 281 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 282
2ea3c6a2 283/* quirks for Intel PCH */
d7dab4db 284#define AZX_DCAPS_INTEL_PCH_NOPM \
103884a3 285 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee 286 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db
TI		 287
288#define AZX_DCAPS_INTEL_PCH \
289 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 290
33499a15 291#define AZX_DCAPS_INTEL_HASWELL \
103884a3 292 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 293 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
294 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 295
54a0405d
LY		 296/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
297#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 298 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 299 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
300 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 301
d6795827
LY		 302#define AZX_DCAPS_INTEL_SKYLAKE \
303 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG)
304
9477c58e
TI		 305/* quirks for ATI SB / AMD Hudson */
306#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 307 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
308 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 309
310/* quirks for ATI/AMD HDMI */
311#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 312 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
313 AZX_DCAPS_NO_MSI64)
9477c58e 314
37e661ee
TI		 315/* quirks for ATI HDMI with snoop off */
316#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
317 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
318
9477c58e
TI		 319/* quirks for Nvidia */
320#define AZX_DCAPS_PRESET_NVIDIA \
103884a3 321 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
37e661ee
TI		 322 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
323 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 324
5ae763b1 325#define AZX_DCAPS_PRESET_CTHDA \
37e661ee
TI		 326 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
327 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 328
a82d51ed
TI		 329/*
330 * VGA-switcher support
331 */
332#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 333#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
334#else
335#define use_vga_switcheroo(chip) 0
336#endif
337
48c8b0eb 338static char *driver_short_names[] = {
07e4ca50 339 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 340 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 341 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 342 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 343 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 344 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 345 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 346 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
347 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 348 [AZX_DRIVER_ULI] = "HDA ULI M5461",
349 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 350 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 351 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 352 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 353 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 354 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 355};
356
27fe48d9 357#ifdef CONFIG_X86
9ddf1aeb 358static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 359{
9ddf1aeb
TI		 360 int pages;
361
27fe48d9
TI		 362 if (azx_snoop(chip))
363 return;
9ddf1aeb
TI		 364 if (!dmab || !dmab->area || !dmab->bytes)
365 return;
366
367#ifdef CONFIG_SND_DMA_SGBUF
368 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
369 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 370 if (chip->driver_type == AZX_DRIVER_CMEDIA)
371 return; /* deal with only CORB/RIRB buffers */
27fe48d9 372 if (on)
9ddf1aeb 373 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 374 else
9ddf1aeb
TI		 375 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
376 return;
27fe48d9 377 }
9ddf1aeb
TI		 378#endif
379
380 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
381 if (on)
382 set_memory_wc((unsigned long)dmab->area, pages);
383 else
384 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 385}
386
387static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
388 bool on)
389{
9ddf1aeb 390 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 391}
392static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 393 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 394{
395 if (azx_dev->wc_marked != on) {
9ddf1aeb 396 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 397 azx_dev->wc_marked = on;
398 }
399}
400#else
401/* NOP for other archs */
402static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
403 bool on)
404{
405}
406static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 407 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 408{
409}
410#endif
411
68e7fffc 412static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 413
cb53c626
TI		 414/*
415 * initialize the PCI registers
416 */
417/* update bits in a PCI register byte */
418static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
419 unsigned char mask, unsigned char val)
420{
421 unsigned char data;
422
423 pci_read_config_byte(pci, reg, &data);
424 data &= ~mask;
425 data |= (val & mask);
426 pci_write_config_byte(pci, reg, data);
427}
428
429static void azx_init_pci(struct azx *chip)
430{
37e661ee
TI		 431 int snoop_type = azx_get_snoop_type(chip);
432
cb53c626
TI		 433 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
434 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
435 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 436 * codecs.
437 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 438 */
46f2cc80 439 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 440 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 441 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 442 }
cb53c626 443
9477c58e
TI		 444 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
445 * we need to enable snoop.
446 */
37e661ee 447 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 448 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
449 azx_snoop(chip));
cb53c626 450 update_pci_byte(chip->pci,
27fe48d9
TI		 451 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
452 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 453 }
454
455 /* For NVIDIA HDA, enable snoop */
37e661ee 456 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 457 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
458 azx_snoop(chip));
cb53c626
TI		 459 update_pci_byte(chip->pci,
460 NVIDIA_HDA_TRANSREG_ADDR,
461 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 462 update_pci_byte(chip->pci,
463 NVIDIA_HDA_ISTRM_COH,
464 0x01, NVIDIA_HDA_ENABLE_COHBIT);
465 update_pci_byte(chip->pci,
466 NVIDIA_HDA_OSTRM_COH,
467 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 468 }
469
470 /* Enable SCH/PCH snoop if needed */
37e661ee 471 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 472 unsigned short snoop;
90a5ad52 473 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 474 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
475 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
476 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
477 if (!azx_snoop(chip))
478 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
479 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 480 pci_read_config_word(chip->pci,
481 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 482 }
4e76a883
TI		 483 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
484 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
485 "Disabled" : "Enabled");
da3fca21 486 }
1da177e4
LT		 487}
488
b6050ef6
TI		 489/* calculate runtime delay from LPIB */
490static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
491 unsigned int pos)
492{
493 struct snd_pcm_substream *substream = azx_dev->substream;
494 int stream = substream->stream;
495 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
496 int delay;
497
498 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
499 delay = pos - lpib_pos;
500 else
501 delay = lpib_pos - pos;
502 if (delay < 0) {
503 if (delay >= azx_dev->delay_negative_threshold)
504 delay = 0;
505 else
506 delay += azx_dev->bufsize;
507 }
508
509 if (delay >= azx_dev->period_bytes) {
510 dev_info(chip->card->dev,
511 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
512 delay, azx_dev->period_bytes);
513 delay = 0;
514 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
515 chip->get_delay[stream] = NULL;
516 }
517
518 return bytes_to_frames(substream->runtime, delay);
519}
520
9ad593f6
TI		 521static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
522
7ca954a8
DR		 523/* called from IRQ */
524static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
525{
9a34af4a 526 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 527 int ok;
528
529 ok = azx_position_ok(chip, azx_dev);
530 if (ok == 1) {
531 azx_dev->irq_pending = 0;
532 return ok;
533 } else if (ok == 0 && chip->bus && chip->bus->workq) {
534 /* bogus IRQ, process it later */
535 azx_dev->irq_pending = 1;
9a34af4a 536 queue_work(chip->bus->workq, &hda->irq_pending_work);
7ca954a8
DR		 537 }
538 return 0;
539}
540
9ad593f6
TI		 541/*
542 * Check whether the current DMA position is acceptable for updating
543 * periods. Returns non-zero if it's OK.
544 *
545 * Many HD-audio controllers appear pretty inaccurate about
546 * the update-IRQ timing. The IRQ is issued before actually the
547 * data is processed. So, we need to process it afterwords in a
548 * workqueue.
549 */
550static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
551{
b6050ef6
TI		 552 struct snd_pcm_substream *substream = azx_dev->substream;
553 int stream = substream->stream;
e5463720 554 u32 wallclk;
9ad593f6
TI		 555 unsigned int pos;
556
f48f606d
JK		 557 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
558 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 559 return -1; /* bogus (too early) interrupt */
fa00e046 560
b6050ef6
TI		 561 if (chip->get_position[stream])
562 pos = chip->get_position[stream](chip, azx_dev);
563 else { /* use the position buffer as default */
564 pos = azx_get_pos_posbuf(chip, azx_dev);
565 if (!pos || pos == (u32)-1) {
566 dev_info(chip->card->dev,
567 "Invalid position buffer, using LPIB read method instead.\n");
568 chip->get_position[stream] = azx_get_pos_lpib;
569 pos = azx_get_pos_lpib(chip, azx_dev);
570 chip->get_delay[stream] = NULL;
571 } else {
572 chip->get_position[stream] = azx_get_pos_posbuf;
573 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
574 chip->get_delay[stream] = azx_get_delay_from_lpib;
575 }
576 }
577
578 if (pos >= azx_dev->bufsize)
579 pos = 0;
9ad593f6 580
d6d8bf54
TI		 581 if (WARN_ONCE(!azx_dev->period_bytes,
582 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 583 return -1; /* this shouldn't happen! */
edb39935 584 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 585 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
586 /* NG - it's below the first next period boundary */
9cdc0115 587 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 588 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 589 return 1; /* OK, it's fine */
590}
591
592/*
593 * The work for pending PCM period updates.
594 */
595static void azx_irq_pending_work(struct work_struct *work)
596{
9a34af4a
TI		 597 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
598 struct azx *chip = &hda->chip;
e5463720 599 int i, pending, ok;
9ad593f6 600
9a34af4a 601 if (!hda->irq_pending_warned) {
4e76a883
TI		 602 dev_info(chip->card->dev,
603 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
604 chip->card->number);
9a34af4a 605 hda->irq_pending_warned = 1;
a6a950a8
TI		 606 }
607
9ad593f6
TI		 608 for (;;) {
609 pending = 0;
610 spin_lock_irq(&chip->reg_lock);
611 for (i = 0; i < chip->num_streams; i++) {
612 struct azx_dev *azx_dev = &chip->azx_dev[i];
613 if (!azx_dev->irq_pending ||
614 !azx_dev->substream ||
615 !azx_dev->running)
616 continue;
e5463720
JK		 617 ok = azx_position_ok(chip, azx_dev);
618 if (ok > 0) {
9ad593f6
TI		 619 azx_dev->irq_pending = 0;
620 spin_unlock(&chip->reg_lock);
621 snd_pcm_period_elapsed(azx_dev->substream);
622 spin_lock(&chip->reg_lock);
e5463720
JK		 623 } else if (ok < 0) {
624 pending = 0; /* too early */
9ad593f6
TI		 625 } else
626 pending++;
627 }
628 spin_unlock_irq(&chip->reg_lock);
629 if (!pending)
630 return;
08af495f 631 msleep(1);
9ad593f6
TI		 632 }
633}
634
635/* clear irq_pending flags and assure no on-going workq */
636static void azx_clear_irq_pending(struct azx *chip)
637{
638 int i;
639
640 spin_lock_irq(&chip->reg_lock);
641 for (i = 0; i < chip->num_streams; i++)
642 chip->azx_dev[i].irq_pending = 0;
643 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 644}
645
68e7fffc
TI		 646static int azx_acquire_irq(struct azx *chip, int do_disconnect)
647{
437a5a46
TI		 648 if (request_irq(chip->pci->irq, azx_interrupt,
649 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 650 KBUILD_MODNAME, chip)) {
4e76a883
TI		 651 dev_err(chip->card->dev,
652 "unable to grab IRQ %d, disabling device\n",
653 chip->pci->irq);
68e7fffc
TI		 654 if (do_disconnect)
655 snd_card_disconnect(chip->card);
656 return -1;
657 }
658 chip->irq = chip->pci->irq;
69e13418 659 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 660 return 0;
661}
662
b6050ef6
TI		 663/* get the current DMA position with correction on VIA chips */
664static unsigned int azx_via_get_position(struct azx *chip,
665 struct azx_dev *azx_dev)
666{
667 unsigned int link_pos, mini_pos, bound_pos;
668 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
669 unsigned int fifo_size;
670
671 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
672 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
673 /* Playback, no problem using link position */
674 return link_pos;
675 }
676
677 /* Capture */
678 /* For new chipset,
679 * use mod to get the DMA position just like old chipset
680 */
681 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
682 mod_dma_pos %= azx_dev->period_bytes;
683
684 /* azx_dev->fifo_size can't get FIFO size of in stream.
685 * Get from base address + offset.
686 */
687 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
688
689 if (azx_dev->insufficient) {
690 /* Link position never gather than FIFO size */
691 if (link_pos <= fifo_size)
692 return 0;
693
694 azx_dev->insufficient = 0;
695 }
696
697 if (link_pos <= fifo_size)
698 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
699 else
700 mini_pos = link_pos - fifo_size;
701
702 /* Find nearest previous boudary */
703 mod_mini_pos = mini_pos % azx_dev->period_bytes;
704 mod_link_pos = link_pos % azx_dev->period_bytes;
705 if (mod_link_pos >= fifo_size)
706 bound_pos = link_pos - mod_link_pos;
707 else if (mod_dma_pos >= mod_mini_pos)
708 bound_pos = mini_pos - mod_mini_pos;
709 else {
710 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
711 if (bound_pos >= azx_dev->bufsize)
712 bound_pos = 0;
713 }
714
715 /* Calculate real DMA position we want */
716 return bound_pos + mod_dma_pos;
717}
718
83012a7c 719#ifdef CONFIG_PM
65fcd41d
TI		 720static DEFINE_MUTEX(card_list_lock);
721static LIST_HEAD(card_list);
722
723static void azx_add_card_list(struct azx *chip)
724{
9a34af4a 725 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 726 mutex_lock(&card_list_lock);
9a34af4a 727 list_add(&hda->list, &card_list);
65fcd41d
TI		 728 mutex_unlock(&card_list_lock);
729}
730
731static void azx_del_card_list(struct azx *chip)
732{
9a34af4a 733 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 734 mutex_lock(&card_list_lock);
9a34af4a 735 list_del_init(&hda->list);
65fcd41d
TI		 736 mutex_unlock(&card_list_lock);
737}
738
739/* trigger power-save check at writing parameter */
740static int param_set_xint(const char *val, const struct kernel_param *kp)
741{
9a34af4a 742 struct hda_intel *hda;
65fcd41d
TI		 743 struct azx *chip;
744 struct hda_codec *c;
745 int prev = power_save;
746 int ret = param_set_int(val, kp);
747
748 if (ret || prev == power_save)
749 return ret;
750
751 mutex_lock(&card_list_lock);
9a34af4a
TI		 752 list_for_each_entry(hda, &card_list, list) {
753 chip = &hda->chip;
65fcd41d
TI		 754 if (!chip->bus || chip->disabled)
755 continue;
756 list_for_each_entry(c, &chip->bus->codec_list, list)
757 snd_hda_power_sync(c);
758 }
759 mutex_unlock(&card_list_lock);
760 return 0;
761}
762#else
763#define azx_add_card_list(chip) /* NOP */
764#define azx_del_card_list(chip) /* NOP */
83012a7c 765#endif /* CONFIG_PM */
5c0b9bec 766
7ccbde57 767#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 768/*
769 * power management
770 */
68cb2b55 771static int azx_suspend(struct device *dev)
1da177e4 772{
68cb2b55
TI		 773 struct pci_dev *pci = to_pci_dev(dev);
774 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 775 struct azx *chip;
776 struct hda_intel *hda;
01b65bfb 777 struct azx_pcm *p;
1da177e4 778
2d9772ef
TI		 779 if (!card)
780 return 0;
781
782 chip = card->private_data;
783 hda = container_of(chip, struct hda_intel, chip);
1618e84a 784 if (chip->disabled || hda->init_failed)
c5c21523
TI		 785 return 0;
786
421a1252 787 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 788 azx_clear_irq_pending(chip);
01b65bfb
TI		 789 list_for_each_entry(p, &chip->pcm_list, list)
790 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 791 if (chip->initialized)
8dd78330 792 snd_hda_suspend(chip->bus);
cb53c626 793 azx_stop_chip(chip);
7295b264 794 azx_enter_link_reset(chip);
30b35399 795 if (chip->irq >= 0) {
43001c95 796 free_irq(chip->irq, chip);
30b35399
TI		 797 chip->irq = -1;
798 }
a07187c9 799
68e7fffc 800 if (chip->msi)
43001c95 801 pci_disable_msi(chip->pci);
421a1252
TI		 802 pci_disable_device(pci);
803 pci_save_state(pci);
68cb2b55 804 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 805 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
806 hda_display_power(false);
1da177e4
LT		 807 return 0;
808}
809
68cb2b55 810static int azx_resume(struct device *dev)
1da177e4 811{
68cb2b55
TI		 812 struct pci_dev *pci = to_pci_dev(dev);
813 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 814 struct azx *chip;
815 struct hda_intel *hda;
816
817 if (!card)
818 return 0;
1da177e4 819
2d9772ef
TI		 820 chip = card->private_data;
821 hda = container_of(chip, struct hda_intel, chip);
1618e84a 822 if (chip->disabled || hda->init_failed)
c5c21523
TI		 823 return 0;
824
a07187c9 825 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
99a2008d 826 hda_display_power(true);
e4d9e513 827 haswell_set_bclk(chip);
a07187c9 828 }
d14a7e0b
TI		 829 pci_set_power_state(pci, PCI_D0);
830 pci_restore_state(pci);
30b35399 831 if (pci_enable_device(pci) < 0) {
4e76a883
TI		 832 dev_err(chip->card->dev,
833 "pci_enable_device failed, disabling device\n");
30b35399
TI		 834 snd_card_disconnect(card);
835 return -EIO;
836 }
837 pci_set_master(pci);
68e7fffc
TI		 838 if (chip->msi)
839 if (pci_enable_msi(pci) < 0)
840 chip->msi = 0;
841 if (azx_acquire_irq(chip, 1) < 0)
30b35399 842 return -EIO;
cb53c626 843 azx_init_pci(chip);
d804ad92 844
17c3ad03 845 azx_init_chip(chip, true);
d804ad92 846
1da177e4 847 snd_hda_resume(chip->bus);
421a1252 848 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 849 return 0;
850}
b8dfc462
ML		 851#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
852
641d334b 853#ifdef CONFIG_PM
b8dfc462
ML		 854static int azx_runtime_suspend(struct device *dev)
855{
856 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 857 struct azx *chip;
858 struct hda_intel *hda;
b8dfc462 859
2d9772ef
TI		 860 if (!card)
861 return 0;
862
863 chip = card->private_data;
864 hda = container_of(chip, struct hda_intel, chip);
1618e84a 865 if (chip->disabled || hda->init_failed)
246efa4a
DA		 866 return 0;
867
868 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
869 return 0;
870
7d4f606c
WX		 871 /* enable controller wake up event */
872 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
873 STATESTS_INT_MASK);
874
b8dfc462 875 azx_stop_chip(chip);
873ce8ad 876 azx_enter_link_reset(chip);
b8dfc462 877 azx_clear_irq_pending(chip);
e4d9e513 878 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
99a2008d 879 hda_display_power(false);
e4d9e513 880
b8dfc462
ML		 881 return 0;
882}
883
884static int azx_runtime_resume(struct device *dev)
885{
886 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 887 struct azx *chip;
888 struct hda_intel *hda;
7d4f606c
WX		 889 struct hda_bus *bus;
890 struct hda_codec *codec;
891 int status;
b8dfc462 892
2d9772ef
TI		 893 if (!card)
894 return 0;
895
896 chip = card->private_data;
897 hda = container_of(chip, struct hda_intel, chip);
1618e84a 898 if (chip->disabled || hda->init_failed)
246efa4a
DA		 899 return 0;
900
901 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
902 return 0;
903
a07187c9 904 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
99a2008d 905 hda_display_power(true);
e4d9e513 906 haswell_set_bclk(chip);
a07187c9 907 }
7d4f606c
WX		 908
909 /* Read STATESTS before controller reset */
910 status = azx_readw(chip, STATESTS);
911
b8dfc462 912 azx_init_pci(chip);
17c3ad03 913 azx_init_chip(chip, true);
7d4f606c
WX		 914
915 bus = chip->bus;
916 if (status && bus) {
917 list_for_each_entry(codec, &bus->codec_list, list)
918 if (status & (1 << codec->addr))
919 queue_delayed_work(codec->bus->workq,
920 &codec->jackpoll_work, codec->jackpoll_interval);
921 }
922
923 /* disable controller Wake Up event*/
924 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
925 ~STATESTS_INT_MASK);
926
b8dfc462
ML		 927 return 0;
928}
6eb827d2
TI		 929
930static int azx_runtime_idle(struct device *dev)
931{
932 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 933 struct azx *chip;
934 struct hda_intel *hda;
935
936 if (!card)
937 return 0;
6eb827d2 938
2d9772ef
TI		 939 chip = card->private_data;
940 hda = container_of(chip, struct hda_intel, chip);
1618e84a 941 if (chip->disabled || hda->init_failed)
246efa4a
DA		 942 return 0;
943
6eb827d2
TI		 944 if (!power_save_controller ||
945 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
946 return -EBUSY;
947
948 return 0;
949}
950
b8dfc462
ML		 951static const struct dev_pm_ops azx_pm = {
952 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 953 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 954};
955
68cb2b55
TI		 956#define AZX_PM_OPS &azx_pm
957#else
68cb2b55 958#define AZX_PM_OPS NULL
b8dfc462 959#endif /* CONFIG_PM */
1da177e4
LT		 960
961
48c8b0eb 962static int azx_probe_continue(struct azx *chip);
a82d51ed 963
8393ec4a 964#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 965static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 966
a82d51ed
TI		 967static void azx_vs_set_state(struct pci_dev *pci,
968 enum vga_switcheroo_state state)
969{
970 struct snd_card *card = pci_get_drvdata(pci);
971 struct azx *chip = card->private_data;
9a34af4a 972 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 973 bool disabled;
974
9a34af4a
TI		 975 wait_for_completion(&hda->probe_wait);
976 if (hda->init_failed)
a82d51ed
TI		 977 return;
978
979 disabled = (state == VGA_SWITCHEROO_OFF);
980 if (chip->disabled == disabled)
981 return;
982
983 if (!chip->bus) {
984 chip->disabled = disabled;
985 if (!disabled) {
4e76a883
TI		 986 dev_info(chip->card->dev,
987 "Start delayed initialization\n");
5c90680e 988 if (azx_probe_continue(chip) < 0) {
4e76a883 989 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 990 hda->init_failed = true;
a82d51ed
TI		 991 }
992 }
993 } else {
4e76a883
TI		 994 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
995 disabled ? "Disabling" : "Enabling");
a82d51ed 996 if (disabled) {
8928756d
DR		 997 pm_runtime_put_sync_suspend(card->dev);
998 azx_suspend(card->dev);
246efa4a
DA		 999 /* when we get suspended by vga switcheroo we end up in D3cold,
1000 * however we have no ACPI handle, so pci/acpi can't put us there,
1001 * put ourselves there */
1002 pci->current_state = PCI_D3cold;
a82d51ed 1003 chip->disabled = true;
128960a9 1004 if (snd_hda_lock_devices(chip->bus))
4e76a883
TI		 1005 dev_warn(chip->card->dev,
1006 "Cannot lock devices!\n");
a82d51ed
TI		 1007 } else {
1008 snd_hda_unlock_devices(chip->bus);
8928756d 1009 pm_runtime_get_noresume(card->dev);
a82d51ed 1010 chip->disabled = false;
8928756d 1011 azx_resume(card->dev);
a82d51ed
TI		 1012 }
1013 }
1014}
1015
1016static bool azx_vs_can_switch(struct pci_dev *pci)
1017{
1018 struct snd_card *card = pci_get_drvdata(pci);
1019 struct azx *chip = card->private_data;
9a34af4a 1020 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1021
9a34af4a
TI		 1022 wait_for_completion(&hda->probe_wait);
1023 if (hda->init_failed)
a82d51ed
TI		 1024 return false;
1025 if (chip->disabled || !chip->bus)
1026 return true;
1027 if (snd_hda_lock_devices(chip->bus))
1028 return false;
1029 snd_hda_unlock_devices(chip->bus);
1030 return true;
1031}
1032
e23e7a14 1033static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1034{
9a34af4a 1035 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1036 struct pci_dev *p = get_bound_vga(chip->pci);
1037 if (p) {
4e76a883
TI		 1038 dev_info(chip->card->dev,
1039 "Handle VGA-switcheroo audio client\n");
9a34af4a 1040 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1041 pci_dev_put(p);
1042 }
1043}
1044
1045static const struct vga_switcheroo_client_ops azx_vs_ops = {
1046 .set_gpu_state = azx_vs_set_state,
1047 .can_switch = azx_vs_can_switch,
1048};
1049
e23e7a14 1050static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1051{
9a34af4a 1052 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1053 int err;
1054
9a34af4a 1055 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1056 return 0;
1057 /* FIXME: currently only handling DIS controller
1058 * is there any machine with two switchable HDMI audio controllers?
1059 */
128960a9 1060 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 1061 VGA_SWITCHEROO_DIS,
1062 chip->bus != NULL);
128960a9
TI		 1063 if (err < 0)
1064 return err;
9a34af4a 1065 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1066
1067 /* register as an optimus hdmi audio power domain */
8928756d 1068 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1069 &hda->hdmi_pm_domain);
128960a9 1070 return 0;
a82d51ed
TI		 1071}
1072#else
1073#define init_vga_switcheroo(chip) /* NOP */
1074#define register_vga_switcheroo(chip) 0
8393ec4a 1075#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1076#endif /* SUPPORT_VGA_SWITCHER */
1077
1da177e4
LT		 1078/*
1079 * destructor
1080 */
a98f90fd 1081static int azx_free(struct azx *chip)
1da177e4 1082{
c67e2228 1083 struct pci_dev *pci = chip->pci;
a07187c9 1084 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4ce107b9
TI		 1085 int i;
1086
c67e2228
WX		 1087 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1088 && chip->running)
1089 pm_runtime_get_noresume(&pci->dev);
1090
65fcd41d
TI		 1091 azx_del_card_list(chip);
1092
0cbf0098
TI		 1093 azx_notifier_unregister(chip);
1094
9a34af4a
TI		 1095 hda->init_failed = 1; /* to be sure */
1096 complete_all(&hda->probe_wait);
f4c482a4 1097
9a34af4a 1098 if (use_vga_switcheroo(hda)) {
a82d51ed
TI		 1099 if (chip->disabled && chip->bus)
1100 snd_hda_unlock_devices(chip->bus);
9a34af4a 1101 if (hda->vga_switcheroo_registered)
128960a9 1102 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1103 }
1104
ce43fbae 1105 if (chip->initialized) {
9ad593f6 1106 azx_clear_irq_pending(chip);
07e4ca50 1107 for (i = 0; i < chip->num_streams; i++)
1da177e4 1108 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 1109 azx_stop_chip(chip);
1da177e4
LT		 1110 }
1111
f000fd80 1112 if (chip->irq >= 0)
1da177e4 1113 free_irq(chip->irq, (void*)chip);
68e7fffc 1114 if (chip->msi)
30b35399 1115 pci_disable_msi(chip->pci);
f079c25a
TI		 1116 if (chip->remap_addr)
1117 iounmap(chip->remap_addr);
1da177e4 1118
67908994 1119 azx_free_stream_pages(chip);
a82d51ed
TI		 1120 if (chip->region_requested)
1121 pci_release_regions(chip->pci);
1da177e4 1122 pci_disable_device(chip->pci);
07e4ca50 1123 kfree(chip->azx_dev);
4918cdab 1124#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1125 release_firmware(chip->fw);
4918cdab 1126#endif
99a2008d
WX		 1127 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1128 hda_display_power(false);
1129 hda_i915_exit();
1130 }
a07187c9 1131 kfree(hda);
1da177e4
LT		 1132
1133 return 0;
1134}
1135
a98f90fd 1136static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1137{
1138 return azx_free(device->device_data);
1139}
1140
8393ec4a 1141#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 1142/*
1143 * Check of disabled HDMI controller by vga-switcheroo
1144 */
e23e7a14 1145static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1146{
1147 struct pci_dev *p;
1148
1149 /* check only discrete GPU */
1150 switch (pci->vendor) {
1151 case PCI_VENDOR_ID_ATI:
1152 case PCI_VENDOR_ID_AMD:
1153 case PCI_VENDOR_ID_NVIDIA:
1154 if (pci->devfn == 1) {
1155 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1156 pci->bus->number, 0);
1157 if (p) {
1158 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1159 return p;
1160 pci_dev_put(p);
1161 }
1162 }
1163 break;
1164 }
1165 return NULL;
1166}
1167
e23e7a14 1168static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1169{
1170 bool vga_inactive = false;
1171 struct pci_dev *p = get_bound_vga(pci);
1172
1173 if (p) {
12b78a7f 1174 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1175 vga_inactive = true;
1176 pci_dev_put(p);
1177 }
1178 return vga_inactive;
1179}
8393ec4a 1180#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1181
3372a153
TI		 1182/*
1183 * white/black-listing for position_fix
1184 */
e23e7a14 1185static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1186 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1187 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1188 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1189 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1190 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1191 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1192 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1193 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1194 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1195 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1196 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1197 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1198 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1199 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1200 {}
1201};
1202
e23e7a14 1203static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1204{
1205 const struct snd_pci_quirk *q;
1206
c673ba1c 1207 switch (fix) {
1dac6695 1208 case POS_FIX_AUTO:
c673ba1c
TI		 1209 case POS_FIX_LPIB:
1210 case POS_FIX_POSBUF:
4cb36310 1211 case POS_FIX_VIACOMBO:
a6f2fd55 1212 case POS_FIX_COMBO:
c673ba1c
TI		 1213 return fix;
1214 }
1215
c673ba1c
TI		 1216 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1217 if (q) {
4e76a883
TI		 1218 dev_info(chip->card->dev,
1219 "position_fix set to %d for device %04x:%04x\n",
1220 q->value, q->subvendor, q->subdevice);
c673ba1c 1221 return q->value;
3372a153 1222 }
bdd9ef24
DH		 1223
1224 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1225 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1226 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1227 return POS_FIX_VIACOMBO;
9477c58e
TI		 1228 }
1229 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1230 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1231 return POS_FIX_LPIB;
bdd9ef24 1232 }
c673ba1c 1233 return POS_FIX_AUTO;
3372a153
TI		 1234}
1235
b6050ef6
TI		 1236static void assign_position_fix(struct azx *chip, int fix)
1237{
1238 static azx_get_pos_callback_t callbacks[] = {
1239 [POS_FIX_AUTO] = NULL,
1240 [POS_FIX_LPIB] = azx_get_pos_lpib,
1241 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1242 [POS_FIX_VIACOMBO] = azx_via_get_position,
1243 [POS_FIX_COMBO] = azx_get_pos_lpib,
1244 };
1245
1246 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1247
1248 /* combo mode uses LPIB only for playback */
1249 if (fix == POS_FIX_COMBO)
1250 chip->get_position[1] = NULL;
1251
1252 if (fix == POS_FIX_POSBUF &&
1253 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1254 chip->get_delay[0] = chip->get_delay[1] =
1255 azx_get_delay_from_lpib;
1256 }
1257
1258}
1259
669ba27a
TI		 1260/*
1261 * black-lists for probe_mask
1262 */
e23e7a14 1263static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1264 /* Thinkpad often breaks the controller communication when accessing
1265 * to the non-working (or non-existing) modem codec slot.
1266 */
1267 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1268 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1269 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1270 /* broken BIOS */
1271 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1272 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1273 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1274 /* forced codec slots */
93574844 1275 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1276 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1277 /* WinFast VP200 H (Teradici) user reported broken communication */
1278 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1279 {}
1280};
1281
f1eaaeec
TI		 1282#define AZX_FORCE_CODEC_MASK 0x100
1283
e23e7a14 1284static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1285{
1286 const struct snd_pci_quirk *q;
1287
f1eaaeec
TI		 1288 chip->codec_probe_mask = probe_mask[dev];
1289 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1290 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1291 if (q) {
4e76a883
TI		 1292 dev_info(chip->card->dev,
1293 "probe_mask set to 0x%x for device %04x:%04x\n",
1294 q->value, q->subvendor, q->subdevice);
f1eaaeec 1295 chip->codec_probe_mask = q->value;
669ba27a
TI		 1296 }
1297 }
f1eaaeec
TI		 1298
1299 /* check forced option */
1300 if (chip->codec_probe_mask != -1 &&
1301 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1302 chip->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883
TI		 1303 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1304 chip->codec_mask);
f1eaaeec 1305 }
669ba27a
TI		 1306}
1307
4d8e22e0 1308/*
71623855 1309 * white/black-list for enable_msi
4d8e22e0 1310 */
e23e7a14 1311static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1312 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1313 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1314 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1315 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1316 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1317 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1318 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1319 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1320 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1321 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1322 {}
1323};
1324
e23e7a14 1325static void check_msi(struct azx *chip)
4d8e22e0
TI		 1326{
1327 const struct snd_pci_quirk *q;
1328
71623855
TI		 1329 if (enable_msi >= 0) {
1330 chip->msi = !!enable_msi;
4d8e22e0 1331 return;
71623855
TI		 1332 }
1333 chip->msi = 1; /* enable MSI as default */
1334 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1335 if (q) {
4e76a883
TI		 1336 dev_info(chip->card->dev,
1337 "msi for device %04x:%04x set to %d\n",
1338 q->subvendor, q->subdevice, q->value);
4d8e22e0 1339 chip->msi = q->value;
80c43ed7
TI		 1340 return;
1341 }
1342
1343 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1344 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1345 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1346 chip->msi = 0;
4d8e22e0
TI		 1347 }
1348}
1349
a1585d76 1350/* check the snoop mode availability */
e23e7a14 1351static void azx_check_snoop_available(struct azx *chip)
a1585d76 1352{
7c732015 1353 int snoop = hda_snoop;
a1585d76 1354
7c732015
TI		 1355 if (snoop >= 0) {
1356 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1357 snoop ? "snoop" : "non-snoop");
1358 chip->snoop = snoop;
1359 return;
1360 }
1361
1362 snoop = true;
37e661ee
TI		 1363 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1364 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1365 /* force to non-snoop mode for a new VIA controller
1366 * when BIOS is set
1367 */
7c732015
TI		 1368 u8 val;
1369 pci_read_config_byte(chip->pci, 0x42, &val);
1370 if (!(val & 0x80) && chip->pci->revision == 0x30)
1371 snoop = false;
a1585d76
TI		 1372 }
1373
37e661ee
TI		 1374 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1375 snoop = false;
1376
7c732015
TI		 1377 chip->snoop = snoop;
1378 if (!snoop)
1379 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1380}
669ba27a 1381
99a2008d
WX		 1382static void azx_probe_work(struct work_struct *work)
1383{
9a34af4a
TI		 1384 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1385 azx_probe_continue(&hda->chip);
99a2008d 1386}
99a2008d 1387
1da177e4
LT		 1388/*
1389 * constructor
1390 */
e23e7a14
BP		 1391static int azx_create(struct snd_card *card, struct pci_dev *pci,
1392 int dev, unsigned int driver_caps,
40830813 1393 const struct hda_controller_ops *hda_ops,
e23e7a14 1394 struct azx **rchip)
1da177e4 1395{
a98f90fd 1396 static struct snd_device_ops ops = {
1da177e4
LT		 1397 .dev_free = azx_dev_free,
1398 };
a07187c9 1399 struct hda_intel *hda;
a82d51ed
TI		 1400 struct azx *chip;
1401 int err;
1da177e4
LT		 1402
1403 *rchip = NULL;
bcd72003 1404
927fc866
PM		 1405 err = pci_enable_device(pci);
1406 if (err < 0)
1da177e4
LT		 1407 return err;
1408
a07187c9
ML		 1409 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1410 if (!hda) {
1411 dev_err(card->dev, "Cannot allocate hda\n");
1da177e4
LT		 1412 pci_disable_device(pci);
1413 return -ENOMEM;
1414 }
1415
a07187c9 1416 chip = &hda->chip;
1da177e4 1417 spin_lock_init(&chip->reg_lock);
62932df8 1418 mutex_init(&chip->open_mutex);
1da177e4
LT		 1419 chip->card = card;
1420 chip->pci = pci;
40830813 1421 chip->ops = hda_ops;
1da177e4 1422 chip->irq = -1;
9477c58e
TI		 1423 chip->driver_caps = driver_caps;
1424 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1425 check_msi(chip);
555e219f 1426 chip->dev_index = dev;
749ee287 1427 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1428 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1429 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1430 INIT_LIST_HEAD(&hda->list);
a82d51ed 1431 init_vga_switcheroo(chip);
9a34af4a 1432 init_completion(&hda->probe_wait);
1da177e4 1433
b6050ef6 1434 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1435
5aba4f8e 1436 check_probe_mask(chip, dev);
3372a153 1437
27346166 1438 chip->single_cmd = single_cmd;
a1585d76 1439 azx_check_snoop_available(chip);
c74db86b 1440
5c0d7bc1
TI		 1441 if (bdl_pos_adj[dev] < 0) {
1442 switch (chip->driver_type) {
0c6341ac 1443 case AZX_DRIVER_ICH:
32679f95 1444 case AZX_DRIVER_PCH:
0c6341ac 1445 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1446 break;
1447 default:
0c6341ac 1448 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1449 break;
1450 }
1451 }
9cdc0115 1452 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1453
a82d51ed
TI		 1454 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1455 if (err < 0) {
4e76a883 1456 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1457 azx_free(chip);
1458 return err;
1459 }
1460
99a2008d 1461 /* continue probing in work context as may trigger request module */
9a34af4a 1462 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1463
a82d51ed 1464 *rchip = chip;
99a2008d 1465
a82d51ed
TI		 1466 return 0;
1467}
1468
48c8b0eb 1469static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1470{
1471 int dev = chip->dev_index;
1472 struct pci_dev *pci = chip->pci;
1473 struct snd_card *card = chip->card;
67908994 1474 int err;
a82d51ed 1475 unsigned short gcap;
413cbf46 1476 unsigned int dma_bits = 64;
a82d51ed 1477
07e4ca50
TI		 1478#if BITS_PER_LONG != 64
1479 /* Fix up base address on ULI M5461 */
1480 if (chip->driver_type == AZX_DRIVER_ULI) {
1481 u16 tmp3;
1482 pci_read_config_word(pci, 0x40, &tmp3);
1483 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1484 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1485 }
1486#endif
1487
927fc866 1488 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1489 if (err < 0)
1da177e4 1490 return err;
a82d51ed 1491 chip->region_requested = 1;
1da177e4 1492
927fc866 1493 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 1494 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 1495 if (chip->remap_addr == NULL) {
4e76a883 1496 dev_err(card->dev, "ioremap error\n");
a82d51ed 1497 return -ENXIO;
1da177e4
LT		 1498 }
1499
db79afa1
BH		 1500 if (chip->msi) {
1501 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1502 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1503 pci->no_64bit_msi = true;
1504 }
68e7fffc
TI		 1505 if (pci_enable_msi(pci) < 0)
1506 chip->msi = 0;
db79afa1 1507 }
7376d013 1508
a82d51ed
TI		 1509 if (azx_acquire_irq(chip, 0) < 0)
1510 return -EBUSY;
1da177e4
LT		 1511
1512 pci_set_master(pci);
1513 synchronize_irq(chip->irq);
1514
bcd72003 1515 gcap = azx_readw(chip, GCAP);
4e76a883 1516 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1517
413cbf46
TI		 1518 /* AMD devices support 40 or 48bit DMA, take the safe one */
1519 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1520 dma_bits = 40;
1521
dc4c2e6b 1522 /* disable SB600 64bit support for safety */
9477c58e 1523 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1524 struct pci_dev *p_smbus;
413cbf46 1525 dma_bits = 40;
dc4c2e6b
AB		 1526 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1527 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1528 NULL);
1529 if (p_smbus) {
1530 if (p_smbus->revision < 0x30)
fb1d8ac2 1531 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1532 pci_dev_put(p_smbus);
1533 }
1534 }
09240cf4 1535
9477c58e
TI		 1536 /* disable 64bit DMA address on some devices */
1537 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1538 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1539 gcap &= ~AZX_GCAP_64OK;
9477c58e 1540 }
396087ea 1541
2ae66c26 1542 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1543 if (align_buffer_size >= 0)
1544 chip->align_buffer_size = !!align_buffer_size;
1545 else {
103884a3 1546 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1547 chip->align_buffer_size = 0;
7bfe059e
TI		 1548 else
1549 chip->align_buffer_size = 1;
1550 }
2ae66c26 1551
cf7aaca8 1552 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1553 if (!(gcap & AZX_GCAP_64OK))
1554 dma_bits = 32;
1555 if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) {
1556 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits));
1557 } else {
e930438c
YH		 1558 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1559 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 1560 }
cf7aaca8 1561
8b6ed8e7
TI		 1562 /* read number of streams from GCAP register instead of using
1563 * hardcoded value
1564 */
1565 chip->capture_streams = (gcap >> 8) & 0x0f;
1566 chip->playback_streams = (gcap >> 12) & 0x0f;
1567 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1568 /* gcap didn't give any info, switching to old method */
1569
1570 switch (chip->driver_type) {
1571 case AZX_DRIVER_ULI:
1572 chip->playback_streams = ULI_NUM_PLAYBACK;
1573 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1574 break;
1575 case AZX_DRIVER_ATIHDMI:
1815b34a 1576 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1577 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1578 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1579 break;
c4da29ca 1580 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1581 default:
1582 chip->playback_streams = ICH6_NUM_PLAYBACK;
1583 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1584 break;
1585 }
07e4ca50 1586 }
8b6ed8e7
TI		 1587 chip->capture_index_offset = 0;
1588 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1589 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 1590 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1591 GFP_KERNEL);
927fc866 1592 if (!chip->azx_dev) {
4e76a883 1593 dev_err(card->dev, "cannot malloc azx_dev\n");
a82d51ed 1594 return -ENOMEM;
07e4ca50
TI		 1595 }
1596
67908994 1597 err = azx_alloc_stream_pages(chip);
81740861 1598 if (err < 0)
a82d51ed 1599 return err;
1da177e4
LT		 1600
1601 /* initialize streams */
1602 azx_init_stream(chip);
1603
1604 /* initialize chip */
cb53c626 1605 azx_init_pci(chip);
e4d9e513
ML		 1606
1607 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1608 haswell_set_bclk(chip);
1609
10e77dda 1610 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1611
1612 /* codec detection */
927fc866 1613 if (!chip->codec_mask) {
4e76a883 1614 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1615 return -ENODEV;
1da177e4
LT		 1616 }
1617
07e4ca50 1618 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1619 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1620 sizeof(card->shortname));
1621 snprintf(card->longname, sizeof(card->longname),
1622 "%s at 0x%lx irq %i",
1623 card->shortname, chip->addr, chip->irq);
07e4ca50 1624
1da177e4 1625 return 0;
1da177e4
LT		 1626}
1627
cb53c626
TI		 1628static void power_down_all_codecs(struct azx *chip)
1629{
83012a7c 1630#ifdef CONFIG_PM
cb53c626
TI		 1631 /* The codecs were powered up in snd_hda_codec_new().
1632 * Now all initialization done, so turn them down if possible
1633 */
1634 struct hda_codec *codec;
1635 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1636 snd_hda_power_down(codec);
1637 }
1638#endif
1639}
1640
97c6a3d1 1641#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1642/* callback from request_firmware_nowait() */
1643static void azx_firmware_cb(const struct firmware *fw, void *context)
1644{
1645 struct snd_card *card = context;
1646 struct azx *chip = card->private_data;
1647 struct pci_dev *pci = chip->pci;
1648
1649 if (!fw) {
4e76a883 1650 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1651 goto error;
1652 }
1653
1654 chip->fw = fw;
1655 if (!chip->disabled) {
1656 /* continue probing */
1657 if (azx_probe_continue(chip))
1658 goto error;
1659 }
1660 return; /* OK */
1661
1662 error:
1663 snd_card_free(card);
1664 pci_set_drvdata(pci, NULL);
1665}
97c6a3d1 1666#endif
5cb543db 1667
40830813
DR		 1668/*
1669 * HDA controller ops.
1670 */
1671
1672/* PCI register access. */
db291e36 1673static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1674{
1675 writel(value, addr);
1676}
1677
db291e36 1678static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1679{
1680 return readl(addr);
1681}
1682
db291e36 1683static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1684{
1685 writew(value, addr);
1686}
1687
db291e36 1688static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1689{
1690 return readw(addr);
1691}
1692
db291e36 1693static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1694{
1695 writeb(value, addr);
1696}
1697
db291e36 1698static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1699{
1700 return readb(addr);
1701}
1702
f46ea609
DR		 1703static int disable_msi_reset_irq(struct azx *chip)
1704{
1705 int err;
1706
1707 free_irq(chip->irq, chip);
1708 chip->irq = -1;
1709 pci_disable_msi(chip->pci);
1710 chip->msi = 0;
1711 err = azx_acquire_irq(chip, 1);
1712 if (err < 0)
1713 return err;
1714
1715 return 0;
1716}
1717
b419b35b
DR		 1718/* DMA page allocation helpers. */
1719static int dma_alloc_pages(struct azx *chip,
1720 int type,
1721 size_t size,
1722 struct snd_dma_buffer *buf)
1723{
1724 int err;
1725
1726 err = snd_dma_alloc_pages(type,
1727 chip->card->dev,
1728 size, buf);
1729 if (err < 0)
1730 return err;
1731 mark_pages_wc(chip, buf, true);
1732 return 0;
1733}
1734
1735static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1736{
1737 mark_pages_wc(chip, buf, false);
1738 snd_dma_free_pages(buf);
1739}
1740
1741static int substream_alloc_pages(struct azx *chip,
1742 struct snd_pcm_substream *substream,
1743 size_t size)
1744{
1745 struct azx_dev *azx_dev = get_azx_dev(substream);
1746 int ret;
1747
1748 mark_runtime_wc(chip, azx_dev, substream, false);
1749 azx_dev->bufsize = 0;
1750 azx_dev->period_bytes = 0;
1751 azx_dev->format_val = 0;
1752 ret = snd_pcm_lib_malloc_pages(substream, size);
1753 if (ret < 0)
1754 return ret;
1755 mark_runtime_wc(chip, azx_dev, substream, true);
1756 return 0;
1757}
1758
1759static int substream_free_pages(struct azx *chip,
1760 struct snd_pcm_substream *substream)
1761{
1762 struct azx_dev *azx_dev = get_azx_dev(substream);
1763 mark_runtime_wc(chip, azx_dev, substream, false);
1764 return snd_pcm_lib_free_pages(substream);
1765}
1766
8769b278
DR		 1767static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1768 struct vm_area_struct *area)
1769{
1770#ifdef CONFIG_X86
1771 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1772 struct azx *chip = apcm->chip;
3b70bdba 1773 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 1774 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1775#endif
1776}
1777
40830813 1778static const struct hda_controller_ops pci_hda_ops = {
778bde6f
DR		 1779 .reg_writel = pci_azx_writel,
1780 .reg_readl = pci_azx_readl,
1781 .reg_writew = pci_azx_writew,
1782 .reg_readw = pci_azx_readw,
1783 .reg_writeb = pci_azx_writeb,
1784 .reg_readb = pci_azx_readb,
f46ea609 1785 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1786 .dma_alloc_pages = dma_alloc_pages,
1787 .dma_free_pages = dma_free_pages,
1788 .substream_alloc_pages = substream_alloc_pages,
1789 .substream_free_pages = substream_free_pages,
8769b278 1790 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1791 .position_check = azx_position_check,
40830813
DR		 1792};
1793
e23e7a14
BP		 1794static int azx_probe(struct pci_dev *pci,
1795 const struct pci_device_id *pci_id)
1da177e4 1796{
5aba4f8e 1797 static int dev;
a98f90fd 1798 struct snd_card *card;
9a34af4a 1799 struct hda_intel *hda;
a98f90fd 1800 struct azx *chip;
aad730d0 1801 bool schedule_probe;
927fc866 1802 int err;
1da177e4 1803
5aba4f8e
TI		 1804 if (dev >= SNDRV_CARDS)
1805 return -ENODEV;
1806 if (!enable[dev]) {
1807 dev++;
1808 return -ENOENT;
1809 }
1810
60c5772b
TI		 1811 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1812 0, &card);
e58de7ba 1813 if (err < 0) {
4e76a883 1814 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1815 return err;
1da177e4
LT		 1816 }
1817
40830813
DR		 1818 err = azx_create(card, pci, dev, pci_id->driver_data,
1819 &pci_hda_ops, &chip);
41dda0fd
WF		 1820 if (err < 0)
1821 goto out_free;
421a1252 1822 card->private_data = chip;
9a34af4a 1823 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1824
1825 pci_set_drvdata(pci, card);
1826
1827 err = register_vga_switcheroo(chip);
1828 if (err < 0) {
4e76a883 1829 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1830 goto out_free;
1831 }
1832
1833 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1834 dev_info(card->dev, "VGA controller is disabled\n");
1835 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1836 chip->disabled = true;
1837 }
1838
aad730d0 1839 schedule_probe = !chip->disabled;
1da177e4 1840
4918cdab
TI		 1841#ifdef CONFIG_SND_HDA_PATCH_LOADER
1842 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1843 dev_info(card->dev, "Applying patch firmware '%s'\n",
1844 patch[dev]);
5cb543db
TI		 1845 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1846 &pci->dev, GFP_KERNEL, card,
1847 azx_firmware_cb);
4918cdab
TI		 1848 if (err < 0)
1849 goto out_free;
aad730d0 1850 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1851 }
1852#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1853
aad730d0
TI		 1854#ifndef CONFIG_SND_HDA_I915
1855 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1856 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1857#endif
99a2008d 1858
aad730d0 1859 if (schedule_probe)
9a34af4a 1860 schedule_work(&hda->probe_work);
a82d51ed 1861
a82d51ed 1862 dev++;
88d071fc 1863 if (chip->disabled)
9a34af4a 1864 complete_all(&hda->probe_wait);
a82d51ed
TI		 1865 return 0;
1866
1867out_free:
1868 snd_card_free(card);
1869 return err;
1870}
1871
e62a42ae
DR		 1872/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1873static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1874 [AZX_DRIVER_NVIDIA] = 8,
1875 [AZX_DRIVER_TERA] = 1,
1876};
1877
48c8b0eb 1878static int azx_probe_continue(struct azx *chip)
a82d51ed 1879{
9a34af4a 1880 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
c67e2228 1881 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1882 int dev = chip->dev_index;
1883 int err;
1884
99a2008d
WX		 1885 /* Request power well for Haswell HDA controller and codec */
1886 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 1887#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 1888 err = hda_i915_init();
1889 if (err < 0) {
4e76a883
TI		 1890 dev_err(chip->card->dev,
1891 "Error request power-well from i915\n");
99a2008d
WX		 1892 goto out_free;
1893 }
74b0c2d7
TI		 1894 err = hda_display_power(true);
1895 if (err < 0) {
1896 dev_err(chip->card->dev,
1897 "Cannot turn on display power on i915\n");
1898 goto out_free;
1899 }
c841ad2a 1900#endif
99a2008d
WX		 1901 }
1902
5c90680e
TI		 1903 err = azx_first_init(chip);
1904 if (err < 0)
1905 goto out_free;
1906
2dca0bba
JK		 1907#ifdef CONFIG_SND_HDA_INPUT_BEEP
1908 chip->beep_mode = beep_mode[dev];
1909#endif
1910
1da177e4 1911 /* create codec instances */
e62a42ae
DR		 1912 err = azx_codec_create(chip, model[dev],
1913 azx_max_codecs[chip->driver_type],
1914 power_save_addr);
1915
41dda0fd
WF		 1916 if (err < 0)
1917 goto out_free;
4ea6fbc8 1918#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 1919 if (chip->fw) {
1920 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1921 chip->fw->data);
4ea6fbc8
TI		 1922 if (err < 0)
1923 goto out_free;
e39ae856 1924#ifndef CONFIG_PM
4918cdab
TI		 1925 release_firmware(chip->fw); /* no longer needed */
1926 chip->fw = NULL;
e39ae856 1927#endif
4ea6fbc8
TI		 1928 }
1929#endif
10e77dda 1930 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 1931 err = azx_codec_configure(chip);
1932 if (err < 0)
1933 goto out_free;
1934 }
1da177e4
LT		 1935
1936 /* create PCM streams */
176d5335 1937 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 1938 if (err < 0)
1939 goto out_free;
1da177e4
LT		 1940
1941 /* create mixer controls */
d01ce99f 1942 err = azx_mixer_create(chip);
41dda0fd
WF		 1943 if (err < 0)
1944 goto out_free;
1da177e4 1945
a82d51ed 1946 err = snd_card_register(chip->card);
41dda0fd
WF		 1947 if (err < 0)
1948 goto out_free;
1da177e4 1949
cb53c626
TI		 1950 chip->running = 1;
1951 power_down_all_codecs(chip);
0cbf0098 1952 azx_notifier_register(chip);
65fcd41d 1953 azx_add_card_list(chip);
9a34af4a 1954 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || hda->use_vga_switcheroo)
c67e2228 1955 pm_runtime_put_noidle(&pci->dev);
1da177e4 1956
41dda0fd 1957out_free:
88d071fc 1958 if (err < 0)
9a34af4a
TI		 1959 hda->init_failed = 1;
1960 complete_all(&hda->probe_wait);
41dda0fd 1961 return err;
1da177e4
LT		 1962}
1963
e23e7a14 1964static void azx_remove(struct pci_dev *pci)
1da177e4 1965{
9121947d 1966 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 1967
9121947d
TI		 1968 if (card)
1969 snd_card_free(card);
1da177e4
LT		 1970}
1971
1972/* PCI IDs */
6f51f6cf 1973static const struct pci_device_id azx_ids[] = {
d2f2fcd2 1974 /* CPT */
9477c58e 1975 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 1976 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 1977 /* PBG */
9477c58e 1978 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 1979 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 1980 /* Panther Point */
9477c58e 1981 { PCI_DEVICE(0x8086, 0x1e20),
b1920c21 1982 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 1983 /* Lynx Point */
1984 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 1985 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 1986 /* 9 Series */
1987 { PCI_DEVICE(0x8086, 0x8ca0),
1988 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 1989 /* Wellsburg */
1990 { PCI_DEVICE(0x8086, 0x8d20),
1991 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1992 { PCI_DEVICE(0x8086, 0x8d21),
1993 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1994 /* Lynx Point-LP */
1995 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 1996 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1997 /* Lynx Point-LP */
1998 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 1999 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2000 /* Wildcat Point-LP */
2001 { PCI_DEVICE(0x8086, 0x9ca0),
2002 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2003 /* Sunrise Point */
2004 { PCI_DEVICE(0x8086, 0xa170),
2005 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
b4565913
DR		 2006 /* Sunrise Point-LP */
2007 { PCI_DEVICE(0x8086, 0x9d70),
d6795827 2008 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
e926f2c8 2009 /* Haswell */
4a7c516b 2010 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2011 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2012 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2013 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2014 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2015 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2016 /* Broadwell */
2017 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2018 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2019 /* 5 Series/3400 */
2020 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2021 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2022 /* Poulsbo */
9477c58e 2023 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 2024 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2025 /* Oaktrail */
09904b95 2026 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 2027 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 2028 /* BayTrail */
2029 { PCI_DEVICE(0x8086, 0x0f04),
2030 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
f31b2ffc
LY		 2031 /* Braswell */
2032 { PCI_DEVICE(0x8086, 0x2284),
2033 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
b42b4afb 2034 /* ICH6 */
8b0bd226 2035 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2036 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2037 /* ICH7 */
8b0bd226 2038 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2039 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2040 /* ESB2 */
8b0bd226 2041 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2042 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2043 /* ICH8 */
8b0bd226 2044 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2045 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2046 /* ICH9 */
8b0bd226 2047 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2048 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2049 /* ICH9 */
8b0bd226 2050 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2051 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2052 /* ICH10 */
8b0bd226 2053 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2054 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2055 /* ICH10 */
8b0bd226 2056 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2057 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2058 /* Generic Intel */
2059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2060 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2061 .class_mask = 0xffffff,
103884a3 2062 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2063 /* ATI SB 450/600/700/800/900 */
2064 { PCI_DEVICE(0x1002, 0x437b),
2065 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2066 { PCI_DEVICE(0x1002, 0x4383),
2067 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2068 /* AMD Hudson */
2069 { PCI_DEVICE(0x1022, 0x780d),
2070 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2071 /* ATI HDMI */
9477c58e
TI		 2072 { PCI_DEVICE(0x1002, 0x793b),
2073 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2074 { PCI_DEVICE(0x1002, 0x7919),
2075 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2076 { PCI_DEVICE(0x1002, 0x960f),
2077 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2078 { PCI_DEVICE(0x1002, 0x970f),
2079 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2080 { PCI_DEVICE(0x1002, 0xaa00),
2081 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2082 { PCI_DEVICE(0x1002, 0xaa08),
2083 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2084 { PCI_DEVICE(0x1002, 0xaa10),
2085 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2086 { PCI_DEVICE(0x1002, 0xaa18),
2087 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2088 { PCI_DEVICE(0x1002, 0xaa20),
2089 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2090 { PCI_DEVICE(0x1002, 0xaa28),
2091 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2092 { PCI_DEVICE(0x1002, 0xaa30),
2093 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2094 { PCI_DEVICE(0x1002, 0xaa38),
2095 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2096 { PCI_DEVICE(0x1002, 0xaa40),
2097 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2098 { PCI_DEVICE(0x1002, 0xaa48),
2099 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2100 { PCI_DEVICE(0x1002, 0xaa50),
2101 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2102 { PCI_DEVICE(0x1002, 0xaa58),
2103 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2104 { PCI_DEVICE(0x1002, 0xaa60),
2105 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2106 { PCI_DEVICE(0x1002, 0xaa68),
2107 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2108 { PCI_DEVICE(0x1002, 0xaa80),
2109 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2110 { PCI_DEVICE(0x1002, 0xaa88),
2111 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2112 { PCI_DEVICE(0x1002, 0xaa90),
2113 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2114 { PCI_DEVICE(0x1002, 0xaa98),
2115 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2116 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2117 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2118 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2119 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2120 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2121 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2122 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2123 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2124 /* VIA VT8251/VT8237A */
9477c58e
TI		 2125 { PCI_DEVICE(0x1106, 0x3288),
2126 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 2127 /* VIA GFX VT7122/VX900 */
2128 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2129 /* VIA GFX VT6122/VX11 */
2130 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2131 /* SIS966 */
2132 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2133 /* ULI M5461 */
2134 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2135 /* NVIDIA MCP */
0c2fd1bf
TI		 2136 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2137 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2138 .class_mask = 0xffffff,
9477c58e 2139 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2140 /* Teradici */
9477c58e
TI		 2141 { PCI_DEVICE(0x6549, 0x1200),
2142 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2143 { PCI_DEVICE(0x6549, 0x2200),
2144 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2145 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2146 /* CTHDA chips */
2147 { PCI_DEVICE(0x1102, 0x0010),
2148 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2149 { PCI_DEVICE(0x1102, 0x0012),
2150 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2151#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2152 /* the following entry conflicts with snd-ctxfi driver,
2153 * as ctxfi driver mutates from HD-audio to native mode with
2154 * a special command sequence.
2155 */
4e01f54b
TI		 2156 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2157 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2158 .class_mask = 0xffffff,
9477c58e 2159 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2160 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2161#else
2162 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2163 { PCI_DEVICE(0x1102, 0x0009),
2164 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2165 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2166#endif
c563f473
TI		 2167 /* CM8888 */
2168 { PCI_DEVICE(0x13f6, 0x5011),
2169 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2170 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2171 /* Vortex86MX */
2172 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2173 /* VMware HDAudio */
2174 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2175 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2176 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2177 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2178 .class_mask = 0xffffff,
9477c58e 2179 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2180 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2181 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2182 .class_mask = 0xffffff,
9477c58e 2183 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2184 { 0, }
2185};
2186MODULE_DEVICE_TABLE(pci, azx_ids);
2187
2188/* pci_driver definition */
e9f66d9b 2189static struct pci_driver azx_driver = {
3733e424 2190 .name = KBUILD_MODNAME,
1da177e4
LT		 2191 .id_table = azx_ids,
2192 .probe = azx_probe,
e23e7a14 2193 .remove = azx_remove,
68cb2b55
TI		 2194 .driver = {
2195 .pm = AZX_PM_OPS,
2196 },
1da177e4
LT		 2197};
2198
e9f66d9b 2199module_pci_driver(azx_driver);
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