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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * | |
3 | * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio. | |
4 | * | |
5 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
8 | * PeiSen Hou <pshou@realtek.com.tw> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the Free | |
12 | * Software Foundation; either version 2 of the License, or (at your option) | |
13 | * any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
18 | * more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along with | |
21 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
22 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
23 | * | |
24 | * CONTACTS: | |
25 | * | |
26 | * Matt Jared matt.jared@intel.com | |
27 | * Andy Kopp andy.kopp@intel.com | |
28 | * Dan Kogan dan.d.kogan@intel.com | |
29 | * | |
30 | * CHANGES: | |
31 | * | |
32 | * 2004.12.01 Major rewrite by tiwai, merged the work of pshou | |
33 | * | |
34 | */ | |
35 | ||
36 | #include <sound/driver.h> | |
37 | #include <asm/io.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
362775e2 | 40 | #include <linux/kernel.h> |
1da177e4 LT |
41 | #include <linux/module.h> |
42 | #include <linux/moduleparam.h> | |
43 | #include <linux/init.h> | |
44 | #include <linux/slab.h> | |
45 | #include <linux/pci.h> | |
62932df8 | 46 | #include <linux/mutex.h> |
1da177e4 LT |
47 | #include <sound/core.h> |
48 | #include <sound/initval.h> | |
49 | #include "hda_codec.h" | |
50 | ||
51 | ||
b7fe4622 CL |
52 | static int index = SNDRV_DEFAULT_IDX1; |
53 | static char *id = SNDRV_DEFAULT_STR1; | |
54 | static char *model; | |
55 | static int position_fix; | |
954fa19a | 56 | static int probe_mask = -1; |
27346166 | 57 | static int single_cmd; |
1da177e4 | 58 | |
b7fe4622 | 59 | module_param(index, int, 0444); |
1da177e4 | 60 | MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); |
b7fe4622 | 61 | module_param(id, charp, 0444); |
1da177e4 | 62 | MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); |
b7fe4622 | 63 | module_param(model, charp, 0444); |
1da177e4 | 64 | MODULE_PARM_DESC(model, "Use the given board model."); |
b7fe4622 | 65 | module_param(position_fix, int, 0444); |
0be3b5d3 | 66 | MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size)."); |
606ad75f TI |
67 | module_param(probe_mask, int, 0444); |
68 | MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); | |
27346166 TI |
69 | module_param(single_cmd, bool, 0444); |
70 | MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs (for debugging only)."); | |
606ad75f | 71 | |
1da177e4 | 72 | |
2b3e584b TI |
73 | /* just for backward compatibility */ |
74 | static int enable; | |
698444f3 | 75 | module_param(enable, bool, 0444); |
2b3e584b | 76 | |
1da177e4 LT |
77 | MODULE_LICENSE("GPL"); |
78 | MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," | |
79 | "{Intel, ICH6M}," | |
2f1b3818 | 80 | "{Intel, ICH7}," |
f5d40b30 | 81 | "{Intel, ESB2}," |
d2981393 | 82 | "{Intel, ICH8}," |
fc20a562 TI |
83 | "{ATI, SB450}," |
84 | "{VIA, VT8251}," | |
47672310 | 85 | "{VIA, VT8237A}," |
07e4ca50 TI |
86 | "{SiS, SIS966}," |
87 | "{ULI, M5461}}"); | |
1da177e4 LT |
88 | MODULE_DESCRIPTION("Intel HDA driver"); |
89 | ||
90 | #define SFX "hda-intel: " | |
91 | ||
92 | /* | |
93 | * registers | |
94 | */ | |
95 | #define ICH6_REG_GCAP 0x00 | |
96 | #define ICH6_REG_VMIN 0x02 | |
97 | #define ICH6_REG_VMAJ 0x03 | |
98 | #define ICH6_REG_OUTPAY 0x04 | |
99 | #define ICH6_REG_INPAY 0x06 | |
100 | #define ICH6_REG_GCTL 0x08 | |
101 | #define ICH6_REG_WAKEEN 0x0c | |
102 | #define ICH6_REG_STATESTS 0x0e | |
103 | #define ICH6_REG_GSTS 0x10 | |
104 | #define ICH6_REG_INTCTL 0x20 | |
105 | #define ICH6_REG_INTSTS 0x24 | |
106 | #define ICH6_REG_WALCLK 0x30 | |
107 | #define ICH6_REG_SYNC 0x34 | |
108 | #define ICH6_REG_CORBLBASE 0x40 | |
109 | #define ICH6_REG_CORBUBASE 0x44 | |
110 | #define ICH6_REG_CORBWP 0x48 | |
111 | #define ICH6_REG_CORBRP 0x4A | |
112 | #define ICH6_REG_CORBCTL 0x4c | |
113 | #define ICH6_REG_CORBSTS 0x4d | |
114 | #define ICH6_REG_CORBSIZE 0x4e | |
115 | ||
116 | #define ICH6_REG_RIRBLBASE 0x50 | |
117 | #define ICH6_REG_RIRBUBASE 0x54 | |
118 | #define ICH6_REG_RIRBWP 0x58 | |
119 | #define ICH6_REG_RINTCNT 0x5a | |
120 | #define ICH6_REG_RIRBCTL 0x5c | |
121 | #define ICH6_REG_RIRBSTS 0x5d | |
122 | #define ICH6_REG_RIRBSIZE 0x5e | |
123 | ||
124 | #define ICH6_REG_IC 0x60 | |
125 | #define ICH6_REG_IR 0x64 | |
126 | #define ICH6_REG_IRS 0x68 | |
127 | #define ICH6_IRS_VALID (1<<1) | |
128 | #define ICH6_IRS_BUSY (1<<0) | |
129 | ||
130 | #define ICH6_REG_DPLBASE 0x70 | |
131 | #define ICH6_REG_DPUBASE 0x74 | |
132 | #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ | |
133 | ||
134 | /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ | |
135 | enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; | |
136 | ||
137 | /* stream register offsets from stream base */ | |
138 | #define ICH6_REG_SD_CTL 0x00 | |
139 | #define ICH6_REG_SD_STS 0x03 | |
140 | #define ICH6_REG_SD_LPIB 0x04 | |
141 | #define ICH6_REG_SD_CBL 0x08 | |
142 | #define ICH6_REG_SD_LVI 0x0c | |
143 | #define ICH6_REG_SD_FIFOW 0x0e | |
144 | #define ICH6_REG_SD_FIFOSIZE 0x10 | |
145 | #define ICH6_REG_SD_FORMAT 0x12 | |
146 | #define ICH6_REG_SD_BDLPL 0x18 | |
147 | #define ICH6_REG_SD_BDLPU 0x1c | |
148 | ||
149 | /* PCI space */ | |
150 | #define ICH6_PCIREG_TCSEL 0x44 | |
151 | ||
152 | /* | |
153 | * other constants | |
154 | */ | |
155 | ||
156 | /* max number of SDs */ | |
07e4ca50 TI |
157 | /* ICH, ATI and VIA have 4 playback and 4 capture */ |
158 | #define ICH6_CAPTURE_INDEX 0 | |
159 | #define ICH6_NUM_CAPTURE 4 | |
160 | #define ICH6_PLAYBACK_INDEX 4 | |
161 | #define ICH6_NUM_PLAYBACK 4 | |
162 | ||
163 | /* ULI has 6 playback and 5 capture */ | |
164 | #define ULI_CAPTURE_INDEX 0 | |
165 | #define ULI_NUM_CAPTURE 5 | |
166 | #define ULI_PLAYBACK_INDEX 5 | |
167 | #define ULI_NUM_PLAYBACK 6 | |
168 | ||
169 | /* this number is statically defined for simplicity */ | |
170 | #define MAX_AZX_DEV 16 | |
171 | ||
1da177e4 | 172 | /* max number of fragments - we may use more if allocating more pages for BDL */ |
07e4ca50 TI |
173 | #define BDL_SIZE PAGE_ALIGN(8192) |
174 | #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16)) | |
1da177e4 LT |
175 | /* max buffer size - no h/w limit, you can increase as you like */ |
176 | #define AZX_MAX_BUF_SIZE (1024*1024*1024) | |
177 | /* max number of PCM devics per card */ | |
ec9e1c5c TI |
178 | #define AZX_MAX_AUDIO_PCMS 6 |
179 | #define AZX_MAX_MODEM_PCMS 2 | |
180 | #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS) | |
1da177e4 LT |
181 | |
182 | /* RIRB int mask: overrun[2], response[0] */ | |
183 | #define RIRB_INT_RESPONSE 0x01 | |
184 | #define RIRB_INT_OVERRUN 0x04 | |
185 | #define RIRB_INT_MASK 0x05 | |
186 | ||
187 | /* STATESTS int mask: SD2,SD1,SD0 */ | |
188 | #define STATESTS_INT_MASK 0x07 | |
f5d40b30 | 189 | #define AZX_MAX_CODECS 4 |
1da177e4 LT |
190 | |
191 | /* SD_CTL bits */ | |
192 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ | |
193 | #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ | |
194 | #define SD_CTL_STREAM_TAG_MASK (0xf << 20) | |
195 | #define SD_CTL_STREAM_TAG_SHIFT 20 | |
196 | ||
197 | /* SD_CTL and SD_STS */ | |
198 | #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ | |
199 | #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ | |
200 | #define SD_INT_COMPLETE 0x04 /* completion interrupt */ | |
201 | #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE) | |
202 | ||
203 | /* SD_STS */ | |
204 | #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ | |
205 | ||
206 | /* INTCTL and INTSTS */ | |
207 | #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ | |
208 | #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ | |
209 | #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ | |
210 | ||
41e2fce4 M |
211 | /* GCTL unsolicited response enable bit */ |
212 | #define ICH6_GCTL_UREN (1<<8) | |
213 | ||
1da177e4 LT |
214 | /* GCTL reset bit */ |
215 | #define ICH6_GCTL_RESET (1<<0) | |
216 | ||
217 | /* CORB/RIRB control, read/write pointer */ | |
218 | #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */ | |
219 | #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */ | |
220 | #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */ | |
221 | /* below are so far hardcoded - should read registers in future */ | |
222 | #define ICH6_MAX_CORB_ENTRIES 256 | |
223 | #define ICH6_MAX_RIRB_ENTRIES 256 | |
224 | ||
c74db86b TI |
225 | /* position fix mode */ |
226 | enum { | |
0be3b5d3 | 227 | POS_FIX_AUTO, |
c74db86b | 228 | POS_FIX_NONE, |
0be3b5d3 TI |
229 | POS_FIX_POSBUF, |
230 | POS_FIX_FIFO, | |
c74db86b | 231 | }; |
1da177e4 | 232 | |
f5d40b30 | 233 | /* Defines for ATI HD Audio support in SB450 south bridge */ |
f5d40b30 FL |
234 | #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 |
235 | #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 | |
236 | ||
da3fca21 V |
237 | /* Defines for Nvidia HDA support */ |
238 | #define NVIDIA_HDA_TRANSREG_ADDR 0x4e | |
239 | #define NVIDIA_HDA_ENABLE_COHBITS 0x0f | |
f5d40b30 | 240 | |
1da177e4 LT |
241 | /* |
242 | */ | |
243 | ||
a98f90fd | 244 | struct azx_dev { |
1da177e4 LT |
245 | u32 *bdl; /* virtual address of the BDL */ |
246 | dma_addr_t bdl_addr; /* physical address of the BDL */ | |
247 | volatile u32 *posbuf; /* position buffer pointer */ | |
248 | ||
249 | unsigned int bufsize; /* size of the play buffer in bytes */ | |
250 | unsigned int fragsize; /* size of each period in bytes */ | |
251 | unsigned int frags; /* number for period in the play buffer */ | |
252 | unsigned int fifo_size; /* FIFO size */ | |
253 | ||
254 | void __iomem *sd_addr; /* stream descriptor pointer */ | |
255 | ||
256 | u32 sd_int_sta_mask; /* stream int status mask */ | |
257 | ||
258 | /* pcm support */ | |
a98f90fd | 259 | struct snd_pcm_substream *substream; /* assigned substream, set in PCM open */ |
1da177e4 LT |
260 | unsigned int format_val; /* format value to be set in the controller and the codec */ |
261 | unsigned char stream_tag; /* assigned stream */ | |
262 | unsigned char index; /* stream index */ | |
1a56f8d6 TI |
263 | /* for sanity check of position buffer */ |
264 | unsigned int period_intr; | |
1da177e4 LT |
265 | |
266 | unsigned int opened: 1; | |
267 | unsigned int running: 1; | |
268 | }; | |
269 | ||
270 | /* CORB/RIRB */ | |
a98f90fd | 271 | struct azx_rb { |
1da177e4 LT |
272 | u32 *buf; /* CORB/RIRB buffer |
273 | * Each CORB entry is 4byte, RIRB is 8byte | |
274 | */ | |
275 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | |
276 | /* for RIRB */ | |
277 | unsigned short rp, wp; /* read/write pointers */ | |
278 | int cmds; /* number of pending requests */ | |
279 | u32 res; /* last read value */ | |
280 | }; | |
281 | ||
a98f90fd TI |
282 | struct azx { |
283 | struct snd_card *card; | |
1da177e4 LT |
284 | struct pci_dev *pci; |
285 | ||
07e4ca50 TI |
286 | /* chip type specific */ |
287 | int driver_type; | |
288 | int playback_streams; | |
289 | int playback_index_offset; | |
290 | int capture_streams; | |
291 | int capture_index_offset; | |
292 | int num_streams; | |
293 | ||
1da177e4 LT |
294 | /* pci resources */ |
295 | unsigned long addr; | |
296 | void __iomem *remap_addr; | |
297 | int irq; | |
298 | ||
299 | /* locks */ | |
300 | spinlock_t reg_lock; | |
62932df8 | 301 | struct mutex open_mutex; |
1da177e4 | 302 | |
07e4ca50 | 303 | /* streams (x num_streams) */ |
a98f90fd | 304 | struct azx_dev *azx_dev; |
1da177e4 LT |
305 | |
306 | /* PCM */ | |
307 | unsigned int pcm_devs; | |
a98f90fd | 308 | struct snd_pcm *pcm[AZX_MAX_PCMS]; |
1da177e4 LT |
309 | |
310 | /* HD codec */ | |
311 | unsigned short codec_mask; | |
312 | struct hda_bus *bus; | |
313 | ||
314 | /* CORB/RIRB */ | |
a98f90fd TI |
315 | struct azx_rb corb; |
316 | struct azx_rb rirb; | |
1da177e4 LT |
317 | |
318 | /* BDL, CORB/RIRB and position buffers */ | |
319 | struct snd_dma_buffer bdl; | |
320 | struct snd_dma_buffer rb; | |
321 | struct snd_dma_buffer posbuf; | |
c74db86b TI |
322 | |
323 | /* flags */ | |
324 | int position_fix; | |
ce43fbae | 325 | unsigned int initialized: 1; |
27346166 | 326 | unsigned int single_cmd: 1; |
1da177e4 LT |
327 | }; |
328 | ||
07e4ca50 TI |
329 | /* driver types */ |
330 | enum { | |
331 | AZX_DRIVER_ICH, | |
332 | AZX_DRIVER_ATI, | |
333 | AZX_DRIVER_VIA, | |
334 | AZX_DRIVER_SIS, | |
335 | AZX_DRIVER_ULI, | |
da3fca21 | 336 | AZX_DRIVER_NVIDIA, |
07e4ca50 TI |
337 | }; |
338 | ||
339 | static char *driver_short_names[] __devinitdata = { | |
340 | [AZX_DRIVER_ICH] = "HDA Intel", | |
341 | [AZX_DRIVER_ATI] = "HDA ATI SB", | |
342 | [AZX_DRIVER_VIA] = "HDA VIA VT82xx", | |
343 | [AZX_DRIVER_SIS] = "HDA SIS966", | |
da3fca21 V |
344 | [AZX_DRIVER_ULI] = "HDA ULI M5461", |
345 | [AZX_DRIVER_NVIDIA] = "HDA NVidia", | |
07e4ca50 TI |
346 | }; |
347 | ||
1da177e4 LT |
348 | /* |
349 | * macros for easy use | |
350 | */ | |
351 | #define azx_writel(chip,reg,value) \ | |
352 | writel(value, (chip)->remap_addr + ICH6_REG_##reg) | |
353 | #define azx_readl(chip,reg) \ | |
354 | readl((chip)->remap_addr + ICH6_REG_##reg) | |
355 | #define azx_writew(chip,reg,value) \ | |
356 | writew(value, (chip)->remap_addr + ICH6_REG_##reg) | |
357 | #define azx_readw(chip,reg) \ | |
358 | readw((chip)->remap_addr + ICH6_REG_##reg) | |
359 | #define azx_writeb(chip,reg,value) \ | |
360 | writeb(value, (chip)->remap_addr + ICH6_REG_##reg) | |
361 | #define azx_readb(chip,reg) \ | |
362 | readb((chip)->remap_addr + ICH6_REG_##reg) | |
363 | ||
364 | #define azx_sd_writel(dev,reg,value) \ | |
365 | writel(value, (dev)->sd_addr + ICH6_REG_##reg) | |
366 | #define azx_sd_readl(dev,reg) \ | |
367 | readl((dev)->sd_addr + ICH6_REG_##reg) | |
368 | #define azx_sd_writew(dev,reg,value) \ | |
369 | writew(value, (dev)->sd_addr + ICH6_REG_##reg) | |
370 | #define azx_sd_readw(dev,reg) \ | |
371 | readw((dev)->sd_addr + ICH6_REG_##reg) | |
372 | #define azx_sd_writeb(dev,reg,value) \ | |
373 | writeb(value, (dev)->sd_addr + ICH6_REG_##reg) | |
374 | #define azx_sd_readb(dev,reg) \ | |
375 | readb((dev)->sd_addr + ICH6_REG_##reg) | |
376 | ||
377 | /* for pcm support */ | |
a98f90fd | 378 | #define get_azx_dev(substream) (substream->runtime->private_data) |
1da177e4 LT |
379 | |
380 | /* Get the upper 32bit of the given dma_addr_t | |
381 | * Compiler should optimize and eliminate the code if dma_addr_t is 32bit | |
382 | */ | |
383 | #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0) | |
384 | ||
385 | ||
386 | /* | |
387 | * Interface for HD codec | |
388 | */ | |
389 | ||
1da177e4 LT |
390 | /* |
391 | * CORB / RIRB interface | |
392 | */ | |
a98f90fd | 393 | static int azx_alloc_cmd_io(struct azx *chip) |
1da177e4 LT |
394 | { |
395 | int err; | |
396 | ||
397 | /* single page (at least 4096 bytes) must suffice for both ringbuffes */ | |
398 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
399 | PAGE_SIZE, &chip->rb); | |
400 | if (err < 0) { | |
401 | snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n"); | |
402 | return err; | |
403 | } | |
404 | return 0; | |
405 | } | |
406 | ||
a98f90fd | 407 | static void azx_init_cmd_io(struct azx *chip) |
1da177e4 LT |
408 | { |
409 | /* CORB set up */ | |
410 | chip->corb.addr = chip->rb.addr; | |
411 | chip->corb.buf = (u32 *)chip->rb.area; | |
412 | azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); | |
413 | azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr)); | |
414 | ||
07e4ca50 TI |
415 | /* set the corb size to 256 entries (ULI requires explicitly) */ |
416 | azx_writeb(chip, CORBSIZE, 0x02); | |
1da177e4 LT |
417 | /* set the corb write pointer to 0 */ |
418 | azx_writew(chip, CORBWP, 0); | |
419 | /* reset the corb hw read pointer */ | |
420 | azx_writew(chip, CORBRP, ICH6_RBRWP_CLR); | |
421 | /* enable corb dma */ | |
422 | azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN); | |
423 | ||
424 | /* RIRB set up */ | |
425 | chip->rirb.addr = chip->rb.addr + 2048; | |
426 | chip->rirb.buf = (u32 *)(chip->rb.area + 2048); | |
427 | azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); | |
428 | azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr)); | |
429 | ||
07e4ca50 TI |
430 | /* set the rirb size to 256 entries (ULI requires explicitly) */ |
431 | azx_writeb(chip, RIRBSIZE, 0x02); | |
1da177e4 LT |
432 | /* reset the rirb hw write pointer */ |
433 | azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR); | |
434 | /* set N=1, get RIRB response interrupt for new entry */ | |
435 | azx_writew(chip, RINTCNT, 1); | |
436 | /* enable rirb dma and response irq */ | |
1da177e4 | 437 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); |
1da177e4 LT |
438 | chip->rirb.rp = chip->rirb.cmds = 0; |
439 | } | |
440 | ||
a98f90fd | 441 | static void azx_free_cmd_io(struct azx *chip) |
1da177e4 LT |
442 | { |
443 | /* disable ringbuffer DMAs */ | |
444 | azx_writeb(chip, RIRBCTL, 0); | |
445 | azx_writeb(chip, CORBCTL, 0); | |
446 | } | |
447 | ||
448 | /* send a command */ | |
111d3af5 TI |
449 | static int azx_corb_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct, |
450 | unsigned int verb, unsigned int para) | |
1da177e4 | 451 | { |
a98f90fd | 452 | struct azx *chip = codec->bus->private_data; |
1da177e4 LT |
453 | unsigned int wp; |
454 | u32 val; | |
455 | ||
456 | val = (u32)(codec->addr & 0x0f) << 28; | |
457 | val |= (u32)direct << 27; | |
458 | val |= (u32)nid << 20; | |
459 | val |= verb << 8; | |
460 | val |= para; | |
461 | ||
462 | /* add command to corb */ | |
463 | wp = azx_readb(chip, CORBWP); | |
464 | wp++; | |
465 | wp %= ICH6_MAX_CORB_ENTRIES; | |
466 | ||
467 | spin_lock_irq(&chip->reg_lock); | |
468 | chip->rirb.cmds++; | |
469 | chip->corb.buf[wp] = cpu_to_le32(val); | |
470 | azx_writel(chip, CORBWP, wp); | |
471 | spin_unlock_irq(&chip->reg_lock); | |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
476 | #define ICH6_RIRB_EX_UNSOL_EV (1<<4) | |
477 | ||
478 | /* retrieve RIRB entry - called from interrupt handler */ | |
a98f90fd | 479 | static void azx_update_rirb(struct azx *chip) |
1da177e4 LT |
480 | { |
481 | unsigned int rp, wp; | |
482 | u32 res, res_ex; | |
483 | ||
484 | wp = azx_readb(chip, RIRBWP); | |
485 | if (wp == chip->rirb.wp) | |
486 | return; | |
487 | chip->rirb.wp = wp; | |
488 | ||
489 | while (chip->rirb.rp != wp) { | |
490 | chip->rirb.rp++; | |
491 | chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; | |
492 | ||
493 | rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ | |
494 | res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); | |
495 | res = le32_to_cpu(chip->rirb.buf[rp]); | |
496 | if (res_ex & ICH6_RIRB_EX_UNSOL_EV) | |
497 | snd_hda_queue_unsol_event(chip->bus, res, res_ex); | |
498 | else if (chip->rirb.cmds) { | |
499 | chip->rirb.cmds--; | |
500 | chip->rirb.res = res; | |
501 | } | |
502 | } | |
503 | } | |
504 | ||
505 | /* receive a response */ | |
111d3af5 | 506 | static unsigned int azx_rirb_get_response(struct hda_codec *codec) |
1da177e4 | 507 | { |
a98f90fd | 508 | struct azx *chip = codec->bus->private_data; |
1da177e4 LT |
509 | int timeout = 50; |
510 | ||
511 | while (chip->rirb.cmds) { | |
512 | if (! --timeout) { | |
111d3af5 TI |
513 | snd_printk(KERN_ERR |
514 | "hda_intel: azx_get_response timeout, " | |
515 | "switching to single_cmd mode...\n"); | |
1da177e4 LT |
516 | chip->rirb.rp = azx_readb(chip, RIRBWP); |
517 | chip->rirb.cmds = 0; | |
111d3af5 TI |
518 | /* switch to single_cmd mode */ |
519 | chip->single_cmd = 1; | |
520 | azx_free_cmd_io(chip); | |
1da177e4 LT |
521 | return -1; |
522 | } | |
523 | msleep(1); | |
524 | } | |
525 | return chip->rirb.res; /* the last value */ | |
526 | } | |
527 | ||
1da177e4 LT |
528 | /* |
529 | * Use the single immediate command instead of CORB/RIRB for simplicity | |
530 | * | |
531 | * Note: according to Intel, this is not preferred use. The command was | |
532 | * intended for the BIOS only, and may get confused with unsolicited | |
533 | * responses. So, we shouldn't use it for normal operation from the | |
534 | * driver. | |
535 | * I left the codes, however, for debugging/testing purposes. | |
536 | */ | |
537 | ||
1da177e4 | 538 | /* send a command */ |
27346166 TI |
539 | static int azx_single_send_cmd(struct hda_codec *codec, hda_nid_t nid, |
540 | int direct, unsigned int verb, | |
541 | unsigned int para) | |
1da177e4 | 542 | { |
a98f90fd | 543 | struct azx *chip = codec->bus->private_data; |
1da177e4 LT |
544 | u32 val; |
545 | int timeout = 50; | |
546 | ||
547 | val = (u32)(codec->addr & 0x0f) << 28; | |
548 | val |= (u32)direct << 27; | |
549 | val |= (u32)nid << 20; | |
550 | val |= verb << 8; | |
551 | val |= para; | |
552 | ||
553 | while (timeout--) { | |
554 | /* check ICB busy bit */ | |
555 | if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) { | |
556 | /* Clear IRV valid bit */ | |
557 | azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID); | |
558 | azx_writel(chip, IC, val); | |
559 | azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY); | |
560 | return 0; | |
561 | } | |
562 | udelay(1); | |
563 | } | |
564 | snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val); | |
565 | return -EIO; | |
566 | } | |
567 | ||
568 | /* receive a response */ | |
27346166 | 569 | static unsigned int azx_single_get_response(struct hda_codec *codec) |
1da177e4 | 570 | { |
a98f90fd | 571 | struct azx *chip = codec->bus->private_data; |
1da177e4 LT |
572 | int timeout = 50; |
573 | ||
574 | while (timeout--) { | |
575 | /* check IRV busy bit */ | |
576 | if (azx_readw(chip, IRS) & ICH6_IRS_VALID) | |
577 | return azx_readl(chip, IR); | |
578 | udelay(1); | |
579 | } | |
580 | snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS)); | |
581 | return (unsigned int)-1; | |
582 | } | |
583 | ||
111d3af5 TI |
584 | /* |
585 | * The below are the main callbacks from hda_codec. | |
586 | * | |
587 | * They are just the skeleton to call sub-callbacks according to the | |
588 | * current setting of chip->single_cmd. | |
589 | */ | |
590 | ||
591 | /* send a command */ | |
592 | static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, | |
593 | int direct, unsigned int verb, | |
594 | unsigned int para) | |
595 | { | |
596 | struct azx *chip = codec->bus->private_data; | |
597 | if (chip->single_cmd) | |
598 | return azx_single_send_cmd(codec, nid, direct, verb, para); | |
599 | else | |
600 | return azx_corb_send_cmd(codec, nid, direct, verb, para); | |
601 | } | |
602 | ||
603 | /* get a response */ | |
604 | static unsigned int azx_get_response(struct hda_codec *codec) | |
605 | { | |
606 | struct azx *chip = codec->bus->private_data; | |
607 | if (chip->single_cmd) | |
608 | return azx_single_get_response(codec); | |
609 | else | |
610 | return azx_rirb_get_response(codec); | |
611 | } | |
612 | ||
613 | ||
1da177e4 | 614 | /* reset codec link */ |
a98f90fd | 615 | static int azx_reset(struct azx *chip) |
1da177e4 LT |
616 | { |
617 | int count; | |
618 | ||
619 | /* reset controller */ | |
620 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); | |
621 | ||
622 | count = 50; | |
623 | while (azx_readb(chip, GCTL) && --count) | |
624 | msleep(1); | |
625 | ||
626 | /* delay for >= 100us for codec PLL to settle per spec | |
627 | * Rev 0.9 section 5.5.1 | |
628 | */ | |
629 | msleep(1); | |
630 | ||
631 | /* Bring controller out of reset */ | |
632 | azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); | |
633 | ||
634 | count = 50; | |
635 | while (! azx_readb(chip, GCTL) && --count) | |
636 | msleep(1); | |
637 | ||
638 | /* Brent Chartrand said to wait >= 540us for codecs to intialize */ | |
639 | msleep(1); | |
640 | ||
641 | /* check to see if controller is ready */ | |
642 | if (! azx_readb(chip, GCTL)) { | |
643 | snd_printd("azx_reset: controller not ready!\n"); | |
644 | return -EBUSY; | |
645 | } | |
646 | ||
41e2fce4 M |
647 | /* Accept unsolicited responses */ |
648 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN); | |
649 | ||
1da177e4 LT |
650 | /* detect codecs */ |
651 | if (! chip->codec_mask) { | |
652 | chip->codec_mask = azx_readw(chip, STATESTS); | |
653 | snd_printdd("codec_mask = 0x%x\n", chip->codec_mask); | |
654 | } | |
655 | ||
656 | return 0; | |
657 | } | |
658 | ||
659 | ||
660 | /* | |
661 | * Lowlevel interface | |
662 | */ | |
663 | ||
664 | /* enable interrupts */ | |
a98f90fd | 665 | static void azx_int_enable(struct azx *chip) |
1da177e4 LT |
666 | { |
667 | /* enable controller CIE and GIE */ | |
668 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | | |
669 | ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); | |
670 | } | |
671 | ||
672 | /* disable interrupts */ | |
a98f90fd | 673 | static void azx_int_disable(struct azx *chip) |
1da177e4 LT |
674 | { |
675 | int i; | |
676 | ||
677 | /* disable interrupts in stream descriptor */ | |
07e4ca50 | 678 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 679 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
680 | azx_sd_writeb(azx_dev, SD_CTL, |
681 | azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); | |
682 | } | |
683 | ||
684 | /* disable SIE for all streams */ | |
685 | azx_writeb(chip, INTCTL, 0); | |
686 | ||
687 | /* disable controller CIE and GIE */ | |
688 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & | |
689 | ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); | |
690 | } | |
691 | ||
692 | /* clear interrupts */ | |
a98f90fd | 693 | static void azx_int_clear(struct azx *chip) |
1da177e4 LT |
694 | { |
695 | int i; | |
696 | ||
697 | /* clear stream status */ | |
07e4ca50 | 698 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 699 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
700 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); |
701 | } | |
702 | ||
703 | /* clear STATESTS */ | |
704 | azx_writeb(chip, STATESTS, STATESTS_INT_MASK); | |
705 | ||
706 | /* clear rirb status */ | |
707 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
708 | ||
709 | /* clear int status */ | |
710 | azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); | |
711 | } | |
712 | ||
713 | /* start a stream */ | |
a98f90fd | 714 | static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) |
1da177e4 LT |
715 | { |
716 | /* enable SIE */ | |
717 | azx_writeb(chip, INTCTL, | |
718 | azx_readb(chip, INTCTL) | (1 << azx_dev->index)); | |
719 | /* set DMA start and interrupt mask */ | |
720 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | | |
721 | SD_CTL_DMA_START | SD_INT_MASK); | |
722 | } | |
723 | ||
724 | /* stop a stream */ | |
a98f90fd | 725 | static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) |
1da177e4 LT |
726 | { |
727 | /* stop DMA */ | |
728 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & | |
729 | ~(SD_CTL_DMA_START | SD_INT_MASK)); | |
730 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | |
731 | /* disable SIE */ | |
732 | azx_writeb(chip, INTCTL, | |
733 | azx_readb(chip, INTCTL) & ~(1 << azx_dev->index)); | |
734 | } | |
735 | ||
736 | ||
737 | /* | |
738 | * initialize the chip | |
739 | */ | |
a98f90fd | 740 | static void azx_init_chip(struct azx *chip) |
1da177e4 | 741 | { |
da3fca21 | 742 | unsigned char reg; |
1da177e4 LT |
743 | |
744 | /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) | |
745 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | |
746 | * Ensuring these bits are 0 clears playback static on some HD Audio codecs | |
747 | */ | |
da3fca21 V |
748 | pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, ®); |
749 | pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, reg & 0xf8); | |
1da177e4 LT |
750 | |
751 | /* reset controller */ | |
752 | azx_reset(chip); | |
753 | ||
754 | /* initialize interrupts */ | |
755 | azx_int_clear(chip); | |
756 | azx_int_enable(chip); | |
757 | ||
758 | /* initialize the codec command I/O */ | |
27346166 TI |
759 | if (! chip->single_cmd) |
760 | azx_init_cmd_io(chip); | |
1da177e4 | 761 | |
0be3b5d3 TI |
762 | /* program the position buffer */ |
763 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); | |
764 | azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr)); | |
f5d40b30 | 765 | |
da3fca21 V |
766 | switch (chip->driver_type) { |
767 | case AZX_DRIVER_ATI: | |
768 | /* For ATI SB450 azalia HD audio, we need to enable snoop */ | |
f5d40b30 | 769 | pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, |
da3fca21 | 770 | ®); |
f5d40b30 | 771 | pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, |
da3fca21 V |
772 | (reg & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP); |
773 | break; | |
774 | case AZX_DRIVER_NVIDIA: | |
775 | /* For NVIDIA HDA, enable snoop */ | |
776 | pci_read_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, ®); | |
777 | pci_write_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, | |
778 | (reg & 0xf0) | NVIDIA_HDA_ENABLE_COHBITS); | |
779 | break; | |
780 | } | |
1da177e4 LT |
781 | } |
782 | ||
783 | ||
784 | /* | |
785 | * interrupt handler | |
786 | */ | |
787 | static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs) | |
788 | { | |
a98f90fd TI |
789 | struct azx *chip = dev_id; |
790 | struct azx_dev *azx_dev; | |
1da177e4 LT |
791 | u32 status; |
792 | int i; | |
793 | ||
794 | spin_lock(&chip->reg_lock); | |
795 | ||
796 | status = azx_readl(chip, INTSTS); | |
797 | if (status == 0) { | |
798 | spin_unlock(&chip->reg_lock); | |
799 | return IRQ_NONE; | |
800 | } | |
801 | ||
07e4ca50 | 802 | for (i = 0; i < chip->num_streams; i++) { |
1da177e4 LT |
803 | azx_dev = &chip->azx_dev[i]; |
804 | if (status & azx_dev->sd_int_sta_mask) { | |
805 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); | |
806 | if (azx_dev->substream && azx_dev->running) { | |
1a56f8d6 | 807 | azx_dev->period_intr++; |
1da177e4 LT |
808 | spin_unlock(&chip->reg_lock); |
809 | snd_pcm_period_elapsed(azx_dev->substream); | |
810 | spin_lock(&chip->reg_lock); | |
811 | } | |
812 | } | |
813 | } | |
814 | ||
815 | /* clear rirb int */ | |
816 | status = azx_readb(chip, RIRBSTS); | |
817 | if (status & RIRB_INT_MASK) { | |
27346166 | 818 | if (! chip->single_cmd && (status & RIRB_INT_RESPONSE)) |
1da177e4 LT |
819 | azx_update_rirb(chip); |
820 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
821 | } | |
822 | ||
823 | #if 0 | |
824 | /* clear state status int */ | |
825 | if (azx_readb(chip, STATESTS) & 0x04) | |
826 | azx_writeb(chip, STATESTS, 0x04); | |
827 | #endif | |
828 | spin_unlock(&chip->reg_lock); | |
829 | ||
830 | return IRQ_HANDLED; | |
831 | } | |
832 | ||
833 | ||
834 | /* | |
835 | * set up BDL entries | |
836 | */ | |
a98f90fd | 837 | static void azx_setup_periods(struct azx_dev *azx_dev) |
1da177e4 LT |
838 | { |
839 | u32 *bdl = azx_dev->bdl; | |
840 | dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr; | |
841 | int idx; | |
842 | ||
843 | /* reset BDL address */ | |
844 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
845 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
846 | ||
847 | /* program the initial BDL entries */ | |
848 | for (idx = 0; idx < azx_dev->frags; idx++) { | |
849 | unsigned int off = idx << 2; /* 4 dword step */ | |
850 | dma_addr_t addr = dma_addr + idx * azx_dev->fragsize; | |
851 | /* program the address field of the BDL entry */ | |
852 | bdl[off] = cpu_to_le32((u32)addr); | |
853 | bdl[off+1] = cpu_to_le32(upper_32bit(addr)); | |
854 | ||
855 | /* program the size field of the BDL entry */ | |
856 | bdl[off+2] = cpu_to_le32(azx_dev->fragsize); | |
857 | ||
858 | /* program the IOC to enable interrupt when buffer completes */ | |
859 | bdl[off+3] = cpu_to_le32(0x01); | |
860 | } | |
861 | } | |
862 | ||
863 | /* | |
864 | * set up the SD for streaming | |
865 | */ | |
a98f90fd | 866 | static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) |
1da177e4 LT |
867 | { |
868 | unsigned char val; | |
869 | int timeout; | |
870 | ||
871 | /* make sure the run bit is zero for SD */ | |
872 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START); | |
873 | /* reset stream */ | |
874 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET); | |
875 | udelay(3); | |
876 | timeout = 300; | |
877 | while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
878 | --timeout) | |
879 | ; | |
880 | val &= ~SD_CTL_STREAM_RESET; | |
881 | azx_sd_writeb(azx_dev, SD_CTL, val); | |
882 | udelay(3); | |
883 | ||
884 | timeout = 300; | |
885 | /* waiting for hardware to report that the stream is out of reset */ | |
886 | while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
887 | --timeout) | |
888 | ; | |
889 | ||
890 | /* program the stream_tag */ | |
891 | azx_sd_writel(azx_dev, SD_CTL, | |
892 | (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) | | |
893 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); | |
894 | ||
895 | /* program the length of samples in cyclic buffer */ | |
896 | azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); | |
897 | ||
898 | /* program the stream format */ | |
899 | /* this value needs to be the same as the one programmed */ | |
900 | azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); | |
901 | ||
902 | /* program the stream LVI (last valid index) of the BDL */ | |
903 | azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); | |
904 | ||
905 | /* program the BDL address */ | |
906 | /* lower BDL address */ | |
907 | azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr); | |
908 | /* upper BDL address */ | |
909 | azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr)); | |
910 | ||
0be3b5d3 TI |
911 | /* enable the position buffer */ |
912 | if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) | |
913 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); | |
c74db86b | 914 | |
1da177e4 LT |
915 | /* set the interrupt enable bits in the descriptor control register */ |
916 | azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); | |
917 | ||
918 | return 0; | |
919 | } | |
920 | ||
921 | ||
922 | /* | |
923 | * Codec initialization | |
924 | */ | |
925 | ||
a98f90fd | 926 | static int __devinit azx_codec_create(struct azx *chip, const char *model) |
1da177e4 LT |
927 | { |
928 | struct hda_bus_template bus_temp; | |
929 | int c, codecs, err; | |
930 | ||
931 | memset(&bus_temp, 0, sizeof(bus_temp)); | |
932 | bus_temp.private_data = chip; | |
933 | bus_temp.modelname = model; | |
934 | bus_temp.pci = chip->pci; | |
111d3af5 TI |
935 | bus_temp.ops.command = azx_send_cmd; |
936 | bus_temp.ops.get_response = azx_get_response; | |
1da177e4 LT |
937 | |
938 | if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0) | |
939 | return err; | |
940 | ||
941 | codecs = 0; | |
942 | for (c = 0; c < AZX_MAX_CODECS; c++) { | |
606ad75f | 943 | if ((chip->codec_mask & (1 << c)) & probe_mask) { |
1da177e4 LT |
944 | err = snd_hda_codec_new(chip->bus, c, NULL); |
945 | if (err < 0) | |
946 | continue; | |
947 | codecs++; | |
948 | } | |
949 | } | |
950 | if (! codecs) { | |
951 | snd_printk(KERN_ERR SFX "no codecs initialized\n"); | |
952 | return -ENXIO; | |
953 | } | |
954 | ||
955 | return 0; | |
956 | } | |
957 | ||
958 | ||
959 | /* | |
960 | * PCM support | |
961 | */ | |
962 | ||
963 | /* assign a stream for the PCM */ | |
a98f90fd | 964 | static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream) |
1da177e4 | 965 | { |
07e4ca50 TI |
966 | int dev, i, nums; |
967 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
968 | dev = chip->playback_index_offset; | |
969 | nums = chip->playback_streams; | |
970 | } else { | |
971 | dev = chip->capture_index_offset; | |
972 | nums = chip->capture_streams; | |
973 | } | |
974 | for (i = 0; i < nums; i++, dev++) | |
1da177e4 LT |
975 | if (! chip->azx_dev[dev].opened) { |
976 | chip->azx_dev[dev].opened = 1; | |
977 | return &chip->azx_dev[dev]; | |
978 | } | |
979 | return NULL; | |
980 | } | |
981 | ||
982 | /* release the assigned stream */ | |
a98f90fd | 983 | static inline void azx_release_device(struct azx_dev *azx_dev) |
1da177e4 LT |
984 | { |
985 | azx_dev->opened = 0; | |
986 | } | |
987 | ||
a98f90fd | 988 | static struct snd_pcm_hardware azx_pcm_hw = { |
1da177e4 LT |
989 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | |
990 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
991 | SNDRV_PCM_INFO_MMAP_VALID | | |
47123197 JK |
992 | SNDRV_PCM_INFO_PAUSE /*|*/ |
993 | /*SNDRV_PCM_INFO_RESUME*/), | |
1da177e4 LT |
994 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
995 | .rates = SNDRV_PCM_RATE_48000, | |
996 | .rate_min = 48000, | |
997 | .rate_max = 48000, | |
998 | .channels_min = 2, | |
999 | .channels_max = 2, | |
1000 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, | |
1001 | .period_bytes_min = 128, | |
1002 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | |
1003 | .periods_min = 2, | |
1004 | .periods_max = AZX_MAX_FRAG, | |
1005 | .fifo_size = 0, | |
1006 | }; | |
1007 | ||
1008 | struct azx_pcm { | |
a98f90fd | 1009 | struct azx *chip; |
1da177e4 LT |
1010 | struct hda_codec *codec; |
1011 | struct hda_pcm_stream *hinfo[2]; | |
1012 | }; | |
1013 | ||
a98f90fd | 1014 | static int azx_pcm_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
1015 | { |
1016 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1017 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
a98f90fd TI |
1018 | struct azx *chip = apcm->chip; |
1019 | struct azx_dev *azx_dev; | |
1020 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1021 | unsigned long flags; |
1022 | int err; | |
1023 | ||
62932df8 | 1024 | mutex_lock(&chip->open_mutex); |
1da177e4 LT |
1025 | azx_dev = azx_assign_device(chip, substream->stream); |
1026 | if (azx_dev == NULL) { | |
62932df8 | 1027 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1028 | return -EBUSY; |
1029 | } | |
1030 | runtime->hw = azx_pcm_hw; | |
1031 | runtime->hw.channels_min = hinfo->channels_min; | |
1032 | runtime->hw.channels_max = hinfo->channels_max; | |
1033 | runtime->hw.formats = hinfo->formats; | |
1034 | runtime->hw.rates = hinfo->rates; | |
1035 | snd_pcm_limit_hw_rates(runtime); | |
1036 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | |
1037 | if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) { | |
1038 | azx_release_device(azx_dev); | |
62932df8 | 1039 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1040 | return err; |
1041 | } | |
1042 | spin_lock_irqsave(&chip->reg_lock, flags); | |
1043 | azx_dev->substream = substream; | |
1044 | azx_dev->running = 0; | |
1045 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
1046 | ||
1047 | runtime->private_data = azx_dev; | |
62932df8 | 1048 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1049 | return 0; |
1050 | } | |
1051 | ||
a98f90fd | 1052 | static int azx_pcm_close(struct snd_pcm_substream *substream) |
1da177e4 LT |
1053 | { |
1054 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1055 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
a98f90fd TI |
1056 | struct azx *chip = apcm->chip; |
1057 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 LT |
1058 | unsigned long flags; |
1059 | ||
62932df8 | 1060 | mutex_lock(&chip->open_mutex); |
1da177e4 LT |
1061 | spin_lock_irqsave(&chip->reg_lock, flags); |
1062 | azx_dev->substream = NULL; | |
1063 | azx_dev->running = 0; | |
1064 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
1065 | azx_release_device(azx_dev); | |
1066 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
62932df8 | 1067 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1068 | return 0; |
1069 | } | |
1070 | ||
a98f90fd | 1071 | static int azx_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) |
1da177e4 LT |
1072 | { |
1073 | return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
1074 | } | |
1075 | ||
a98f90fd | 1076 | static int azx_pcm_hw_free(struct snd_pcm_substream *substream) |
1da177e4 LT |
1077 | { |
1078 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd | 1079 | struct azx_dev *azx_dev = get_azx_dev(substream); |
1da177e4 LT |
1080 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
1081 | ||
1082 | /* reset BDL address */ | |
1083 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
1084 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
1085 | azx_sd_writel(azx_dev, SD_CTL, 0); | |
1086 | ||
1087 | hinfo->ops.cleanup(hinfo, apcm->codec, substream); | |
1088 | ||
1089 | return snd_pcm_lib_free_pages(substream); | |
1090 | } | |
1091 | ||
a98f90fd | 1092 | static int azx_pcm_prepare(struct snd_pcm_substream *substream) |
1da177e4 LT |
1093 | { |
1094 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd TI |
1095 | struct azx *chip = apcm->chip; |
1096 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 | 1097 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
a98f90fd | 1098 | struct snd_pcm_runtime *runtime = substream->runtime; |
1da177e4 LT |
1099 | |
1100 | azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream); | |
1101 | azx_dev->fragsize = snd_pcm_lib_period_bytes(substream); | |
1102 | azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize; | |
1103 | azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate, | |
1104 | runtime->channels, | |
1105 | runtime->format, | |
1106 | hinfo->maxbps); | |
1107 | if (! azx_dev->format_val) { | |
1108 | snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n", | |
1109 | runtime->rate, runtime->channels, runtime->format); | |
1110 | return -EINVAL; | |
1111 | } | |
1112 | ||
1113 | snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n", | |
1114 | azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val); | |
1115 | azx_setup_periods(azx_dev); | |
1116 | azx_setup_controller(chip, azx_dev); | |
1117 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1118 | azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; | |
1119 | else | |
1120 | azx_dev->fifo_size = 0; | |
1121 | ||
1122 | return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag, | |
1123 | azx_dev->format_val, substream); | |
1124 | } | |
1125 | ||
a98f90fd | 1126 | static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 LT |
1127 | { |
1128 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd TI |
1129 | struct azx_dev *azx_dev = get_azx_dev(substream); |
1130 | struct azx *chip = apcm->chip; | |
1da177e4 LT |
1131 | int err = 0; |
1132 | ||
1133 | spin_lock(&chip->reg_lock); | |
1134 | switch (cmd) { | |
1135 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
1136 | case SNDRV_PCM_TRIGGER_RESUME: | |
1137 | case SNDRV_PCM_TRIGGER_START: | |
1138 | azx_stream_start(chip, azx_dev); | |
1139 | azx_dev->running = 1; | |
1140 | break; | |
1141 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
47123197 | 1142 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1da177e4 LT |
1143 | case SNDRV_PCM_TRIGGER_STOP: |
1144 | azx_stream_stop(chip, azx_dev); | |
1145 | azx_dev->running = 0; | |
1146 | break; | |
1147 | default: | |
1148 | err = -EINVAL; | |
1149 | } | |
1150 | spin_unlock(&chip->reg_lock); | |
1151 | if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH || | |
47123197 | 1152 | cmd == SNDRV_PCM_TRIGGER_SUSPEND || |
1da177e4 LT |
1153 | cmd == SNDRV_PCM_TRIGGER_STOP) { |
1154 | int timeout = 5000; | |
1155 | while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout) | |
1156 | ; | |
1157 | } | |
1158 | return err; | |
1159 | } | |
1160 | ||
a98f90fd | 1161 | static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 1162 | { |
c74db86b | 1163 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
a98f90fd TI |
1164 | struct azx *chip = apcm->chip; |
1165 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 LT |
1166 | unsigned int pos; |
1167 | ||
1a56f8d6 TI |
1168 | if (chip->position_fix == POS_FIX_POSBUF || |
1169 | chip->position_fix == POS_FIX_AUTO) { | |
c74db86b TI |
1170 | /* use the position buffer */ |
1171 | pos = *azx_dev->posbuf; | |
1a56f8d6 TI |
1172 | if (chip->position_fix == POS_FIX_AUTO && |
1173 | azx_dev->period_intr == 1 && ! pos) { | |
1174 | printk(KERN_WARNING | |
1175 | "hda-intel: Invalid position buffer, " | |
1176 | "using LPIB read method instead.\n"); | |
1177 | chip->position_fix = POS_FIX_NONE; | |
1178 | goto read_lpib; | |
1179 | } | |
c74db86b | 1180 | } else { |
1a56f8d6 | 1181 | read_lpib: |
c74db86b TI |
1182 | /* read LPIB */ |
1183 | pos = azx_sd_readl(azx_dev, SD_LPIB); | |
1184 | if (chip->position_fix == POS_FIX_FIFO) | |
1185 | pos += azx_dev->fifo_size; | |
1186 | } | |
1da177e4 LT |
1187 | if (pos >= azx_dev->bufsize) |
1188 | pos = 0; | |
1189 | return bytes_to_frames(substream->runtime, pos); | |
1190 | } | |
1191 | ||
a98f90fd | 1192 | static struct snd_pcm_ops azx_pcm_ops = { |
1da177e4 LT |
1193 | .open = azx_pcm_open, |
1194 | .close = azx_pcm_close, | |
1195 | .ioctl = snd_pcm_lib_ioctl, | |
1196 | .hw_params = azx_pcm_hw_params, | |
1197 | .hw_free = azx_pcm_hw_free, | |
1198 | .prepare = azx_pcm_prepare, | |
1199 | .trigger = azx_pcm_trigger, | |
1200 | .pointer = azx_pcm_pointer, | |
1201 | }; | |
1202 | ||
a98f90fd | 1203 | static void azx_pcm_free(struct snd_pcm *pcm) |
1da177e4 LT |
1204 | { |
1205 | kfree(pcm->private_data); | |
1206 | } | |
1207 | ||
a98f90fd | 1208 | static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec, |
1da177e4 LT |
1209 | struct hda_pcm *cpcm, int pcm_dev) |
1210 | { | |
1211 | int err; | |
a98f90fd | 1212 | struct snd_pcm *pcm; |
1da177e4 LT |
1213 | struct azx_pcm *apcm; |
1214 | ||
1215 | snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL); | |
1216 | snd_assert(cpcm->name, return -EINVAL); | |
1217 | ||
1218 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, | |
1219 | cpcm->stream[0].substreams, cpcm->stream[1].substreams, | |
1220 | &pcm); | |
1221 | if (err < 0) | |
1222 | return err; | |
1223 | strcpy(pcm->name, cpcm->name); | |
1224 | apcm = kmalloc(sizeof(*apcm), GFP_KERNEL); | |
1225 | if (apcm == NULL) | |
1226 | return -ENOMEM; | |
1227 | apcm->chip = chip; | |
1228 | apcm->codec = codec; | |
1229 | apcm->hinfo[0] = &cpcm->stream[0]; | |
1230 | apcm->hinfo[1] = &cpcm->stream[1]; | |
1231 | pcm->private_data = apcm; | |
1232 | pcm->private_free = azx_pcm_free; | |
1233 | if (cpcm->stream[0].substreams) | |
1234 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops); | |
1235 | if (cpcm->stream[1].substreams) | |
1236 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops); | |
1237 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1238 | snd_dma_pci_data(chip->pci), | |
1239 | 1024 * 64, 1024 * 128); | |
1240 | chip->pcm[pcm_dev] = pcm; | |
47123197 | 1241 | chip->pcm_devs = pcm_dev + 1; |
1da177e4 LT |
1242 | |
1243 | return 0; | |
1244 | } | |
1245 | ||
a98f90fd | 1246 | static int __devinit azx_pcm_create(struct azx *chip) |
1da177e4 LT |
1247 | { |
1248 | struct list_head *p; | |
1249 | struct hda_codec *codec; | |
1250 | int c, err; | |
1251 | int pcm_dev; | |
1252 | ||
1253 | if ((err = snd_hda_build_pcms(chip->bus)) < 0) | |
1254 | return err; | |
1255 | ||
ec9e1c5c | 1256 | /* create audio PCMs */ |
1da177e4 LT |
1257 | pcm_dev = 0; |
1258 | list_for_each(p, &chip->bus->codec_list) { | |
1259 | codec = list_entry(p, struct hda_codec, list); | |
1260 | for (c = 0; c < codec->num_pcms; c++) { | |
ec9e1c5c TI |
1261 | if (codec->pcm_info[c].is_modem) |
1262 | continue; /* create later */ | |
1263 | if (pcm_dev >= AZX_MAX_AUDIO_PCMS) { | |
1264 | snd_printk(KERN_ERR SFX "Too many audio PCMs\n"); | |
1265 | return -EINVAL; | |
1266 | } | |
1267 | err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev); | |
1268 | if (err < 0) | |
1269 | return err; | |
1270 | pcm_dev++; | |
1271 | } | |
1272 | } | |
1273 | ||
1274 | /* create modem PCMs */ | |
1275 | pcm_dev = AZX_MAX_AUDIO_PCMS; | |
1276 | list_for_each(p, &chip->bus->codec_list) { | |
1277 | codec = list_entry(p, struct hda_codec, list); | |
1278 | for (c = 0; c < codec->num_pcms; c++) { | |
1279 | if (! codec->pcm_info[c].is_modem) | |
1280 | continue; /* already created */ | |
a28f1cda | 1281 | if (pcm_dev >= AZX_MAX_PCMS) { |
ec9e1c5c | 1282 | snd_printk(KERN_ERR SFX "Too many modem PCMs\n"); |
1da177e4 LT |
1283 | return -EINVAL; |
1284 | } | |
1285 | err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev); | |
1286 | if (err < 0) | |
1287 | return err; | |
6632d198 | 1288 | chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM; |
1da177e4 LT |
1289 | pcm_dev++; |
1290 | } | |
1291 | } | |
1292 | return 0; | |
1293 | } | |
1294 | ||
1295 | /* | |
1296 | * mixer creation - all stuff is implemented in hda module | |
1297 | */ | |
a98f90fd | 1298 | static int __devinit azx_mixer_create(struct azx *chip) |
1da177e4 LT |
1299 | { |
1300 | return snd_hda_build_controls(chip->bus); | |
1301 | } | |
1302 | ||
1303 | ||
1304 | /* | |
1305 | * initialize SD streams | |
1306 | */ | |
a98f90fd | 1307 | static int __devinit azx_init_stream(struct azx *chip) |
1da177e4 LT |
1308 | { |
1309 | int i; | |
1310 | ||
1311 | /* initialize each stream (aka device) | |
1312 | * assign the starting bdl address to each stream (device) and initialize | |
1313 | */ | |
07e4ca50 | 1314 | for (i = 0; i < chip->num_streams; i++) { |
1da177e4 | 1315 | unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4); |
a98f90fd | 1316 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
1317 | azx_dev->bdl = (u32 *)(chip->bdl.area + off); |
1318 | azx_dev->bdl_addr = chip->bdl.addr + off; | |
0be3b5d3 | 1319 | azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8); |
1da177e4 LT |
1320 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
1321 | azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); | |
1322 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ | |
1323 | azx_dev->sd_int_sta_mask = 1 << i; | |
1324 | /* stream tag: must be non-zero and unique */ | |
1325 | azx_dev->index = i; | |
1326 | azx_dev->stream_tag = i + 1; | |
1327 | } | |
1328 | ||
1329 | return 0; | |
1330 | } | |
1331 | ||
1332 | ||
1333 | #ifdef CONFIG_PM | |
1334 | /* | |
1335 | * power management | |
1336 | */ | |
421a1252 | 1337 | static int azx_suspend(struct pci_dev *pci, pm_message_t state) |
1da177e4 | 1338 | { |
421a1252 TI |
1339 | struct snd_card *card = pci_get_drvdata(pci); |
1340 | struct azx *chip = card->private_data; | |
1da177e4 LT |
1341 | int i; |
1342 | ||
421a1252 | 1343 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
1da177e4 | 1344 | for (i = 0; i < chip->pcm_devs; i++) |
421a1252 | 1345 | snd_pcm_suspend_all(chip->pcm[i]); |
1da177e4 | 1346 | snd_hda_suspend(chip->bus, state); |
111d3af5 | 1347 | azx_free_cmd_io(chip); |
421a1252 TI |
1348 | pci_disable_device(pci); |
1349 | pci_save_state(pci); | |
1da177e4 LT |
1350 | return 0; |
1351 | } | |
1352 | ||
421a1252 | 1353 | static int azx_resume(struct pci_dev *pci) |
1da177e4 | 1354 | { |
421a1252 TI |
1355 | struct snd_card *card = pci_get_drvdata(pci); |
1356 | struct azx *chip = card->private_data; | |
1da177e4 | 1357 | |
421a1252 TI |
1358 | pci_restore_state(pci); |
1359 | pci_enable_device(pci); | |
1360 | pci_set_master(pci); | |
1da177e4 LT |
1361 | azx_init_chip(chip); |
1362 | snd_hda_resume(chip->bus); | |
421a1252 | 1363 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
1da177e4 LT |
1364 | return 0; |
1365 | } | |
1366 | #endif /* CONFIG_PM */ | |
1367 | ||
1368 | ||
1369 | /* | |
1370 | * destructor | |
1371 | */ | |
a98f90fd | 1372 | static int azx_free(struct azx *chip) |
1da177e4 | 1373 | { |
ce43fbae | 1374 | if (chip->initialized) { |
1da177e4 LT |
1375 | int i; |
1376 | ||
07e4ca50 | 1377 | for (i = 0; i < chip->num_streams; i++) |
1da177e4 LT |
1378 | azx_stream_stop(chip, &chip->azx_dev[i]); |
1379 | ||
1380 | /* disable interrupts */ | |
1381 | azx_int_disable(chip); | |
1382 | azx_int_clear(chip); | |
1383 | ||
1384 | /* disable CORB/RIRB */ | |
111d3af5 | 1385 | azx_free_cmd_io(chip); |
1da177e4 LT |
1386 | |
1387 | /* disable position buffer */ | |
1388 | azx_writel(chip, DPLBASE, 0); | |
1389 | azx_writel(chip, DPUBASE, 0); | |
1390 | ||
1391 | /* wait a little for interrupts to finish */ | |
1392 | msleep(1); | |
1da177e4 LT |
1393 | } |
1394 | ||
07e4ca50 TI |
1395 | if (chip->remap_addr) |
1396 | iounmap(chip->remap_addr); | |
1da177e4 LT |
1397 | if (chip->irq >= 0) |
1398 | free_irq(chip->irq, (void*)chip); | |
1399 | ||
1400 | if (chip->bdl.area) | |
1401 | snd_dma_free_pages(&chip->bdl); | |
1402 | if (chip->rb.area) | |
1403 | snd_dma_free_pages(&chip->rb); | |
1da177e4 LT |
1404 | if (chip->posbuf.area) |
1405 | snd_dma_free_pages(&chip->posbuf); | |
1da177e4 LT |
1406 | pci_release_regions(chip->pci); |
1407 | pci_disable_device(chip->pci); | |
07e4ca50 | 1408 | kfree(chip->azx_dev); |
1da177e4 LT |
1409 | kfree(chip); |
1410 | ||
1411 | return 0; | |
1412 | } | |
1413 | ||
a98f90fd | 1414 | static int azx_dev_free(struct snd_device *device) |
1da177e4 LT |
1415 | { |
1416 | return azx_free(device->device_data); | |
1417 | } | |
1418 | ||
1419 | /* | |
1420 | * constructor | |
1421 | */ | |
a98f90fd | 1422 | static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci, |
606ad75f | 1423 | int driver_type, |
a98f90fd | 1424 | struct azx **rchip) |
1da177e4 | 1425 | { |
a98f90fd | 1426 | struct azx *chip; |
1da177e4 | 1427 | int err = 0; |
a98f90fd | 1428 | static struct snd_device_ops ops = { |
1da177e4 LT |
1429 | .dev_free = azx_dev_free, |
1430 | }; | |
1431 | ||
1432 | *rchip = NULL; | |
1433 | ||
1434 | if ((err = pci_enable_device(pci)) < 0) | |
1435 | return err; | |
1436 | ||
e560d8d8 | 1437 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
1da177e4 LT |
1438 | |
1439 | if (NULL == chip) { | |
1440 | snd_printk(KERN_ERR SFX "cannot allocate chip\n"); | |
1441 | pci_disable_device(pci); | |
1442 | return -ENOMEM; | |
1443 | } | |
1444 | ||
1445 | spin_lock_init(&chip->reg_lock); | |
62932df8 | 1446 | mutex_init(&chip->open_mutex); |
1da177e4 LT |
1447 | chip->card = card; |
1448 | chip->pci = pci; | |
1449 | chip->irq = -1; | |
07e4ca50 | 1450 | chip->driver_type = driver_type; |
1da177e4 | 1451 | |
1a56f8d6 | 1452 | chip->position_fix = position_fix; |
27346166 | 1453 | chip->single_cmd = single_cmd; |
c74db86b | 1454 | |
07e4ca50 TI |
1455 | #if BITS_PER_LONG != 64 |
1456 | /* Fix up base address on ULI M5461 */ | |
1457 | if (chip->driver_type == AZX_DRIVER_ULI) { | |
1458 | u16 tmp3; | |
1459 | pci_read_config_word(pci, 0x40, &tmp3); | |
1460 | pci_write_config_word(pci, 0x40, tmp3 | 0x10); | |
1461 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); | |
1462 | } | |
1463 | #endif | |
1464 | ||
1da177e4 LT |
1465 | if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) { |
1466 | kfree(chip); | |
1467 | pci_disable_device(pci); | |
1468 | return err; | |
1469 | } | |
1470 | ||
1471 | chip->addr = pci_resource_start(pci,0); | |
1472 | chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0)); | |
1473 | if (chip->remap_addr == NULL) { | |
1474 | snd_printk(KERN_ERR SFX "ioremap error\n"); | |
1475 | err = -ENXIO; | |
1476 | goto errout; | |
1477 | } | |
1478 | ||
1479 | if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ, | |
1480 | "HDA Intel", (void*)chip)) { | |
1481 | snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq); | |
1482 | err = -EBUSY; | |
1483 | goto errout; | |
1484 | } | |
1485 | chip->irq = pci->irq; | |
1486 | ||
1487 | pci_set_master(pci); | |
1488 | synchronize_irq(chip->irq); | |
1489 | ||
07e4ca50 TI |
1490 | switch (chip->driver_type) { |
1491 | case AZX_DRIVER_ULI: | |
1492 | chip->playback_streams = ULI_NUM_PLAYBACK; | |
1493 | chip->capture_streams = ULI_NUM_CAPTURE; | |
1494 | chip->playback_index_offset = ULI_PLAYBACK_INDEX; | |
1495 | chip->capture_index_offset = ULI_CAPTURE_INDEX; | |
1496 | break; | |
1497 | default: | |
1498 | chip->playback_streams = ICH6_NUM_PLAYBACK; | |
1499 | chip->capture_streams = ICH6_NUM_CAPTURE; | |
1500 | chip->playback_index_offset = ICH6_PLAYBACK_INDEX; | |
1501 | chip->capture_index_offset = ICH6_CAPTURE_INDEX; | |
1502 | break; | |
1503 | } | |
1504 | chip->num_streams = chip->playback_streams + chip->capture_streams; | |
1505 | chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), GFP_KERNEL); | |
1506 | if (! chip->azx_dev) { | |
1507 | snd_printk(KERN_ERR "cannot malloc azx_dev\n"); | |
1508 | goto errout; | |
1509 | } | |
1510 | ||
1da177e4 LT |
1511 | /* allocate memory for the BDL for each stream */ |
1512 | if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
07e4ca50 | 1513 | BDL_SIZE, &chip->bdl)) < 0) { |
1da177e4 LT |
1514 | snd_printk(KERN_ERR SFX "cannot allocate BDL\n"); |
1515 | goto errout; | |
1516 | } | |
0be3b5d3 TI |
1517 | /* allocate memory for the position buffer */ |
1518 | if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
1519 | chip->num_streams * 8, &chip->posbuf)) < 0) { | |
1520 | snd_printk(KERN_ERR SFX "cannot allocate posbuf\n"); | |
1521 | goto errout; | |
1da177e4 | 1522 | } |
1da177e4 | 1523 | /* allocate CORB/RIRB */ |
27346166 TI |
1524 | if (! chip->single_cmd) |
1525 | if ((err = azx_alloc_cmd_io(chip)) < 0) | |
1526 | goto errout; | |
1da177e4 LT |
1527 | |
1528 | /* initialize streams */ | |
1529 | azx_init_stream(chip); | |
1530 | ||
1531 | /* initialize chip */ | |
1532 | azx_init_chip(chip); | |
1533 | ||
ce43fbae TI |
1534 | chip->initialized = 1; |
1535 | ||
1da177e4 LT |
1536 | /* codec detection */ |
1537 | if (! chip->codec_mask) { | |
1538 | snd_printk(KERN_ERR SFX "no codecs found!\n"); | |
1539 | err = -ENODEV; | |
1540 | goto errout; | |
1541 | } | |
1542 | ||
1543 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) { | |
1544 | snd_printk(KERN_ERR SFX "Error creating device [card]!\n"); | |
1545 | goto errout; | |
1546 | } | |
1547 | ||
07e4ca50 TI |
1548 | strcpy(card->driver, "HDA-Intel"); |
1549 | strcpy(card->shortname, driver_short_names[chip->driver_type]); | |
1550 | sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq); | |
1551 | ||
1da177e4 LT |
1552 | *rchip = chip; |
1553 | return 0; | |
1554 | ||
1555 | errout: | |
1556 | azx_free(chip); | |
1557 | return err; | |
1558 | } | |
1559 | ||
1560 | static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) | |
1561 | { | |
a98f90fd TI |
1562 | struct snd_card *card; |
1563 | struct azx *chip; | |
1da177e4 LT |
1564 | int err = 0; |
1565 | ||
b7fe4622 | 1566 | card = snd_card_new(index, id, THIS_MODULE, 0); |
1da177e4 LT |
1567 | if (NULL == card) { |
1568 | snd_printk(KERN_ERR SFX "Error creating card!\n"); | |
1569 | return -ENOMEM; | |
1570 | } | |
1571 | ||
606ad75f | 1572 | if ((err = azx_create(card, pci, pci_id->driver_data, |
07e4ca50 | 1573 | &chip)) < 0) { |
1da177e4 LT |
1574 | snd_card_free(card); |
1575 | return err; | |
1576 | } | |
421a1252 | 1577 | card->private_data = chip; |
1da177e4 | 1578 | |
1da177e4 | 1579 | /* create codec instances */ |
b7fe4622 | 1580 | if ((err = azx_codec_create(chip, model)) < 0) { |
1da177e4 LT |
1581 | snd_card_free(card); |
1582 | return err; | |
1583 | } | |
1584 | ||
1585 | /* create PCM streams */ | |
1586 | if ((err = azx_pcm_create(chip)) < 0) { | |
1587 | snd_card_free(card); | |
1588 | return err; | |
1589 | } | |
1590 | ||
1591 | /* create mixer controls */ | |
1592 | if ((err = azx_mixer_create(chip)) < 0) { | |
1593 | snd_card_free(card); | |
1594 | return err; | |
1595 | } | |
1596 | ||
1da177e4 LT |
1597 | snd_card_set_dev(card, &pci->dev); |
1598 | ||
1599 | if ((err = snd_card_register(card)) < 0) { | |
1600 | snd_card_free(card); | |
1601 | return err; | |
1602 | } | |
1603 | ||
1604 | pci_set_drvdata(pci, card); | |
1da177e4 LT |
1605 | |
1606 | return err; | |
1607 | } | |
1608 | ||
1609 | static void __devexit azx_remove(struct pci_dev *pci) | |
1610 | { | |
1611 | snd_card_free(pci_get_drvdata(pci)); | |
1612 | pci_set_drvdata(pci, NULL); | |
1613 | } | |
1614 | ||
1615 | /* PCI IDs */ | |
1616 | static struct pci_device_id azx_ids[] = { | |
07e4ca50 TI |
1617 | { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */ |
1618 | { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */ | |
1619 | { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */ | |
d2981393 | 1620 | { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */ |
07e4ca50 TI |
1621 | { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */ |
1622 | { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */ | |
1623 | { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */ | |
1624 | { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */ | |
da3fca21 V |
1625 | { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA 026c */ |
1626 | { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA 0371 */ | |
1da177e4 LT |
1627 | { 0, } |
1628 | }; | |
1629 | MODULE_DEVICE_TABLE(pci, azx_ids); | |
1630 | ||
1631 | /* pci_driver definition */ | |
1632 | static struct pci_driver driver = { | |
1633 | .name = "HDA Intel", | |
1634 | .id_table = azx_ids, | |
1635 | .probe = azx_probe, | |
1636 | .remove = __devexit_p(azx_remove), | |
421a1252 TI |
1637 | #ifdef CONFIG_PM |
1638 | .suspend = azx_suspend, | |
1639 | .resume = azx_resume, | |
1640 | #endif | |
1da177e4 LT |
1641 | }; |
1642 | ||
1643 | static int __init alsa_card_azx_init(void) | |
1644 | { | |
01d25d46 | 1645 | return pci_register_driver(&driver); |
1da177e4 LT |
1646 | } |
1647 | ||
1648 | static void __exit alsa_card_azx_exit(void) | |
1649 | { | |
1650 | pci_unregister_driver(&driver); | |
1651 | } | |
1652 | ||
1653 | module_init(alsa_card_azx_init) | |
1654 | module_exit(alsa_card_azx_exit) |