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ALSA: hda/tegra - Fix build error and warning
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
9121947d 60#include <linux/vgaarb.h>
a82d51ed 61#include <linux/vga_switcheroo.h>
4918cdab 62#include <linux/firmware.h>
1da177e4 63#include "hda_codec.h"
05e84878 64#include "hda_controller.h"
347de1f8 65#include "hda_intel.h"
1da177e4 66
b6050ef6
TI		 67/* position fix mode */
68enum {
69 POS_FIX_AUTO,
70 POS_FIX_LPIB,
71 POS_FIX_POSBUF,
72 POS_FIX_VIACOMBO,
73 POS_FIX_COMBO,
74};
75
9a34af4a
TI		 76/* Defines for ATI HD Audio support in SB450 south bridge */
77#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
78#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
79
80/* Defines for Nvidia HDA support */
81#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
82#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
83#define NVIDIA_HDA_ISTRM_COH 0x4d
84#define NVIDIA_HDA_OSTRM_COH 0x4c
85#define NVIDIA_HDA_ENABLE_COHBIT 0x01
86
87/* Defines for Intel SCH HDA snoop control */
88#define INTEL_SCH_HDA_DEVC 0x78
89#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
90
91/* Define IN stream 0 FIFO size offset in VIA controller */
92#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
93/* Define VIA HD Audio Device ID*/
94#define VIA_HDAC_DEVICE_ID 0x3288
95
33124929
TI		 96/* max number of SDs */
97/* ICH, ATI and VIA have 4 playback and 4 capture */
98#define ICH6_NUM_CAPTURE 4
99#define ICH6_NUM_PLAYBACK 4
100
101/* ULI has 6 playback and 5 capture */
102#define ULI_NUM_CAPTURE 5
103#define ULI_NUM_PLAYBACK 6
104
105/* ATI HDMI may have up to 8 playbacks and 0 capture */
106#define ATIHDMI_NUM_CAPTURE 0
107#define ATIHDMI_NUM_PLAYBACK 8
108
109/* TERA has 4 playback and 3 capture */
110#define TERA_NUM_CAPTURE 3
111#define TERA_NUM_PLAYBACK 4
112
1da177e4 113
5aba4f8e
TI		 114static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
115static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 116static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 117static char *model[SNDRV_CARDS];
1dac6695 118static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 119static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 120static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 121static int probe_only[SNDRV_CARDS];
26a6cb6c 122static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 123static bool single_cmd;
71623855 124static int enable_msi = -1;
4ea6fbc8
TI		 125#ifdef CONFIG_SND_HDA_PATCH_LOADER
126static char *patch[SNDRV_CARDS];
127#endif
2dca0bba 128#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 129static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 130 CONFIG_SND_HDA_INPUT_BEEP_MODE};
131#endif
1da177e4 132
5aba4f8e 133module_param_array(index, int, NULL, 0444);
1da177e4 134MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 135module_param_array(id, charp, NULL, 0444);
1da177e4 136MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 137module_param_array(enable, bool, NULL, 0444);
138MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
139module_param_array(model, charp, NULL, 0444);
1da177e4 140MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 141module_param_array(position_fix, int, NULL, 0444);
4cb36310 142MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 143 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 144module_param_array(bdl_pos_adj, int, NULL, 0644);
145MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 146module_param_array(probe_mask, int, NULL, 0444);
606ad75f 147MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 148module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 149MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 150module_param_array(jackpoll_ms, int, NULL, 0444);
151MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 152module_param(single_cmd, bool, 0444);
d01ce99f
TI		 153MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
154 "(for debugging only).");
ac9ef6cf 155module_param(enable_msi, bint, 0444);
134a11f0 156MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 157#ifdef CONFIG_SND_HDA_PATCH_LOADER
158module_param_array(patch, charp, NULL, 0444);
159MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
160#endif
2dca0bba 161#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 162module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 163MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 164 "(0=off, 1=on) (default=1).");
2dca0bba 165#endif
606ad75f 166
83012a7c 167#ifdef CONFIG_PM
65fcd41d
TI		 168static int param_set_xint(const char *val, const struct kernel_param *kp);
169static struct kernel_param_ops param_ops_xint = {
170 .set = param_set_xint,
171 .get = param_get_int,
172};
173#define param_check_xint param_check_int
174
fee2fba3 175static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 176module_param(power_save, xint, 0644);
fee2fba3
TI		 177MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
178 "(in second, 0 = disable).");
1da177e4 179
dee1b66c
TI		 180/* reset the HD-audio controller in power save mode.
181 * this may give more power-saving, but will take longer time to
182 * wake up.
183 */
8fc24426
TI		 184static bool power_save_controller = 1;
185module_param(power_save_controller, bool, 0644);
dee1b66c 186MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 187#else
bb573928 188#define power_save 0
83012a7c 189#endif /* CONFIG_PM */
dee1b66c 190
7bfe059e
TI		 191static int align_buffer_size = -1;
192module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 193MODULE_PARM_DESC(align_buffer_size,
194 "Force buffer and period sizes to be multiple of 128 bytes.");
195
27fe48d9 196#ifdef CONFIG_X86
7c732015
TI		 197static int hda_snoop = -1;
198module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 199MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 200#else
201#define hda_snoop true
27fe48d9
TI		 202#endif
203
204
1da177e4
LT		 205MODULE_LICENSE("GPL");
206MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
207 "{Intel, ICH6M},"
2f1b3818 208 "{Intel, ICH7},"
f5d40b30 209 "{Intel, ESB2},"
d2981393 210 "{Intel, ICH8},"
f9cc8a8b 211 "{Intel, ICH9},"
c34f5a04 212 "{Intel, ICH10},"
b29c2360 213 "{Intel, PCH},"
d2f2fcd2 214 "{Intel, CPT},"
d2edeb7c 215 "{Intel, PPT},"
8bc039a1 216 "{Intel, LPT},"
144dad99 217 "{Intel, LPT_LP},"
4eeca499 218 "{Intel, WPT_LP},"
c8b00fd2 219 "{Intel, SPT},"
b4565913 220 "{Intel, SPT_LP},"
e926f2c8 221 "{Intel, HPT},"
cea310e8 222 "{Intel, PBG},"
4979bca9 223 "{Intel, SCH},"
fc20a562 224 "{ATI, SB450},"
89be83f8 225 "{ATI, SB600},"
778b6e1b 226 "{ATI, RS600},"
5b15c95f 227 "{ATI, RS690},"
e6db1119
WL		 228 "{ATI, RS780},"
229 "{ATI, R600},"
2797f724
HRK		 230 "{ATI, RV630},"
231 "{ATI, RV610},"
27da1834
WL		 232 "{ATI, RV670},"
233 "{ATI, RV635},"
234 "{ATI, RV620},"
235 "{ATI, RV770},"
fc20a562 236 "{VIA, VT8251},"
47672310 237 "{VIA, VT8237A},"
07e4ca50
TI		 238 "{SiS, SIS966},"
239 "{ULI, M5461}}");
1da177e4
LT		 240MODULE_DESCRIPTION("Intel HDA driver");
241
a82d51ed 242#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 243#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 244#define SUPPORT_VGA_SWITCHEROO
245#endif
246#endif
247
248
1da177e4 249/*
1da177e4 250 */
1da177e4 251
07e4ca50
TI		 252/* driver types */
253enum {
254 AZX_DRIVER_ICH,
32679f95 255 AZX_DRIVER_PCH,
4979bca9 256 AZX_DRIVER_SCH,
fab1285a 257 AZX_DRIVER_HDMI,
07e4ca50 258 AZX_DRIVER_ATI,
778b6e1b 259 AZX_DRIVER_ATIHDMI,
1815b34a 260 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 261 AZX_DRIVER_VIA,
262 AZX_DRIVER_SIS,
263 AZX_DRIVER_ULI,
da3fca21 264 AZX_DRIVER_NVIDIA,
f269002e 265 AZX_DRIVER_TERA,
14d34f16 266 AZX_DRIVER_CTX,
5ae763b1 267 AZX_DRIVER_CTHDA,
c563f473 268 AZX_DRIVER_CMEDIA,
c4da29ca 269 AZX_DRIVER_GENERIC,
2f5983f2 270 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 271};
272
37e661ee
TI		 273#define azx_get_snoop_type(chip) \
274 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
275#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
276
b42b4afb
TI		 277/* quirks for old Intel chipsets */
278#define AZX_DCAPS_INTEL_ICH \
103884a3 279 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 280
2ea3c6a2 281/* quirks for Intel PCH */
d7dab4db 282#define AZX_DCAPS_INTEL_PCH_NOPM \
103884a3 283 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee 284 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db
TI		 285
286#define AZX_DCAPS_INTEL_PCH \
287 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 288
33499a15 289#define AZX_DCAPS_INTEL_HASWELL \
103884a3 290 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 291 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
292 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 293
54a0405d
LY		 294/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
295#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 296 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 297 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
298 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 299
2d846c74
LY		 300#define AZX_DCAPS_INTEL_BRASWELL \
301 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
302
d6795827 303#define AZX_DCAPS_INTEL_SKYLAKE \
2d846c74
LY		 304 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
305 AZX_DCAPS_I915_POWERWELL)
d6795827 306
9477c58e
TI		 307/* quirks for ATI SB / AMD Hudson */
308#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 309 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
310 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 311
312/* quirks for ATI/AMD HDMI */
313#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 314 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
315 AZX_DCAPS_NO_MSI64)
9477c58e 316
37e661ee
TI		 317/* quirks for ATI HDMI with snoop off */
318#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
319 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
320
9477c58e
TI		 321/* quirks for Nvidia */
322#define AZX_DCAPS_PRESET_NVIDIA \
103884a3 323 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
37e661ee
TI		 324 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
325 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 326
5ae763b1 327#define AZX_DCAPS_PRESET_CTHDA \
37e661ee
TI		 328 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
329 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 330
a82d51ed
TI		 331/*
332 * VGA-switcher support
333 */
334#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 335#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
336#else
337#define use_vga_switcheroo(chip) 0
338#endif
339
48c8b0eb 340static char *driver_short_names[] = {
07e4ca50 341 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 342 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 343 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 344 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 345 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 346 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 347 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 348 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
349 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 350 [AZX_DRIVER_ULI] = "HDA ULI M5461",
351 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 352 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 353 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 354 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 355 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 356 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 357};
358
27fe48d9 359#ifdef CONFIG_X86
9ddf1aeb 360static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 361{
9ddf1aeb
TI		 362 int pages;
363
27fe48d9
TI		 364 if (azx_snoop(chip))
365 return;
9ddf1aeb
TI		 366 if (!dmab || !dmab->area || !dmab->bytes)
367 return;
368
369#ifdef CONFIG_SND_DMA_SGBUF
370 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
371 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 372 if (chip->driver_type == AZX_DRIVER_CMEDIA)
373 return; /* deal with only CORB/RIRB buffers */
27fe48d9 374 if (on)
9ddf1aeb 375 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 376 else
9ddf1aeb
TI		 377 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
378 return;
27fe48d9 379 }
9ddf1aeb
TI		 380#endif
381
382 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
383 if (on)
384 set_memory_wc((unsigned long)dmab->area, pages);
385 else
386 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 387}
388
389static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
390 bool on)
391{
9ddf1aeb 392 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 393}
394static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 395 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 396{
397 if (azx_dev->wc_marked != on) {
9ddf1aeb 398 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 399 azx_dev->wc_marked = on;
400 }
401}
402#else
403/* NOP for other archs */
404static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
405 bool on)
406{
407}
408static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 409 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 410{
411}
412#endif
413
68e7fffc 414static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 415
cb53c626
TI		 416/*
417 * initialize the PCI registers
418 */
419/* update bits in a PCI register byte */
420static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
421 unsigned char mask, unsigned char val)
422{
423 unsigned char data;
424
425 pci_read_config_byte(pci, reg, &data);
426 data &= ~mask;
427 data |= (val & mask);
428 pci_write_config_byte(pci, reg, data);
429}
430
431static void azx_init_pci(struct azx *chip)
432{
37e661ee
TI		 433 int snoop_type = azx_get_snoop_type(chip);
434
cb53c626
TI		 435 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
436 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
437 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 438 * codecs.
439 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 440 */
46f2cc80 441 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 442 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 443 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 444 }
cb53c626 445
9477c58e
TI		 446 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
447 * we need to enable snoop.
448 */
37e661ee 449 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 450 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
451 azx_snoop(chip));
cb53c626 452 update_pci_byte(chip->pci,
27fe48d9
TI		 453 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
454 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 455 }
456
457 /* For NVIDIA HDA, enable snoop */
37e661ee 458 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 459 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
460 azx_snoop(chip));
cb53c626
TI		 461 update_pci_byte(chip->pci,
462 NVIDIA_HDA_TRANSREG_ADDR,
463 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 464 update_pci_byte(chip->pci,
465 NVIDIA_HDA_ISTRM_COH,
466 0x01, NVIDIA_HDA_ENABLE_COHBIT);
467 update_pci_byte(chip->pci,
468 NVIDIA_HDA_OSTRM_COH,
469 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 470 }
471
472 /* Enable SCH/PCH snoop if needed */
37e661ee 473 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 474 unsigned short snoop;
90a5ad52 475 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 476 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
477 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
478 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
479 if (!azx_snoop(chip))
480 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
481 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 482 pci_read_config_word(chip->pci,
483 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 484 }
4e76a883
TI		 485 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
486 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
487 "Disabled" : "Enabled");
da3fca21 488 }
1da177e4
LT		 489}
490
b6050ef6
TI		 491/* calculate runtime delay from LPIB */
492static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
493 unsigned int pos)
494{
7833c3f8 495 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 496 int stream = substream->stream;
497 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
498 int delay;
499
500 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
501 delay = pos - lpib_pos;
502 else
503 delay = lpib_pos - pos;
504 if (delay < 0) {
7833c3f8 505 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 506 delay = 0;
507 else
7833c3f8 508 delay += azx_dev->core.bufsize;
b6050ef6
TI		 509 }
510
7833c3f8 511 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 512 dev_info(chip->card->dev,
513 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 514 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 515 delay = 0;
516 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
517 chip->get_delay[stream] = NULL;
518 }
519
520 return bytes_to_frames(substream->runtime, delay);
521}
522
9ad593f6
TI		 523static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
524
7ca954a8
DR		 525/* called from IRQ */
526static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
527{
9a34af4a 528 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 529 int ok;
530
531 ok = azx_position_ok(chip, azx_dev);
532 if (ok == 1) {
533 azx_dev->irq_pending = 0;
534 return ok;
2f35c630 535 } else if (ok == 0) {
7ca954a8
DR		 536 /* bogus IRQ, process it later */
537 azx_dev->irq_pending = 1;
2f35c630 538 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 539 }
540 return 0;
541}
542
9ad593f6
TI		 543/*
544 * Check whether the current DMA position is acceptable for updating
545 * periods. Returns non-zero if it's OK.
546 *
547 * Many HD-audio controllers appear pretty inaccurate about
548 * the update-IRQ timing. The IRQ is issued before actually the
549 * data is processed. So, we need to process it afterwords in a
550 * workqueue.
551 */
552static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
553{
7833c3f8 554 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 555 int stream = substream->stream;
e5463720 556 u32 wallclk;
9ad593f6
TI		 557 unsigned int pos;
558
7833c3f8
TI		 559 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
560 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 561 return -1; /* bogus (too early) interrupt */
fa00e046 562
b6050ef6
TI		 563 if (chip->get_position[stream])
564 pos = chip->get_position[stream](chip, azx_dev);
565 else { /* use the position buffer as default */
566 pos = azx_get_pos_posbuf(chip, azx_dev);
567 if (!pos || pos == (u32)-1) {
568 dev_info(chip->card->dev,
569 "Invalid position buffer, using LPIB read method instead.\n");
570 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 571 if (chip->get_position[0] == azx_get_pos_lpib &&
572 chip->get_position[1] == azx_get_pos_lpib)
573 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 574 pos = azx_get_pos_lpib(chip, azx_dev);
575 chip->get_delay[stream] = NULL;
576 } else {
577 chip->get_position[stream] = azx_get_pos_posbuf;
578 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
579 chip->get_delay[stream] = azx_get_delay_from_lpib;
580 }
581 }
582
7833c3f8 583 if (pos >= azx_dev->core.bufsize)
b6050ef6 584 pos = 0;
9ad593f6 585
7833c3f8 586 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 587 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 588 return -1; /* this shouldn't happen! */
7833c3f8
TI		 589 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
590 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 591 /* NG - it's below the first next period boundary */
9cdc0115 592 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
7833c3f8 593 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 594 return 1; /* OK, it's fine */
595}
596
597/*
598 * The work for pending PCM period updates.
599 */
600static void azx_irq_pending_work(struct work_struct *work)
601{
9a34af4a
TI		 602 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
603 struct azx *chip = &hda->chip;
7833c3f8
TI		 604 struct hdac_bus *bus = azx_bus(chip);
605 struct hdac_stream *s;
606 int pending, ok;
9ad593f6 607
9a34af4a 608 if (!hda->irq_pending_warned) {
4e76a883
TI		 609 dev_info(chip->card->dev,
610 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
611 chip->card->number);
9a34af4a 612 hda->irq_pending_warned = 1;
a6a950a8
TI		 613 }
614
9ad593f6
TI		 615 for (;;) {
616 pending = 0;
a41d1224 617 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 618 list_for_each_entry(s, &bus->stream_list, list) {
619 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 620 if (!azx_dev->irq_pending ||
7833c3f8
TI		 621 !s->substream ||
622 !s->running)
9ad593f6 623 continue;
e5463720
JK		 624 ok = azx_position_ok(chip, azx_dev);
625 if (ok > 0) {
9ad593f6 626 azx_dev->irq_pending = 0;
a41d1224 627 spin_unlock(&bus->reg_lock);
7833c3f8 628 snd_pcm_period_elapsed(s->substream);
a41d1224 629 spin_lock(&bus->reg_lock);
e5463720
JK		 630 } else if (ok < 0) {
631 pending = 0; /* too early */
9ad593f6
TI		 632 } else
633 pending++;
634 }
a41d1224 635 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 636 if (!pending)
637 return;
08af495f 638 msleep(1);
9ad593f6
TI		 639 }
640}
641
642/* clear irq_pending flags and assure no on-going workq */
643static void azx_clear_irq_pending(struct azx *chip)
644{
7833c3f8
TI		 645 struct hdac_bus *bus = azx_bus(chip);
646 struct hdac_stream *s;
9ad593f6 647
a41d1224 648 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 649 list_for_each_entry(s, &bus->stream_list, list) {
650 struct azx_dev *azx_dev = stream_to_azx_dev(s);
651 azx_dev->irq_pending = 0;
652 }
a41d1224 653 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 654}
655
68e7fffc
TI		 656static int azx_acquire_irq(struct azx *chip, int do_disconnect)
657{
a41d1224
TI		 658 struct hdac_bus *bus = azx_bus(chip);
659
437a5a46
TI		 660 if (request_irq(chip->pci->irq, azx_interrupt,
661 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 662 KBUILD_MODNAME, chip)) {
4e76a883
TI		 663 dev_err(chip->card->dev,
664 "unable to grab IRQ %d, disabling device\n",
665 chip->pci->irq);
68e7fffc
TI		 666 if (do_disconnect)
667 snd_card_disconnect(chip->card);
668 return -1;
669 }
a41d1224 670 bus->irq = chip->pci->irq;
69e13418 671 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 672 return 0;
673}
674
b6050ef6
TI		 675/* get the current DMA position with correction on VIA chips */
676static unsigned int azx_via_get_position(struct azx *chip,
677 struct azx_dev *azx_dev)
678{
679 unsigned int link_pos, mini_pos, bound_pos;
680 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
681 unsigned int fifo_size;
682
683 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
7833c3f8 684 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 685 /* Playback, no problem using link position */
686 return link_pos;
687 }
688
689 /* Capture */
690 /* For new chipset,
691 * use mod to get the DMA position just like old chipset
692 */
7833c3f8
TI		 693 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
694 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 695
696 /* azx_dev->fifo_size can't get FIFO size of in stream.
697 * Get from base address + offset.
698 */
a41d1224
TI		 699 fifo_size = readw(azx_bus(chip)->remap_addr +
700 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 701
702 if (azx_dev->insufficient) {
703 /* Link position never gather than FIFO size */
704 if (link_pos <= fifo_size)
705 return 0;
706
707 azx_dev->insufficient = 0;
708 }
709
710 if (link_pos <= fifo_size)
7833c3f8 711 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 712 else
713 mini_pos = link_pos - fifo_size;
714
715 /* Find nearest previous boudary */
7833c3f8
TI		 716 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
717 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 718 if (mod_link_pos >= fifo_size)
719 bound_pos = link_pos - mod_link_pos;
720 else if (mod_dma_pos >= mod_mini_pos)
721 bound_pos = mini_pos - mod_mini_pos;
722 else {
7833c3f8
TI		 723 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
724 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 725 bound_pos = 0;
726 }
727
728 /* Calculate real DMA position we want */
729 return bound_pos + mod_dma_pos;
730}
731
83012a7c 732#ifdef CONFIG_PM
65fcd41d
TI		 733static DEFINE_MUTEX(card_list_lock);
734static LIST_HEAD(card_list);
735
736static void azx_add_card_list(struct azx *chip)
737{
9a34af4a 738 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 739 mutex_lock(&card_list_lock);
9a34af4a 740 list_add(&hda->list, &card_list);
65fcd41d
TI		 741 mutex_unlock(&card_list_lock);
742}
743
744static void azx_del_card_list(struct azx *chip)
745{
9a34af4a 746 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 747 mutex_lock(&card_list_lock);
9a34af4a 748 list_del_init(&hda->list);
65fcd41d
TI		 749 mutex_unlock(&card_list_lock);
750}
751
752/* trigger power-save check at writing parameter */
753static int param_set_xint(const char *val, const struct kernel_param *kp)
754{
9a34af4a 755 struct hda_intel *hda;
65fcd41d 756 struct azx *chip;
65fcd41d
TI		 757 int prev = power_save;
758 int ret = param_set_int(val, kp);
759
760 if (ret || prev == power_save)
761 return ret;
762
763 mutex_lock(&card_list_lock);
9a34af4a
TI		 764 list_for_each_entry(hda, &card_list, list) {
765 chip = &hda->chip;
a41d1224 766 if (!hda->probe_continued || chip->disabled)
65fcd41d 767 continue;
a41d1224 768 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 769 }
770 mutex_unlock(&card_list_lock);
771 return 0;
772}
773#else
774#define azx_add_card_list(chip) /* NOP */
775#define azx_del_card_list(chip) /* NOP */
83012a7c 776#endif /* CONFIG_PM */
5c0b9bec 777
7ccbde57 778#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 779/*
780 * power management
781 */
68cb2b55 782static int azx_suspend(struct device *dev)
1da177e4 783{
68cb2b55 784 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 785 struct azx *chip;
786 struct hda_intel *hda;
a41d1224 787 struct hdac_bus *bus;
1da177e4 788
2d9772ef
TI		 789 if (!card)
790 return 0;
791
792 chip = card->private_data;
793 hda = container_of(chip, struct hda_intel, chip);
1618e84a 794 if (chip->disabled || hda->init_failed)
c5c21523
TI		 795 return 0;
796
a41d1224 797 bus = azx_bus(chip);
421a1252 798 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 799 azx_clear_irq_pending(chip);
cb53c626 800 azx_stop_chip(chip);
7295b264 801 azx_enter_link_reset(chip);
a41d1224
TI		 802 if (bus->irq >= 0) {
803 free_irq(bus->irq, chip);
804 bus->irq = -1;
30b35399 805 }
a07187c9 806
68e7fffc 807 if (chip->msi)
43001c95 808 pci_disable_msi(chip->pci);
99a2008d 809 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
926981ae 810 hda_display_power(hda, false);
1da177e4
LT		 811 return 0;
812}
813
68cb2b55 814static int azx_resume(struct device *dev)
1da177e4 815{
68cb2b55
TI		 816 struct pci_dev *pci = to_pci_dev(dev);
817 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 818 struct azx *chip;
819 struct hda_intel *hda;
820
821 if (!card)
822 return 0;
1da177e4 823
2d9772ef
TI		 824 chip = card->private_data;
825 hda = container_of(chip, struct hda_intel, chip);
1618e84a 826 if (chip->disabled || hda->init_failed)
c5c21523
TI		 827 return 0;
828
a07187c9 829 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
926981ae
ID		 830 hda_display_power(hda, true);
831 haswell_set_bclk(hda);
a07187c9 832 }
68e7fffc
TI		 833 if (chip->msi)
834 if (pci_enable_msi(pci) < 0)
835 chip->msi = 0;
836 if (azx_acquire_irq(chip, 1) < 0)
30b35399 837 return -EIO;
cb53c626 838 azx_init_pci(chip);
d804ad92 839
17c3ad03 840 azx_init_chip(chip, true);
d804ad92 841
421a1252 842 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 843 return 0;
844}
b8dfc462
ML		 845#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
846
641d334b 847#ifdef CONFIG_PM
b8dfc462
ML		 848static int azx_runtime_suspend(struct device *dev)
849{
850 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 851 struct azx *chip;
852 struct hda_intel *hda;
b8dfc462 853
2d9772ef
TI		 854 if (!card)
855 return 0;
856
857 chip = card->private_data;
858 hda = container_of(chip, struct hda_intel, chip);
1618e84a 859 if (chip->disabled || hda->init_failed)
246efa4a
DA		 860 return 0;
861
364aa716 862 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 863 return 0;
864
7d4f606c
WX		 865 /* enable controller wake up event */
866 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
867 STATESTS_INT_MASK);
868
b8dfc462 869 azx_stop_chip(chip);
873ce8ad 870 azx_enter_link_reset(chip);
b8dfc462 871 azx_clear_irq_pending(chip);
e4d9e513 872 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
926981ae 873 hda_display_power(hda, false);
e4d9e513 874
b8dfc462
ML		 875 return 0;
876}
877
878static int azx_runtime_resume(struct device *dev)
879{
880 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 881 struct azx *chip;
882 struct hda_intel *hda;
7d4f606c
WX		 883 struct hda_codec *codec;
884 int status;
b8dfc462 885
2d9772ef
TI		 886 if (!card)
887 return 0;
888
889 chip = card->private_data;
890 hda = container_of(chip, struct hda_intel, chip);
1618e84a 891 if (chip->disabled || hda->init_failed)
246efa4a
DA		 892 return 0;
893
364aa716 894 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 895 return 0;
896
a07187c9 897 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
926981ae
ID		 898 hda_display_power(hda, true);
899 haswell_set_bclk(hda);
a07187c9 900 }
7d4f606c
WX		 901
902 /* Read STATESTS before controller reset */
903 status = azx_readw(chip, STATESTS);
904
b8dfc462 905 azx_init_pci(chip);
17c3ad03 906 azx_init_chip(chip, true);
7d4f606c 907
a41d1224
TI		 908 if (status) {
909 list_for_each_codec(codec, &chip->bus)
7d4f606c 910 if (status & (1 << codec->addr))
2f35c630
TI		 911 schedule_delayed_work(&codec->jackpoll_work,
912 codec->jackpoll_interval);
7d4f606c
WX		 913 }
914
915 /* disable controller Wake Up event*/
916 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
917 ~STATESTS_INT_MASK);
918
b8dfc462
ML		 919 return 0;
920}
6eb827d2
TI		 921
922static int azx_runtime_idle(struct device *dev)
923{
924 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 925 struct azx *chip;
926 struct hda_intel *hda;
927
928 if (!card)
929 return 0;
6eb827d2 930
2d9772ef
TI		 931 chip = card->private_data;
932 hda = container_of(chip, struct hda_intel, chip);
1618e84a 933 if (chip->disabled || hda->init_failed)
246efa4a
DA		 934 return 0;
935
55ed9cd1 936 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
a41d1224 937 azx_bus(chip)->codec_powered)
6eb827d2
TI		 938 return -EBUSY;
939
940 return 0;
941}
942
b8dfc462
ML		 943static const struct dev_pm_ops azx_pm = {
944 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 945 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 946};
947
68cb2b55
TI		 948#define AZX_PM_OPS &azx_pm
949#else
68cb2b55 950#define AZX_PM_OPS NULL
b8dfc462 951#endif /* CONFIG_PM */
1da177e4
LT		 952
953
48c8b0eb 954static int azx_probe_continue(struct azx *chip);
a82d51ed 955
8393ec4a 956#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 957static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 958
a82d51ed
TI		 959static void azx_vs_set_state(struct pci_dev *pci,
960 enum vga_switcheroo_state state)
961{
962 struct snd_card *card = pci_get_drvdata(pci);
963 struct azx *chip = card->private_data;
9a34af4a 964 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 965 bool disabled;
966
9a34af4a
TI		 967 wait_for_completion(&hda->probe_wait);
968 if (hda->init_failed)
a82d51ed
TI		 969 return;
970
971 disabled = (state == VGA_SWITCHEROO_OFF);
972 if (chip->disabled == disabled)
973 return;
974
a41d1224 975 if (!hda->probe_continued) {
a82d51ed
TI		 976 chip->disabled = disabled;
977 if (!disabled) {
4e76a883
TI		 978 dev_info(chip->card->dev,
979 "Start delayed initialization\n");
5c90680e 980 if (azx_probe_continue(chip) < 0) {
4e76a883 981 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 982 hda->init_failed = true;
a82d51ed
TI		 983 }
984 }
985 } else {
4e76a883
TI		 986 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
987 disabled ? "Disabling" : "Enabling");
a82d51ed 988 if (disabled) {
8928756d
DR		 989 pm_runtime_put_sync_suspend(card->dev);
990 azx_suspend(card->dev);
246efa4a
DA		 991 /* when we get suspended by vga switcheroo we end up in D3cold,
992 * however we have no ACPI handle, so pci/acpi can't put us there,
993 * put ourselves there */
994 pci->current_state = PCI_D3cold;
a82d51ed 995 chip->disabled = true;
a41d1224 996 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 997 dev_warn(chip->card->dev,
998 "Cannot lock devices!\n");
a82d51ed 999 } else {
a41d1224 1000 snd_hda_unlock_devices(&chip->bus);
8928756d 1001 pm_runtime_get_noresume(card->dev);
a82d51ed 1002 chip->disabled = false;
8928756d 1003 azx_resume(card->dev);
a82d51ed
TI		 1004 }
1005 }
1006}
1007
1008static bool azx_vs_can_switch(struct pci_dev *pci)
1009{
1010 struct snd_card *card = pci_get_drvdata(pci);
1011 struct azx *chip = card->private_data;
9a34af4a 1012 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1013
9a34af4a
TI		 1014 wait_for_completion(&hda->probe_wait);
1015 if (hda->init_failed)
a82d51ed 1016 return false;
a41d1224 1017 if (chip->disabled || !hda->probe_continued)
a82d51ed 1018 return true;
a41d1224 1019 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1020 return false;
a41d1224 1021 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1022 return true;
1023}
1024
e23e7a14 1025static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1026{
9a34af4a 1027 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1028 struct pci_dev *p = get_bound_vga(chip->pci);
1029 if (p) {
4e76a883
TI		 1030 dev_info(chip->card->dev,
1031 "Handle VGA-switcheroo audio client\n");
9a34af4a 1032 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1033 pci_dev_put(p);
1034 }
1035}
1036
1037static const struct vga_switcheroo_client_ops azx_vs_ops = {
1038 .set_gpu_state = azx_vs_set_state,
1039 .can_switch = azx_vs_can_switch,
1040};
1041
e23e7a14 1042static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1043{
9a34af4a 1044 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1045 int err;
1046
9a34af4a 1047 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1048 return 0;
1049 /* FIXME: currently only handling DIS controller
1050 * is there any machine with two switchable HDMI audio controllers?
1051 */
128960a9 1052 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed 1053 VGA_SWITCHEROO_DIS,
a41d1224 1054 hda->probe_continued);
128960a9
TI		 1055 if (err < 0)
1056 return err;
9a34af4a 1057 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1058
1059 /* register as an optimus hdmi audio power domain */
8928756d 1060 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1061 &hda->hdmi_pm_domain);
128960a9 1062 return 0;
a82d51ed
TI		 1063}
1064#else
1065#define init_vga_switcheroo(chip) /* NOP */
1066#define register_vga_switcheroo(chip) 0
8393ec4a 1067#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1068#endif /* SUPPORT_VGA_SWITCHER */
1069
1da177e4
LT		 1070/*
1071 * destructor
1072 */
a98f90fd 1073static int azx_free(struct azx *chip)
1da177e4 1074{
c67e2228 1075 struct pci_dev *pci = chip->pci;
a07187c9 1076 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1077 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1078
364aa716 1079 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1080 pm_runtime_get_noresume(&pci->dev);
1081
65fcd41d
TI		 1082 azx_del_card_list(chip);
1083
9a34af4a
TI		 1084 hda->init_failed = 1; /* to be sure */
1085 complete_all(&hda->probe_wait);
f4c482a4 1086
9a34af4a 1087 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1088 if (chip->disabled && hda->probe_continued)
1089 snd_hda_unlock_devices(&chip->bus);
9a34af4a 1090 if (hda->vga_switcheroo_registered)
128960a9 1091 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1092 }
1093
a41d1224 1094 if (bus->chip_init) {
9ad593f6 1095 azx_clear_irq_pending(chip);
7833c3f8 1096 azx_stop_all_streams(chip);
cb53c626 1097 azx_stop_chip(chip);
1da177e4
LT		 1098 }
1099
a41d1224
TI		 1100 if (bus->irq >= 0)
1101 free_irq(bus->irq, (void*)chip);
68e7fffc 1102 if (chip->msi)
30b35399 1103 pci_disable_msi(chip->pci);
a41d1224 1104 iounmap(bus->remap_addr);
1da177e4 1105
67908994 1106 azx_free_stream_pages(chip);
a41d1224
TI		 1107 azx_free_streams(chip);
1108 snd_hdac_bus_exit(bus);
1109
a82d51ed
TI		 1110 if (chip->region_requested)
1111 pci_release_regions(chip->pci);
a41d1224 1112
1da177e4 1113 pci_disable_device(chip->pci);
4918cdab 1114#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1115 release_firmware(chip->fw);
4918cdab 1116#endif
99a2008d 1117 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
926981ae
ID		 1118 hda_display_power(hda, false);
1119 hda_i915_exit(hda);
99a2008d 1120 }
a07187c9 1121 kfree(hda);
1da177e4
LT		 1122
1123 return 0;
1124}
1125
a41d1224
TI		 1126static int azx_dev_disconnect(struct snd_device *device)
1127{
1128 struct azx *chip = device->device_data;
1129
1130 chip->bus.shutdown = 1;
1131 return 0;
1132}
1133
a98f90fd 1134static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1135{
1136 return azx_free(device->device_data);
1137}
1138
8393ec4a 1139#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 1140/*
1141 * Check of disabled HDMI controller by vga-switcheroo
1142 */
e23e7a14 1143static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1144{
1145 struct pci_dev *p;
1146
1147 /* check only discrete GPU */
1148 switch (pci->vendor) {
1149 case PCI_VENDOR_ID_ATI:
1150 case PCI_VENDOR_ID_AMD:
1151 case PCI_VENDOR_ID_NVIDIA:
1152 if (pci->devfn == 1) {
1153 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1154 pci->bus->number, 0);
1155 if (p) {
1156 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1157 return p;
1158 pci_dev_put(p);
1159 }
1160 }
1161 break;
1162 }
1163 return NULL;
1164}
1165
e23e7a14 1166static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1167{
1168 bool vga_inactive = false;
1169 struct pci_dev *p = get_bound_vga(pci);
1170
1171 if (p) {
12b78a7f 1172 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1173 vga_inactive = true;
1174 pci_dev_put(p);
1175 }
1176 return vga_inactive;
1177}
8393ec4a 1178#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1179
3372a153
TI		 1180/*
1181 * white/black-listing for position_fix
1182 */
e23e7a14 1183static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1184 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1185 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1186 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1187 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1188 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1189 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1190 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1191 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1192 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1193 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1194 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1195 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1196 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1197 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1198 {}
1199};
1200
e23e7a14 1201static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1202{
1203 const struct snd_pci_quirk *q;
1204
c673ba1c 1205 switch (fix) {
1dac6695 1206 case POS_FIX_AUTO:
c673ba1c
TI		 1207 case POS_FIX_LPIB:
1208 case POS_FIX_POSBUF:
4cb36310 1209 case POS_FIX_VIACOMBO:
a6f2fd55 1210 case POS_FIX_COMBO:
c673ba1c
TI		 1211 return fix;
1212 }
1213
c673ba1c
TI		 1214 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1215 if (q) {
4e76a883
TI		 1216 dev_info(chip->card->dev,
1217 "position_fix set to %d for device %04x:%04x\n",
1218 q->value, q->subvendor, q->subdevice);
c673ba1c 1219 return q->value;
3372a153 1220 }
bdd9ef24
DH		 1221
1222 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1223 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1224 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1225 return POS_FIX_VIACOMBO;
9477c58e
TI		 1226 }
1227 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1228 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1229 return POS_FIX_LPIB;
bdd9ef24 1230 }
c673ba1c 1231 return POS_FIX_AUTO;
3372a153
TI		 1232}
1233
b6050ef6
TI		 1234static void assign_position_fix(struct azx *chip, int fix)
1235{
1236 static azx_get_pos_callback_t callbacks[] = {
1237 [POS_FIX_AUTO] = NULL,
1238 [POS_FIX_LPIB] = azx_get_pos_lpib,
1239 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1240 [POS_FIX_VIACOMBO] = azx_via_get_position,
1241 [POS_FIX_COMBO] = azx_get_pos_lpib,
1242 };
1243
1244 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1245
1246 /* combo mode uses LPIB only for playback */
1247 if (fix == POS_FIX_COMBO)
1248 chip->get_position[1] = NULL;
1249
1250 if (fix == POS_FIX_POSBUF &&
1251 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1252 chip->get_delay[0] = chip->get_delay[1] =
1253 azx_get_delay_from_lpib;
1254 }
1255
1256}
1257
669ba27a
TI		 1258/*
1259 * black-lists for probe_mask
1260 */
e23e7a14 1261static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1262 /* Thinkpad often breaks the controller communication when accessing
1263 * to the non-working (or non-existing) modem codec slot.
1264 */
1265 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1266 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1267 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1268 /* broken BIOS */
1269 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1270 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1271 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1272 /* forced codec slots */
93574844 1273 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1274 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1275 /* WinFast VP200 H (Teradici) user reported broken communication */
1276 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1277 {}
1278};
1279
f1eaaeec
TI		 1280#define AZX_FORCE_CODEC_MASK 0x100
1281
e23e7a14 1282static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1283{
1284 const struct snd_pci_quirk *q;
1285
f1eaaeec
TI		 1286 chip->codec_probe_mask = probe_mask[dev];
1287 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1288 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1289 if (q) {
4e76a883
TI		 1290 dev_info(chip->card->dev,
1291 "probe_mask set to 0x%x for device %04x:%04x\n",
1292 q->value, q->subvendor, q->subdevice);
f1eaaeec 1293 chip->codec_probe_mask = q->value;
669ba27a
TI		 1294 }
1295 }
f1eaaeec
TI		 1296
1297 /* check forced option */
1298 if (chip->codec_probe_mask != -1 &&
1299 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1300 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1301 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1302 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1303 }
669ba27a
TI		 1304}
1305
4d8e22e0 1306/*
71623855 1307 * white/black-list for enable_msi
4d8e22e0 1308 */
e23e7a14 1309static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1310 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1311 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1312 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1313 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1314 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1315 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1316 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1317 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1318 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1319 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1320 {}
1321};
1322
e23e7a14 1323static void check_msi(struct azx *chip)
4d8e22e0
TI		 1324{
1325 const struct snd_pci_quirk *q;
1326
71623855
TI		 1327 if (enable_msi >= 0) {
1328 chip->msi = !!enable_msi;
4d8e22e0 1329 return;
71623855
TI		 1330 }
1331 chip->msi = 1; /* enable MSI as default */
1332 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1333 if (q) {
4e76a883
TI		 1334 dev_info(chip->card->dev,
1335 "msi for device %04x:%04x set to %d\n",
1336 q->subvendor, q->subdevice, q->value);
4d8e22e0 1337 chip->msi = q->value;
80c43ed7
TI		 1338 return;
1339 }
1340
1341 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1342 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1343 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1344 chip->msi = 0;
4d8e22e0
TI		 1345 }
1346}
1347
a1585d76 1348/* check the snoop mode availability */
e23e7a14 1349static void azx_check_snoop_available(struct azx *chip)
a1585d76 1350{
7c732015 1351 int snoop = hda_snoop;
a1585d76 1352
7c732015
TI		 1353 if (snoop >= 0) {
1354 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1355 snoop ? "snoop" : "non-snoop");
1356 chip->snoop = snoop;
1357 return;
1358 }
1359
1360 snoop = true;
37e661ee
TI		 1361 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1362 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1363 /* force to non-snoop mode for a new VIA controller
1364 * when BIOS is set
1365 */
7c732015
TI		 1366 u8 val;
1367 pci_read_config_byte(chip->pci, 0x42, &val);
1368 if (!(val & 0x80) && chip->pci->revision == 0x30)
1369 snoop = false;
a1585d76
TI		 1370 }
1371
37e661ee
TI		 1372 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1373 snoop = false;
1374
7c732015
TI		 1375 chip->snoop = snoop;
1376 if (!snoop)
1377 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1378}
669ba27a 1379
99a2008d
WX		 1380static void azx_probe_work(struct work_struct *work)
1381{
9a34af4a
TI		 1382 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1383 azx_probe_continue(&hda->chip);
99a2008d 1384}
99a2008d 1385
1da177e4
LT		 1386/*
1387 * constructor
1388 */
a43ff5ba
TI		 1389static const struct hdac_io_ops pci_hda_io_ops;
1390static const struct hda_controller_ops pci_hda_ops;
1391
e23e7a14
BP		 1392static int azx_create(struct snd_card *card, struct pci_dev *pci,
1393 int dev, unsigned int driver_caps,
1394 struct azx **rchip)
1da177e4 1395{
a98f90fd 1396 static struct snd_device_ops ops = {
a41d1224 1397 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1398 .dev_free = azx_dev_free,
1399 };
a07187c9 1400 struct hda_intel *hda;
a82d51ed
TI		 1401 struct azx *chip;
1402 int err;
1da177e4
LT		 1403
1404 *rchip = NULL;
bcd72003 1405
927fc866
PM		 1406 err = pci_enable_device(pci);
1407 if (err < 0)
1da177e4
LT		 1408 return err;
1409
a07187c9
ML		 1410 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1411 if (!hda) {
1da177e4
LT		 1412 pci_disable_device(pci);
1413 return -ENOMEM;
1414 }
1415
a07187c9 1416 chip = &hda->chip;
62932df8 1417 mutex_init(&chip->open_mutex);
1da177e4
LT		 1418 chip->card = card;
1419 chip->pci = pci;
a43ff5ba 1420 chip->ops = &pci_hda_ops;
9477c58e
TI		 1421 chip->driver_caps = driver_caps;
1422 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1423 check_msi(chip);
555e219f 1424 chip->dev_index = dev;
749ee287 1425 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1426 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1427 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1428 INIT_LIST_HEAD(&hda->list);
a82d51ed 1429 init_vga_switcheroo(chip);
9a34af4a 1430 init_completion(&hda->probe_wait);
1da177e4 1431
b6050ef6 1432 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1433
5aba4f8e 1434 check_probe_mask(chip, dev);
3372a153 1435
27346166 1436 chip->single_cmd = single_cmd;
a1585d76 1437 azx_check_snoop_available(chip);
c74db86b 1438
5c0d7bc1
TI		 1439 if (bdl_pos_adj[dev] < 0) {
1440 switch (chip->driver_type) {
0c6341ac 1441 case AZX_DRIVER_ICH:
32679f95 1442 case AZX_DRIVER_PCH:
0c6341ac 1443 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1444 break;
1445 default:
0c6341ac 1446 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1447 break;
1448 }
1449 }
9cdc0115 1450 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1451
a41d1224
TI		 1452 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1453 if (err < 0) {
1454 kfree(hda);
1455 pci_disable_device(pci);
1456 return err;
1457 }
1458
a82d51ed
TI		 1459 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1460 if (err < 0) {
4e76a883 1461 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1462 azx_free(chip);
1463 return err;
1464 }
1465
99a2008d 1466 /* continue probing in work context as may trigger request module */
9a34af4a 1467 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1468
a82d51ed 1469 *rchip = chip;
99a2008d 1470
a82d51ed
TI		 1471 return 0;
1472}
1473
48c8b0eb 1474static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1475{
1476 int dev = chip->dev_index;
1477 struct pci_dev *pci = chip->pci;
1478 struct snd_card *card = chip->card;
a41d1224 1479 struct hdac_bus *bus = azx_bus(chip);
67908994 1480 int err;
a82d51ed 1481 unsigned short gcap;
413cbf46 1482 unsigned int dma_bits = 64;
a82d51ed 1483
07e4ca50
TI		 1484#if BITS_PER_LONG != 64
1485 /* Fix up base address on ULI M5461 */
1486 if (chip->driver_type == AZX_DRIVER_ULI) {
1487 u16 tmp3;
1488 pci_read_config_word(pci, 0x40, &tmp3);
1489 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1490 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1491 }
1492#endif
1493
927fc866 1494 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1495 if (err < 0)
1da177e4 1496 return err;
a82d51ed 1497 chip->region_requested = 1;
1da177e4 1498
a41d1224
TI		 1499 bus->addr = pci_resource_start(pci, 0);
1500 bus->remap_addr = pci_ioremap_bar(pci, 0);
1501 if (bus->remap_addr == NULL) {
4e76a883 1502 dev_err(card->dev, "ioremap error\n");
a82d51ed 1503 return -ENXIO;
1da177e4
LT		 1504 }
1505
db79afa1
BH		 1506 if (chip->msi) {
1507 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1508 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1509 pci->no_64bit_msi = true;
1510 }
68e7fffc
TI		 1511 if (pci_enable_msi(pci) < 0)
1512 chip->msi = 0;
db79afa1 1513 }
7376d013 1514
a82d51ed
TI		 1515 if (azx_acquire_irq(chip, 0) < 0)
1516 return -EBUSY;
1da177e4
LT		 1517
1518 pci_set_master(pci);
a41d1224 1519 synchronize_irq(bus->irq);
1da177e4 1520
bcd72003 1521 gcap = azx_readw(chip, GCAP);
4e76a883 1522 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1523
413cbf46
TI		 1524 /* AMD devices support 40 or 48bit DMA, take the safe one */
1525 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1526 dma_bits = 40;
1527
dc4c2e6b 1528 /* disable SB600 64bit support for safety */
9477c58e 1529 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1530 struct pci_dev *p_smbus;
413cbf46 1531 dma_bits = 40;
dc4c2e6b
AB		 1532 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1533 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1534 NULL);
1535 if (p_smbus) {
1536 if (p_smbus->revision < 0x30)
fb1d8ac2 1537 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1538 pci_dev_put(p_smbus);
1539 }
1540 }
09240cf4 1541
9477c58e
TI		 1542 /* disable 64bit DMA address on some devices */
1543 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1544 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1545 gcap &= ~AZX_GCAP_64OK;
9477c58e 1546 }
396087ea 1547
2ae66c26 1548 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1549 if (align_buffer_size >= 0)
1550 chip->align_buffer_size = !!align_buffer_size;
1551 else {
103884a3 1552 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1553 chip->align_buffer_size = 0;
7bfe059e
TI		 1554 else
1555 chip->align_buffer_size = 1;
1556 }
2ae66c26 1557
cf7aaca8 1558 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1559 if (!(gcap & AZX_GCAP_64OK))
1560 dma_bits = 32;
1561 if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) {
1562 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits));
1563 } else {
e930438c
YH		 1564 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1565 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 1566 }
cf7aaca8 1567
8b6ed8e7
TI		 1568 /* read number of streams from GCAP register instead of using
1569 * hardcoded value
1570 */
1571 chip->capture_streams = (gcap >> 8) & 0x0f;
1572 chip->playback_streams = (gcap >> 12) & 0x0f;
1573 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1574 /* gcap didn't give any info, switching to old method */
1575
1576 switch (chip->driver_type) {
1577 case AZX_DRIVER_ULI:
1578 chip->playback_streams = ULI_NUM_PLAYBACK;
1579 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1580 break;
1581 case AZX_DRIVER_ATIHDMI:
1815b34a 1582 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1583 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1584 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1585 break;
c4da29ca 1586 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1587 default:
1588 chip->playback_streams = ICH6_NUM_PLAYBACK;
1589 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1590 break;
1591 }
07e4ca50 1592 }
8b6ed8e7
TI		 1593 chip->capture_index_offset = 0;
1594 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1595 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1596
a41d1224
TI		 1597 /* initialize streams */
1598 err = azx_init_streams(chip);
81740861 1599 if (err < 0)
a82d51ed 1600 return err;
1da177e4 1601
a41d1224
TI		 1602 err = azx_alloc_stream_pages(chip);
1603 if (err < 0)
1604 return err;
1da177e4
LT		 1605
1606 /* initialize chip */
cb53c626 1607 azx_init_pci(chip);
e4d9e513 1608
926981ae
ID		 1609 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1610 struct hda_intel *hda;
1611
1612 hda = container_of(chip, struct hda_intel, chip);
1613 haswell_set_bclk(hda);
1614 }
e4d9e513 1615
10e77dda 1616 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1617
1618 /* codec detection */
a41d1224 1619 if (!azx_bus(chip)->codec_mask) {
4e76a883 1620 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1621 return -ENODEV;
1da177e4
LT		 1622 }
1623
07e4ca50 1624 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1625 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1626 sizeof(card->shortname));
1627 snprintf(card->longname, sizeof(card->longname),
1628 "%s at 0x%lx irq %i",
a41d1224 1629 card->shortname, bus->addr, bus->irq);
07e4ca50 1630
1da177e4 1631 return 0;
1da177e4
LT		 1632}
1633
97c6a3d1 1634#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1635/* callback from request_firmware_nowait() */
1636static void azx_firmware_cb(const struct firmware *fw, void *context)
1637{
1638 struct snd_card *card = context;
1639 struct azx *chip = card->private_data;
1640 struct pci_dev *pci = chip->pci;
1641
1642 if (!fw) {
4e76a883 1643 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1644 goto error;
1645 }
1646
1647 chip->fw = fw;
1648 if (!chip->disabled) {
1649 /* continue probing */
1650 if (azx_probe_continue(chip))
1651 goto error;
1652 }
1653 return; /* OK */
1654
1655 error:
1656 snd_card_free(card);
1657 pci_set_drvdata(pci, NULL);
1658}
97c6a3d1 1659#endif
5cb543db 1660
40830813
DR		 1661/*
1662 * HDA controller ops.
1663 */
1664
1665/* PCI register access. */
db291e36 1666static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1667{
1668 writel(value, addr);
1669}
1670
db291e36 1671static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1672{
1673 return readl(addr);
1674}
1675
db291e36 1676static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1677{
1678 writew(value, addr);
1679}
1680
db291e36 1681static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1682{
1683 return readw(addr);
1684}
1685
db291e36 1686static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1687{
1688 writeb(value, addr);
1689}
1690
db291e36 1691static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1692{
1693 return readb(addr);
1694}
1695
f46ea609
DR		 1696static int disable_msi_reset_irq(struct azx *chip)
1697{
a41d1224 1698 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 1699 int err;
1700
a41d1224
TI		 1701 free_irq(bus->irq, chip);
1702 bus->irq = -1;
f46ea609
DR		 1703 pci_disable_msi(chip->pci);
1704 chip->msi = 0;
1705 err = azx_acquire_irq(chip, 1);
1706 if (err < 0)
1707 return err;
1708
1709 return 0;
1710}
1711
b419b35b 1712/* DMA page allocation helpers. */
a43ff5ba 1713static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 1714 int type,
1715 size_t size,
1716 struct snd_dma_buffer *buf)
1717{
a41d1224 1718 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 1719 int err;
1720
1721 err = snd_dma_alloc_pages(type,
a43ff5ba 1722 bus->dev,
b419b35b
DR		 1723 size, buf);
1724 if (err < 0)
1725 return err;
1726 mark_pages_wc(chip, buf, true);
1727 return 0;
1728}
1729
a43ff5ba 1730static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 1731{
a41d1224 1732 struct azx *chip = bus_to_azx(bus);
a43ff5ba 1733
b419b35b
DR		 1734 mark_pages_wc(chip, buf, false);
1735 snd_dma_free_pages(buf);
1736}
1737
1738static int substream_alloc_pages(struct azx *chip,
1739 struct snd_pcm_substream *substream,
1740 size_t size)
1741{
1742 struct azx_dev *azx_dev = get_azx_dev(substream);
1743 int ret;
1744
1745 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 1746 ret = snd_pcm_lib_malloc_pages(substream, size);
1747 if (ret < 0)
1748 return ret;
1749 mark_runtime_wc(chip, azx_dev, substream, true);
1750 return 0;
1751}
1752
1753static int substream_free_pages(struct azx *chip,
1754 struct snd_pcm_substream *substream)
1755{
1756 struct azx_dev *azx_dev = get_azx_dev(substream);
1757 mark_runtime_wc(chip, azx_dev, substream, false);
1758 return snd_pcm_lib_free_pages(substream);
1759}
1760
8769b278
DR		 1761static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1762 struct vm_area_struct *area)
1763{
1764#ifdef CONFIG_X86
1765 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1766 struct azx *chip = apcm->chip;
3b70bdba 1767 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 1768 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1769#endif
1770}
1771
a43ff5ba 1772static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 1773 .reg_writel = pci_azx_writel,
1774 .reg_readl = pci_azx_readl,
1775 .reg_writew = pci_azx_writew,
1776 .reg_readw = pci_azx_readw,
1777 .reg_writeb = pci_azx_writeb,
1778 .reg_readb = pci_azx_readb,
b419b35b
DR		 1779 .dma_alloc_pages = dma_alloc_pages,
1780 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 1781};
1782
1783static const struct hda_controller_ops pci_hda_ops = {
1784 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1785 .substream_alloc_pages = substream_alloc_pages,
1786 .substream_free_pages = substream_free_pages,
8769b278 1787 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1788 .position_check = azx_position_check,
40830813
DR		 1789};
1790
e23e7a14
BP		 1791static int azx_probe(struct pci_dev *pci,
1792 const struct pci_device_id *pci_id)
1da177e4 1793{
5aba4f8e 1794 static int dev;
a98f90fd 1795 struct snd_card *card;
9a34af4a 1796 struct hda_intel *hda;
a98f90fd 1797 struct azx *chip;
aad730d0 1798 bool schedule_probe;
927fc866 1799 int err;
1da177e4 1800
5aba4f8e
TI		 1801 if (dev >= SNDRV_CARDS)
1802 return -ENODEV;
1803 if (!enable[dev]) {
1804 dev++;
1805 return -ENOENT;
1806 }
1807
60c5772b
TI		 1808 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1809 0, &card);
e58de7ba 1810 if (err < 0) {
4e76a883 1811 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1812 return err;
1da177e4
LT		 1813 }
1814
a43ff5ba 1815 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 1816 if (err < 0)
1817 goto out_free;
421a1252 1818 card->private_data = chip;
9a34af4a 1819 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1820
1821 pci_set_drvdata(pci, card);
1822
1823 err = register_vga_switcheroo(chip);
1824 if (err < 0) {
4e76a883 1825 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1826 goto out_free;
1827 }
1828
1829 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1830 dev_info(card->dev, "VGA controller is disabled\n");
1831 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1832 chip->disabled = true;
1833 }
1834
aad730d0 1835 schedule_probe = !chip->disabled;
1da177e4 1836
4918cdab
TI		 1837#ifdef CONFIG_SND_HDA_PATCH_LOADER
1838 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1839 dev_info(card->dev, "Applying patch firmware '%s'\n",
1840 patch[dev]);
5cb543db
TI		 1841 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1842 &pci->dev, GFP_KERNEL, card,
1843 azx_firmware_cb);
4918cdab
TI		 1844 if (err < 0)
1845 goto out_free;
aad730d0 1846 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1847 }
1848#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1849
aad730d0
TI		 1850#ifndef CONFIG_SND_HDA_I915
1851 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1852 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1853#endif
99a2008d 1854
aad730d0 1855 if (schedule_probe)
9a34af4a 1856 schedule_work(&hda->probe_work);
a82d51ed 1857
a82d51ed 1858 dev++;
88d071fc 1859 if (chip->disabled)
9a34af4a 1860 complete_all(&hda->probe_wait);
a82d51ed
TI		 1861 return 0;
1862
1863out_free:
1864 snd_card_free(card);
1865 return err;
1866}
1867
e62a42ae
DR		 1868/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1869static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1870 [AZX_DRIVER_NVIDIA] = 8,
1871 [AZX_DRIVER_TERA] = 1,
1872};
1873
48c8b0eb 1874static int azx_probe_continue(struct azx *chip)
a82d51ed 1875{
9a34af4a 1876 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
c67e2228 1877 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1878 int dev = chip->dev_index;
1879 int err;
1880
a41d1224 1881 hda->probe_continued = 1;
99a2008d
WX		 1882 /* Request power well for Haswell HDA controller and codec */
1883 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 1884#ifdef CONFIG_SND_HDA_I915
926981ae 1885 err = hda_i915_init(hda);
d7055bd6 1886 if (err < 0)
99a2008d 1887 goto out_free;
926981ae 1888 err = hda_display_power(hda, true);
74b0c2d7
TI		 1889 if (err < 0) {
1890 dev_err(chip->card->dev,
1891 "Cannot turn on display power on i915\n");
1892 goto out_free;
1893 }
c841ad2a 1894#endif
99a2008d
WX		 1895 }
1896
5c90680e
TI		 1897 err = azx_first_init(chip);
1898 if (err < 0)
1899 goto out_free;
1900
2dca0bba
JK		 1901#ifdef CONFIG_SND_HDA_INPUT_BEEP
1902 chip->beep_mode = beep_mode[dev];
1903#endif
1904
1da177e4 1905 /* create codec instances */
96d2bd6e 1906 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 1907 if (err < 0)
1908 goto out_free;
96d2bd6e 1909
4ea6fbc8 1910#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 1911 if (chip->fw) {
a41d1224 1912 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 1913 chip->fw->data);
4ea6fbc8
TI		 1914 if (err < 0)
1915 goto out_free;
e39ae856 1916#ifndef CONFIG_PM
4918cdab
TI		 1917 release_firmware(chip->fw); /* no longer needed */
1918 chip->fw = NULL;
e39ae856 1919#endif
4ea6fbc8
TI		 1920 }
1921#endif
10e77dda 1922 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 1923 err = azx_codec_configure(chip);
1924 if (err < 0)
1925 goto out_free;
1926 }
1da177e4 1927
a82d51ed 1928 err = snd_card_register(chip->card);
41dda0fd
WF		 1929 if (err < 0)
1930 goto out_free;
1da177e4 1931
cb53c626 1932 chip->running = 1;
65fcd41d 1933 azx_add_card_list(chip);
a41d1224 1934 snd_hda_set_power_save(&chip->bus, power_save * 1000);
364aa716 1935 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
c67e2228 1936 pm_runtime_put_noidle(&pci->dev);
1da177e4 1937
41dda0fd 1938out_free:
88d071fc 1939 if (err < 0)
9a34af4a
TI		 1940 hda->init_failed = 1;
1941 complete_all(&hda->probe_wait);
41dda0fd 1942 return err;
1da177e4
LT		 1943}
1944
e23e7a14 1945static void azx_remove(struct pci_dev *pci)
1da177e4 1946{
9121947d 1947 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 1948
9121947d
TI		 1949 if (card)
1950 snd_card_free(card);
1da177e4
LT		 1951}
1952
b2a0bafa
TI		 1953static void azx_shutdown(struct pci_dev *pci)
1954{
1955 struct snd_card *card = pci_get_drvdata(pci);
1956 struct azx *chip;
1957
1958 if (!card)
1959 return;
1960 chip = card->private_data;
1961 if (chip && chip->running)
1962 azx_stop_chip(chip);
1963}
1964
1da177e4 1965/* PCI IDs */
6f51f6cf 1966static const struct pci_device_id azx_ids[] = {
d2f2fcd2 1967 /* CPT */
9477c58e 1968 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 1969 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 1970 /* PBG */
9477c58e 1971 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 1972 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 1973 /* Panther Point */
9477c58e 1974 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 1975 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 1976 /* Lynx Point */
1977 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 1978 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 1979 /* 9 Series */
1980 { PCI_DEVICE(0x8086, 0x8ca0),
1981 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 1982 /* Wellsburg */
1983 { PCI_DEVICE(0x8086, 0x8d20),
1984 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1985 { PCI_DEVICE(0x8086, 0x8d21),
1986 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1987 /* Lynx Point-LP */
1988 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 1989 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1990 /* Lynx Point-LP */
1991 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 1992 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 1993 /* Wildcat Point-LP */
1994 { PCI_DEVICE(0x8086, 0x9ca0),
1995 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 1996 /* Sunrise Point */
1997 { PCI_DEVICE(0x8086, 0xa170),
db48abf4 1998 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 1999 /* Sunrise Point-LP */
2000 { PCI_DEVICE(0x8086, 0x9d70),
d6795827 2001 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
e926f2c8 2002 /* Haswell */
4a7c516b 2003 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2004 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2005 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2006 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2007 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2008 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2009 /* Broadwell */
2010 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2011 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2012 /* 5 Series/3400 */
2013 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2014 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2015 /* Poulsbo */
9477c58e 2016 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 2017 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2018 /* Oaktrail */
09904b95 2019 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 2020 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 2021 /* BayTrail */
2022 { PCI_DEVICE(0x8086, 0x0f04),
2023 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
f31b2ffc
LY		 2024 /* Braswell */
2025 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2026 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2027 /* ICH6 */
8b0bd226 2028 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2029 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2030 /* ICH7 */
8b0bd226 2031 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2032 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2033 /* ESB2 */
8b0bd226 2034 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2035 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2036 /* ICH8 */
8b0bd226 2037 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2038 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2039 /* ICH9 */
8b0bd226 2040 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2041 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2042 /* ICH9 */
8b0bd226 2043 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2044 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2045 /* ICH10 */
8b0bd226 2046 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2047 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2048 /* ICH10 */
8b0bd226 2049 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2050 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2051 /* Generic Intel */
2052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2053 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2054 .class_mask = 0xffffff,
103884a3 2055 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2056 /* ATI SB 450/600/700/800/900 */
2057 { PCI_DEVICE(0x1002, 0x437b),
2058 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2059 { PCI_DEVICE(0x1002, 0x4383),
2060 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2061 /* AMD Hudson */
2062 { PCI_DEVICE(0x1022, 0x780d),
2063 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2064 /* ATI HDMI */
9477c58e
TI		 2065 { PCI_DEVICE(0x1002, 0x793b),
2066 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2067 { PCI_DEVICE(0x1002, 0x7919),
2068 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2069 { PCI_DEVICE(0x1002, 0x960f),
2070 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2071 { PCI_DEVICE(0x1002, 0x970f),
2072 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2073 { PCI_DEVICE(0x1002, 0xaa00),
2074 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2075 { PCI_DEVICE(0x1002, 0xaa08),
2076 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2077 { PCI_DEVICE(0x1002, 0xaa10),
2078 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2079 { PCI_DEVICE(0x1002, 0xaa18),
2080 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2081 { PCI_DEVICE(0x1002, 0xaa20),
2082 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2083 { PCI_DEVICE(0x1002, 0xaa28),
2084 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2085 { PCI_DEVICE(0x1002, 0xaa30),
2086 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2087 { PCI_DEVICE(0x1002, 0xaa38),
2088 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2089 { PCI_DEVICE(0x1002, 0xaa40),
2090 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2091 { PCI_DEVICE(0x1002, 0xaa48),
2092 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2093 { PCI_DEVICE(0x1002, 0xaa50),
2094 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2095 { PCI_DEVICE(0x1002, 0xaa58),
2096 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2097 { PCI_DEVICE(0x1002, 0xaa60),
2098 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2099 { PCI_DEVICE(0x1002, 0xaa68),
2100 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2101 { PCI_DEVICE(0x1002, 0xaa80),
2102 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2103 { PCI_DEVICE(0x1002, 0xaa88),
2104 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2105 { PCI_DEVICE(0x1002, 0xaa90),
2106 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2107 { PCI_DEVICE(0x1002, 0xaa98),
2108 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2109 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2110 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2111 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2112 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2113 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2114 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2115 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2116 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2117 /* VIA VT8251/VT8237A */
9477c58e
TI		 2118 { PCI_DEVICE(0x1106, 0x3288),
2119 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 2120 /* VIA GFX VT7122/VX900 */
2121 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2122 /* VIA GFX VT6122/VX11 */
2123 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2124 /* SIS966 */
2125 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2126 /* ULI M5461 */
2127 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2128 /* NVIDIA MCP */
0c2fd1bf
TI		 2129 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2130 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2131 .class_mask = 0xffffff,
9477c58e 2132 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2133 /* Teradici */
9477c58e
TI		 2134 { PCI_DEVICE(0x6549, 0x1200),
2135 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2136 { PCI_DEVICE(0x6549, 0x2200),
2137 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2138 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2139 /* CTHDA chips */
2140 { PCI_DEVICE(0x1102, 0x0010),
2141 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2142 { PCI_DEVICE(0x1102, 0x0012),
2143 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2144#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2145 /* the following entry conflicts with snd-ctxfi driver,
2146 * as ctxfi driver mutates from HD-audio to native mode with
2147 * a special command sequence.
2148 */
4e01f54b
TI		 2149 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2150 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2151 .class_mask = 0xffffff,
9477c58e 2152 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2153 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2154#else
2155 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2156 { PCI_DEVICE(0x1102, 0x0009),
2157 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2158 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2159#endif
c563f473
TI		 2160 /* CM8888 */
2161 { PCI_DEVICE(0x13f6, 0x5011),
2162 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2163 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2164 /* Vortex86MX */
2165 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2166 /* VMware HDAudio */
2167 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2168 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2169 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2170 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2171 .class_mask = 0xffffff,
9477c58e 2172 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2173 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2174 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2175 .class_mask = 0xffffff,
9477c58e 2176 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2177 { 0, }
2178};
2179MODULE_DEVICE_TABLE(pci, azx_ids);
2180
2181/* pci_driver definition */
e9f66d9b 2182static struct pci_driver azx_driver = {
3733e424 2183 .name = KBUILD_MODNAME,
1da177e4
LT		 2184 .id_table = azx_ids,
2185 .probe = azx_probe,
e23e7a14 2186 .remove = azx_remove,
b2a0bafa 2187 .shutdown = azx_shutdown,
68cb2b55
TI		 2188 .driver = {
2189 .pm = AZX_PM_OPS,
2190 },
1da177e4
LT		 2191};
2192
e9f66d9b 2193module_pci_driver(azx_driver);
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