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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * | |
3 | * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio. | |
4 | * | |
5 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
8 | * PeiSen Hou <pshou@realtek.com.tw> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the Free | |
12 | * Software Foundation; either version 2 of the License, or (at your option) | |
13 | * any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
18 | * more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along with | |
21 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
22 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
23 | * | |
24 | * CONTACTS: | |
25 | * | |
26 | * Matt Jared matt.jared@intel.com | |
27 | * Andy Kopp andy.kopp@intel.com | |
28 | * Dan Kogan dan.d.kogan@intel.com | |
29 | * | |
30 | * CHANGES: | |
31 | * | |
32 | * 2004.12.01 Major rewrite by tiwai, merged the work of pshou | |
33 | * | |
34 | */ | |
35 | ||
36 | #include <sound/driver.h> | |
37 | #include <asm/io.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
362775e2 | 40 | #include <linux/kernel.h> |
1da177e4 LT |
41 | #include <linux/module.h> |
42 | #include <linux/moduleparam.h> | |
43 | #include <linux/init.h> | |
44 | #include <linux/slab.h> | |
45 | #include <linux/pci.h> | |
46 | #include <sound/core.h> | |
47 | #include <sound/initval.h> | |
48 | #include "hda_codec.h" | |
49 | ||
50 | ||
b7fe4622 CL |
51 | static int index = SNDRV_DEFAULT_IDX1; |
52 | static char *id = SNDRV_DEFAULT_STR1; | |
53 | static char *model; | |
54 | static int position_fix; | |
1da177e4 | 55 | |
b7fe4622 | 56 | module_param(index, int, 0444); |
1da177e4 | 57 | MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); |
b7fe4622 | 58 | module_param(id, charp, 0444); |
1da177e4 | 59 | MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); |
b7fe4622 | 60 | module_param(model, charp, 0444); |
1da177e4 | 61 | MODULE_PARM_DESC(model, "Use the given board model."); |
b7fe4622 | 62 | module_param(position_fix, int, 0444); |
0be3b5d3 | 63 | MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size)."); |
1da177e4 | 64 | |
2b3e584b TI |
65 | /* just for backward compatibility */ |
66 | static int enable; | |
698444f3 | 67 | module_param(enable, bool, 0444); |
2b3e584b | 68 | |
1da177e4 LT |
69 | MODULE_LICENSE("GPL"); |
70 | MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," | |
71 | "{Intel, ICH6M}," | |
2f1b3818 | 72 | "{Intel, ICH7}," |
f5d40b30 | 73 | "{Intel, ESB2}," |
fc20a562 TI |
74 | "{ATI, SB450}," |
75 | "{VIA, VT8251}," | |
47672310 | 76 | "{VIA, VT8237A}," |
07e4ca50 TI |
77 | "{SiS, SIS966}," |
78 | "{ULI, M5461}}"); | |
1da177e4 LT |
79 | MODULE_DESCRIPTION("Intel HDA driver"); |
80 | ||
81 | #define SFX "hda-intel: " | |
82 | ||
83 | /* | |
84 | * registers | |
85 | */ | |
86 | #define ICH6_REG_GCAP 0x00 | |
87 | #define ICH6_REG_VMIN 0x02 | |
88 | #define ICH6_REG_VMAJ 0x03 | |
89 | #define ICH6_REG_OUTPAY 0x04 | |
90 | #define ICH6_REG_INPAY 0x06 | |
91 | #define ICH6_REG_GCTL 0x08 | |
92 | #define ICH6_REG_WAKEEN 0x0c | |
93 | #define ICH6_REG_STATESTS 0x0e | |
94 | #define ICH6_REG_GSTS 0x10 | |
95 | #define ICH6_REG_INTCTL 0x20 | |
96 | #define ICH6_REG_INTSTS 0x24 | |
97 | #define ICH6_REG_WALCLK 0x30 | |
98 | #define ICH6_REG_SYNC 0x34 | |
99 | #define ICH6_REG_CORBLBASE 0x40 | |
100 | #define ICH6_REG_CORBUBASE 0x44 | |
101 | #define ICH6_REG_CORBWP 0x48 | |
102 | #define ICH6_REG_CORBRP 0x4A | |
103 | #define ICH6_REG_CORBCTL 0x4c | |
104 | #define ICH6_REG_CORBSTS 0x4d | |
105 | #define ICH6_REG_CORBSIZE 0x4e | |
106 | ||
107 | #define ICH6_REG_RIRBLBASE 0x50 | |
108 | #define ICH6_REG_RIRBUBASE 0x54 | |
109 | #define ICH6_REG_RIRBWP 0x58 | |
110 | #define ICH6_REG_RINTCNT 0x5a | |
111 | #define ICH6_REG_RIRBCTL 0x5c | |
112 | #define ICH6_REG_RIRBSTS 0x5d | |
113 | #define ICH6_REG_RIRBSIZE 0x5e | |
114 | ||
115 | #define ICH6_REG_IC 0x60 | |
116 | #define ICH6_REG_IR 0x64 | |
117 | #define ICH6_REG_IRS 0x68 | |
118 | #define ICH6_IRS_VALID (1<<1) | |
119 | #define ICH6_IRS_BUSY (1<<0) | |
120 | ||
121 | #define ICH6_REG_DPLBASE 0x70 | |
122 | #define ICH6_REG_DPUBASE 0x74 | |
123 | #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ | |
124 | ||
125 | /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ | |
126 | enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; | |
127 | ||
128 | /* stream register offsets from stream base */ | |
129 | #define ICH6_REG_SD_CTL 0x00 | |
130 | #define ICH6_REG_SD_STS 0x03 | |
131 | #define ICH6_REG_SD_LPIB 0x04 | |
132 | #define ICH6_REG_SD_CBL 0x08 | |
133 | #define ICH6_REG_SD_LVI 0x0c | |
134 | #define ICH6_REG_SD_FIFOW 0x0e | |
135 | #define ICH6_REG_SD_FIFOSIZE 0x10 | |
136 | #define ICH6_REG_SD_FORMAT 0x12 | |
137 | #define ICH6_REG_SD_BDLPL 0x18 | |
138 | #define ICH6_REG_SD_BDLPU 0x1c | |
139 | ||
140 | /* PCI space */ | |
141 | #define ICH6_PCIREG_TCSEL 0x44 | |
142 | ||
143 | /* | |
144 | * other constants | |
145 | */ | |
146 | ||
147 | /* max number of SDs */ | |
07e4ca50 TI |
148 | /* ICH, ATI and VIA have 4 playback and 4 capture */ |
149 | #define ICH6_CAPTURE_INDEX 0 | |
150 | #define ICH6_NUM_CAPTURE 4 | |
151 | #define ICH6_PLAYBACK_INDEX 4 | |
152 | #define ICH6_NUM_PLAYBACK 4 | |
153 | ||
154 | /* ULI has 6 playback and 5 capture */ | |
155 | #define ULI_CAPTURE_INDEX 0 | |
156 | #define ULI_NUM_CAPTURE 5 | |
157 | #define ULI_PLAYBACK_INDEX 5 | |
158 | #define ULI_NUM_PLAYBACK 6 | |
159 | ||
160 | /* this number is statically defined for simplicity */ | |
161 | #define MAX_AZX_DEV 16 | |
162 | ||
1da177e4 | 163 | /* max number of fragments - we may use more if allocating more pages for BDL */ |
07e4ca50 TI |
164 | #define BDL_SIZE PAGE_ALIGN(8192) |
165 | #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16)) | |
1da177e4 LT |
166 | /* max buffer size - no h/w limit, you can increase as you like */ |
167 | #define AZX_MAX_BUF_SIZE (1024*1024*1024) | |
168 | /* max number of PCM devics per card */ | |
ec9e1c5c TI |
169 | #define AZX_MAX_AUDIO_PCMS 6 |
170 | #define AZX_MAX_MODEM_PCMS 2 | |
171 | #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS) | |
1da177e4 LT |
172 | |
173 | /* RIRB int mask: overrun[2], response[0] */ | |
174 | #define RIRB_INT_RESPONSE 0x01 | |
175 | #define RIRB_INT_OVERRUN 0x04 | |
176 | #define RIRB_INT_MASK 0x05 | |
177 | ||
178 | /* STATESTS int mask: SD2,SD1,SD0 */ | |
179 | #define STATESTS_INT_MASK 0x07 | |
f5d40b30 | 180 | #define AZX_MAX_CODECS 4 |
1da177e4 LT |
181 | |
182 | /* SD_CTL bits */ | |
183 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ | |
184 | #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ | |
185 | #define SD_CTL_STREAM_TAG_MASK (0xf << 20) | |
186 | #define SD_CTL_STREAM_TAG_SHIFT 20 | |
187 | ||
188 | /* SD_CTL and SD_STS */ | |
189 | #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ | |
190 | #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ | |
191 | #define SD_INT_COMPLETE 0x04 /* completion interrupt */ | |
192 | #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE) | |
193 | ||
194 | /* SD_STS */ | |
195 | #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ | |
196 | ||
197 | /* INTCTL and INTSTS */ | |
198 | #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ | |
199 | #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ | |
200 | #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ | |
201 | ||
41e2fce4 M |
202 | /* GCTL unsolicited response enable bit */ |
203 | #define ICH6_GCTL_UREN (1<<8) | |
204 | ||
1da177e4 LT |
205 | /* GCTL reset bit */ |
206 | #define ICH6_GCTL_RESET (1<<0) | |
207 | ||
208 | /* CORB/RIRB control, read/write pointer */ | |
209 | #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */ | |
210 | #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */ | |
211 | #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */ | |
212 | /* below are so far hardcoded - should read registers in future */ | |
213 | #define ICH6_MAX_CORB_ENTRIES 256 | |
214 | #define ICH6_MAX_RIRB_ENTRIES 256 | |
215 | ||
c74db86b TI |
216 | /* position fix mode */ |
217 | enum { | |
0be3b5d3 | 218 | POS_FIX_AUTO, |
c74db86b | 219 | POS_FIX_NONE, |
0be3b5d3 TI |
220 | POS_FIX_POSBUF, |
221 | POS_FIX_FIFO, | |
c74db86b | 222 | }; |
1da177e4 | 223 | |
f5d40b30 | 224 | /* Defines for ATI HD Audio support in SB450 south bridge */ |
f5d40b30 FL |
225 | #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 |
226 | #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 | |
227 | ||
da3fca21 V |
228 | /* Defines for Nvidia HDA support */ |
229 | #define NVIDIA_HDA_TRANSREG_ADDR 0x4e | |
230 | #define NVIDIA_HDA_ENABLE_COHBITS 0x0f | |
f5d40b30 | 231 | |
1da177e4 LT |
232 | /* |
233 | * Use CORB/RIRB for communication from/to codecs. | |
234 | * This is the way recommended by Intel (see below). | |
235 | */ | |
236 | #define USE_CORB_RIRB | |
237 | ||
1da177e4 LT |
238 | /* |
239 | */ | |
240 | ||
a98f90fd | 241 | struct azx_dev { |
1da177e4 LT |
242 | u32 *bdl; /* virtual address of the BDL */ |
243 | dma_addr_t bdl_addr; /* physical address of the BDL */ | |
244 | volatile u32 *posbuf; /* position buffer pointer */ | |
245 | ||
246 | unsigned int bufsize; /* size of the play buffer in bytes */ | |
247 | unsigned int fragsize; /* size of each period in bytes */ | |
248 | unsigned int frags; /* number for period in the play buffer */ | |
249 | unsigned int fifo_size; /* FIFO size */ | |
0be3b5d3 | 250 | unsigned int last_pos; /* last updated period position */ |
1da177e4 LT |
251 | |
252 | void __iomem *sd_addr; /* stream descriptor pointer */ | |
253 | ||
254 | u32 sd_int_sta_mask; /* stream int status mask */ | |
255 | ||
256 | /* pcm support */ | |
a98f90fd | 257 | struct snd_pcm_substream *substream; /* assigned substream, set in PCM open */ |
1da177e4 LT |
258 | unsigned int format_val; /* format value to be set in the controller and the codec */ |
259 | unsigned char stream_tag; /* assigned stream */ | |
260 | unsigned char index; /* stream index */ | |
261 | ||
262 | unsigned int opened: 1; | |
263 | unsigned int running: 1; | |
0be3b5d3 | 264 | unsigned int period_updating: 1; |
1da177e4 LT |
265 | }; |
266 | ||
267 | /* CORB/RIRB */ | |
a98f90fd | 268 | struct azx_rb { |
1da177e4 LT |
269 | u32 *buf; /* CORB/RIRB buffer |
270 | * Each CORB entry is 4byte, RIRB is 8byte | |
271 | */ | |
272 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | |
273 | /* for RIRB */ | |
274 | unsigned short rp, wp; /* read/write pointers */ | |
275 | int cmds; /* number of pending requests */ | |
276 | u32 res; /* last read value */ | |
277 | }; | |
278 | ||
a98f90fd TI |
279 | struct azx { |
280 | struct snd_card *card; | |
1da177e4 LT |
281 | struct pci_dev *pci; |
282 | ||
07e4ca50 TI |
283 | /* chip type specific */ |
284 | int driver_type; | |
285 | int playback_streams; | |
286 | int playback_index_offset; | |
287 | int capture_streams; | |
288 | int capture_index_offset; | |
289 | int num_streams; | |
290 | ||
1da177e4 LT |
291 | /* pci resources */ |
292 | unsigned long addr; | |
293 | void __iomem *remap_addr; | |
294 | int irq; | |
295 | ||
296 | /* locks */ | |
297 | spinlock_t reg_lock; | |
298 | struct semaphore open_mutex; | |
299 | ||
07e4ca50 | 300 | /* streams (x num_streams) */ |
a98f90fd | 301 | struct azx_dev *azx_dev; |
1da177e4 LT |
302 | |
303 | /* PCM */ | |
304 | unsigned int pcm_devs; | |
a98f90fd | 305 | struct snd_pcm *pcm[AZX_MAX_PCMS]; |
1da177e4 LT |
306 | |
307 | /* HD codec */ | |
308 | unsigned short codec_mask; | |
309 | struct hda_bus *bus; | |
310 | ||
311 | /* CORB/RIRB */ | |
a98f90fd TI |
312 | struct azx_rb corb; |
313 | struct azx_rb rirb; | |
1da177e4 LT |
314 | |
315 | /* BDL, CORB/RIRB and position buffers */ | |
316 | struct snd_dma_buffer bdl; | |
317 | struct snd_dma_buffer rb; | |
318 | struct snd_dma_buffer posbuf; | |
c74db86b TI |
319 | |
320 | /* flags */ | |
321 | int position_fix; | |
ce43fbae | 322 | unsigned int initialized: 1; |
1da177e4 LT |
323 | }; |
324 | ||
07e4ca50 TI |
325 | /* driver types */ |
326 | enum { | |
327 | AZX_DRIVER_ICH, | |
328 | AZX_DRIVER_ATI, | |
329 | AZX_DRIVER_VIA, | |
330 | AZX_DRIVER_SIS, | |
331 | AZX_DRIVER_ULI, | |
da3fca21 | 332 | AZX_DRIVER_NVIDIA, |
07e4ca50 TI |
333 | }; |
334 | ||
335 | static char *driver_short_names[] __devinitdata = { | |
336 | [AZX_DRIVER_ICH] = "HDA Intel", | |
337 | [AZX_DRIVER_ATI] = "HDA ATI SB", | |
338 | [AZX_DRIVER_VIA] = "HDA VIA VT82xx", | |
339 | [AZX_DRIVER_SIS] = "HDA SIS966", | |
da3fca21 V |
340 | [AZX_DRIVER_ULI] = "HDA ULI M5461", |
341 | [AZX_DRIVER_NVIDIA] = "HDA NVidia", | |
07e4ca50 TI |
342 | }; |
343 | ||
1da177e4 LT |
344 | /* |
345 | * macros for easy use | |
346 | */ | |
347 | #define azx_writel(chip,reg,value) \ | |
348 | writel(value, (chip)->remap_addr + ICH6_REG_##reg) | |
349 | #define azx_readl(chip,reg) \ | |
350 | readl((chip)->remap_addr + ICH6_REG_##reg) | |
351 | #define azx_writew(chip,reg,value) \ | |
352 | writew(value, (chip)->remap_addr + ICH6_REG_##reg) | |
353 | #define azx_readw(chip,reg) \ | |
354 | readw((chip)->remap_addr + ICH6_REG_##reg) | |
355 | #define azx_writeb(chip,reg,value) \ | |
356 | writeb(value, (chip)->remap_addr + ICH6_REG_##reg) | |
357 | #define azx_readb(chip,reg) \ | |
358 | readb((chip)->remap_addr + ICH6_REG_##reg) | |
359 | ||
360 | #define azx_sd_writel(dev,reg,value) \ | |
361 | writel(value, (dev)->sd_addr + ICH6_REG_##reg) | |
362 | #define azx_sd_readl(dev,reg) \ | |
363 | readl((dev)->sd_addr + ICH6_REG_##reg) | |
364 | #define azx_sd_writew(dev,reg,value) \ | |
365 | writew(value, (dev)->sd_addr + ICH6_REG_##reg) | |
366 | #define azx_sd_readw(dev,reg) \ | |
367 | readw((dev)->sd_addr + ICH6_REG_##reg) | |
368 | #define azx_sd_writeb(dev,reg,value) \ | |
369 | writeb(value, (dev)->sd_addr + ICH6_REG_##reg) | |
370 | #define azx_sd_readb(dev,reg) \ | |
371 | readb((dev)->sd_addr + ICH6_REG_##reg) | |
372 | ||
373 | /* for pcm support */ | |
a98f90fd | 374 | #define get_azx_dev(substream) (substream->runtime->private_data) |
1da177e4 LT |
375 | |
376 | /* Get the upper 32bit of the given dma_addr_t | |
377 | * Compiler should optimize and eliminate the code if dma_addr_t is 32bit | |
378 | */ | |
379 | #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0) | |
380 | ||
381 | ||
382 | /* | |
383 | * Interface for HD codec | |
384 | */ | |
385 | ||
386 | #ifdef USE_CORB_RIRB | |
387 | /* | |
388 | * CORB / RIRB interface | |
389 | */ | |
a98f90fd | 390 | static int azx_alloc_cmd_io(struct azx *chip) |
1da177e4 LT |
391 | { |
392 | int err; | |
393 | ||
394 | /* single page (at least 4096 bytes) must suffice for both ringbuffes */ | |
395 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
396 | PAGE_SIZE, &chip->rb); | |
397 | if (err < 0) { | |
398 | snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n"); | |
399 | return err; | |
400 | } | |
401 | return 0; | |
402 | } | |
403 | ||
a98f90fd | 404 | static void azx_init_cmd_io(struct azx *chip) |
1da177e4 LT |
405 | { |
406 | /* CORB set up */ | |
407 | chip->corb.addr = chip->rb.addr; | |
408 | chip->corb.buf = (u32 *)chip->rb.area; | |
409 | azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); | |
410 | azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr)); | |
411 | ||
07e4ca50 TI |
412 | /* set the corb size to 256 entries (ULI requires explicitly) */ |
413 | azx_writeb(chip, CORBSIZE, 0x02); | |
1da177e4 LT |
414 | /* set the corb write pointer to 0 */ |
415 | azx_writew(chip, CORBWP, 0); | |
416 | /* reset the corb hw read pointer */ | |
417 | azx_writew(chip, CORBRP, ICH6_RBRWP_CLR); | |
418 | /* enable corb dma */ | |
419 | azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN); | |
420 | ||
421 | /* RIRB set up */ | |
422 | chip->rirb.addr = chip->rb.addr + 2048; | |
423 | chip->rirb.buf = (u32 *)(chip->rb.area + 2048); | |
424 | azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); | |
425 | azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr)); | |
426 | ||
07e4ca50 TI |
427 | /* set the rirb size to 256 entries (ULI requires explicitly) */ |
428 | azx_writeb(chip, RIRBSIZE, 0x02); | |
1da177e4 LT |
429 | /* reset the rirb hw write pointer */ |
430 | azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR); | |
431 | /* set N=1, get RIRB response interrupt for new entry */ | |
432 | azx_writew(chip, RINTCNT, 1); | |
433 | /* enable rirb dma and response irq */ | |
434 | #ifdef USE_CORB_RIRB | |
435 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); | |
436 | #else | |
437 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN); | |
438 | #endif | |
439 | chip->rirb.rp = chip->rirb.cmds = 0; | |
440 | } | |
441 | ||
a98f90fd | 442 | static void azx_free_cmd_io(struct azx *chip) |
1da177e4 LT |
443 | { |
444 | /* disable ringbuffer DMAs */ | |
445 | azx_writeb(chip, RIRBCTL, 0); | |
446 | azx_writeb(chip, CORBCTL, 0); | |
447 | } | |
448 | ||
449 | /* send a command */ | |
450 | static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct, | |
451 | unsigned int verb, unsigned int para) | |
452 | { | |
a98f90fd | 453 | struct azx *chip = codec->bus->private_data; |
1da177e4 LT |
454 | unsigned int wp; |
455 | u32 val; | |
456 | ||
457 | val = (u32)(codec->addr & 0x0f) << 28; | |
458 | val |= (u32)direct << 27; | |
459 | val |= (u32)nid << 20; | |
460 | val |= verb << 8; | |
461 | val |= para; | |
462 | ||
463 | /* add command to corb */ | |
464 | wp = azx_readb(chip, CORBWP); | |
465 | wp++; | |
466 | wp %= ICH6_MAX_CORB_ENTRIES; | |
467 | ||
468 | spin_lock_irq(&chip->reg_lock); | |
469 | chip->rirb.cmds++; | |
470 | chip->corb.buf[wp] = cpu_to_le32(val); | |
471 | azx_writel(chip, CORBWP, wp); | |
472 | spin_unlock_irq(&chip->reg_lock); | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
477 | #define ICH6_RIRB_EX_UNSOL_EV (1<<4) | |
478 | ||
479 | /* retrieve RIRB entry - called from interrupt handler */ | |
a98f90fd | 480 | static void azx_update_rirb(struct azx *chip) |
1da177e4 LT |
481 | { |
482 | unsigned int rp, wp; | |
483 | u32 res, res_ex; | |
484 | ||
485 | wp = azx_readb(chip, RIRBWP); | |
486 | if (wp == chip->rirb.wp) | |
487 | return; | |
488 | chip->rirb.wp = wp; | |
489 | ||
490 | while (chip->rirb.rp != wp) { | |
491 | chip->rirb.rp++; | |
492 | chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; | |
493 | ||
494 | rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ | |
495 | res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); | |
496 | res = le32_to_cpu(chip->rirb.buf[rp]); | |
497 | if (res_ex & ICH6_RIRB_EX_UNSOL_EV) | |
498 | snd_hda_queue_unsol_event(chip->bus, res, res_ex); | |
499 | else if (chip->rirb.cmds) { | |
500 | chip->rirb.cmds--; | |
501 | chip->rirb.res = res; | |
502 | } | |
503 | } | |
504 | } | |
505 | ||
506 | /* receive a response */ | |
507 | static unsigned int azx_get_response(struct hda_codec *codec) | |
508 | { | |
a98f90fd | 509 | struct azx *chip = codec->bus->private_data; |
1da177e4 LT |
510 | int timeout = 50; |
511 | ||
512 | while (chip->rirb.cmds) { | |
513 | if (! --timeout) { | |
362775e2 RD |
514 | if (printk_ratelimit()) |
515 | snd_printk(KERN_ERR | |
516 | "azx_get_response timeout\n"); | |
1da177e4 LT |
517 | chip->rirb.rp = azx_readb(chip, RIRBWP); |
518 | chip->rirb.cmds = 0; | |
519 | return -1; | |
520 | } | |
521 | msleep(1); | |
522 | } | |
523 | return chip->rirb.res; /* the last value */ | |
524 | } | |
525 | ||
526 | #else | |
527 | /* | |
528 | * Use the single immediate command instead of CORB/RIRB for simplicity | |
529 | * | |
530 | * Note: according to Intel, this is not preferred use. The command was | |
531 | * intended for the BIOS only, and may get confused with unsolicited | |
532 | * responses. So, we shouldn't use it for normal operation from the | |
533 | * driver. | |
534 | * I left the codes, however, for debugging/testing purposes. | |
535 | */ | |
536 | ||
537 | #define azx_alloc_cmd_io(chip) 0 | |
538 | #define azx_init_cmd_io(chip) | |
539 | #define azx_free_cmd_io(chip) | |
540 | ||
541 | /* send a command */ | |
542 | static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct, | |
543 | unsigned int verb, unsigned int para) | |
544 | { | |
a98f90fd | 545 | struct azx *chip = codec->bus->private_data; |
1da177e4 LT |
546 | u32 val; |
547 | int timeout = 50; | |
548 | ||
549 | val = (u32)(codec->addr & 0x0f) << 28; | |
550 | val |= (u32)direct << 27; | |
551 | val |= (u32)nid << 20; | |
552 | val |= verb << 8; | |
553 | val |= para; | |
554 | ||
555 | while (timeout--) { | |
556 | /* check ICB busy bit */ | |
557 | if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) { | |
558 | /* Clear IRV valid bit */ | |
559 | azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID); | |
560 | azx_writel(chip, IC, val); | |
561 | azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY); | |
562 | return 0; | |
563 | } | |
564 | udelay(1); | |
565 | } | |
566 | snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val); | |
567 | return -EIO; | |
568 | } | |
569 | ||
570 | /* receive a response */ | |
571 | static unsigned int azx_get_response(struct hda_codec *codec) | |
572 | { | |
a98f90fd | 573 | struct azx *chip = codec->bus->private_data; |
1da177e4 LT |
574 | int timeout = 50; |
575 | ||
576 | while (timeout--) { | |
577 | /* check IRV busy bit */ | |
578 | if (azx_readw(chip, IRS) & ICH6_IRS_VALID) | |
579 | return azx_readl(chip, IR); | |
580 | udelay(1); | |
581 | } | |
582 | snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS)); | |
583 | return (unsigned int)-1; | |
584 | } | |
585 | ||
586 | #define azx_update_rirb(chip) | |
587 | ||
588 | #endif /* USE_CORB_RIRB */ | |
589 | ||
590 | /* reset codec link */ | |
a98f90fd | 591 | static int azx_reset(struct azx *chip) |
1da177e4 LT |
592 | { |
593 | int count; | |
594 | ||
595 | /* reset controller */ | |
596 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); | |
597 | ||
598 | count = 50; | |
599 | while (azx_readb(chip, GCTL) && --count) | |
600 | msleep(1); | |
601 | ||
602 | /* delay for >= 100us for codec PLL to settle per spec | |
603 | * Rev 0.9 section 5.5.1 | |
604 | */ | |
605 | msleep(1); | |
606 | ||
607 | /* Bring controller out of reset */ | |
608 | azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); | |
609 | ||
610 | count = 50; | |
611 | while (! azx_readb(chip, GCTL) && --count) | |
612 | msleep(1); | |
613 | ||
614 | /* Brent Chartrand said to wait >= 540us for codecs to intialize */ | |
615 | msleep(1); | |
616 | ||
617 | /* check to see if controller is ready */ | |
618 | if (! azx_readb(chip, GCTL)) { | |
619 | snd_printd("azx_reset: controller not ready!\n"); | |
620 | return -EBUSY; | |
621 | } | |
622 | ||
41e2fce4 M |
623 | /* Accept unsolicited responses */ |
624 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN); | |
625 | ||
1da177e4 LT |
626 | /* detect codecs */ |
627 | if (! chip->codec_mask) { | |
628 | chip->codec_mask = azx_readw(chip, STATESTS); | |
629 | snd_printdd("codec_mask = 0x%x\n", chip->codec_mask); | |
630 | } | |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
635 | ||
636 | /* | |
637 | * Lowlevel interface | |
638 | */ | |
639 | ||
640 | /* enable interrupts */ | |
a98f90fd | 641 | static void azx_int_enable(struct azx *chip) |
1da177e4 LT |
642 | { |
643 | /* enable controller CIE and GIE */ | |
644 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | | |
645 | ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); | |
646 | } | |
647 | ||
648 | /* disable interrupts */ | |
a98f90fd | 649 | static void azx_int_disable(struct azx *chip) |
1da177e4 LT |
650 | { |
651 | int i; | |
652 | ||
653 | /* disable interrupts in stream descriptor */ | |
07e4ca50 | 654 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 655 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
656 | azx_sd_writeb(azx_dev, SD_CTL, |
657 | azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); | |
658 | } | |
659 | ||
660 | /* disable SIE for all streams */ | |
661 | azx_writeb(chip, INTCTL, 0); | |
662 | ||
663 | /* disable controller CIE and GIE */ | |
664 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & | |
665 | ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); | |
666 | } | |
667 | ||
668 | /* clear interrupts */ | |
a98f90fd | 669 | static void azx_int_clear(struct azx *chip) |
1da177e4 LT |
670 | { |
671 | int i; | |
672 | ||
673 | /* clear stream status */ | |
07e4ca50 | 674 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 675 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
676 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); |
677 | } | |
678 | ||
679 | /* clear STATESTS */ | |
680 | azx_writeb(chip, STATESTS, STATESTS_INT_MASK); | |
681 | ||
682 | /* clear rirb status */ | |
683 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
684 | ||
685 | /* clear int status */ | |
686 | azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); | |
687 | } | |
688 | ||
689 | /* start a stream */ | |
a98f90fd | 690 | static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) |
1da177e4 LT |
691 | { |
692 | /* enable SIE */ | |
693 | azx_writeb(chip, INTCTL, | |
694 | azx_readb(chip, INTCTL) | (1 << azx_dev->index)); | |
695 | /* set DMA start and interrupt mask */ | |
696 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | | |
697 | SD_CTL_DMA_START | SD_INT_MASK); | |
698 | } | |
699 | ||
700 | /* stop a stream */ | |
a98f90fd | 701 | static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) |
1da177e4 LT |
702 | { |
703 | /* stop DMA */ | |
704 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & | |
705 | ~(SD_CTL_DMA_START | SD_INT_MASK)); | |
706 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | |
707 | /* disable SIE */ | |
708 | azx_writeb(chip, INTCTL, | |
709 | azx_readb(chip, INTCTL) & ~(1 << azx_dev->index)); | |
710 | } | |
711 | ||
712 | ||
713 | /* | |
714 | * initialize the chip | |
715 | */ | |
a98f90fd | 716 | static void azx_init_chip(struct azx *chip) |
1da177e4 | 717 | { |
da3fca21 | 718 | unsigned char reg; |
1da177e4 LT |
719 | |
720 | /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) | |
721 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | |
722 | * Ensuring these bits are 0 clears playback static on some HD Audio codecs | |
723 | */ | |
da3fca21 V |
724 | pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, ®); |
725 | pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, reg & 0xf8); | |
1da177e4 LT |
726 | |
727 | /* reset controller */ | |
728 | azx_reset(chip); | |
729 | ||
730 | /* initialize interrupts */ | |
731 | azx_int_clear(chip); | |
732 | azx_int_enable(chip); | |
733 | ||
734 | /* initialize the codec command I/O */ | |
735 | azx_init_cmd_io(chip); | |
736 | ||
0be3b5d3 TI |
737 | /* program the position buffer */ |
738 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); | |
739 | azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr)); | |
f5d40b30 | 740 | |
da3fca21 V |
741 | switch (chip->driver_type) { |
742 | case AZX_DRIVER_ATI: | |
743 | /* For ATI SB450 azalia HD audio, we need to enable snoop */ | |
f5d40b30 | 744 | pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, |
da3fca21 | 745 | ®); |
f5d40b30 | 746 | pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, |
da3fca21 V |
747 | (reg & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP); |
748 | break; | |
749 | case AZX_DRIVER_NVIDIA: | |
750 | /* For NVIDIA HDA, enable snoop */ | |
751 | pci_read_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, ®); | |
752 | pci_write_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, | |
753 | (reg & 0xf0) | NVIDIA_HDA_ENABLE_COHBITS); | |
754 | break; | |
755 | } | |
1da177e4 LT |
756 | } |
757 | ||
758 | ||
759 | /* | |
760 | * interrupt handler | |
761 | */ | |
762 | static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs) | |
763 | { | |
a98f90fd TI |
764 | struct azx *chip = dev_id; |
765 | struct azx_dev *azx_dev; | |
1da177e4 LT |
766 | u32 status; |
767 | int i; | |
768 | ||
769 | spin_lock(&chip->reg_lock); | |
770 | ||
771 | status = azx_readl(chip, INTSTS); | |
772 | if (status == 0) { | |
773 | spin_unlock(&chip->reg_lock); | |
774 | return IRQ_NONE; | |
775 | } | |
776 | ||
07e4ca50 | 777 | for (i = 0; i < chip->num_streams; i++) { |
1da177e4 LT |
778 | azx_dev = &chip->azx_dev[i]; |
779 | if (status & azx_dev->sd_int_sta_mask) { | |
780 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); | |
781 | if (azx_dev->substream && azx_dev->running) { | |
0be3b5d3 | 782 | azx_dev->period_updating = 1; |
1da177e4 LT |
783 | spin_unlock(&chip->reg_lock); |
784 | snd_pcm_period_elapsed(azx_dev->substream); | |
785 | spin_lock(&chip->reg_lock); | |
0be3b5d3 | 786 | azx_dev->period_updating = 0; |
1da177e4 LT |
787 | } |
788 | } | |
789 | } | |
790 | ||
791 | /* clear rirb int */ | |
792 | status = azx_readb(chip, RIRBSTS); | |
793 | if (status & RIRB_INT_MASK) { | |
794 | if (status & RIRB_INT_RESPONSE) | |
795 | azx_update_rirb(chip); | |
796 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
797 | } | |
798 | ||
799 | #if 0 | |
800 | /* clear state status int */ | |
801 | if (azx_readb(chip, STATESTS) & 0x04) | |
802 | azx_writeb(chip, STATESTS, 0x04); | |
803 | #endif | |
804 | spin_unlock(&chip->reg_lock); | |
805 | ||
806 | return IRQ_HANDLED; | |
807 | } | |
808 | ||
809 | ||
810 | /* | |
811 | * set up BDL entries | |
812 | */ | |
a98f90fd | 813 | static void azx_setup_periods(struct azx_dev *azx_dev) |
1da177e4 LT |
814 | { |
815 | u32 *bdl = azx_dev->bdl; | |
816 | dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr; | |
817 | int idx; | |
818 | ||
819 | /* reset BDL address */ | |
820 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
821 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
822 | ||
823 | /* program the initial BDL entries */ | |
824 | for (idx = 0; idx < azx_dev->frags; idx++) { | |
825 | unsigned int off = idx << 2; /* 4 dword step */ | |
826 | dma_addr_t addr = dma_addr + idx * azx_dev->fragsize; | |
827 | /* program the address field of the BDL entry */ | |
828 | bdl[off] = cpu_to_le32((u32)addr); | |
829 | bdl[off+1] = cpu_to_le32(upper_32bit(addr)); | |
830 | ||
831 | /* program the size field of the BDL entry */ | |
832 | bdl[off+2] = cpu_to_le32(azx_dev->fragsize); | |
833 | ||
834 | /* program the IOC to enable interrupt when buffer completes */ | |
835 | bdl[off+3] = cpu_to_le32(0x01); | |
836 | } | |
837 | } | |
838 | ||
839 | /* | |
840 | * set up the SD for streaming | |
841 | */ | |
a98f90fd | 842 | static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) |
1da177e4 LT |
843 | { |
844 | unsigned char val; | |
845 | int timeout; | |
846 | ||
847 | /* make sure the run bit is zero for SD */ | |
848 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START); | |
849 | /* reset stream */ | |
850 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET); | |
851 | udelay(3); | |
852 | timeout = 300; | |
853 | while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
854 | --timeout) | |
855 | ; | |
856 | val &= ~SD_CTL_STREAM_RESET; | |
857 | azx_sd_writeb(azx_dev, SD_CTL, val); | |
858 | udelay(3); | |
859 | ||
860 | timeout = 300; | |
861 | /* waiting for hardware to report that the stream is out of reset */ | |
862 | while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
863 | --timeout) | |
864 | ; | |
865 | ||
866 | /* program the stream_tag */ | |
867 | azx_sd_writel(azx_dev, SD_CTL, | |
868 | (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) | | |
869 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); | |
870 | ||
871 | /* program the length of samples in cyclic buffer */ | |
872 | azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); | |
873 | ||
874 | /* program the stream format */ | |
875 | /* this value needs to be the same as the one programmed */ | |
876 | azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); | |
877 | ||
878 | /* program the stream LVI (last valid index) of the BDL */ | |
879 | azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); | |
880 | ||
881 | /* program the BDL address */ | |
882 | /* lower BDL address */ | |
883 | azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr); | |
884 | /* upper BDL address */ | |
885 | azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr)); | |
886 | ||
0be3b5d3 TI |
887 | /* enable the position buffer */ |
888 | if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) | |
889 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); | |
c74db86b | 890 | |
1da177e4 LT |
891 | /* set the interrupt enable bits in the descriptor control register */ |
892 | azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); | |
893 | ||
894 | return 0; | |
895 | } | |
896 | ||
897 | ||
898 | /* | |
899 | * Codec initialization | |
900 | */ | |
901 | ||
a98f90fd | 902 | static int __devinit azx_codec_create(struct azx *chip, const char *model) |
1da177e4 LT |
903 | { |
904 | struct hda_bus_template bus_temp; | |
905 | int c, codecs, err; | |
906 | ||
907 | memset(&bus_temp, 0, sizeof(bus_temp)); | |
908 | bus_temp.private_data = chip; | |
909 | bus_temp.modelname = model; | |
910 | bus_temp.pci = chip->pci; | |
911 | bus_temp.ops.command = azx_send_cmd; | |
912 | bus_temp.ops.get_response = azx_get_response; | |
913 | ||
914 | if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0) | |
915 | return err; | |
916 | ||
917 | codecs = 0; | |
918 | for (c = 0; c < AZX_MAX_CODECS; c++) { | |
919 | if (chip->codec_mask & (1 << c)) { | |
920 | err = snd_hda_codec_new(chip->bus, c, NULL); | |
921 | if (err < 0) | |
922 | continue; | |
923 | codecs++; | |
924 | } | |
925 | } | |
926 | if (! codecs) { | |
927 | snd_printk(KERN_ERR SFX "no codecs initialized\n"); | |
928 | return -ENXIO; | |
929 | } | |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
934 | ||
935 | /* | |
936 | * PCM support | |
937 | */ | |
938 | ||
939 | /* assign a stream for the PCM */ | |
a98f90fd | 940 | static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream) |
1da177e4 | 941 | { |
07e4ca50 TI |
942 | int dev, i, nums; |
943 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
944 | dev = chip->playback_index_offset; | |
945 | nums = chip->playback_streams; | |
946 | } else { | |
947 | dev = chip->capture_index_offset; | |
948 | nums = chip->capture_streams; | |
949 | } | |
950 | for (i = 0; i < nums; i++, dev++) | |
1da177e4 LT |
951 | if (! chip->azx_dev[dev].opened) { |
952 | chip->azx_dev[dev].opened = 1; | |
953 | return &chip->azx_dev[dev]; | |
954 | } | |
955 | return NULL; | |
956 | } | |
957 | ||
958 | /* release the assigned stream */ | |
a98f90fd | 959 | static inline void azx_release_device(struct azx_dev *azx_dev) |
1da177e4 LT |
960 | { |
961 | azx_dev->opened = 0; | |
962 | } | |
963 | ||
a98f90fd | 964 | static struct snd_pcm_hardware azx_pcm_hw = { |
1da177e4 LT |
965 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | |
966 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
967 | SNDRV_PCM_INFO_MMAP_VALID | | |
47123197 JK |
968 | SNDRV_PCM_INFO_PAUSE /*|*/ |
969 | /*SNDRV_PCM_INFO_RESUME*/), | |
1da177e4 LT |
970 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
971 | .rates = SNDRV_PCM_RATE_48000, | |
972 | .rate_min = 48000, | |
973 | .rate_max = 48000, | |
974 | .channels_min = 2, | |
975 | .channels_max = 2, | |
976 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, | |
977 | .period_bytes_min = 128, | |
978 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | |
979 | .periods_min = 2, | |
980 | .periods_max = AZX_MAX_FRAG, | |
981 | .fifo_size = 0, | |
982 | }; | |
983 | ||
984 | struct azx_pcm { | |
a98f90fd | 985 | struct azx *chip; |
1da177e4 LT |
986 | struct hda_codec *codec; |
987 | struct hda_pcm_stream *hinfo[2]; | |
988 | }; | |
989 | ||
a98f90fd | 990 | static int azx_pcm_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
991 | { |
992 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
993 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
a98f90fd TI |
994 | struct azx *chip = apcm->chip; |
995 | struct azx_dev *azx_dev; | |
996 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
997 | unsigned long flags; |
998 | int err; | |
999 | ||
1000 | down(&chip->open_mutex); | |
1001 | azx_dev = azx_assign_device(chip, substream->stream); | |
1002 | if (azx_dev == NULL) { | |
1003 | up(&chip->open_mutex); | |
1004 | return -EBUSY; | |
1005 | } | |
1006 | runtime->hw = azx_pcm_hw; | |
1007 | runtime->hw.channels_min = hinfo->channels_min; | |
1008 | runtime->hw.channels_max = hinfo->channels_max; | |
1009 | runtime->hw.formats = hinfo->formats; | |
1010 | runtime->hw.rates = hinfo->rates; | |
1011 | snd_pcm_limit_hw_rates(runtime); | |
1012 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | |
1013 | if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) { | |
1014 | azx_release_device(azx_dev); | |
1015 | up(&chip->open_mutex); | |
1016 | return err; | |
1017 | } | |
1018 | spin_lock_irqsave(&chip->reg_lock, flags); | |
1019 | azx_dev->substream = substream; | |
1020 | azx_dev->running = 0; | |
1021 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
1022 | ||
1023 | runtime->private_data = azx_dev; | |
1024 | up(&chip->open_mutex); | |
1025 | return 0; | |
1026 | } | |
1027 | ||
a98f90fd | 1028 | static int azx_pcm_close(struct snd_pcm_substream *substream) |
1da177e4 LT |
1029 | { |
1030 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1031 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
a98f90fd TI |
1032 | struct azx *chip = apcm->chip; |
1033 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 LT |
1034 | unsigned long flags; |
1035 | ||
1036 | down(&chip->open_mutex); | |
1037 | spin_lock_irqsave(&chip->reg_lock, flags); | |
1038 | azx_dev->substream = NULL; | |
1039 | azx_dev->running = 0; | |
1040 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
1041 | azx_release_device(azx_dev); | |
1042 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
1043 | up(&chip->open_mutex); | |
1044 | return 0; | |
1045 | } | |
1046 | ||
a98f90fd | 1047 | static int azx_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) |
1da177e4 LT |
1048 | { |
1049 | return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
1050 | } | |
1051 | ||
a98f90fd | 1052 | static int azx_pcm_hw_free(struct snd_pcm_substream *substream) |
1da177e4 LT |
1053 | { |
1054 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd | 1055 | struct azx_dev *azx_dev = get_azx_dev(substream); |
1da177e4 LT |
1056 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
1057 | ||
1058 | /* reset BDL address */ | |
1059 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
1060 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
1061 | azx_sd_writel(azx_dev, SD_CTL, 0); | |
1062 | ||
1063 | hinfo->ops.cleanup(hinfo, apcm->codec, substream); | |
1064 | ||
1065 | return snd_pcm_lib_free_pages(substream); | |
1066 | } | |
1067 | ||
a98f90fd | 1068 | static int azx_pcm_prepare(struct snd_pcm_substream *substream) |
1da177e4 LT |
1069 | { |
1070 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd TI |
1071 | struct azx *chip = apcm->chip; |
1072 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 | 1073 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
a98f90fd | 1074 | struct snd_pcm_runtime *runtime = substream->runtime; |
1da177e4 LT |
1075 | |
1076 | azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream); | |
1077 | azx_dev->fragsize = snd_pcm_lib_period_bytes(substream); | |
1078 | azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize; | |
1079 | azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate, | |
1080 | runtime->channels, | |
1081 | runtime->format, | |
1082 | hinfo->maxbps); | |
1083 | if (! azx_dev->format_val) { | |
1084 | snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n", | |
1085 | runtime->rate, runtime->channels, runtime->format); | |
1086 | return -EINVAL; | |
1087 | } | |
1088 | ||
1089 | snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n", | |
1090 | azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val); | |
1091 | azx_setup_periods(azx_dev); | |
1092 | azx_setup_controller(chip, azx_dev); | |
1093 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1094 | azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; | |
1095 | else | |
1096 | azx_dev->fifo_size = 0; | |
0be3b5d3 | 1097 | azx_dev->last_pos = 0; |
1da177e4 LT |
1098 | |
1099 | return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag, | |
1100 | azx_dev->format_val, substream); | |
1101 | } | |
1102 | ||
a98f90fd | 1103 | static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 LT |
1104 | { |
1105 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd TI |
1106 | struct azx_dev *azx_dev = get_azx_dev(substream); |
1107 | struct azx *chip = apcm->chip; | |
1da177e4 LT |
1108 | int err = 0; |
1109 | ||
1110 | spin_lock(&chip->reg_lock); | |
1111 | switch (cmd) { | |
1112 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
1113 | case SNDRV_PCM_TRIGGER_RESUME: | |
1114 | case SNDRV_PCM_TRIGGER_START: | |
1115 | azx_stream_start(chip, azx_dev); | |
1116 | azx_dev->running = 1; | |
1117 | break; | |
1118 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
47123197 | 1119 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1da177e4 LT |
1120 | case SNDRV_PCM_TRIGGER_STOP: |
1121 | azx_stream_stop(chip, azx_dev); | |
1122 | azx_dev->running = 0; | |
1123 | break; | |
1124 | default: | |
1125 | err = -EINVAL; | |
1126 | } | |
1127 | spin_unlock(&chip->reg_lock); | |
1128 | if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH || | |
47123197 | 1129 | cmd == SNDRV_PCM_TRIGGER_SUSPEND || |
1da177e4 LT |
1130 | cmd == SNDRV_PCM_TRIGGER_STOP) { |
1131 | int timeout = 5000; | |
1132 | while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout) | |
1133 | ; | |
1134 | } | |
1135 | return err; | |
1136 | } | |
1137 | ||
a98f90fd | 1138 | static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 1139 | { |
c74db86b | 1140 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
a98f90fd TI |
1141 | struct azx *chip = apcm->chip; |
1142 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 LT |
1143 | unsigned int pos; |
1144 | ||
c74db86b TI |
1145 | if (chip->position_fix == POS_FIX_POSBUF) { |
1146 | /* use the position buffer */ | |
1147 | pos = *azx_dev->posbuf; | |
1148 | } else { | |
1149 | /* read LPIB */ | |
1150 | pos = azx_sd_readl(azx_dev, SD_LPIB); | |
1151 | if (chip->position_fix == POS_FIX_FIFO) | |
1152 | pos += azx_dev->fifo_size; | |
e8dede5a | 1153 | #if 0 /* disabled temprarily, auto-correction doesn't work well... */ |
0be3b5d3 TI |
1154 | else if (chip->position_fix == POS_FIX_AUTO && azx_dev->period_updating) { |
1155 | /* check the validity of DMA position */ | |
1156 | unsigned int diff = 0; | |
1157 | azx_dev->last_pos += azx_dev->fragsize; | |
1158 | if (azx_dev->last_pos > pos) | |
1159 | diff = azx_dev->last_pos - pos; | |
1160 | if (azx_dev->last_pos >= azx_dev->bufsize) { | |
1161 | if (pos < azx_dev->fragsize) | |
1162 | diff = 0; | |
1163 | azx_dev->last_pos = 0; | |
1164 | } | |
1165 | if (diff > 0 && diff <= azx_dev->fifo_size) | |
1166 | pos += azx_dev->fifo_size; | |
1167 | else { | |
1168 | snd_printdd(KERN_INFO "hda_intel: DMA position fix %d, switching to posbuf\n", diff); | |
1169 | chip->position_fix = POS_FIX_POSBUF; | |
1170 | pos = *azx_dev->posbuf; | |
1171 | } | |
1172 | azx_dev->period_updating = 0; | |
1173 | } | |
e8dede5a TI |
1174 | #else |
1175 | else if (chip->position_fix == POS_FIX_AUTO) | |
1176 | pos += azx_dev->fifo_size; | |
1177 | #endif | |
c74db86b | 1178 | } |
1da177e4 LT |
1179 | if (pos >= azx_dev->bufsize) |
1180 | pos = 0; | |
1181 | return bytes_to_frames(substream->runtime, pos); | |
1182 | } | |
1183 | ||
a98f90fd | 1184 | static struct snd_pcm_ops azx_pcm_ops = { |
1da177e4 LT |
1185 | .open = azx_pcm_open, |
1186 | .close = azx_pcm_close, | |
1187 | .ioctl = snd_pcm_lib_ioctl, | |
1188 | .hw_params = azx_pcm_hw_params, | |
1189 | .hw_free = azx_pcm_hw_free, | |
1190 | .prepare = azx_pcm_prepare, | |
1191 | .trigger = azx_pcm_trigger, | |
1192 | .pointer = azx_pcm_pointer, | |
1193 | }; | |
1194 | ||
a98f90fd | 1195 | static void azx_pcm_free(struct snd_pcm *pcm) |
1da177e4 LT |
1196 | { |
1197 | kfree(pcm->private_data); | |
1198 | } | |
1199 | ||
a98f90fd | 1200 | static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec, |
1da177e4 LT |
1201 | struct hda_pcm *cpcm, int pcm_dev) |
1202 | { | |
1203 | int err; | |
a98f90fd | 1204 | struct snd_pcm *pcm; |
1da177e4 LT |
1205 | struct azx_pcm *apcm; |
1206 | ||
1207 | snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL); | |
1208 | snd_assert(cpcm->name, return -EINVAL); | |
1209 | ||
1210 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, | |
1211 | cpcm->stream[0].substreams, cpcm->stream[1].substreams, | |
1212 | &pcm); | |
1213 | if (err < 0) | |
1214 | return err; | |
1215 | strcpy(pcm->name, cpcm->name); | |
1216 | apcm = kmalloc(sizeof(*apcm), GFP_KERNEL); | |
1217 | if (apcm == NULL) | |
1218 | return -ENOMEM; | |
1219 | apcm->chip = chip; | |
1220 | apcm->codec = codec; | |
1221 | apcm->hinfo[0] = &cpcm->stream[0]; | |
1222 | apcm->hinfo[1] = &cpcm->stream[1]; | |
1223 | pcm->private_data = apcm; | |
1224 | pcm->private_free = azx_pcm_free; | |
1225 | if (cpcm->stream[0].substreams) | |
1226 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops); | |
1227 | if (cpcm->stream[1].substreams) | |
1228 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops); | |
1229 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1230 | snd_dma_pci_data(chip->pci), | |
1231 | 1024 * 64, 1024 * 128); | |
1232 | chip->pcm[pcm_dev] = pcm; | |
47123197 | 1233 | chip->pcm_devs = pcm_dev + 1; |
1da177e4 LT |
1234 | |
1235 | return 0; | |
1236 | } | |
1237 | ||
a98f90fd | 1238 | static int __devinit azx_pcm_create(struct azx *chip) |
1da177e4 LT |
1239 | { |
1240 | struct list_head *p; | |
1241 | struct hda_codec *codec; | |
1242 | int c, err; | |
1243 | int pcm_dev; | |
1244 | ||
1245 | if ((err = snd_hda_build_pcms(chip->bus)) < 0) | |
1246 | return err; | |
1247 | ||
ec9e1c5c | 1248 | /* create audio PCMs */ |
1da177e4 LT |
1249 | pcm_dev = 0; |
1250 | list_for_each(p, &chip->bus->codec_list) { | |
1251 | codec = list_entry(p, struct hda_codec, list); | |
1252 | for (c = 0; c < codec->num_pcms; c++) { | |
ec9e1c5c TI |
1253 | if (codec->pcm_info[c].is_modem) |
1254 | continue; /* create later */ | |
1255 | if (pcm_dev >= AZX_MAX_AUDIO_PCMS) { | |
1256 | snd_printk(KERN_ERR SFX "Too many audio PCMs\n"); | |
1257 | return -EINVAL; | |
1258 | } | |
1259 | err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev); | |
1260 | if (err < 0) | |
1261 | return err; | |
1262 | pcm_dev++; | |
1263 | } | |
1264 | } | |
1265 | ||
1266 | /* create modem PCMs */ | |
1267 | pcm_dev = AZX_MAX_AUDIO_PCMS; | |
1268 | list_for_each(p, &chip->bus->codec_list) { | |
1269 | codec = list_entry(p, struct hda_codec, list); | |
1270 | for (c = 0; c < codec->num_pcms; c++) { | |
1271 | if (! codec->pcm_info[c].is_modem) | |
1272 | continue; /* already created */ | |
a28f1cda | 1273 | if (pcm_dev >= AZX_MAX_PCMS) { |
ec9e1c5c | 1274 | snd_printk(KERN_ERR SFX "Too many modem PCMs\n"); |
1da177e4 LT |
1275 | return -EINVAL; |
1276 | } | |
1277 | err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev); | |
1278 | if (err < 0) | |
1279 | return err; | |
6632d198 | 1280 | chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM; |
1da177e4 LT |
1281 | pcm_dev++; |
1282 | } | |
1283 | } | |
1284 | return 0; | |
1285 | } | |
1286 | ||
1287 | /* | |
1288 | * mixer creation - all stuff is implemented in hda module | |
1289 | */ | |
a98f90fd | 1290 | static int __devinit azx_mixer_create(struct azx *chip) |
1da177e4 LT |
1291 | { |
1292 | return snd_hda_build_controls(chip->bus); | |
1293 | } | |
1294 | ||
1295 | ||
1296 | /* | |
1297 | * initialize SD streams | |
1298 | */ | |
a98f90fd | 1299 | static int __devinit azx_init_stream(struct azx *chip) |
1da177e4 LT |
1300 | { |
1301 | int i; | |
1302 | ||
1303 | /* initialize each stream (aka device) | |
1304 | * assign the starting bdl address to each stream (device) and initialize | |
1305 | */ | |
07e4ca50 | 1306 | for (i = 0; i < chip->num_streams; i++) { |
1da177e4 | 1307 | unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4); |
a98f90fd | 1308 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
1309 | azx_dev->bdl = (u32 *)(chip->bdl.area + off); |
1310 | azx_dev->bdl_addr = chip->bdl.addr + off; | |
0be3b5d3 | 1311 | azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8); |
1da177e4 LT |
1312 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
1313 | azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); | |
1314 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ | |
1315 | azx_dev->sd_int_sta_mask = 1 << i; | |
1316 | /* stream tag: must be non-zero and unique */ | |
1317 | azx_dev->index = i; | |
1318 | azx_dev->stream_tag = i + 1; | |
1319 | } | |
1320 | ||
1321 | return 0; | |
1322 | } | |
1323 | ||
1324 | ||
1325 | #ifdef CONFIG_PM | |
1326 | /* | |
1327 | * power management | |
1328 | */ | |
421a1252 | 1329 | static int azx_suspend(struct pci_dev *pci, pm_message_t state) |
1da177e4 | 1330 | { |
421a1252 TI |
1331 | struct snd_card *card = pci_get_drvdata(pci); |
1332 | struct azx *chip = card->private_data; | |
1da177e4 LT |
1333 | int i; |
1334 | ||
421a1252 | 1335 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
1da177e4 | 1336 | for (i = 0; i < chip->pcm_devs; i++) |
421a1252 | 1337 | snd_pcm_suspend_all(chip->pcm[i]); |
1da177e4 LT |
1338 | snd_hda_suspend(chip->bus, state); |
1339 | azx_free_cmd_io(chip); | |
421a1252 TI |
1340 | pci_disable_device(pci); |
1341 | pci_save_state(pci); | |
1da177e4 LT |
1342 | return 0; |
1343 | } | |
1344 | ||
421a1252 | 1345 | static int azx_resume(struct pci_dev *pci) |
1da177e4 | 1346 | { |
421a1252 TI |
1347 | struct snd_card *card = pci_get_drvdata(pci); |
1348 | struct azx *chip = card->private_data; | |
1da177e4 | 1349 | |
421a1252 TI |
1350 | pci_restore_state(pci); |
1351 | pci_enable_device(pci); | |
1352 | pci_set_master(pci); | |
1da177e4 LT |
1353 | azx_init_chip(chip); |
1354 | snd_hda_resume(chip->bus); | |
421a1252 | 1355 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
1da177e4 LT |
1356 | return 0; |
1357 | } | |
1358 | #endif /* CONFIG_PM */ | |
1359 | ||
1360 | ||
1361 | /* | |
1362 | * destructor | |
1363 | */ | |
a98f90fd | 1364 | static int azx_free(struct azx *chip) |
1da177e4 | 1365 | { |
ce43fbae | 1366 | if (chip->initialized) { |
1da177e4 LT |
1367 | int i; |
1368 | ||
07e4ca50 | 1369 | for (i = 0; i < chip->num_streams; i++) |
1da177e4 LT |
1370 | azx_stream_stop(chip, &chip->azx_dev[i]); |
1371 | ||
1372 | /* disable interrupts */ | |
1373 | azx_int_disable(chip); | |
1374 | azx_int_clear(chip); | |
1375 | ||
1376 | /* disable CORB/RIRB */ | |
1377 | azx_free_cmd_io(chip); | |
1378 | ||
1379 | /* disable position buffer */ | |
1380 | azx_writel(chip, DPLBASE, 0); | |
1381 | azx_writel(chip, DPUBASE, 0); | |
1382 | ||
1383 | /* wait a little for interrupts to finish */ | |
1384 | msleep(1); | |
1da177e4 LT |
1385 | } |
1386 | ||
07e4ca50 TI |
1387 | if (chip->remap_addr) |
1388 | iounmap(chip->remap_addr); | |
1da177e4 LT |
1389 | if (chip->irq >= 0) |
1390 | free_irq(chip->irq, (void*)chip); | |
1391 | ||
1392 | if (chip->bdl.area) | |
1393 | snd_dma_free_pages(&chip->bdl); | |
1394 | if (chip->rb.area) | |
1395 | snd_dma_free_pages(&chip->rb); | |
1da177e4 LT |
1396 | if (chip->posbuf.area) |
1397 | snd_dma_free_pages(&chip->posbuf); | |
1da177e4 LT |
1398 | pci_release_regions(chip->pci); |
1399 | pci_disable_device(chip->pci); | |
07e4ca50 | 1400 | kfree(chip->azx_dev); |
1da177e4 LT |
1401 | kfree(chip); |
1402 | ||
1403 | return 0; | |
1404 | } | |
1405 | ||
a98f90fd | 1406 | static int azx_dev_free(struct snd_device *device) |
1da177e4 LT |
1407 | { |
1408 | return azx_free(device->device_data); | |
1409 | } | |
1410 | ||
1411 | /* | |
1412 | * constructor | |
1413 | */ | |
a98f90fd | 1414 | static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci, |
07e4ca50 | 1415 | int posfix, int driver_type, |
a98f90fd | 1416 | struct azx **rchip) |
1da177e4 | 1417 | { |
a98f90fd | 1418 | struct azx *chip; |
1da177e4 | 1419 | int err = 0; |
a98f90fd | 1420 | static struct snd_device_ops ops = { |
1da177e4 LT |
1421 | .dev_free = azx_dev_free, |
1422 | }; | |
1423 | ||
1424 | *rchip = NULL; | |
1425 | ||
1426 | if ((err = pci_enable_device(pci)) < 0) | |
1427 | return err; | |
1428 | ||
e560d8d8 | 1429 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
1da177e4 LT |
1430 | |
1431 | if (NULL == chip) { | |
1432 | snd_printk(KERN_ERR SFX "cannot allocate chip\n"); | |
1433 | pci_disable_device(pci); | |
1434 | return -ENOMEM; | |
1435 | } | |
1436 | ||
1437 | spin_lock_init(&chip->reg_lock); | |
1438 | init_MUTEX(&chip->open_mutex); | |
1439 | chip->card = card; | |
1440 | chip->pci = pci; | |
1441 | chip->irq = -1; | |
07e4ca50 | 1442 | chip->driver_type = driver_type; |
1da177e4 | 1443 | |
c74db86b TI |
1444 | chip->position_fix = posfix; |
1445 | ||
07e4ca50 TI |
1446 | #if BITS_PER_LONG != 64 |
1447 | /* Fix up base address on ULI M5461 */ | |
1448 | if (chip->driver_type == AZX_DRIVER_ULI) { | |
1449 | u16 tmp3; | |
1450 | pci_read_config_word(pci, 0x40, &tmp3); | |
1451 | pci_write_config_word(pci, 0x40, tmp3 | 0x10); | |
1452 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); | |
1453 | } | |
1454 | #endif | |
1455 | ||
1da177e4 LT |
1456 | if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) { |
1457 | kfree(chip); | |
1458 | pci_disable_device(pci); | |
1459 | return err; | |
1460 | } | |
1461 | ||
1462 | chip->addr = pci_resource_start(pci,0); | |
1463 | chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0)); | |
1464 | if (chip->remap_addr == NULL) { | |
1465 | snd_printk(KERN_ERR SFX "ioremap error\n"); | |
1466 | err = -ENXIO; | |
1467 | goto errout; | |
1468 | } | |
1469 | ||
1470 | if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ, | |
1471 | "HDA Intel", (void*)chip)) { | |
1472 | snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq); | |
1473 | err = -EBUSY; | |
1474 | goto errout; | |
1475 | } | |
1476 | chip->irq = pci->irq; | |
1477 | ||
1478 | pci_set_master(pci); | |
1479 | synchronize_irq(chip->irq); | |
1480 | ||
07e4ca50 TI |
1481 | switch (chip->driver_type) { |
1482 | case AZX_DRIVER_ULI: | |
1483 | chip->playback_streams = ULI_NUM_PLAYBACK; | |
1484 | chip->capture_streams = ULI_NUM_CAPTURE; | |
1485 | chip->playback_index_offset = ULI_PLAYBACK_INDEX; | |
1486 | chip->capture_index_offset = ULI_CAPTURE_INDEX; | |
1487 | break; | |
1488 | default: | |
1489 | chip->playback_streams = ICH6_NUM_PLAYBACK; | |
1490 | chip->capture_streams = ICH6_NUM_CAPTURE; | |
1491 | chip->playback_index_offset = ICH6_PLAYBACK_INDEX; | |
1492 | chip->capture_index_offset = ICH6_CAPTURE_INDEX; | |
1493 | break; | |
1494 | } | |
1495 | chip->num_streams = chip->playback_streams + chip->capture_streams; | |
1496 | chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), GFP_KERNEL); | |
1497 | if (! chip->azx_dev) { | |
1498 | snd_printk(KERN_ERR "cannot malloc azx_dev\n"); | |
1499 | goto errout; | |
1500 | } | |
1501 | ||
1da177e4 LT |
1502 | /* allocate memory for the BDL for each stream */ |
1503 | if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
07e4ca50 | 1504 | BDL_SIZE, &chip->bdl)) < 0) { |
1da177e4 LT |
1505 | snd_printk(KERN_ERR SFX "cannot allocate BDL\n"); |
1506 | goto errout; | |
1507 | } | |
0be3b5d3 TI |
1508 | /* allocate memory for the position buffer */ |
1509 | if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
1510 | chip->num_streams * 8, &chip->posbuf)) < 0) { | |
1511 | snd_printk(KERN_ERR SFX "cannot allocate posbuf\n"); | |
1512 | goto errout; | |
1da177e4 | 1513 | } |
1da177e4 LT |
1514 | /* allocate CORB/RIRB */ |
1515 | if ((err = azx_alloc_cmd_io(chip)) < 0) | |
1516 | goto errout; | |
1517 | ||
1518 | /* initialize streams */ | |
1519 | azx_init_stream(chip); | |
1520 | ||
1521 | /* initialize chip */ | |
1522 | azx_init_chip(chip); | |
1523 | ||
ce43fbae TI |
1524 | chip->initialized = 1; |
1525 | ||
1da177e4 LT |
1526 | /* codec detection */ |
1527 | if (! chip->codec_mask) { | |
1528 | snd_printk(KERN_ERR SFX "no codecs found!\n"); | |
1529 | err = -ENODEV; | |
1530 | goto errout; | |
1531 | } | |
1532 | ||
1533 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) { | |
1534 | snd_printk(KERN_ERR SFX "Error creating device [card]!\n"); | |
1535 | goto errout; | |
1536 | } | |
1537 | ||
07e4ca50 TI |
1538 | strcpy(card->driver, "HDA-Intel"); |
1539 | strcpy(card->shortname, driver_short_names[chip->driver_type]); | |
1540 | sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq); | |
1541 | ||
1da177e4 LT |
1542 | *rchip = chip; |
1543 | return 0; | |
1544 | ||
1545 | errout: | |
1546 | azx_free(chip); | |
1547 | return err; | |
1548 | } | |
1549 | ||
1550 | static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) | |
1551 | { | |
a98f90fd TI |
1552 | struct snd_card *card; |
1553 | struct azx *chip; | |
1da177e4 LT |
1554 | int err = 0; |
1555 | ||
b7fe4622 | 1556 | card = snd_card_new(index, id, THIS_MODULE, 0); |
1da177e4 LT |
1557 | if (NULL == card) { |
1558 | snd_printk(KERN_ERR SFX "Error creating card!\n"); | |
1559 | return -ENOMEM; | |
1560 | } | |
1561 | ||
b7fe4622 | 1562 | if ((err = azx_create(card, pci, position_fix, pci_id->driver_data, |
07e4ca50 | 1563 | &chip)) < 0) { |
1da177e4 LT |
1564 | snd_card_free(card); |
1565 | return err; | |
1566 | } | |
421a1252 | 1567 | card->private_data = chip; |
1da177e4 | 1568 | |
1da177e4 | 1569 | /* create codec instances */ |
b7fe4622 | 1570 | if ((err = azx_codec_create(chip, model)) < 0) { |
1da177e4 LT |
1571 | snd_card_free(card); |
1572 | return err; | |
1573 | } | |
1574 | ||
1575 | /* create PCM streams */ | |
1576 | if ((err = azx_pcm_create(chip)) < 0) { | |
1577 | snd_card_free(card); | |
1578 | return err; | |
1579 | } | |
1580 | ||
1581 | /* create mixer controls */ | |
1582 | if ((err = azx_mixer_create(chip)) < 0) { | |
1583 | snd_card_free(card); | |
1584 | return err; | |
1585 | } | |
1586 | ||
1da177e4 LT |
1587 | snd_card_set_dev(card, &pci->dev); |
1588 | ||
1589 | if ((err = snd_card_register(card)) < 0) { | |
1590 | snd_card_free(card); | |
1591 | return err; | |
1592 | } | |
1593 | ||
1594 | pci_set_drvdata(pci, card); | |
1da177e4 LT |
1595 | |
1596 | return err; | |
1597 | } | |
1598 | ||
1599 | static void __devexit azx_remove(struct pci_dev *pci) | |
1600 | { | |
1601 | snd_card_free(pci_get_drvdata(pci)); | |
1602 | pci_set_drvdata(pci, NULL); | |
1603 | } | |
1604 | ||
1605 | /* PCI IDs */ | |
1606 | static struct pci_device_id azx_ids[] = { | |
07e4ca50 TI |
1607 | { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */ |
1608 | { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */ | |
1609 | { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */ | |
1610 | { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */ | |
1611 | { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */ | |
1612 | { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */ | |
1613 | { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */ | |
da3fca21 V |
1614 | { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA 026c */ |
1615 | { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA 0371 */ | |
1da177e4 LT |
1616 | { 0, } |
1617 | }; | |
1618 | MODULE_DEVICE_TABLE(pci, azx_ids); | |
1619 | ||
1620 | /* pci_driver definition */ | |
1621 | static struct pci_driver driver = { | |
1622 | .name = "HDA Intel", | |
1623 | .id_table = azx_ids, | |
1624 | .probe = azx_probe, | |
1625 | .remove = __devexit_p(azx_remove), | |
421a1252 TI |
1626 | #ifdef CONFIG_PM |
1627 | .suspend = azx_suspend, | |
1628 | .resume = azx_resume, | |
1629 | #endif | |
1da177e4 LT |
1630 | }; |
1631 | ||
1632 | static int __init alsa_card_azx_init(void) | |
1633 | { | |
01d25d46 | 1634 | return pci_register_driver(&driver); |
1da177e4 LT |
1635 | } |
1636 | ||
1637 | static void __exit alsa_card_azx_exit(void) | |
1638 | { | |
1639 | pci_unregister_driver(&driver); | |
1640 | } | |
1641 | ||
1642 | module_init(alsa_card_azx_init) | |
1643 | module_exit(alsa_card_azx_exit) |