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[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
50279d9b 57#include <asm/cpufeature.h>
27fe48d9 58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
98d8fc6c
ML		 61#include <sound/hdaudio.h>
62#include <sound/hda_i915.h>
9121947d 63#include <linux/vgaarb.h>
a82d51ed 64#include <linux/vga_switcheroo.h>
4918cdab 65#include <linux/firmware.h>
1da177e4 66#include "hda_codec.h"
05e84878 67#include "hda_controller.h"
347de1f8 68#include "hda_intel.h"
1da177e4 69
785d8c4b
LY		 70#define CREATE_TRACE_POINTS
71#include "hda_intel_trace.h"
72
b6050ef6
TI		 73/* position fix mode */
74enum {
75 POS_FIX_AUTO,
76 POS_FIX_LPIB,
77 POS_FIX_POSBUF,
78 POS_FIX_VIACOMBO,
79 POS_FIX_COMBO,
f87e7f25 80 POS_FIX_SKL,
b6050ef6
TI		 81};
82
9a34af4a
TI		 83/* Defines for ATI HD Audio support in SB450 south bridge */
84#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
85#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
86
87/* Defines for Nvidia HDA support */
88#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
89#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
90#define NVIDIA_HDA_ISTRM_COH 0x4d
91#define NVIDIA_HDA_OSTRM_COH 0x4c
92#define NVIDIA_HDA_ENABLE_COHBIT 0x01
93
94/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 95#define INTEL_HDA_CGCTL 0x48
96#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 97#define INTEL_SCH_HDA_DEVC 0x78
98#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
99
100/* Define IN stream 0 FIFO size offset in VIA controller */
101#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
102/* Define VIA HD Audio Device ID*/
103#define VIA_HDAC_DEVICE_ID 0x3288
104
33124929
TI		 105/* max number of SDs */
106/* ICH, ATI and VIA have 4 playback and 4 capture */
107#define ICH6_NUM_CAPTURE 4
108#define ICH6_NUM_PLAYBACK 4
109
110/* ULI has 6 playback and 5 capture */
111#define ULI_NUM_CAPTURE 5
112#define ULI_NUM_PLAYBACK 6
113
114/* ATI HDMI may have up to 8 playbacks and 0 capture */
115#define ATIHDMI_NUM_CAPTURE 0
116#define ATIHDMI_NUM_PLAYBACK 8
117
118/* TERA has 4 playback and 3 capture */
119#define TERA_NUM_CAPTURE 3
120#define TERA_NUM_PLAYBACK 4
121
1da177e4 122
5aba4f8e
TI		 123static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
124static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 125static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 126static char *model[SNDRV_CARDS];
1dac6695 127static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 128static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 129static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 130static int probe_only[SNDRV_CARDS];
26a6cb6c 131static int jackpoll_ms[SNDRV_CARDS];
41438f13 132static int single_cmd = -1;
71623855 133static int enable_msi = -1;
4ea6fbc8
TI		 134#ifdef CONFIG_SND_HDA_PATCH_LOADER
135static char *patch[SNDRV_CARDS];
136#endif
2dca0bba 137#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 138static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 139 CONFIG_SND_HDA_INPUT_BEEP_MODE};
140#endif
1da177e4 141
5aba4f8e 142module_param_array(index, int, NULL, 0444);
1da177e4 143MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 144module_param_array(id, charp, NULL, 0444);
1da177e4 145MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 146module_param_array(enable, bool, NULL, 0444);
147MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
148module_param_array(model, charp, NULL, 0444);
1da177e4 149MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 150module_param_array(position_fix, int, NULL, 0444);
4cb36310 151MODULE_PARM_DESC(position_fix, "DMA pointer read method."
f87e7f25 152 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
555e219f
TI		 153module_param_array(bdl_pos_adj, int, NULL, 0644);
154MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 155module_param_array(probe_mask, int, NULL, 0444);
606ad75f 156MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 157module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 158MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 159module_param_array(jackpoll_ms, int, NULL, 0444);
160MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 161module_param(single_cmd, bint, 0444);
d01ce99f
TI		 162MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
163 "(for debugging only).");
ac9ef6cf 164module_param(enable_msi, bint, 0444);
134a11f0 165MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 166#ifdef CONFIG_SND_HDA_PATCH_LOADER
167module_param_array(patch, charp, NULL, 0444);
168MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
169#endif
2dca0bba 170#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 171module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 172MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 173 "(0=off, 1=on) (default=1).");
2dca0bba 174#endif
606ad75f 175
83012a7c 176#ifdef CONFIG_PM
65fcd41d 177static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 178static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 179 .set = param_set_xint,
180 .get = param_get_int,
181};
182#define param_check_xint param_check_int
183
fee2fba3 184static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 185module_param(power_save, xint, 0644);
fee2fba3
TI		 186MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
187 "(in second, 0 = disable).");
1da177e4 188
dee1b66c
TI		 189/* reset the HD-audio controller in power save mode.
190 * this may give more power-saving, but will take longer time to
191 * wake up.
192 */
8fc24426
TI		 193static bool power_save_controller = 1;
194module_param(power_save_controller, bool, 0644);
dee1b66c 195MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 196#else
bb573928 197#define power_save 0
83012a7c 198#endif /* CONFIG_PM */
dee1b66c 199
7bfe059e
TI		 200static int align_buffer_size = -1;
201module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 202MODULE_PARM_DESC(align_buffer_size,
203 "Force buffer and period sizes to be multiple of 128 bytes.");
204
27fe48d9 205#ifdef CONFIG_X86
7c732015
TI		 206static int hda_snoop = -1;
207module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 208MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 209#else
210#define hda_snoop true
27fe48d9
TI		 211#endif
212
213
1da177e4
LT		 214MODULE_LICENSE("GPL");
215MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
216 "{Intel, ICH6M},"
2f1b3818 217 "{Intel, ICH7},"
f5d40b30 218 "{Intel, ESB2},"
d2981393 219 "{Intel, ICH8},"
f9cc8a8b 220 "{Intel, ICH9},"
c34f5a04 221 "{Intel, ICH10},"
b29c2360 222 "{Intel, PCH},"
d2f2fcd2 223 "{Intel, CPT},"
d2edeb7c 224 "{Intel, PPT},"
8bc039a1 225 "{Intel, LPT},"
144dad99 226 "{Intel, LPT_LP},"
4eeca499 227 "{Intel, WPT_LP},"
c8b00fd2 228 "{Intel, SPT},"
b4565913 229 "{Intel, SPT_LP},"
e926f2c8 230 "{Intel, HPT},"
cea310e8 231 "{Intel, PBG},"
4979bca9 232 "{Intel, SCH},"
fc20a562 233 "{ATI, SB450},"
89be83f8 234 "{ATI, SB600},"
778b6e1b 235 "{ATI, RS600},"
5b15c95f 236 "{ATI, RS690},"
e6db1119
WL		 237 "{ATI, RS780},"
238 "{ATI, R600},"
2797f724
HRK		 239 "{ATI, RV630},"
240 "{ATI, RV610},"
27da1834
WL		 241 "{ATI, RV670},"
242 "{ATI, RV635},"
243 "{ATI, RV620},"
244 "{ATI, RV770},"
fc20a562 245 "{VIA, VT8251},"
47672310 246 "{VIA, VT8237A},"
07e4ca50
TI		 247 "{SiS, SIS966},"
248 "{ULI, M5461}}");
1da177e4
LT		 249MODULE_DESCRIPTION("Intel HDA driver");
250
a82d51ed 251#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 252#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 253#define SUPPORT_VGA_SWITCHEROO
254#endif
255#endif
256
257
1da177e4 258/*
1da177e4 259 */
1da177e4 260
07e4ca50
TI		 261/* driver types */
262enum {
263 AZX_DRIVER_ICH,
32679f95 264 AZX_DRIVER_PCH,
4979bca9 265 AZX_DRIVER_SCH,
fab1285a 266 AZX_DRIVER_HDMI,
07e4ca50 267 AZX_DRIVER_ATI,
778b6e1b 268 AZX_DRIVER_ATIHDMI,
1815b34a 269 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 270 AZX_DRIVER_VIA,
271 AZX_DRIVER_SIS,
272 AZX_DRIVER_ULI,
da3fca21 273 AZX_DRIVER_NVIDIA,
f269002e 274 AZX_DRIVER_TERA,
14d34f16 275 AZX_DRIVER_CTX,
5ae763b1 276 AZX_DRIVER_CTHDA,
c563f473 277 AZX_DRIVER_CMEDIA,
c4da29ca 278 AZX_DRIVER_GENERIC,
2f5983f2 279 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 280};
281
37e661ee
TI		 282#define azx_get_snoop_type(chip) \
283 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
284#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
285
b42b4afb
TI		 286/* quirks for old Intel chipsets */
287#define AZX_DCAPS_INTEL_ICH \
103884a3 288 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 289
2ea3c6a2 290/* quirks for Intel PCH */
6603249d 291#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 292 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
bcb337d1 293 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 294
55913110 295/* PCH up to IVB; no runtime PM */
6603249d 296#define AZX_DCAPS_INTEL_PCH_NOPM \
55913110 297 (AZX_DCAPS_INTEL_PCH_BASE)
6603249d 298
55913110 299/* PCH for HSW/BDW; with runtime PM */
d7dab4db 300#define AZX_DCAPS_INTEL_PCH \
6603249d 301 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 302
6603249d 303/* HSW HDMI */
33499a15 304#define AZX_DCAPS_INTEL_HASWELL \
103884a3 305 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 306 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
307 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 308
54a0405d
LY		 309/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
310#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
313 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 314
40cc2392
ML		 315#define AZX_DCAPS_INTEL_BAYTRAIL \
316 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
317
2d846c74
LY		 318#define AZX_DCAPS_INTEL_BRASWELL \
319 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
320
d6795827 321#define AZX_DCAPS_INTEL_SKYLAKE \
2d846c74
LY		 322 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
323 AZX_DCAPS_I915_POWERWELL)
d6795827 324
c87693da
LH		 325#define AZX_DCAPS_INTEL_BROXTON \
326 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
327 AZX_DCAPS_I915_POWERWELL)
328
9477c58e
TI		 329/* quirks for ATI SB / AMD Hudson */
330#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 331 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
332 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 333
334/* quirks for ATI/AMD HDMI */
335#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 336 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
337 AZX_DCAPS_NO_MSI64)
9477c58e 338
37e661ee
TI		 339/* quirks for ATI HDMI with snoop off */
340#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
341 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
342
9477c58e
TI		 343/* quirks for Nvidia */
344#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 345 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 346 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 347
5ae763b1 348#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 349 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 350 AZX_DCAPS_NO_64BIT |\
37e661ee 351 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 352
a82d51ed 353/*
2b760d88 354 * vga_switcheroo support
a82d51ed
TI		 355 */
356#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 357#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
358#else
359#define use_vga_switcheroo(chip) 0
360#endif
361
03b135ce
LY		 362#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
363 ((pci)->device == 0x0c0c) || \
364 ((pci)->device == 0x0d0c) || \
365 ((pci)->device == 0x160c))
366
7e31a015
TI		 367#define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
368#define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
35639a0e
VK		 369#define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
370#define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
6858107e 371#define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
7e31a015 372#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
12ee4022 373#define IS_GLK(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x3198)
35639a0e 374#define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \
12ee4022
SP		 375 IS_KBL(pci) || IS_KBL_LP(pci) || IS_KBL_H(pci) || \
376 IS_GLK(pci)
7c23b7c1 377
48c8b0eb 378static char *driver_short_names[] = {
07e4ca50 379 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 380 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 381 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 382 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 383 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 384 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 385 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 386 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
387 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 388 [AZX_DRIVER_ULI] = "HDA ULI M5461",
389 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 390 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 391 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 392 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 393 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 394 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 395};
396
27fe48d9 397#ifdef CONFIG_X86
9ddf1aeb 398static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 399{
9ddf1aeb
TI		 400 int pages;
401
27fe48d9
TI		 402 if (azx_snoop(chip))
403 return;
9ddf1aeb
TI		 404 if (!dmab || !dmab->area || !dmab->bytes)
405 return;
406
407#ifdef CONFIG_SND_DMA_SGBUF
408 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
409 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 410 if (chip->driver_type == AZX_DRIVER_CMEDIA)
411 return; /* deal with only CORB/RIRB buffers */
27fe48d9 412 if (on)
9ddf1aeb 413 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 414 else
9ddf1aeb
TI		 415 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
416 return;
27fe48d9 417 }
9ddf1aeb
TI		 418#endif
419
420 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
421 if (on)
422 set_memory_wc((unsigned long)dmab->area, pages);
423 else
424 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 425}
426
427static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
428 bool on)
429{
9ddf1aeb 430 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 431}
432static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 433 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 434{
435 if (azx_dev->wc_marked != on) {
9ddf1aeb 436 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 437 azx_dev->wc_marked = on;
438 }
439}
440#else
441/* NOP for other archs */
442static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
443 bool on)
444{
445}
446static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 447 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 448{
449}
450#endif
451
68e7fffc 452static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 453
cb53c626
TI		 454/*
455 * initialize the PCI registers
456 */
457/* update bits in a PCI register byte */
458static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
459 unsigned char mask, unsigned char val)
460{
461 unsigned char data;
462
463 pci_read_config_byte(pci, reg, &data);
464 data &= ~mask;
465 data |= (val & mask);
466 pci_write_config_byte(pci, reg, data);
467}
468
469static void azx_init_pci(struct azx *chip)
470{
37e661ee
TI		 471 int snoop_type = azx_get_snoop_type(chip);
472
cb53c626
TI		 473 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
474 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
475 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 476 * codecs.
477 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 478 */
46f2cc80 479 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 480 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 481 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 482 }
cb53c626 483
9477c58e
TI		 484 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
485 * we need to enable snoop.
486 */
37e661ee 487 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 488 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
489 azx_snoop(chip));
cb53c626 490 update_pci_byte(chip->pci,
27fe48d9
TI		 491 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
492 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 493 }
494
495 /* For NVIDIA HDA, enable snoop */
37e661ee 496 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 497 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
498 azx_snoop(chip));
cb53c626
TI		 499 update_pci_byte(chip->pci,
500 NVIDIA_HDA_TRANSREG_ADDR,
501 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 502 update_pci_byte(chip->pci,
503 NVIDIA_HDA_ISTRM_COH,
504 0x01, NVIDIA_HDA_ENABLE_COHBIT);
505 update_pci_byte(chip->pci,
506 NVIDIA_HDA_OSTRM_COH,
507 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 508 }
509
510 /* Enable SCH/PCH snoop if needed */
37e661ee 511 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 512 unsigned short snoop;
90a5ad52 513 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 514 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
515 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
516 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
517 if (!azx_snoop(chip))
518 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
519 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 520 pci_read_config_word(chip->pci,
521 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 522 }
4e76a883
TI		 523 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
524 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
525 "Disabled" : "Enabled");
da3fca21 526 }
1da177e4
LT		 527}
528
7c23b7c1
LH		 529/*
530 * In BXT-P A0, HD-Audio DMA requests is later than expected,
531 * and makes an audio stream sensitive to system latencies when
532 * 24/32 bits are playing.
533 * Adjusting threshold of DMA fifo to force the DMA request
534 * sooner to improve latency tolerance at the expense of power.
535 */
536static void bxt_reduce_dma_latency(struct azx *chip)
537{
538 u32 val;
539
70eafad8 540 val = azx_readl(chip, VS_EM4L);
7c23b7c1 541 val &= (0x3 << 20);
70eafad8 542 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 543}
544
1f9d3d98
LY		 545/*
546 * ML_LCAP bits:
547 * bit 0: 6 MHz Supported
548 * bit 1: 12 MHz Supported
549 * bit 2: 24 MHz Supported
550 * bit 3: 48 MHz Supported
551 * bit 4: 96 MHz Supported
552 * bit 5: 192 MHz Supported
553 */
554static int intel_get_lctl_scf(struct azx *chip)
555{
556 struct hdac_bus *bus = azx_bus(chip);
557 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
558 u32 val, t;
559 int i;
560
561 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
562
563 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
564 t = preferred_bits[i];
565 if (val & (1 << t))
566 return t;
567 }
568
569 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
570 return 0;
571}
572
573static int intel_ml_lctl_set_power(struct azx *chip, int state)
574{
575 struct hdac_bus *bus = azx_bus(chip);
576 u32 val;
577 int timeout;
578
579 /*
580 * the codecs are sharing the first link setting by default
581 * If other links are enabled for stream, they need similar fix
582 */
583 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
584 val &= ~AZX_MLCTL_SPA;
585 val |= state << AZX_MLCTL_SPA_SHIFT;
586 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
587 /* wait for CPA */
588 timeout = 50;
589 while (timeout) {
590 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
591 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
592 return 0;
593 timeout--;
594 udelay(10);
595 }
596
597 return -1;
598}
599
600static void intel_init_lctl(struct azx *chip)
601{
602 struct hdac_bus *bus = azx_bus(chip);
603 u32 val;
604 int ret;
605
606 /* 0. check lctl register value is correct or not */
607 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
608 /* if SCF is already set, let's use it */
609 if ((val & ML_LCTL_SCF_MASK) != 0)
610 return;
611
612 /*
613 * Before operating on SPA, CPA must match SPA.
614 * Any deviation may result in undefined behavior.
615 */
616 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
617 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
618 return;
619
620 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
621 ret = intel_ml_lctl_set_power(chip, 0);
622 udelay(100);
623 if (ret)
624 goto set_spa;
625
626 /* 2. update SCF to select a properly audio clock*/
627 val &= ~ML_LCTL_SCF_MASK;
628 val |= intel_get_lctl_scf(chip);
629 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
630
631set_spa:
632 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
633 intel_ml_lctl_set_power(chip, 1);
634 udelay(100);
635}
636
0a673521
LH		 637static void hda_intel_init_chip(struct azx *chip, bool full_reset)
638{
98d8fc6c 639 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 640 struct pci_dev *pci = chip->pci;
6639484d 641 u32 val;
0a673521
LH		 642
643 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 644 snd_hdac_set_codec_wakeup(bus, true);
7e31a015 645 if (IS_SKL_PLUS(pci)) {
6639484d
LY		 646 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
647 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
648 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
649 }
0a673521 650 azx_init_chip(chip, full_reset);
7e31a015 651 if (IS_SKL_PLUS(pci)) {
6639484d
LY		 652 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
653 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
654 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
655 }
0a673521 656 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 657 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 658
659 /* reduce dma latency to avoid noise */
7e31a015 660 if (IS_BXT(pci))
7c23b7c1 661 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 662
663 if (bus->mlcap != NULL)
664 intel_init_lctl(chip);
0a673521
LH		 665}
666
b6050ef6
TI		 667/* calculate runtime delay from LPIB */
668static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
669 unsigned int pos)
670{
7833c3f8 671 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 672 int stream = substream->stream;
673 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
674 int delay;
675
676 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
677 delay = pos - lpib_pos;
678 else
679 delay = lpib_pos - pos;
680 if (delay < 0) {
7833c3f8 681 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 682 delay = 0;
683 else
7833c3f8 684 delay += azx_dev->core.bufsize;
b6050ef6
TI		 685 }
686
7833c3f8 687 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 688 dev_info(chip->card->dev,
689 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 690 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 691 delay = 0;
692 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
693 chip->get_delay[stream] = NULL;
694 }
695
696 return bytes_to_frames(substream->runtime, delay);
697}
698
9ad593f6
TI		 699static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
700
7ca954a8
DR		 701/* called from IRQ */
702static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
703{
9a34af4a 704 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 705 int ok;
706
707 ok = azx_position_ok(chip, azx_dev);
708 if (ok == 1) {
709 azx_dev->irq_pending = 0;
710 return ok;
2f35c630 711 } else if (ok == 0) {
7ca954a8
DR		 712 /* bogus IRQ, process it later */
713 azx_dev->irq_pending = 1;
2f35c630 714 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 715 }
716 return 0;
717}
718
17eccb27
ML		 719/* Enable/disable i915 display power for the link */
720static int azx_intel_link_power(struct azx *chip, bool enable)
721{
98d8fc6c 722 struct hdac_bus *bus = azx_bus(chip);
17eccb27 723
98d8fc6c 724 return snd_hdac_display_power(bus, enable);
17eccb27
ML		 725}
726
9ad593f6
TI		 727/*
728 * Check whether the current DMA position is acceptable for updating
729 * periods. Returns non-zero if it's OK.
730 *
731 * Many HD-audio controllers appear pretty inaccurate about
732 * the update-IRQ timing. The IRQ is issued before actually the
733 * data is processed. So, we need to process it afterwords in a
734 * workqueue.
735 */
736static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
737{
7833c3f8 738 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 739 int stream = substream->stream;
e5463720 740 u32 wallclk;
9ad593f6
TI		 741 unsigned int pos;
742
7833c3f8
TI		 743 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
744 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 745 return -1; /* bogus (too early) interrupt */
fa00e046 746
b6050ef6
TI		 747 if (chip->get_position[stream])
748 pos = chip->get_position[stream](chip, azx_dev);
749 else { /* use the position buffer as default */
750 pos = azx_get_pos_posbuf(chip, azx_dev);
751 if (!pos || pos == (u32)-1) {
752 dev_info(chip->card->dev,
753 "Invalid position buffer, using LPIB read method instead.\n");
754 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 755 if (chip->get_position[0] == azx_get_pos_lpib &&
756 chip->get_position[1] == azx_get_pos_lpib)
757 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 758 pos = azx_get_pos_lpib(chip, azx_dev);
759 chip->get_delay[stream] = NULL;
760 } else {
761 chip->get_position[stream] = azx_get_pos_posbuf;
762 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
763 chip->get_delay[stream] = azx_get_delay_from_lpib;
764 }
765 }
766
7833c3f8 767 if (pos >= azx_dev->core.bufsize)
b6050ef6 768 pos = 0;
9ad593f6 769
7833c3f8 770 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 771 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 772 return -1; /* this shouldn't happen! */
7833c3f8
TI		 773 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
774 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 775 /* NG - it's below the first next period boundary */
4f0189be 776 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 777 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 778 return 1; /* OK, it's fine */
779}
780
781/*
782 * The work for pending PCM period updates.
783 */
784static void azx_irq_pending_work(struct work_struct *work)
785{
9a34af4a
TI		 786 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
787 struct azx *chip = &hda->chip;
7833c3f8
TI		 788 struct hdac_bus *bus = azx_bus(chip);
789 struct hdac_stream *s;
790 int pending, ok;
9ad593f6 791
9a34af4a 792 if (!hda->irq_pending_warned) {
4e76a883
TI		 793 dev_info(chip->card->dev,
794 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
795 chip->card->number);
9a34af4a 796 hda->irq_pending_warned = 1;
a6a950a8
TI		 797 }
798
9ad593f6
TI		 799 for (;;) {
800 pending = 0;
a41d1224 801 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 802 list_for_each_entry(s, &bus->stream_list, list) {
803 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 804 if (!azx_dev->irq_pending ||
7833c3f8
TI		 805 !s->substream ||
806 !s->running)
9ad593f6 807 continue;
e5463720
JK		 808 ok = azx_position_ok(chip, azx_dev);
809 if (ok > 0) {
9ad593f6 810 azx_dev->irq_pending = 0;
a41d1224 811 spin_unlock(&bus->reg_lock);
7833c3f8 812 snd_pcm_period_elapsed(s->substream);
a41d1224 813 spin_lock(&bus->reg_lock);
e5463720
JK		 814 } else if (ok < 0) {
815 pending = 0; /* too early */
9ad593f6
TI		 816 } else
817 pending++;
818 }
a41d1224 819 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 820 if (!pending)
821 return;
08af495f 822 msleep(1);
9ad593f6
TI		 823 }
824}
825
826/* clear irq_pending flags and assure no on-going workq */
827static void azx_clear_irq_pending(struct azx *chip)
828{
7833c3f8
TI		 829 struct hdac_bus *bus = azx_bus(chip);
830 struct hdac_stream *s;
9ad593f6 831
a41d1224 832 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 833 list_for_each_entry(s, &bus->stream_list, list) {
834 struct azx_dev *azx_dev = stream_to_azx_dev(s);
835 azx_dev->irq_pending = 0;
836 }
a41d1224 837 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 838}
839
68e7fffc
TI		 840static int azx_acquire_irq(struct azx *chip, int do_disconnect)
841{
a41d1224
TI		 842 struct hdac_bus *bus = azx_bus(chip);
843
437a5a46
TI		 844 if (request_irq(chip->pci->irq, azx_interrupt,
845 chip->msi ? 0 : IRQF_SHARED,
de65360b 846 chip->card->irq_descr, chip)) {
4e76a883
TI		 847 dev_err(chip->card->dev,
848 "unable to grab IRQ %d, disabling device\n",
849 chip->pci->irq);
68e7fffc
TI		 850 if (do_disconnect)
851 snd_card_disconnect(chip->card);
852 return -1;
853 }
a41d1224 854 bus->irq = chip->pci->irq;
69e13418 855 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 856 return 0;
857}
858
b6050ef6
TI		 859/* get the current DMA position with correction on VIA chips */
860static unsigned int azx_via_get_position(struct azx *chip,
861 struct azx_dev *azx_dev)
862{
863 unsigned int link_pos, mini_pos, bound_pos;
864 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
865 unsigned int fifo_size;
866
1604eeee 867 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 868 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 869 /* Playback, no problem using link position */
870 return link_pos;
871 }
872
873 /* Capture */
874 /* For new chipset,
875 * use mod to get the DMA position just like old chipset
876 */
7833c3f8
TI		 877 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
878 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 879
880 /* azx_dev->fifo_size can't get FIFO size of in stream.
881 * Get from base address + offset.
882 */
a41d1224
TI		 883 fifo_size = readw(azx_bus(chip)->remap_addr +
884 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 885
886 if (azx_dev->insufficient) {
887 /* Link position never gather than FIFO size */
888 if (link_pos <= fifo_size)
889 return 0;
890
891 azx_dev->insufficient = 0;
892 }
893
894 if (link_pos <= fifo_size)
7833c3f8 895 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 896 else
897 mini_pos = link_pos - fifo_size;
898
899 /* Find nearest previous boudary */
7833c3f8
TI		 900 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
901 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 902 if (mod_link_pos >= fifo_size)
903 bound_pos = link_pos - mod_link_pos;
904 else if (mod_dma_pos >= mod_mini_pos)
905 bound_pos = mini_pos - mod_mini_pos;
906 else {
7833c3f8
TI		 907 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
908 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 909 bound_pos = 0;
910 }
911
912 /* Calculate real DMA position we want */
913 return bound_pos + mod_dma_pos;
914}
915
f87e7f25
TI		 916static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
917 struct azx_dev *azx_dev)
918{
919 return _snd_hdac_chip_readl(azx_bus(chip),
920 AZX_REG_VS_SDXDPIB_XBASE +
921 (AZX_REG_VS_SDXDPIB_XINTERVAL *
922 azx_dev->core.index));
923}
924
925/* get the current DMA position with correction on SKL+ chips */
926static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
927{
928 /* DPIB register gives a more accurate position for playback */
929 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
930 return azx_skl_get_dpib_pos(chip, azx_dev);
931
932 /* For capture, we need to read posbuf, but it requires a delay
933 * for the possible boundary overlap; the read of DPIB fetches the
934 * actual posbuf
935 */
936 udelay(20);
937 azx_skl_get_dpib_pos(chip, azx_dev);
938 return azx_get_pos_posbuf(chip, azx_dev);
939}
940
83012a7c 941#ifdef CONFIG_PM
65fcd41d
TI		 942static DEFINE_MUTEX(card_list_lock);
943static LIST_HEAD(card_list);
944
945static void azx_add_card_list(struct azx *chip)
946{
9a34af4a 947 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 948 mutex_lock(&card_list_lock);
9a34af4a 949 list_add(&hda->list, &card_list);
65fcd41d
TI		 950 mutex_unlock(&card_list_lock);
951}
952
953static void azx_del_card_list(struct azx *chip)
954{
9a34af4a 955 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 956 mutex_lock(&card_list_lock);
9a34af4a 957 list_del_init(&hda->list);
65fcd41d
TI		 958 mutex_unlock(&card_list_lock);
959}
960
961/* trigger power-save check at writing parameter */
962static int param_set_xint(const char *val, const struct kernel_param *kp)
963{
9a34af4a 964 struct hda_intel *hda;
65fcd41d 965 struct azx *chip;
65fcd41d
TI		 966 int prev = power_save;
967 int ret = param_set_int(val, kp);
968
969 if (ret || prev == power_save)
970 return ret;
971
972 mutex_lock(&card_list_lock);
9a34af4a
TI		 973 list_for_each_entry(hda, &card_list, list) {
974 chip = &hda->chip;
a41d1224 975 if (!hda->probe_continued || chip->disabled)
65fcd41d 976 continue;
a41d1224 977 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 978 }
979 mutex_unlock(&card_list_lock);
980 return 0;
981}
982#else
983#define azx_add_card_list(chip) /* NOP */
984#define azx_del_card_list(chip) /* NOP */
83012a7c 985#endif /* CONFIG_PM */
5c0b9bec 986
7ccbde57 987#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 988/*
989 * power management
990 */
68cb2b55 991static int azx_suspend(struct device *dev)
1da177e4 992{
68cb2b55 993 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 994 struct azx *chip;
995 struct hda_intel *hda;
a41d1224 996 struct hdac_bus *bus;
1da177e4 997
2d9772ef
TI		 998 if (!card)
999 return 0;
1000
1001 chip = card->private_data;
1002 hda = container_of(chip, struct hda_intel, chip);
342e8449 1003 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 1004 return 0;
1005
a41d1224 1006 bus = azx_bus(chip);
421a1252 1007 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 1008 azx_clear_irq_pending(chip);
cb53c626 1009 azx_stop_chip(chip);
7295b264 1010 azx_enter_link_reset(chip);
a41d1224
TI		 1011 if (bus->irq >= 0) {
1012 free_irq(bus->irq, chip);
1013 bus->irq = -1;
30b35399 1014 }
a07187c9 1015
68e7fffc 1016 if (chip->msi)
43001c95 1017 pci_disable_msi(chip->pci);
795614dd
ML		 1018 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1019 && hda->need_i915_power)
98d8fc6c 1020 snd_hdac_display_power(bus, false);
785d8c4b
LY		 1021
1022 trace_azx_suspend(chip);
1da177e4
LT		 1023 return 0;
1024}
1025
68cb2b55 1026static int azx_resume(struct device *dev)
1da177e4 1027{
68cb2b55
TI		 1028 struct pci_dev *pci = to_pci_dev(dev);
1029 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1030 struct azx *chip;
1031 struct hda_intel *hda;
a52ff34e 1032 struct hdac_bus *bus;
2d9772ef
TI		 1033
1034 if (!card)
1035 return 0;
1da177e4 1036
2d9772ef
TI		 1037 chip = card->private_data;
1038 hda = container_of(chip, struct hda_intel, chip);
a52ff34e 1039 bus = azx_bus(chip);
342e8449 1040 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 1041 return 0;
1042
a52ff34e
TI		 1043 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1044 snd_hdac_display_power(bus, true);
1045 if (hda->need_i915_power)
1046 snd_hdac_i915_set_bclk(bus);
a07187c9 1047 }
a52ff34e 1048
68e7fffc
TI		 1049 if (chip->msi)
1050 if (pci_enable_msi(pci) < 0)
1051 chip->msi = 0;
1052 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1053 return -EIO;
cb53c626 1054 azx_init_pci(chip);
d804ad92 1055
0a673521 1056 hda_intel_init_chip(chip, true);
d804ad92 1057
a52ff34e
TI		 1058 /* power down again for link-controlled chips */
1059 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1060 !hda->need_i915_power)
1061 snd_hdac_display_power(bus, false);
1062
421a1252 1063 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 1064
1065 trace_azx_resume(chip);
1da177e4
LT		 1066 return 0;
1067}
b8dfc462
ML		 1068#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1069
3e6db33a
XZ		 1070#ifdef CONFIG_PM_SLEEP
1071/* put codec down to D3 at hibernation for Intel SKL+;
1072 * otherwise BIOS may still access the codec and screw up the driver
1073 */
3e6db33a
XZ		 1074static int azx_freeze_noirq(struct device *dev)
1075{
1076 struct pci_dev *pci = to_pci_dev(dev);
1077
1078 if (IS_SKL_PLUS(pci))
1079 pci_set_power_state(pci, PCI_D3hot);
1080
1081 return 0;
1082}
1083
1084static int azx_thaw_noirq(struct device *dev)
1085{
1086 struct pci_dev *pci = to_pci_dev(dev);
1087
1088 if (IS_SKL_PLUS(pci))
1089 pci_set_power_state(pci, PCI_D0);
1090
1091 return 0;
1092}
1093#endif /* CONFIG_PM_SLEEP */
1094
641d334b 1095#ifdef CONFIG_PM
b8dfc462
ML		 1096static int azx_runtime_suspend(struct device *dev)
1097{
1098 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1099 struct azx *chip;
1100 struct hda_intel *hda;
b8dfc462 1101
2d9772ef
TI		 1102 if (!card)
1103 return 0;
1104
1105 chip = card->private_data;
1106 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1107 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1108 return 0;
1109
364aa716 1110 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1111 return 0;
1112
7d4f606c
WX		 1113 /* enable controller wake up event */
1114 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1115 STATESTS_INT_MASK);
1116
b8dfc462 1117 azx_stop_chip(chip);
873ce8ad 1118 azx_enter_link_reset(chip);
b8dfc462 1119 azx_clear_irq_pending(chip);
795614dd
ML		 1120 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1121 && hda->need_i915_power)
98d8fc6c 1122 snd_hdac_display_power(azx_bus(chip), false);
e4d9e513 1123
785d8c4b 1124 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1125 return 0;
1126}
1127
1128static int azx_runtime_resume(struct device *dev)
1129{
1130 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1131 struct azx *chip;
1132 struct hda_intel *hda;
98d8fc6c 1133 struct hdac_bus *bus;
7d4f606c
WX		 1134 struct hda_codec *codec;
1135 int status;
b8dfc462 1136
2d9772ef
TI		 1137 if (!card)
1138 return 0;
1139
1140 chip = card->private_data;
1141 hda = container_of(chip, struct hda_intel, chip);
a52ff34e 1142 bus = azx_bus(chip);
1618e84a 1143 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1144 return 0;
1145
364aa716 1146 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1147 return 0;
1148
033ea349 1149 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
a52ff34e
TI		 1150 snd_hdac_display_power(bus, true);
1151 if (hda->need_i915_power)
bb03ed21 1152 snd_hdac_i915_set_bclk(bus);
a07187c9 1153 }
7d4f606c
WX		 1154
1155 /* Read STATESTS before controller reset */
1156 status = azx_readw(chip, STATESTS);
1157
b8dfc462 1158 azx_init_pci(chip);
0a673521 1159 hda_intel_init_chip(chip, true);
7d4f606c 1160
a41d1224
TI		 1161 if (status) {
1162 list_for_each_codec(codec, &chip->bus)
7d4f606c 1163 if (status & (1 << codec->addr))
2f35c630
TI		 1164 schedule_delayed_work(&codec->jackpoll_work,
1165 codec->jackpoll_interval);
7d4f606c
WX		 1166 }
1167
1168 /* disable controller Wake Up event*/
1169 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1170 ~STATESTS_INT_MASK);
1171
a52ff34e
TI		 1172 /* power down again for link-controlled chips */
1173 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1174 !hda->need_i915_power)
1175 snd_hdac_display_power(bus, false);
1176
785d8c4b 1177 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1178 return 0;
1179}
6eb827d2
TI		 1180
1181static int azx_runtime_idle(struct device *dev)
1182{
1183 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1184 struct azx *chip;
1185 struct hda_intel *hda;
1186
1187 if (!card)
1188 return 0;
6eb827d2 1189
2d9772ef
TI		 1190 chip = card->private_data;
1191 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1192 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1193 return 0;
1194
55ed9cd1 1195 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1196 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1197 return -EBUSY;
1198
1199 return 0;
1200}
1201
b8dfc462
ML		 1202static const struct dev_pm_ops azx_pm = {
1203 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1204#ifdef CONFIG_PM_SLEEP
1205 .freeze_noirq = azx_freeze_noirq,
1206 .thaw_noirq = azx_thaw_noirq,
1207#endif
6eb827d2 1208 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1209};
1210
68cb2b55
TI		 1211#define AZX_PM_OPS &azx_pm
1212#else
68cb2b55 1213#define AZX_PM_OPS NULL
b8dfc462 1214#endif /* CONFIG_PM */
1da177e4
LT		 1215
1216
48c8b0eb 1217static int azx_probe_continue(struct azx *chip);
a82d51ed 1218
8393ec4a 1219#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1220static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1221
a82d51ed
TI		 1222static void azx_vs_set_state(struct pci_dev *pci,
1223 enum vga_switcheroo_state state)
1224{
1225 struct snd_card *card = pci_get_drvdata(pci);
1226 struct azx *chip = card->private_data;
9a34af4a 1227 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1228 bool disabled;
1229
9a34af4a
TI		 1230 wait_for_completion(&hda->probe_wait);
1231 if (hda->init_failed)
a82d51ed
TI		 1232 return;
1233
1234 disabled = (state == VGA_SWITCHEROO_OFF);
1235 if (chip->disabled == disabled)
1236 return;
1237
a41d1224 1238 if (!hda->probe_continued) {
a82d51ed
TI		 1239 chip->disabled = disabled;
1240 if (!disabled) {
4e76a883
TI		 1241 dev_info(chip->card->dev,
1242 "Start delayed initialization\n");
5c90680e 1243 if (azx_probe_continue(chip) < 0) {
4e76a883 1244 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1245 hda->init_failed = true;
a82d51ed
TI		 1246 }
1247 }
1248 } else {
2b760d88 1249 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1250 disabled ? "Disabling" : "Enabling");
a82d51ed 1251 if (disabled) {
8928756d
DR		 1252 pm_runtime_put_sync_suspend(card->dev);
1253 azx_suspend(card->dev);
2b760d88 1254 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1255 * however we have no ACPI handle, so pci/acpi can't put us there,
1256 * put ourselves there */
1257 pci->current_state = PCI_D3cold;
a82d51ed 1258 chip->disabled = true;
a41d1224 1259 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1260 dev_warn(chip->card->dev,
1261 "Cannot lock devices!\n");
a82d51ed 1262 } else {
a41d1224 1263 snd_hda_unlock_devices(&chip->bus);
8928756d 1264 pm_runtime_get_noresume(card->dev);
a82d51ed 1265 chip->disabled = false;
8928756d 1266 azx_resume(card->dev);
a82d51ed
TI		 1267 }
1268 }
1269}
1270
1271static bool azx_vs_can_switch(struct pci_dev *pci)
1272{
1273 struct snd_card *card = pci_get_drvdata(pci);
1274 struct azx *chip = card->private_data;
9a34af4a 1275 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1276
9a34af4a
TI		 1277 wait_for_completion(&hda->probe_wait);
1278 if (hda->init_failed)
a82d51ed 1279 return false;
a41d1224 1280 if (chip->disabled || !hda->probe_continued)
a82d51ed 1281 return true;
a41d1224 1282 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1283 return false;
a41d1224 1284 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1285 return true;
1286}
1287
e23e7a14 1288static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1289{
9a34af4a 1290 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1291 struct pci_dev *p = get_bound_vga(chip->pci);
1292 if (p) {
4e76a883 1293 dev_info(chip->card->dev,
2b760d88 1294 "Handle vga_switcheroo audio client\n");
9a34af4a 1295 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1296 pci_dev_put(p);
1297 }
1298}
1299
1300static const struct vga_switcheroo_client_ops azx_vs_ops = {
1301 .set_gpu_state = azx_vs_set_state,
1302 .can_switch = azx_vs_can_switch,
1303};
1304
e23e7a14 1305static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1306{
9a34af4a 1307 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1308 int err;
1309
9a34af4a 1310 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1311 return 0;
1312 /* FIXME: currently only handling DIS controller
1313 * is there any machine with two switchable HDMI audio controllers?
1314 */
128960a9 1315 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
21b45676 1316 VGA_SWITCHEROO_DIS);
128960a9
TI		 1317 if (err < 0)
1318 return err;
9a34af4a 1319 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1320
1321 /* register as an optimus hdmi audio power domain */
8928756d 1322 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1323 &hda->hdmi_pm_domain);
128960a9 1324 return 0;
a82d51ed
TI		 1325}
1326#else
1327#define init_vga_switcheroo(chip) /* NOP */
1328#define register_vga_switcheroo(chip) 0
8393ec4a 1329#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1330#endif /* SUPPORT_VGA_SWITCHER */
1331
1da177e4
LT		 1332/*
1333 * destructor
1334 */
a98f90fd 1335static int azx_free(struct azx *chip)
1da177e4 1336{
c67e2228 1337 struct pci_dev *pci = chip->pci;
a07187c9 1338 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1339 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1340
364aa716 1341 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1342 pm_runtime_get_noresume(&pci->dev);
1343
65fcd41d
TI		 1344 azx_del_card_list(chip);
1345
9a34af4a
TI		 1346 hda->init_failed = 1; /* to be sure */
1347 complete_all(&hda->probe_wait);
f4c482a4 1348
9a34af4a 1349 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1350 if (chip->disabled && hda->probe_continued)
1351 snd_hda_unlock_devices(&chip->bus);
ab58d8cc 1352 if (hda->vga_switcheroo_registered) {
128960a9 1353 vga_switcheroo_unregister_client(chip->pci);
ab58d8cc
PW		 1354 vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1355 }
a82d51ed
TI		 1356 }
1357
a41d1224 1358 if (bus->chip_init) {
9ad593f6 1359 azx_clear_irq_pending(chip);
7833c3f8 1360 azx_stop_all_streams(chip);
cb53c626 1361 azx_stop_chip(chip);
1da177e4
LT		 1362 }
1363
a41d1224
TI		 1364 if (bus->irq >= 0)
1365 free_irq(bus->irq, (void*)chip);
68e7fffc 1366 if (chip->msi)
30b35399 1367 pci_disable_msi(chip->pci);
a41d1224 1368 iounmap(bus->remap_addr);
1da177e4 1369
67908994 1370 azx_free_stream_pages(chip);
a41d1224
TI		 1371 azx_free_streams(chip);
1372 snd_hdac_bus_exit(bus);
1373
a82d51ed
TI		 1374 if (chip->region_requested)
1375 pci_release_regions(chip->pci);
a41d1224 1376
1da177e4 1377 pci_disable_device(chip->pci);
4918cdab 1378#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1379 release_firmware(chip->fw);
4918cdab 1380#endif
98d8fc6c 1381
99a2008d 1382 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
795614dd 1383 if (hda->need_i915_power)
98d8fc6c
ML		 1384 snd_hdac_display_power(bus, false);
1385 snd_hdac_i915_exit(bus);
99a2008d 1386 }
a07187c9 1387 kfree(hda);
1da177e4
LT		 1388
1389 return 0;
1390}
1391
a41d1224
TI		 1392static int azx_dev_disconnect(struct snd_device *device)
1393{
1394 struct azx *chip = device->device_data;
1395
1396 chip->bus.shutdown = 1;
1397 return 0;
1398}
1399
a98f90fd 1400static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1401{
1402 return azx_free(device->device_data);
1403}
1404
8393ec4a 1405#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1406/*
2b760d88 1407 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1408 */
e23e7a14 1409static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1410{
1411 struct pci_dev *p;
1412
1413 /* check only discrete GPU */
1414 switch (pci->vendor) {
1415 case PCI_VENDOR_ID_ATI:
1416 case PCI_VENDOR_ID_AMD:
1417 case PCI_VENDOR_ID_NVIDIA:
1418 if (pci->devfn == 1) {
1419 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1420 pci->bus->number, 0);
1421 if (p) {
1422 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1423 return p;
1424 pci_dev_put(p);
1425 }
1426 }
1427 break;
1428 }
1429 return NULL;
1430}
1431
e23e7a14 1432static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1433{
1434 bool vga_inactive = false;
1435 struct pci_dev *p = get_bound_vga(pci);
1436
1437 if (p) {
12b78a7f 1438 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1439 vga_inactive = true;
1440 pci_dev_put(p);
1441 }
1442 return vga_inactive;
1443}
8393ec4a 1444#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1445
3372a153
TI		 1446/*
1447 * white/black-listing for position_fix
1448 */
e23e7a14 1449static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1450 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1451 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1452 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1453 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1454 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1455 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1456 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1457 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1458 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1459 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1460 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1461 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1462 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1463 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1464 {}
1465};
1466
e23e7a14 1467static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1468{
1469 const struct snd_pci_quirk *q;
1470
c673ba1c 1471 switch (fix) {
1dac6695 1472 case POS_FIX_AUTO:
c673ba1c
TI		 1473 case POS_FIX_LPIB:
1474 case POS_FIX_POSBUF:
4cb36310 1475 case POS_FIX_VIACOMBO:
a6f2fd55 1476 case POS_FIX_COMBO:
f87e7f25 1477 case POS_FIX_SKL:
c673ba1c
TI		 1478 return fix;
1479 }
1480
c673ba1c
TI		 1481 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1482 if (q) {
4e76a883
TI		 1483 dev_info(chip->card->dev,
1484 "position_fix set to %d for device %04x:%04x\n",
1485 q->value, q->subvendor, q->subdevice);
c673ba1c 1486 return q->value;
3372a153 1487 }
bdd9ef24
DH		 1488
1489 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1490 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1491 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1492 return POS_FIX_VIACOMBO;
9477c58e
TI		 1493 }
1494 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1495 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1496 return POS_FIX_LPIB;
bdd9ef24 1497 }
f87e7f25
TI		 1498 if (IS_SKL_PLUS(chip->pci)) {
1499 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1500 return POS_FIX_SKL;
1501 }
c673ba1c 1502 return POS_FIX_AUTO;
3372a153
TI		 1503}
1504
b6050ef6
TI		 1505static void assign_position_fix(struct azx *chip, int fix)
1506{
1507 static azx_get_pos_callback_t callbacks[] = {
1508 [POS_FIX_AUTO] = NULL,
1509 [POS_FIX_LPIB] = azx_get_pos_lpib,
1510 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1511 [POS_FIX_VIACOMBO] = azx_via_get_position,
1512 [POS_FIX_COMBO] = azx_get_pos_lpib,
f87e7f25 1513 [POS_FIX_SKL] = azx_get_pos_skl,
b6050ef6
TI		 1514 };
1515
1516 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1517
1518 /* combo mode uses LPIB only for playback */
1519 if (fix == POS_FIX_COMBO)
1520 chip->get_position[1] = NULL;
1521
f87e7f25 1522 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1523 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1524 chip->get_delay[0] = chip->get_delay[1] =
1525 azx_get_delay_from_lpib;
1526 }
1527
1528}
1529
669ba27a
TI		 1530/*
1531 * black-lists for probe_mask
1532 */
e23e7a14 1533static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1534 /* Thinkpad often breaks the controller communication when accessing
1535 * to the non-working (or non-existing) modem codec slot.
1536 */
1537 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1538 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1539 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1540 /* broken BIOS */
1541 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1542 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1543 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1544 /* forced codec slots */
93574844 1545 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1546 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1547 /* WinFast VP200 H (Teradici) user reported broken communication */
1548 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1549 {}
1550};
1551
f1eaaeec
TI		 1552#define AZX_FORCE_CODEC_MASK 0x100
1553
e23e7a14 1554static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1555{
1556 const struct snd_pci_quirk *q;
1557
f1eaaeec
TI		 1558 chip->codec_probe_mask = probe_mask[dev];
1559 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1560 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1561 if (q) {
4e76a883
TI		 1562 dev_info(chip->card->dev,
1563 "probe_mask set to 0x%x for device %04x:%04x\n",
1564 q->value, q->subvendor, q->subdevice);
f1eaaeec 1565 chip->codec_probe_mask = q->value;
669ba27a
TI		 1566 }
1567 }
f1eaaeec
TI		 1568
1569 /* check forced option */
1570 if (chip->codec_probe_mask != -1 &&
1571 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1572 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1573 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1574 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1575 }
669ba27a
TI		 1576}
1577
4d8e22e0 1578/*
71623855 1579 * white/black-list for enable_msi
4d8e22e0 1580 */
e23e7a14 1581static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1582 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1583 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1584 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1585 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1586 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1587 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1588 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1589 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1590 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1591 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1592 {}
1593};
1594
e23e7a14 1595static void check_msi(struct azx *chip)
4d8e22e0
TI		 1596{
1597 const struct snd_pci_quirk *q;
1598
71623855
TI		 1599 if (enable_msi >= 0) {
1600 chip->msi = !!enable_msi;
4d8e22e0 1601 return;
71623855
TI		 1602 }
1603 chip->msi = 1; /* enable MSI as default */
1604 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1605 if (q) {
4e76a883
TI		 1606 dev_info(chip->card->dev,
1607 "msi for device %04x:%04x set to %d\n",
1608 q->subvendor, q->subdevice, q->value);
4d8e22e0 1609 chip->msi = q->value;
80c43ed7
TI		 1610 return;
1611 }
1612
1613 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1614 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1615 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1616 chip->msi = 0;
4d8e22e0
TI		 1617 }
1618}
1619
a1585d76 1620/* check the snoop mode availability */
e23e7a14 1621static void azx_check_snoop_available(struct azx *chip)
a1585d76 1622{
7c732015 1623 int snoop = hda_snoop;
a1585d76 1624
7c732015
TI		 1625 if (snoop >= 0) {
1626 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1627 snoop ? "snoop" : "non-snoop");
1628 chip->snoop = snoop;
1629 return;
1630 }
1631
1632 snoop = true;
37e661ee
TI		 1633 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1634 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1635 /* force to non-snoop mode for a new VIA controller
1636 * when BIOS is set
1637 */
7c732015
TI		 1638 u8 val;
1639 pci_read_config_byte(chip->pci, 0x42, &val);
1640 if (!(val & 0x80) && chip->pci->revision == 0x30)
1641 snoop = false;
a1585d76
TI		 1642 }
1643
37e661ee
TI		 1644 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1645 snoop = false;
1646
7c732015
TI		 1647 chip->snoop = snoop;
1648 if (!snoop)
1649 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1650}
669ba27a 1651
99a2008d
WX		 1652static void azx_probe_work(struct work_struct *work)
1653{
9a34af4a
TI		 1654 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1655 azx_probe_continue(&hda->chip);
99a2008d 1656}
99a2008d 1657
4f0189be
TI		 1658static int default_bdl_pos_adj(struct azx *chip)
1659{
2cf721db
TI		 1660 /* some exceptions: Atoms seem problematic with value 1 */
1661 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1662 switch (chip->pci->device) {
1663 case 0x0f04: /* Baytrail */
1664 case 0x2284: /* Braswell */
1665 return 32;
1666 }
1667 }
1668
4f0189be
TI		 1669 switch (chip->driver_type) {
1670 case AZX_DRIVER_ICH:
1671 case AZX_DRIVER_PCH:
1672 return 1;
1673 default:
1674 return 32;
1675 }
1676}
1677
1da177e4
LT		 1678/*
1679 * constructor
1680 */
a43ff5ba
TI		 1681static const struct hdac_io_ops pci_hda_io_ops;
1682static const struct hda_controller_ops pci_hda_ops;
1683
e23e7a14
BP		 1684static int azx_create(struct snd_card *card, struct pci_dev *pci,
1685 int dev, unsigned int driver_caps,
1686 struct azx **rchip)
1da177e4 1687{
a98f90fd 1688 static struct snd_device_ops ops = {
a41d1224 1689 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1690 .dev_free = azx_dev_free,
1691 };
a07187c9 1692 struct hda_intel *hda;
a82d51ed
TI		 1693 struct azx *chip;
1694 int err;
1da177e4
LT		 1695
1696 *rchip = NULL;
bcd72003 1697
927fc866
PM		 1698 err = pci_enable_device(pci);
1699 if (err < 0)
1da177e4
LT		 1700 return err;
1701
a07187c9
ML		 1702 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1703 if (!hda) {
1da177e4
LT		 1704 pci_disable_device(pci);
1705 return -ENOMEM;
1706 }
1707
a07187c9 1708 chip = &hda->chip;
62932df8 1709 mutex_init(&chip->open_mutex);
1da177e4
LT		 1710 chip->card = card;
1711 chip->pci = pci;
a43ff5ba 1712 chip->ops = &pci_hda_ops;
9477c58e
TI		 1713 chip->driver_caps = driver_caps;
1714 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1715 check_msi(chip);
555e219f 1716 chip->dev_index = dev;
749ee287 1717 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1718 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1719 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1720 INIT_LIST_HEAD(&hda->list);
a82d51ed 1721 init_vga_switcheroo(chip);
9a34af4a 1722 init_completion(&hda->probe_wait);
1da177e4 1723
b6050ef6 1724 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1725
5aba4f8e 1726 check_probe_mask(chip, dev);
3372a153 1727
41438f13
TI		 1728 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1729 chip->fallback_to_single_cmd = 1;
1730 else /* explicitly set to single_cmd or not */
1731 chip->single_cmd = single_cmd;
1732
a1585d76 1733 azx_check_snoop_available(chip);
c74db86b 1734
4f0189be
TI		 1735 if (bdl_pos_adj[dev] < 0)
1736 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1737 else
1738 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1739
a41d1224
TI		 1740 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1741 if (err < 0) {
1742 kfree(hda);
1743 pci_disable_device(pci);
1744 return err;
1745 }
1746
7d9a1808
TI		 1747 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1748 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1749 chip->bus.needs_damn_long_delay = 1;
1750 }
1751
a82d51ed
TI		 1752 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1753 if (err < 0) {
4e76a883 1754 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1755 azx_free(chip);
1756 return err;
1757 }
1758
99a2008d 1759 /* continue probing in work context as may trigger request module */
9a34af4a 1760 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1761
a82d51ed 1762 *rchip = chip;
99a2008d 1763
a82d51ed
TI		 1764 return 0;
1765}
1766
48c8b0eb 1767static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1768{
1769 int dev = chip->dev_index;
1770 struct pci_dev *pci = chip->pci;
1771 struct snd_card *card = chip->card;
a41d1224 1772 struct hdac_bus *bus = azx_bus(chip);
67908994 1773 int err;
a82d51ed 1774 unsigned short gcap;
413cbf46 1775 unsigned int dma_bits = 64;
a82d51ed 1776
07e4ca50
TI		 1777#if BITS_PER_LONG != 64
1778 /* Fix up base address on ULI M5461 */
1779 if (chip->driver_type == AZX_DRIVER_ULI) {
1780 u16 tmp3;
1781 pci_read_config_word(pci, 0x40, &tmp3);
1782 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1783 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1784 }
1785#endif
1786
927fc866 1787 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1788 if (err < 0)
1da177e4 1789 return err;
a82d51ed 1790 chip->region_requested = 1;
1da177e4 1791
a41d1224
TI		 1792 bus->addr = pci_resource_start(pci, 0);
1793 bus->remap_addr = pci_ioremap_bar(pci, 0);
1794 if (bus->remap_addr == NULL) {
4e76a883 1795 dev_err(card->dev, "ioremap error\n");
a82d51ed 1796 return -ENXIO;
1da177e4
LT		 1797 }
1798
50279d9b
GS		 1799 if (IS_SKL_PLUS(pci))
1800 snd_hdac_bus_parse_capabilities(bus);
1801
1802 /*
1803 * Some Intel CPUs has always running timer (ART) feature and
1804 * controller may have Global time sync reporting capability, so
1805 * check both of these before declaring synchronized time reporting
1806 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1807 */
1808 chip->gts_present = false;
1809
1810#ifdef CONFIG_X86
1811 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1812 chip->gts_present = true;
1813#endif
1814
db79afa1
BH		 1815 if (chip->msi) {
1816 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1817 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1818 pci->no_64bit_msi = true;
1819 }
68e7fffc
TI		 1820 if (pci_enable_msi(pci) < 0)
1821 chip->msi = 0;
db79afa1 1822 }
7376d013 1823
a82d51ed
TI		 1824 if (azx_acquire_irq(chip, 0) < 0)
1825 return -EBUSY;
1da177e4
LT		 1826
1827 pci_set_master(pci);
a41d1224 1828 synchronize_irq(bus->irq);
1da177e4 1829
bcd72003 1830 gcap = azx_readw(chip, GCAP);
4e76a883 1831 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1832
413cbf46
TI		 1833 /* AMD devices support 40 or 48bit DMA, take the safe one */
1834 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1835 dma_bits = 40;
1836
dc4c2e6b 1837 /* disable SB600 64bit support for safety */
9477c58e 1838 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1839 struct pci_dev *p_smbus;
413cbf46 1840 dma_bits = 40;
dc4c2e6b
AB		 1841 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1842 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1843 NULL);
1844 if (p_smbus) {
1845 if (p_smbus->revision < 0x30)
fb1d8ac2 1846 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1847 pci_dev_put(p_smbus);
1848 }
1849 }
09240cf4 1850
3ab7511e
AB		 1851 /* NVidia hardware normally only supports up to 40 bits of DMA */
1852 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1853 dma_bits = 40;
1854
9477c58e
TI		 1855 /* disable 64bit DMA address on some devices */
1856 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1857 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1858 gcap &= ~AZX_GCAP_64OK;
9477c58e 1859 }
396087ea 1860
2ae66c26 1861 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1862 if (align_buffer_size >= 0)
1863 chip->align_buffer_size = !!align_buffer_size;
1864 else {
103884a3 1865 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1866 chip->align_buffer_size = 0;
7bfe059e
TI		 1867 else
1868 chip->align_buffer_size = 1;
1869 }
2ae66c26 1870
cf7aaca8 1871 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1872 if (!(gcap & AZX_GCAP_64OK))
1873 dma_bits = 32;
412b979c
QL		 1874 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1875 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1876 } else {
412b979c
QL		 1877 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1878 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1879 }
cf7aaca8 1880
8b6ed8e7
TI		 1881 /* read number of streams from GCAP register instead of using
1882 * hardcoded value
1883 */
1884 chip->capture_streams = (gcap >> 8) & 0x0f;
1885 chip->playback_streams = (gcap >> 12) & 0x0f;
1886 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1887 /* gcap didn't give any info, switching to old method */
1888
1889 switch (chip->driver_type) {
1890 case AZX_DRIVER_ULI:
1891 chip->playback_streams = ULI_NUM_PLAYBACK;
1892 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1893 break;
1894 case AZX_DRIVER_ATIHDMI:
1815b34a 1895 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1896 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1897 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1898 break;
c4da29ca 1899 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1900 default:
1901 chip->playback_streams = ICH6_NUM_PLAYBACK;
1902 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1903 break;
1904 }
07e4ca50 1905 }
8b6ed8e7
TI		 1906 chip->capture_index_offset = 0;
1907 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1908 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1909
df56c3db
JK		 1910 /* sanity check for the SDxCTL.STRM field overflow */
1911 if (chip->num_streams > 15 &&
1912 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1913 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1914 "forcing separate stream tags", chip->num_streams);
1915 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1916 }
1917
a41d1224
TI		 1918 /* initialize streams */
1919 err = azx_init_streams(chip);
81740861 1920 if (err < 0)
a82d51ed 1921 return err;
1da177e4 1922
a41d1224
TI		 1923 err = azx_alloc_stream_pages(chip);
1924 if (err < 0)
1925 return err;
1da177e4
LT		 1926
1927 /* initialize chip */
cb53c626 1928 azx_init_pci(chip);
e4d9e513 1929
bb03ed21
TI		 1930 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1931 snd_hdac_i915_set_bclk(bus);
e4d9e513 1932
0a673521 1933 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1934
1935 /* codec detection */
a41d1224 1936 if (!azx_bus(chip)->codec_mask) {
4e76a883 1937 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1938 return -ENODEV;
1da177e4
LT		 1939 }
1940
07e4ca50 1941 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1942 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1943 sizeof(card->shortname));
1944 snprintf(card->longname, sizeof(card->longname),
1945 "%s at 0x%lx irq %i",
a41d1224 1946 card->shortname, bus->addr, bus->irq);
07e4ca50 1947
1da177e4 1948 return 0;
1da177e4
LT		 1949}
1950
97c6a3d1 1951#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1952/* callback from request_firmware_nowait() */
1953static void azx_firmware_cb(const struct firmware *fw, void *context)
1954{
1955 struct snd_card *card = context;
1956 struct azx *chip = card->private_data;
1957 struct pci_dev *pci = chip->pci;
1958
1959 if (!fw) {
4e76a883 1960 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1961 goto error;
1962 }
1963
1964 chip->fw = fw;
1965 if (!chip->disabled) {
1966 /* continue probing */
1967 if (azx_probe_continue(chip))
1968 goto error;
1969 }
1970 return; /* OK */
1971
1972 error:
1973 snd_card_free(card);
1974 pci_set_drvdata(pci, NULL);
1975}
97c6a3d1 1976#endif
5cb543db 1977
40830813
DR		 1978/*
1979 * HDA controller ops.
1980 */
1981
1982/* PCI register access. */
db291e36 1983static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1984{
1985 writel(value, addr);
1986}
1987
db291e36 1988static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1989{
1990 return readl(addr);
1991}
1992
db291e36 1993static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1994{
1995 writew(value, addr);
1996}
1997
db291e36 1998static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1999{
2000 return readw(addr);
2001}
2002
db291e36 2003static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 2004{
2005 writeb(value, addr);
2006}
2007
db291e36 2008static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 2009{
2010 return readb(addr);
2011}
2012
f46ea609
DR		 2013static int disable_msi_reset_irq(struct azx *chip)
2014{
a41d1224 2015 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 2016 int err;
2017
a41d1224
TI		 2018 free_irq(bus->irq, chip);
2019 bus->irq = -1;
f46ea609
DR		 2020 pci_disable_msi(chip->pci);
2021 chip->msi = 0;
2022 err = azx_acquire_irq(chip, 1);
2023 if (err < 0)
2024 return err;
2025
2026 return 0;
2027}
2028
b419b35b 2029/* DMA page allocation helpers. */
a43ff5ba 2030static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 2031 int type,
2032 size_t size,
2033 struct snd_dma_buffer *buf)
2034{
a41d1224 2035 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 2036 int err;
2037
2038 err = snd_dma_alloc_pages(type,
a43ff5ba 2039 bus->dev,
b419b35b
DR		 2040 size, buf);
2041 if (err < 0)
2042 return err;
2043 mark_pages_wc(chip, buf, true);
2044 return 0;
2045}
2046
a43ff5ba 2047static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 2048{
a41d1224 2049 struct azx *chip = bus_to_azx(bus);
a43ff5ba 2050
b419b35b
DR		 2051 mark_pages_wc(chip, buf, false);
2052 snd_dma_free_pages(buf);
2053}
2054
2055static int substream_alloc_pages(struct azx *chip,
2056 struct snd_pcm_substream *substream,
2057 size_t size)
2058{
2059 struct azx_dev *azx_dev = get_azx_dev(substream);
2060 int ret;
2061
2062 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 2063 ret = snd_pcm_lib_malloc_pages(substream, size);
2064 if (ret < 0)
2065 return ret;
2066 mark_runtime_wc(chip, azx_dev, substream, true);
2067 return 0;
2068}
2069
2070static int substream_free_pages(struct azx *chip,
2071 struct snd_pcm_substream *substream)
2072{
2073 struct azx_dev *azx_dev = get_azx_dev(substream);
2074 mark_runtime_wc(chip, azx_dev, substream, false);
2075 return snd_pcm_lib_free_pages(substream);
2076}
2077
8769b278
DR		 2078static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2079 struct vm_area_struct *area)
2080{
2081#ifdef CONFIG_X86
2082 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2083 struct azx *chip = apcm->chip;
3b70bdba 2084 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 2085 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2086#endif
2087}
2088
a43ff5ba 2089static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 2090 .reg_writel = pci_azx_writel,
2091 .reg_readl = pci_azx_readl,
2092 .reg_writew = pci_azx_writew,
2093 .reg_readw = pci_azx_readw,
2094 .reg_writeb = pci_azx_writeb,
2095 .reg_readb = pci_azx_readb,
b419b35b
DR		 2096 .dma_alloc_pages = dma_alloc_pages,
2097 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 2098};
2099
2100static const struct hda_controller_ops pci_hda_ops = {
2101 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 2102 .substream_alloc_pages = substream_alloc_pages,
2103 .substream_free_pages = substream_free_pages,
8769b278 2104 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 2105 .position_check = azx_position_check,
17eccb27 2106 .link_power = azx_intel_link_power,
40830813
DR		 2107};
2108
e23e7a14
BP		 2109static int azx_probe(struct pci_dev *pci,
2110 const struct pci_device_id *pci_id)
1da177e4 2111{
5aba4f8e 2112 static int dev;
a98f90fd 2113 struct snd_card *card;
9a34af4a 2114 struct hda_intel *hda;
a98f90fd 2115 struct azx *chip;
aad730d0 2116 bool schedule_probe;
927fc866 2117 int err;
1da177e4 2118
5aba4f8e
TI		 2119 if (dev >= SNDRV_CARDS)
2120 return -ENODEV;
2121 if (!enable[dev]) {
2122 dev++;
2123 return -ENOENT;
2124 }
2125
60c5772b
TI		 2126 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2127 0, &card);
e58de7ba 2128 if (err < 0) {
4e76a883 2129 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2130 return err;
1da177e4
LT		 2131 }
2132
a43ff5ba 2133 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2134 if (err < 0)
2135 goto out_free;
421a1252 2136 card->private_data = chip;
9a34af4a 2137 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2138
2139 pci_set_drvdata(pci, card);
2140
2141 err = register_vga_switcheroo(chip);
2142 if (err < 0) {
2b760d88 2143 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2144 goto out_free;
2145 }
2146
2147 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2148 dev_info(card->dev, "VGA controller is disabled\n");
2149 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2150 chip->disabled = true;
2151 }
2152
aad730d0 2153 schedule_probe = !chip->disabled;
1da177e4 2154
4918cdab
TI		 2155#ifdef CONFIG_SND_HDA_PATCH_LOADER
2156 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2157 dev_info(card->dev, "Applying patch firmware '%s'\n",
2158 patch[dev]);
5cb543db
TI		 2159 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2160 &pci->dev, GFP_KERNEL, card,
2161 azx_firmware_cb);
4918cdab
TI		 2162 if (err < 0)
2163 goto out_free;
aad730d0 2164 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2165 }
2166#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2167
aad730d0 2168#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2169 if (CONTROLLER_IN_GPU(pci))
2170 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2171#endif
99a2008d 2172
aad730d0 2173 if (schedule_probe)
9a34af4a 2174 schedule_work(&hda->probe_work);
a82d51ed 2175
a82d51ed 2176 dev++;
88d071fc 2177 if (chip->disabled)
9a34af4a 2178 complete_all(&hda->probe_wait);
a82d51ed
TI		 2179 return 0;
2180
2181out_free:
2182 snd_card_free(card);
2183 return err;
2184}
2185
e62a42ae
DR		 2186/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2187static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2188 [AZX_DRIVER_NVIDIA] = 8,
2189 [AZX_DRIVER_TERA] = 1,
2190};
2191
48c8b0eb 2192static int azx_probe_continue(struct azx *chip)
a82d51ed 2193{
9a34af4a 2194 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2195 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2196 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2197 int dev = chip->dev_index;
2198 int err;
2199
a41d1224 2200 hda->probe_continued = 1;
795614dd
ML		 2201
2202 /* Request display power well for the HDA controller or codec. For
2203 * Haswell/Broadwell, both the display HDA controller and codec need
2204 * this power. For other platforms, like Baytrail/Braswell, only the
2205 * display codec needs the power and it can be released after probe.
2206 */
99a2008d 2207 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
03b135ce
LY		 2208 /* HSW/BDW controllers need this power */
2209 if (CONTROLLER_IN_GPU(pci))
2bd1f73f
ML		 2210 hda->need_i915_power = 1;
2211
98d8fc6c 2212 err = snd_hdac_i915_init(bus);
535115b5
TI		 2213 if (err < 0) {
2214 /* if the controller is bound only with HDMI/DP
2215 * (for HSW and BDW), we need to abort the probe;
2216 * for other chips, still continue probing as other
2217 * codecs can be on the same link.
2218 */
bed2e98e
TI		 2219 if (CONTROLLER_IN_GPU(pci)) {
2220 dev_err(chip->card->dev,
2221 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2222 goto out_free;
bed2e98e 2223 } else
535115b5
TI		 2224 goto skip_i915;
2225 }
795614dd 2226
98d8fc6c 2227 err = snd_hdac_display_power(bus, true);
74b0c2d7
TI		 2228 if (err < 0) {
2229 dev_err(chip->card->dev,
2230 "Cannot turn on display power on i915\n");
795614dd 2231 goto i915_power_fail;
74b0c2d7 2232 }
99a2008d
WX		 2233 }
2234
bf06848b 2235 skip_i915:
5c90680e
TI		 2236 err = azx_first_init(chip);
2237 if (err < 0)
2238 goto out_free;
2239
2dca0bba
JK		 2240#ifdef CONFIG_SND_HDA_INPUT_BEEP
2241 chip->beep_mode = beep_mode[dev];
2242#endif
2243
1da177e4 2244 /* create codec instances */
96d2bd6e 2245 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2246 if (err < 0)
2247 goto out_free;
96d2bd6e 2248
4ea6fbc8 2249#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2250 if (chip->fw) {
a41d1224 2251 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2252 chip->fw->data);
4ea6fbc8
TI		 2253 if (err < 0)
2254 goto out_free;
e39ae856 2255#ifndef CONFIG_PM
4918cdab
TI		 2256 release_firmware(chip->fw); /* no longer needed */
2257 chip->fw = NULL;
e39ae856 2258#endif
4ea6fbc8
TI		 2259 }
2260#endif
10e77dda 2261 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2262 err = azx_codec_configure(chip);
2263 if (err < 0)
2264 goto out_free;
2265 }
1da177e4 2266
a82d51ed 2267 err = snd_card_register(chip->card);
41dda0fd
WF		 2268 if (err < 0)
2269 goto out_free;
1da177e4 2270
cb53c626 2271 chip->running = 1;
65fcd41d 2272 azx_add_card_list(chip);
a41d1224 2273 snd_hda_set_power_save(&chip->bus, power_save * 1000);
364aa716 2274 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
30ff5957 2275 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2276
41dda0fd 2277out_free:
795614dd
ML		 2278 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2279 && !hda->need_i915_power)
98d8fc6c 2280 snd_hdac_display_power(bus, false);
795614dd
ML		 2281
2282i915_power_fail:
88d071fc 2283 if (err < 0)
9a34af4a
TI		 2284 hda->init_failed = 1;
2285 complete_all(&hda->probe_wait);
41dda0fd 2286 return err;
1da177e4
LT		 2287}
2288
e23e7a14 2289static void azx_remove(struct pci_dev *pci)
1da177e4 2290{
9121947d 2291 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2292 struct azx *chip;
2293 struct hda_intel *hda;
2294
2295 if (card) {
0b8c8219 2296 /* cancel the pending probing work */
991f86d7
TI		 2297 chip = card->private_data;
2298 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2299 /* FIXME: below is an ugly workaround.
2300 * Both device_release_driver() and driver_probe_device()
2301 * take *both* the device's and its parent's lock before
2302 * calling the remove() and probe() callbacks. The codec
2303 * probe takes the locks of both the codec itself and its
2304 * parent, i.e. the PCI controller dev. Meanwhile, when
2305 * the PCI controller is unbound, it takes its lock, too
2306 * ==> ouch, a deadlock!
2307 * As a workaround, we unlock temporarily here the controller
2308 * device during cancel_work_sync() call.
2309 */
2310 device_unlock(&pci->dev);
0b8c8219 2311 cancel_work_sync(&hda->probe_work);
ab949d51 2312 device_lock(&pci->dev);
b8dfc462 2313
9121947d 2314 snd_card_free(card);
991f86d7 2315 }
1da177e4
LT		 2316}
2317
b2a0bafa
TI		 2318static void azx_shutdown(struct pci_dev *pci)
2319{
2320 struct snd_card *card = pci_get_drvdata(pci);
2321 struct azx *chip;
2322
2323 if (!card)
2324 return;
2325 chip = card->private_data;
2326 if (chip && chip->running)
2327 azx_stop_chip(chip);
2328}
2329
1da177e4 2330/* PCI IDs */
6f51f6cf 2331static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2332 /* CPT */
9477c58e 2333 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2334 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2335 /* PBG */
9477c58e 2336 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2337 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2338 /* Panther Point */
9477c58e 2339 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2340 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2341 /* Lynx Point */
2342 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2343 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2344 /* 9 Series */
2345 { PCI_DEVICE(0x8086, 0x8ca0),
2346 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2347 /* Wellsburg */
2348 { PCI_DEVICE(0x8086, 0x8d20),
2349 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2350 { PCI_DEVICE(0x8086, 0x8d21),
2351 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2352 /* Lewisburg */
2353 { PCI_DEVICE(0x8086, 0xa1f0),
e7480b34 2354 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
5cf92c8b 2355 { PCI_DEVICE(0x8086, 0xa270),
e7480b34 2356 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
144dad99
JR		 2357 /* Lynx Point-LP */
2358 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2359 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2360 /* Lynx Point-LP */
2361 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2362 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2363 /* Wildcat Point-LP */
2364 { PCI_DEVICE(0x8086, 0x9ca0),
2365 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2366 /* Sunrise Point */
2367 { PCI_DEVICE(0x8086, 0xa170),
db48abf4 2368 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2369 /* Sunrise Point-LP */
2370 { PCI_DEVICE(0x8086, 0x9d70),
d6795827 2371 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2372 /* Kabylake */
2373 { PCI_DEVICE(0x8086, 0xa171),
2374 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2375 /* Kabylake-LP */
2376 { PCI_DEVICE(0x8086, 0x9d71),
2377 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2378 /* Kabylake-H */
2379 { PCI_DEVICE(0x8086, 0xa2f0),
2380 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
c87693da
LH		 2381 /* Broxton-P(Apollolake) */
2382 { PCI_DEVICE(0x8086, 0x5a98),
2383 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2384 /* Broxton-T */
2385 { PCI_DEVICE(0x8086, 0x1a98),
2386 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
44b46d73
VK		 2387 /* Gemini-Lake */
2388 { PCI_DEVICE(0x8086, 0x3198),
2389 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2390 /* Haswell */
4a7c516b 2391 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2392 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2393 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2394 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2395 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2396 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2397 /* Broadwell */
2398 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2399 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2400 /* 5 Series/3400 */
2401 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2402 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2403 /* Poulsbo */
9477c58e 2404 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2405 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2406 /* Oaktrail */
09904b95 2407 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2408 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2409 /* BayTrail */
2410 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2411 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2412 /* Braswell */
2413 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2414 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2415 /* ICH6 */
8b0bd226 2416 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2417 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2418 /* ICH7 */
8b0bd226 2419 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2420 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2421 /* ESB2 */
8b0bd226 2422 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2423 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2424 /* ICH8 */
8b0bd226 2425 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2426 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2427 /* ICH9 */
8b0bd226 2428 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2429 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2430 /* ICH9 */
8b0bd226 2431 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2432 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2433 /* ICH10 */
8b0bd226 2434 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2435 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2436 /* ICH10 */
8b0bd226 2437 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2438 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2439 /* Generic Intel */
2440 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2441 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2442 .class_mask = 0xffffff,
103884a3 2443 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2444 /* ATI SB 450/600/700/800/900 */
2445 { PCI_DEVICE(0x1002, 0x437b),
2446 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2447 { PCI_DEVICE(0x1002, 0x4383),
2448 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2449 /* AMD Hudson */
2450 { PCI_DEVICE(0x1022, 0x780d),
2451 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2452 /* ATI HDMI */
fd48331f
MSB		 2453 { PCI_DEVICE(0x1002, 0x0002),
2454 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
650474fb
AD		 2455 { PCI_DEVICE(0x1002, 0x1308),
2456 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2457 { PCI_DEVICE(0x1002, 0x157a),
2458 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
d716fb03
AB		 2459 { PCI_DEVICE(0x1002, 0x15b3),
2460 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2461 { PCI_DEVICE(0x1002, 0x793b),
2462 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2463 { PCI_DEVICE(0x1002, 0x7919),
2464 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2465 { PCI_DEVICE(0x1002, 0x960f),
2466 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2467 { PCI_DEVICE(0x1002, 0x970f),
2468 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2469 { PCI_DEVICE(0x1002, 0x9840),
2470 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2471 { PCI_DEVICE(0x1002, 0xaa00),
2472 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2473 { PCI_DEVICE(0x1002, 0xaa08),
2474 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2475 { PCI_DEVICE(0x1002, 0xaa10),
2476 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2477 { PCI_DEVICE(0x1002, 0xaa18),
2478 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2479 { PCI_DEVICE(0x1002, 0xaa20),
2480 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2481 { PCI_DEVICE(0x1002, 0xaa28),
2482 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2483 { PCI_DEVICE(0x1002, 0xaa30),
2484 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2485 { PCI_DEVICE(0x1002, 0xaa38),
2486 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2487 { PCI_DEVICE(0x1002, 0xaa40),
2488 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2489 { PCI_DEVICE(0x1002, 0xaa48),
2490 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2491 { PCI_DEVICE(0x1002, 0xaa50),
2492 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2493 { PCI_DEVICE(0x1002, 0xaa58),
2494 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2495 { PCI_DEVICE(0x1002, 0xaa60),
2496 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2497 { PCI_DEVICE(0x1002, 0xaa68),
2498 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2499 { PCI_DEVICE(0x1002, 0xaa80),
2500 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2501 { PCI_DEVICE(0x1002, 0xaa88),
2502 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2503 { PCI_DEVICE(0x1002, 0xaa90),
2504 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2505 { PCI_DEVICE(0x1002, 0xaa98),
2506 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2507 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2508 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2509 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2510 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2511 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2512 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2513 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2514 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2515 { PCI_DEVICE(0x1002, 0xaac0),
2516 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2517 { PCI_DEVICE(0x1002, 0xaac8),
2518 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2519 { PCI_DEVICE(0x1002, 0xaad8),
2520 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2521 { PCI_DEVICE(0x1002, 0xaae8),
2522 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
8eb22214
MSB		 2523 { PCI_DEVICE(0x1002, 0xaae0),
2524 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2525 { PCI_DEVICE(0x1002, 0xaaf0),
2526 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2527 /* VIA VT8251/VT8237A */
26f05717 2528 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2529 /* VIA GFX VT7122/VX900 */
2530 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2531 /* VIA GFX VT6122/VX11 */
2532 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2533 /* SIS966 */
2534 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2535 /* ULI M5461 */
2536 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2537 /* NVIDIA MCP */
0c2fd1bf
TI		 2538 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2539 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2540 .class_mask = 0xffffff,
9477c58e 2541 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2542 /* Teradici */
9477c58e
TI		 2543 { PCI_DEVICE(0x6549, 0x1200),
2544 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2545 { PCI_DEVICE(0x6549, 0x2200),
2546 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2547 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2548 /* CTHDA chips */
2549 { PCI_DEVICE(0x1102, 0x0010),
2550 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2551 { PCI_DEVICE(0x1102, 0x0012),
2552 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2553#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2554 /* the following entry conflicts with snd-ctxfi driver,
2555 * as ctxfi driver mutates from HD-audio to native mode with
2556 * a special command sequence.
2557 */
4e01f54b
TI		 2558 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2559 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2560 .class_mask = 0xffffff,
9477c58e 2561 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2562 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2563#else
2564 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2565 { PCI_DEVICE(0x1102, 0x0009),
2566 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2567 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2568#endif
c563f473
TI		 2569 /* CM8888 */
2570 { PCI_DEVICE(0x13f6, 0x5011),
2571 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2572 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2573 /* Vortex86MX */
2574 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2575 /* VMware HDAudio */
2576 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2577 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2578 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2579 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2580 .class_mask = 0xffffff,
9477c58e 2581 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2582 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2583 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2584 .class_mask = 0xffffff,
9477c58e 2585 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2586 { 0, }
2587};
2588MODULE_DEVICE_TABLE(pci, azx_ids);
2589
2590/* pci_driver definition */
e9f66d9b 2591static struct pci_driver azx_driver = {
3733e424 2592 .name = KBUILD_MODNAME,
1da177e4
LT		 2593 .id_table = azx_ids,
2594 .probe = azx_probe,
e23e7a14 2595 .remove = azx_remove,
b2a0bafa 2596 .shutdown = azx_shutdown,
68cb2b55
TI		 2597 .driver = {
2598 .pm = AZX_PM_OPS,
2599 },
1da177e4
LT		 2600};
2601
e9f66d9b 2602module_pci_driver(azx_driver);
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