]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - sound/pci/hda/hda_intel.c
[ALSA] hda-codec - Fix ALC268 acer model
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT
1/*
2 *
d01ce99f
TI
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37#include <sound/driver.h>
38#include <asm/io.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
362775e2 41#include <linux/kernel.h>
1da177e4
LT
42#include <linux/module.h>
43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
62932df8 47#include <linux/mutex.h>
1da177e4
LT
48#include <sound/core.h>
49#include <sound/initval.h>
50#include "hda_codec.h"
51
52
b7fe4622
CL
53static int index = SNDRV_DEFAULT_IDX1;
54static char *id = SNDRV_DEFAULT_STR1;
55static char *model;
56static int position_fix;
954fa19a 57static int probe_mask = -1;
27346166 58static int single_cmd;
134a11f0 59static int enable_msi;
1da177e4 60
b7fe4622 61module_param(index, int, 0444);
1da177e4 62MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
b7fe4622 63module_param(id, charp, 0444);
1da177e4 64MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
b7fe4622 65module_param(model, charp, 0444);
1da177e4 66MODULE_PARM_DESC(model, "Use the given board model.");
b7fe4622 67module_param(position_fix, int, 0444);
d01ce99f
TI
68MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
69 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
606ad75f
TI
70module_param(probe_mask, int, 0444);
71MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
27346166 72module_param(single_cmd, bool, 0444);
d01ce99f
TI
73MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
74 "(for debugging only).");
134a11f0
TI
75module_param(enable_msi, int, 0);
76MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
606ad75f 77
dee1b66c 78#ifdef CONFIG_SND_HDA_POWER_SAVE
cb53c626 79/* power_save option is defined in hda_codec.c */
1da177e4 80
dee1b66c
TI
81/* reset the HD-audio controller in power save mode.
82 * this may give more power-saving, but will take longer time to
83 * wake up.
84 */
85static int power_save_controller = 1;
86module_param(power_save_controller, bool, 0644);
87MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
88#endif
89
2b3e584b
TI
90/* just for backward compatibility */
91static int enable;
698444f3 92module_param(enable, bool, 0444);
2b3e584b 93
1da177e4
LT
94MODULE_LICENSE("GPL");
95MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
96 "{Intel, ICH6M},"
2f1b3818 97 "{Intel, ICH7},"
f5d40b30 98 "{Intel, ESB2},"
d2981393 99 "{Intel, ICH8},"
f9cc8a8b 100 "{Intel, ICH9},"
fc20a562 101 "{ATI, SB450},"
89be83f8 102 "{ATI, SB600},"
778b6e1b 103 "{ATI, RS600},"
5b15c95f 104 "{ATI, RS690},"
e6db1119
WL
105 "{ATI, RS780},"
106 "{ATI, R600},"
fc20a562 107 "{VIA, VT8251},"
47672310 108 "{VIA, VT8237A},"
07e4ca50
TI
109 "{SiS, SIS966},"
110 "{ULI, M5461}}");
1da177e4
LT
111MODULE_DESCRIPTION("Intel HDA driver");
112
113#define SFX "hda-intel: "
114
cb53c626 115
1da177e4
LT
116/*
117 * registers
118 */
119#define ICH6_REG_GCAP 0x00
120#define ICH6_REG_VMIN 0x02
121#define ICH6_REG_VMAJ 0x03
122#define ICH6_REG_OUTPAY 0x04
123#define ICH6_REG_INPAY 0x06
124#define ICH6_REG_GCTL 0x08
125#define ICH6_REG_WAKEEN 0x0c
126#define ICH6_REG_STATESTS 0x0e
127#define ICH6_REG_GSTS 0x10
128#define ICH6_REG_INTCTL 0x20
129#define ICH6_REG_INTSTS 0x24
130#define ICH6_REG_WALCLK 0x30
131#define ICH6_REG_SYNC 0x34
132#define ICH6_REG_CORBLBASE 0x40
133#define ICH6_REG_CORBUBASE 0x44
134#define ICH6_REG_CORBWP 0x48
135#define ICH6_REG_CORBRP 0x4A
136#define ICH6_REG_CORBCTL 0x4c
137#define ICH6_REG_CORBSTS 0x4d
138#define ICH6_REG_CORBSIZE 0x4e
139
140#define ICH6_REG_RIRBLBASE 0x50
141#define ICH6_REG_RIRBUBASE 0x54
142#define ICH6_REG_RIRBWP 0x58
143#define ICH6_REG_RINTCNT 0x5a
144#define ICH6_REG_RIRBCTL 0x5c
145#define ICH6_REG_RIRBSTS 0x5d
146#define ICH6_REG_RIRBSIZE 0x5e
147
148#define ICH6_REG_IC 0x60
149#define ICH6_REG_IR 0x64
150#define ICH6_REG_IRS 0x68
151#define ICH6_IRS_VALID (1<<1)
152#define ICH6_IRS_BUSY (1<<0)
153
154#define ICH6_REG_DPLBASE 0x70
155#define ICH6_REG_DPUBASE 0x74
156#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
157
158/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
159enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
160
161/* stream register offsets from stream base */
162#define ICH6_REG_SD_CTL 0x00
163#define ICH6_REG_SD_STS 0x03
164#define ICH6_REG_SD_LPIB 0x04
165#define ICH6_REG_SD_CBL 0x08
166#define ICH6_REG_SD_LVI 0x0c
167#define ICH6_REG_SD_FIFOW 0x0e
168#define ICH6_REG_SD_FIFOSIZE 0x10
169#define ICH6_REG_SD_FORMAT 0x12
170#define ICH6_REG_SD_BDLPL 0x18
171#define ICH6_REG_SD_BDLPU 0x1c
172
173/* PCI space */
174#define ICH6_PCIREG_TCSEL 0x44
175
176/*
177 * other constants
178 */
179
180/* max number of SDs */
07e4ca50
TI
181/* ICH, ATI and VIA have 4 playback and 4 capture */
182#define ICH6_CAPTURE_INDEX 0
183#define ICH6_NUM_CAPTURE 4
184#define ICH6_PLAYBACK_INDEX 4
185#define ICH6_NUM_PLAYBACK 4
186
187/* ULI has 6 playback and 5 capture */
188#define ULI_CAPTURE_INDEX 0
189#define ULI_NUM_CAPTURE 5
190#define ULI_PLAYBACK_INDEX 5
191#define ULI_NUM_PLAYBACK 6
192
778b6e1b
FK
193/* ATI HDMI has 1 playback and 0 capture */
194#define ATIHDMI_CAPTURE_INDEX 0
195#define ATIHDMI_NUM_CAPTURE 0
196#define ATIHDMI_PLAYBACK_INDEX 0
197#define ATIHDMI_NUM_PLAYBACK 1
198
07e4ca50
TI
199/* this number is statically defined for simplicity */
200#define MAX_AZX_DEV 16
201
1da177e4 202/* max number of fragments - we may use more if allocating more pages for BDL */
07e4ca50
TI
203#define BDL_SIZE PAGE_ALIGN(8192)
204#define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
1da177e4
LT
205/* max buffer size - no h/w limit, you can increase as you like */
206#define AZX_MAX_BUF_SIZE (1024*1024*1024)
207/* max number of PCM devics per card */
ec9e1c5c
TI
208#define AZX_MAX_AUDIO_PCMS 6
209#define AZX_MAX_MODEM_PCMS 2
210#define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
1da177e4
LT
211
212/* RIRB int mask: overrun[2], response[0] */
213#define RIRB_INT_RESPONSE 0x01
214#define RIRB_INT_OVERRUN 0x04
215#define RIRB_INT_MASK 0x05
216
217/* STATESTS int mask: SD2,SD1,SD0 */
19a982b6 218#define AZX_MAX_CODECS 3
1da177e4 219#define STATESTS_INT_MASK 0x07
1da177e4
LT
220
221/* SD_CTL bits */
222#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
223#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
224#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
225#define SD_CTL_STREAM_TAG_SHIFT 20
226
227/* SD_CTL and SD_STS */
228#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
229#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
230#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI
231#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
232 SD_INT_COMPLETE)
1da177e4
LT
233
234/* SD_STS */
235#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
236
237/* INTCTL and INTSTS */
d01ce99f
TI
238#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
239#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
240#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 241
41e2fce4
M
242/* GCTL unsolicited response enable bit */
243#define ICH6_GCTL_UREN (1<<8)
244
1da177e4
LT
245/* GCTL reset bit */
246#define ICH6_GCTL_RESET (1<<0)
247
248/* CORB/RIRB control, read/write pointer */
249#define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
250#define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
251#define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
252/* below are so far hardcoded - should read registers in future */
253#define ICH6_MAX_CORB_ENTRIES 256
254#define ICH6_MAX_RIRB_ENTRIES 256
255
c74db86b
TI
256/* position fix mode */
257enum {
0be3b5d3 258 POS_FIX_AUTO,
c74db86b 259 POS_FIX_NONE,
0be3b5d3
TI
260 POS_FIX_POSBUF,
261 POS_FIX_FIFO,
c74db86b 262};
1da177e4 263
f5d40b30 264/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL
265#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
266#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
267
da3fca21
V
268/* Defines for Nvidia HDA support */
269#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
270#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
f5d40b30 271
1da177e4
LT
272/*
273 */
274
a98f90fd 275struct azx_dev {
d01ce99f
TI
276 u32 *bdl; /* virtual address of the BDL */
277 dma_addr_t bdl_addr; /* physical address of the BDL */
278 u32 *posbuf; /* position buffer pointer */
1da177e4 279
d01ce99f
TI
280 unsigned int bufsize; /* size of the play buffer in bytes */
281 unsigned int fragsize; /* size of each period in bytes */
282 unsigned int frags; /* number for period in the play buffer */
283 unsigned int fifo_size; /* FIFO size */
1da177e4 284
d01ce99f 285 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 286
d01ce99f 287 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT
288
289 /* pcm support */
d01ce99f
TI
290 struct snd_pcm_substream *substream; /* assigned substream,
291 * set in PCM open
292 */
293 unsigned int format_val; /* format value to be set in the
294 * controller and the codec
295 */
1da177e4
LT
296 unsigned char stream_tag; /* assigned stream */
297 unsigned char index; /* stream index */
1a56f8d6
TI
298 /* for sanity check of position buffer */
299 unsigned int period_intr;
1da177e4 300
927fc866
PM
301 unsigned int opened :1;
302 unsigned int running :1;
1da177e4
LT
303};
304
305/* CORB/RIRB */
a98f90fd 306struct azx_rb {
1da177e4
LT
307 u32 *buf; /* CORB/RIRB buffer
308 * Each CORB entry is 4byte, RIRB is 8byte
309 */
310 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
311 /* for RIRB */
312 unsigned short rp, wp; /* read/write pointers */
313 int cmds; /* number of pending requests */
314 u32 res; /* last read value */
315};
316
a98f90fd
TI
317struct azx {
318 struct snd_card *card;
1da177e4
LT
319 struct pci_dev *pci;
320
07e4ca50
TI
321 /* chip type specific */
322 int driver_type;
323 int playback_streams;
324 int playback_index_offset;
325 int capture_streams;
326 int capture_index_offset;
327 int num_streams;
328
1da177e4
LT
329 /* pci resources */
330 unsigned long addr;
331 void __iomem *remap_addr;
332 int irq;
333
334 /* locks */
335 spinlock_t reg_lock;
62932df8 336 struct mutex open_mutex;
1da177e4 337
07e4ca50 338 /* streams (x num_streams) */
a98f90fd 339 struct azx_dev *azx_dev;
1da177e4
LT
340
341 /* PCM */
342 unsigned int pcm_devs;
a98f90fd 343 struct snd_pcm *pcm[AZX_MAX_PCMS];
1da177e4
LT
344
345 /* HD codec */
346 unsigned short codec_mask;
347 struct hda_bus *bus;
348
349 /* CORB/RIRB */
a98f90fd
TI
350 struct azx_rb corb;
351 struct azx_rb rirb;
1da177e4
LT
352
353 /* BDL, CORB/RIRB and position buffers */
354 struct snd_dma_buffer bdl;
355 struct snd_dma_buffer rb;
356 struct snd_dma_buffer posbuf;
c74db86b
TI
357
358 /* flags */
359 int position_fix;
cb53c626 360 unsigned int running :1;
927fc866
PM
361 unsigned int initialized :1;
362 unsigned int single_cmd :1;
363 unsigned int polling_mode :1;
68e7fffc 364 unsigned int msi :1;
43bbb6cc
TI
365
366 /* for debugging */
367 unsigned int last_cmd; /* last issued command (to sync) */
1da177e4
LT
368};
369
07e4ca50
TI
370/* driver types */
371enum {
372 AZX_DRIVER_ICH,
373 AZX_DRIVER_ATI,
778b6e1b 374 AZX_DRIVER_ATIHDMI,
07e4ca50
TI
375 AZX_DRIVER_VIA,
376 AZX_DRIVER_SIS,
377 AZX_DRIVER_ULI,
da3fca21 378 AZX_DRIVER_NVIDIA,
07e4ca50
TI
379};
380
381static char *driver_short_names[] __devinitdata = {
382 [AZX_DRIVER_ICH] = "HDA Intel",
383 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 384 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI
385 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
386 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V
387 [AZX_DRIVER_ULI] = "HDA ULI M5461",
388 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
07e4ca50
TI
389};
390
1da177e4
LT
391/*
392 * macros for easy use
393 */
394#define azx_writel(chip,reg,value) \
395 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
396#define azx_readl(chip,reg) \
397 readl((chip)->remap_addr + ICH6_REG_##reg)
398#define azx_writew(chip,reg,value) \
399 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
400#define azx_readw(chip,reg) \
401 readw((chip)->remap_addr + ICH6_REG_##reg)
402#define azx_writeb(chip,reg,value) \
403 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
404#define azx_readb(chip,reg) \
405 readb((chip)->remap_addr + ICH6_REG_##reg)
406
407#define azx_sd_writel(dev,reg,value) \
408 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
409#define azx_sd_readl(dev,reg) \
410 readl((dev)->sd_addr + ICH6_REG_##reg)
411#define azx_sd_writew(dev,reg,value) \
412 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
413#define azx_sd_readw(dev,reg) \
414 readw((dev)->sd_addr + ICH6_REG_##reg)
415#define azx_sd_writeb(dev,reg,value) \
416 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
417#define azx_sd_readb(dev,reg) \
418 readb((dev)->sd_addr + ICH6_REG_##reg)
419
420/* for pcm support */
a98f90fd 421#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4
LT
422
423/* Get the upper 32bit of the given dma_addr_t
424 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
425 */
426#define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
427
68e7fffc 428static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1da177e4
LT
429
430/*
431 * Interface for HD codec
432 */
433
1da177e4
LT
434/*
435 * CORB / RIRB interface
436 */
a98f90fd 437static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT
438{
439 int err;
440
441 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI
442 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
443 snd_dma_pci_data(chip->pci),
1da177e4
LT
444 PAGE_SIZE, &chip->rb);
445 if (err < 0) {
446 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
447 return err;
448 }
449 return 0;
450}
451
a98f90fd 452static void azx_init_cmd_io(struct azx *chip)
1da177e4
LT
453{
454 /* CORB set up */
455 chip->corb.addr = chip->rb.addr;
456 chip->corb.buf = (u32 *)chip->rb.area;
457 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
458 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
459
07e4ca50
TI
460 /* set the corb size to 256 entries (ULI requires explicitly) */
461 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT
462 /* set the corb write pointer to 0 */
463 azx_writew(chip, CORBWP, 0);
464 /* reset the corb hw read pointer */
465 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
466 /* enable corb dma */
467 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
468
469 /* RIRB set up */
470 chip->rirb.addr = chip->rb.addr + 2048;
471 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
472 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
473 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
474
07e4ca50
TI
475 /* set the rirb size to 256 entries (ULI requires explicitly) */
476 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4
LT
477 /* reset the rirb hw write pointer */
478 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
479 /* set N=1, get RIRB response interrupt for new entry */
480 azx_writew(chip, RINTCNT, 1);
481 /* enable rirb dma and response irq */
1da177e4 482 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
1da177e4
LT
483 chip->rirb.rp = chip->rirb.cmds = 0;
484}
485
a98f90fd 486static void azx_free_cmd_io(struct azx *chip)
1da177e4
LT
487{
488 /* disable ringbuffer DMAs */
489 azx_writeb(chip, RIRBCTL, 0);
490 azx_writeb(chip, CORBCTL, 0);
491}
492
493/* send a command */
43bbb6cc 494static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
1da177e4 495{
a98f90fd 496 struct azx *chip = codec->bus->private_data;
1da177e4 497 unsigned int wp;
1da177e4
LT
498
499 /* add command to corb */
500 wp = azx_readb(chip, CORBWP);
501 wp++;
502 wp %= ICH6_MAX_CORB_ENTRIES;
503
504 spin_lock_irq(&chip->reg_lock);
505 chip->rirb.cmds++;
506 chip->corb.buf[wp] = cpu_to_le32(val);
507 azx_writel(chip, CORBWP, wp);
508 spin_unlock_irq(&chip->reg_lock);
509
510 return 0;
511}
512
513#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
514
515/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 516static void azx_update_rirb(struct azx *chip)
1da177e4
LT
517{
518 unsigned int rp, wp;
519 u32 res, res_ex;
520
521 wp = azx_readb(chip, RIRBWP);
522 if (wp == chip->rirb.wp)
523 return;
524 chip->rirb.wp = wp;
525
526 while (chip->rirb.rp != wp) {
527 chip->rirb.rp++;
528 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
529
530 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
531 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
532 res = le32_to_cpu(chip->rirb.buf[rp]);
533 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
534 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
535 else if (chip->rirb.cmds) {
536 chip->rirb.cmds--;
537 chip->rirb.res = res;
538 }
539 }
540}
541
542/* receive a response */
111d3af5 543static unsigned int azx_rirb_get_response(struct hda_codec *codec)
1da177e4 544{
a98f90fd 545 struct azx *chip = codec->bus->private_data;
5c79b1f8 546 unsigned long timeout;
1da177e4 547
5c79b1f8
TI
548 again:
549 timeout = jiffies + msecs_to_jiffies(1000);
550 do {
e96224ae
TI
551 if (chip->polling_mode) {
552 spin_lock_irq(&chip->reg_lock);
553 azx_update_rirb(chip);
554 spin_unlock_irq(&chip->reg_lock);
555 }
d01ce99f 556 if (!chip->rirb.cmds)
5c79b1f8 557 return chip->rirb.res; /* the last value */
e65365de 558 schedule_timeout(1);
5c79b1f8
TI
559 } while (time_after_eq(timeout, jiffies));
560
68e7fffc
TI
561 if (chip->msi) {
562 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
43bbb6cc 563 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
68e7fffc
TI
564 free_irq(chip->irq, chip);
565 chip->irq = -1;
566 pci_disable_msi(chip->pci);
567 chip->msi = 0;
568 if (azx_acquire_irq(chip, 1) < 0)
569 return -1;
570 goto again;
571 }
572
5c79b1f8
TI
573 if (!chip->polling_mode) {
574 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
43bbb6cc
TI
575 "switching to polling mode: last cmd=0x%08x\n",
576 chip->last_cmd);
5c79b1f8
TI
577 chip->polling_mode = 1;
578 goto again;
1da177e4 579 }
5c79b1f8
TI
580
581 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
43bbb6cc
TI
582 "switching to single_cmd mode: last cmd=0x%08x\n",
583 chip->last_cmd);
5c79b1f8
TI
584 chip->rirb.rp = azx_readb(chip, RIRBWP);
585 chip->rirb.cmds = 0;
586 /* switch to single_cmd mode */
587 chip->single_cmd = 1;
588 azx_free_cmd_io(chip);
589 return -1;
1da177e4
LT
590}
591
1da177e4
LT
592/*
593 * Use the single immediate command instead of CORB/RIRB for simplicity
594 *
595 * Note: according to Intel, this is not preferred use. The command was
596 * intended for the BIOS only, and may get confused with unsolicited
597 * responses. So, we shouldn't use it for normal operation from the
598 * driver.
599 * I left the codes, however, for debugging/testing purposes.
600 */
601
1da177e4 602/* send a command */
43bbb6cc 603static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
1da177e4 604{
a98f90fd 605 struct azx *chip = codec->bus->private_data;
1da177e4
LT
606 int timeout = 50;
607
1da177e4
LT
608 while (timeout--) {
609 /* check ICB busy bit */
d01ce99f 610 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 611 /* Clear IRV valid bit */
d01ce99f
TI
612 azx_writew(chip, IRS, azx_readw(chip, IRS) |
613 ICH6_IRS_VALID);
1da177e4 614 azx_writel(chip, IC, val);
d01ce99f
TI
615 azx_writew(chip, IRS, azx_readw(chip, IRS) |
616 ICH6_IRS_BUSY);
1da177e4
LT
617 return 0;
618 }
619 udelay(1);
620 }
d01ce99f
TI
621 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
622 azx_readw(chip, IRS), val);
1da177e4
LT
623 return -EIO;
624}
625
626/* receive a response */
27346166 627static unsigned int azx_single_get_response(struct hda_codec *codec)
1da177e4 628{
a98f90fd 629 struct azx *chip = codec->bus->private_data;
1da177e4
LT
630 int timeout = 50;
631
632 while (timeout--) {
633 /* check IRV busy bit */
634 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
635 return azx_readl(chip, IR);
636 udelay(1);
637 }
d01ce99f
TI
638 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
639 azx_readw(chip, IRS));
1da177e4
LT
640 return (unsigned int)-1;
641}
642
111d3af5
TI
643/*
644 * The below are the main callbacks from hda_codec.
645 *
646 * They are just the skeleton to call sub-callbacks according to the
647 * current setting of chip->single_cmd.
648 */
649
650/* send a command */
651static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
652 int direct, unsigned int verb,
653 unsigned int para)
654{
655 struct azx *chip = codec->bus->private_data;
43bbb6cc
TI
656 u32 val;
657
658 val = (u32)(codec->addr & 0x0f) << 28;
659 val |= (u32)direct << 27;
660 val |= (u32)nid << 20;
661 val |= verb << 8;
662 val |= para;
663 chip->last_cmd = val;
664
111d3af5 665 if (chip->single_cmd)
43bbb6cc 666 return azx_single_send_cmd(codec, val);
111d3af5 667 else
43bbb6cc 668 return azx_corb_send_cmd(codec, val);
111d3af5
TI
669}
670
671/* get a response */
672static unsigned int azx_get_response(struct hda_codec *codec)
673{
674 struct azx *chip = codec->bus->private_data;
675 if (chip->single_cmd)
676 return azx_single_get_response(codec);
677 else
678 return azx_rirb_get_response(codec);
679}
680
cb53c626
TI
681#ifdef CONFIG_SND_HDA_POWER_SAVE
682static void azx_power_notify(struct hda_codec *codec);
683#endif
111d3af5 684
1da177e4 685/* reset codec link */
a98f90fd 686static int azx_reset(struct azx *chip)
1da177e4
LT
687{
688 int count;
689
690 /* reset controller */
691 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
692
693 count = 50;
694 while (azx_readb(chip, GCTL) && --count)
695 msleep(1);
696
697 /* delay for >= 100us for codec PLL to settle per spec
698 * Rev 0.9 section 5.5.1
699 */
700 msleep(1);
701
702 /* Bring controller out of reset */
703 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
704
705 count = 50;
927fc866 706 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT
707 msleep(1);
708
927fc866 709 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT
710 msleep(1);
711
712 /* check to see if controller is ready */
927fc866 713 if (!azx_readb(chip, GCTL)) {
1da177e4
LT
714 snd_printd("azx_reset: controller not ready!\n");
715 return -EBUSY;
716 }
717
41e2fce4
M
718 /* Accept unsolicited responses */
719 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
720
1da177e4 721 /* detect codecs */
927fc866 722 if (!chip->codec_mask) {
1da177e4
LT
723 chip->codec_mask = azx_readw(chip, STATESTS);
724 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
725 }
726
727 return 0;
728}
729
730
731/*
732 * Lowlevel interface
733 */
734
735/* enable interrupts */
a98f90fd 736static void azx_int_enable(struct azx *chip)
1da177e4
LT
737{
738 /* enable controller CIE and GIE */
739 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
740 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
741}
742
743/* disable interrupts */
a98f90fd 744static void azx_int_disable(struct azx *chip)
1da177e4
LT
745{
746 int i;
747
748 /* disable interrupts in stream descriptor */
07e4ca50 749 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 750 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT
751 azx_sd_writeb(azx_dev, SD_CTL,
752 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
753 }
754
755 /* disable SIE for all streams */
756 azx_writeb(chip, INTCTL, 0);
757
758 /* disable controller CIE and GIE */
759 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
760 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
761}
762
763/* clear interrupts */
a98f90fd 764static void azx_int_clear(struct azx *chip)
1da177e4
LT
765{
766 int i;
767
768 /* clear stream status */
07e4ca50 769 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 770 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT
771 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
772 }
773
774 /* clear STATESTS */
775 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
776
777 /* clear rirb status */
778 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
779
780 /* clear int status */
781 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
782}
783
784/* start a stream */
a98f90fd 785static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT
786{
787 /* enable SIE */
788 azx_writeb(chip, INTCTL,
789 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
790 /* set DMA start and interrupt mask */
791 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
792 SD_CTL_DMA_START | SD_INT_MASK);
793}
794
795/* stop a stream */
a98f90fd 796static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT
797{
798 /* stop DMA */
799 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
800 ~(SD_CTL_DMA_START | SD_INT_MASK));
801 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
802 /* disable SIE */
803 azx_writeb(chip, INTCTL,
804 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
805}
806
807
808/*
cb53c626 809 * reset and start the controller registers
1da177e4 810 */
a98f90fd 811static void azx_init_chip(struct azx *chip)
1da177e4 812{
cb53c626
TI
813 if (chip->initialized)
814 return;
1da177e4
LT
815
816 /* reset controller */
817 azx_reset(chip);
818
819 /* initialize interrupts */
820 azx_int_clear(chip);
821 azx_int_enable(chip);
822
823 /* initialize the codec command I/O */
927fc866 824 if (!chip->single_cmd)
27346166 825 azx_init_cmd_io(chip);
1da177e4 826
0be3b5d3
TI
827 /* program the position buffer */
828 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
829 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
f5d40b30 830
cb53c626
TI
831 chip->initialized = 1;
832}
833
834/*
835 * initialize the PCI registers
836 */
837/* update bits in a PCI register byte */
838static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
839 unsigned char mask, unsigned char val)
840{
841 unsigned char data;
842
843 pci_read_config_byte(pci, reg, &data);
844 data &= ~mask;
845 data |= (val & mask);
846 pci_write_config_byte(pci, reg, data);
847}
848
849static void azx_init_pci(struct azx *chip)
850{
851 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
852 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
853 * Ensuring these bits are 0 clears playback static on some HD Audio
854 * codecs
855 */
856 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
857
da3fca21
V
858 switch (chip->driver_type) {
859 case AZX_DRIVER_ATI:
860 /* For ATI SB450 azalia HD audio, we need to enable snoop */
cb53c626
TI
861 update_pci_byte(chip->pci,
862 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
863 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
da3fca21
V
864 break;
865 case AZX_DRIVER_NVIDIA:
866 /* For NVIDIA HDA, enable snoop */
cb53c626
TI
867 update_pci_byte(chip->pci,
868 NVIDIA_HDA_TRANSREG_ADDR,
869 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
da3fca21
V
870 break;
871 }
1da177e4
LT
872}
873
874
875/*
876 * interrupt handler
877 */
7d12e780 878static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 879{
a98f90fd
TI
880 struct azx *chip = dev_id;
881 struct azx_dev *azx_dev;
1da177e4
LT
882 u32 status;
883 int i;
884
885 spin_lock(&chip->reg_lock);
886
887 status = azx_readl(chip, INTSTS);
888 if (status == 0) {
889 spin_unlock(&chip->reg_lock);
890 return IRQ_NONE;
891 }
892
07e4ca50 893 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT
894 azx_dev = &chip->azx_dev[i];
895 if (status & azx_dev->sd_int_sta_mask) {
896 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
897 if (azx_dev->substream && azx_dev->running) {
1a56f8d6 898 azx_dev->period_intr++;
1da177e4
LT
899 spin_unlock(&chip->reg_lock);
900 snd_pcm_period_elapsed(azx_dev->substream);
901 spin_lock(&chip->reg_lock);
902 }
903 }
904 }
905
906 /* clear rirb int */
907 status = azx_readb(chip, RIRBSTS);
908 if (status & RIRB_INT_MASK) {
d01ce99f 909 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
1da177e4
LT
910 azx_update_rirb(chip);
911 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
912 }
913
914#if 0
915 /* clear state status int */
916 if (azx_readb(chip, STATESTS) & 0x04)
917 azx_writeb(chip, STATESTS, 0x04);
918#endif
919 spin_unlock(&chip->reg_lock);
920
921 return IRQ_HANDLED;
922}
923
924
925/*
926 * set up BDL entries
927 */
a98f90fd 928static void azx_setup_periods(struct azx_dev *azx_dev)
1da177e4
LT
929{
930 u32 *bdl = azx_dev->bdl;
931 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
932 int idx;
933
934 /* reset BDL address */
935 azx_sd_writel(azx_dev, SD_BDLPL, 0);
936 azx_sd_writel(azx_dev, SD_BDLPU, 0);
937
938 /* program the initial BDL entries */
939 for (idx = 0; idx < azx_dev->frags; idx++) {
940 unsigned int off = idx << 2; /* 4 dword step */
941 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
942 /* program the address field of the BDL entry */
943 bdl[off] = cpu_to_le32((u32)addr);
944 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
945
946 /* program the size field of the BDL entry */
947 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
948
949 /* program the IOC to enable interrupt when buffer completes */
950 bdl[off+3] = cpu_to_le32(0x01);
951 }
952}
953
954/*
955 * set up the SD for streaming
956 */
a98f90fd 957static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT
958{
959 unsigned char val;
960 int timeout;
961
962 /* make sure the run bit is zero for SD */
d01ce99f
TI
963 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
964 ~SD_CTL_DMA_START);
1da177e4 965 /* reset stream */
d01ce99f
TI
966 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
967 SD_CTL_STREAM_RESET);
1da177e4
LT
968 udelay(3);
969 timeout = 300;
970 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
971 --timeout)
972 ;
973 val &= ~SD_CTL_STREAM_RESET;
974 azx_sd_writeb(azx_dev, SD_CTL, val);
975 udelay(3);
976
977 timeout = 300;
978 /* waiting for hardware to report that the stream is out of reset */
979 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
980 --timeout)
981 ;
982
983 /* program the stream_tag */
984 azx_sd_writel(azx_dev, SD_CTL,
d01ce99f 985 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1da177e4
LT
986 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
987
988 /* program the length of samples in cyclic buffer */
989 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
990
991 /* program the stream format */
992 /* this value needs to be the same as the one programmed */
993 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
994
995 /* program the stream LVI (last valid index) of the BDL */
996 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
997
998 /* program the BDL address */
999 /* lower BDL address */
1000 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
1001 /* upper BDL address */
1002 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
1003
0be3b5d3 1004 /* enable the position buffer */
d01ce99f
TI
1005 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1006 azx_writel(chip, DPLBASE,
1007 (u32)chip->posbuf.addr |ICH6_DPLBASE_ENABLE);
c74db86b 1008
1da177e4 1009 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI
1010 azx_sd_writel(azx_dev, SD_CTL,
1011 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT
1012
1013 return 0;
1014}
1015
1016
1017/*
1018 * Codec initialization
1019 */
1020
a9995a35
TI
1021static unsigned int azx_max_codecs[] __devinitdata = {
1022 [AZX_DRIVER_ICH] = 3,
1023 [AZX_DRIVER_ATI] = 4,
1024 [AZX_DRIVER_ATIHDMI] = 4,
1025 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1026 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1027 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1028 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1029};
1030
a98f90fd 1031static int __devinit azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT
1032{
1033 struct hda_bus_template bus_temp;
bccad14e 1034 int c, codecs, audio_codecs, err;
1da177e4
LT
1035
1036 memset(&bus_temp, 0, sizeof(bus_temp));
1037 bus_temp.private_data = chip;
1038 bus_temp.modelname = model;
1039 bus_temp.pci = chip->pci;
111d3af5
TI
1040 bus_temp.ops.command = azx_send_cmd;
1041 bus_temp.ops.get_response = azx_get_response;
cb53c626
TI
1042#ifdef CONFIG_SND_HDA_POWER_SAVE
1043 bus_temp.ops.pm_notify = azx_power_notify;
1044#endif
1da177e4 1045
d01ce99f
TI
1046 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1047 if (err < 0)
1da177e4
LT
1048 return err;
1049
bccad14e 1050 codecs = audio_codecs = 0;
19a982b6 1051 for (c = 0; c < AZX_MAX_CODECS; c++) {
606ad75f 1052 if ((chip->codec_mask & (1 << c)) & probe_mask) {
bccad14e
TI
1053 struct hda_codec *codec;
1054 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT
1055 if (err < 0)
1056 continue;
1057 codecs++;
bccad14e
TI
1058 if (codec->afg)
1059 audio_codecs++;
1da177e4
LT
1060 }
1061 }
bccad14e 1062 if (!audio_codecs) {
19a982b6
TI
1063 /* probe additional slots if no codec is found */
1064 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1065 if ((chip->codec_mask & (1 << c)) & probe_mask) {
1066 err = snd_hda_codec_new(chip->bus, c, NULL);
1067 if (err < 0)
1068 continue;
1069 codecs++;
1070 }
1071 }
1072 }
1073 if (!codecs) {
1da177e4
LT
1074 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1075 return -ENXIO;
1076 }
1077
1078 return 0;
1079}
1080
1081
1082/*
1083 * PCM support
1084 */
1085
1086/* assign a stream for the PCM */
a98f90fd 1087static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1da177e4 1088{
07e4ca50
TI
1089 int dev, i, nums;
1090 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1091 dev = chip->playback_index_offset;
1092 nums = chip->playback_streams;
1093 } else {
1094 dev = chip->capture_index_offset;
1095 nums = chip->capture_streams;
1096 }
1097 for (i = 0; i < nums; i++, dev++)
d01ce99f 1098 if (!chip->azx_dev[dev].opened) {
1da177e4
LT
1099 chip->azx_dev[dev].opened = 1;
1100 return &chip->azx_dev[dev];
1101 }
1102 return NULL;
1103}
1104
1105/* release the assigned stream */
a98f90fd 1106static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT
1107{
1108 azx_dev->opened = 0;
1109}
1110
a98f90fd 1111static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI
1112 .info = (SNDRV_PCM_INFO_MMAP |
1113 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT
1114 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1115 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM
1116 /* No full-resume yet implemented */
1117 /* SNDRV_PCM_INFO_RESUME |*/
1118 SNDRV_PCM_INFO_PAUSE),
1da177e4
LT
1119 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1120 .rates = SNDRV_PCM_RATE_48000,
1121 .rate_min = 48000,
1122 .rate_max = 48000,
1123 .channels_min = 2,
1124 .channels_max = 2,
1125 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1126 .period_bytes_min = 128,
1127 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1128 .periods_min = 2,
1129 .periods_max = AZX_MAX_FRAG,
1130 .fifo_size = 0,
1131};
1132
1133struct azx_pcm {
a98f90fd 1134 struct azx *chip;
1da177e4
LT
1135 struct hda_codec *codec;
1136 struct hda_pcm_stream *hinfo[2];
1137};
1138
a98f90fd 1139static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT
1140{
1141 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1142 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI
1143 struct azx *chip = apcm->chip;
1144 struct azx_dev *azx_dev;
1145 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT
1146 unsigned long flags;
1147 int err;
1148
62932df8 1149 mutex_lock(&chip->open_mutex);
1da177e4
LT
1150 azx_dev = azx_assign_device(chip, substream->stream);
1151 if (azx_dev == NULL) {
62932df8 1152 mutex_unlock(&chip->open_mutex);
1da177e4
LT
1153 return -EBUSY;
1154 }
1155 runtime->hw = azx_pcm_hw;
1156 runtime->hw.channels_min = hinfo->channels_min;
1157 runtime->hw.channels_max = hinfo->channels_max;
1158 runtime->hw.formats = hinfo->formats;
1159 runtime->hw.rates = hinfo->rates;
1160 snd_pcm_limit_hw_rates(runtime);
1161 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5f1545bc
JD
1162 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1163 128);
1164 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1165 128);
cb53c626 1166 snd_hda_power_up(apcm->codec);
d01ce99f
TI
1167 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1168 if (err < 0) {
1da177e4 1169 azx_release_device(azx_dev);
cb53c626 1170 snd_hda_power_down(apcm->codec);
62932df8 1171 mutex_unlock(&chip->open_mutex);
1da177e4
LT
1172 return err;
1173 }
1174 spin_lock_irqsave(&chip->reg_lock, flags);
1175 azx_dev->substream = substream;
1176 azx_dev->running = 0;
1177 spin_unlock_irqrestore(&chip->reg_lock, flags);
1178
1179 runtime->private_data = azx_dev;
62932df8 1180 mutex_unlock(&chip->open_mutex);
1da177e4
LT
1181 return 0;
1182}
1183
a98f90fd 1184static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT
1185{
1186 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1187 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI
1188 struct azx *chip = apcm->chip;
1189 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT
1190 unsigned long flags;
1191
62932df8 1192 mutex_lock(&chip->open_mutex);
1da177e4
LT
1193 spin_lock_irqsave(&chip->reg_lock, flags);
1194 azx_dev->substream = NULL;
1195 azx_dev->running = 0;
1196 spin_unlock_irqrestore(&chip->reg_lock, flags);
1197 azx_release_device(azx_dev);
1198 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1199 snd_hda_power_down(apcm->codec);
62932df8 1200 mutex_unlock(&chip->open_mutex);
1da177e4
LT
1201 return 0;
1202}
1203
d01ce99f
TI
1204static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1205 struct snd_pcm_hw_params *hw_params)
1da177e4 1206{
d01ce99f
TI
1207 return snd_pcm_lib_malloc_pages(substream,
1208 params_buffer_bytes(hw_params));
1da177e4
LT
1209}
1210
a98f90fd 1211static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT
1212{
1213 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1214 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT
1215 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1216
1217 /* reset BDL address */
1218 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1219 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1220 azx_sd_writel(azx_dev, SD_CTL, 0);
1221
1222 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1223
1224 return snd_pcm_lib_free_pages(substream);
1225}
1226
a98f90fd 1227static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT
1228{
1229 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI
1230 struct azx *chip = apcm->chip;
1231 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1232 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1233 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT
1234
1235 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1236 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1237 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1238 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1239 runtime->channels,
1240 runtime->format,
1241 hinfo->maxbps);
d01ce99f
TI
1242 if (!azx_dev->format_val) {
1243 snd_printk(KERN_ERR SFX
1244 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT
1245 runtime->rate, runtime->channels, runtime->format);
1246 return -EINVAL;
1247 }
1248
d01ce99f
TI
1249 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, "
1250 "format=0x%x\n",
1da177e4
LT
1251 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1252 azx_setup_periods(azx_dev);
1253 azx_setup_controller(chip, azx_dev);
1254 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1255 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1256 else
1257 azx_dev->fifo_size = 0;
1258
1259 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1260 azx_dev->format_val, substream);
1261}
1262
a98f90fd 1263static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT
1264{
1265 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI
1266 struct azx_dev *azx_dev = get_azx_dev(substream);
1267 struct azx *chip = apcm->chip;
1da177e4
LT
1268 int err = 0;
1269
1270 spin_lock(&chip->reg_lock);
1271 switch (cmd) {
1272 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1273 case SNDRV_PCM_TRIGGER_RESUME:
1274 case SNDRV_PCM_TRIGGER_START:
1275 azx_stream_start(chip, azx_dev);
1276 azx_dev->running = 1;
1277 break;
1278 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1279 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT
1280 case SNDRV_PCM_TRIGGER_STOP:
1281 azx_stream_stop(chip, azx_dev);
1282 azx_dev->running = 0;
1283 break;
1284 default:
1285 err = -EINVAL;
1286 }
1287 spin_unlock(&chip->reg_lock);
1288 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
47123197 1289 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1da177e4
LT
1290 cmd == SNDRV_PCM_TRIGGER_STOP) {
1291 int timeout = 5000;
d01ce99f
TI
1292 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1293 --timeout)
1da177e4
LT
1294 ;
1295 }
1296 return err;
1297}
1298
a98f90fd 1299static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 1300{
c74db86b 1301 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI
1302 struct azx *chip = apcm->chip;
1303 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT
1304 unsigned int pos;
1305
1a56f8d6
TI
1306 if (chip->position_fix == POS_FIX_POSBUF ||
1307 chip->position_fix == POS_FIX_AUTO) {
c74db86b 1308 /* use the position buffer */
929861c6 1309 pos = le32_to_cpu(*azx_dev->posbuf);
1a56f8d6 1310 if (chip->position_fix == POS_FIX_AUTO &&
d01ce99f 1311 azx_dev->period_intr == 1 && !pos) {
1a56f8d6
TI
1312 printk(KERN_WARNING
1313 "hda-intel: Invalid position buffer, "
1314 "using LPIB read method instead.\n");
1315 chip->position_fix = POS_FIX_NONE;
1316 goto read_lpib;
1317 }
c74db86b 1318 } else {
1a56f8d6 1319 read_lpib:
c74db86b
TI
1320 /* read LPIB */
1321 pos = azx_sd_readl(azx_dev, SD_LPIB);
1322 if (chip->position_fix == POS_FIX_FIFO)
1323 pos += azx_dev->fifo_size;
1324 }
1da177e4
LT
1325 if (pos >= azx_dev->bufsize)
1326 pos = 0;
1327 return bytes_to_frames(substream->runtime, pos);
1328}
1329
a98f90fd 1330static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT
1331 .open = azx_pcm_open,
1332 .close = azx_pcm_close,
1333 .ioctl = snd_pcm_lib_ioctl,
1334 .hw_params = azx_pcm_hw_params,
1335 .hw_free = azx_pcm_hw_free,
1336 .prepare = azx_pcm_prepare,
1337 .trigger = azx_pcm_trigger,
1338 .pointer = azx_pcm_pointer,
1339};
1340
a98f90fd 1341static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4
LT
1342{
1343 kfree(pcm->private_data);
1344}
1345
a98f90fd 1346static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1da177e4
LT
1347 struct hda_pcm *cpcm, int pcm_dev)
1348{
1349 int err;
a98f90fd 1350 struct snd_pcm *pcm;
1da177e4
LT
1351 struct azx_pcm *apcm;
1352
e08a007d
TI
1353 /* if no substreams are defined for both playback and capture,
1354 * it's just a placeholder. ignore it.
1355 */
1356 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1357 return 0;
1358
1da177e4
LT
1359 snd_assert(cpcm->name, return -EINVAL);
1360
1361 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
d01ce99f
TI
1362 cpcm->stream[0].substreams,
1363 cpcm->stream[1].substreams,
1da177e4
LT
1364 &pcm);
1365 if (err < 0)
1366 return err;
1367 strcpy(pcm->name, cpcm->name);
1368 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1369 if (apcm == NULL)
1370 return -ENOMEM;
1371 apcm->chip = chip;
1372 apcm->codec = codec;
1373 apcm->hinfo[0] = &cpcm->stream[0];
1374 apcm->hinfo[1] = &cpcm->stream[1];
1375 pcm->private_data = apcm;
1376 pcm->private_free = azx_pcm_free;
1377 if (cpcm->stream[0].substreams)
1378 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1379 if (cpcm->stream[1].substreams)
1380 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1381 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1382 snd_dma_pci_data(chip->pci),
b66b3cfe 1383 1024 * 64, 1024 * 1024);
1da177e4 1384 chip->pcm[pcm_dev] = pcm;
e08a007d
TI
1385 if (chip->pcm_devs < pcm_dev + 1)
1386 chip->pcm_devs = pcm_dev + 1;
1da177e4
LT
1387
1388 return 0;
1389}
1390
a98f90fd 1391static int __devinit azx_pcm_create(struct azx *chip)
1da177e4
LT
1392{
1393 struct list_head *p;
1394 struct hda_codec *codec;
1395 int c, err;
1396 int pcm_dev;
1397
d01ce99f
TI
1398 err = snd_hda_build_pcms(chip->bus);
1399 if (err < 0)
1da177e4
LT
1400 return err;
1401
ec9e1c5c 1402 /* create audio PCMs */
1da177e4
LT
1403 pcm_dev = 0;
1404 list_for_each(p, &chip->bus->codec_list) {
1405 codec = list_entry(p, struct hda_codec, list);
1406 for (c = 0; c < codec->num_pcms; c++) {
ec9e1c5c
TI
1407 if (codec->pcm_info[c].is_modem)
1408 continue; /* create later */
1409 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
d01ce99f
TI
1410 snd_printk(KERN_ERR SFX
1411 "Too many audio PCMs\n");
ec9e1c5c
TI
1412 return -EINVAL;
1413 }
d01ce99f
TI
1414 err = create_codec_pcm(chip, codec,
1415 &codec->pcm_info[c], pcm_dev);
ec9e1c5c
TI
1416 if (err < 0)
1417 return err;
1418 pcm_dev++;
1419 }
1420 }
1421
1422 /* create modem PCMs */
1423 pcm_dev = AZX_MAX_AUDIO_PCMS;
1424 list_for_each(p, &chip->bus->codec_list) {
1425 codec = list_entry(p, struct hda_codec, list);
1426 for (c = 0; c < codec->num_pcms; c++) {
d01ce99f 1427 if (!codec->pcm_info[c].is_modem)
ec9e1c5c 1428 continue; /* already created */
a28f1cda 1429 if (pcm_dev >= AZX_MAX_PCMS) {
d01ce99f
TI
1430 snd_printk(KERN_ERR SFX
1431 "Too many modem PCMs\n");
1da177e4
LT
1432 return -EINVAL;
1433 }
d01ce99f
TI
1434 err = create_codec_pcm(chip, codec,
1435 &codec->pcm_info[c], pcm_dev);
1da177e4
LT
1436 if (err < 0)
1437 return err;
6632d198 1438 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1da177e4
LT
1439 pcm_dev++;
1440 }
1441 }
1442 return 0;
1443}
1444
1445/*
1446 * mixer creation - all stuff is implemented in hda module
1447 */
a98f90fd 1448static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT
1449{
1450 return snd_hda_build_controls(chip->bus);
1451}
1452
1453
1454/*
1455 * initialize SD streams
1456 */
a98f90fd 1457static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT
1458{
1459 int i;
1460
1461 /* initialize each stream (aka device)
d01ce99f
TI
1462 * assign the starting bdl address to each stream (device)
1463 * and initialize
1da177e4 1464 */
07e4ca50 1465 for (i = 0; i < chip->num_streams; i++) {
1da177e4 1466 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
a98f90fd 1467 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT
1468 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1469 azx_dev->bdl_addr = chip->bdl.addr + off;
929861c6 1470 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT
1471 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1472 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1473 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1474 azx_dev->sd_int_sta_mask = 1 << i;
1475 /* stream tag: must be non-zero and unique */
1476 azx_dev->index = i;
1477 azx_dev->stream_tag = i + 1;
1478 }
1479
1480 return 0;
1481}
1482
68e7fffc
TI
1483static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1484{
437a5a46
TI
1485 if (request_irq(chip->pci->irq, azx_interrupt,
1486 chip->msi ? 0 : IRQF_SHARED,
68e7fffc
TI
1487 "HDA Intel", chip)) {
1488 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1489 "disabling device\n", chip->pci->irq);
1490 if (do_disconnect)
1491 snd_card_disconnect(chip->card);
1492 return -1;
1493 }
1494 chip->irq = chip->pci->irq;
69e13418 1495 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI
1496 return 0;
1497}
1498
1da177e4 1499
cb53c626
TI
1500static void azx_stop_chip(struct azx *chip)
1501{
95e99fda 1502 if (!chip->initialized)
cb53c626
TI
1503 return;
1504
1505 /* disable interrupts */
1506 azx_int_disable(chip);
1507 azx_int_clear(chip);
1508
1509 /* disable CORB/RIRB */
1510 azx_free_cmd_io(chip);
1511
1512 /* disable position buffer */
1513 azx_writel(chip, DPLBASE, 0);
1514 azx_writel(chip, DPUBASE, 0);
1515
1516 chip->initialized = 0;
1517}
1518
1519#ifdef CONFIG_SND_HDA_POWER_SAVE
1520/* power-up/down the controller */
1521static void azx_power_notify(struct hda_codec *codec)
1522{
1523 struct azx *chip = codec->bus->private_data;
1524 struct hda_codec *c;
1525 int power_on = 0;
1526
1527 list_for_each_entry(c, &codec->bus->codec_list, list) {
1528 if (c->power_on) {
1529 power_on = 1;
1530 break;
1531 }
1532 }
1533 if (power_on)
1534 azx_init_chip(chip);
dee1b66c 1535 else if (chip->running && power_save_controller)
cb53c626 1536 azx_stop_chip(chip);
cb53c626
TI
1537}
1538#endif /* CONFIG_SND_HDA_POWER_SAVE */
1539
1da177e4
LT
1540#ifdef CONFIG_PM
1541/*
1542 * power management
1543 */
421a1252 1544static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 1545{
421a1252
TI
1546 struct snd_card *card = pci_get_drvdata(pci);
1547 struct azx *chip = card->private_data;
1da177e4
LT
1548 int i;
1549
421a1252 1550 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1da177e4 1551 for (i = 0; i < chip->pcm_devs; i++)
421a1252 1552 snd_pcm_suspend_all(chip->pcm[i]);
0b7a2e9c
TI
1553 if (chip->initialized)
1554 snd_hda_suspend(chip->bus, state);
cb53c626 1555 azx_stop_chip(chip);
30b35399
TI
1556 if (chip->irq >= 0) {
1557 synchronize_irq(chip->irq);
43001c95 1558 free_irq(chip->irq, chip);
30b35399
TI
1559 chip->irq = -1;
1560 }
68e7fffc 1561 if (chip->msi)
43001c95 1562 pci_disable_msi(chip->pci);
421a1252
TI
1563 pci_disable_device(pci);
1564 pci_save_state(pci);
30b35399 1565 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT
1566 return 0;
1567}
1568
421a1252 1569static int azx_resume(struct pci_dev *pci)
1da177e4 1570{
421a1252
TI
1571 struct snd_card *card = pci_get_drvdata(pci);
1572 struct azx *chip = card->private_data;
1da177e4 1573
30b35399 1574 pci_set_power_state(pci, PCI_D0);
421a1252 1575 pci_restore_state(pci);
30b35399
TI
1576 if (pci_enable_device(pci) < 0) {
1577 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1578 "disabling device\n");
1579 snd_card_disconnect(card);
1580 return -EIO;
1581 }
1582 pci_set_master(pci);
68e7fffc
TI
1583 if (chip->msi)
1584 if (pci_enable_msi(pci) < 0)
1585 chip->msi = 0;
1586 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1587 return -EIO;
cb53c626
TI
1588 azx_init_pci(chip);
1589#ifndef CONFIG_SND_HDA_POWER_SAVE
1590 /* the explicit resume is needed only when POWER_SAVE isn't set */
1da177e4
LT
1591 azx_init_chip(chip);
1592 snd_hda_resume(chip->bus);
cb53c626 1593#endif
421a1252 1594 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT
1595 return 0;
1596}
1597#endif /* CONFIG_PM */
1598
1599
1600/*
1601 * destructor
1602 */
a98f90fd 1603static int azx_free(struct azx *chip)
1da177e4 1604{
ce43fbae 1605 if (chip->initialized) {
1da177e4 1606 int i;
07e4ca50 1607 for (i = 0; i < chip->num_streams; i++)
1da177e4 1608 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 1609 azx_stop_chip(chip);
1da177e4
LT
1610 }
1611
7376d013 1612 if (chip->irq >= 0) {
30b35399 1613 synchronize_irq(chip->irq);
1da177e4 1614 free_irq(chip->irq, (void*)chip);
7376d013 1615 }
68e7fffc 1616 if (chip->msi)
30b35399 1617 pci_disable_msi(chip->pci);
f079c25a
TI
1618 if (chip->remap_addr)
1619 iounmap(chip->remap_addr);
1da177e4
LT
1620
1621 if (chip->bdl.area)
1622 snd_dma_free_pages(&chip->bdl);
1623 if (chip->rb.area)
1624 snd_dma_free_pages(&chip->rb);
1da177e4
LT
1625 if (chip->posbuf.area)
1626 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT
1627 pci_release_regions(chip->pci);
1628 pci_disable_device(chip->pci);
07e4ca50 1629 kfree(chip->azx_dev);
1da177e4
LT
1630 kfree(chip);
1631
1632 return 0;
1633}
1634
a98f90fd 1635static int azx_dev_free(struct snd_device *device)
1da177e4
LT
1636{
1637 return azx_free(device->device_data);
1638}
1639
3372a153
TI
1640/*
1641 * white/black-listing for position_fix
1642 */
623ec047 1643static struct snd_pci_quirk position_fix_list[] __devinitdata = {
3372a153 1644 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
0cb65f22 1645 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
3372a153
TI
1646 {}
1647};
1648
1649static int __devinit check_position_fix(struct azx *chip, int fix)
1650{
1651 const struct snd_pci_quirk *q;
1652
1653 if (fix == POS_FIX_AUTO) {
1654 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1655 if (q) {
1656 snd_printdd(KERN_INFO
1657 "hda_intel: position_fix set to %d "
1658 "for device %04x:%04x\n",
1659 q->value, q->subvendor, q->subdevice);
1660 return q->value;
1661 }
1662 }
1663 return fix;
1664}
1665
1da177e4
LT
1666/*
1667 * constructor
1668 */
a98f90fd 1669static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
606ad75f 1670 int driver_type,
a98f90fd 1671 struct azx **rchip)
1da177e4 1672{
a98f90fd 1673 struct azx *chip;
927fc866 1674 int err;
a98f90fd 1675 static struct snd_device_ops ops = {
1da177e4
LT
1676 .dev_free = azx_dev_free,
1677 };
1678
1679 *rchip = NULL;
1680
927fc866
PM
1681 err = pci_enable_device(pci);
1682 if (err < 0)
1da177e4
LT
1683 return err;
1684
e560d8d8 1685 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 1686 if (!chip) {
1da177e4
LT
1687 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1688 pci_disable_device(pci);
1689 return -ENOMEM;
1690 }
1691
1692 spin_lock_init(&chip->reg_lock);
62932df8 1693 mutex_init(&chip->open_mutex);
1da177e4
LT
1694 chip->card = card;
1695 chip->pci = pci;
1696 chip->irq = -1;
07e4ca50 1697 chip->driver_type = driver_type;
134a11f0 1698 chip->msi = enable_msi;
1da177e4 1699
3372a153
TI
1700 chip->position_fix = check_position_fix(chip, position_fix);
1701
27346166 1702 chip->single_cmd = single_cmd;
c74db86b 1703
07e4ca50
TI
1704#if BITS_PER_LONG != 64
1705 /* Fix up base address on ULI M5461 */
1706 if (chip->driver_type == AZX_DRIVER_ULI) {
1707 u16 tmp3;
1708 pci_read_config_word(pci, 0x40, &tmp3);
1709 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1710 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1711 }
1712#endif
1713
927fc866
PM
1714 err = pci_request_regions(pci, "ICH HD audio");
1715 if (err < 0) {
1da177e4
LT
1716 kfree(chip);
1717 pci_disable_device(pci);
1718 return err;
1719 }
1720
927fc866 1721 chip->addr = pci_resource_start(pci, 0);
1da177e4
LT
1722 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1723 if (chip->remap_addr == NULL) {
1724 snd_printk(KERN_ERR SFX "ioremap error\n");
1725 err = -ENXIO;
1726 goto errout;
1727 }
1728
68e7fffc
TI
1729 if (chip->msi)
1730 if (pci_enable_msi(pci) < 0)
1731 chip->msi = 0;
7376d013 1732
68e7fffc 1733 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT
1734 err = -EBUSY;
1735 goto errout;
1736 }
1da177e4
LT
1737
1738 pci_set_master(pci);
1739 synchronize_irq(chip->irq);
1740
07e4ca50
TI
1741 switch (chip->driver_type) {
1742 case AZX_DRIVER_ULI:
1743 chip->playback_streams = ULI_NUM_PLAYBACK;
1744 chip->capture_streams = ULI_NUM_CAPTURE;
1745 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1746 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1747 break;
778b6e1b
FK
1748 case AZX_DRIVER_ATIHDMI:
1749 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1750 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1751 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1752 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1753 break;
07e4ca50
TI
1754 default:
1755 chip->playback_streams = ICH6_NUM_PLAYBACK;
1756 chip->capture_streams = ICH6_NUM_CAPTURE;
1757 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1758 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1759 break;
1760 }
1761 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI
1762 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1763 GFP_KERNEL);
927fc866 1764 if (!chip->azx_dev) {
07e4ca50
TI
1765 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1766 goto errout;
1767 }
1768
1da177e4 1769 /* allocate memory for the BDL for each stream */
d01ce99f
TI
1770 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1771 snd_dma_pci_data(chip->pci),
1772 BDL_SIZE, &chip->bdl);
1773 if (err < 0) {
1da177e4
LT
1774 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1775 goto errout;
1776 }
0be3b5d3 1777 /* allocate memory for the position buffer */
d01ce99f
TI
1778 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1779 snd_dma_pci_data(chip->pci),
1780 chip->num_streams * 8, &chip->posbuf);
1781 if (err < 0) {
0be3b5d3
TI
1782 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1783 goto errout;
1da177e4 1784 }
1da177e4 1785 /* allocate CORB/RIRB */
d01ce99f
TI
1786 if (!chip->single_cmd) {
1787 err = azx_alloc_cmd_io(chip);
1788 if (err < 0)
27346166 1789 goto errout;
d01ce99f 1790 }
1da177e4
LT
1791
1792 /* initialize streams */
1793 azx_init_stream(chip);
1794
1795 /* initialize chip */
cb53c626 1796 azx_init_pci(chip);
1da177e4
LT
1797 azx_init_chip(chip);
1798
1799 /* codec detection */
927fc866 1800 if (!chip->codec_mask) {
1da177e4
LT
1801 snd_printk(KERN_ERR SFX "no codecs found!\n");
1802 err = -ENODEV;
1803 goto errout;
1804 }
1805
d01ce99f
TI
1806 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1807 if (err <0) {
1da177e4
LT
1808 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1809 goto errout;
1810 }
1811
07e4ca50
TI
1812 strcpy(card->driver, "HDA-Intel");
1813 strcpy(card->shortname, driver_short_names[chip->driver_type]);
d01ce99f
TI
1814 sprintf(card->longname, "%s at 0x%lx irq %i",
1815 card->shortname, chip->addr, chip->irq);
07e4ca50 1816
1da177e4
LT
1817 *rchip = chip;
1818 return 0;
1819
1820 errout:
1821 azx_free(chip);
1822 return err;
1823}
1824
cb53c626
TI
1825static void power_down_all_codecs(struct azx *chip)
1826{
1827#ifdef CONFIG_SND_HDA_POWER_SAVE
1828 /* The codecs were powered up in snd_hda_codec_new().
1829 * Now all initialization done, so turn them down if possible
1830 */
1831 struct hda_codec *codec;
1832 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1833 snd_hda_power_down(codec);
1834 }
1835#endif
1836}
1837
d01ce99f
TI
1838static int __devinit azx_probe(struct pci_dev *pci,
1839 const struct pci_device_id *pci_id)
1da177e4 1840{
a98f90fd
TI
1841 struct snd_card *card;
1842 struct azx *chip;
927fc866 1843 int err;
1da177e4 1844
b7fe4622 1845 card = snd_card_new(index, id, THIS_MODULE, 0);
927fc866 1846 if (!card) {
1da177e4
LT
1847 snd_printk(KERN_ERR SFX "Error creating card!\n");
1848 return -ENOMEM;
1849 }
1850
927fc866
PM
1851 err = azx_create(card, pci, pci_id->driver_data, &chip);
1852 if (err < 0) {
1da177e4
LT
1853 snd_card_free(card);
1854 return err;
1855 }
421a1252 1856 card->private_data = chip;
1da177e4 1857
1da177e4 1858 /* create codec instances */
d01ce99f
TI
1859 err = azx_codec_create(chip, model);
1860 if (err < 0) {
1da177e4
LT
1861 snd_card_free(card);
1862 return err;
1863 }
1864
1865 /* create PCM streams */
d01ce99f
TI
1866 err = azx_pcm_create(chip);
1867 if (err < 0) {
1da177e4
LT
1868 snd_card_free(card);
1869 return err;
1870 }
1871
1872 /* create mixer controls */
d01ce99f
TI
1873 err = azx_mixer_create(chip);
1874 if (err < 0) {
1da177e4
LT
1875 snd_card_free(card);
1876 return err;
1877 }
1878
1da177e4
LT
1879 snd_card_set_dev(card, &pci->dev);
1880
d01ce99f
TI
1881 err = snd_card_register(card);
1882 if (err < 0) {
1da177e4
LT
1883 snd_card_free(card);
1884 return err;
1885 }
1886
1887 pci_set_drvdata(pci, card);
cb53c626
TI
1888 chip->running = 1;
1889 power_down_all_codecs(chip);
1da177e4
LT
1890
1891 return err;
1892}
1893
1894static void __devexit azx_remove(struct pci_dev *pci)
1895{
1896 snd_card_free(pci_get_drvdata(pci));
1897 pci_set_drvdata(pci, NULL);
1898}
1899
1900/* PCI IDs */
f40b6890 1901static struct pci_device_id azx_ids[] = {
07e4ca50
TI
1902 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1903 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1904 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
d2981393 1905 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
f9cc8a8b
JG
1906 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1907 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
07e4ca50 1908 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
89be83f8 1909 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
778b6e1b 1910 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
5b15c95f 1911 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
e6db1119
WL
1912 { 0x1002, 0x960c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
1913 { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
07e4ca50
TI
1914 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1915 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1916 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
5b005a01
PC
1917 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
1918 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
1919 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1920 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1921 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1922 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1923 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1924 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
15cc4458
PC
1925 { 0x10de, 0x07fc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
1926 { 0x10de, 0x07fd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
1927 { 0x10de, 0x0774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1928 { 0x10de, 0x0775, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1929 { 0x10de, 0x0776, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1930 { 0x10de, 0x0777, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1da177e4
LT
1931 { 0, }
1932};
1933MODULE_DEVICE_TABLE(pci, azx_ids);
1934
1935/* pci_driver definition */
1936static struct pci_driver driver = {
1937 .name = "HDA Intel",
1938 .id_table = azx_ids,
1939 .probe = azx_probe,
1940 .remove = __devexit_p(azx_remove),
421a1252
TI
1941#ifdef CONFIG_PM
1942 .suspend = azx_suspend,
1943 .resume = azx_resume,
1944#endif
1da177e4
LT
1945};
1946
1947static int __init alsa_card_azx_init(void)
1948{
01d25d46 1949 return pci_register_driver(&driver);
1da177e4
LT
1950}
1951
1952static void __exit alsa_card_azx_exit(void)
1953{
1954 pci_unregister_driver(&driver);
1955}
1956
1957module_init(alsa_card_azx_init)
1958module_exit(alsa_card_azx_exit)