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ALSA: hda - Disable widget power-save for VIA codecs
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
98d8fc6c
ML		 60#include <sound/hdaudio.h>
61#include <sound/hda_i915.h>
9121947d 62#include <linux/vgaarb.h>
a82d51ed 63#include <linux/vga_switcheroo.h>
4918cdab 64#include <linux/firmware.h>
1da177e4 65#include "hda_codec.h"
05e84878 66#include "hda_controller.h"
347de1f8 67#include "hda_intel.h"
1da177e4 68
785d8c4b
LY		 69#define CREATE_TRACE_POINTS
70#include "hda_intel_trace.h"
71
b6050ef6
TI		 72/* position fix mode */
73enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79};
80
9a34af4a
TI		 81/* Defines for ATI HD Audio support in SB450 south bridge */
82#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85/* Defines for Nvidia HDA support */
86#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88#define NVIDIA_HDA_ISTRM_COH 0x4d
89#define NVIDIA_HDA_OSTRM_COH 0x4c
90#define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92/* Defines for Intel SCH HDA snoop control */
93#define INTEL_SCH_HDA_DEVC 0x78
94#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
95
96/* Define IN stream 0 FIFO size offset in VIA controller */
97#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
98/* Define VIA HD Audio Device ID*/
99#define VIA_HDAC_DEVICE_ID 0x3288
100
33124929
TI		 101/* max number of SDs */
102/* ICH, ATI and VIA have 4 playback and 4 capture */
103#define ICH6_NUM_CAPTURE 4
104#define ICH6_NUM_PLAYBACK 4
105
106/* ULI has 6 playback and 5 capture */
107#define ULI_NUM_CAPTURE 5
108#define ULI_NUM_PLAYBACK 6
109
110/* ATI HDMI may have up to 8 playbacks and 0 capture */
111#define ATIHDMI_NUM_CAPTURE 0
112#define ATIHDMI_NUM_PLAYBACK 8
113
114/* TERA has 4 playback and 3 capture */
115#define TERA_NUM_CAPTURE 3
116#define TERA_NUM_PLAYBACK 4
117
1da177e4 118
5aba4f8e
TI		 119static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
120static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 121static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 122static char *model[SNDRV_CARDS];
1dac6695 123static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 124static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 125static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 126static int probe_only[SNDRV_CARDS];
26a6cb6c 127static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 128static bool single_cmd;
71623855 129static int enable_msi = -1;
4ea6fbc8
TI		 130#ifdef CONFIG_SND_HDA_PATCH_LOADER
131static char *patch[SNDRV_CARDS];
132#endif
2dca0bba 133#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 134static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 135 CONFIG_SND_HDA_INPUT_BEEP_MODE};
136#endif
1da177e4 137
5aba4f8e 138module_param_array(index, int, NULL, 0444);
1da177e4 139MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 140module_param_array(id, charp, NULL, 0444);
1da177e4 141MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 142module_param_array(enable, bool, NULL, 0444);
143MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
144module_param_array(model, charp, NULL, 0444);
1da177e4 145MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 146module_param_array(position_fix, int, NULL, 0444);
4cb36310 147MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 148 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 149module_param_array(bdl_pos_adj, int, NULL, 0644);
150MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 151module_param_array(probe_mask, int, NULL, 0444);
606ad75f 152MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 153module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 154MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 155module_param_array(jackpoll_ms, int, NULL, 0444);
156MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 157module_param(single_cmd, bool, 0444);
d01ce99f
TI		 158MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
159 "(for debugging only).");
ac9ef6cf 160module_param(enable_msi, bint, 0444);
134a11f0 161MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 162#ifdef CONFIG_SND_HDA_PATCH_LOADER
163module_param_array(patch, charp, NULL, 0444);
164MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
165#endif
2dca0bba 166#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 167module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 168MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 169 "(0=off, 1=on) (default=1).");
2dca0bba 170#endif
606ad75f 171
83012a7c 172#ifdef CONFIG_PM
65fcd41d
TI		 173static int param_set_xint(const char *val, const struct kernel_param *kp);
174static struct kernel_param_ops param_ops_xint = {
175 .set = param_set_xint,
176 .get = param_get_int,
177};
178#define param_check_xint param_check_int
179
fee2fba3 180static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 181module_param(power_save, xint, 0644);
fee2fba3
TI		 182MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
183 "(in second, 0 = disable).");
1da177e4 184
dee1b66c
TI		 185/* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
8fc24426
TI		 189static bool power_save_controller = 1;
190module_param(power_save_controller, bool, 0644);
dee1b66c 191MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 192#else
bb573928 193#define power_save 0
83012a7c 194#endif /* CONFIG_PM */
dee1b66c 195
7bfe059e
TI		 196static int align_buffer_size = -1;
197module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 198MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
27fe48d9 201#ifdef CONFIG_X86
7c732015
TI		 202static int hda_snoop = -1;
203module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 204MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 205#else
206#define hda_snoop true
27fe48d9
TI		 207#endif
208
209
1da177e4
LT		 210MODULE_LICENSE("GPL");
211MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212 "{Intel, ICH6M},"
2f1b3818 213 "{Intel, ICH7},"
f5d40b30 214 "{Intel, ESB2},"
d2981393 215 "{Intel, ICH8},"
f9cc8a8b 216 "{Intel, ICH9},"
c34f5a04 217 "{Intel, ICH10},"
b29c2360 218 "{Intel, PCH},"
d2f2fcd2 219 "{Intel, CPT},"
d2edeb7c 220 "{Intel, PPT},"
8bc039a1 221 "{Intel, LPT},"
144dad99 222 "{Intel, LPT_LP},"
4eeca499 223 "{Intel, WPT_LP},"
c8b00fd2 224 "{Intel, SPT},"
b4565913 225 "{Intel, SPT_LP},"
e926f2c8 226 "{Intel, HPT},"
cea310e8 227 "{Intel, PBG},"
4979bca9 228 "{Intel, SCH},"
fc20a562 229 "{ATI, SB450},"
89be83f8 230 "{ATI, SB600},"
778b6e1b 231 "{ATI, RS600},"
5b15c95f 232 "{ATI, RS690},"
e6db1119
WL		 233 "{ATI, RS780},"
234 "{ATI, R600},"
2797f724
HRK		 235 "{ATI, RV630},"
236 "{ATI, RV610},"
27da1834
WL		 237 "{ATI, RV670},"
238 "{ATI, RV635},"
239 "{ATI, RV620},"
240 "{ATI, RV770},"
fc20a562 241 "{VIA, VT8251},"
47672310 242 "{VIA, VT8237A},"
07e4ca50
TI		 243 "{SiS, SIS966},"
244 "{ULI, M5461}}");
1da177e4
LT		 245MODULE_DESCRIPTION("Intel HDA driver");
246
a82d51ed 247#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 248#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 249#define SUPPORT_VGA_SWITCHEROO
250#endif
251#endif
252
253
1da177e4 254/*
1da177e4 255 */
1da177e4 256
07e4ca50
TI		 257/* driver types */
258enum {
259 AZX_DRIVER_ICH,
32679f95 260 AZX_DRIVER_PCH,
4979bca9 261 AZX_DRIVER_SCH,
fab1285a 262 AZX_DRIVER_HDMI,
07e4ca50 263 AZX_DRIVER_ATI,
778b6e1b 264 AZX_DRIVER_ATIHDMI,
1815b34a 265 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 266 AZX_DRIVER_VIA,
267 AZX_DRIVER_SIS,
268 AZX_DRIVER_ULI,
da3fca21 269 AZX_DRIVER_NVIDIA,
f269002e 270 AZX_DRIVER_TERA,
14d34f16 271 AZX_DRIVER_CTX,
5ae763b1 272 AZX_DRIVER_CTHDA,
c563f473 273 AZX_DRIVER_CMEDIA,
c4da29ca 274 AZX_DRIVER_GENERIC,
2f5983f2 275 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 276};
277
37e661ee
TI		 278#define azx_get_snoop_type(chip) \
279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
280#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
281
b42b4afb
TI		 282/* quirks for old Intel chipsets */
283#define AZX_DCAPS_INTEL_ICH \
103884a3 284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 285
2ea3c6a2 286/* quirks for Intel PCH */
d7dab4db 287#define AZX_DCAPS_INTEL_PCH_NOPM \
103884a3 288 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee 289 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db
TI		 290
291#define AZX_DCAPS_INTEL_PCH \
292 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 293
33499a15 294#define AZX_DCAPS_INTEL_HASWELL \
103884a3 295 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 296 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
297 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 298
54a0405d
LY		 299/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
300#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 301 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 302 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
303 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 304
40cc2392
ML		 305#define AZX_DCAPS_INTEL_BAYTRAIL \
306 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
307
2d846c74
LY		 308#define AZX_DCAPS_INTEL_BRASWELL \
309 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
310
d6795827 311#define AZX_DCAPS_INTEL_SKYLAKE \
2d846c74
LY		 312 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
313 AZX_DCAPS_I915_POWERWELL)
d6795827 314
9477c58e
TI		 315/* quirks for ATI SB / AMD Hudson */
316#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 317 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
318 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 319
320/* quirks for ATI/AMD HDMI */
321#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 322 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
323 AZX_DCAPS_NO_MSI64)
9477c58e 324
37e661ee
TI		 325/* quirks for ATI HDMI with snoop off */
326#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
327 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
328
9477c58e
TI		 329/* quirks for Nvidia */
330#define AZX_DCAPS_PRESET_NVIDIA \
103884a3 331 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
37e661ee
TI		 332 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
333 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 334
5ae763b1 335#define AZX_DCAPS_PRESET_CTHDA \
37e661ee
TI		 336 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
337 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 338
a82d51ed
TI		 339/*
340 * VGA-switcher support
341 */
342#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 343#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
344#else
345#define use_vga_switcheroo(chip) 0
346#endif
347
03b135ce
LY		 348#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
349 ((pci)->device == 0x0c0c) || \
350 ((pci)->device == 0x0d0c) || \
351 ((pci)->device == 0x160c))
352
48c8b0eb 353static char *driver_short_names[] = {
07e4ca50 354 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 355 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 356 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 357 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 358 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 359 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 360 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 361 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
362 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 363 [AZX_DRIVER_ULI] = "HDA ULI M5461",
364 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 365 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 366 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 367 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 368 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 369 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 370};
371
27fe48d9 372#ifdef CONFIG_X86
9ddf1aeb 373static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 374{
9ddf1aeb
TI		 375 int pages;
376
27fe48d9
TI		 377 if (azx_snoop(chip))
378 return;
9ddf1aeb
TI		 379 if (!dmab || !dmab->area || !dmab->bytes)
380 return;
381
382#ifdef CONFIG_SND_DMA_SGBUF
383 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
384 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 385 if (chip->driver_type == AZX_DRIVER_CMEDIA)
386 return; /* deal with only CORB/RIRB buffers */
27fe48d9 387 if (on)
9ddf1aeb 388 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 389 else
9ddf1aeb
TI		 390 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
391 return;
27fe48d9 392 }
9ddf1aeb
TI		 393#endif
394
395 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
396 if (on)
397 set_memory_wc((unsigned long)dmab->area, pages);
398 else
399 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 400}
401
402static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
403 bool on)
404{
9ddf1aeb 405 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 406}
407static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 408 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 409{
410 if (azx_dev->wc_marked != on) {
9ddf1aeb 411 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 412 azx_dev->wc_marked = on;
413 }
414}
415#else
416/* NOP for other archs */
417static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
418 bool on)
419{
420}
421static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 422 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 423{
424}
425#endif
426
68e7fffc 427static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 428
cb53c626
TI		 429/*
430 * initialize the PCI registers
431 */
432/* update bits in a PCI register byte */
433static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
434 unsigned char mask, unsigned char val)
435{
436 unsigned char data;
437
438 pci_read_config_byte(pci, reg, &data);
439 data &= ~mask;
440 data |= (val & mask);
441 pci_write_config_byte(pci, reg, data);
442}
443
444static void azx_init_pci(struct azx *chip)
445{
37e661ee
TI		 446 int snoop_type = azx_get_snoop_type(chip);
447
cb53c626
TI		 448 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
449 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
450 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 451 * codecs.
452 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 453 */
46f2cc80 454 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 455 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 456 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 457 }
cb53c626 458
9477c58e
TI		 459 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
460 * we need to enable snoop.
461 */
37e661ee 462 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 463 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
464 azx_snoop(chip));
cb53c626 465 update_pci_byte(chip->pci,
27fe48d9
TI		 466 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
467 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 468 }
469
470 /* For NVIDIA HDA, enable snoop */
37e661ee 471 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 472 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
473 azx_snoop(chip));
cb53c626
TI		 474 update_pci_byte(chip->pci,
475 NVIDIA_HDA_TRANSREG_ADDR,
476 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 477 update_pci_byte(chip->pci,
478 NVIDIA_HDA_ISTRM_COH,
479 0x01, NVIDIA_HDA_ENABLE_COHBIT);
480 update_pci_byte(chip->pci,
481 NVIDIA_HDA_OSTRM_COH,
482 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 483 }
484
485 /* Enable SCH/PCH snoop if needed */
37e661ee 486 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 487 unsigned short snoop;
90a5ad52 488 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 489 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
490 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
491 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
492 if (!azx_snoop(chip))
493 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
494 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 495 pci_read_config_word(chip->pci,
496 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 497 }
4e76a883
TI		 498 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
499 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
500 "Disabled" : "Enabled");
da3fca21 501 }
1da177e4
LT		 502}
503
0a673521
LH		 504static void hda_intel_init_chip(struct azx *chip, bool full_reset)
505{
98d8fc6c 506 struct hdac_bus *bus = azx_bus(chip);
0a673521
LH		 507
508 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 509 snd_hdac_set_codec_wakeup(bus, true);
0a673521
LH		 510 azx_init_chip(chip, full_reset);
511 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 512 snd_hdac_set_codec_wakeup(bus, false);
0a673521
LH		 513}
514
b6050ef6
TI		 515/* calculate runtime delay from LPIB */
516static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
517 unsigned int pos)
518{
7833c3f8 519 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 520 int stream = substream->stream;
521 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
522 int delay;
523
524 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
525 delay = pos - lpib_pos;
526 else
527 delay = lpib_pos - pos;
528 if (delay < 0) {
7833c3f8 529 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 530 delay = 0;
531 else
7833c3f8 532 delay += azx_dev->core.bufsize;
b6050ef6
TI		 533 }
534
7833c3f8 535 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 536 dev_info(chip->card->dev,
537 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 538 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 539 delay = 0;
540 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
541 chip->get_delay[stream] = NULL;
542 }
543
544 return bytes_to_frames(substream->runtime, delay);
545}
546
9ad593f6
TI		 547static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
548
7ca954a8
DR		 549/* called from IRQ */
550static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
551{
9a34af4a 552 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 553 int ok;
554
555 ok = azx_position_ok(chip, azx_dev);
556 if (ok == 1) {
557 azx_dev->irq_pending = 0;
558 return ok;
2f35c630 559 } else if (ok == 0) {
7ca954a8
DR		 560 /* bogus IRQ, process it later */
561 azx_dev->irq_pending = 1;
2f35c630 562 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 563 }
564 return 0;
565}
566
17eccb27
ML		 567/* Enable/disable i915 display power for the link */
568static int azx_intel_link_power(struct azx *chip, bool enable)
569{
98d8fc6c 570 struct hdac_bus *bus = azx_bus(chip);
17eccb27 571
98d8fc6c 572 return snd_hdac_display_power(bus, enable);
17eccb27
ML		 573}
574
9ad593f6
TI		 575/*
576 * Check whether the current DMA position is acceptable for updating
577 * periods. Returns non-zero if it's OK.
578 *
579 * Many HD-audio controllers appear pretty inaccurate about
580 * the update-IRQ timing. The IRQ is issued before actually the
581 * data is processed. So, we need to process it afterwords in a
582 * workqueue.
583 */
584static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
585{
7833c3f8 586 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 587 int stream = substream->stream;
e5463720 588 u32 wallclk;
9ad593f6
TI		 589 unsigned int pos;
590
7833c3f8
TI		 591 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
592 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 593 return -1; /* bogus (too early) interrupt */
fa00e046 594
b6050ef6
TI		 595 if (chip->get_position[stream])
596 pos = chip->get_position[stream](chip, azx_dev);
597 else { /* use the position buffer as default */
598 pos = azx_get_pos_posbuf(chip, azx_dev);
599 if (!pos || pos == (u32)-1) {
600 dev_info(chip->card->dev,
601 "Invalid position buffer, using LPIB read method instead.\n");
602 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 603 if (chip->get_position[0] == azx_get_pos_lpib &&
604 chip->get_position[1] == azx_get_pos_lpib)
605 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 606 pos = azx_get_pos_lpib(chip, azx_dev);
607 chip->get_delay[stream] = NULL;
608 } else {
609 chip->get_position[stream] = azx_get_pos_posbuf;
610 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
611 chip->get_delay[stream] = azx_get_delay_from_lpib;
612 }
613 }
614
7833c3f8 615 if (pos >= azx_dev->core.bufsize)
b6050ef6 616 pos = 0;
9ad593f6 617
7833c3f8 618 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 619 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 620 return -1; /* this shouldn't happen! */
7833c3f8
TI		 621 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
622 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 623 /* NG - it's below the first next period boundary */
9cdc0115 624 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
7833c3f8 625 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 626 return 1; /* OK, it's fine */
627}
628
629/*
630 * The work for pending PCM period updates.
631 */
632static void azx_irq_pending_work(struct work_struct *work)
633{
9a34af4a
TI		 634 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
635 struct azx *chip = &hda->chip;
7833c3f8
TI		 636 struct hdac_bus *bus = azx_bus(chip);
637 struct hdac_stream *s;
638 int pending, ok;
9ad593f6 639
9a34af4a 640 if (!hda->irq_pending_warned) {
4e76a883
TI		 641 dev_info(chip->card->dev,
642 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
643 chip->card->number);
9a34af4a 644 hda->irq_pending_warned = 1;
a6a950a8
TI		 645 }
646
9ad593f6
TI		 647 for (;;) {
648 pending = 0;
a41d1224 649 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 650 list_for_each_entry(s, &bus->stream_list, list) {
651 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 652 if (!azx_dev->irq_pending ||
7833c3f8
TI		 653 !s->substream ||
654 !s->running)
9ad593f6 655 continue;
e5463720
JK		 656 ok = azx_position_ok(chip, azx_dev);
657 if (ok > 0) {
9ad593f6 658 azx_dev->irq_pending = 0;
a41d1224 659 spin_unlock(&bus->reg_lock);
7833c3f8 660 snd_pcm_period_elapsed(s->substream);
a41d1224 661 spin_lock(&bus->reg_lock);
e5463720
JK		 662 } else if (ok < 0) {
663 pending = 0; /* too early */
9ad593f6
TI		 664 } else
665 pending++;
666 }
a41d1224 667 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 668 if (!pending)
669 return;
08af495f 670 msleep(1);
9ad593f6
TI		 671 }
672}
673
674/* clear irq_pending flags and assure no on-going workq */
675static void azx_clear_irq_pending(struct azx *chip)
676{
7833c3f8
TI		 677 struct hdac_bus *bus = azx_bus(chip);
678 struct hdac_stream *s;
9ad593f6 679
a41d1224 680 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 681 list_for_each_entry(s, &bus->stream_list, list) {
682 struct azx_dev *azx_dev = stream_to_azx_dev(s);
683 azx_dev->irq_pending = 0;
684 }
a41d1224 685 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 686}
687
68e7fffc
TI		 688static int azx_acquire_irq(struct azx *chip, int do_disconnect)
689{
a41d1224
TI		 690 struct hdac_bus *bus = azx_bus(chip);
691
437a5a46
TI		 692 if (request_irq(chip->pci->irq, azx_interrupt,
693 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 694 KBUILD_MODNAME, chip)) {
4e76a883
TI		 695 dev_err(chip->card->dev,
696 "unable to grab IRQ %d, disabling device\n",
697 chip->pci->irq);
68e7fffc
TI		 698 if (do_disconnect)
699 snd_card_disconnect(chip->card);
700 return -1;
701 }
a41d1224 702 bus->irq = chip->pci->irq;
69e13418 703 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 704 return 0;
705}
706
b6050ef6
TI		 707/* get the current DMA position with correction on VIA chips */
708static unsigned int azx_via_get_position(struct azx *chip,
709 struct azx_dev *azx_dev)
710{
711 unsigned int link_pos, mini_pos, bound_pos;
712 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
713 unsigned int fifo_size;
714
1604eeee 715 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 716 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 717 /* Playback, no problem using link position */
718 return link_pos;
719 }
720
721 /* Capture */
722 /* For new chipset,
723 * use mod to get the DMA position just like old chipset
724 */
7833c3f8
TI		 725 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
726 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 727
728 /* azx_dev->fifo_size can't get FIFO size of in stream.
729 * Get from base address + offset.
730 */
a41d1224
TI		 731 fifo_size = readw(azx_bus(chip)->remap_addr +
732 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 733
734 if (azx_dev->insufficient) {
735 /* Link position never gather than FIFO size */
736 if (link_pos <= fifo_size)
737 return 0;
738
739 azx_dev->insufficient = 0;
740 }
741
742 if (link_pos <= fifo_size)
7833c3f8 743 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 744 else
745 mini_pos = link_pos - fifo_size;
746
747 /* Find nearest previous boudary */
7833c3f8
TI		 748 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
749 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 750 if (mod_link_pos >= fifo_size)
751 bound_pos = link_pos - mod_link_pos;
752 else if (mod_dma_pos >= mod_mini_pos)
753 bound_pos = mini_pos - mod_mini_pos;
754 else {
7833c3f8
TI		 755 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
756 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 757 bound_pos = 0;
758 }
759
760 /* Calculate real DMA position we want */
761 return bound_pos + mod_dma_pos;
762}
763
83012a7c 764#ifdef CONFIG_PM
65fcd41d
TI		 765static DEFINE_MUTEX(card_list_lock);
766static LIST_HEAD(card_list);
767
768static void azx_add_card_list(struct azx *chip)
769{
9a34af4a 770 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 771 mutex_lock(&card_list_lock);
9a34af4a 772 list_add(&hda->list, &card_list);
65fcd41d
TI		 773 mutex_unlock(&card_list_lock);
774}
775
776static void azx_del_card_list(struct azx *chip)
777{
9a34af4a 778 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 779 mutex_lock(&card_list_lock);
9a34af4a 780 list_del_init(&hda->list);
65fcd41d
TI		 781 mutex_unlock(&card_list_lock);
782}
783
784/* trigger power-save check at writing parameter */
785static int param_set_xint(const char *val, const struct kernel_param *kp)
786{
9a34af4a 787 struct hda_intel *hda;
65fcd41d 788 struct azx *chip;
65fcd41d
TI		 789 int prev = power_save;
790 int ret = param_set_int(val, kp);
791
792 if (ret || prev == power_save)
793 return ret;
794
795 mutex_lock(&card_list_lock);
9a34af4a
TI		 796 list_for_each_entry(hda, &card_list, list) {
797 chip = &hda->chip;
a41d1224 798 if (!hda->probe_continued || chip->disabled)
65fcd41d 799 continue;
a41d1224 800 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 801 }
802 mutex_unlock(&card_list_lock);
803 return 0;
804}
805#else
806#define azx_add_card_list(chip) /* NOP */
807#define azx_del_card_list(chip) /* NOP */
83012a7c 808#endif /* CONFIG_PM */
5c0b9bec 809
98d8fc6c
ML		 810/* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
811 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
812 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
813 * BCLK = CDCLK * M / N
814 * The values will be lost when the display power well is disabled and need to
815 * be restored to avoid abnormal playback speed.
816 */
817static void haswell_set_bclk(struct hda_intel *hda)
818{
819 struct azx *chip = &hda->chip;
820 int cdclk_freq;
821 unsigned int bclk_m, bclk_n;
822
823 if (!hda->need_i915_power)
824 return;
825
826 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
827 switch (cdclk_freq) {
828 case 337500:
829 bclk_m = 16;
830 bclk_n = 225;
831 break;
832
833 case 450000:
834 default: /* default CDCLK 450MHz */
835 bclk_m = 4;
836 bclk_n = 75;
837 break;
838
839 case 540000:
840 bclk_m = 4;
841 bclk_n = 90;
842 break;
843
844 case 675000:
845 bclk_m = 8;
846 bclk_n = 225;
847 break;
848 }
849
850 azx_writew(chip, HSW_EM4, bclk_m);
851 azx_writew(chip, HSW_EM5, bclk_n);
852}
853
7ccbde57 854#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 855/*
856 * power management
857 */
68cb2b55 858static int azx_suspend(struct device *dev)
1da177e4 859{
68cb2b55 860 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 861 struct azx *chip;
862 struct hda_intel *hda;
a41d1224 863 struct hdac_bus *bus;
1da177e4 864
2d9772ef
TI		 865 if (!card)
866 return 0;
867
868 chip = card->private_data;
869 hda = container_of(chip, struct hda_intel, chip);
1618e84a 870 if (chip->disabled || hda->init_failed)
c5c21523
TI		 871 return 0;
872
a41d1224 873 bus = azx_bus(chip);
421a1252 874 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 875 azx_clear_irq_pending(chip);
cb53c626 876 azx_stop_chip(chip);
7295b264 877 azx_enter_link_reset(chip);
a41d1224
TI		 878 if (bus->irq >= 0) {
879 free_irq(bus->irq, chip);
880 bus->irq = -1;
30b35399 881 }
a07187c9 882
68e7fffc 883 if (chip->msi)
43001c95 884 pci_disable_msi(chip->pci);
795614dd
ML		 885 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
886 && hda->need_i915_power)
98d8fc6c 887 snd_hdac_display_power(bus, false);
785d8c4b
LY		 888
889 trace_azx_suspend(chip);
1da177e4
LT		 890 return 0;
891}
892
68cb2b55 893static int azx_resume(struct device *dev)
1da177e4 894{
68cb2b55
TI		 895 struct pci_dev *pci = to_pci_dev(dev);
896 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 897 struct azx *chip;
898 struct hda_intel *hda;
899
900 if (!card)
901 return 0;
1da177e4 902
2d9772ef
TI		 903 chip = card->private_data;
904 hda = container_of(chip, struct hda_intel, chip);
1618e84a 905 if (chip->disabled || hda->init_failed)
c5c21523
TI		 906 return 0;
907
795614dd
ML		 908 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
909 && hda->need_i915_power) {
98d8fc6c 910 snd_hdac_display_power(azx_bus(chip), true);
926981ae 911 haswell_set_bclk(hda);
a07187c9 912 }
68e7fffc
TI		 913 if (chip->msi)
914 if (pci_enable_msi(pci) < 0)
915 chip->msi = 0;
916 if (azx_acquire_irq(chip, 1) < 0)
30b35399 917 return -EIO;
cb53c626 918 azx_init_pci(chip);
d804ad92 919
0a673521 920 hda_intel_init_chip(chip, true);
d804ad92 921
421a1252 922 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 923
924 trace_azx_resume(chip);
1da177e4
LT		 925 return 0;
926}
b8dfc462
ML		 927#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
928
641d334b 929#ifdef CONFIG_PM
b8dfc462
ML		 930static int azx_runtime_suspend(struct device *dev)
931{
932 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 933 struct azx *chip;
934 struct hda_intel *hda;
b8dfc462 935
2d9772ef
TI		 936 if (!card)
937 return 0;
938
939 chip = card->private_data;
940 hda = container_of(chip, struct hda_intel, chip);
1618e84a 941 if (chip->disabled || hda->init_failed)
246efa4a
DA		 942 return 0;
943
364aa716 944 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 945 return 0;
946
7d4f606c
WX		 947 /* enable controller wake up event */
948 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
949 STATESTS_INT_MASK);
950
b8dfc462 951 azx_stop_chip(chip);
873ce8ad 952 azx_enter_link_reset(chip);
b8dfc462 953 azx_clear_irq_pending(chip);
795614dd
ML		 954 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
955 && hda->need_i915_power)
98d8fc6c 956 snd_hdac_display_power(azx_bus(chip), false);
e4d9e513 957
785d8c4b 958 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 959 return 0;
960}
961
962static int azx_runtime_resume(struct device *dev)
963{
964 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 965 struct azx *chip;
966 struct hda_intel *hda;
98d8fc6c 967 struct hdac_bus *bus;
7d4f606c
WX		 968 struct hda_codec *codec;
969 int status;
b8dfc462 970
2d9772ef
TI		 971 if (!card)
972 return 0;
973
974 chip = card->private_data;
975 hda = container_of(chip, struct hda_intel, chip);
1618e84a 976 if (chip->disabled || hda->init_failed)
246efa4a
DA		 977 return 0;
978
364aa716 979 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 980 return 0;
981
795614dd
ML		 982 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
983 && hda->need_i915_power) {
98d8fc6c
ML		 984 bus = azx_bus(chip);
985 snd_hdac_display_power(bus, true);
926981ae 986 haswell_set_bclk(hda);
0a673521 987 /* toggle codec wakeup bit for STATESTS read */
98d8fc6c
ML		 988 snd_hdac_set_codec_wakeup(bus, true);
989 snd_hdac_set_codec_wakeup(bus, false);
a07187c9 990 }
7d4f606c
WX		 991
992 /* Read STATESTS before controller reset */
993 status = azx_readw(chip, STATESTS);
994
b8dfc462 995 azx_init_pci(chip);
0a673521 996 hda_intel_init_chip(chip, true);
7d4f606c 997
a41d1224
TI		 998 if (status) {
999 list_for_each_codec(codec, &chip->bus)
7d4f606c 1000 if (status & (1 << codec->addr))
2f35c630
TI		 1001 schedule_delayed_work(&codec->jackpoll_work,
1002 codec->jackpoll_interval);
7d4f606c
WX		 1003 }
1004
1005 /* disable controller Wake Up event*/
1006 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1007 ~STATESTS_INT_MASK);
1008
785d8c4b 1009 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1010 return 0;
1011}
6eb827d2
TI		 1012
1013static int azx_runtime_idle(struct device *dev)
1014{
1015 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1016 struct azx *chip;
1017 struct hda_intel *hda;
1018
1019 if (!card)
1020 return 0;
6eb827d2 1021
2d9772ef
TI		 1022 chip = card->private_data;
1023 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1024 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1025 return 0;
1026
55ed9cd1 1027 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
a41d1224 1028 azx_bus(chip)->codec_powered)
6eb827d2
TI		 1029 return -EBUSY;
1030
1031 return 0;
1032}
1033
b8dfc462
ML		 1034static const struct dev_pm_ops azx_pm = {
1035 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 1036 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1037};
1038
68cb2b55
TI		 1039#define AZX_PM_OPS &azx_pm
1040#else
68cb2b55 1041#define AZX_PM_OPS NULL
b8dfc462 1042#endif /* CONFIG_PM */
1da177e4
LT		 1043
1044
48c8b0eb 1045static int azx_probe_continue(struct azx *chip);
a82d51ed 1046
8393ec4a 1047#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1048static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1049
a82d51ed
TI		 1050static void azx_vs_set_state(struct pci_dev *pci,
1051 enum vga_switcheroo_state state)
1052{
1053 struct snd_card *card = pci_get_drvdata(pci);
1054 struct azx *chip = card->private_data;
9a34af4a 1055 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1056 bool disabled;
1057
9a34af4a
TI		 1058 wait_for_completion(&hda->probe_wait);
1059 if (hda->init_failed)
a82d51ed
TI		 1060 return;
1061
1062 disabled = (state == VGA_SWITCHEROO_OFF);
1063 if (chip->disabled == disabled)
1064 return;
1065
a41d1224 1066 if (!hda->probe_continued) {
a82d51ed
TI		 1067 chip->disabled = disabled;
1068 if (!disabled) {
4e76a883
TI		 1069 dev_info(chip->card->dev,
1070 "Start delayed initialization\n");
5c90680e 1071 if (azx_probe_continue(chip) < 0) {
4e76a883 1072 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1073 hda->init_failed = true;
a82d51ed
TI		 1074 }
1075 }
1076 } else {
4e76a883
TI		 1077 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1078 disabled ? "Disabling" : "Enabling");
a82d51ed 1079 if (disabled) {
8928756d
DR		 1080 pm_runtime_put_sync_suspend(card->dev);
1081 azx_suspend(card->dev);
246efa4a
DA		 1082 /* when we get suspended by vga switcheroo we end up in D3cold,
1083 * however we have no ACPI handle, so pci/acpi can't put us there,
1084 * put ourselves there */
1085 pci->current_state = PCI_D3cold;
a82d51ed 1086 chip->disabled = true;
a41d1224 1087 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1088 dev_warn(chip->card->dev,
1089 "Cannot lock devices!\n");
a82d51ed 1090 } else {
a41d1224 1091 snd_hda_unlock_devices(&chip->bus);
8928756d 1092 pm_runtime_get_noresume(card->dev);
a82d51ed 1093 chip->disabled = false;
8928756d 1094 azx_resume(card->dev);
a82d51ed
TI		 1095 }
1096 }
1097}
1098
1099static bool azx_vs_can_switch(struct pci_dev *pci)
1100{
1101 struct snd_card *card = pci_get_drvdata(pci);
1102 struct azx *chip = card->private_data;
9a34af4a 1103 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1104
9a34af4a
TI		 1105 wait_for_completion(&hda->probe_wait);
1106 if (hda->init_failed)
a82d51ed 1107 return false;
a41d1224 1108 if (chip->disabled || !hda->probe_continued)
a82d51ed 1109 return true;
a41d1224 1110 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1111 return false;
a41d1224 1112 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1113 return true;
1114}
1115
e23e7a14 1116static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1117{
9a34af4a 1118 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1119 struct pci_dev *p = get_bound_vga(chip->pci);
1120 if (p) {
4e76a883
TI		 1121 dev_info(chip->card->dev,
1122 "Handle VGA-switcheroo audio client\n");
9a34af4a 1123 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1124 pci_dev_put(p);
1125 }
1126}
1127
1128static const struct vga_switcheroo_client_ops azx_vs_ops = {
1129 .set_gpu_state = azx_vs_set_state,
1130 .can_switch = azx_vs_can_switch,
1131};
1132
e23e7a14 1133static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1134{
9a34af4a 1135 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1136 int err;
1137
9a34af4a 1138 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1139 return 0;
1140 /* FIXME: currently only handling DIS controller
1141 * is there any machine with two switchable HDMI audio controllers?
1142 */
128960a9 1143 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed 1144 VGA_SWITCHEROO_DIS,
a41d1224 1145 hda->probe_continued);
128960a9
TI		 1146 if (err < 0)
1147 return err;
9a34af4a 1148 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1149
1150 /* register as an optimus hdmi audio power domain */
8928756d 1151 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1152 &hda->hdmi_pm_domain);
128960a9 1153 return 0;
a82d51ed
TI		 1154}
1155#else
1156#define init_vga_switcheroo(chip) /* NOP */
1157#define register_vga_switcheroo(chip) 0
8393ec4a 1158#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1159#endif /* SUPPORT_VGA_SWITCHER */
1160
1da177e4
LT		 1161/*
1162 * destructor
1163 */
a98f90fd 1164static int azx_free(struct azx *chip)
1da177e4 1165{
c67e2228 1166 struct pci_dev *pci = chip->pci;
a07187c9 1167 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1168 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1169
364aa716 1170 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1171 pm_runtime_get_noresume(&pci->dev);
1172
65fcd41d
TI		 1173 azx_del_card_list(chip);
1174
9a34af4a
TI		 1175 hda->init_failed = 1; /* to be sure */
1176 complete_all(&hda->probe_wait);
f4c482a4 1177
9a34af4a 1178 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1179 if (chip->disabled && hda->probe_continued)
1180 snd_hda_unlock_devices(&chip->bus);
9a34af4a 1181 if (hda->vga_switcheroo_registered)
128960a9 1182 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1183 }
1184
a41d1224 1185 if (bus->chip_init) {
9ad593f6 1186 azx_clear_irq_pending(chip);
7833c3f8 1187 azx_stop_all_streams(chip);
cb53c626 1188 azx_stop_chip(chip);
1da177e4
LT		 1189 }
1190
a41d1224
TI		 1191 if (bus->irq >= 0)
1192 free_irq(bus->irq, (void*)chip);
68e7fffc 1193 if (chip->msi)
30b35399 1194 pci_disable_msi(chip->pci);
a41d1224 1195 iounmap(bus->remap_addr);
1da177e4 1196
67908994 1197 azx_free_stream_pages(chip);
a41d1224
TI		 1198 azx_free_streams(chip);
1199 snd_hdac_bus_exit(bus);
1200
a82d51ed
TI		 1201 if (chip->region_requested)
1202 pci_release_regions(chip->pci);
a41d1224 1203
1da177e4 1204 pci_disable_device(chip->pci);
4918cdab 1205#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1206 release_firmware(chip->fw);
4918cdab 1207#endif
98d8fc6c 1208
99a2008d 1209 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
795614dd 1210 if (hda->need_i915_power)
98d8fc6c
ML		 1211 snd_hdac_display_power(bus, false);
1212 snd_hdac_i915_exit(bus);
99a2008d 1213 }
a07187c9 1214 kfree(hda);
1da177e4
LT		 1215
1216 return 0;
1217}
1218
a41d1224
TI		 1219static int azx_dev_disconnect(struct snd_device *device)
1220{
1221 struct azx *chip = device->device_data;
1222
1223 chip->bus.shutdown = 1;
1224 return 0;
1225}
1226
a98f90fd 1227static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1228{
1229 return azx_free(device->device_data);
1230}
1231
8393ec4a 1232#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 1233/*
1234 * Check of disabled HDMI controller by vga-switcheroo
1235 */
e23e7a14 1236static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1237{
1238 struct pci_dev *p;
1239
1240 /* check only discrete GPU */
1241 switch (pci->vendor) {
1242 case PCI_VENDOR_ID_ATI:
1243 case PCI_VENDOR_ID_AMD:
1244 case PCI_VENDOR_ID_NVIDIA:
1245 if (pci->devfn == 1) {
1246 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1247 pci->bus->number, 0);
1248 if (p) {
1249 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1250 return p;
1251 pci_dev_put(p);
1252 }
1253 }
1254 break;
1255 }
1256 return NULL;
1257}
1258
e23e7a14 1259static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1260{
1261 bool vga_inactive = false;
1262 struct pci_dev *p = get_bound_vga(pci);
1263
1264 if (p) {
12b78a7f 1265 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1266 vga_inactive = true;
1267 pci_dev_put(p);
1268 }
1269 return vga_inactive;
1270}
8393ec4a 1271#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1272
3372a153
TI		 1273/*
1274 * white/black-listing for position_fix
1275 */
e23e7a14 1276static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1277 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1278 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1279 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1280 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1281 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1282 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1283 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1284 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1285 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1286 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1287 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1288 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1289 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1290 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1291 {}
1292};
1293
e23e7a14 1294static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1295{
1296 const struct snd_pci_quirk *q;
1297
c673ba1c 1298 switch (fix) {
1dac6695 1299 case POS_FIX_AUTO:
c673ba1c
TI		 1300 case POS_FIX_LPIB:
1301 case POS_FIX_POSBUF:
4cb36310 1302 case POS_FIX_VIACOMBO:
a6f2fd55 1303 case POS_FIX_COMBO:
c673ba1c
TI		 1304 return fix;
1305 }
1306
c673ba1c
TI		 1307 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1308 if (q) {
4e76a883
TI		 1309 dev_info(chip->card->dev,
1310 "position_fix set to %d for device %04x:%04x\n",
1311 q->value, q->subvendor, q->subdevice);
c673ba1c 1312 return q->value;
3372a153 1313 }
bdd9ef24
DH		 1314
1315 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1316 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1317 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1318 return POS_FIX_VIACOMBO;
9477c58e
TI		 1319 }
1320 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1321 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1322 return POS_FIX_LPIB;
bdd9ef24 1323 }
c673ba1c 1324 return POS_FIX_AUTO;
3372a153
TI		 1325}
1326
b6050ef6
TI		 1327static void assign_position_fix(struct azx *chip, int fix)
1328{
1329 static azx_get_pos_callback_t callbacks[] = {
1330 [POS_FIX_AUTO] = NULL,
1331 [POS_FIX_LPIB] = azx_get_pos_lpib,
1332 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1333 [POS_FIX_VIACOMBO] = azx_via_get_position,
1334 [POS_FIX_COMBO] = azx_get_pos_lpib,
1335 };
1336
1337 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1338
1339 /* combo mode uses LPIB only for playback */
1340 if (fix == POS_FIX_COMBO)
1341 chip->get_position[1] = NULL;
1342
1343 if (fix == POS_FIX_POSBUF &&
1344 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1345 chip->get_delay[0] = chip->get_delay[1] =
1346 azx_get_delay_from_lpib;
1347 }
1348
1349}
1350
669ba27a
TI		 1351/*
1352 * black-lists for probe_mask
1353 */
e23e7a14 1354static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1355 /* Thinkpad often breaks the controller communication when accessing
1356 * to the non-working (or non-existing) modem codec slot.
1357 */
1358 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1359 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1360 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1361 /* broken BIOS */
1362 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1363 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1364 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1365 /* forced codec slots */
93574844 1366 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1367 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1368 /* WinFast VP200 H (Teradici) user reported broken communication */
1369 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1370 {}
1371};
1372
f1eaaeec
TI		 1373#define AZX_FORCE_CODEC_MASK 0x100
1374
e23e7a14 1375static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1376{
1377 const struct snd_pci_quirk *q;
1378
f1eaaeec
TI		 1379 chip->codec_probe_mask = probe_mask[dev];
1380 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1381 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1382 if (q) {
4e76a883
TI		 1383 dev_info(chip->card->dev,
1384 "probe_mask set to 0x%x for device %04x:%04x\n",
1385 q->value, q->subvendor, q->subdevice);
f1eaaeec 1386 chip->codec_probe_mask = q->value;
669ba27a
TI		 1387 }
1388 }
f1eaaeec
TI		 1389
1390 /* check forced option */
1391 if (chip->codec_probe_mask != -1 &&
1392 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1393 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1394 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1395 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1396 }
669ba27a
TI		 1397}
1398
4d8e22e0 1399/*
71623855 1400 * white/black-list for enable_msi
4d8e22e0 1401 */
e23e7a14 1402static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1403 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1404 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1405 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1406 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1407 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1408 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1409 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1410 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1411 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1412 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1413 {}
1414};
1415
e23e7a14 1416static void check_msi(struct azx *chip)
4d8e22e0
TI		 1417{
1418 const struct snd_pci_quirk *q;
1419
71623855
TI		 1420 if (enable_msi >= 0) {
1421 chip->msi = !!enable_msi;
4d8e22e0 1422 return;
71623855
TI		 1423 }
1424 chip->msi = 1; /* enable MSI as default */
1425 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1426 if (q) {
4e76a883
TI		 1427 dev_info(chip->card->dev,
1428 "msi for device %04x:%04x set to %d\n",
1429 q->subvendor, q->subdevice, q->value);
4d8e22e0 1430 chip->msi = q->value;
80c43ed7
TI		 1431 return;
1432 }
1433
1434 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1435 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1436 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1437 chip->msi = 0;
4d8e22e0
TI		 1438 }
1439}
1440
a1585d76 1441/* check the snoop mode availability */
e23e7a14 1442static void azx_check_snoop_available(struct azx *chip)
a1585d76 1443{
7c732015 1444 int snoop = hda_snoop;
a1585d76 1445
7c732015
TI		 1446 if (snoop >= 0) {
1447 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1448 snoop ? "snoop" : "non-snoop");
1449 chip->snoop = snoop;
1450 return;
1451 }
1452
1453 snoop = true;
37e661ee
TI		 1454 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1455 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1456 /* force to non-snoop mode for a new VIA controller
1457 * when BIOS is set
1458 */
7c732015
TI		 1459 u8 val;
1460 pci_read_config_byte(chip->pci, 0x42, &val);
1461 if (!(val & 0x80) && chip->pci->revision == 0x30)
1462 snoop = false;
a1585d76
TI		 1463 }
1464
37e661ee
TI		 1465 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1466 snoop = false;
1467
7c732015
TI		 1468 chip->snoop = snoop;
1469 if (!snoop)
1470 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1471}
669ba27a 1472
99a2008d
WX		 1473static void azx_probe_work(struct work_struct *work)
1474{
9a34af4a
TI		 1475 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1476 azx_probe_continue(&hda->chip);
99a2008d 1477}
99a2008d 1478
1da177e4
LT		 1479/*
1480 * constructor
1481 */
a43ff5ba
TI		 1482static const struct hdac_io_ops pci_hda_io_ops;
1483static const struct hda_controller_ops pci_hda_ops;
1484
e23e7a14
BP		 1485static int azx_create(struct snd_card *card, struct pci_dev *pci,
1486 int dev, unsigned int driver_caps,
1487 struct azx **rchip)
1da177e4 1488{
a98f90fd 1489 static struct snd_device_ops ops = {
a41d1224 1490 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1491 .dev_free = azx_dev_free,
1492 };
a07187c9 1493 struct hda_intel *hda;
a82d51ed
TI		 1494 struct azx *chip;
1495 int err;
1da177e4
LT		 1496
1497 *rchip = NULL;
bcd72003 1498
927fc866
PM		 1499 err = pci_enable_device(pci);
1500 if (err < 0)
1da177e4
LT		 1501 return err;
1502
a07187c9
ML		 1503 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1504 if (!hda) {
1da177e4
LT		 1505 pci_disable_device(pci);
1506 return -ENOMEM;
1507 }
1508
a07187c9 1509 chip = &hda->chip;
62932df8 1510 mutex_init(&chip->open_mutex);
1da177e4
LT		 1511 chip->card = card;
1512 chip->pci = pci;
a43ff5ba 1513 chip->ops = &pci_hda_ops;
9477c58e
TI		 1514 chip->driver_caps = driver_caps;
1515 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1516 check_msi(chip);
555e219f 1517 chip->dev_index = dev;
749ee287 1518 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1519 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1520 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1521 INIT_LIST_HEAD(&hda->list);
a82d51ed 1522 init_vga_switcheroo(chip);
9a34af4a 1523 init_completion(&hda->probe_wait);
1da177e4 1524
b6050ef6 1525 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1526
5aba4f8e 1527 check_probe_mask(chip, dev);
3372a153 1528
27346166 1529 chip->single_cmd = single_cmd;
a1585d76 1530 azx_check_snoop_available(chip);
c74db86b 1531
5c0d7bc1
TI		 1532 if (bdl_pos_adj[dev] < 0) {
1533 switch (chip->driver_type) {
0c6341ac 1534 case AZX_DRIVER_ICH:
32679f95 1535 case AZX_DRIVER_PCH:
0c6341ac 1536 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1537 break;
1538 default:
0c6341ac 1539 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1540 break;
1541 }
1542 }
9cdc0115 1543 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1544
a41d1224
TI		 1545 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1546 if (err < 0) {
1547 kfree(hda);
1548 pci_disable_device(pci);
1549 return err;
1550 }
1551
a82d51ed
TI		 1552 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1553 if (err < 0) {
4e76a883 1554 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1555 azx_free(chip);
1556 return err;
1557 }
1558
99a2008d 1559 /* continue probing in work context as may trigger request module */
9a34af4a 1560 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1561
a82d51ed 1562 *rchip = chip;
99a2008d 1563
a82d51ed
TI		 1564 return 0;
1565}
1566
48c8b0eb 1567static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1568{
1569 int dev = chip->dev_index;
1570 struct pci_dev *pci = chip->pci;
1571 struct snd_card *card = chip->card;
a41d1224 1572 struct hdac_bus *bus = azx_bus(chip);
67908994 1573 int err;
a82d51ed 1574 unsigned short gcap;
413cbf46 1575 unsigned int dma_bits = 64;
a82d51ed 1576
07e4ca50
TI		 1577#if BITS_PER_LONG != 64
1578 /* Fix up base address on ULI M5461 */
1579 if (chip->driver_type == AZX_DRIVER_ULI) {
1580 u16 tmp3;
1581 pci_read_config_word(pci, 0x40, &tmp3);
1582 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1583 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1584 }
1585#endif
1586
927fc866 1587 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1588 if (err < 0)
1da177e4 1589 return err;
a82d51ed 1590 chip->region_requested = 1;
1da177e4 1591
a41d1224
TI		 1592 bus->addr = pci_resource_start(pci, 0);
1593 bus->remap_addr = pci_ioremap_bar(pci, 0);
1594 if (bus->remap_addr == NULL) {
4e76a883 1595 dev_err(card->dev, "ioremap error\n");
a82d51ed 1596 return -ENXIO;
1da177e4
LT		 1597 }
1598
db79afa1
BH		 1599 if (chip->msi) {
1600 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1601 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1602 pci->no_64bit_msi = true;
1603 }
68e7fffc
TI		 1604 if (pci_enable_msi(pci) < 0)
1605 chip->msi = 0;
db79afa1 1606 }
7376d013 1607
a82d51ed
TI		 1608 if (azx_acquire_irq(chip, 0) < 0)
1609 return -EBUSY;
1da177e4
LT		 1610
1611 pci_set_master(pci);
a41d1224 1612 synchronize_irq(bus->irq);
1da177e4 1613
bcd72003 1614 gcap = azx_readw(chip, GCAP);
4e76a883 1615 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1616
413cbf46
TI		 1617 /* AMD devices support 40 or 48bit DMA, take the safe one */
1618 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1619 dma_bits = 40;
1620
dc4c2e6b 1621 /* disable SB600 64bit support for safety */
9477c58e 1622 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1623 struct pci_dev *p_smbus;
413cbf46 1624 dma_bits = 40;
dc4c2e6b
AB		 1625 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1626 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1627 NULL);
1628 if (p_smbus) {
1629 if (p_smbus->revision < 0x30)
fb1d8ac2 1630 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1631 pci_dev_put(p_smbus);
1632 }
1633 }
09240cf4 1634
9477c58e
TI		 1635 /* disable 64bit DMA address on some devices */
1636 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1637 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1638 gcap &= ~AZX_GCAP_64OK;
9477c58e 1639 }
396087ea 1640
2ae66c26 1641 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1642 if (align_buffer_size >= 0)
1643 chip->align_buffer_size = !!align_buffer_size;
1644 else {
103884a3 1645 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1646 chip->align_buffer_size = 0;
7bfe059e
TI		 1647 else
1648 chip->align_buffer_size = 1;
1649 }
2ae66c26 1650
cf7aaca8 1651 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1652 if (!(gcap & AZX_GCAP_64OK))
1653 dma_bits = 32;
412b979c
QL		 1654 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1655 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1656 } else {
412b979c
QL		 1657 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1658 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1659 }
cf7aaca8 1660
8b6ed8e7
TI		 1661 /* read number of streams from GCAP register instead of using
1662 * hardcoded value
1663 */
1664 chip->capture_streams = (gcap >> 8) & 0x0f;
1665 chip->playback_streams = (gcap >> 12) & 0x0f;
1666 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1667 /* gcap didn't give any info, switching to old method */
1668
1669 switch (chip->driver_type) {
1670 case AZX_DRIVER_ULI:
1671 chip->playback_streams = ULI_NUM_PLAYBACK;
1672 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1673 break;
1674 case AZX_DRIVER_ATIHDMI:
1815b34a 1675 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1676 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1677 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1678 break;
c4da29ca 1679 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1680 default:
1681 chip->playback_streams = ICH6_NUM_PLAYBACK;
1682 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1683 break;
1684 }
07e4ca50 1685 }
8b6ed8e7
TI		 1686 chip->capture_index_offset = 0;
1687 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1688 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1689
a41d1224
TI		 1690 /* initialize streams */
1691 err = azx_init_streams(chip);
81740861 1692 if (err < 0)
a82d51ed 1693 return err;
1da177e4 1694
a41d1224
TI		 1695 err = azx_alloc_stream_pages(chip);
1696 if (err < 0)
1697 return err;
1da177e4
LT		 1698
1699 /* initialize chip */
cb53c626 1700 azx_init_pci(chip);
e4d9e513 1701
926981ae
ID		 1702 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1703 struct hda_intel *hda;
1704
1705 hda = container_of(chip, struct hda_intel, chip);
1706 haswell_set_bclk(hda);
1707 }
e4d9e513 1708
0a673521 1709 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1710
1711 /* codec detection */
a41d1224 1712 if (!azx_bus(chip)->codec_mask) {
4e76a883 1713 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1714 return -ENODEV;
1da177e4
LT		 1715 }
1716
07e4ca50 1717 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1718 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1719 sizeof(card->shortname));
1720 snprintf(card->longname, sizeof(card->longname),
1721 "%s at 0x%lx irq %i",
a41d1224 1722 card->shortname, bus->addr, bus->irq);
07e4ca50 1723
1da177e4 1724 return 0;
1da177e4
LT		 1725}
1726
97c6a3d1 1727#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1728/* callback from request_firmware_nowait() */
1729static void azx_firmware_cb(const struct firmware *fw, void *context)
1730{
1731 struct snd_card *card = context;
1732 struct azx *chip = card->private_data;
1733 struct pci_dev *pci = chip->pci;
1734
1735 if (!fw) {
4e76a883 1736 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1737 goto error;
1738 }
1739
1740 chip->fw = fw;
1741 if (!chip->disabled) {
1742 /* continue probing */
1743 if (azx_probe_continue(chip))
1744 goto error;
1745 }
1746 return; /* OK */
1747
1748 error:
1749 snd_card_free(card);
1750 pci_set_drvdata(pci, NULL);
1751}
97c6a3d1 1752#endif
5cb543db 1753
40830813
DR		 1754/*
1755 * HDA controller ops.
1756 */
1757
1758/* PCI register access. */
db291e36 1759static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1760{
1761 writel(value, addr);
1762}
1763
db291e36 1764static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1765{
1766 return readl(addr);
1767}
1768
db291e36 1769static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1770{
1771 writew(value, addr);
1772}
1773
db291e36 1774static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1775{
1776 return readw(addr);
1777}
1778
db291e36 1779static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1780{
1781 writeb(value, addr);
1782}
1783
db291e36 1784static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1785{
1786 return readb(addr);
1787}
1788
f46ea609
DR		 1789static int disable_msi_reset_irq(struct azx *chip)
1790{
a41d1224 1791 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 1792 int err;
1793
a41d1224
TI		 1794 free_irq(bus->irq, chip);
1795 bus->irq = -1;
f46ea609
DR		 1796 pci_disable_msi(chip->pci);
1797 chip->msi = 0;
1798 err = azx_acquire_irq(chip, 1);
1799 if (err < 0)
1800 return err;
1801
1802 return 0;
1803}
1804
b419b35b 1805/* DMA page allocation helpers. */
a43ff5ba 1806static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 1807 int type,
1808 size_t size,
1809 struct snd_dma_buffer *buf)
1810{
a41d1224 1811 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 1812 int err;
1813
1814 err = snd_dma_alloc_pages(type,
a43ff5ba 1815 bus->dev,
b419b35b
DR		 1816 size, buf);
1817 if (err < 0)
1818 return err;
1819 mark_pages_wc(chip, buf, true);
1820 return 0;
1821}
1822
a43ff5ba 1823static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 1824{
a41d1224 1825 struct azx *chip = bus_to_azx(bus);
a43ff5ba 1826
b419b35b
DR		 1827 mark_pages_wc(chip, buf, false);
1828 snd_dma_free_pages(buf);
1829}
1830
1831static int substream_alloc_pages(struct azx *chip,
1832 struct snd_pcm_substream *substream,
1833 size_t size)
1834{
1835 struct azx_dev *azx_dev = get_azx_dev(substream);
1836 int ret;
1837
1838 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 1839 ret = snd_pcm_lib_malloc_pages(substream, size);
1840 if (ret < 0)
1841 return ret;
1842 mark_runtime_wc(chip, azx_dev, substream, true);
1843 return 0;
1844}
1845
1846static int substream_free_pages(struct azx *chip,
1847 struct snd_pcm_substream *substream)
1848{
1849 struct azx_dev *azx_dev = get_azx_dev(substream);
1850 mark_runtime_wc(chip, azx_dev, substream, false);
1851 return snd_pcm_lib_free_pages(substream);
1852}
1853
8769b278
DR		 1854static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1855 struct vm_area_struct *area)
1856{
1857#ifdef CONFIG_X86
1858 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1859 struct azx *chip = apcm->chip;
3b70bdba 1860 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 1861 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1862#endif
1863}
1864
a43ff5ba 1865static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 1866 .reg_writel = pci_azx_writel,
1867 .reg_readl = pci_azx_readl,
1868 .reg_writew = pci_azx_writew,
1869 .reg_readw = pci_azx_readw,
1870 .reg_writeb = pci_azx_writeb,
1871 .reg_readb = pci_azx_readb,
b419b35b
DR		 1872 .dma_alloc_pages = dma_alloc_pages,
1873 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 1874};
1875
1876static const struct hda_controller_ops pci_hda_ops = {
1877 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1878 .substream_alloc_pages = substream_alloc_pages,
1879 .substream_free_pages = substream_free_pages,
8769b278 1880 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1881 .position_check = azx_position_check,
17eccb27 1882 .link_power = azx_intel_link_power,
40830813
DR		 1883};
1884
e23e7a14
BP		 1885static int azx_probe(struct pci_dev *pci,
1886 const struct pci_device_id *pci_id)
1da177e4 1887{
5aba4f8e 1888 static int dev;
a98f90fd 1889 struct snd_card *card;
9a34af4a 1890 struct hda_intel *hda;
a98f90fd 1891 struct azx *chip;
aad730d0 1892 bool schedule_probe;
927fc866 1893 int err;
1da177e4 1894
5aba4f8e
TI		 1895 if (dev >= SNDRV_CARDS)
1896 return -ENODEV;
1897 if (!enable[dev]) {
1898 dev++;
1899 return -ENOENT;
1900 }
1901
60c5772b
TI		 1902 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1903 0, &card);
e58de7ba 1904 if (err < 0) {
4e76a883 1905 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1906 return err;
1da177e4
LT		 1907 }
1908
a43ff5ba 1909 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 1910 if (err < 0)
1911 goto out_free;
421a1252 1912 card->private_data = chip;
9a34af4a 1913 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1914
1915 pci_set_drvdata(pci, card);
1916
1917 err = register_vga_switcheroo(chip);
1918 if (err < 0) {
4e76a883 1919 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1920 goto out_free;
1921 }
1922
1923 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1924 dev_info(card->dev, "VGA controller is disabled\n");
1925 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1926 chip->disabled = true;
1927 }
1928
aad730d0 1929 schedule_probe = !chip->disabled;
1da177e4 1930
4918cdab
TI		 1931#ifdef CONFIG_SND_HDA_PATCH_LOADER
1932 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1933 dev_info(card->dev, "Applying patch firmware '%s'\n",
1934 patch[dev]);
5cb543db
TI		 1935 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1936 &pci->dev, GFP_KERNEL, card,
1937 azx_firmware_cb);
4918cdab
TI		 1938 if (err < 0)
1939 goto out_free;
aad730d0 1940 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1941 }
1942#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1943
aad730d0
TI		 1944#ifndef CONFIG_SND_HDA_I915
1945 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1946 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1947#endif
99a2008d 1948
aad730d0 1949 if (schedule_probe)
9a34af4a 1950 schedule_work(&hda->probe_work);
a82d51ed 1951
a82d51ed 1952 dev++;
88d071fc 1953 if (chip->disabled)
9a34af4a 1954 complete_all(&hda->probe_wait);
a82d51ed
TI		 1955 return 0;
1956
1957out_free:
1958 snd_card_free(card);
1959 return err;
1960}
1961
e62a42ae
DR		 1962/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1963static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1964 [AZX_DRIVER_NVIDIA] = 8,
1965 [AZX_DRIVER_TERA] = 1,
1966};
1967
48c8b0eb 1968static int azx_probe_continue(struct azx *chip)
a82d51ed 1969{
9a34af4a 1970 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 1971 struct hdac_bus *bus = azx_bus(chip);
c67e2228 1972 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1973 int dev = chip->dev_index;
1974 int err;
1975
a41d1224 1976 hda->probe_continued = 1;
795614dd
ML		 1977
1978 /* Request display power well for the HDA controller or codec. For
1979 * Haswell/Broadwell, both the display HDA controller and codec need
1980 * this power. For other platforms, like Baytrail/Braswell, only the
1981 * display codec needs the power and it can be released after probe.
1982 */
99a2008d 1983 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
03b135ce
LY		 1984 /* HSW/BDW controllers need this power */
1985 if (CONTROLLER_IN_GPU(pci))
2bd1f73f
ML		 1986 hda->need_i915_power = 1;
1987
98d8fc6c 1988 err = snd_hdac_i915_init(bus);
535115b5
TI		 1989 if (err < 0) {
1990 /* if the controller is bound only with HDMI/DP
1991 * (for HSW and BDW), we need to abort the probe;
1992 * for other chips, still continue probing as other
1993 * codecs can be on the same link.
1994 */
1995 if (CONTROLLER_IN_GPU(pci))
1996 goto out_free;
1997 else
1998 goto skip_i915;
1999 }
795614dd 2000
98d8fc6c 2001 err = snd_hdac_display_power(bus, true);
74b0c2d7
TI		 2002 if (err < 0) {
2003 dev_err(chip->card->dev,
2004 "Cannot turn on display power on i915\n");
795614dd 2005 goto i915_power_fail;
74b0c2d7 2006 }
99a2008d
WX		 2007 }
2008
bf06848b 2009 skip_i915:
5c90680e
TI		 2010 err = azx_first_init(chip);
2011 if (err < 0)
2012 goto out_free;
2013
2dca0bba
JK		 2014#ifdef CONFIG_SND_HDA_INPUT_BEEP
2015 chip->beep_mode = beep_mode[dev];
2016#endif
2017
1da177e4 2018 /* create codec instances */
96d2bd6e 2019 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2020 if (err < 0)
2021 goto out_free;
96d2bd6e 2022
4ea6fbc8 2023#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2024 if (chip->fw) {
a41d1224 2025 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2026 chip->fw->data);
4ea6fbc8
TI		 2027 if (err < 0)
2028 goto out_free;
e39ae856 2029#ifndef CONFIG_PM
4918cdab
TI		 2030 release_firmware(chip->fw); /* no longer needed */
2031 chip->fw = NULL;
e39ae856 2032#endif
4ea6fbc8
TI		 2033 }
2034#endif
10e77dda 2035 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2036 err = azx_codec_configure(chip);
2037 if (err < 0)
2038 goto out_free;
2039 }
1da177e4 2040
a82d51ed 2041 err = snd_card_register(chip->card);
41dda0fd
WF		 2042 if (err < 0)
2043 goto out_free;
1da177e4 2044
cb53c626 2045 chip->running = 1;
65fcd41d 2046 azx_add_card_list(chip);
a41d1224 2047 snd_hda_set_power_save(&chip->bus, power_save * 1000);
364aa716 2048 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
c67e2228 2049 pm_runtime_put_noidle(&pci->dev);
1da177e4 2050
41dda0fd 2051out_free:
795614dd
ML		 2052 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2053 && !hda->need_i915_power)
98d8fc6c 2054 snd_hdac_display_power(bus, false);
795614dd
ML		 2055
2056i915_power_fail:
88d071fc 2057 if (err < 0)
9a34af4a
TI		 2058 hda->init_failed = 1;
2059 complete_all(&hda->probe_wait);
41dda0fd 2060 return err;
1da177e4
LT		 2061}
2062
e23e7a14 2063static void azx_remove(struct pci_dev *pci)
1da177e4 2064{
9121947d 2065 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 2066
9121947d
TI		 2067 if (card)
2068 snd_card_free(card);
1da177e4
LT		 2069}
2070
b2a0bafa
TI		 2071static void azx_shutdown(struct pci_dev *pci)
2072{
2073 struct snd_card *card = pci_get_drvdata(pci);
2074 struct azx *chip;
2075
2076 if (!card)
2077 return;
2078 chip = card->private_data;
2079 if (chip && chip->running)
2080 azx_stop_chip(chip);
2081}
2082
1da177e4 2083/* PCI IDs */
6f51f6cf 2084static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2085 /* CPT */
9477c58e 2086 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2087 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2088 /* PBG */
9477c58e 2089 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2090 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2091 /* Panther Point */
9477c58e 2092 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2093 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2094 /* Lynx Point */
2095 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2096 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2097 /* 9 Series */
2098 { PCI_DEVICE(0x8086, 0x8ca0),
2099 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2100 /* Wellsburg */
2101 { PCI_DEVICE(0x8086, 0x8d20),
2102 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2103 { PCI_DEVICE(0x8086, 0x8d21),
2104 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2105 /* Lynx Point-LP */
2106 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2107 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2108 /* Lynx Point-LP */
2109 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2110 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2111 /* Wildcat Point-LP */
2112 { PCI_DEVICE(0x8086, 0x9ca0),
2113 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2114 /* Sunrise Point */
2115 { PCI_DEVICE(0x8086, 0xa170),
db48abf4 2116 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2117 /* Sunrise Point-LP */
2118 { PCI_DEVICE(0x8086, 0x9d70),
d6795827 2119 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
e926f2c8 2120 /* Haswell */
4a7c516b 2121 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2122 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2123 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2124 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2125 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2126 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2127 /* Broadwell */
2128 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2129 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2130 /* 5 Series/3400 */
2131 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2132 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2133 /* Poulsbo */
9477c58e 2134 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 2135 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2136 /* Oaktrail */
09904b95 2137 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 2138 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 2139 /* BayTrail */
2140 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2141 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2142 /* Braswell */
2143 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2144 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2145 /* ICH6 */
8b0bd226 2146 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2147 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2148 /* ICH7 */
8b0bd226 2149 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2150 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2151 /* ESB2 */
8b0bd226 2152 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2153 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2154 /* ICH8 */
8b0bd226 2155 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2156 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2157 /* ICH9 */
8b0bd226 2158 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2159 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2160 /* ICH9 */
8b0bd226 2161 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2162 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2163 /* ICH10 */
8b0bd226 2164 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2165 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2166 /* ICH10 */
8b0bd226 2167 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2168 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2169 /* Generic Intel */
2170 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2171 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2172 .class_mask = 0xffffff,
103884a3 2173 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2174 /* ATI SB 450/600/700/800/900 */
2175 { PCI_DEVICE(0x1002, 0x437b),
2176 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2177 { PCI_DEVICE(0x1002, 0x4383),
2178 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2179 /* AMD Hudson */
2180 { PCI_DEVICE(0x1022, 0x780d),
2181 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2182 /* ATI HDMI */
9477c58e
TI		 2183 { PCI_DEVICE(0x1002, 0x793b),
2184 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2185 { PCI_DEVICE(0x1002, 0x7919),
2186 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2187 { PCI_DEVICE(0x1002, 0x960f),
2188 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2189 { PCI_DEVICE(0x1002, 0x970f),
2190 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2191 { PCI_DEVICE(0x1002, 0xaa00),
2192 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2193 { PCI_DEVICE(0x1002, 0xaa08),
2194 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2195 { PCI_DEVICE(0x1002, 0xaa10),
2196 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2197 { PCI_DEVICE(0x1002, 0xaa18),
2198 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2199 { PCI_DEVICE(0x1002, 0xaa20),
2200 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2201 { PCI_DEVICE(0x1002, 0xaa28),
2202 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2203 { PCI_DEVICE(0x1002, 0xaa30),
2204 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2205 { PCI_DEVICE(0x1002, 0xaa38),
2206 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2207 { PCI_DEVICE(0x1002, 0xaa40),
2208 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2209 { PCI_DEVICE(0x1002, 0xaa48),
2210 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2211 { PCI_DEVICE(0x1002, 0xaa50),
2212 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2213 { PCI_DEVICE(0x1002, 0xaa58),
2214 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2215 { PCI_DEVICE(0x1002, 0xaa60),
2216 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2217 { PCI_DEVICE(0x1002, 0xaa68),
2218 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2219 { PCI_DEVICE(0x1002, 0xaa80),
2220 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2221 { PCI_DEVICE(0x1002, 0xaa88),
2222 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2223 { PCI_DEVICE(0x1002, 0xaa90),
2224 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2225 { PCI_DEVICE(0x1002, 0xaa98),
2226 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2227 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2228 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2229 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2230 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2231 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2232 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2233 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2234 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2235 { PCI_DEVICE(0x1002, 0xaac8),
2236 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2237 /* VIA VT8251/VT8237A */
9477c58e
TI		 2238 { PCI_DEVICE(0x1106, 0x3288),
2239 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 2240 /* VIA GFX VT7122/VX900 */
2241 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2242 /* VIA GFX VT6122/VX11 */
2243 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2244 /* SIS966 */
2245 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2246 /* ULI M5461 */
2247 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2248 /* NVIDIA MCP */
0c2fd1bf
TI		 2249 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2250 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2251 .class_mask = 0xffffff,
9477c58e 2252 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2253 /* Teradici */
9477c58e
TI		 2254 { PCI_DEVICE(0x6549, 0x1200),
2255 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2256 { PCI_DEVICE(0x6549, 0x2200),
2257 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2258 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2259 /* CTHDA chips */
2260 { PCI_DEVICE(0x1102, 0x0010),
2261 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2262 { PCI_DEVICE(0x1102, 0x0012),
2263 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2264#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2265 /* the following entry conflicts with snd-ctxfi driver,
2266 * as ctxfi driver mutates from HD-audio to native mode with
2267 * a special command sequence.
2268 */
4e01f54b
TI		 2269 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2270 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2271 .class_mask = 0xffffff,
9477c58e 2272 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2273 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2274#else
2275 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2276 { PCI_DEVICE(0x1102, 0x0009),
2277 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 2278 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2279#endif
c563f473
TI		 2280 /* CM8888 */
2281 { PCI_DEVICE(0x13f6, 0x5011),
2282 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2283 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2284 /* Vortex86MX */
2285 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2286 /* VMware HDAudio */
2287 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2288 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2289 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2290 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2291 .class_mask = 0xffffff,
9477c58e 2292 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2293 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2294 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2295 .class_mask = 0xffffff,
9477c58e 2296 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2297 { 0, }
2298};
2299MODULE_DEVICE_TABLE(pci, azx_ids);
2300
2301/* pci_driver definition */
e9f66d9b 2302static struct pci_driver azx_driver = {
3733e424 2303 .name = KBUILD_MODNAME,
1da177e4
LT		 2304 .id_table = azx_ids,
2305 .probe = azx_probe,
e23e7a14 2306 .remove = azx_remove,
b2a0bafa 2307 .shutdown = azx_shutdown,
68cb2b55
TI		 2308 .driver = {
2309 .pm = AZX_PM_OPS,
2310 },
1da177e4
LT		 2311};
2312
e9f66d9b 2313module_pci_driver(azx_driver);
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