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Merge remote-tracking branch 'regulator/fix/max77802' into regulator-linus
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
7f80f513 56#include <asm/set_memory.h>
50279d9b 57#include <asm/cpufeature.h>
27fe48d9 58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
98d8fc6c
ML		 61#include <sound/hdaudio.h>
62#include <sound/hda_i915.h>
9121947d 63#include <linux/vgaarb.h>
a82d51ed 64#include <linux/vga_switcheroo.h>
4918cdab 65#include <linux/firmware.h>
1da177e4 66#include "hda_codec.h"
05e84878 67#include "hda_controller.h"
347de1f8 68#include "hda_intel.h"
1da177e4 69
785d8c4b
LY		 70#define CREATE_TRACE_POINTS
71#include "hda_intel_trace.h"
72
b6050ef6
TI		 73/* position fix mode */
74enum {
75 POS_FIX_AUTO,
76 POS_FIX_LPIB,
77 POS_FIX_POSBUF,
78 POS_FIX_VIACOMBO,
79 POS_FIX_COMBO,
f87e7f25 80 POS_FIX_SKL,
b6050ef6
TI		 81};
82
9a34af4a
TI		 83/* Defines for ATI HD Audio support in SB450 south bridge */
84#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
85#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
86
87/* Defines for Nvidia HDA support */
88#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
89#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
90#define NVIDIA_HDA_ISTRM_COH 0x4d
91#define NVIDIA_HDA_OSTRM_COH 0x4c
92#define NVIDIA_HDA_ENABLE_COHBIT 0x01
93
94/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 95#define INTEL_HDA_CGCTL 0x48
96#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 97#define INTEL_SCH_HDA_DEVC 0x78
98#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
99
100/* Define IN stream 0 FIFO size offset in VIA controller */
101#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
102/* Define VIA HD Audio Device ID*/
103#define VIA_HDAC_DEVICE_ID 0x3288
104
33124929
TI		 105/* max number of SDs */
106/* ICH, ATI and VIA have 4 playback and 4 capture */
107#define ICH6_NUM_CAPTURE 4
108#define ICH6_NUM_PLAYBACK 4
109
110/* ULI has 6 playback and 5 capture */
111#define ULI_NUM_CAPTURE 5
112#define ULI_NUM_PLAYBACK 6
113
114/* ATI HDMI may have up to 8 playbacks and 0 capture */
115#define ATIHDMI_NUM_CAPTURE 0
116#define ATIHDMI_NUM_PLAYBACK 8
117
118/* TERA has 4 playback and 3 capture */
119#define TERA_NUM_CAPTURE 3
120#define TERA_NUM_PLAYBACK 4
121
1da177e4 122
5aba4f8e
TI		 123static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
124static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 125static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 126static char *model[SNDRV_CARDS];
1dac6695 127static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 128static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 129static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 130static int probe_only[SNDRV_CARDS];
26a6cb6c 131static int jackpoll_ms[SNDRV_CARDS];
41438f13 132static int single_cmd = -1;
71623855 133static int enable_msi = -1;
4ea6fbc8
TI		 134#ifdef CONFIG_SND_HDA_PATCH_LOADER
135static char *patch[SNDRV_CARDS];
136#endif
2dca0bba 137#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 138static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 139 CONFIG_SND_HDA_INPUT_BEEP_MODE};
140#endif
1da177e4 141
5aba4f8e 142module_param_array(index, int, NULL, 0444);
1da177e4 143MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 144module_param_array(id, charp, NULL, 0444);
1da177e4 145MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 146module_param_array(enable, bool, NULL, 0444);
147MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
148module_param_array(model, charp, NULL, 0444);
1da177e4 149MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 150module_param_array(position_fix, int, NULL, 0444);
4cb36310 151MODULE_PARM_DESC(position_fix, "DMA pointer read method."
f87e7f25 152 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
555e219f
TI		 153module_param_array(bdl_pos_adj, int, NULL, 0644);
154MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 155module_param_array(probe_mask, int, NULL, 0444);
606ad75f 156MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 157module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 158MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 159module_param_array(jackpoll_ms, int, NULL, 0444);
160MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 161module_param(single_cmd, bint, 0444);
d01ce99f
TI		 162MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
163 "(for debugging only).");
ac9ef6cf 164module_param(enable_msi, bint, 0444);
134a11f0 165MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 166#ifdef CONFIG_SND_HDA_PATCH_LOADER
167module_param_array(patch, charp, NULL, 0444);
168MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
169#endif
2dca0bba 170#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 171module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 172MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 173 "(0=off, 1=on) (default=1).");
2dca0bba 174#endif
606ad75f 175
83012a7c 176#ifdef CONFIG_PM
65fcd41d 177static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 178static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 179 .set = param_set_xint,
180 .get = param_get_int,
181};
182#define param_check_xint param_check_int
183
fee2fba3 184static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 185module_param(power_save, xint, 0644);
fee2fba3
TI		 186MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
187 "(in second, 0 = disable).");
1da177e4 188
dee1b66c
TI		 189/* reset the HD-audio controller in power save mode.
190 * this may give more power-saving, but will take longer time to
191 * wake up.
192 */
8fc24426
TI		 193static bool power_save_controller = 1;
194module_param(power_save_controller, bool, 0644);
dee1b66c 195MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 196#else
bb573928 197#define power_save 0
83012a7c 198#endif /* CONFIG_PM */
dee1b66c 199
7bfe059e
TI		 200static int align_buffer_size = -1;
201module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 202MODULE_PARM_DESC(align_buffer_size,
203 "Force buffer and period sizes to be multiple of 128 bytes.");
204
27fe48d9 205#ifdef CONFIG_X86
7c732015
TI		 206static int hda_snoop = -1;
207module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 208MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 209#else
210#define hda_snoop true
27fe48d9
TI		 211#endif
212
213
1da177e4
LT		 214MODULE_LICENSE("GPL");
215MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
216 "{Intel, ICH6M},"
2f1b3818 217 "{Intel, ICH7},"
f5d40b30 218 "{Intel, ESB2},"
d2981393 219 "{Intel, ICH8},"
f9cc8a8b 220 "{Intel, ICH9},"
c34f5a04 221 "{Intel, ICH10},"
b29c2360 222 "{Intel, PCH},"
d2f2fcd2 223 "{Intel, CPT},"
d2edeb7c 224 "{Intel, PPT},"
8bc039a1 225 "{Intel, LPT},"
144dad99 226 "{Intel, LPT_LP},"
4eeca499 227 "{Intel, WPT_LP},"
c8b00fd2 228 "{Intel, SPT},"
b4565913 229 "{Intel, SPT_LP},"
e926f2c8 230 "{Intel, HPT},"
cea310e8 231 "{Intel, PBG},"
4979bca9 232 "{Intel, SCH},"
fc20a562 233 "{ATI, SB450},"
89be83f8 234 "{ATI, SB600},"
778b6e1b 235 "{ATI, RS600},"
5b15c95f 236 "{ATI, RS690},"
e6db1119
WL		 237 "{ATI, RS780},"
238 "{ATI, R600},"
2797f724
HRK		 239 "{ATI, RV630},"
240 "{ATI, RV610},"
27da1834
WL		 241 "{ATI, RV670},"
242 "{ATI, RV635},"
243 "{ATI, RV620},"
244 "{ATI, RV770},"
fc20a562 245 "{VIA, VT8251},"
47672310 246 "{VIA, VT8237A},"
07e4ca50
TI		 247 "{SiS, SIS966},"
248 "{ULI, M5461}}");
1da177e4
LT		 249MODULE_DESCRIPTION("Intel HDA driver");
250
a82d51ed 251#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 252#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 253#define SUPPORT_VGA_SWITCHEROO
254#endif
255#endif
256
257
1da177e4 258/*
1da177e4 259 */
1da177e4 260
07e4ca50
TI		 261/* driver types */
262enum {
263 AZX_DRIVER_ICH,
32679f95 264 AZX_DRIVER_PCH,
4979bca9 265 AZX_DRIVER_SCH,
fab1285a 266 AZX_DRIVER_HDMI,
07e4ca50 267 AZX_DRIVER_ATI,
778b6e1b 268 AZX_DRIVER_ATIHDMI,
1815b34a 269 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 270 AZX_DRIVER_VIA,
271 AZX_DRIVER_SIS,
272 AZX_DRIVER_ULI,
da3fca21 273 AZX_DRIVER_NVIDIA,
f269002e 274 AZX_DRIVER_TERA,
14d34f16 275 AZX_DRIVER_CTX,
5ae763b1 276 AZX_DRIVER_CTHDA,
c563f473 277 AZX_DRIVER_CMEDIA,
c4da29ca 278 AZX_DRIVER_GENERIC,
2f5983f2 279 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 280};
281
37e661ee
TI		 282#define azx_get_snoop_type(chip) \
283 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
284#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
285
b42b4afb
TI		 286/* quirks for old Intel chipsets */
287#define AZX_DCAPS_INTEL_ICH \
103884a3 288 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 289
2ea3c6a2 290/* quirks for Intel PCH */
6603249d 291#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 292 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
bcb337d1 293 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 294
55913110 295/* PCH up to IVB; no runtime PM */
6603249d 296#define AZX_DCAPS_INTEL_PCH_NOPM \
55913110 297 (AZX_DCAPS_INTEL_PCH_BASE)
6603249d 298
55913110 299/* PCH for HSW/BDW; with runtime PM */
d7dab4db 300#define AZX_DCAPS_INTEL_PCH \
6603249d 301 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 302
6603249d 303/* HSW HDMI */
33499a15 304#define AZX_DCAPS_INTEL_HASWELL \
103884a3 305 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 306 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
307 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 308
54a0405d
LY		 309/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
310#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
313 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 314
40cc2392
ML		 315#define AZX_DCAPS_INTEL_BAYTRAIL \
316 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
317
2d846c74
LY		 318#define AZX_DCAPS_INTEL_BRASWELL \
319 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
320
d6795827 321#define AZX_DCAPS_INTEL_SKYLAKE \
2d846c74
LY		 322 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
323 AZX_DCAPS_I915_POWERWELL)
d6795827 324
c87693da
LH		 325#define AZX_DCAPS_INTEL_BROXTON \
326 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
327 AZX_DCAPS_I915_POWERWELL)
328
9477c58e
TI		 329/* quirks for ATI SB / AMD Hudson */
330#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 331 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
332 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 333
334/* quirks for ATI/AMD HDMI */
335#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 336 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
337 AZX_DCAPS_NO_MSI64)
9477c58e 338
37e661ee
TI		 339/* quirks for ATI HDMI with snoop off */
340#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
341 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
342
9477c58e
TI		 343/* quirks for Nvidia */
344#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 345 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 346 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 347
5ae763b1 348#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 349 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 350 AZX_DCAPS_NO_64BIT |\
37e661ee 351 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 352
a82d51ed 353/*
2b760d88 354 * vga_switcheroo support
a82d51ed
TI		 355 */
356#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 357#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
358#else
359#define use_vga_switcheroo(chip) 0
360#endif
361
03b135ce
LY		 362#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
363 ((pci)->device == 0x0c0c) || \
364 ((pci)->device == 0x0d0c) || \
365 ((pci)->device == 0x160c))
366
7e31a015
TI		 367#define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
368#define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
35639a0e
VK		 369#define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
370#define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
6858107e 371#define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
7e31a015 372#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
c7ecb906 373#define IS_BXT_T(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x1a98)
12ee4022 374#define IS_GLK(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x3198)
e79b0006 375#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
c7ecb906
TI		 376#define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci) || \
377 IS_BXT_T(pci) || IS_KBL(pci) || IS_KBL_LP(pci) || \
378 IS_KBL_H(pci) || IS_GLK(pci) || IS_CFL(pci))
7c23b7c1 379
48c8b0eb 380static char *driver_short_names[] = {
07e4ca50 381 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 382 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 383 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 384 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 385 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 386 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 387 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 388 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
389 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 390 [AZX_DRIVER_ULI] = "HDA ULI M5461",
391 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 392 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 393 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 394 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 395 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 396 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 397};
398
27fe48d9 399#ifdef CONFIG_X86
9ddf1aeb 400static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 401{
9ddf1aeb
TI		 402 int pages;
403
27fe48d9
TI		 404 if (azx_snoop(chip))
405 return;
9ddf1aeb
TI		 406 if (!dmab || !dmab->area || !dmab->bytes)
407 return;
408
409#ifdef CONFIG_SND_DMA_SGBUF
410 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
411 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 412 if (chip->driver_type == AZX_DRIVER_CMEDIA)
413 return; /* deal with only CORB/RIRB buffers */
27fe48d9 414 if (on)
9ddf1aeb 415 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 416 else
9ddf1aeb
TI		 417 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
418 return;
27fe48d9 419 }
9ddf1aeb
TI		 420#endif
421
422 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
423 if (on)
424 set_memory_wc((unsigned long)dmab->area, pages);
425 else
426 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 427}
428
429static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
430 bool on)
431{
9ddf1aeb 432 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 433}
434static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 435 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 436{
437 if (azx_dev->wc_marked != on) {
9ddf1aeb 438 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 439 azx_dev->wc_marked = on;
440 }
441}
442#else
443/* NOP for other archs */
444static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
445 bool on)
446{
447}
448static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 449 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 450{
451}
452#endif
453
68e7fffc 454static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 455
cb53c626
TI		 456/*
457 * initialize the PCI registers
458 */
459/* update bits in a PCI register byte */
460static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
461 unsigned char mask, unsigned char val)
462{
463 unsigned char data;
464
465 pci_read_config_byte(pci, reg, &data);
466 data &= ~mask;
467 data |= (val & mask);
468 pci_write_config_byte(pci, reg, data);
469}
470
471static void azx_init_pci(struct azx *chip)
472{
37e661ee
TI		 473 int snoop_type = azx_get_snoop_type(chip);
474
cb53c626
TI		 475 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
476 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
477 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 478 * codecs.
479 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 480 */
46f2cc80 481 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 482 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 483 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 484 }
cb53c626 485
9477c58e
TI		 486 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
487 * we need to enable snoop.
488 */
37e661ee 489 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 490 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
491 azx_snoop(chip));
cb53c626 492 update_pci_byte(chip->pci,
27fe48d9
TI		 493 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
494 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 495 }
496
497 /* For NVIDIA HDA, enable snoop */
37e661ee 498 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 499 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
500 azx_snoop(chip));
cb53c626
TI		 501 update_pci_byte(chip->pci,
502 NVIDIA_HDA_TRANSREG_ADDR,
503 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 504 update_pci_byte(chip->pci,
505 NVIDIA_HDA_ISTRM_COH,
506 0x01, NVIDIA_HDA_ENABLE_COHBIT);
507 update_pci_byte(chip->pci,
508 NVIDIA_HDA_OSTRM_COH,
509 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 510 }
511
512 /* Enable SCH/PCH snoop if needed */
37e661ee 513 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 514 unsigned short snoop;
90a5ad52 515 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 516 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
517 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
518 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
519 if (!azx_snoop(chip))
520 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
521 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 522 pci_read_config_word(chip->pci,
523 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 524 }
4e76a883
TI		 525 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
526 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
527 "Disabled" : "Enabled");
da3fca21 528 }
1da177e4
LT		 529}
530
7c23b7c1
LH		 531/*
532 * In BXT-P A0, HD-Audio DMA requests is later than expected,
533 * and makes an audio stream sensitive to system latencies when
534 * 24/32 bits are playing.
535 * Adjusting threshold of DMA fifo to force the DMA request
536 * sooner to improve latency tolerance at the expense of power.
537 */
538static void bxt_reduce_dma_latency(struct azx *chip)
539{
540 u32 val;
541
70eafad8 542 val = azx_readl(chip, VS_EM4L);
7c23b7c1 543 val &= (0x3 << 20);
70eafad8 544 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 545}
546
1f9d3d98
LY		 547/*
548 * ML_LCAP bits:
549 * bit 0: 6 MHz Supported
550 * bit 1: 12 MHz Supported
551 * bit 2: 24 MHz Supported
552 * bit 3: 48 MHz Supported
553 * bit 4: 96 MHz Supported
554 * bit 5: 192 MHz Supported
555 */
556static int intel_get_lctl_scf(struct azx *chip)
557{
558 struct hdac_bus *bus = azx_bus(chip);
559 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
560 u32 val, t;
561 int i;
562
563 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
564
565 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
566 t = preferred_bits[i];
567 if (val & (1 << t))
568 return t;
569 }
570
571 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
572 return 0;
573}
574
575static int intel_ml_lctl_set_power(struct azx *chip, int state)
576{
577 struct hdac_bus *bus = azx_bus(chip);
578 u32 val;
579 int timeout;
580
581 /*
582 * the codecs are sharing the first link setting by default
583 * If other links are enabled for stream, they need similar fix
584 */
585 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
586 val &= ~AZX_MLCTL_SPA;
587 val |= state << AZX_MLCTL_SPA_SHIFT;
588 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
589 /* wait for CPA */
590 timeout = 50;
591 while (timeout) {
592 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
593 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
594 return 0;
595 timeout--;
596 udelay(10);
597 }
598
599 return -1;
600}
601
602static void intel_init_lctl(struct azx *chip)
603{
604 struct hdac_bus *bus = azx_bus(chip);
605 u32 val;
606 int ret;
607
608 /* 0. check lctl register value is correct or not */
609 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
610 /* if SCF is already set, let's use it */
611 if ((val & ML_LCTL_SCF_MASK) != 0)
612 return;
613
614 /*
615 * Before operating on SPA, CPA must match SPA.
616 * Any deviation may result in undefined behavior.
617 */
618 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
619 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
620 return;
621
622 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
623 ret = intel_ml_lctl_set_power(chip, 0);
624 udelay(100);
625 if (ret)
626 goto set_spa;
627
628 /* 2. update SCF to select a properly audio clock*/
629 val &= ~ML_LCTL_SCF_MASK;
630 val |= intel_get_lctl_scf(chip);
631 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
632
633set_spa:
634 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
635 intel_ml_lctl_set_power(chip, 1);
636 udelay(100);
637}
638
0a673521
LH		 639static void hda_intel_init_chip(struct azx *chip, bool full_reset)
640{
98d8fc6c 641 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 642 struct pci_dev *pci = chip->pci;
6639484d 643 u32 val;
0a673521
LH		 644
645 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 646 snd_hdac_set_codec_wakeup(bus, true);
7e31a015 647 if (IS_SKL_PLUS(pci)) {
6639484d
LY		 648 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
649 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
650 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
651 }
0a673521 652 azx_init_chip(chip, full_reset);
7e31a015 653 if (IS_SKL_PLUS(pci)) {
6639484d
LY		 654 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
655 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
656 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
657 }
0a673521 658 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 659 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 660
661 /* reduce dma latency to avoid noise */
7e31a015 662 if (IS_BXT(pci))
7c23b7c1 663 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 664
665 if (bus->mlcap != NULL)
666 intel_init_lctl(chip);
0a673521
LH		 667}
668
b6050ef6
TI		 669/* calculate runtime delay from LPIB */
670static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
671 unsigned int pos)
672{
7833c3f8 673 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 674 int stream = substream->stream;
675 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
676 int delay;
677
678 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
679 delay = pos - lpib_pos;
680 else
681 delay = lpib_pos - pos;
682 if (delay < 0) {
7833c3f8 683 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 684 delay = 0;
685 else
7833c3f8 686 delay += azx_dev->core.bufsize;
b6050ef6
TI		 687 }
688
7833c3f8 689 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 690 dev_info(chip->card->dev,
691 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 692 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 693 delay = 0;
694 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
695 chip->get_delay[stream] = NULL;
696 }
697
698 return bytes_to_frames(substream->runtime, delay);
699}
700
9ad593f6
TI		 701static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
702
7ca954a8
DR		 703/* called from IRQ */
704static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
705{
9a34af4a 706 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 707 int ok;
708
709 ok = azx_position_ok(chip, azx_dev);
710 if (ok == 1) {
711 azx_dev->irq_pending = 0;
712 return ok;
2f35c630 713 } else if (ok == 0) {
7ca954a8
DR		 714 /* bogus IRQ, process it later */
715 azx_dev->irq_pending = 1;
2f35c630 716 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 717 }
718 return 0;
719}
720
17eccb27
ML		 721/* Enable/disable i915 display power for the link */
722static int azx_intel_link_power(struct azx *chip, bool enable)
723{
98d8fc6c 724 struct hdac_bus *bus = azx_bus(chip);
17eccb27 725
98d8fc6c 726 return snd_hdac_display_power(bus, enable);
17eccb27
ML		 727}
728
9ad593f6
TI		 729/*
730 * Check whether the current DMA position is acceptable for updating
731 * periods. Returns non-zero if it's OK.
732 *
733 * Many HD-audio controllers appear pretty inaccurate about
734 * the update-IRQ timing. The IRQ is issued before actually the
735 * data is processed. So, we need to process it afterwords in a
736 * workqueue.
737 */
738static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
739{
7833c3f8 740 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 741 int stream = substream->stream;
e5463720 742 u32 wallclk;
9ad593f6
TI		 743 unsigned int pos;
744
7833c3f8
TI		 745 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
746 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 747 return -1; /* bogus (too early) interrupt */
fa00e046 748
b6050ef6
TI		 749 if (chip->get_position[stream])
750 pos = chip->get_position[stream](chip, azx_dev);
751 else { /* use the position buffer as default */
752 pos = azx_get_pos_posbuf(chip, azx_dev);
753 if (!pos || pos == (u32)-1) {
754 dev_info(chip->card->dev,
755 "Invalid position buffer, using LPIB read method instead.\n");
756 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 757 if (chip->get_position[0] == azx_get_pos_lpib &&
758 chip->get_position[1] == azx_get_pos_lpib)
759 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 760 pos = azx_get_pos_lpib(chip, azx_dev);
761 chip->get_delay[stream] = NULL;
762 } else {
763 chip->get_position[stream] = azx_get_pos_posbuf;
764 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
765 chip->get_delay[stream] = azx_get_delay_from_lpib;
766 }
767 }
768
7833c3f8 769 if (pos >= azx_dev->core.bufsize)
b6050ef6 770 pos = 0;
9ad593f6 771
7833c3f8 772 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 773 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 774 return -1; /* this shouldn't happen! */
7833c3f8
TI		 775 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
776 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 777 /* NG - it's below the first next period boundary */
4f0189be 778 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 779 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 780 return 1; /* OK, it's fine */
781}
782
783/*
784 * The work for pending PCM period updates.
785 */
786static void azx_irq_pending_work(struct work_struct *work)
787{
9a34af4a
TI		 788 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
789 struct azx *chip = &hda->chip;
7833c3f8
TI		 790 struct hdac_bus *bus = azx_bus(chip);
791 struct hdac_stream *s;
792 int pending, ok;
9ad593f6 793
9a34af4a 794 if (!hda->irq_pending_warned) {
4e76a883
TI		 795 dev_info(chip->card->dev,
796 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
797 chip->card->number);
9a34af4a 798 hda->irq_pending_warned = 1;
a6a950a8
TI		 799 }
800
9ad593f6
TI		 801 for (;;) {
802 pending = 0;
a41d1224 803 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 804 list_for_each_entry(s, &bus->stream_list, list) {
805 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 806 if (!azx_dev->irq_pending ||
7833c3f8
TI		 807 !s->substream ||
808 !s->running)
9ad593f6 809 continue;
e5463720
JK		 810 ok = azx_position_ok(chip, azx_dev);
811 if (ok > 0) {
9ad593f6 812 azx_dev->irq_pending = 0;
a41d1224 813 spin_unlock(&bus->reg_lock);
7833c3f8 814 snd_pcm_period_elapsed(s->substream);
a41d1224 815 spin_lock(&bus->reg_lock);
e5463720
JK		 816 } else if (ok < 0) {
817 pending = 0; /* too early */
9ad593f6
TI		 818 } else
819 pending++;
820 }
a41d1224 821 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 822 if (!pending)
823 return;
08af495f 824 msleep(1);
9ad593f6
TI		 825 }
826}
827
828/* clear irq_pending flags and assure no on-going workq */
829static void azx_clear_irq_pending(struct azx *chip)
830{
7833c3f8
TI		 831 struct hdac_bus *bus = azx_bus(chip);
832 struct hdac_stream *s;
9ad593f6 833
a41d1224 834 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 835 list_for_each_entry(s, &bus->stream_list, list) {
836 struct azx_dev *azx_dev = stream_to_azx_dev(s);
837 azx_dev->irq_pending = 0;
838 }
a41d1224 839 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 840}
841
68e7fffc
TI		 842static int azx_acquire_irq(struct azx *chip, int do_disconnect)
843{
a41d1224
TI		 844 struct hdac_bus *bus = azx_bus(chip);
845
437a5a46
TI		 846 if (request_irq(chip->pci->irq, azx_interrupt,
847 chip->msi ? 0 : IRQF_SHARED,
de65360b 848 chip->card->irq_descr, chip)) {
4e76a883
TI		 849 dev_err(chip->card->dev,
850 "unable to grab IRQ %d, disabling device\n",
851 chip->pci->irq);
68e7fffc
TI		 852 if (do_disconnect)
853 snd_card_disconnect(chip->card);
854 return -1;
855 }
a41d1224 856 bus->irq = chip->pci->irq;
69e13418 857 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 858 return 0;
859}
860
b6050ef6
TI		 861/* get the current DMA position with correction on VIA chips */
862static unsigned int azx_via_get_position(struct azx *chip,
863 struct azx_dev *azx_dev)
864{
865 unsigned int link_pos, mini_pos, bound_pos;
866 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
867 unsigned int fifo_size;
868
1604eeee 869 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 870 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 871 /* Playback, no problem using link position */
872 return link_pos;
873 }
874
875 /* Capture */
876 /* For new chipset,
877 * use mod to get the DMA position just like old chipset
878 */
7833c3f8
TI		 879 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
880 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 881
882 /* azx_dev->fifo_size can't get FIFO size of in stream.
883 * Get from base address + offset.
884 */
a41d1224
TI		 885 fifo_size = readw(azx_bus(chip)->remap_addr +
886 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 887
888 if (azx_dev->insufficient) {
889 /* Link position never gather than FIFO size */
890 if (link_pos <= fifo_size)
891 return 0;
892
893 azx_dev->insufficient = 0;
894 }
895
896 if (link_pos <= fifo_size)
7833c3f8 897 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 898 else
899 mini_pos = link_pos - fifo_size;
900
901 /* Find nearest previous boudary */
7833c3f8
TI		 902 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
903 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 904 if (mod_link_pos >= fifo_size)
905 bound_pos = link_pos - mod_link_pos;
906 else if (mod_dma_pos >= mod_mini_pos)
907 bound_pos = mini_pos - mod_mini_pos;
908 else {
7833c3f8
TI		 909 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
910 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 911 bound_pos = 0;
912 }
913
914 /* Calculate real DMA position we want */
915 return bound_pos + mod_dma_pos;
916}
917
f87e7f25
TI		 918static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
919 struct azx_dev *azx_dev)
920{
921 return _snd_hdac_chip_readl(azx_bus(chip),
922 AZX_REG_VS_SDXDPIB_XBASE +
923 (AZX_REG_VS_SDXDPIB_XINTERVAL *
924 azx_dev->core.index));
925}
926
927/* get the current DMA position with correction on SKL+ chips */
928static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
929{
930 /* DPIB register gives a more accurate position for playback */
931 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
932 return azx_skl_get_dpib_pos(chip, azx_dev);
933
934 /* For capture, we need to read posbuf, but it requires a delay
935 * for the possible boundary overlap; the read of DPIB fetches the
936 * actual posbuf
937 */
938 udelay(20);
939 azx_skl_get_dpib_pos(chip, azx_dev);
940 return azx_get_pos_posbuf(chip, azx_dev);
941}
942
83012a7c 943#ifdef CONFIG_PM
65fcd41d
TI		 944static DEFINE_MUTEX(card_list_lock);
945static LIST_HEAD(card_list);
946
947static void azx_add_card_list(struct azx *chip)
948{
9a34af4a 949 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 950 mutex_lock(&card_list_lock);
9a34af4a 951 list_add(&hda->list, &card_list);
65fcd41d
TI		 952 mutex_unlock(&card_list_lock);
953}
954
955static void azx_del_card_list(struct azx *chip)
956{
9a34af4a 957 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 958 mutex_lock(&card_list_lock);
9a34af4a 959 list_del_init(&hda->list);
65fcd41d
TI		 960 mutex_unlock(&card_list_lock);
961}
962
963/* trigger power-save check at writing parameter */
964static int param_set_xint(const char *val, const struct kernel_param *kp)
965{
9a34af4a 966 struct hda_intel *hda;
65fcd41d 967 struct azx *chip;
65fcd41d
TI		 968 int prev = power_save;
969 int ret = param_set_int(val, kp);
970
971 if (ret || prev == power_save)
972 return ret;
973
974 mutex_lock(&card_list_lock);
9a34af4a
TI		 975 list_for_each_entry(hda, &card_list, list) {
976 chip = &hda->chip;
a41d1224 977 if (!hda->probe_continued || chip->disabled)
65fcd41d 978 continue;
a41d1224 979 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 980 }
981 mutex_unlock(&card_list_lock);
982 return 0;
983}
984#else
985#define azx_add_card_list(chip) /* NOP */
986#define azx_del_card_list(chip) /* NOP */
83012a7c 987#endif /* CONFIG_PM */
5c0b9bec 988
7ccbde57 989#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 990/*
991 * power management
992 */
68cb2b55 993static int azx_suspend(struct device *dev)
1da177e4 994{
68cb2b55 995 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 996 struct azx *chip;
997 struct hda_intel *hda;
a41d1224 998 struct hdac_bus *bus;
1da177e4 999
2d9772ef
TI		 1000 if (!card)
1001 return 0;
1002
1003 chip = card->private_data;
1004 hda = container_of(chip, struct hda_intel, chip);
342e8449 1005 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 1006 return 0;
1007
a41d1224 1008 bus = azx_bus(chip);
421a1252 1009 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 1010 azx_clear_irq_pending(chip);
cb53c626 1011 azx_stop_chip(chip);
7295b264 1012 azx_enter_link_reset(chip);
a41d1224
TI		 1013 if (bus->irq >= 0) {
1014 free_irq(bus->irq, chip);
1015 bus->irq = -1;
30b35399 1016 }
a07187c9 1017
68e7fffc 1018 if (chip->msi)
43001c95 1019 pci_disable_msi(chip->pci);
795614dd
ML		 1020 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1021 && hda->need_i915_power)
98d8fc6c 1022 snd_hdac_display_power(bus, false);
785d8c4b
LY		 1023
1024 trace_azx_suspend(chip);
1da177e4
LT		 1025 return 0;
1026}
1027
68cb2b55 1028static int azx_resume(struct device *dev)
1da177e4 1029{
68cb2b55
TI		 1030 struct pci_dev *pci = to_pci_dev(dev);
1031 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1032 struct azx *chip;
1033 struct hda_intel *hda;
a52ff34e 1034 struct hdac_bus *bus;
2d9772ef
TI		 1035
1036 if (!card)
1037 return 0;
1da177e4 1038
2d9772ef
TI		 1039 chip = card->private_data;
1040 hda = container_of(chip, struct hda_intel, chip);
a52ff34e 1041 bus = azx_bus(chip);
342e8449 1042 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 1043 return 0;
1044
a52ff34e
TI		 1045 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1046 snd_hdac_display_power(bus, true);
1047 if (hda->need_i915_power)
1048 snd_hdac_i915_set_bclk(bus);
a07187c9 1049 }
a52ff34e 1050
68e7fffc
TI		 1051 if (chip->msi)
1052 if (pci_enable_msi(pci) < 0)
1053 chip->msi = 0;
1054 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1055 return -EIO;
cb53c626 1056 azx_init_pci(chip);
d804ad92 1057
0a673521 1058 hda_intel_init_chip(chip, true);
d804ad92 1059
a52ff34e
TI		 1060 /* power down again for link-controlled chips */
1061 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1062 !hda->need_i915_power)
1063 snd_hdac_display_power(bus, false);
1064
421a1252 1065 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 1066
1067 trace_azx_resume(chip);
1da177e4
LT		 1068 return 0;
1069}
b8dfc462
ML		 1070#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1071
3e6db33a
XZ		 1072#ifdef CONFIG_PM_SLEEP
1073/* put codec down to D3 at hibernation for Intel SKL+;
1074 * otherwise BIOS may still access the codec and screw up the driver
1075 */
3e6db33a
XZ		 1076static int azx_freeze_noirq(struct device *dev)
1077{
1078 struct pci_dev *pci = to_pci_dev(dev);
1079
1080 if (IS_SKL_PLUS(pci))
1081 pci_set_power_state(pci, PCI_D3hot);
1082
1083 return 0;
1084}
1085
1086static int azx_thaw_noirq(struct device *dev)
1087{
1088 struct pci_dev *pci = to_pci_dev(dev);
1089
1090 if (IS_SKL_PLUS(pci))
1091 pci_set_power_state(pci, PCI_D0);
1092
1093 return 0;
1094}
1095#endif /* CONFIG_PM_SLEEP */
1096
641d334b 1097#ifdef CONFIG_PM
b8dfc462
ML		 1098static int azx_runtime_suspend(struct device *dev)
1099{
1100 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1101 struct azx *chip;
1102 struct hda_intel *hda;
b8dfc462 1103
2d9772ef
TI		 1104 if (!card)
1105 return 0;
1106
1107 chip = card->private_data;
1108 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1109 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1110 return 0;
1111
364aa716 1112 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1113 return 0;
1114
7d4f606c
WX		 1115 /* enable controller wake up event */
1116 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1117 STATESTS_INT_MASK);
1118
b8dfc462 1119 azx_stop_chip(chip);
873ce8ad 1120 azx_enter_link_reset(chip);
b8dfc462 1121 azx_clear_irq_pending(chip);
795614dd
ML		 1122 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1123 && hda->need_i915_power)
98d8fc6c 1124 snd_hdac_display_power(azx_bus(chip), false);
e4d9e513 1125
785d8c4b 1126 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1127 return 0;
1128}
1129
1130static int azx_runtime_resume(struct device *dev)
1131{
1132 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1133 struct azx *chip;
1134 struct hda_intel *hda;
98d8fc6c 1135 struct hdac_bus *bus;
7d4f606c
WX		 1136 struct hda_codec *codec;
1137 int status;
b8dfc462 1138
2d9772ef
TI		 1139 if (!card)
1140 return 0;
1141
1142 chip = card->private_data;
1143 hda = container_of(chip, struct hda_intel, chip);
a52ff34e 1144 bus = azx_bus(chip);
1618e84a 1145 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1146 return 0;
1147
364aa716 1148 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1149 return 0;
1150
033ea349 1151 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
a52ff34e
TI		 1152 snd_hdac_display_power(bus, true);
1153 if (hda->need_i915_power)
bb03ed21 1154 snd_hdac_i915_set_bclk(bus);
a07187c9 1155 }
7d4f606c
WX		 1156
1157 /* Read STATESTS before controller reset */
1158 status = azx_readw(chip, STATESTS);
1159
b8dfc462 1160 azx_init_pci(chip);
0a673521 1161 hda_intel_init_chip(chip, true);
7d4f606c 1162
a41d1224
TI		 1163 if (status) {
1164 list_for_each_codec(codec, &chip->bus)
7d4f606c 1165 if (status & (1 << codec->addr))
2f35c630
TI		 1166 schedule_delayed_work(&codec->jackpoll_work,
1167 codec->jackpoll_interval);
7d4f606c
WX		 1168 }
1169
1170 /* disable controller Wake Up event*/
1171 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1172 ~STATESTS_INT_MASK);
1173
a52ff34e
TI		 1174 /* power down again for link-controlled chips */
1175 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1176 !hda->need_i915_power)
1177 snd_hdac_display_power(bus, false);
1178
785d8c4b 1179 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1180 return 0;
1181}
6eb827d2
TI		 1182
1183static int azx_runtime_idle(struct device *dev)
1184{
1185 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1186 struct azx *chip;
1187 struct hda_intel *hda;
1188
1189 if (!card)
1190 return 0;
6eb827d2 1191
2d9772ef
TI		 1192 chip = card->private_data;
1193 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1194 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1195 return 0;
1196
55ed9cd1 1197 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1198 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1199 return -EBUSY;
1200
1201 return 0;
1202}
1203
b8dfc462
ML		 1204static const struct dev_pm_ops azx_pm = {
1205 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1206#ifdef CONFIG_PM_SLEEP
1207 .freeze_noirq = azx_freeze_noirq,
1208 .thaw_noirq = azx_thaw_noirq,
1209#endif
6eb827d2 1210 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1211};
1212
68cb2b55
TI		 1213#define AZX_PM_OPS &azx_pm
1214#else
68cb2b55 1215#define AZX_PM_OPS NULL
b8dfc462 1216#endif /* CONFIG_PM */
1da177e4
LT		 1217
1218
48c8b0eb 1219static int azx_probe_continue(struct azx *chip);
a82d51ed 1220
8393ec4a 1221#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1222static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1223
a82d51ed
TI		 1224static void azx_vs_set_state(struct pci_dev *pci,
1225 enum vga_switcheroo_state state)
1226{
1227 struct snd_card *card = pci_get_drvdata(pci);
1228 struct azx *chip = card->private_data;
9a34af4a 1229 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1230 bool disabled;
1231
9a34af4a
TI		 1232 wait_for_completion(&hda->probe_wait);
1233 if (hda->init_failed)
a82d51ed
TI		 1234 return;
1235
1236 disabled = (state == VGA_SWITCHEROO_OFF);
1237 if (chip->disabled == disabled)
1238 return;
1239
a41d1224 1240 if (!hda->probe_continued) {
a82d51ed
TI		 1241 chip->disabled = disabled;
1242 if (!disabled) {
4e76a883
TI		 1243 dev_info(chip->card->dev,
1244 "Start delayed initialization\n");
5c90680e 1245 if (azx_probe_continue(chip) < 0) {
4e76a883 1246 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1247 hda->init_failed = true;
a82d51ed
TI		 1248 }
1249 }
1250 } else {
2b760d88 1251 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1252 disabled ? "Disabling" : "Enabling");
a82d51ed 1253 if (disabled) {
8928756d
DR		 1254 pm_runtime_put_sync_suspend(card->dev);
1255 azx_suspend(card->dev);
2b760d88 1256 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1257 * however we have no ACPI handle, so pci/acpi can't put us there,
1258 * put ourselves there */
1259 pci->current_state = PCI_D3cold;
a82d51ed 1260 chip->disabled = true;
a41d1224 1261 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1262 dev_warn(chip->card->dev,
1263 "Cannot lock devices!\n");
a82d51ed 1264 } else {
a41d1224 1265 snd_hda_unlock_devices(&chip->bus);
8928756d 1266 pm_runtime_get_noresume(card->dev);
a82d51ed 1267 chip->disabled = false;
8928756d 1268 azx_resume(card->dev);
a82d51ed
TI		 1269 }
1270 }
1271}
1272
1273static bool azx_vs_can_switch(struct pci_dev *pci)
1274{
1275 struct snd_card *card = pci_get_drvdata(pci);
1276 struct azx *chip = card->private_data;
9a34af4a 1277 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1278
9a34af4a
TI		 1279 wait_for_completion(&hda->probe_wait);
1280 if (hda->init_failed)
a82d51ed 1281 return false;
a41d1224 1282 if (chip->disabled || !hda->probe_continued)
a82d51ed 1283 return true;
a41d1224 1284 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1285 return false;
a41d1224 1286 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1287 return true;
1288}
1289
e23e7a14 1290static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1291{
9a34af4a 1292 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1293 struct pci_dev *p = get_bound_vga(chip->pci);
1294 if (p) {
4e76a883 1295 dev_info(chip->card->dev,
2b760d88 1296 "Handle vga_switcheroo audio client\n");
9a34af4a 1297 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1298 pci_dev_put(p);
1299 }
1300}
1301
1302static const struct vga_switcheroo_client_ops azx_vs_ops = {
1303 .set_gpu_state = azx_vs_set_state,
1304 .can_switch = azx_vs_can_switch,
1305};
1306
e23e7a14 1307static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1308{
9a34af4a 1309 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1310 int err;
1311
9a34af4a 1312 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1313 return 0;
1314 /* FIXME: currently only handling DIS controller
1315 * is there any machine with two switchable HDMI audio controllers?
1316 */
128960a9 1317 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
21b45676 1318 VGA_SWITCHEROO_DIS);
128960a9
TI		 1319 if (err < 0)
1320 return err;
9a34af4a 1321 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1322
1323 /* register as an optimus hdmi audio power domain */
8928756d 1324 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1325 &hda->hdmi_pm_domain);
128960a9 1326 return 0;
a82d51ed
TI		 1327}
1328#else
1329#define init_vga_switcheroo(chip) /* NOP */
1330#define register_vga_switcheroo(chip) 0
8393ec4a 1331#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1332#endif /* SUPPORT_VGA_SWITCHER */
1333
1da177e4
LT		 1334/*
1335 * destructor
1336 */
a98f90fd 1337static int azx_free(struct azx *chip)
1da177e4 1338{
c67e2228 1339 struct pci_dev *pci = chip->pci;
a07187c9 1340 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1341 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1342
364aa716 1343 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1344 pm_runtime_get_noresume(&pci->dev);
1345
65fcd41d
TI		 1346 azx_del_card_list(chip);
1347
9a34af4a
TI		 1348 hda->init_failed = 1; /* to be sure */
1349 complete_all(&hda->probe_wait);
f4c482a4 1350
9a34af4a 1351 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1352 if (chip->disabled && hda->probe_continued)
1353 snd_hda_unlock_devices(&chip->bus);
ab58d8cc 1354 if (hda->vga_switcheroo_registered) {
128960a9 1355 vga_switcheroo_unregister_client(chip->pci);
ab58d8cc
PW		 1356 vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1357 }
a82d51ed
TI		 1358 }
1359
a41d1224 1360 if (bus->chip_init) {
9ad593f6 1361 azx_clear_irq_pending(chip);
7833c3f8 1362 azx_stop_all_streams(chip);
cb53c626 1363 azx_stop_chip(chip);
1da177e4
LT		 1364 }
1365
a41d1224
TI		 1366 if (bus->irq >= 0)
1367 free_irq(bus->irq, (void*)chip);
68e7fffc 1368 if (chip->msi)
30b35399 1369 pci_disable_msi(chip->pci);
a41d1224 1370 iounmap(bus->remap_addr);
1da177e4 1371
67908994 1372 azx_free_stream_pages(chip);
a41d1224
TI		 1373 azx_free_streams(chip);
1374 snd_hdac_bus_exit(bus);
1375
a82d51ed
TI		 1376 if (chip->region_requested)
1377 pci_release_regions(chip->pci);
a41d1224 1378
1da177e4 1379 pci_disable_device(chip->pci);
4918cdab 1380#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1381 release_firmware(chip->fw);
4918cdab 1382#endif
98d8fc6c 1383
99a2008d 1384 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
795614dd 1385 if (hda->need_i915_power)
98d8fc6c
ML		 1386 snd_hdac_display_power(bus, false);
1387 snd_hdac_i915_exit(bus);
99a2008d 1388 }
a07187c9 1389 kfree(hda);
1da177e4
LT		 1390
1391 return 0;
1392}
1393
a41d1224
TI		 1394static int azx_dev_disconnect(struct snd_device *device)
1395{
1396 struct azx *chip = device->device_data;
1397
1398 chip->bus.shutdown = 1;
1399 return 0;
1400}
1401
a98f90fd 1402static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1403{
1404 return azx_free(device->device_data);
1405}
1406
8393ec4a 1407#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1408/*
2b760d88 1409 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1410 */
e23e7a14 1411static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1412{
1413 struct pci_dev *p;
1414
1415 /* check only discrete GPU */
1416 switch (pci->vendor) {
1417 case PCI_VENDOR_ID_ATI:
1418 case PCI_VENDOR_ID_AMD:
1419 case PCI_VENDOR_ID_NVIDIA:
1420 if (pci->devfn == 1) {
1421 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1422 pci->bus->number, 0);
1423 if (p) {
1424 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1425 return p;
1426 pci_dev_put(p);
1427 }
1428 }
1429 break;
1430 }
1431 return NULL;
1432}
1433
e23e7a14 1434static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1435{
1436 bool vga_inactive = false;
1437 struct pci_dev *p = get_bound_vga(pci);
1438
1439 if (p) {
12b78a7f 1440 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1441 vga_inactive = true;
1442 pci_dev_put(p);
1443 }
1444 return vga_inactive;
1445}
8393ec4a 1446#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1447
3372a153
TI		 1448/*
1449 * white/black-listing for position_fix
1450 */
e23e7a14 1451static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1452 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1453 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1454 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1455 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1456 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1457 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1458 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1459 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1460 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1461 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1462 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1463 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1464 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1465 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1466 {}
1467};
1468
e23e7a14 1469static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1470{
1471 const struct snd_pci_quirk *q;
1472
c673ba1c 1473 switch (fix) {
1dac6695 1474 case POS_FIX_AUTO:
c673ba1c
TI		 1475 case POS_FIX_LPIB:
1476 case POS_FIX_POSBUF:
4cb36310 1477 case POS_FIX_VIACOMBO:
a6f2fd55 1478 case POS_FIX_COMBO:
f87e7f25 1479 case POS_FIX_SKL:
c673ba1c
TI		 1480 return fix;
1481 }
1482
c673ba1c
TI		 1483 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1484 if (q) {
4e76a883
TI		 1485 dev_info(chip->card->dev,
1486 "position_fix set to %d for device %04x:%04x\n",
1487 q->value, q->subvendor, q->subdevice);
c673ba1c 1488 return q->value;
3372a153 1489 }
bdd9ef24
DH		 1490
1491 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1492 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1493 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1494 return POS_FIX_VIACOMBO;
9477c58e
TI		 1495 }
1496 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1497 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1498 return POS_FIX_LPIB;
bdd9ef24 1499 }
f87e7f25
TI		 1500 if (IS_SKL_PLUS(chip->pci)) {
1501 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1502 return POS_FIX_SKL;
1503 }
c673ba1c 1504 return POS_FIX_AUTO;
3372a153
TI		 1505}
1506
b6050ef6
TI		 1507static void assign_position_fix(struct azx *chip, int fix)
1508{
1509 static azx_get_pos_callback_t callbacks[] = {
1510 [POS_FIX_AUTO] = NULL,
1511 [POS_FIX_LPIB] = azx_get_pos_lpib,
1512 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1513 [POS_FIX_VIACOMBO] = azx_via_get_position,
1514 [POS_FIX_COMBO] = azx_get_pos_lpib,
f87e7f25 1515 [POS_FIX_SKL] = azx_get_pos_skl,
b6050ef6
TI		 1516 };
1517
1518 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1519
1520 /* combo mode uses LPIB only for playback */
1521 if (fix == POS_FIX_COMBO)
1522 chip->get_position[1] = NULL;
1523
f87e7f25 1524 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1525 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1526 chip->get_delay[0] = chip->get_delay[1] =
1527 azx_get_delay_from_lpib;
1528 }
1529
1530}
1531
669ba27a
TI		 1532/*
1533 * black-lists for probe_mask
1534 */
e23e7a14 1535static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1536 /* Thinkpad often breaks the controller communication when accessing
1537 * to the non-working (or non-existing) modem codec slot.
1538 */
1539 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1540 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1541 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1542 /* broken BIOS */
1543 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1544 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1545 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1546 /* forced codec slots */
93574844 1547 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1548 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1549 /* WinFast VP200 H (Teradici) user reported broken communication */
1550 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1551 {}
1552};
1553
f1eaaeec
TI		 1554#define AZX_FORCE_CODEC_MASK 0x100
1555
e23e7a14 1556static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1557{
1558 const struct snd_pci_quirk *q;
1559
f1eaaeec
TI		 1560 chip->codec_probe_mask = probe_mask[dev];
1561 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1562 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1563 if (q) {
4e76a883
TI		 1564 dev_info(chip->card->dev,
1565 "probe_mask set to 0x%x for device %04x:%04x\n",
1566 q->value, q->subvendor, q->subdevice);
f1eaaeec 1567 chip->codec_probe_mask = q->value;
669ba27a
TI		 1568 }
1569 }
f1eaaeec
TI		 1570
1571 /* check forced option */
1572 if (chip->codec_probe_mask != -1 &&
1573 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1574 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1575 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1576 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1577 }
669ba27a
TI		 1578}
1579
4d8e22e0 1580/*
71623855 1581 * white/black-list for enable_msi
4d8e22e0 1582 */
e23e7a14 1583static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1584 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1585 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1586 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1587 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1588 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1589 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1590 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1591 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1592 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1593 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1594 {}
1595};
1596
e23e7a14 1597static void check_msi(struct azx *chip)
4d8e22e0
TI		 1598{
1599 const struct snd_pci_quirk *q;
1600
71623855
TI		 1601 if (enable_msi >= 0) {
1602 chip->msi = !!enable_msi;
4d8e22e0 1603 return;
71623855
TI		 1604 }
1605 chip->msi = 1; /* enable MSI as default */
1606 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1607 if (q) {
4e76a883
TI		 1608 dev_info(chip->card->dev,
1609 "msi for device %04x:%04x set to %d\n",
1610 q->subvendor, q->subdevice, q->value);
4d8e22e0 1611 chip->msi = q->value;
80c43ed7
TI		 1612 return;
1613 }
1614
1615 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1616 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1617 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1618 chip->msi = 0;
4d8e22e0
TI		 1619 }
1620}
1621
a1585d76 1622/* check the snoop mode availability */
e23e7a14 1623static void azx_check_snoop_available(struct azx *chip)
a1585d76 1624{
7c732015 1625 int snoop = hda_snoop;
a1585d76 1626
7c732015
TI		 1627 if (snoop >= 0) {
1628 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1629 snoop ? "snoop" : "non-snoop");
1630 chip->snoop = snoop;
1631 return;
1632 }
1633
1634 snoop = true;
37e661ee
TI		 1635 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1636 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1637 /* force to non-snoop mode for a new VIA controller
1638 * when BIOS is set
1639 */
7c732015
TI		 1640 u8 val;
1641 pci_read_config_byte(chip->pci, 0x42, &val);
1642 if (!(val & 0x80) && chip->pci->revision == 0x30)
1643 snoop = false;
a1585d76
TI		 1644 }
1645
37e661ee
TI		 1646 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1647 snoop = false;
1648
7c732015
TI		 1649 chip->snoop = snoop;
1650 if (!snoop)
1651 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1652}
669ba27a 1653
99a2008d
WX		 1654static void azx_probe_work(struct work_struct *work)
1655{
9a34af4a
TI		 1656 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1657 azx_probe_continue(&hda->chip);
99a2008d 1658}
99a2008d 1659
4f0189be
TI		 1660static int default_bdl_pos_adj(struct azx *chip)
1661{
2cf721db
TI		 1662 /* some exceptions: Atoms seem problematic with value 1 */
1663 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1664 switch (chip->pci->device) {
1665 case 0x0f04: /* Baytrail */
1666 case 0x2284: /* Braswell */
1667 return 32;
1668 }
1669 }
1670
4f0189be
TI		 1671 switch (chip->driver_type) {
1672 case AZX_DRIVER_ICH:
1673 case AZX_DRIVER_PCH:
1674 return 1;
1675 default:
1676 return 32;
1677 }
1678}
1679
1da177e4
LT		 1680/*
1681 * constructor
1682 */
a43ff5ba
TI		 1683static const struct hdac_io_ops pci_hda_io_ops;
1684static const struct hda_controller_ops pci_hda_ops;
1685
e23e7a14
BP		 1686static int azx_create(struct snd_card *card, struct pci_dev *pci,
1687 int dev, unsigned int driver_caps,
1688 struct azx **rchip)
1da177e4 1689{
a98f90fd 1690 static struct snd_device_ops ops = {
a41d1224 1691 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1692 .dev_free = azx_dev_free,
1693 };
a07187c9 1694 struct hda_intel *hda;
a82d51ed
TI		 1695 struct azx *chip;
1696 int err;
1da177e4
LT		 1697
1698 *rchip = NULL;
bcd72003 1699
927fc866
PM		 1700 err = pci_enable_device(pci);
1701 if (err < 0)
1da177e4
LT		 1702 return err;
1703
a07187c9
ML		 1704 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1705 if (!hda) {
1da177e4
LT		 1706 pci_disable_device(pci);
1707 return -ENOMEM;
1708 }
1709
a07187c9 1710 chip = &hda->chip;
62932df8 1711 mutex_init(&chip->open_mutex);
1da177e4
LT		 1712 chip->card = card;
1713 chip->pci = pci;
a43ff5ba 1714 chip->ops = &pci_hda_ops;
9477c58e
TI		 1715 chip->driver_caps = driver_caps;
1716 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1717 check_msi(chip);
555e219f 1718 chip->dev_index = dev;
749ee287 1719 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1720 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1721 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1722 INIT_LIST_HEAD(&hda->list);
a82d51ed 1723 init_vga_switcheroo(chip);
9a34af4a 1724 init_completion(&hda->probe_wait);
1da177e4 1725
b6050ef6 1726 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1727
5aba4f8e 1728 check_probe_mask(chip, dev);
3372a153 1729
41438f13
TI		 1730 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1731 chip->fallback_to_single_cmd = 1;
1732 else /* explicitly set to single_cmd or not */
1733 chip->single_cmd = single_cmd;
1734
a1585d76 1735 azx_check_snoop_available(chip);
c74db86b 1736
4f0189be
TI		 1737 if (bdl_pos_adj[dev] < 0)
1738 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1739 else
1740 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1741
a41d1224
TI		 1742 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1743 if (err < 0) {
1744 kfree(hda);
1745 pci_disable_device(pci);
1746 return err;
1747 }
1748
7d9a1808
TI		 1749 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1750 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1751 chip->bus.needs_damn_long_delay = 1;
1752 }
1753
a82d51ed
TI		 1754 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1755 if (err < 0) {
4e76a883 1756 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1757 azx_free(chip);
1758 return err;
1759 }
1760
99a2008d 1761 /* continue probing in work context as may trigger request module */
9a34af4a 1762 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1763
a82d51ed 1764 *rchip = chip;
99a2008d 1765
a82d51ed
TI		 1766 return 0;
1767}
1768
48c8b0eb 1769static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1770{
1771 int dev = chip->dev_index;
1772 struct pci_dev *pci = chip->pci;
1773 struct snd_card *card = chip->card;
a41d1224 1774 struct hdac_bus *bus = azx_bus(chip);
67908994 1775 int err;
a82d51ed 1776 unsigned short gcap;
413cbf46 1777 unsigned int dma_bits = 64;
a82d51ed 1778
07e4ca50
TI		 1779#if BITS_PER_LONG != 64
1780 /* Fix up base address on ULI M5461 */
1781 if (chip->driver_type == AZX_DRIVER_ULI) {
1782 u16 tmp3;
1783 pci_read_config_word(pci, 0x40, &tmp3);
1784 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1785 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1786 }
1787#endif
1788
927fc866 1789 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1790 if (err < 0)
1da177e4 1791 return err;
a82d51ed 1792 chip->region_requested = 1;
1da177e4 1793
a41d1224
TI		 1794 bus->addr = pci_resource_start(pci, 0);
1795 bus->remap_addr = pci_ioremap_bar(pci, 0);
1796 if (bus->remap_addr == NULL) {
4e76a883 1797 dev_err(card->dev, "ioremap error\n");
a82d51ed 1798 return -ENXIO;
1da177e4
LT		 1799 }
1800
50279d9b
GS		 1801 if (IS_SKL_PLUS(pci))
1802 snd_hdac_bus_parse_capabilities(bus);
1803
1804 /*
1805 * Some Intel CPUs has always running timer (ART) feature and
1806 * controller may have Global time sync reporting capability, so
1807 * check both of these before declaring synchronized time reporting
1808 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1809 */
1810 chip->gts_present = false;
1811
1812#ifdef CONFIG_X86
1813 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1814 chip->gts_present = true;
1815#endif
1816
db79afa1
BH		 1817 if (chip->msi) {
1818 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1819 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1820 pci->no_64bit_msi = true;
1821 }
68e7fffc
TI		 1822 if (pci_enable_msi(pci) < 0)
1823 chip->msi = 0;
db79afa1 1824 }
7376d013 1825
a82d51ed
TI		 1826 if (azx_acquire_irq(chip, 0) < 0)
1827 return -EBUSY;
1da177e4
LT		 1828
1829 pci_set_master(pci);
a41d1224 1830 synchronize_irq(bus->irq);
1da177e4 1831
bcd72003 1832 gcap = azx_readw(chip, GCAP);
4e76a883 1833 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1834
413cbf46
TI		 1835 /* AMD devices support 40 or 48bit DMA, take the safe one */
1836 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1837 dma_bits = 40;
1838
dc4c2e6b 1839 /* disable SB600 64bit support for safety */
9477c58e 1840 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1841 struct pci_dev *p_smbus;
413cbf46 1842 dma_bits = 40;
dc4c2e6b
AB		 1843 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1844 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1845 NULL);
1846 if (p_smbus) {
1847 if (p_smbus->revision < 0x30)
fb1d8ac2 1848 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1849 pci_dev_put(p_smbus);
1850 }
1851 }
09240cf4 1852
3ab7511e
AB		 1853 /* NVidia hardware normally only supports up to 40 bits of DMA */
1854 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1855 dma_bits = 40;
1856
9477c58e
TI		 1857 /* disable 64bit DMA address on some devices */
1858 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1859 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1860 gcap &= ~AZX_GCAP_64OK;
9477c58e 1861 }
396087ea 1862
2ae66c26 1863 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1864 if (align_buffer_size >= 0)
1865 chip->align_buffer_size = !!align_buffer_size;
1866 else {
103884a3 1867 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1868 chip->align_buffer_size = 0;
7bfe059e
TI		 1869 else
1870 chip->align_buffer_size = 1;
1871 }
2ae66c26 1872
cf7aaca8 1873 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1874 if (!(gcap & AZX_GCAP_64OK))
1875 dma_bits = 32;
412b979c
QL		 1876 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1877 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1878 } else {
412b979c
QL		 1879 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1880 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1881 }
cf7aaca8 1882
8b6ed8e7
TI		 1883 /* read number of streams from GCAP register instead of using
1884 * hardcoded value
1885 */
1886 chip->capture_streams = (gcap >> 8) & 0x0f;
1887 chip->playback_streams = (gcap >> 12) & 0x0f;
1888 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1889 /* gcap didn't give any info, switching to old method */
1890
1891 switch (chip->driver_type) {
1892 case AZX_DRIVER_ULI:
1893 chip->playback_streams = ULI_NUM_PLAYBACK;
1894 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1895 break;
1896 case AZX_DRIVER_ATIHDMI:
1815b34a 1897 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1898 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1899 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1900 break;
c4da29ca 1901 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1902 default:
1903 chip->playback_streams = ICH6_NUM_PLAYBACK;
1904 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1905 break;
1906 }
07e4ca50 1907 }
8b6ed8e7
TI		 1908 chip->capture_index_offset = 0;
1909 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1910 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1911
df56c3db
JK		 1912 /* sanity check for the SDxCTL.STRM field overflow */
1913 if (chip->num_streams > 15 &&
1914 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1915 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1916 "forcing separate stream tags", chip->num_streams);
1917 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1918 }
1919
a41d1224
TI		 1920 /* initialize streams */
1921 err = azx_init_streams(chip);
81740861 1922 if (err < 0)
a82d51ed 1923 return err;
1da177e4 1924
a41d1224
TI		 1925 err = azx_alloc_stream_pages(chip);
1926 if (err < 0)
1927 return err;
1da177e4
LT		 1928
1929 /* initialize chip */
cb53c626 1930 azx_init_pci(chip);
e4d9e513 1931
bb03ed21
TI		 1932 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1933 snd_hdac_i915_set_bclk(bus);
e4d9e513 1934
0a673521 1935 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1936
1937 /* codec detection */
a41d1224 1938 if (!azx_bus(chip)->codec_mask) {
4e76a883 1939 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1940 return -ENODEV;
1da177e4
LT		 1941 }
1942
07e4ca50 1943 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1944 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1945 sizeof(card->shortname));
1946 snprintf(card->longname, sizeof(card->longname),
1947 "%s at 0x%lx irq %i",
a41d1224 1948 card->shortname, bus->addr, bus->irq);
07e4ca50 1949
1da177e4 1950 return 0;
1da177e4
LT		 1951}
1952
97c6a3d1 1953#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1954/* callback from request_firmware_nowait() */
1955static void azx_firmware_cb(const struct firmware *fw, void *context)
1956{
1957 struct snd_card *card = context;
1958 struct azx *chip = card->private_data;
1959 struct pci_dev *pci = chip->pci;
1960
1961 if (!fw) {
4e76a883 1962 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1963 goto error;
1964 }
1965
1966 chip->fw = fw;
1967 if (!chip->disabled) {
1968 /* continue probing */
1969 if (azx_probe_continue(chip))
1970 goto error;
1971 }
1972 return; /* OK */
1973
1974 error:
1975 snd_card_free(card);
1976 pci_set_drvdata(pci, NULL);
1977}
97c6a3d1 1978#endif
5cb543db 1979
40830813
DR		 1980/*
1981 * HDA controller ops.
1982 */
1983
1984/* PCI register access. */
db291e36 1985static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1986{
1987 writel(value, addr);
1988}
1989
db291e36 1990static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1991{
1992 return readl(addr);
1993}
1994
db291e36 1995static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1996{
1997 writew(value, addr);
1998}
1999
db291e36 2000static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 2001{
2002 return readw(addr);
2003}
2004
db291e36 2005static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 2006{
2007 writeb(value, addr);
2008}
2009
db291e36 2010static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 2011{
2012 return readb(addr);
2013}
2014
f46ea609
DR		 2015static int disable_msi_reset_irq(struct azx *chip)
2016{
a41d1224 2017 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 2018 int err;
2019
a41d1224
TI		 2020 free_irq(bus->irq, chip);
2021 bus->irq = -1;
f46ea609
DR		 2022 pci_disable_msi(chip->pci);
2023 chip->msi = 0;
2024 err = azx_acquire_irq(chip, 1);
2025 if (err < 0)
2026 return err;
2027
2028 return 0;
2029}
2030
b419b35b 2031/* DMA page allocation helpers. */
a43ff5ba 2032static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 2033 int type,
2034 size_t size,
2035 struct snd_dma_buffer *buf)
2036{
a41d1224 2037 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 2038 int err;
2039
2040 err = snd_dma_alloc_pages(type,
a43ff5ba 2041 bus->dev,
b419b35b
DR		 2042 size, buf);
2043 if (err < 0)
2044 return err;
2045 mark_pages_wc(chip, buf, true);
2046 return 0;
2047}
2048
a43ff5ba 2049static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 2050{
a41d1224 2051 struct azx *chip = bus_to_azx(bus);
a43ff5ba 2052
b419b35b
DR		 2053 mark_pages_wc(chip, buf, false);
2054 snd_dma_free_pages(buf);
2055}
2056
2057static int substream_alloc_pages(struct azx *chip,
2058 struct snd_pcm_substream *substream,
2059 size_t size)
2060{
2061 struct azx_dev *azx_dev = get_azx_dev(substream);
2062 int ret;
2063
2064 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 2065 ret = snd_pcm_lib_malloc_pages(substream, size);
2066 if (ret < 0)
2067 return ret;
2068 mark_runtime_wc(chip, azx_dev, substream, true);
2069 return 0;
2070}
2071
2072static int substream_free_pages(struct azx *chip,
2073 struct snd_pcm_substream *substream)
2074{
2075 struct azx_dev *azx_dev = get_azx_dev(substream);
2076 mark_runtime_wc(chip, azx_dev, substream, false);
2077 return snd_pcm_lib_free_pages(substream);
2078}
2079
8769b278
DR		 2080static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2081 struct vm_area_struct *area)
2082{
2083#ifdef CONFIG_X86
2084 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2085 struct azx *chip = apcm->chip;
3b70bdba 2086 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 2087 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2088#endif
2089}
2090
a43ff5ba 2091static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 2092 .reg_writel = pci_azx_writel,
2093 .reg_readl = pci_azx_readl,
2094 .reg_writew = pci_azx_writew,
2095 .reg_readw = pci_azx_readw,
2096 .reg_writeb = pci_azx_writeb,
2097 .reg_readb = pci_azx_readb,
b419b35b
DR		 2098 .dma_alloc_pages = dma_alloc_pages,
2099 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 2100};
2101
2102static const struct hda_controller_ops pci_hda_ops = {
2103 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 2104 .substream_alloc_pages = substream_alloc_pages,
2105 .substream_free_pages = substream_free_pages,
8769b278 2106 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 2107 .position_check = azx_position_check,
17eccb27 2108 .link_power = azx_intel_link_power,
40830813
DR		 2109};
2110
e23e7a14
BP		 2111static int azx_probe(struct pci_dev *pci,
2112 const struct pci_device_id *pci_id)
1da177e4 2113{
5aba4f8e 2114 static int dev;
a98f90fd 2115 struct snd_card *card;
9a34af4a 2116 struct hda_intel *hda;
a98f90fd 2117 struct azx *chip;
aad730d0 2118 bool schedule_probe;
927fc866 2119 int err;
1da177e4 2120
5aba4f8e
TI		 2121 if (dev >= SNDRV_CARDS)
2122 return -ENODEV;
2123 if (!enable[dev]) {
2124 dev++;
2125 return -ENOENT;
2126 }
2127
60c5772b
TI		 2128 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2129 0, &card);
e58de7ba 2130 if (err < 0) {
4e76a883 2131 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2132 return err;
1da177e4
LT		 2133 }
2134
a43ff5ba 2135 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2136 if (err < 0)
2137 goto out_free;
421a1252 2138 card->private_data = chip;
9a34af4a 2139 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2140
2141 pci_set_drvdata(pci, card);
2142
2143 err = register_vga_switcheroo(chip);
2144 if (err < 0) {
2b760d88 2145 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2146 goto out_free;
2147 }
2148
2149 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2150 dev_info(card->dev, "VGA controller is disabled\n");
2151 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2152 chip->disabled = true;
2153 }
2154
aad730d0 2155 schedule_probe = !chip->disabled;
1da177e4 2156
4918cdab
TI		 2157#ifdef CONFIG_SND_HDA_PATCH_LOADER
2158 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2159 dev_info(card->dev, "Applying patch firmware '%s'\n",
2160 patch[dev]);
5cb543db
TI		 2161 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2162 &pci->dev, GFP_KERNEL, card,
2163 azx_firmware_cb);
4918cdab
TI		 2164 if (err < 0)
2165 goto out_free;
aad730d0 2166 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2167 }
2168#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2169
aad730d0 2170#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2171 if (CONTROLLER_IN_GPU(pci))
2172 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2173#endif
99a2008d 2174
aad730d0 2175 if (schedule_probe)
9a34af4a 2176 schedule_work(&hda->probe_work);
a82d51ed 2177
a82d51ed 2178 dev++;
88d071fc 2179 if (chip->disabled)
9a34af4a 2180 complete_all(&hda->probe_wait);
a82d51ed
TI		 2181 return 0;
2182
2183out_free:
2184 snd_card_free(card);
2185 return err;
2186}
2187
e62a42ae
DR		 2188/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2189static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2190 [AZX_DRIVER_NVIDIA] = 8,
2191 [AZX_DRIVER_TERA] = 1,
2192};
2193
48c8b0eb 2194static int azx_probe_continue(struct azx *chip)
a82d51ed 2195{
9a34af4a 2196 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2197 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2198 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2199 int dev = chip->dev_index;
2200 int err;
2201
a41d1224 2202 hda->probe_continued = 1;
795614dd
ML		 2203
2204 /* Request display power well for the HDA controller or codec. For
2205 * Haswell/Broadwell, both the display HDA controller and codec need
2206 * this power. For other platforms, like Baytrail/Braswell, only the
2207 * display codec needs the power and it can be released after probe.
2208 */
99a2008d 2209 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
03b135ce
LY		 2210 /* HSW/BDW controllers need this power */
2211 if (CONTROLLER_IN_GPU(pci))
2bd1f73f
ML		 2212 hda->need_i915_power = 1;
2213
98d8fc6c 2214 err = snd_hdac_i915_init(bus);
535115b5
TI		 2215 if (err < 0) {
2216 /* if the controller is bound only with HDMI/DP
2217 * (for HSW and BDW), we need to abort the probe;
2218 * for other chips, still continue probing as other
2219 * codecs can be on the same link.
2220 */
bed2e98e
TI		 2221 if (CONTROLLER_IN_GPU(pci)) {
2222 dev_err(chip->card->dev,
2223 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2224 goto out_free;
bed2e98e 2225 } else
535115b5
TI		 2226 goto skip_i915;
2227 }
795614dd 2228
98d8fc6c 2229 err = snd_hdac_display_power(bus, true);
74b0c2d7
TI		 2230 if (err < 0) {
2231 dev_err(chip->card->dev,
2232 "Cannot turn on display power on i915\n");
795614dd 2233 goto i915_power_fail;
74b0c2d7 2234 }
99a2008d
WX		 2235 }
2236
bf06848b 2237 skip_i915:
5c90680e
TI		 2238 err = azx_first_init(chip);
2239 if (err < 0)
2240 goto out_free;
2241
2dca0bba
JK		 2242#ifdef CONFIG_SND_HDA_INPUT_BEEP
2243 chip->beep_mode = beep_mode[dev];
2244#endif
2245
1da177e4 2246 /* create codec instances */
96d2bd6e 2247 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2248 if (err < 0)
2249 goto out_free;
96d2bd6e 2250
4ea6fbc8 2251#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2252 if (chip->fw) {
a41d1224 2253 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2254 chip->fw->data);
4ea6fbc8
TI		 2255 if (err < 0)
2256 goto out_free;
e39ae856 2257#ifndef CONFIG_PM
4918cdab
TI		 2258 release_firmware(chip->fw); /* no longer needed */
2259 chip->fw = NULL;
e39ae856 2260#endif
4ea6fbc8
TI		 2261 }
2262#endif
10e77dda 2263 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2264 err = azx_codec_configure(chip);
2265 if (err < 0)
2266 goto out_free;
2267 }
1da177e4 2268
a82d51ed 2269 err = snd_card_register(chip->card);
41dda0fd
WF		 2270 if (err < 0)
2271 goto out_free;
1da177e4 2272
cb53c626 2273 chip->running = 1;
65fcd41d 2274 azx_add_card_list(chip);
a41d1224 2275 snd_hda_set_power_save(&chip->bus, power_save * 1000);
364aa716 2276 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
30ff5957 2277 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2278
41dda0fd 2279out_free:
795614dd
ML		 2280 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2281 && !hda->need_i915_power)
98d8fc6c 2282 snd_hdac_display_power(bus, false);
795614dd
ML		 2283
2284i915_power_fail:
88d071fc 2285 if (err < 0)
9a34af4a
TI		 2286 hda->init_failed = 1;
2287 complete_all(&hda->probe_wait);
41dda0fd 2288 return err;
1da177e4
LT		 2289}
2290
e23e7a14 2291static void azx_remove(struct pci_dev *pci)
1da177e4 2292{
9121947d 2293 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2294 struct azx *chip;
2295 struct hda_intel *hda;
2296
2297 if (card) {
0b8c8219 2298 /* cancel the pending probing work */
991f86d7
TI		 2299 chip = card->private_data;
2300 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2301 /* FIXME: below is an ugly workaround.
2302 * Both device_release_driver() and driver_probe_device()
2303 * take *both* the device's and its parent's lock before
2304 * calling the remove() and probe() callbacks. The codec
2305 * probe takes the locks of both the codec itself and its
2306 * parent, i.e. the PCI controller dev. Meanwhile, when
2307 * the PCI controller is unbound, it takes its lock, too
2308 * ==> ouch, a deadlock!
2309 * As a workaround, we unlock temporarily here the controller
2310 * device during cancel_work_sync() call.
2311 */
2312 device_unlock(&pci->dev);
0b8c8219 2313 cancel_work_sync(&hda->probe_work);
ab949d51 2314 device_lock(&pci->dev);
b8dfc462 2315
9121947d 2316 snd_card_free(card);
991f86d7 2317 }
1da177e4
LT		 2318}
2319
b2a0bafa
TI		 2320static void azx_shutdown(struct pci_dev *pci)
2321{
2322 struct snd_card *card = pci_get_drvdata(pci);
2323 struct azx *chip;
2324
2325 if (!card)
2326 return;
2327 chip = card->private_data;
2328 if (chip && chip->running)
2329 azx_stop_chip(chip);
2330}
2331
1da177e4 2332/* PCI IDs */
6f51f6cf 2333static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2334 /* CPT */
9477c58e 2335 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2336 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2337 /* PBG */
9477c58e 2338 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2339 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2340 /* Panther Point */
9477c58e 2341 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2342 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2343 /* Lynx Point */
2344 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2345 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2346 /* 9 Series */
2347 { PCI_DEVICE(0x8086, 0x8ca0),
2348 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2349 /* Wellsburg */
2350 { PCI_DEVICE(0x8086, 0x8d20),
2351 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2352 { PCI_DEVICE(0x8086, 0x8d21),
2353 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2354 /* Lewisburg */
2355 { PCI_DEVICE(0x8086, 0xa1f0),
e7480b34 2356 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
5cf92c8b 2357 { PCI_DEVICE(0x8086, 0xa270),
e7480b34 2358 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
144dad99
JR		 2359 /* Lynx Point-LP */
2360 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2361 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2362 /* Lynx Point-LP */
2363 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2364 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2365 /* Wildcat Point-LP */
2366 { PCI_DEVICE(0x8086, 0x9ca0),
2367 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2368 /* Sunrise Point */
2369 { PCI_DEVICE(0x8086, 0xa170),
db48abf4 2370 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2371 /* Sunrise Point-LP */
2372 { PCI_DEVICE(0x8086, 0x9d70),
d6795827 2373 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2374 /* Kabylake */
2375 { PCI_DEVICE(0x8086, 0xa171),
2376 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2377 /* Kabylake-LP */
2378 { PCI_DEVICE(0x8086, 0x9d71),
2379 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2380 /* Kabylake-H */
2381 { PCI_DEVICE(0x8086, 0xa2f0),
2382 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
e79b0006
MD		 2383 /* Coffelake */
2384 { PCI_DEVICE(0x8086, 0xa348),
2385 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE},
c87693da
LH		 2386 /* Broxton-P(Apollolake) */
2387 { PCI_DEVICE(0x8086, 0x5a98),
2388 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2389 /* Broxton-T */
2390 { PCI_DEVICE(0x8086, 0x1a98),
2391 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
44b46d73
VK		 2392 /* Gemini-Lake */
2393 { PCI_DEVICE(0x8086, 0x3198),
2394 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2395 /* Haswell */
4a7c516b 2396 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2397 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2398 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2399 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2400 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2401 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2402 /* Broadwell */
2403 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2404 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2405 /* 5 Series/3400 */
2406 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2407 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2408 /* Poulsbo */
9477c58e 2409 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2410 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2411 /* Oaktrail */
09904b95 2412 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2413 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2414 /* BayTrail */
2415 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2416 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2417 /* Braswell */
2418 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2419 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2420 /* ICH6 */
8b0bd226 2421 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2422 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2423 /* ICH7 */
8b0bd226 2424 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2425 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2426 /* ESB2 */
8b0bd226 2427 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2428 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2429 /* ICH8 */
8b0bd226 2430 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2431 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2432 /* ICH9 */
8b0bd226 2433 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2434 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2435 /* ICH9 */
8b0bd226 2436 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2437 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2438 /* ICH10 */
8b0bd226 2439 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2440 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2441 /* ICH10 */
8b0bd226 2442 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2443 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2444 /* Generic Intel */
2445 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2446 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2447 .class_mask = 0xffffff,
103884a3 2448 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2449 /* ATI SB 450/600/700/800/900 */
2450 { PCI_DEVICE(0x1002, 0x437b),
2451 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2452 { PCI_DEVICE(0x1002, 0x4383),
2453 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2454 /* AMD Hudson */
2455 { PCI_DEVICE(0x1022, 0x780d),
2456 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2457 /* ATI HDMI */
fd48331f
MSB		 2458 { PCI_DEVICE(0x1002, 0x0002),
2459 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
650474fb
AD		 2460 { PCI_DEVICE(0x1002, 0x1308),
2461 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2462 { PCI_DEVICE(0x1002, 0x157a),
2463 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
d716fb03
AB		 2464 { PCI_DEVICE(0x1002, 0x15b3),
2465 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2466 { PCI_DEVICE(0x1002, 0x793b),
2467 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2468 { PCI_DEVICE(0x1002, 0x7919),
2469 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2470 { PCI_DEVICE(0x1002, 0x960f),
2471 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2472 { PCI_DEVICE(0x1002, 0x970f),
2473 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2474 { PCI_DEVICE(0x1002, 0x9840),
2475 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2476 { PCI_DEVICE(0x1002, 0xaa00),
2477 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2478 { PCI_DEVICE(0x1002, 0xaa08),
2479 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2480 { PCI_DEVICE(0x1002, 0xaa10),
2481 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2482 { PCI_DEVICE(0x1002, 0xaa18),
2483 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2484 { PCI_DEVICE(0x1002, 0xaa20),
2485 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2486 { PCI_DEVICE(0x1002, 0xaa28),
2487 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2488 { PCI_DEVICE(0x1002, 0xaa30),
2489 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2490 { PCI_DEVICE(0x1002, 0xaa38),
2491 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2492 { PCI_DEVICE(0x1002, 0xaa40),
2493 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2494 { PCI_DEVICE(0x1002, 0xaa48),
2495 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2496 { PCI_DEVICE(0x1002, 0xaa50),
2497 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2498 { PCI_DEVICE(0x1002, 0xaa58),
2499 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2500 { PCI_DEVICE(0x1002, 0xaa60),
2501 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2502 { PCI_DEVICE(0x1002, 0xaa68),
2503 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2504 { PCI_DEVICE(0x1002, 0xaa80),
2505 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2506 { PCI_DEVICE(0x1002, 0xaa88),
2507 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2508 { PCI_DEVICE(0x1002, 0xaa90),
2509 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510 { PCI_DEVICE(0x1002, 0xaa98),
2511 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2512 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2513 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2514 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2515 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2516 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2517 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2518 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2519 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2520 { PCI_DEVICE(0x1002, 0xaac0),
2521 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2522 { PCI_DEVICE(0x1002, 0xaac8),
2523 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2524 { PCI_DEVICE(0x1002, 0xaad8),
2525 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2526 { PCI_DEVICE(0x1002, 0xaae8),
2527 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
8eb22214
MSB		 2528 { PCI_DEVICE(0x1002, 0xaae0),
2529 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2530 { PCI_DEVICE(0x1002, 0xaaf0),
2531 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2532 /* VIA VT8251/VT8237A */
26f05717 2533 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2534 /* VIA GFX VT7122/VX900 */
2535 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2536 /* VIA GFX VT6122/VX11 */
2537 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2538 /* SIS966 */
2539 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2540 /* ULI M5461 */
2541 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2542 /* NVIDIA MCP */
0c2fd1bf
TI		 2543 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2544 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2545 .class_mask = 0xffffff,
9477c58e 2546 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2547 /* Teradici */
9477c58e
TI		 2548 { PCI_DEVICE(0x6549, 0x1200),
2549 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2550 { PCI_DEVICE(0x6549, 0x2200),
2551 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2552 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2553 /* CTHDA chips */
2554 { PCI_DEVICE(0x1102, 0x0010),
2555 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2556 { PCI_DEVICE(0x1102, 0x0012),
2557 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2558#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2559 /* the following entry conflicts with snd-ctxfi driver,
2560 * as ctxfi driver mutates from HD-audio to native mode with
2561 * a special command sequence.
2562 */
4e01f54b
TI		 2563 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2564 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2565 .class_mask = 0xffffff,
9477c58e 2566 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2567 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2568#else
2569 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2570 { PCI_DEVICE(0x1102, 0x0009),
2571 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2572 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2573#endif
c563f473
TI		 2574 /* CM8888 */
2575 { PCI_DEVICE(0x13f6, 0x5011),
2576 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2577 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2578 /* Vortex86MX */
2579 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2580 /* VMware HDAudio */
2581 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2582 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2583 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2584 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2585 .class_mask = 0xffffff,
9477c58e 2586 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2587 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2588 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2589 .class_mask = 0xffffff,
9477c58e 2590 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2591 { 0, }
2592};
2593MODULE_DEVICE_TABLE(pci, azx_ids);
2594
2595/* pci_driver definition */
e9f66d9b 2596static struct pci_driver azx_driver = {
3733e424 2597 .name = KBUILD_MODNAME,
1da177e4
LT		 2598 .id_table = azx_ids,
2599 .probe = azx_probe,
e23e7a14 2600 .remove = azx_remove,
b2a0bafa 2601 .shutdown = azx_shutdown,
68cb2b55
TI		 2602 .driver = {
2603 .pm = AZX_PM_OPS,
2604 },
1da177e4
LT		 2605};
2606
e9f66d9b 2607module_pci_driver(azx_driver);
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