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vga_switcheroo: Deduplicate power state tracking
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
7f80f513 56#include <asm/set_memory.h>
50279d9b 57#include <asm/cpufeature.h>
27fe48d9 58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
98d8fc6c
ML		 61#include <sound/hdaudio.h>
62#include <sound/hda_i915.h>
9121947d 63#include <linux/vgaarb.h>
a82d51ed 64#include <linux/vga_switcheroo.h>
4918cdab 65#include <linux/firmware.h>
1da177e4 66#include "hda_codec.h"
05e84878 67#include "hda_controller.h"
347de1f8 68#include "hda_intel.h"
1da177e4 69
785d8c4b
LY		 70#define CREATE_TRACE_POINTS
71#include "hda_intel_trace.h"
72
b6050ef6
TI		 73/* position fix mode */
74enum {
75 POS_FIX_AUTO,
76 POS_FIX_LPIB,
77 POS_FIX_POSBUF,
78 POS_FIX_VIACOMBO,
79 POS_FIX_COMBO,
f87e7f25 80 POS_FIX_SKL,
b6050ef6
TI		 81};
82
9a34af4a
TI		 83/* Defines for ATI HD Audio support in SB450 south bridge */
84#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
85#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
86
87/* Defines for Nvidia HDA support */
88#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
89#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
90#define NVIDIA_HDA_ISTRM_COH 0x4d
91#define NVIDIA_HDA_OSTRM_COH 0x4c
92#define NVIDIA_HDA_ENABLE_COHBIT 0x01
93
94/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 95#define INTEL_HDA_CGCTL 0x48
96#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 97#define INTEL_SCH_HDA_DEVC 0x78
98#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
99
100/* Define IN stream 0 FIFO size offset in VIA controller */
101#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
102/* Define VIA HD Audio Device ID*/
103#define VIA_HDAC_DEVICE_ID 0x3288
104
33124929
TI		 105/* max number of SDs */
106/* ICH, ATI and VIA have 4 playback and 4 capture */
107#define ICH6_NUM_CAPTURE 4
108#define ICH6_NUM_PLAYBACK 4
109
110/* ULI has 6 playback and 5 capture */
111#define ULI_NUM_CAPTURE 5
112#define ULI_NUM_PLAYBACK 6
113
114/* ATI HDMI may have up to 8 playbacks and 0 capture */
115#define ATIHDMI_NUM_CAPTURE 0
116#define ATIHDMI_NUM_PLAYBACK 8
117
118/* TERA has 4 playback and 3 capture */
119#define TERA_NUM_CAPTURE 3
120#define TERA_NUM_PLAYBACK 4
121
1da177e4 122
5aba4f8e
TI		 123static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
124static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 125static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 126static char *model[SNDRV_CARDS];
1dac6695 127static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 128static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 129static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 130static int probe_only[SNDRV_CARDS];
26a6cb6c 131static int jackpoll_ms[SNDRV_CARDS];
41438f13 132static int single_cmd = -1;
71623855 133static int enable_msi = -1;
4ea6fbc8
TI		 134#ifdef CONFIG_SND_HDA_PATCH_LOADER
135static char *patch[SNDRV_CARDS];
136#endif
2dca0bba 137#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 138static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 139 CONFIG_SND_HDA_INPUT_BEEP_MODE};
140#endif
1da177e4 141
5aba4f8e 142module_param_array(index, int, NULL, 0444);
1da177e4 143MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 144module_param_array(id, charp, NULL, 0444);
1da177e4 145MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 146module_param_array(enable, bool, NULL, 0444);
147MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
148module_param_array(model, charp, NULL, 0444);
1da177e4 149MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 150module_param_array(position_fix, int, NULL, 0444);
4cb36310 151MODULE_PARM_DESC(position_fix, "DMA pointer read method."
f87e7f25 152 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
555e219f
TI		 153module_param_array(bdl_pos_adj, int, NULL, 0644);
154MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 155module_param_array(probe_mask, int, NULL, 0444);
606ad75f 156MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 157module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 158MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 159module_param_array(jackpoll_ms, int, NULL, 0444);
160MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 161module_param(single_cmd, bint, 0444);
d01ce99f
TI		 162MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
163 "(for debugging only).");
ac9ef6cf 164module_param(enable_msi, bint, 0444);
134a11f0 165MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 166#ifdef CONFIG_SND_HDA_PATCH_LOADER
167module_param_array(patch, charp, NULL, 0444);
168MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
169#endif
2dca0bba 170#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 171module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 172MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 173 "(0=off, 1=on) (default=1).");
2dca0bba 174#endif
606ad75f 175
83012a7c 176#ifdef CONFIG_PM
65fcd41d 177static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 178static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 179 .set = param_set_xint,
180 .get = param_get_int,
181};
182#define param_check_xint param_check_int
183
fee2fba3 184static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 185module_param(power_save, xint, 0644);
fee2fba3
TI		 186MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
187 "(in second, 0 = disable).");
1da177e4 188
dee1b66c
TI		 189/* reset the HD-audio controller in power save mode.
190 * this may give more power-saving, but will take longer time to
191 * wake up.
192 */
8fc24426
TI		 193static bool power_save_controller = 1;
194module_param(power_save_controller, bool, 0644);
dee1b66c 195MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 196#else
bb573928 197#define power_save 0
83012a7c 198#endif /* CONFIG_PM */
dee1b66c 199
7bfe059e
TI		 200static int align_buffer_size = -1;
201module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 202MODULE_PARM_DESC(align_buffer_size,
203 "Force buffer and period sizes to be multiple of 128 bytes.");
204
27fe48d9 205#ifdef CONFIG_X86
7c732015
TI		 206static int hda_snoop = -1;
207module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 208MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 209#else
210#define hda_snoop true
27fe48d9
TI		 211#endif
212
213
1da177e4
LT		 214MODULE_LICENSE("GPL");
215MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
216 "{Intel, ICH6M},"
2f1b3818 217 "{Intel, ICH7},"
f5d40b30 218 "{Intel, ESB2},"
d2981393 219 "{Intel, ICH8},"
f9cc8a8b 220 "{Intel, ICH9},"
c34f5a04 221 "{Intel, ICH10},"
b29c2360 222 "{Intel, PCH},"
d2f2fcd2 223 "{Intel, CPT},"
d2edeb7c 224 "{Intel, PPT},"
8bc039a1 225 "{Intel, LPT},"
144dad99 226 "{Intel, LPT_LP},"
4eeca499 227 "{Intel, WPT_LP},"
c8b00fd2 228 "{Intel, SPT},"
b4565913 229 "{Intel, SPT_LP},"
e926f2c8 230 "{Intel, HPT},"
cea310e8 231 "{Intel, PBG},"
4979bca9 232 "{Intel, SCH},"
fc20a562 233 "{ATI, SB450},"
89be83f8 234 "{ATI, SB600},"
778b6e1b 235 "{ATI, RS600},"
5b15c95f 236 "{ATI, RS690},"
e6db1119
WL		 237 "{ATI, RS780},"
238 "{ATI, R600},"
2797f724
HRK		 239 "{ATI, RV630},"
240 "{ATI, RV610},"
27da1834
WL		 241 "{ATI, RV670},"
242 "{ATI, RV635},"
243 "{ATI, RV620},"
244 "{ATI, RV770},"
fc20a562 245 "{VIA, VT8251},"
47672310 246 "{VIA, VT8237A},"
07e4ca50
TI		 247 "{SiS, SIS966},"
248 "{ULI, M5461}}");
1da177e4
LT		 249MODULE_DESCRIPTION("Intel HDA driver");
250
a82d51ed 251#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 252#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 253#define SUPPORT_VGA_SWITCHEROO
254#endif
255#endif
256
257
1da177e4 258/*
1da177e4 259 */
1da177e4 260
07e4ca50
TI		 261/* driver types */
262enum {
263 AZX_DRIVER_ICH,
32679f95 264 AZX_DRIVER_PCH,
4979bca9 265 AZX_DRIVER_SCH,
a4b4793f 266 AZX_DRIVER_SKL,
fab1285a 267 AZX_DRIVER_HDMI,
07e4ca50 268 AZX_DRIVER_ATI,
778b6e1b 269 AZX_DRIVER_ATIHDMI,
1815b34a 270 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 271 AZX_DRIVER_VIA,
272 AZX_DRIVER_SIS,
273 AZX_DRIVER_ULI,
da3fca21 274 AZX_DRIVER_NVIDIA,
f269002e 275 AZX_DRIVER_TERA,
14d34f16 276 AZX_DRIVER_CTX,
5ae763b1 277 AZX_DRIVER_CTHDA,
c563f473 278 AZX_DRIVER_CMEDIA,
c4da29ca 279 AZX_DRIVER_GENERIC,
2f5983f2 280 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 281};
282
37e661ee
TI		 283#define azx_get_snoop_type(chip) \
284 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
285#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
286
b42b4afb
TI		 287/* quirks for old Intel chipsets */
288#define AZX_DCAPS_INTEL_ICH \
103884a3 289 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 290
2ea3c6a2 291/* quirks for Intel PCH */
6603249d 292#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 293 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
bcb337d1 294 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 295
dba9b7b6 296/* PCH up to IVB; no runtime PM; bind with i915 gfx */
6603249d 297#define AZX_DCAPS_INTEL_PCH_NOPM \
dba9b7b6 298 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
6603249d 299
55913110 300/* PCH for HSW/BDW; with runtime PM */
dba9b7b6 301/* no i915 binding for this as HSW/BDW has another controller for HDMI */
d7dab4db 302#define AZX_DCAPS_INTEL_PCH \
6603249d 303 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 304
6603249d 305/* HSW HDMI */
33499a15 306#define AZX_DCAPS_INTEL_HASWELL \
103884a3 307 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
dba9b7b6
TI		 308 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
309 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 310
54a0405d
LY		 311/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
312#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 313 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
dba9b7b6
TI		 314 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
315 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 316
40cc2392 317#define AZX_DCAPS_INTEL_BAYTRAIL \
dba9b7b6
TI		 318 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
319 AZX_DCAPS_I915_POWERWELL)
40cc2392 320
2d846c74 321#define AZX_DCAPS_INTEL_BRASWELL \
dba9b7b6
TI		 322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
323 AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
2d846c74 324
d6795827 325#define AZX_DCAPS_INTEL_SKYLAKE \
dba9b7b6
TI		 326 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
327 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
2d846c74 328 AZX_DCAPS_I915_POWERWELL)
d6795827 329
c87693da 330#define AZX_DCAPS_INTEL_BROXTON \
dba9b7b6
TI		 331 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
332 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
c87693da
LH		 333 AZX_DCAPS_I915_POWERWELL)
334
9477c58e
TI		 335/* quirks for ATI SB / AMD Hudson */
336#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 337 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
338 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 339
340/* quirks for ATI/AMD HDMI */
341#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 342 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
343 AZX_DCAPS_NO_MSI64)
9477c58e 344
37e661ee
TI		 345/* quirks for ATI HDMI with snoop off */
346#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
347 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
348
9477c58e
TI		 349/* quirks for Nvidia */
350#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 351 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 352 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 353
5ae763b1 354#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 355 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 356 AZX_DCAPS_NO_64BIT |\
37e661ee 357 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 358
a82d51ed 359/*
2b760d88 360 * vga_switcheroo support
a82d51ed
TI		 361 */
362#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 363#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
364#else
365#define use_vga_switcheroo(chip) 0
366#endif
367
03b135ce
LY		 368#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
369 ((pci)->device == 0x0c0c) || \
370 ((pci)->device == 0x0d0c) || \
371 ((pci)->device == 0x160c))
372
7e31a015 373#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
7c23b7c1 374
48c8b0eb 375static char *driver_short_names[] = {
07e4ca50 376 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 377 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 378 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 379 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 380 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 381 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 382 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 383 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 384 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
385 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 386 [AZX_DRIVER_ULI] = "HDA ULI M5461",
387 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 388 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 389 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 390 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 391 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 392 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 393};
394
27fe48d9 395#ifdef CONFIG_X86
9ddf1aeb 396static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 397{
9ddf1aeb
TI		 398 int pages;
399
27fe48d9
TI		 400 if (azx_snoop(chip))
401 return;
9ddf1aeb
TI		 402 if (!dmab || !dmab->area || !dmab->bytes)
403 return;
404
405#ifdef CONFIG_SND_DMA_SGBUF
406 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
407 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 408 if (chip->driver_type == AZX_DRIVER_CMEDIA)
409 return; /* deal with only CORB/RIRB buffers */
27fe48d9 410 if (on)
9ddf1aeb 411 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 412 else
9ddf1aeb
TI		 413 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
414 return;
27fe48d9 415 }
9ddf1aeb
TI		 416#endif
417
418 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
419 if (on)
420 set_memory_wc((unsigned long)dmab->area, pages);
421 else
422 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 423}
424
425static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
426 bool on)
427{
9ddf1aeb 428 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 429}
430static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 431 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 432{
433 if (azx_dev->wc_marked != on) {
9ddf1aeb 434 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 435 azx_dev->wc_marked = on;
436 }
437}
438#else
439/* NOP for other archs */
440static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
441 bool on)
442{
443}
444static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 445 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 446{
447}
448#endif
449
68e7fffc 450static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 451
cb53c626
TI		 452/*
453 * initialize the PCI registers
454 */
455/* update bits in a PCI register byte */
456static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
457 unsigned char mask, unsigned char val)
458{
459 unsigned char data;
460
461 pci_read_config_byte(pci, reg, &data);
462 data &= ~mask;
463 data |= (val & mask);
464 pci_write_config_byte(pci, reg, data);
465}
466
467static void azx_init_pci(struct azx *chip)
468{
37e661ee
TI		 469 int snoop_type = azx_get_snoop_type(chip);
470
cb53c626
TI		 471 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
472 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
473 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 474 * codecs.
475 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 476 */
46f2cc80 477 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 478 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 479 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 480 }
cb53c626 481
9477c58e
TI		 482 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
483 * we need to enable snoop.
484 */
37e661ee 485 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 486 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
487 azx_snoop(chip));
cb53c626 488 update_pci_byte(chip->pci,
27fe48d9
TI		 489 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
490 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 491 }
492
493 /* For NVIDIA HDA, enable snoop */
37e661ee 494 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 495 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
496 azx_snoop(chip));
cb53c626
TI		 497 update_pci_byte(chip->pci,
498 NVIDIA_HDA_TRANSREG_ADDR,
499 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 500 update_pci_byte(chip->pci,
501 NVIDIA_HDA_ISTRM_COH,
502 0x01, NVIDIA_HDA_ENABLE_COHBIT);
503 update_pci_byte(chip->pci,
504 NVIDIA_HDA_OSTRM_COH,
505 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 506 }
507
508 /* Enable SCH/PCH snoop if needed */
37e661ee 509 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 510 unsigned short snoop;
90a5ad52 511 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 512 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
513 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
514 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
515 if (!azx_snoop(chip))
516 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
517 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 518 pci_read_config_word(chip->pci,
519 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 520 }
4e76a883
TI		 521 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
522 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
523 "Disabled" : "Enabled");
da3fca21 524 }
1da177e4
LT		 525}
526
7c23b7c1
LH		 527/*
528 * In BXT-P A0, HD-Audio DMA requests is later than expected,
529 * and makes an audio stream sensitive to system latencies when
530 * 24/32 bits are playing.
531 * Adjusting threshold of DMA fifo to force the DMA request
532 * sooner to improve latency tolerance at the expense of power.
533 */
534static void bxt_reduce_dma_latency(struct azx *chip)
535{
536 u32 val;
537
70eafad8 538 val = azx_readl(chip, VS_EM4L);
7c23b7c1 539 val &= (0x3 << 20);
70eafad8 540 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 541}
542
1f9d3d98
LY		 543/*
544 * ML_LCAP bits:
545 * bit 0: 6 MHz Supported
546 * bit 1: 12 MHz Supported
547 * bit 2: 24 MHz Supported
548 * bit 3: 48 MHz Supported
549 * bit 4: 96 MHz Supported
550 * bit 5: 192 MHz Supported
551 */
552static int intel_get_lctl_scf(struct azx *chip)
553{
554 struct hdac_bus *bus = azx_bus(chip);
555 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
556 u32 val, t;
557 int i;
558
559 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
560
561 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
562 t = preferred_bits[i];
563 if (val & (1 << t))
564 return t;
565 }
566
567 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
568 return 0;
569}
570
571static int intel_ml_lctl_set_power(struct azx *chip, int state)
572{
573 struct hdac_bus *bus = azx_bus(chip);
574 u32 val;
575 int timeout;
576
577 /*
578 * the codecs are sharing the first link setting by default
579 * If other links are enabled for stream, they need similar fix
580 */
581 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
582 val &= ~AZX_MLCTL_SPA;
583 val |= state << AZX_MLCTL_SPA_SHIFT;
584 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
585 /* wait for CPA */
586 timeout = 50;
587 while (timeout) {
588 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
589 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
590 return 0;
591 timeout--;
592 udelay(10);
593 }
594
595 return -1;
596}
597
598static void intel_init_lctl(struct azx *chip)
599{
600 struct hdac_bus *bus = azx_bus(chip);
601 u32 val;
602 int ret;
603
604 /* 0. check lctl register value is correct or not */
605 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
606 /* if SCF is already set, let's use it */
607 if ((val & ML_LCTL_SCF_MASK) != 0)
608 return;
609
610 /*
611 * Before operating on SPA, CPA must match SPA.
612 * Any deviation may result in undefined behavior.
613 */
614 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
615 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
616 return;
617
618 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
619 ret = intel_ml_lctl_set_power(chip, 0);
620 udelay(100);
621 if (ret)
622 goto set_spa;
623
624 /* 2. update SCF to select a properly audio clock*/
625 val &= ~ML_LCTL_SCF_MASK;
626 val |= intel_get_lctl_scf(chip);
627 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
628
629set_spa:
630 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
631 intel_ml_lctl_set_power(chip, 1);
632 udelay(100);
633}
634
0a673521
LH		 635static void hda_intel_init_chip(struct azx *chip, bool full_reset)
636{
98d8fc6c 637 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 638 struct pci_dev *pci = chip->pci;
6639484d 639 u32 val;
0a673521
LH		 640
641 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 642 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 643 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 644 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
645 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
646 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
647 }
0a673521 648 azx_init_chip(chip, full_reset);
a4b4793f 649 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 650 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
651 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
652 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
653 }
0a673521 654 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 655 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 656
657 /* reduce dma latency to avoid noise */
7e31a015 658 if (IS_BXT(pci))
7c23b7c1 659 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 660
661 if (bus->mlcap != NULL)
662 intel_init_lctl(chip);
0a673521
LH		 663}
664
b6050ef6
TI		 665/* calculate runtime delay from LPIB */
666static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
667 unsigned int pos)
668{
7833c3f8 669 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 670 int stream = substream->stream;
671 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
672 int delay;
673
674 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
675 delay = pos - lpib_pos;
676 else
677 delay = lpib_pos - pos;
678 if (delay < 0) {
7833c3f8 679 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 680 delay = 0;
681 else
7833c3f8 682 delay += azx_dev->core.bufsize;
b6050ef6
TI		 683 }
684
7833c3f8 685 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 686 dev_info(chip->card->dev,
687 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 688 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 689 delay = 0;
690 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
691 chip->get_delay[stream] = NULL;
692 }
693
694 return bytes_to_frames(substream->runtime, delay);
695}
696
9ad593f6
TI		 697static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
698
7ca954a8
DR		 699/* called from IRQ */
700static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
701{
9a34af4a 702 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 703 int ok;
704
705 ok = azx_position_ok(chip, azx_dev);
706 if (ok == 1) {
707 azx_dev->irq_pending = 0;
708 return ok;
2f35c630 709 } else if (ok == 0) {
7ca954a8
DR		 710 /* bogus IRQ, process it later */
711 azx_dev->irq_pending = 1;
2f35c630 712 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 713 }
714 return 0;
715}
716
17eccb27
ML		 717/* Enable/disable i915 display power for the link */
718static int azx_intel_link_power(struct azx *chip, bool enable)
719{
98d8fc6c 720 struct hdac_bus *bus = azx_bus(chip);
17eccb27 721
98d8fc6c 722 return snd_hdac_display_power(bus, enable);
17eccb27
ML		 723}
724
9ad593f6
TI		 725/*
726 * Check whether the current DMA position is acceptable for updating
727 * periods. Returns non-zero if it's OK.
728 *
729 * Many HD-audio controllers appear pretty inaccurate about
730 * the update-IRQ timing. The IRQ is issued before actually the
731 * data is processed. So, we need to process it afterwords in a
732 * workqueue.
733 */
734static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
735{
7833c3f8 736 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 737 int stream = substream->stream;
e5463720 738 u32 wallclk;
9ad593f6
TI		 739 unsigned int pos;
740
7833c3f8
TI		 741 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
742 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 743 return -1; /* bogus (too early) interrupt */
fa00e046 744
b6050ef6
TI		 745 if (chip->get_position[stream])
746 pos = chip->get_position[stream](chip, azx_dev);
747 else { /* use the position buffer as default */
748 pos = azx_get_pos_posbuf(chip, azx_dev);
749 if (!pos || pos == (u32)-1) {
750 dev_info(chip->card->dev,
751 "Invalid position buffer, using LPIB read method instead.\n");
752 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 753 if (chip->get_position[0] == azx_get_pos_lpib &&
754 chip->get_position[1] == azx_get_pos_lpib)
755 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 756 pos = azx_get_pos_lpib(chip, azx_dev);
757 chip->get_delay[stream] = NULL;
758 } else {
759 chip->get_position[stream] = azx_get_pos_posbuf;
760 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
761 chip->get_delay[stream] = azx_get_delay_from_lpib;
762 }
763 }
764
7833c3f8 765 if (pos >= azx_dev->core.bufsize)
b6050ef6 766 pos = 0;
9ad593f6 767
7833c3f8 768 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 769 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 770 return -1; /* this shouldn't happen! */
7833c3f8
TI		 771 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
772 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 773 /* NG - it's below the first next period boundary */
4f0189be 774 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 775 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 776 return 1; /* OK, it's fine */
777}
778
779/*
780 * The work for pending PCM period updates.
781 */
782static void azx_irq_pending_work(struct work_struct *work)
783{
9a34af4a
TI		 784 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
785 struct azx *chip = &hda->chip;
7833c3f8
TI		 786 struct hdac_bus *bus = azx_bus(chip);
787 struct hdac_stream *s;
788 int pending, ok;
9ad593f6 789
9a34af4a 790 if (!hda->irq_pending_warned) {
4e76a883
TI		 791 dev_info(chip->card->dev,
792 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
793 chip->card->number);
9a34af4a 794 hda->irq_pending_warned = 1;
a6a950a8
TI		 795 }
796
9ad593f6
TI		 797 for (;;) {
798 pending = 0;
a41d1224 799 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 800 list_for_each_entry(s, &bus->stream_list, list) {
801 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 802 if (!azx_dev->irq_pending ||
7833c3f8
TI		 803 !s->substream ||
804 !s->running)
9ad593f6 805 continue;
e5463720
JK		 806 ok = azx_position_ok(chip, azx_dev);
807 if (ok > 0) {
9ad593f6 808 azx_dev->irq_pending = 0;
a41d1224 809 spin_unlock(&bus->reg_lock);
7833c3f8 810 snd_pcm_period_elapsed(s->substream);
a41d1224 811 spin_lock(&bus->reg_lock);
e5463720
JK		 812 } else if (ok < 0) {
813 pending = 0; /* too early */
9ad593f6
TI		 814 } else
815 pending++;
816 }
a41d1224 817 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 818 if (!pending)
819 return;
08af495f 820 msleep(1);
9ad593f6
TI		 821 }
822}
823
824/* clear irq_pending flags and assure no on-going workq */
825static void azx_clear_irq_pending(struct azx *chip)
826{
7833c3f8
TI		 827 struct hdac_bus *bus = azx_bus(chip);
828 struct hdac_stream *s;
9ad593f6 829
a41d1224 830 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 831 list_for_each_entry(s, &bus->stream_list, list) {
832 struct azx_dev *azx_dev = stream_to_azx_dev(s);
833 azx_dev->irq_pending = 0;
834 }
a41d1224 835 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 836}
837
68e7fffc
TI		 838static int azx_acquire_irq(struct azx *chip, int do_disconnect)
839{
a41d1224
TI		 840 struct hdac_bus *bus = azx_bus(chip);
841
437a5a46
TI		 842 if (request_irq(chip->pci->irq, azx_interrupt,
843 chip->msi ? 0 : IRQF_SHARED,
de65360b 844 chip->card->irq_descr, chip)) {
4e76a883
TI		 845 dev_err(chip->card->dev,
846 "unable to grab IRQ %d, disabling device\n",
847 chip->pci->irq);
68e7fffc
TI		 848 if (do_disconnect)
849 snd_card_disconnect(chip->card);
850 return -1;
851 }
a41d1224 852 bus->irq = chip->pci->irq;
69e13418 853 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 854 return 0;
855}
856
b6050ef6
TI		 857/* get the current DMA position with correction on VIA chips */
858static unsigned int azx_via_get_position(struct azx *chip,
859 struct azx_dev *azx_dev)
860{
861 unsigned int link_pos, mini_pos, bound_pos;
862 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
863 unsigned int fifo_size;
864
1604eeee 865 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 866 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 867 /* Playback, no problem using link position */
868 return link_pos;
869 }
870
871 /* Capture */
872 /* For new chipset,
873 * use mod to get the DMA position just like old chipset
874 */
7833c3f8
TI		 875 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
876 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 877
878 /* azx_dev->fifo_size can't get FIFO size of in stream.
879 * Get from base address + offset.
880 */
a41d1224
TI		 881 fifo_size = readw(azx_bus(chip)->remap_addr +
882 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 883
884 if (azx_dev->insufficient) {
885 /* Link position never gather than FIFO size */
886 if (link_pos <= fifo_size)
887 return 0;
888
889 azx_dev->insufficient = 0;
890 }
891
892 if (link_pos <= fifo_size)
7833c3f8 893 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 894 else
895 mini_pos = link_pos - fifo_size;
896
897 /* Find nearest previous boudary */
7833c3f8
TI		 898 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
899 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 900 if (mod_link_pos >= fifo_size)
901 bound_pos = link_pos - mod_link_pos;
902 else if (mod_dma_pos >= mod_mini_pos)
903 bound_pos = mini_pos - mod_mini_pos;
904 else {
7833c3f8
TI		 905 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
906 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 907 bound_pos = 0;
908 }
909
910 /* Calculate real DMA position we want */
911 return bound_pos + mod_dma_pos;
912}
913
f87e7f25
TI		 914static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
915 struct azx_dev *azx_dev)
916{
917 return _snd_hdac_chip_readl(azx_bus(chip),
918 AZX_REG_VS_SDXDPIB_XBASE +
919 (AZX_REG_VS_SDXDPIB_XINTERVAL *
920 azx_dev->core.index));
921}
922
923/* get the current DMA position with correction on SKL+ chips */
924static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
925{
926 /* DPIB register gives a more accurate position for playback */
927 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
928 return azx_skl_get_dpib_pos(chip, azx_dev);
929
930 /* For capture, we need to read posbuf, but it requires a delay
931 * for the possible boundary overlap; the read of DPIB fetches the
932 * actual posbuf
933 */
934 udelay(20);
935 azx_skl_get_dpib_pos(chip, azx_dev);
936 return azx_get_pos_posbuf(chip, azx_dev);
937}
938
83012a7c 939#ifdef CONFIG_PM
65fcd41d
TI		 940static DEFINE_MUTEX(card_list_lock);
941static LIST_HEAD(card_list);
942
943static void azx_add_card_list(struct azx *chip)
944{
9a34af4a 945 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 946 mutex_lock(&card_list_lock);
9a34af4a 947 list_add(&hda->list, &card_list);
65fcd41d
TI		 948 mutex_unlock(&card_list_lock);
949}
950
951static void azx_del_card_list(struct azx *chip)
952{
9a34af4a 953 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 954 mutex_lock(&card_list_lock);
9a34af4a 955 list_del_init(&hda->list);
65fcd41d
TI		 956 mutex_unlock(&card_list_lock);
957}
958
959/* trigger power-save check at writing parameter */
960static int param_set_xint(const char *val, const struct kernel_param *kp)
961{
9a34af4a 962 struct hda_intel *hda;
65fcd41d 963 struct azx *chip;
65fcd41d
TI		 964 int prev = power_save;
965 int ret = param_set_int(val, kp);
966
967 if (ret || prev == power_save)
968 return ret;
969
970 mutex_lock(&card_list_lock);
9a34af4a
TI		 971 list_for_each_entry(hda, &card_list, list) {
972 chip = &hda->chip;
a41d1224 973 if (!hda->probe_continued || chip->disabled)
65fcd41d 974 continue;
a41d1224 975 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 976 }
977 mutex_unlock(&card_list_lock);
978 return 0;
979}
980#else
981#define azx_add_card_list(chip) /* NOP */
982#define azx_del_card_list(chip) /* NOP */
83012a7c 983#endif /* CONFIG_PM */
5c0b9bec 984
7ccbde57 985#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 986/*
987 * power management
988 */
68cb2b55 989static int azx_suspend(struct device *dev)
1da177e4 990{
68cb2b55 991 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 992 struct azx *chip;
993 struct hda_intel *hda;
a41d1224 994 struct hdac_bus *bus;
1da177e4 995
2d9772ef
TI		 996 if (!card)
997 return 0;
998
999 chip = card->private_data;
1000 hda = container_of(chip, struct hda_intel, chip);
342e8449 1001 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 1002 return 0;
1003
a41d1224 1004 bus = azx_bus(chip);
421a1252 1005 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 1006 azx_clear_irq_pending(chip);
cb53c626 1007 azx_stop_chip(chip);
7295b264 1008 azx_enter_link_reset(chip);
a41d1224
TI		 1009 if (bus->irq >= 0) {
1010 free_irq(bus->irq, chip);
1011 bus->irq = -1;
30b35399 1012 }
a07187c9 1013
68e7fffc 1014 if (chip->msi)
43001c95 1015 pci_disable_msi(chip->pci);
dba9b7b6 1016 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
795614dd 1017 && hda->need_i915_power)
98d8fc6c 1018 snd_hdac_display_power(bus, false);
785d8c4b
LY		 1019
1020 trace_azx_suspend(chip);
1da177e4
LT		 1021 return 0;
1022}
1023
68cb2b55 1024static int azx_resume(struct device *dev)
1da177e4 1025{
68cb2b55
TI		 1026 struct pci_dev *pci = to_pci_dev(dev);
1027 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1028 struct azx *chip;
1029 struct hda_intel *hda;
a52ff34e 1030 struct hdac_bus *bus;
2d9772ef
TI		 1031
1032 if (!card)
1033 return 0;
1da177e4 1034
2d9772ef
TI		 1035 chip = card->private_data;
1036 hda = container_of(chip, struct hda_intel, chip);
a52ff34e 1037 bus = azx_bus(chip);
342e8449 1038 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 1039 return 0;
1040
a52ff34e
TI		 1041 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1042 snd_hdac_display_power(bus, true);
1043 if (hda->need_i915_power)
1044 snd_hdac_i915_set_bclk(bus);
a07187c9 1045 }
a52ff34e 1046
68e7fffc
TI		 1047 if (chip->msi)
1048 if (pci_enable_msi(pci) < 0)
1049 chip->msi = 0;
1050 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1051 return -EIO;
cb53c626 1052 azx_init_pci(chip);
d804ad92 1053
0a673521 1054 hda_intel_init_chip(chip, true);
d804ad92 1055
a52ff34e
TI		 1056 /* power down again for link-controlled chips */
1057 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1058 !hda->need_i915_power)
1059 snd_hdac_display_power(bus, false);
1060
421a1252 1061 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 1062
1063 trace_azx_resume(chip);
1da177e4
LT		 1064 return 0;
1065}
b8dfc462
ML		 1066#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1067
3e6db33a
XZ		 1068#ifdef CONFIG_PM_SLEEP
1069/* put codec down to D3 at hibernation for Intel SKL+;
1070 * otherwise BIOS may still access the codec and screw up the driver
1071 */
3e6db33a
XZ		 1072static int azx_freeze_noirq(struct device *dev)
1073{
a4b4793f
TI		 1074 struct snd_card *card = dev_get_drvdata(dev);
1075 struct azx *chip = card->private_data;
3e6db33a
XZ		 1076 struct pci_dev *pci = to_pci_dev(dev);
1077
a4b4793f 1078 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1079 pci_set_power_state(pci, PCI_D3hot);
1080
1081 return 0;
1082}
1083
1084static int azx_thaw_noirq(struct device *dev)
1085{
a4b4793f
TI		 1086 struct snd_card *card = dev_get_drvdata(dev);
1087 struct azx *chip = card->private_data;
3e6db33a
XZ		 1088 struct pci_dev *pci = to_pci_dev(dev);
1089
a4b4793f 1090 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1091 pci_set_power_state(pci, PCI_D0);
1092
1093 return 0;
1094}
1095#endif /* CONFIG_PM_SLEEP */
1096
641d334b 1097#ifdef CONFIG_PM
b8dfc462
ML		 1098static int azx_runtime_suspend(struct device *dev)
1099{
1100 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1101 struct azx *chip;
1102 struct hda_intel *hda;
b8dfc462 1103
2d9772ef
TI		 1104 if (!card)
1105 return 0;
1106
1107 chip = card->private_data;
1108 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1109 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1110 return 0;
1111
364aa716 1112 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1113 return 0;
1114
7d4f606c
WX		 1115 /* enable controller wake up event */
1116 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1117 STATESTS_INT_MASK);
1118
b8dfc462 1119 azx_stop_chip(chip);
873ce8ad 1120 azx_enter_link_reset(chip);
b8dfc462 1121 azx_clear_irq_pending(chip);
dba9b7b6 1122 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
795614dd 1123 && hda->need_i915_power)
98d8fc6c 1124 snd_hdac_display_power(azx_bus(chip), false);
e4d9e513 1125
785d8c4b 1126 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1127 return 0;
1128}
1129
1130static int azx_runtime_resume(struct device *dev)
1131{
1132 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1133 struct azx *chip;
1134 struct hda_intel *hda;
98d8fc6c 1135 struct hdac_bus *bus;
7d4f606c
WX		 1136 struct hda_codec *codec;
1137 int status;
b8dfc462 1138
2d9772ef
TI		 1139 if (!card)
1140 return 0;
1141
1142 chip = card->private_data;
1143 hda = container_of(chip, struct hda_intel, chip);
a52ff34e 1144 bus = azx_bus(chip);
1618e84a 1145 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1146 return 0;
1147
364aa716 1148 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1149 return 0;
1150
033ea349 1151 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
a52ff34e
TI		 1152 snd_hdac_display_power(bus, true);
1153 if (hda->need_i915_power)
bb03ed21 1154 snd_hdac_i915_set_bclk(bus);
a07187c9 1155 }
7d4f606c
WX		 1156
1157 /* Read STATESTS before controller reset */
1158 status = azx_readw(chip, STATESTS);
1159
b8dfc462 1160 azx_init_pci(chip);
0a673521 1161 hda_intel_init_chip(chip, true);
7d4f606c 1162
a41d1224
TI		 1163 if (status) {
1164 list_for_each_codec(codec, &chip->bus)
7d4f606c 1165 if (status & (1 << codec->addr))
2f35c630
TI		 1166 schedule_delayed_work(&codec->jackpoll_work,
1167 codec->jackpoll_interval);
7d4f606c
WX		 1168 }
1169
1170 /* disable controller Wake Up event*/
1171 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1172 ~STATESTS_INT_MASK);
1173
a52ff34e
TI		 1174 /* power down again for link-controlled chips */
1175 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1176 !hda->need_i915_power)
1177 snd_hdac_display_power(bus, false);
1178
785d8c4b 1179 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1180 return 0;
1181}
6eb827d2
TI		 1182
1183static int azx_runtime_idle(struct device *dev)
1184{
1185 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1186 struct azx *chip;
1187 struct hda_intel *hda;
1188
1189 if (!card)
1190 return 0;
6eb827d2 1191
2d9772ef
TI		 1192 chip = card->private_data;
1193 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1194 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1195 return 0;
1196
55ed9cd1 1197 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1198 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1199 return -EBUSY;
1200
1201 return 0;
1202}
1203
b8dfc462
ML		 1204static const struct dev_pm_ops azx_pm = {
1205 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1206#ifdef CONFIG_PM_SLEEP
1207 .freeze_noirq = azx_freeze_noirq,
1208 .thaw_noirq = azx_thaw_noirq,
1209#endif
6eb827d2 1210 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1211};
1212
68cb2b55
TI		 1213#define AZX_PM_OPS &azx_pm
1214#else
68cb2b55 1215#define AZX_PM_OPS NULL
b8dfc462 1216#endif /* CONFIG_PM */
1da177e4
LT		 1217
1218
48c8b0eb 1219static int azx_probe_continue(struct azx *chip);
a82d51ed 1220
8393ec4a 1221#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1222static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1223
a82d51ed
TI		 1224static void azx_vs_set_state(struct pci_dev *pci,
1225 enum vga_switcheroo_state state)
1226{
1227 struct snd_card *card = pci_get_drvdata(pci);
1228 struct azx *chip = card->private_data;
9a34af4a 1229 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1230 bool disabled;
1231
9a34af4a
TI		 1232 wait_for_completion(&hda->probe_wait);
1233 if (hda->init_failed)
a82d51ed
TI		 1234 return;
1235
1236 disabled = (state == VGA_SWITCHEROO_OFF);
1237 if (chip->disabled == disabled)
1238 return;
1239
a41d1224 1240 if (!hda->probe_continued) {
a82d51ed
TI		 1241 chip->disabled = disabled;
1242 if (!disabled) {
4e76a883
TI		 1243 dev_info(chip->card->dev,
1244 "Start delayed initialization\n");
5c90680e 1245 if (azx_probe_continue(chip) < 0) {
4e76a883 1246 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1247 hda->init_failed = true;
a82d51ed
TI		 1248 }
1249 }
1250 } else {
2b760d88 1251 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1252 disabled ? "Disabling" : "Enabling");
a82d51ed 1253 if (disabled) {
8928756d
DR		 1254 pm_runtime_put_sync_suspend(card->dev);
1255 azx_suspend(card->dev);
2b760d88 1256 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1257 * however we have no ACPI handle, so pci/acpi can't put us there,
1258 * put ourselves there */
1259 pci->current_state = PCI_D3cold;
a82d51ed 1260 chip->disabled = true;
a41d1224 1261 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1262 dev_warn(chip->card->dev,
1263 "Cannot lock devices!\n");
a82d51ed 1264 } else {
a41d1224 1265 snd_hda_unlock_devices(&chip->bus);
8928756d 1266 pm_runtime_get_noresume(card->dev);
a82d51ed 1267 chip->disabled = false;
8928756d 1268 azx_resume(card->dev);
a82d51ed
TI		 1269 }
1270 }
1271}
1272
1273static bool azx_vs_can_switch(struct pci_dev *pci)
1274{
1275 struct snd_card *card = pci_get_drvdata(pci);
1276 struct azx *chip = card->private_data;
9a34af4a 1277 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1278
9a34af4a
TI		 1279 wait_for_completion(&hda->probe_wait);
1280 if (hda->init_failed)
a82d51ed 1281 return false;
a41d1224 1282 if (chip->disabled || !hda->probe_continued)
a82d51ed 1283 return true;
a41d1224 1284 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1285 return false;
a41d1224 1286 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1287 return true;
1288}
1289
e23e7a14 1290static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1291{
9a34af4a 1292 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1293 struct pci_dev *p = get_bound_vga(chip->pci);
1294 if (p) {
4e76a883 1295 dev_info(chip->card->dev,
2b760d88 1296 "Handle vga_switcheroo audio client\n");
9a34af4a 1297 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1298 pci_dev_put(p);
1299 }
1300}
1301
1302static const struct vga_switcheroo_client_ops azx_vs_ops = {
1303 .set_gpu_state = azx_vs_set_state,
1304 .can_switch = azx_vs_can_switch,
1305};
1306
e23e7a14 1307static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1308{
9a34af4a 1309 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1310 int err;
1311
9a34af4a 1312 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1313 return 0;
1314 /* FIXME: currently only handling DIS controller
1315 * is there any machine with two switchable HDMI audio controllers?
1316 */
128960a9 1317 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
21b45676 1318 VGA_SWITCHEROO_DIS);
128960a9
TI		 1319 if (err < 0)
1320 return err;
9a34af4a 1321 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1322
1323 /* register as an optimus hdmi audio power domain */
8928756d 1324 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1325 &hda->hdmi_pm_domain);
128960a9 1326 return 0;
a82d51ed
TI		 1327}
1328#else
1329#define init_vga_switcheroo(chip) /* NOP */
1330#define register_vga_switcheroo(chip) 0
8393ec4a 1331#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1332#endif /* SUPPORT_VGA_SWITCHER */
1333
1da177e4
LT		 1334/*
1335 * destructor
1336 */
a98f90fd 1337static int azx_free(struct azx *chip)
1da177e4 1338{
c67e2228 1339 struct pci_dev *pci = chip->pci;
a07187c9 1340 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1341 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1342
364aa716 1343 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1344 pm_runtime_get_noresume(&pci->dev);
1345
65fcd41d
TI		 1346 azx_del_card_list(chip);
1347
9a34af4a
TI		 1348 hda->init_failed = 1; /* to be sure */
1349 complete_all(&hda->probe_wait);
f4c482a4 1350
9a34af4a 1351 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1352 if (chip->disabled && hda->probe_continued)
1353 snd_hda_unlock_devices(&chip->bus);
ab58d8cc 1354 if (hda->vga_switcheroo_registered) {
128960a9 1355 vga_switcheroo_unregister_client(chip->pci);
ab58d8cc
PW		 1356 vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1357 }
a82d51ed
TI		 1358 }
1359
a41d1224 1360 if (bus->chip_init) {
9ad593f6 1361 azx_clear_irq_pending(chip);
7833c3f8 1362 azx_stop_all_streams(chip);
cb53c626 1363 azx_stop_chip(chip);
1da177e4
LT		 1364 }
1365
a41d1224
TI		 1366 if (bus->irq >= 0)
1367 free_irq(bus->irq, (void*)chip);
68e7fffc 1368 if (chip->msi)
30b35399 1369 pci_disable_msi(chip->pci);
a41d1224 1370 iounmap(bus->remap_addr);
1da177e4 1371
67908994 1372 azx_free_stream_pages(chip);
a41d1224
TI		 1373 azx_free_streams(chip);
1374 snd_hdac_bus_exit(bus);
1375
a82d51ed
TI		 1376 if (chip->region_requested)
1377 pci_release_regions(chip->pci);
a41d1224 1378
1da177e4 1379 pci_disable_device(chip->pci);
4918cdab 1380#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1381 release_firmware(chip->fw);
4918cdab 1382#endif
98d8fc6c 1383
99a2008d 1384 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
795614dd 1385 if (hda->need_i915_power)
98d8fc6c 1386 snd_hdac_display_power(bus, false);
99a2008d 1387 }
fc18282c 1388 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
fcc88d91 1389 snd_hdac_i915_exit(bus);
a07187c9 1390 kfree(hda);
1da177e4
LT		 1391
1392 return 0;
1393}
1394
a41d1224
TI		 1395static int azx_dev_disconnect(struct snd_device *device)
1396{
1397 struct azx *chip = device->device_data;
1398
1399 chip->bus.shutdown = 1;
1400 return 0;
1401}
1402
a98f90fd 1403static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1404{
1405 return azx_free(device->device_data);
1406}
1407
8393ec4a 1408#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1409/*
2b760d88 1410 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1411 */
e23e7a14 1412static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1413{
1414 struct pci_dev *p;
1415
1416 /* check only discrete GPU */
1417 switch (pci->vendor) {
1418 case PCI_VENDOR_ID_ATI:
1419 case PCI_VENDOR_ID_AMD:
1420 case PCI_VENDOR_ID_NVIDIA:
1421 if (pci->devfn == 1) {
1422 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1423 pci->bus->number, 0);
1424 if (p) {
1425 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1426 return p;
1427 pci_dev_put(p);
1428 }
1429 }
1430 break;
1431 }
1432 return NULL;
1433}
1434
e23e7a14 1435static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1436{
1437 bool vga_inactive = false;
1438 struct pci_dev *p = get_bound_vga(pci);
1439
1440 if (p) {
12b78a7f 1441 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1442 vga_inactive = true;
1443 pci_dev_put(p);
1444 }
1445 return vga_inactive;
1446}
8393ec4a 1447#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1448
3372a153
TI		 1449/*
1450 * white/black-listing for position_fix
1451 */
e23e7a14 1452static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1453 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1454 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1455 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1456 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1457 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1458 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1459 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1460 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1461 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1462 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1463 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1464 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1465 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1466 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1467 {}
1468};
1469
e23e7a14 1470static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1471{
1472 const struct snd_pci_quirk *q;
1473
c673ba1c 1474 switch (fix) {
1dac6695 1475 case POS_FIX_AUTO:
c673ba1c
TI		 1476 case POS_FIX_LPIB:
1477 case POS_FIX_POSBUF:
4cb36310 1478 case POS_FIX_VIACOMBO:
a6f2fd55 1479 case POS_FIX_COMBO:
f87e7f25 1480 case POS_FIX_SKL:
c673ba1c
TI		 1481 return fix;
1482 }
1483
c673ba1c
TI		 1484 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1485 if (q) {
4e76a883
TI		 1486 dev_info(chip->card->dev,
1487 "position_fix set to %d for device %04x:%04x\n",
1488 q->value, q->subvendor, q->subdevice);
c673ba1c 1489 return q->value;
3372a153 1490 }
bdd9ef24
DH		 1491
1492 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1493 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1494 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1495 return POS_FIX_VIACOMBO;
9477c58e
TI		 1496 }
1497 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1498 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1499 return POS_FIX_LPIB;
bdd9ef24 1500 }
a4b4793f 1501 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1502 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1503 return POS_FIX_SKL;
1504 }
c673ba1c 1505 return POS_FIX_AUTO;
3372a153
TI		 1506}
1507
b6050ef6
TI		 1508static void assign_position_fix(struct azx *chip, int fix)
1509{
1510 static azx_get_pos_callback_t callbacks[] = {
1511 [POS_FIX_AUTO] = NULL,
1512 [POS_FIX_LPIB] = azx_get_pos_lpib,
1513 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1514 [POS_FIX_VIACOMBO] = azx_via_get_position,
1515 [POS_FIX_COMBO] = azx_get_pos_lpib,
f87e7f25 1516 [POS_FIX_SKL] = azx_get_pos_skl,
b6050ef6
TI		 1517 };
1518
1519 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1520
1521 /* combo mode uses LPIB only for playback */
1522 if (fix == POS_FIX_COMBO)
1523 chip->get_position[1] = NULL;
1524
f87e7f25 1525 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1526 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1527 chip->get_delay[0] = chip->get_delay[1] =
1528 azx_get_delay_from_lpib;
1529 }
1530
1531}
1532
669ba27a
TI		 1533/*
1534 * black-lists for probe_mask
1535 */
e23e7a14 1536static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1537 /* Thinkpad often breaks the controller communication when accessing
1538 * to the non-working (or non-existing) modem codec slot.
1539 */
1540 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1541 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1542 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1543 /* broken BIOS */
1544 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1545 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1546 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1547 /* forced codec slots */
93574844 1548 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1549 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1550 /* WinFast VP200 H (Teradici) user reported broken communication */
1551 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1552 {}
1553};
1554
f1eaaeec
TI		 1555#define AZX_FORCE_CODEC_MASK 0x100
1556
e23e7a14 1557static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1558{
1559 const struct snd_pci_quirk *q;
1560
f1eaaeec
TI		 1561 chip->codec_probe_mask = probe_mask[dev];
1562 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1563 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1564 if (q) {
4e76a883
TI		 1565 dev_info(chip->card->dev,
1566 "probe_mask set to 0x%x for device %04x:%04x\n",
1567 q->value, q->subvendor, q->subdevice);
f1eaaeec 1568 chip->codec_probe_mask = q->value;
669ba27a
TI		 1569 }
1570 }
f1eaaeec
TI		 1571
1572 /* check forced option */
1573 if (chip->codec_probe_mask != -1 &&
1574 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1575 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1576 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1577 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1578 }
669ba27a
TI		 1579}
1580
4d8e22e0 1581/*
71623855 1582 * white/black-list for enable_msi
4d8e22e0 1583 */
e23e7a14 1584static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1585 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1586 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1587 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1588 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1589 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1590 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1591 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1592 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1593 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1594 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1595 {}
1596};
1597
e23e7a14 1598static void check_msi(struct azx *chip)
4d8e22e0
TI		 1599{
1600 const struct snd_pci_quirk *q;
1601
71623855
TI		 1602 if (enable_msi >= 0) {
1603 chip->msi = !!enable_msi;
4d8e22e0 1604 return;
71623855
TI		 1605 }
1606 chip->msi = 1; /* enable MSI as default */
1607 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1608 if (q) {
4e76a883
TI		 1609 dev_info(chip->card->dev,
1610 "msi for device %04x:%04x set to %d\n",
1611 q->subvendor, q->subdevice, q->value);
4d8e22e0 1612 chip->msi = q->value;
80c43ed7
TI		 1613 return;
1614 }
1615
1616 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1617 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1618 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1619 chip->msi = 0;
4d8e22e0
TI		 1620 }
1621}
1622
a1585d76 1623/* check the snoop mode availability */
e23e7a14 1624static void azx_check_snoop_available(struct azx *chip)
a1585d76 1625{
7c732015 1626 int snoop = hda_snoop;
a1585d76 1627
7c732015
TI		 1628 if (snoop >= 0) {
1629 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1630 snoop ? "snoop" : "non-snoop");
1631 chip->snoop = snoop;
1632 return;
1633 }
1634
1635 snoop = true;
37e661ee
TI		 1636 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1637 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1638 /* force to non-snoop mode for a new VIA controller
1639 * when BIOS is set
1640 */
7c732015
TI		 1641 u8 val;
1642 pci_read_config_byte(chip->pci, 0x42, &val);
1643 if (!(val & 0x80) && chip->pci->revision == 0x30)
1644 snoop = false;
a1585d76
TI		 1645 }
1646
37e661ee
TI		 1647 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1648 snoop = false;
1649
7c732015
TI		 1650 chip->snoop = snoop;
1651 if (!snoop)
1652 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1653}
669ba27a 1654
99a2008d
WX		 1655static void azx_probe_work(struct work_struct *work)
1656{
9a34af4a
TI		 1657 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1658 azx_probe_continue(&hda->chip);
99a2008d 1659}
99a2008d 1660
4f0189be
TI		 1661static int default_bdl_pos_adj(struct azx *chip)
1662{
2cf721db
TI		 1663 /* some exceptions: Atoms seem problematic with value 1 */
1664 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1665 switch (chip->pci->device) {
1666 case 0x0f04: /* Baytrail */
1667 case 0x2284: /* Braswell */
1668 return 32;
1669 }
1670 }
1671
4f0189be
TI		 1672 switch (chip->driver_type) {
1673 case AZX_DRIVER_ICH:
1674 case AZX_DRIVER_PCH:
1675 return 1;
1676 default:
1677 return 32;
1678 }
1679}
1680
1da177e4
LT		 1681/*
1682 * constructor
1683 */
a43ff5ba
TI		 1684static const struct hdac_io_ops pci_hda_io_ops;
1685static const struct hda_controller_ops pci_hda_ops;
1686
e23e7a14
BP		 1687static int azx_create(struct snd_card *card, struct pci_dev *pci,
1688 int dev, unsigned int driver_caps,
1689 struct azx **rchip)
1da177e4 1690{
a98f90fd 1691 static struct snd_device_ops ops = {
a41d1224 1692 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1693 .dev_free = azx_dev_free,
1694 };
a07187c9 1695 struct hda_intel *hda;
a82d51ed
TI		 1696 struct azx *chip;
1697 int err;
1da177e4
LT		 1698
1699 *rchip = NULL;
bcd72003 1700
927fc866
PM		 1701 err = pci_enable_device(pci);
1702 if (err < 0)
1da177e4
LT		 1703 return err;
1704
a07187c9
ML		 1705 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1706 if (!hda) {
1da177e4
LT		 1707 pci_disable_device(pci);
1708 return -ENOMEM;
1709 }
1710
a07187c9 1711 chip = &hda->chip;
62932df8 1712 mutex_init(&chip->open_mutex);
1da177e4
LT		 1713 chip->card = card;
1714 chip->pci = pci;
a43ff5ba 1715 chip->ops = &pci_hda_ops;
9477c58e
TI		 1716 chip->driver_caps = driver_caps;
1717 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1718 check_msi(chip);
555e219f 1719 chip->dev_index = dev;
749ee287 1720 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1721 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1722 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1723 INIT_LIST_HEAD(&hda->list);
a82d51ed 1724 init_vga_switcheroo(chip);
9a34af4a 1725 init_completion(&hda->probe_wait);
1da177e4 1726
b6050ef6 1727 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1728
5aba4f8e 1729 check_probe_mask(chip, dev);
3372a153 1730
41438f13
TI		 1731 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1732 chip->fallback_to_single_cmd = 1;
1733 else /* explicitly set to single_cmd or not */
1734 chip->single_cmd = single_cmd;
1735
a1585d76 1736 azx_check_snoop_available(chip);
c74db86b 1737
4f0189be
TI		 1738 if (bdl_pos_adj[dev] < 0)
1739 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1740 else
1741 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1742
a41d1224
TI		 1743 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1744 if (err < 0) {
1745 kfree(hda);
1746 pci_disable_device(pci);
1747 return err;
1748 }
1749
7d9a1808
TI		 1750 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1751 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1752 chip->bus.needs_damn_long_delay = 1;
1753 }
1754
a82d51ed
TI		 1755 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1756 if (err < 0) {
4e76a883 1757 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1758 azx_free(chip);
1759 return err;
1760 }
1761
99a2008d 1762 /* continue probing in work context as may trigger request module */
9a34af4a 1763 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1764
a82d51ed 1765 *rchip = chip;
99a2008d 1766
a82d51ed
TI		 1767 return 0;
1768}
1769
48c8b0eb 1770static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1771{
1772 int dev = chip->dev_index;
1773 struct pci_dev *pci = chip->pci;
1774 struct snd_card *card = chip->card;
a41d1224 1775 struct hdac_bus *bus = azx_bus(chip);
67908994 1776 int err;
a82d51ed 1777 unsigned short gcap;
413cbf46 1778 unsigned int dma_bits = 64;
a82d51ed 1779
07e4ca50
TI		 1780#if BITS_PER_LONG != 64
1781 /* Fix up base address on ULI M5461 */
1782 if (chip->driver_type == AZX_DRIVER_ULI) {
1783 u16 tmp3;
1784 pci_read_config_word(pci, 0x40, &tmp3);
1785 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1786 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1787 }
1788#endif
1789
927fc866 1790 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1791 if (err < 0)
1da177e4 1792 return err;
a82d51ed 1793 chip->region_requested = 1;
1da177e4 1794
a41d1224
TI		 1795 bus->addr = pci_resource_start(pci, 0);
1796 bus->remap_addr = pci_ioremap_bar(pci, 0);
1797 if (bus->remap_addr == NULL) {
4e76a883 1798 dev_err(card->dev, "ioremap error\n");
a82d51ed 1799 return -ENXIO;
1da177e4
LT		 1800 }
1801
a4b4793f 1802 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1803 snd_hdac_bus_parse_capabilities(bus);
1804
1805 /*
1806 * Some Intel CPUs has always running timer (ART) feature and
1807 * controller may have Global time sync reporting capability, so
1808 * check both of these before declaring synchronized time reporting
1809 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1810 */
1811 chip->gts_present = false;
1812
1813#ifdef CONFIG_X86
1814 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1815 chip->gts_present = true;
1816#endif
1817
db79afa1
BH		 1818 if (chip->msi) {
1819 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1820 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1821 pci->no_64bit_msi = true;
1822 }
68e7fffc
TI		 1823 if (pci_enable_msi(pci) < 0)
1824 chip->msi = 0;
db79afa1 1825 }
7376d013 1826
a82d51ed
TI		 1827 if (azx_acquire_irq(chip, 0) < 0)
1828 return -EBUSY;
1da177e4
LT		 1829
1830 pci_set_master(pci);
a41d1224 1831 synchronize_irq(bus->irq);
1da177e4 1832
bcd72003 1833 gcap = azx_readw(chip, GCAP);
4e76a883 1834 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1835
413cbf46
TI		 1836 /* AMD devices support 40 or 48bit DMA, take the safe one */
1837 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1838 dma_bits = 40;
1839
dc4c2e6b 1840 /* disable SB600 64bit support for safety */
9477c58e 1841 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1842 struct pci_dev *p_smbus;
413cbf46 1843 dma_bits = 40;
dc4c2e6b
AB		 1844 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1845 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1846 NULL);
1847 if (p_smbus) {
1848 if (p_smbus->revision < 0x30)
fb1d8ac2 1849 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1850 pci_dev_put(p_smbus);
1851 }
1852 }
09240cf4 1853
3ab7511e
AB		 1854 /* NVidia hardware normally only supports up to 40 bits of DMA */
1855 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1856 dma_bits = 40;
1857
9477c58e
TI		 1858 /* disable 64bit DMA address on some devices */
1859 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1860 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1861 gcap &= ~AZX_GCAP_64OK;
9477c58e 1862 }
396087ea 1863
2ae66c26 1864 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1865 if (align_buffer_size >= 0)
1866 chip->align_buffer_size = !!align_buffer_size;
1867 else {
103884a3 1868 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1869 chip->align_buffer_size = 0;
7bfe059e
TI		 1870 else
1871 chip->align_buffer_size = 1;
1872 }
2ae66c26 1873
cf7aaca8 1874 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1875 if (!(gcap & AZX_GCAP_64OK))
1876 dma_bits = 32;
412b979c
QL		 1877 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1878 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1879 } else {
412b979c
QL		 1880 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1881 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1882 }
cf7aaca8 1883
8b6ed8e7
TI		 1884 /* read number of streams from GCAP register instead of using
1885 * hardcoded value
1886 */
1887 chip->capture_streams = (gcap >> 8) & 0x0f;
1888 chip->playback_streams = (gcap >> 12) & 0x0f;
1889 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1890 /* gcap didn't give any info, switching to old method */
1891
1892 switch (chip->driver_type) {
1893 case AZX_DRIVER_ULI:
1894 chip->playback_streams = ULI_NUM_PLAYBACK;
1895 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1896 break;
1897 case AZX_DRIVER_ATIHDMI:
1815b34a 1898 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1899 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1900 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1901 break;
c4da29ca 1902 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1903 default:
1904 chip->playback_streams = ICH6_NUM_PLAYBACK;
1905 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1906 break;
1907 }
07e4ca50 1908 }
8b6ed8e7
TI		 1909 chip->capture_index_offset = 0;
1910 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1911 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1912
df56c3db
JK		 1913 /* sanity check for the SDxCTL.STRM field overflow */
1914 if (chip->num_streams > 15 &&
1915 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1916 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1917 "forcing separate stream tags", chip->num_streams);
1918 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1919 }
1920
a41d1224
TI		 1921 /* initialize streams */
1922 err = azx_init_streams(chip);
81740861 1923 if (err < 0)
a82d51ed 1924 return err;
1da177e4 1925
a41d1224
TI		 1926 err = azx_alloc_stream_pages(chip);
1927 if (err < 0)
1928 return err;
1da177e4
LT		 1929
1930 /* initialize chip */
cb53c626 1931 azx_init_pci(chip);
e4d9e513 1932
bb03ed21
TI		 1933 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1934 snd_hdac_i915_set_bclk(bus);
e4d9e513 1935
0a673521 1936 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1937
1938 /* codec detection */
a41d1224 1939 if (!azx_bus(chip)->codec_mask) {
4e76a883 1940 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1941 return -ENODEV;
1da177e4
LT		 1942 }
1943
07e4ca50 1944 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1945 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1946 sizeof(card->shortname));
1947 snprintf(card->longname, sizeof(card->longname),
1948 "%s at 0x%lx irq %i",
a41d1224 1949 card->shortname, bus->addr, bus->irq);
07e4ca50 1950
1da177e4 1951 return 0;
1da177e4
LT		 1952}
1953
97c6a3d1 1954#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1955/* callback from request_firmware_nowait() */
1956static void azx_firmware_cb(const struct firmware *fw, void *context)
1957{
1958 struct snd_card *card = context;
1959 struct azx *chip = card->private_data;
1960 struct pci_dev *pci = chip->pci;
1961
1962 if (!fw) {
4e76a883 1963 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1964 goto error;
1965 }
1966
1967 chip->fw = fw;
1968 if (!chip->disabled) {
1969 /* continue probing */
1970 if (azx_probe_continue(chip))
1971 goto error;
1972 }
1973 return; /* OK */
1974
1975 error:
1976 snd_card_free(card);
1977 pci_set_drvdata(pci, NULL);
1978}
97c6a3d1 1979#endif
5cb543db 1980
40830813
DR		 1981/*
1982 * HDA controller ops.
1983 */
1984
1985/* PCI register access. */
db291e36 1986static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1987{
1988 writel(value, addr);
1989}
1990
db291e36 1991static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1992{
1993 return readl(addr);
1994}
1995
db291e36 1996static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1997{
1998 writew(value, addr);
1999}
2000
db291e36 2001static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 2002{
2003 return readw(addr);
2004}
2005
db291e36 2006static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 2007{
2008 writeb(value, addr);
2009}
2010
db291e36 2011static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 2012{
2013 return readb(addr);
2014}
2015
f46ea609
DR		 2016static int disable_msi_reset_irq(struct azx *chip)
2017{
a41d1224 2018 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 2019 int err;
2020
a41d1224
TI		 2021 free_irq(bus->irq, chip);
2022 bus->irq = -1;
f46ea609
DR		 2023 pci_disable_msi(chip->pci);
2024 chip->msi = 0;
2025 err = azx_acquire_irq(chip, 1);
2026 if (err < 0)
2027 return err;
2028
2029 return 0;
2030}
2031
b419b35b 2032/* DMA page allocation helpers. */
a43ff5ba 2033static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 2034 int type,
2035 size_t size,
2036 struct snd_dma_buffer *buf)
2037{
a41d1224 2038 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 2039 int err;
2040
2041 err = snd_dma_alloc_pages(type,
a43ff5ba 2042 bus->dev,
b419b35b
DR		 2043 size, buf);
2044 if (err < 0)
2045 return err;
2046 mark_pages_wc(chip, buf, true);
2047 return 0;
2048}
2049
a43ff5ba 2050static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 2051{
a41d1224 2052 struct azx *chip = bus_to_azx(bus);
a43ff5ba 2053
b419b35b
DR		 2054 mark_pages_wc(chip, buf, false);
2055 snd_dma_free_pages(buf);
2056}
2057
2058static int substream_alloc_pages(struct azx *chip,
2059 struct snd_pcm_substream *substream,
2060 size_t size)
2061{
2062 struct azx_dev *azx_dev = get_azx_dev(substream);
2063 int ret;
2064
2065 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 2066 ret = snd_pcm_lib_malloc_pages(substream, size);
2067 if (ret < 0)
2068 return ret;
2069 mark_runtime_wc(chip, azx_dev, substream, true);
2070 return 0;
2071}
2072
2073static int substream_free_pages(struct azx *chip,
2074 struct snd_pcm_substream *substream)
2075{
2076 struct azx_dev *azx_dev = get_azx_dev(substream);
2077 mark_runtime_wc(chip, azx_dev, substream, false);
2078 return snd_pcm_lib_free_pages(substream);
2079}
2080
8769b278
DR		 2081static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2082 struct vm_area_struct *area)
2083{
2084#ifdef CONFIG_X86
2085 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2086 struct azx *chip = apcm->chip;
3b70bdba 2087 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 2088 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2089#endif
2090}
2091
a43ff5ba 2092static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 2093 .reg_writel = pci_azx_writel,
2094 .reg_readl = pci_azx_readl,
2095 .reg_writew = pci_azx_writew,
2096 .reg_readw = pci_azx_readw,
2097 .reg_writeb = pci_azx_writeb,
2098 .reg_readb = pci_azx_readb,
b419b35b
DR		 2099 .dma_alloc_pages = dma_alloc_pages,
2100 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 2101};
2102
2103static const struct hda_controller_ops pci_hda_ops = {
2104 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 2105 .substream_alloc_pages = substream_alloc_pages,
2106 .substream_free_pages = substream_free_pages,
8769b278 2107 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 2108 .position_check = azx_position_check,
17eccb27 2109 .link_power = azx_intel_link_power,
40830813
DR		 2110};
2111
e23e7a14
BP		 2112static int azx_probe(struct pci_dev *pci,
2113 const struct pci_device_id *pci_id)
1da177e4 2114{
5aba4f8e 2115 static int dev;
a98f90fd 2116 struct snd_card *card;
9a34af4a 2117 struct hda_intel *hda;
a98f90fd 2118 struct azx *chip;
aad730d0 2119 bool schedule_probe;
927fc866 2120 int err;
1da177e4 2121
5aba4f8e
TI		 2122 if (dev >= SNDRV_CARDS)
2123 return -ENODEV;
2124 if (!enable[dev]) {
2125 dev++;
2126 return -ENOENT;
2127 }
2128
60c5772b
TI		 2129 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2130 0, &card);
e58de7ba 2131 if (err < 0) {
4e76a883 2132 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2133 return err;
1da177e4
LT		 2134 }
2135
a43ff5ba 2136 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2137 if (err < 0)
2138 goto out_free;
421a1252 2139 card->private_data = chip;
9a34af4a 2140 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2141
2142 pci_set_drvdata(pci, card);
2143
2144 err = register_vga_switcheroo(chip);
2145 if (err < 0) {
2b760d88 2146 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2147 goto out_free;
2148 }
2149
2150 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2151 dev_info(card->dev, "VGA controller is disabled\n");
2152 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2153 chip->disabled = true;
2154 }
2155
aad730d0 2156 schedule_probe = !chip->disabled;
1da177e4 2157
4918cdab
TI		 2158#ifdef CONFIG_SND_HDA_PATCH_LOADER
2159 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2160 dev_info(card->dev, "Applying patch firmware '%s'\n",
2161 patch[dev]);
5cb543db
TI		 2162 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2163 &pci->dev, GFP_KERNEL, card,
2164 azx_firmware_cb);
4918cdab
TI		 2165 if (err < 0)
2166 goto out_free;
aad730d0 2167 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2168 }
2169#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2170
aad730d0 2171#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2172 if (CONTROLLER_IN_GPU(pci))
2173 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2174#endif
99a2008d 2175
aad730d0 2176 if (schedule_probe)
9a34af4a 2177 schedule_work(&hda->probe_work);
a82d51ed 2178
a82d51ed 2179 dev++;
88d071fc 2180 if (chip->disabled)
9a34af4a 2181 complete_all(&hda->probe_wait);
a82d51ed
TI		 2182 return 0;
2183
2184out_free:
2185 snd_card_free(card);
2186 return err;
2187}
2188
e62a42ae
DR		 2189/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2190static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2191 [AZX_DRIVER_NVIDIA] = 8,
2192 [AZX_DRIVER_TERA] = 1,
2193};
2194
48c8b0eb 2195static int azx_probe_continue(struct azx *chip)
a82d51ed 2196{
9a34af4a 2197 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2198 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2199 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2200 int dev = chip->dev_index;
2201 int err;
2202
a41d1224 2203 hda->probe_continued = 1;
795614dd 2204
fcc88d91 2205 /* bind with i915 if needed */
dba9b7b6 2206 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
98d8fc6c 2207 err = snd_hdac_i915_init(bus);
535115b5
TI		 2208 if (err < 0) {
2209 /* if the controller is bound only with HDMI/DP
2210 * (for HSW and BDW), we need to abort the probe;
2211 * for other chips, still continue probing as other
2212 * codecs can be on the same link.
2213 */
bed2e98e
TI		 2214 if (CONTROLLER_IN_GPU(pci)) {
2215 dev_err(chip->card->dev,
2216 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2217 goto out_free;
fcc88d91
TI		 2218 } else {
2219 /* don't bother any longer */
dba9b7b6
TI		 2220 chip->driver_caps &=
2221 ~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL);
fcc88d91 2222 }
535115b5 2223 }
fcc88d91
TI		 2224 }
2225
2226 /* Request display power well for the HDA controller or codec. For
2227 * Haswell/Broadwell, both the display HDA controller and codec need
2228 * this power. For other platforms, like Baytrail/Braswell, only the
2229 * display codec needs the power and it can be released after probe.
2230 */
2231 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2232 /* HSW/BDW controllers need this power */
2233 if (CONTROLLER_IN_GPU(pci))
2234 hda->need_i915_power = 1;
795614dd 2235
98d8fc6c 2236 err = snd_hdac_display_power(bus, true);
74b0c2d7
TI		 2237 if (err < 0) {
2238 dev_err(chip->card->dev,
2239 "Cannot turn on display power on i915\n");
795614dd 2240 goto i915_power_fail;
74b0c2d7 2241 }
99a2008d
WX		 2242 }
2243
5c90680e
TI		 2244 err = azx_first_init(chip);
2245 if (err < 0)
2246 goto out_free;
2247
2dca0bba
JK		 2248#ifdef CONFIG_SND_HDA_INPUT_BEEP
2249 chip->beep_mode = beep_mode[dev];
2250#endif
2251
1da177e4 2252 /* create codec instances */
96d2bd6e 2253 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2254 if (err < 0)
2255 goto out_free;
96d2bd6e 2256
4ea6fbc8 2257#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2258 if (chip->fw) {
a41d1224 2259 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2260 chip->fw->data);
4ea6fbc8
TI		 2261 if (err < 0)
2262 goto out_free;
e39ae856 2263#ifndef CONFIG_PM
4918cdab
TI		 2264 release_firmware(chip->fw); /* no longer needed */
2265 chip->fw = NULL;
e39ae856 2266#endif
4ea6fbc8
TI		 2267 }
2268#endif
10e77dda 2269 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2270 err = azx_codec_configure(chip);
2271 if (err < 0)
2272 goto out_free;
2273 }
1da177e4 2274
a82d51ed 2275 err = snd_card_register(chip->card);
41dda0fd
WF		 2276 if (err < 0)
2277 goto out_free;
1da177e4 2278
cb53c626 2279 chip->running = 1;
65fcd41d 2280 azx_add_card_list(chip);
a41d1224 2281 snd_hda_set_power_save(&chip->bus, power_save * 1000);
364aa716 2282 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
30ff5957 2283 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2284
41dda0fd 2285out_free:
dba9b7b6 2286 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
795614dd 2287 && !hda->need_i915_power)
98d8fc6c 2288 snd_hdac_display_power(bus, false);
795614dd
ML		 2289
2290i915_power_fail:
88d071fc 2291 if (err < 0)
9a34af4a
TI		 2292 hda->init_failed = 1;
2293 complete_all(&hda->probe_wait);
41dda0fd 2294 return err;
1da177e4
LT		 2295}
2296
e23e7a14 2297static void azx_remove(struct pci_dev *pci)
1da177e4 2298{
9121947d 2299 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2300 struct azx *chip;
2301 struct hda_intel *hda;
2302
2303 if (card) {
0b8c8219 2304 /* cancel the pending probing work */
991f86d7
TI		 2305 chip = card->private_data;
2306 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2307 /* FIXME: below is an ugly workaround.
2308 * Both device_release_driver() and driver_probe_device()
2309 * take *both* the device's and its parent's lock before
2310 * calling the remove() and probe() callbacks. The codec
2311 * probe takes the locks of both the codec itself and its
2312 * parent, i.e. the PCI controller dev. Meanwhile, when
2313 * the PCI controller is unbound, it takes its lock, too
2314 * ==> ouch, a deadlock!
2315 * As a workaround, we unlock temporarily here the controller
2316 * device during cancel_work_sync() call.
2317 */
2318 device_unlock(&pci->dev);
0b8c8219 2319 cancel_work_sync(&hda->probe_work);
ab949d51 2320 device_lock(&pci->dev);
b8dfc462 2321
9121947d 2322 snd_card_free(card);
991f86d7 2323 }
1da177e4
LT		 2324}
2325
b2a0bafa
TI		 2326static void azx_shutdown(struct pci_dev *pci)
2327{
2328 struct snd_card *card = pci_get_drvdata(pci);
2329 struct azx *chip;
2330
2331 if (!card)
2332 return;
2333 chip = card->private_data;
2334 if (chip && chip->running)
2335 azx_stop_chip(chip);
2336}
2337
1da177e4 2338/* PCI IDs */
6f51f6cf 2339static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2340 /* CPT */
9477c58e 2341 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2342 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2343 /* PBG */
9477c58e 2344 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2345 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2346 /* Panther Point */
9477c58e 2347 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2348 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2349 /* Lynx Point */
2350 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2351 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2352 /* 9 Series */
2353 { PCI_DEVICE(0x8086, 0x8ca0),
2354 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2355 /* Wellsburg */
2356 { PCI_DEVICE(0x8086, 0x8d20),
2357 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2358 { PCI_DEVICE(0x8086, 0x8d21),
2359 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2360 /* Lewisburg */
2361 { PCI_DEVICE(0x8086, 0xa1f0),
e7480b34 2362 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
5cf92c8b 2363 { PCI_DEVICE(0x8086, 0xa270),
e7480b34 2364 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
144dad99
JR		 2365 /* Lynx Point-LP */
2366 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2367 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2368 /* Lynx Point-LP */
2369 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2370 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2371 /* Wildcat Point-LP */
2372 { PCI_DEVICE(0x8086, 0x9ca0),
2373 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2374 /* Sunrise Point */
2375 { PCI_DEVICE(0x8086, 0xa170),
a4b4793f 2376 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2377 /* Sunrise Point-LP */
2378 { PCI_DEVICE(0x8086, 0x9d70),
a4b4793f 2379 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2380 /* Kabylake */
2381 { PCI_DEVICE(0x8086, 0xa171),
a4b4793f 2382 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2383 /* Kabylake-LP */
2384 { PCI_DEVICE(0x8086, 0x9d71),
a4b4793f 2385 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2386 /* Kabylake-H */
2387 { PCI_DEVICE(0x8086, 0xa2f0),
a4b4793f 2388 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
e79b0006
MD		 2389 /* Coffelake */
2390 { PCI_DEVICE(0x8086, 0xa348),
a4b4793f 2391 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2357f6f0
GS		 2392 /* Cannonlake */
2393 { PCI_DEVICE(0x8086, 0x9dc8),
2394 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
c87693da
LH		 2395 /* Broxton-P(Apollolake) */
2396 { PCI_DEVICE(0x8086, 0x5a98),
a4b4793f 2397 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2398 /* Broxton-T */
2399 { PCI_DEVICE(0x8086, 0x1a98),
a4b4793f 2400 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
44b46d73
VK		 2401 /* Gemini-Lake */
2402 { PCI_DEVICE(0x8086, 0x3198),
a4b4793f 2403 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2404 /* Haswell */
4a7c516b 2405 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2406 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2407 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2408 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2409 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2410 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2411 /* Broadwell */
2412 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2413 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2414 /* 5 Series/3400 */
2415 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2416 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2417 /* Poulsbo */
9477c58e 2418 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2419 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2420 /* Oaktrail */
09904b95 2421 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2422 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2423 /* BayTrail */
2424 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2425 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2426 /* Braswell */
2427 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2428 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2429 /* ICH6 */
8b0bd226 2430 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2431 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2432 /* ICH7 */
8b0bd226 2433 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2434 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2435 /* ESB2 */
8b0bd226 2436 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2437 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2438 /* ICH8 */
8b0bd226 2439 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2440 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2441 /* ICH9 */
8b0bd226 2442 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2443 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2444 /* ICH9 */
8b0bd226 2445 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2446 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2447 /* ICH10 */
8b0bd226 2448 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2449 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2450 /* ICH10 */
8b0bd226 2451 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2452 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2453 /* Generic Intel */
2454 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2455 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2456 .class_mask = 0xffffff,
103884a3 2457 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2458 /* ATI SB 450/600/700/800/900 */
2459 { PCI_DEVICE(0x1002, 0x437b),
2460 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2461 { PCI_DEVICE(0x1002, 0x4383),
2462 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2463 /* AMD Hudson */
2464 { PCI_DEVICE(0x1022, 0x780d),
2465 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
9ceace3c
VM		 2466 /* AMD Raven */
2467 { PCI_DEVICE(0x1022, 0x15e3),
2468 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2469 /* ATI HDMI */
fd48331f
MSB		 2470 { PCI_DEVICE(0x1002, 0x0002),
2471 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
650474fb
AD		 2472 { PCI_DEVICE(0x1002, 0x1308),
2473 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2474 { PCI_DEVICE(0x1002, 0x157a),
2475 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
d716fb03
AB		 2476 { PCI_DEVICE(0x1002, 0x15b3),
2477 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2478 { PCI_DEVICE(0x1002, 0x793b),
2479 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2480 { PCI_DEVICE(0x1002, 0x7919),
2481 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2482 { PCI_DEVICE(0x1002, 0x960f),
2483 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2484 { PCI_DEVICE(0x1002, 0x970f),
2485 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2486 { PCI_DEVICE(0x1002, 0x9840),
2487 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2488 { PCI_DEVICE(0x1002, 0xaa00),
2489 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2490 { PCI_DEVICE(0x1002, 0xaa08),
2491 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2492 { PCI_DEVICE(0x1002, 0xaa10),
2493 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2494 { PCI_DEVICE(0x1002, 0xaa18),
2495 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2496 { PCI_DEVICE(0x1002, 0xaa20),
2497 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2498 { PCI_DEVICE(0x1002, 0xaa28),
2499 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2500 { PCI_DEVICE(0x1002, 0xaa30),
2501 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2502 { PCI_DEVICE(0x1002, 0xaa38),
2503 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2504 { PCI_DEVICE(0x1002, 0xaa40),
2505 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2506 { PCI_DEVICE(0x1002, 0xaa48),
2507 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2508 { PCI_DEVICE(0x1002, 0xaa50),
2509 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510 { PCI_DEVICE(0x1002, 0xaa58),
2511 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512 { PCI_DEVICE(0x1002, 0xaa60),
2513 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2514 { PCI_DEVICE(0x1002, 0xaa68),
2515 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2516 { PCI_DEVICE(0x1002, 0xaa80),
2517 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2518 { PCI_DEVICE(0x1002, 0xaa88),
2519 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2520 { PCI_DEVICE(0x1002, 0xaa90),
2521 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2522 { PCI_DEVICE(0x1002, 0xaa98),
2523 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2524 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2525 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2526 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2527 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2528 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2529 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2530 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2531 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2532 { PCI_DEVICE(0x1002, 0xaac0),
2533 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2534 { PCI_DEVICE(0x1002, 0xaac8),
2535 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2536 { PCI_DEVICE(0x1002, 0xaad8),
2537 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2538 { PCI_DEVICE(0x1002, 0xaae8),
2539 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
8eb22214
MSB		 2540 { PCI_DEVICE(0x1002, 0xaae0),
2541 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2542 { PCI_DEVICE(0x1002, 0xaaf0),
2543 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2544 /* VIA VT8251/VT8237A */
26f05717 2545 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2546 /* VIA GFX VT7122/VX900 */
2547 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2548 /* VIA GFX VT6122/VX11 */
2549 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2550 /* SIS966 */
2551 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2552 /* ULI M5461 */
2553 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2554 /* NVIDIA MCP */
0c2fd1bf
TI		 2555 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2556 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2557 .class_mask = 0xffffff,
9477c58e 2558 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2559 /* Teradici */
9477c58e
TI		 2560 { PCI_DEVICE(0x6549, 0x1200),
2561 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2562 { PCI_DEVICE(0x6549, 0x2200),
2563 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2564 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2565 /* CTHDA chips */
2566 { PCI_DEVICE(0x1102, 0x0010),
2567 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2568 { PCI_DEVICE(0x1102, 0x0012),
2569 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2570#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2571 /* the following entry conflicts with snd-ctxfi driver,
2572 * as ctxfi driver mutates from HD-audio to native mode with
2573 * a special command sequence.
2574 */
4e01f54b
TI		 2575 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2576 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2577 .class_mask = 0xffffff,
9477c58e 2578 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2579 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2580#else
2581 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2582 { PCI_DEVICE(0x1102, 0x0009),
2583 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2584 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2585#endif
c563f473
TI		 2586 /* CM8888 */
2587 { PCI_DEVICE(0x13f6, 0x5011),
2588 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2589 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2590 /* Vortex86MX */
2591 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2592 /* VMware HDAudio */
2593 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2594 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2595 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2596 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2597 .class_mask = 0xffffff,
9477c58e 2598 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2599 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2600 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2601 .class_mask = 0xffffff,
9477c58e 2602 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2603 { 0, }
2604};
2605MODULE_DEVICE_TABLE(pci, azx_ids);
2606
2607/* pci_driver definition */
e9f66d9b 2608static struct pci_driver azx_driver = {
3733e424 2609 .name = KBUILD_MODNAME,
1da177e4
LT		 2610 .id_table = azx_ids,
2611 .probe = azx_probe,
e23e7a14 2612 .remove = azx_remove,
b2a0bafa 2613 .shutdown = azx_shutdown,
68cb2b55
TI		 2614 .driver = {
2615 .pm = AZX_PM_OPS,
2616 },
1da177e4
LT		 2617};
2618
e9f66d9b 2619module_pci_driver(azx_driver);
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