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ALSA: hda - Call snd_hda_jack_report_sync() generically in hda_codec.c
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9
TI		 48#include <linux/io.h>
49#ifdef CONFIG_X86
50/* for snoop control */
51#include <asm/pgtable.h>
52#include <asm/cacheflush.h>
53#endif
1da177e4
LT		 54#include <sound/core.h>
55#include <sound/initval.h>
9121947d 56#include <linux/vgaarb.h>
a82d51ed 57#include <linux/vga_switcheroo.h>
4918cdab 58#include <linux/firmware.h>
1da177e4
LT		 59#include "hda_codec.h"
60
61
5aba4f8e
TI		 62static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
63static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 64static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e
TI		 65static char *model[SNDRV_CARDS];
66static int position_fix[SNDRV_CARDS];
5c0d7bc1 67static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 68static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 69static int probe_only[SNDRV_CARDS];
a67ff6a5 70static bool single_cmd;
71623855 71static int enable_msi = -1;
4ea6fbc8
TI		 72#ifdef CONFIG_SND_HDA_PATCH_LOADER
73static char *patch[SNDRV_CARDS];
74#endif
2dca0bba 75#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 76static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 77 CONFIG_SND_HDA_INPUT_BEEP_MODE};
78#endif
1da177e4 79
5aba4f8e 80module_param_array(index, int, NULL, 0444);
1da177e4 81MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 82module_param_array(id, charp, NULL, 0444);
1da177e4 83MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 84module_param_array(enable, bool, NULL, 0444);
85MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
86module_param_array(model, charp, NULL, 0444);
1da177e4 87MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 88module_param_array(position_fix, int, NULL, 0444);
4cb36310 89MODULE_PARM_DESC(position_fix, "DMA pointer read method."
a6f2fd55 90 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 91module_param_array(bdl_pos_adj, int, NULL, 0644);
92MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 93module_param_array(probe_mask, int, NULL, 0444);
606ad75f 94MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 95module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 96MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 97module_param(single_cmd, bool, 0444);
d01ce99f
TI		 98MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
99 "(for debugging only).");
ac9ef6cf 100module_param(enable_msi, bint, 0444);
134a11f0 101MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 102#ifdef CONFIG_SND_HDA_PATCH_LOADER
103module_param_array(patch, charp, NULL, 0444);
104MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
105#endif
2dca0bba 106#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 107module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 108MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 109 "(0=off, 1=on) (default=1).");
2dca0bba 110#endif
606ad75f 111
dee1b66c 112#ifdef CONFIG_SND_HDA_POWER_SAVE
65fcd41d
TI		 113static int param_set_xint(const char *val, const struct kernel_param *kp);
114static struct kernel_param_ops param_ops_xint = {
115 .set = param_set_xint,
116 .get = param_get_int,
117};
118#define param_check_xint param_check_int
119
fee2fba3 120static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 121module_param(power_save, xint, 0644);
fee2fba3
TI		 122MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
123 "(in second, 0 = disable).");
1da177e4 124
dee1b66c
TI		 125/* reset the HD-audio controller in power save mode.
126 * this may give more power-saving, but will take longer time to
127 * wake up.
128 */
a67ff6a5 129static bool power_save_controller = 1;
dee1b66c
TI		 130module_param(power_save_controller, bool, 0644);
131MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
132#endif
133
7bfe059e
TI		 134static int align_buffer_size = -1;
135module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 136MODULE_PARM_DESC(align_buffer_size,
137 "Force buffer and period sizes to be multiple of 128 bytes.");
138
27fe48d9
TI		 139#ifdef CONFIG_X86
140static bool hda_snoop = true;
141module_param_named(snoop, hda_snoop, bool, 0444);
142MODULE_PARM_DESC(snoop, "Enable/disable snooping");
143#define azx_snoop(chip) (chip)->snoop
144#else
145#define hda_snoop true
146#define azx_snoop(chip) true
147#endif
148
149
1da177e4
LT		 150MODULE_LICENSE("GPL");
151MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
152 "{Intel, ICH6M},"
2f1b3818 153 "{Intel, ICH7},"
f5d40b30 154 "{Intel, ESB2},"
d2981393 155 "{Intel, ICH8},"
f9cc8a8b 156 "{Intel, ICH9},"
c34f5a04 157 "{Intel, ICH10},"
b29c2360 158 "{Intel, PCH},"
d2f2fcd2 159 "{Intel, CPT},"
d2edeb7c 160 "{Intel, PPT},"
8bc039a1 161 "{Intel, LPT},"
144dad99 162 "{Intel, LPT_LP},"
e926f2c8 163 "{Intel, HPT},"
cea310e8 164 "{Intel, PBG},"
4979bca9 165 "{Intel, SCH},"
fc20a562 166 "{ATI, SB450},"
89be83f8 167 "{ATI, SB600},"
778b6e1b 168 "{ATI, RS600},"
5b15c95f 169 "{ATI, RS690},"
e6db1119
WL		 170 "{ATI, RS780},"
171 "{ATI, R600},"
2797f724
HRK		 172 "{ATI, RV630},"
173 "{ATI, RV610},"
27da1834
WL		 174 "{ATI, RV670},"
175 "{ATI, RV635},"
176 "{ATI, RV620},"
177 "{ATI, RV770},"
fc20a562 178 "{VIA, VT8251},"
47672310 179 "{VIA, VT8237A},"
07e4ca50
TI		 180 "{SiS, SIS966},"
181 "{ULI, M5461}}");
1da177e4
LT		 182MODULE_DESCRIPTION("Intel HDA driver");
183
4abc1cc2
TI		 184#ifdef CONFIG_SND_VERBOSE_PRINTK
185#define SFX /* nop */
186#else
1da177e4 187#define SFX "hda-intel: "
4abc1cc2 188#endif
cb53c626 189
a82d51ed
TI		 190#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
191#ifdef CONFIG_SND_HDA_CODEC_HDMI
192#define SUPPORT_VGA_SWITCHEROO
193#endif
194#endif
195
196
1da177e4
LT		 197/*
198 * registers
199 */
200#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 201#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
202#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
203#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
204#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
205#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 206#define ICH6_REG_VMIN 0x02
207#define ICH6_REG_VMAJ 0x03
208#define ICH6_REG_OUTPAY 0x04
209#define ICH6_REG_INPAY 0x06
210#define ICH6_REG_GCTL 0x08
8a933ece 211#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 212#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
213#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 214#define ICH6_REG_WAKEEN 0x0c
215#define ICH6_REG_STATESTS 0x0e
216#define ICH6_REG_GSTS 0x10
b21fadb9 217#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 218#define ICH6_REG_INTCTL 0x20
219#define ICH6_REG_INTSTS 0x24
e5463720 220#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 221#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
222#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 223#define ICH6_REG_CORBLBASE 0x40
224#define ICH6_REG_CORBUBASE 0x44
225#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 226#define ICH6_REG_CORBRP 0x4a
227#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 228#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 229#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
230#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 231#define ICH6_REG_CORBSTS 0x4d
b21fadb9 232#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 233#define ICH6_REG_CORBSIZE 0x4e
234
235#define ICH6_REG_RIRBLBASE 0x50
236#define ICH6_REG_RIRBUBASE 0x54
237#define ICH6_REG_RIRBWP 0x58
b21fadb9 238#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 239#define ICH6_REG_RINTCNT 0x5a
240#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 241#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
242#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
243#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 244#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 245#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
246#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 247#define ICH6_REG_RIRBSIZE 0x5e
248
249#define ICH6_REG_IC 0x60
250#define ICH6_REG_IR 0x64
251#define ICH6_REG_IRS 0x68
252#define ICH6_IRS_VALID (1<<1)
253#define ICH6_IRS_BUSY (1<<0)
254
255#define ICH6_REG_DPLBASE 0x70
256#define ICH6_REG_DPUBASE 0x74
257#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
258
259/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
260enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
261
262/* stream register offsets from stream base */
263#define ICH6_REG_SD_CTL 0x00
264#define ICH6_REG_SD_STS 0x03
265#define ICH6_REG_SD_LPIB 0x04
266#define ICH6_REG_SD_CBL 0x08
267#define ICH6_REG_SD_LVI 0x0c
268#define ICH6_REG_SD_FIFOW 0x0e
269#define ICH6_REG_SD_FIFOSIZE 0x10
270#define ICH6_REG_SD_FORMAT 0x12
271#define ICH6_REG_SD_BDLPL 0x18
272#define ICH6_REG_SD_BDLPU 0x1c
273
274/* PCI space */
275#define ICH6_PCIREG_TCSEL 0x44
276
277/*
278 * other constants
279 */
280
281/* max number of SDs */
07e4ca50 282/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 283#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 284#define ICH6_NUM_PLAYBACK 4
285
286/* ULI has 6 playback and 5 capture */
07e4ca50 287#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 288#define ULI_NUM_PLAYBACK 6
289
778b6e1b 290/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 291#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 292#define ATIHDMI_NUM_PLAYBACK 1
293
f269002e
KY		 294/* TERA has 4 playback and 3 capture */
295#define TERA_NUM_CAPTURE 3
296#define TERA_NUM_PLAYBACK 4
297
07e4ca50
TI		 298/* this number is statically defined for simplicity */
299#define MAX_AZX_DEV 16
300
1da177e4 301/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 302#define BDL_SIZE 4096
303#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
304#define AZX_MAX_FRAG 32
1da177e4
LT		 305/* max buffer size - no h/w limit, you can increase as you like */
306#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 307
308/* RIRB int mask: overrun[2], response[0] */
309#define RIRB_INT_RESPONSE 0x01
310#define RIRB_INT_OVERRUN 0x04
311#define RIRB_INT_MASK 0x05
312
2f5983f2 313/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 314#define AZX_MAX_CODECS 8
315#define AZX_DEFAULT_CODECS 4
deadff16 316#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 317
318/* SD_CTL bits */
319#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
320#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 321#define SD_CTL_STRIPE (3 << 16) /* stripe control */
322#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
323#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 324#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
325#define SD_CTL_STREAM_TAG_SHIFT 20
326
327/* SD_CTL and SD_STS */
328#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
329#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
330#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 331#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
332 SD_INT_COMPLETE)
1da177e4
LT		 333
334/* SD_STS */
335#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
336
337/* INTCTL and INTSTS */
d01ce99f
TI		 338#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
339#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
340#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 341
1da177e4
LT		 342/* below are so far hardcoded - should read registers in future */
343#define ICH6_MAX_CORB_ENTRIES 256
344#define ICH6_MAX_RIRB_ENTRIES 256
345
c74db86b
TI		 346/* position fix mode */
347enum {
0be3b5d3 348 POS_FIX_AUTO,
d2e1c973 349 POS_FIX_LPIB,
0be3b5d3 350 POS_FIX_POSBUF,
4cb36310 351 POS_FIX_VIACOMBO,
a6f2fd55 352 POS_FIX_COMBO,
c74db86b 353};
1da177e4 354
f5d40b30 355/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 356#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
357#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
358
da3fca21
V		 359/* Defines for Nvidia HDA support */
360#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
361#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 362#define NVIDIA_HDA_ISTRM_COH 0x4d
363#define NVIDIA_HDA_OSTRM_COH 0x4c
364#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 365
90a5ad52
TI		 366/* Defines for Intel SCH HDA snoop control */
367#define INTEL_SCH_HDA_DEVC 0x78
368#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
369
0e153474
JC		 370/* Define IN stream 0 FIFO size offset in VIA controller */
371#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
372/* Define VIA HD Audio Device ID*/
373#define VIA_HDAC_DEVICE_ID 0x3288
374
c4da29ca
YL		 375/* HD Audio class code */
376#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 377
1da177e4
LT		 378/*
379 */
380
a98f90fd 381struct azx_dev {
4ce107b9 382 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 383 u32 *posbuf; /* position buffer pointer */
1da177e4 384
d01ce99f 385 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 386 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 387 unsigned int frags; /* number for period in the play buffer */
388 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 389 unsigned long start_wallclk; /* start + minimum wallclk */
390 unsigned long period_wallclk; /* wallclk for period */
1da177e4 391
d01ce99f 392 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 393
d01ce99f 394 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 395
396 /* pcm support */
d01ce99f
TI		 397 struct snd_pcm_substream *substream; /* assigned substream,
398 * set in PCM open
399 */
400 unsigned int format_val; /* format value to be set in the
401 * controller and the codec
402 */
1da177e4
LT		 403 unsigned char stream_tag; /* assigned stream */
404 unsigned char index; /* stream index */
d5cf9911 405 int assigned_key; /* last device# key assigned to */
1da177e4 406
927fc866
PM		 407 unsigned int opened :1;
408 unsigned int running :1;
675f25d4 409 unsigned int irq_pending :1;
0e153474
JC		 410 /*
411 * For VIA:
412 * A flag to ensure DMA position is 0
413 * when link position is not greater than FIFO size
414 */
415 unsigned int insufficient :1;
27fe48d9 416 unsigned int wc_marked:1;
1da177e4
LT		 417};
418
419/* CORB/RIRB */
a98f90fd 420struct azx_rb {
1da177e4
LT		 421 u32 *buf; /* CORB/RIRB buffer
422 * Each CORB entry is 4byte, RIRB is 8byte
423 */
424 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
425 /* for RIRB */
426 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 427 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
428 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 429};
430
01b65bfb
TI		 431struct azx_pcm {
432 struct azx *chip;
433 struct snd_pcm *pcm;
434 struct hda_codec *codec;
435 struct hda_pcm_stream *hinfo[2];
436 struct list_head list;
437};
438
a98f90fd
TI		 439struct azx {
440 struct snd_card *card;
1da177e4 441 struct pci_dev *pci;
555e219f 442 int dev_index;
1da177e4 443
07e4ca50
TI		 444 /* chip type specific */
445 int driver_type;
9477c58e 446 unsigned int driver_caps;
07e4ca50
TI		 447 int playback_streams;
448 int playback_index_offset;
449 int capture_streams;
450 int capture_index_offset;
451 int num_streams;
452
1da177e4
LT		 453 /* pci resources */
454 unsigned long addr;
455 void __iomem *remap_addr;
456 int irq;
457
458 /* locks */
459 spinlock_t reg_lock;
62932df8 460 struct mutex open_mutex;
1da177e4 461
07e4ca50 462 /* streams (x num_streams) */
a98f90fd 463 struct azx_dev *azx_dev;
1da177e4
LT		 464
465 /* PCM */
01b65bfb 466 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 467
468 /* HD codec */
469 unsigned short codec_mask;
f1eaaeec 470 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 471 struct hda_bus *bus;
2dca0bba 472 unsigned int beep_mode;
1da177e4
LT		 473
474 /* CORB/RIRB */
a98f90fd
TI		 475 struct azx_rb corb;
476 struct azx_rb rirb;
1da177e4 477
4ce107b9 478 /* CORB/RIRB and position buffers */
1da177e4
LT		 479 struct snd_dma_buffer rb;
480 struct snd_dma_buffer posbuf;
c74db86b 481
4918cdab
TI		 482#ifdef CONFIG_SND_HDA_PATCH_LOADER
483 const struct firmware *fw;
484#endif
485
c74db86b 486 /* flags */
beaffc39 487 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 488 int poll_count;
cb53c626 489 unsigned int running :1;
927fc866
PM		 490 unsigned int initialized :1;
491 unsigned int single_cmd :1;
492 unsigned int polling_mode :1;
68e7fffc 493 unsigned int msi :1;
a6a950a8 494 unsigned int irq_pending_warned :1;
6ce4a3bc 495 unsigned int probing :1; /* codec probing phase */
27fe48d9 496 unsigned int snoop:1;
52409aa6 497 unsigned int align_buffer_size:1;
a82d51ed
TI		 498 unsigned int region_requested:1;
499
500 /* VGA-switcheroo setup */
501 unsigned int use_vga_switcheroo:1;
502 unsigned int init_failed:1; /* delayed init failed */
503 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 504
505 /* for debugging */
feb27340 506 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 507
508 /* for pending irqs */
509 struct work_struct irq_pending_work;
0cbf0098
TI		 510
511 /* reboot notifier (for mysterious hangup problem at power-down) */
512 struct notifier_block reboot_notifier;
65fcd41d
TI		 513
514 /* card list (for power_save trigger) */
515 struct list_head list;
1da177e4
LT		 516};
517
07e4ca50
TI		 518/* driver types */
519enum {
520 AZX_DRIVER_ICH,
32679f95 521 AZX_DRIVER_PCH,
4979bca9 522 AZX_DRIVER_SCH,
07e4ca50 523 AZX_DRIVER_ATI,
778b6e1b 524 AZX_DRIVER_ATIHDMI,
1815b34a 525 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 526 AZX_DRIVER_VIA,
527 AZX_DRIVER_SIS,
528 AZX_DRIVER_ULI,
da3fca21 529 AZX_DRIVER_NVIDIA,
f269002e 530 AZX_DRIVER_TERA,
14d34f16 531 AZX_DRIVER_CTX,
5ae763b1 532 AZX_DRIVER_CTHDA,
c4da29ca 533 AZX_DRIVER_GENERIC,
2f5983f2 534 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 535};
536
9477c58e
TI		 537/* driver quirks (capabilities) */
538/* bits 0-7 are used for indicating driver type */
539#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
540#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
541#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
542#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
543#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
544#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
545#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
546#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
547#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
548#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
549#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
550#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 551#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 552#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 553#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 554#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
c20c5a84 555#define AZX_DCAPS_POSFIX_COMBO (1 << 24) /* Use COMBO as default */
9477c58e
TI		 556
557/* quirks for ATI SB / AMD Hudson */
558#define AZX_DCAPS_PRESET_ATI_SB \
559 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
560 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
561
562/* quirks for ATI/AMD HDMI */
563#define AZX_DCAPS_PRESET_ATI_HDMI \
564 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
565
566/* quirks for Nvidia */
567#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e
TI		 568 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
569 AZX_DCAPS_ALIGN_BUFSIZE)
9477c58e 570
5ae763b1
TI		 571#define AZX_DCAPS_PRESET_CTHDA \
572 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
573
a82d51ed
TI		 574/*
575 * VGA-switcher support
576 */
577#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 578#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
579#else
580#define use_vga_switcheroo(chip) 0
581#endif
582
583#if defined(SUPPORT_VGA_SWITCHEROO) || defined(CONFIG_SND_HDA_PATCH_LOADER)
a82d51ed
TI		 584#define DELAYED_INIT_MARK
585#define DELAYED_INITDATA_MARK
a82d51ed
TI		 586#else
587#define DELAYED_INIT_MARK __devinit
588#define DELAYED_INITDATA_MARK __devinitdata
a82d51ed
TI		 589#endif
590
591static char *driver_short_names[] DELAYED_INITDATA_MARK = {
07e4ca50 592 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 593 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 594 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 595 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 596 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 597 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 598 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
599 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 600 [AZX_DRIVER_ULI] = "HDA ULI M5461",
601 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 602 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 603 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 604 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 605 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 606};
607
1da177e4
LT		 608/*
609 * macros for easy use
610 */
611#define azx_writel(chip,reg,value) \
612 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
613#define azx_readl(chip,reg) \
614 readl((chip)->remap_addr + ICH6_REG_##reg)
615#define azx_writew(chip,reg,value) \
616 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
617#define azx_readw(chip,reg) \
618 readw((chip)->remap_addr + ICH6_REG_##reg)
619#define azx_writeb(chip,reg,value) \
620 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
621#define azx_readb(chip,reg) \
622 readb((chip)->remap_addr + ICH6_REG_##reg)
623
624#define azx_sd_writel(dev,reg,value) \
625 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
626#define azx_sd_readl(dev,reg) \
627 readl((dev)->sd_addr + ICH6_REG_##reg)
628#define azx_sd_writew(dev,reg,value) \
629 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
630#define azx_sd_readw(dev,reg) \
631 readw((dev)->sd_addr + ICH6_REG_##reg)
632#define azx_sd_writeb(dev,reg,value) \
633 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
634#define azx_sd_readb(dev,reg) \
635 readb((dev)->sd_addr + ICH6_REG_##reg)
636
637/* for pcm support */
a98f90fd 638#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 639
27fe48d9
TI		 640#ifdef CONFIG_X86
641static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
642{
643 if (azx_snoop(chip))
644 return;
645 if (addr && size) {
646 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
647 if (on)
648 set_memory_wc((unsigned long)addr, pages);
649 else
650 set_memory_wb((unsigned long)addr, pages);
651 }
652}
653
654static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
655 bool on)
656{
657 __mark_pages_wc(chip, buf->area, buf->bytes, on);
658}
659static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
660 struct snd_pcm_runtime *runtime, bool on)
661{
662 if (azx_dev->wc_marked != on) {
663 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
664 azx_dev->wc_marked = on;
665 }
666}
667#else
668/* NOP for other archs */
669static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
670 bool on)
671{
672}
673static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
674 struct snd_pcm_runtime *runtime, bool on)
675{
676}
677#endif
678
68e7fffc 679static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 680static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 681/*
682 * Interface for HD codec
683 */
684
1da177e4
LT		 685/*
686 * CORB / RIRB interface
687 */
a98f90fd 688static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 689{
690 int err;
691
692 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 693 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
694 snd_dma_pci_data(chip->pci),
1da177e4
LT		 695 PAGE_SIZE, &chip->rb);
696 if (err < 0) {
697 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
698 return err;
699 }
27fe48d9 700 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 701 return 0;
702}
703
a98f90fd 704static void azx_init_cmd_io(struct azx *chip)
1da177e4 705{
cdb1fbf2 706 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 707 /* CORB set up */
708 chip->corb.addr = chip->rb.addr;
709 chip->corb.buf = (u32 *)chip->rb.area;
710 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 711 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 712
07e4ca50
TI		 713 /* set the corb size to 256 entries (ULI requires explicitly) */
714 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 715 /* set the corb write pointer to 0 */
716 azx_writew(chip, CORBWP, 0);
717 /* reset the corb hw read pointer */
b21fadb9 718 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 719 /* enable corb dma */
b21fadb9 720 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 721
722 /* RIRB set up */
723 chip->rirb.addr = chip->rb.addr + 2048;
724 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 725 chip->rirb.wp = chip->rirb.rp = 0;
726 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 727 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 728 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 729
07e4ca50
TI		 730 /* set the rirb size to 256 entries (ULI requires explicitly) */
731 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 732 /* reset the rirb hw write pointer */
b21fadb9 733 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 734 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 735 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 736 azx_writew(chip, RINTCNT, 0xc0);
737 else
738 azx_writew(chip, RINTCNT, 1);
1da177e4 739 /* enable rirb dma and response irq */
1da177e4 740 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 741 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 742}
743
a98f90fd 744static void azx_free_cmd_io(struct azx *chip)
1da177e4 745{
cdb1fbf2 746 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 747 /* disable ringbuffer DMAs */
748 azx_writeb(chip, RIRBCTL, 0);
749 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 750 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 751}
752
deadff16
WF		 753static unsigned int azx_command_addr(u32 cmd)
754{
755 unsigned int addr = cmd >> 28;
756
757 if (addr >= AZX_MAX_CODECS) {
758 snd_BUG();
759 addr = 0;
760 }
761
762 return addr;
763}
764
765static unsigned int azx_response_addr(u32 res)
766{
767 unsigned int addr = res & 0xf;
768
769 if (addr >= AZX_MAX_CODECS) {
770 snd_BUG();
771 addr = 0;
772 }
773
774 return addr;
1da177e4
LT		 775}
776
777/* send a command */
33fa35ed 778static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 779{
33fa35ed 780 struct azx *chip = bus->private_data;
deadff16 781 unsigned int addr = azx_command_addr(val);
1da177e4 782 unsigned int wp;
1da177e4 783
c32649fe
WF		 784 spin_lock_irq(&chip->reg_lock);
785
1da177e4
LT		 786 /* add command to corb */
787 wp = azx_readb(chip, CORBWP);
788 wp++;
789 wp %= ICH6_MAX_CORB_ENTRIES;
790
deadff16 791 chip->rirb.cmds[addr]++;
1da177e4
LT		 792 chip->corb.buf[wp] = cpu_to_le32(val);
793 azx_writel(chip, CORBWP, wp);
c32649fe 794
1da177e4
LT		 795 spin_unlock_irq(&chip->reg_lock);
796
797 return 0;
798}
799
800#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
801
802/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 803static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 804{
805 unsigned int rp, wp;
deadff16 806 unsigned int addr;
1da177e4
LT		 807 u32 res, res_ex;
808
809 wp = azx_readb(chip, RIRBWP);
810 if (wp == chip->rirb.wp)
811 return;
812 chip->rirb.wp = wp;
deadff16 813
1da177e4
LT		 814 while (chip->rirb.rp != wp) {
815 chip->rirb.rp++;
816 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
817
818 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
819 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
820 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 821 addr = azx_response_addr(res_ex);
1da177e4
LT		 822 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
823 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 824 else if (chip->rirb.cmds[addr]) {
825 chip->rirb.res[addr] = res;
2add9b92 826 smp_wmb();
deadff16 827 chip->rirb.cmds[addr]--;
e310bb06
WF		 828 } else
829 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
830 "last cmd=%#08x\n",
831 res, res_ex,
832 chip->last_cmd[addr]);
1da177e4
LT		 833 }
834}
835
836/* receive a response */
deadff16
WF		 837static unsigned int azx_rirb_get_response(struct hda_bus *bus,
838 unsigned int addr)
1da177e4 839{
33fa35ed 840 struct azx *chip = bus->private_data;
5c79b1f8 841 unsigned long timeout;
32cf4023 842 unsigned long loopcounter;
1eb6dc7d 843 int do_poll = 0;
1da177e4 844
5c79b1f8
TI		 845 again:
846 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 847
848 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 849 if (chip->polling_mode || do_poll) {
e96224ae
TI		 850 spin_lock_irq(&chip->reg_lock);
851 azx_update_rirb(chip);
852 spin_unlock_irq(&chip->reg_lock);
853 }
deadff16 854 if (!chip->rirb.cmds[addr]) {
2add9b92 855 smp_rmb();
b613291f 856 bus->rirb_error = 0;
1eb6dc7d
ML		 857
858 if (!do_poll)
859 chip->poll_count = 0;
deadff16 860 return chip->rirb.res[addr]; /* the last value */
2add9b92 861 }
28a0d9df
TI		 862 if (time_after(jiffies, timeout))
863 break;
32cf4023 864 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 865 msleep(2); /* temporary workaround */
866 else {
867 udelay(10);
868 cond_resched();
869 }
28a0d9df 870 }
5c79b1f8 871
1eb6dc7d
ML		 872 if (!chip->polling_mode && chip->poll_count < 2) {
873 snd_printdd(SFX "azx_get_response timeout, "
874 "polling the codec once: last cmd=0x%08x\n",
875 chip->last_cmd[addr]);
876 do_poll = 1;
877 chip->poll_count++;
878 goto again;
879 }
880
881
23c4a881
TI		 882 if (!chip->polling_mode) {
883 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
884 "switching to polling mode: last cmd=0x%08x\n",
885 chip->last_cmd[addr]);
886 chip->polling_mode = 1;
887 goto again;
888 }
889
68e7fffc 890 if (chip->msi) {
4abc1cc2 891 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 892 "disabling MSI: last cmd=0x%08x\n",
893 chip->last_cmd[addr]);
68e7fffc
TI		 894 free_irq(chip->irq, chip);
895 chip->irq = -1;
896 pci_disable_msi(chip->pci);
897 chip->msi = 0;
b613291f
TI		 898 if (azx_acquire_irq(chip, 1) < 0) {
899 bus->rirb_error = 1;
68e7fffc 900 return -1;
b613291f 901 }
68e7fffc
TI		 902 goto again;
903 }
904
6ce4a3bc
TI		 905 if (chip->probing) {
906 /* If this critical timeout happens during the codec probing
907 * phase, this is likely an access to a non-existing codec
908 * slot. Better to return an error and reset the system.
909 */
910 return -1;
911 }
912
8dd78330
TI		 913 /* a fatal communication error; need either to reset or to fallback
914 * to the single_cmd mode
915 */
b613291f 916 bus->rirb_error = 1;
b20f3b83 917 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 918 bus->response_reset = 1;
919 return -1; /* give a chance to retry */
920 }
921
922 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
923 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 924 chip->last_cmd[addr]);
8dd78330
TI		 925 chip->single_cmd = 1;
926 bus->response_reset = 0;
1a696978 927 /* release CORB/RIRB */
4fcd3920 928 azx_free_cmd_io(chip);
1a696978
TI		 929 /* disable unsolicited responses */
930 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 931 return -1;
1da177e4
LT		 932}
933
1da177e4
LT		 934/*
935 * Use the single immediate command instead of CORB/RIRB for simplicity
936 *
937 * Note: according to Intel, this is not preferred use. The command was
938 * intended for the BIOS only, and may get confused with unsolicited
939 * responses. So, we shouldn't use it for normal operation from the
940 * driver.
941 * I left the codes, however, for debugging/testing purposes.
942 */
943
b05a7d4f 944/* receive a response */
deadff16 945static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 946{
947 int timeout = 50;
948
949 while (timeout--) {
950 /* check IRV busy bit */
951 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
952 /* reuse rirb.res as the response return value */
deadff16 953 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 954 return 0;
955 }
956 udelay(1);
957 }
958 if (printk_ratelimit())
959 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
960 azx_readw(chip, IRS));
deadff16 961 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 962 return -EIO;
963}
964
1da177e4 965/* send a command */
33fa35ed 966static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 967{
33fa35ed 968 struct azx *chip = bus->private_data;
deadff16 969 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 970 int timeout = 50;
971
8dd78330 972 bus->rirb_error = 0;
1da177e4
LT		 973 while (timeout--) {
974 /* check ICB busy bit */
d01ce99f 975 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 976 /* Clear IRV valid bit */
d01ce99f
TI		 977 azx_writew(chip, IRS, azx_readw(chip, IRS) |
978 ICH6_IRS_VALID);
1da177e4 979 azx_writel(chip, IC, val);
d01ce99f
TI		 980 azx_writew(chip, IRS, azx_readw(chip, IRS) |
981 ICH6_IRS_BUSY);
deadff16 982 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 983 }
984 udelay(1);
985 }
1cfd52bc
MB		 986 if (printk_ratelimit())
987 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
988 azx_readw(chip, IRS), val);
1da177e4
LT		 989 return -EIO;
990}
991
992/* receive a response */
deadff16
WF		 993static unsigned int azx_single_get_response(struct hda_bus *bus,
994 unsigned int addr)
1da177e4 995{
33fa35ed 996 struct azx *chip = bus->private_data;
deadff16 997 return chip->rirb.res[addr];
1da177e4
LT		 998}
999
111d3af5
TI		 1000/*
1001 * The below are the main callbacks from hda_codec.
1002 *
1003 * They are just the skeleton to call sub-callbacks according to the
1004 * current setting of chip->single_cmd.
1005 */
1006
1007/* send a command */
33fa35ed 1008static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 1009{
33fa35ed 1010 struct azx *chip = bus->private_data;
43bbb6cc 1011
a82d51ed
TI		 1012 if (chip->disabled)
1013 return 0;
feb27340 1014 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 1015 if (chip->single_cmd)
33fa35ed 1016 return azx_single_send_cmd(bus, val);
111d3af5 1017 else
33fa35ed 1018 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 1019}
1020
1021/* get a response */
deadff16
WF		 1022static unsigned int azx_get_response(struct hda_bus *bus,
1023 unsigned int addr)
111d3af5 1024{
33fa35ed 1025 struct azx *chip = bus->private_data;
a82d51ed
TI		 1026 if (chip->disabled)
1027 return 0;
111d3af5 1028 if (chip->single_cmd)
deadff16 1029 return azx_single_get_response(bus, addr);
111d3af5 1030 else
deadff16 1031 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1032}
1033
cb53c626 1034#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 1035static void azx_power_notify(struct hda_bus *bus);
cb53c626 1036#endif
111d3af5 1037
1da177e4 1038/* reset codec link */
cd508fe5 1039static int azx_reset(struct azx *chip, int full_reset)
1da177e4
LT		 1040{
1041 int count;
1042
cd508fe5
JK		 1043 if (!full_reset)
1044 goto __skip;
1045
e8a7f136
DT		 1046 /* clear STATESTS */
1047 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1048
1da177e4
LT		 1049 /* reset controller */
1050 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1051
1052 count = 50;
1053 while (azx_readb(chip, GCTL) && --count)
1054 msleep(1);
1055
1056 /* delay for >= 100us for codec PLL to settle per spec
1057 * Rev 0.9 section 5.5.1
1058 */
1059 msleep(1);
1060
1061 /* Bring controller out of reset */
1062 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1063
1064 count = 50;
927fc866 1065 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 1066 msleep(1);
1067
927fc866 1068 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 1069 msleep(1);
1070
cd508fe5 1071 __skip:
1da177e4 1072 /* check to see if controller is ready */
927fc866 1073 if (!azx_readb(chip, GCTL)) {
4abc1cc2 1074 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 1075 return -EBUSY;
1076 }
1077
41e2fce4 1078 /* Accept unsolicited responses */
1a696978
TI		 1079 if (!chip->single_cmd)
1080 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1081 ICH6_GCTL_UNSOL);
41e2fce4 1082
1da177e4 1083 /* detect codecs */
927fc866 1084 if (!chip->codec_mask) {
1da177e4 1085 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 1086 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 1087 }
1088
1089 return 0;
1090}
1091
1092
1093/*
1094 * Lowlevel interface
1095 */
1096
1097/* enable interrupts */
a98f90fd 1098static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1099{
1100 /* enable controller CIE and GIE */
1101 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1102 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1103}
1104
1105/* disable interrupts */
a98f90fd 1106static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1107{
1108 int i;
1109
1110 /* disable interrupts in stream descriptor */
07e4ca50 1111 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1112 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1113 azx_sd_writeb(azx_dev, SD_CTL,
1114 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1115 }
1116
1117 /* disable SIE for all streams */
1118 azx_writeb(chip, INTCTL, 0);
1119
1120 /* disable controller CIE and GIE */
1121 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1122 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1123}
1124
1125/* clear interrupts */
a98f90fd 1126static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1127{
1128 int i;
1129
1130 /* clear stream status */
07e4ca50 1131 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1132 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1133 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1134 }
1135
1136 /* clear STATESTS */
1137 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1138
1139 /* clear rirb status */
1140 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1141
1142 /* clear int status */
1143 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1144}
1145
1146/* start a stream */
a98f90fd 1147static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1148{
0e153474
JC		 1149 /*
1150 * Before stream start, initialize parameter
1151 */
1152 azx_dev->insufficient = 1;
1153
1da177e4 1154 /* enable SIE */
ccc5df05
WN		 1155 azx_writel(chip, INTCTL,
1156 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1157 /* set DMA start and interrupt mask */
1158 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1159 SD_CTL_DMA_START | SD_INT_MASK);
1160}
1161
1dddab40
TI		 1162/* stop DMA */
1163static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1164{
1da177e4
LT		 1165 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1166 ~(SD_CTL_DMA_START | SD_INT_MASK));
1167 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1168}
1169
1170/* stop a stream */
1171static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1172{
1173 azx_stream_clear(chip, azx_dev);
1da177e4 1174 /* disable SIE */
ccc5df05
WN		 1175 azx_writel(chip, INTCTL,
1176 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1177}
1178
1179
1180/*
cb53c626 1181 * reset and start the controller registers
1da177e4 1182 */
cd508fe5 1183static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1184{
cb53c626
TI		 1185 if (chip->initialized)
1186 return;
1da177e4
LT		 1187
1188 /* reset controller */
cd508fe5 1189 azx_reset(chip, full_reset);
1da177e4
LT		 1190
1191 /* initialize interrupts */
1192 azx_int_clear(chip);
1193 azx_int_enable(chip);
1194
1195 /* initialize the codec command I/O */
1a696978
TI		 1196 if (!chip->single_cmd)
1197 azx_init_cmd_io(chip);
1da177e4 1198
0be3b5d3
TI		 1199 /* program the position buffer */
1200 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1201 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1202
cb53c626
TI		 1203 chip->initialized = 1;
1204}
1205
1206/*
1207 * initialize the PCI registers
1208 */
1209/* update bits in a PCI register byte */
1210static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1211 unsigned char mask, unsigned char val)
1212{
1213 unsigned char data;
1214
1215 pci_read_config_byte(pci, reg, &data);
1216 data &= ~mask;
1217 data |= (val & mask);
1218 pci_write_config_byte(pci, reg, data);
1219}
1220
1221static void azx_init_pci(struct azx *chip)
1222{
1223 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1224 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1225 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1226 * codecs.
1227 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1228 */
46f2cc80 1229 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
9477c58e 1230 snd_printdd(SFX "Clearing TCSEL\n");
a09e89f6 1231 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1232 }
cb53c626 1233
9477c58e
TI		 1234 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1235 * we need to enable snoop.
1236 */
1237 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
27fe48d9 1238 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
cb53c626 1239 update_pci_byte(chip->pci,
27fe48d9
TI		 1240 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1241 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1242 }
1243
1244 /* For NVIDIA HDA, enable snoop */
1245 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
27fe48d9 1246 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
cb53c626
TI		 1247 update_pci_byte(chip->pci,
1248 NVIDIA_HDA_TRANSREG_ADDR,
1249 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1250 update_pci_byte(chip->pci,
1251 NVIDIA_HDA_ISTRM_COH,
1252 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1253 update_pci_byte(chip->pci,
1254 NVIDIA_HDA_OSTRM_COH,
1255 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1256 }
1257
1258 /* Enable SCH/PCH snoop if needed */
1259 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1260 unsigned short snoop;
90a5ad52 1261 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1262 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1263 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1264 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1265 if (!azx_snoop(chip))
1266 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1267 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1268 pci_read_config_word(chip->pci,
1269 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1270 }
27fe48d9
TI		 1271 snd_printdd(SFX "SCH snoop: %s\n",
1272 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1273 ? "Disabled" : "Enabled");
da3fca21 1274 }
1da177e4
LT		 1275}
1276
1277
9ad593f6
TI		 1278static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1279
1da177e4
LT		 1280/*
1281 * interrupt handler
1282 */
7d12e780 1283static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1284{
a98f90fd
TI		 1285 struct azx *chip = dev_id;
1286 struct azx_dev *azx_dev;
1da177e4 1287 u32 status;
9ef04066 1288 u8 sd_status;
fa00e046 1289 int i, ok;
1da177e4
LT		 1290
1291 spin_lock(&chip->reg_lock);
1292
60911062
DC		 1293 if (chip->disabled) {
1294 spin_unlock(&chip->reg_lock);
a82d51ed 1295 return IRQ_NONE;
60911062 1296 }
a82d51ed 1297
1da177e4
LT		 1298 status = azx_readl(chip, INTSTS);
1299 if (status == 0) {
1300 spin_unlock(&chip->reg_lock);
1301 return IRQ_NONE;
1302 }
1303
07e4ca50 1304 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1305 azx_dev = &chip->azx_dev[i];
1306 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1307 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1308 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1309 if (!azx_dev->substream || !azx_dev->running ||
1310 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1311 continue;
1312 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1313 ok = azx_position_ok(chip, azx_dev);
1314 if (ok == 1) {
9ad593f6 1315 azx_dev->irq_pending = 0;
1da177e4
LT		 1316 spin_unlock(&chip->reg_lock);
1317 snd_pcm_period_elapsed(azx_dev->substream);
1318 spin_lock(&chip->reg_lock);
fa00e046 1319 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1320 /* bogus IRQ, process it later */
1321 azx_dev->irq_pending = 1;
6acaed38
TI		 1322 queue_work(chip->bus->workq,
1323 &chip->irq_pending_work);
1da177e4
LT		 1324 }
1325 }
1326 }
1327
1328 /* clear rirb int */
1329 status = azx_readb(chip, RIRBSTS);
1330 if (status & RIRB_INT_MASK) {
14d34f16 1331 if (status & RIRB_INT_RESPONSE) {
9477c58e 1332 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1333 udelay(80);
1da177e4 1334 azx_update_rirb(chip);
14d34f16 1335 }
1da177e4
LT		 1336 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1337 }
1338
1339#if 0
1340 /* clear state status int */
1341 if (azx_readb(chip, STATESTS) & 0x04)
1342 azx_writeb(chip, STATESTS, 0x04);
1343#endif
1344 spin_unlock(&chip->reg_lock);
1345
1346 return IRQ_HANDLED;
1347}
1348
1349
675f25d4
TI		 1350/*
1351 * set up a BDL entry
1352 */
5ae763b1
TI		 1353static int setup_bdle(struct azx *chip,
1354 struct snd_pcm_substream *substream,
675f25d4
TI		 1355 struct azx_dev *azx_dev, u32 **bdlp,
1356 int ofs, int size, int with_ioc)
1357{
675f25d4
TI		 1358 u32 *bdl = *bdlp;
1359
1360 while (size > 0) {
1361 dma_addr_t addr;
1362 int chunk;
1363
1364 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1365 return -EINVAL;
1366
77a23f26 1367 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1368 /* program the address field of the BDL entry */
1369 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1370 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1371 /* program the size field of the BDL entry */
fc4abee8 1372 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
5ae763b1
TI		 1373 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1374 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1375 u32 remain = 0x1000 - (ofs & 0xfff);
1376 if (chunk > remain)
1377 chunk = remain;
1378 }
675f25d4
TI		 1379 bdl[2] = cpu_to_le32(chunk);
1380 /* program the IOC to enable interrupt
1381 * only when the whole fragment is processed
1382 */
1383 size -= chunk;
1384 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1385 bdl += 4;
1386 azx_dev->frags++;
1387 ofs += chunk;
1388 }
1389 *bdlp = bdl;
1390 return ofs;
1391}
1392
1da177e4
LT		 1393/*
1394 * set up BDL entries
1395 */
555e219f
TI		 1396static int azx_setup_periods(struct azx *chip,
1397 struct snd_pcm_substream *substream,
4ce107b9 1398 struct azx_dev *azx_dev)
1da177e4 1399{
4ce107b9
TI		 1400 u32 *bdl;
1401 int i, ofs, periods, period_bytes;
555e219f 1402 int pos_adj;
1da177e4
LT		 1403
1404 /* reset BDL address */
1405 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1406 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1407
97b71c94 1408 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1409 periods = azx_dev->bufsize / period_bytes;
1410
1da177e4 1411 /* program the initial BDL entries */
4ce107b9
TI		 1412 bdl = (u32 *)azx_dev->bdl.area;
1413 ofs = 0;
1414 azx_dev->frags = 0;
555e219f
TI		 1415 pos_adj = bdl_pos_adj[chip->dev_index];
1416 if (pos_adj > 0) {
675f25d4 1417 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1418 int pos_align = pos_adj;
555e219f 1419 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1420 if (!pos_adj)
e785d3d8
TI		 1421 pos_adj = pos_align;
1422 else
1423 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1424 pos_align;
675f25d4
TI		 1425 pos_adj = frames_to_bytes(runtime, pos_adj);
1426 if (pos_adj >= period_bytes) {
4abc1cc2 1427 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1428 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1429 pos_adj = 0;
1430 } else {
5ae763b1 1431 ofs = setup_bdle(chip, substream, azx_dev,
7bb8fb70
CL		 1432 &bdl, ofs, pos_adj,
1433 !substream->runtime->no_period_wakeup);
675f25d4
TI		 1434 if (ofs < 0)
1435 goto error;
4ce107b9 1436 }
555e219f
TI		 1437 } else
1438 pos_adj = 0;
675f25d4
TI		 1439 for (i = 0; i < periods; i++) {
1440 if (i == periods - 1 && pos_adj)
5ae763b1 1441 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
675f25d4
TI		 1442 period_bytes - pos_adj, 0);
1443 else
5ae763b1 1444 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
7bb8fb70
CL		 1445 period_bytes,
1446 !substream->runtime->no_period_wakeup);
675f25d4
TI		 1447 if (ofs < 0)
1448 goto error;
1da177e4 1449 }
4ce107b9 1450 return 0;
675f25d4
TI		 1451
1452 error:
4abc1cc2 1453 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1454 azx_dev->bufsize, period_bytes);
675f25d4 1455 return -EINVAL;
1da177e4
LT		 1456}
1457
1dddab40
TI		 1458/* reset stream */
1459static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1460{
1461 unsigned char val;
1462 int timeout;
1463
1dddab40
TI		 1464 azx_stream_clear(chip, azx_dev);
1465
d01ce99f
TI		 1466 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1467 SD_CTL_STREAM_RESET);
1da177e4
LT		 1468 udelay(3);
1469 timeout = 300;
1470 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1471 --timeout)
1472 ;
1473 val &= ~SD_CTL_STREAM_RESET;
1474 azx_sd_writeb(azx_dev, SD_CTL, val);
1475 udelay(3);
1476
1477 timeout = 300;
1478 /* waiting for hardware to report that the stream is out of reset */
1479 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1480 --timeout)
1481 ;
fa00e046
JK		 1482
1483 /* reset first position - may not be synced with hw at this time */
1484 *azx_dev->posbuf = 0;
1dddab40 1485}
1da177e4 1486
1dddab40
TI		 1487/*
1488 * set up the SD for streaming
1489 */
1490static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1491{
27fe48d9 1492 unsigned int val;
1dddab40
TI		 1493 /* make sure the run bit is zero for SD */
1494 azx_stream_clear(chip, azx_dev);
1da177e4 1495 /* program the stream_tag */
27fe48d9
TI		 1496 val = azx_sd_readl(azx_dev, SD_CTL);
1497 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1498 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1499 if (!azx_snoop(chip))
1500 val |= SD_CTL_TRAFFIC_PRIO;
1501 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1502
1503 /* program the length of samples in cyclic buffer */
1504 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1505
1506 /* program the stream format */
1507 /* this value needs to be the same as the one programmed */
1508 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1509
1510 /* program the stream LVI (last valid index) of the BDL */
1511 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1512
1513 /* program the BDL address */
1514 /* lower BDL address */
4ce107b9 1515 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1516 /* upper BDL address */
766979e0 1517 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1518
0be3b5d3 1519 /* enable the position buffer */
4cb36310
DH		 1520 if (chip->position_fix[0] != POS_FIX_LPIB ||
1521 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1522 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1523 azx_writel(chip, DPLBASE,
1524 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1525 }
c74db86b 1526
1da177e4 1527 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1528 azx_sd_writel(azx_dev, SD_CTL,
1529 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1530
1531 return 0;
1532}
1533
6ce4a3bc
TI		 1534/*
1535 * Probe the given codec address
1536 */
1537static int probe_codec(struct azx *chip, int addr)
1538{
1539 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1540 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1541 unsigned int res;
1542
a678cdee 1543 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1544 chip->probing = 1;
1545 azx_send_cmd(chip->bus, cmd);
deadff16 1546 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1547 chip->probing = 0;
a678cdee 1548 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1549 if (res == -1)
1550 return -EIO;
4abc1cc2 1551 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1552 return 0;
1553}
1554
33fa35ed
TI		 1555static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1556 struct hda_pcm *cpcm);
6ce4a3bc 1557static void azx_stop_chip(struct azx *chip);
1da177e4 1558
8dd78330
TI		 1559static void azx_bus_reset(struct hda_bus *bus)
1560{
1561 struct azx *chip = bus->private_data;
8dd78330
TI		 1562
1563 bus->in_reset = 1;
1564 azx_stop_chip(chip);
cd508fe5 1565 azx_init_chip(chip, 1);
65f75983 1566#ifdef CONFIG_PM
8dd78330 1567 if (chip->initialized) {
01b65bfb
TI		 1568 struct azx_pcm *p;
1569 list_for_each_entry(p, &chip->pcm_list, list)
1570 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1571 snd_hda_suspend(chip->bus);
1572 snd_hda_resume(chip->bus);
1573 }
65f75983 1574#endif
8dd78330
TI		 1575 bus->in_reset = 0;
1576}
1577
1da177e4
LT		 1578/*
1579 * Codec initialization
1580 */
1581
2f5983f2 1582/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
a82d51ed 1583static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
7445dfc1 1584 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1585 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1586};
1587
a82d51ed 1588static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1589{
1590 struct hda_bus_template bus_temp;
34c25350
TI		 1591 int c, codecs, err;
1592 int max_slots;
1da177e4
LT		 1593
1594 memset(&bus_temp, 0, sizeof(bus_temp));
1595 bus_temp.private_data = chip;
1596 bus_temp.modelname = model;
1597 bus_temp.pci = chip->pci;
111d3af5
TI		 1598 bus_temp.ops.command = azx_send_cmd;
1599 bus_temp.ops.get_response = azx_get_response;
176d5335 1600 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1601 bus_temp.ops.bus_reset = azx_bus_reset;
cb53c626 1602#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1603 bus_temp.power_save = &power_save;
cb53c626
TI		 1604 bus_temp.ops.pm_notify = azx_power_notify;
1605#endif
1da177e4 1606
d01ce99f
TI		 1607 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1608 if (err < 0)
1da177e4
LT		 1609 return err;
1610
9477c58e
TI		 1611 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1612 snd_printd(SFX "Enable delay in RIRB handling\n");
dc9c8e21 1613 chip->bus->needs_damn_long_delay = 1;
9477c58e 1614 }
dc9c8e21 1615
34c25350 1616 codecs = 0;
2f5983f2
TI		 1617 max_slots = azx_max_codecs[chip->driver_type];
1618 if (!max_slots)
7445dfc1 1619 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1620
1621 /* First try to probe all given codec slots */
1622 for (c = 0; c < max_slots; c++) {
f1eaaeec 1623 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1624 if (probe_codec(chip, c) < 0) {
1625 /* Some BIOSen give you wrong codec addresses
1626 * that don't exist
1627 */
4abc1cc2
TI		 1628 snd_printk(KERN_WARNING SFX
1629 "Codec #%d probe error; "
6ce4a3bc
TI		 1630 "disabling it...\n", c);
1631 chip->codec_mask &= ~(1 << c);
1632 /* More badly, accessing to a non-existing
1633 * codec often screws up the controller chip,
2448158e 1634 * and disturbs the further communications.
6ce4a3bc
TI		 1635 * Thus if an error occurs during probing,
1636 * better to reset the controller chip to
1637 * get back to the sanity state.
1638 */
1639 azx_stop_chip(chip);
cd508fe5 1640 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1641 }
1642 }
1643 }
1644
d507cd66
TI		 1645 /* AMD chipsets often cause the communication stalls upon certain
1646 * sequence like the pin-detection. It seems that forcing the synced
1647 * access works around the stall. Grrr...
1648 */
9477c58e
TI		 1649 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1650 snd_printd(SFX "Enable sync_write for stable communication\n");
d507cd66
TI		 1651 chip->bus->sync_write = 1;
1652 chip->bus->allow_bus_reset = 1;
1653 }
1654
6ce4a3bc 1655 /* Then create codec instances */
34c25350 1656 for (c = 0; c < max_slots; c++) {
f1eaaeec 1657 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1658 struct hda_codec *codec;
a1e21c90 1659 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1660 if (err < 0)
1661 continue;
2dca0bba 1662 codec->beep_mode = chip->beep_mode;
1da177e4 1663 codecs++;
19a982b6
TI		 1664 }
1665 }
1666 if (!codecs) {
1da177e4
LT		 1667 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1668 return -ENXIO;
1669 }
a1e21c90
TI		 1670 return 0;
1671}
1da177e4 1672
a1e21c90
TI		 1673/* configure each codec instance */
1674static int __devinit azx_codec_configure(struct azx *chip)
1675{
1676 struct hda_codec *codec;
1677 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1678 snd_hda_codec_configure(codec);
1679 }
1da177e4
LT		 1680 return 0;
1681}
1682
1683
1684/*
1685 * PCM support
1686 */
1687
1688/* assign a stream for the PCM */
ef18bede
WF		 1689static inline struct azx_dev *
1690azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1691{
07e4ca50 1692 int dev, i, nums;
ef18bede 1693 struct azx_dev *res = NULL;
d5cf9911
TI		 1694 /* make a non-zero unique key for the substream */
1695 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1696 (substream->stream + 1);
ef18bede
WF		 1697
1698 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1699 dev = chip->playback_index_offset;
1700 nums = chip->playback_streams;
1701 } else {
1702 dev = chip->capture_index_offset;
1703 nums = chip->capture_streams;
1704 }
1705 for (i = 0; i < nums; i++, dev++)
d01ce99f 1706 if (!chip->azx_dev[dev].opened) {
ef18bede 1707 res = &chip->azx_dev[dev];
d5cf9911 1708 if (res->assigned_key == key)
ef18bede 1709 break;
1da177e4 1710 }
ef18bede
WF		 1711 if (res) {
1712 res->opened = 1;
d5cf9911 1713 res->assigned_key = key;
ef18bede
WF		 1714 }
1715 return res;
1da177e4
LT		 1716}
1717
1718/* release the assigned stream */
a98f90fd 1719static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1720{
1721 azx_dev->opened = 0;
1722}
1723
a98f90fd 1724static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1725 .info = (SNDRV_PCM_INFO_MMAP |
1726 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1727 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1728 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1729 /* No full-resume yet implemented */
1730 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1731 SNDRV_PCM_INFO_PAUSE |
7bb8fb70
CL		 1732 SNDRV_PCM_INFO_SYNC_START |
1733 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1734 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1735 .rates = SNDRV_PCM_RATE_48000,
1736 .rate_min = 48000,
1737 .rate_max = 48000,
1738 .channels_min = 2,
1739 .channels_max = 2,
1740 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1741 .period_bytes_min = 128,
1742 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1743 .periods_min = 2,
1744 .periods_max = AZX_MAX_FRAG,
1745 .fifo_size = 0,
1746};
1747
a98f90fd 1748static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1749{
1750 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1751 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1752 struct azx *chip = apcm->chip;
1753 struct azx_dev *azx_dev;
1754 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1755 unsigned long flags;
1756 int err;
2ae66c26 1757 int buff_step;
1da177e4 1758
62932df8 1759 mutex_lock(&chip->open_mutex);
ef18bede 1760 azx_dev = azx_assign_device(chip, substream);
1da177e4 1761 if (azx_dev == NULL) {
62932df8 1762 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1763 return -EBUSY;
1764 }
1765 runtime->hw = azx_pcm_hw;
1766 runtime->hw.channels_min = hinfo->channels_min;
1767 runtime->hw.channels_max = hinfo->channels_max;
1768 runtime->hw.formats = hinfo->formats;
1769 runtime->hw.rates = hinfo->rates;
1770 snd_pcm_limit_hw_rates(runtime);
1771 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
52409aa6 1772 if (chip->align_buffer_size)
2ae66c26
PLB		 1773 /* constrain buffer sizes to be multiple of 128
1774 bytes. This is more efficient in terms of memory
1775 access but isn't required by the HDA spec and
1776 prevents users from specifying exact period/buffer
1777 sizes. For example for 44.1kHz, a period size set
1778 to 20ms will be rounded to 19.59ms. */
1779 buff_step = 128;
1780 else
1781 /* Don't enforce steps on buffer sizes, still need to
1782 be multiple of 4 bytes (HDA spec). Tested on Intel
1783 HDA controllers, may not work on all devices where
1784 option needs to be disabled */
1785 buff_step = 4;
1786
5f1545bc 1787 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 1788 buff_step);
5f1545bc 1789 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 1790 buff_step);
b4a91cf0 1791 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 1792 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1793 if (err < 0) {
1da177e4 1794 azx_release_device(azx_dev);
cb53c626 1795 snd_hda_power_down(apcm->codec);
62932df8 1796 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1797 return err;
1798 }
70d321e6 1799 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1800 /* sanity check */
1801 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1802 snd_BUG_ON(!runtime->hw.channels_max) ||
1803 snd_BUG_ON(!runtime->hw.formats) ||
1804 snd_BUG_ON(!runtime->hw.rates)) {
1805 azx_release_device(azx_dev);
1806 hinfo->ops.close(hinfo, apcm->codec, substream);
1807 snd_hda_power_down(apcm->codec);
1808 mutex_unlock(&chip->open_mutex);
1809 return -EINVAL;
1810 }
1da177e4
LT		 1811 spin_lock_irqsave(&chip->reg_lock, flags);
1812 azx_dev->substream = substream;
1813 azx_dev->running = 0;
1814 spin_unlock_irqrestore(&chip->reg_lock, flags);
1815
1816 runtime->private_data = azx_dev;
850f0e52 1817 snd_pcm_set_sync(substream);
62932df8 1818 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1819 return 0;
1820}
1821
a98f90fd 1822static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1823{
1824 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1825 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1826 struct azx *chip = apcm->chip;
1827 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1828 unsigned long flags;
1829
62932df8 1830 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1831 spin_lock_irqsave(&chip->reg_lock, flags);
1832 azx_dev->substream = NULL;
1833 azx_dev->running = 0;
1834 spin_unlock_irqrestore(&chip->reg_lock, flags);
1835 azx_release_device(azx_dev);
1836 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1837 snd_hda_power_down(apcm->codec);
62932df8 1838 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1839 return 0;
1840}
1841
d01ce99f
TI		 1842static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1843 struct snd_pcm_hw_params *hw_params)
1da177e4 1844{
27fe48d9
TI		 1845 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1846 struct azx *chip = apcm->chip;
1847 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94 1848 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 1849 int ret;
97b71c94 1850
27fe48d9 1851 mark_runtime_wc(chip, azx_dev, runtime, false);
97b71c94
TI		 1852 azx_dev->bufsize = 0;
1853 azx_dev->period_bytes = 0;
1854 azx_dev->format_val = 0;
27fe48d9 1855 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 1856 params_buffer_bytes(hw_params));
27fe48d9
TI		 1857 if (ret < 0)
1858 return ret;
1859 mark_runtime_wc(chip, azx_dev, runtime, true);
1860 return ret;
1da177e4
LT		 1861}
1862
a98f90fd 1863static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1864{
1865 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1866 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9
TI		 1867 struct azx *chip = apcm->chip;
1868 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1869 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1870
1871 /* reset BDL address */
1872 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1873 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1874 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1875 azx_dev->bufsize = 0;
1876 azx_dev->period_bytes = 0;
1877 azx_dev->format_val = 0;
1da177e4 1878
eb541337 1879 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 1880
27fe48d9 1881 mark_runtime_wc(chip, azx_dev, runtime, false);
1da177e4
LT		 1882 return snd_pcm_lib_free_pages(substream);
1883}
1884
a98f90fd 1885static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1886{
1887 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1888 struct azx *chip = apcm->chip;
1889 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1890 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1891 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 1892 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 1893 int err;
7c935976
SW		 1894 struct hda_spdif_out *spdif =
1895 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1896 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 1897
fa00e046 1898 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1899 format_val = snd_hda_calc_stream_format(runtime->rate,
1900 runtime->channels,
1901 runtime->format,
32c168c8 1902 hinfo->maxbps,
7c935976 1903 ctls);
97b71c94 1904 if (!format_val) {
d01ce99f
TI		 1905 snd_printk(KERN_ERR SFX
1906 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1907 runtime->rate, runtime->channels, runtime->format);
1908 return -EINVAL;
1909 }
1910
97b71c94
TI		 1911 bufsize = snd_pcm_lib_buffer_bytes(substream);
1912 period_bytes = snd_pcm_lib_period_bytes(substream);
1913
4abc1cc2 1914 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1915 bufsize, format_val);
1916
1917 if (bufsize != azx_dev->bufsize ||
1918 period_bytes != azx_dev->period_bytes ||
1919 format_val != azx_dev->format_val) {
1920 azx_dev->bufsize = bufsize;
1921 azx_dev->period_bytes = period_bytes;
1922 azx_dev->format_val = format_val;
1923 err = azx_setup_periods(chip, substream, azx_dev);
1924 if (err < 0)
1925 return err;
1926 }
1927
e5463720
JK		 1928 /* wallclk has 24Mhz clock source */
1929 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1930 runtime->rate) * 1000);
1da177e4
LT		 1931 azx_setup_controller(chip, azx_dev);
1932 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1933 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1934 else
1935 azx_dev->fifo_size = 0;
1936
62b7e5e0
TI		 1937 stream_tag = azx_dev->stream_tag;
1938 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 1939 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 1940 stream_tag > chip->capture_streams)
1941 stream_tag -= chip->capture_streams;
1942 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 1943 azx_dev->format_val, substream);
1da177e4
LT		 1944}
1945
a98f90fd 1946static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1947{
1948 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1949 struct azx *chip = apcm->chip;
850f0e52
TI		 1950 struct azx_dev *azx_dev;
1951 struct snd_pcm_substream *s;
fa00e046 1952 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1953 int nwait, timeout;
1da177e4 1954
1da177e4 1955 switch (cmd) {
fa00e046
JK		 1956 case SNDRV_PCM_TRIGGER_START:
1957 rstart = 1;
1da177e4
LT		 1958 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1959 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1960 start = 1;
1da177e4
LT		 1961 break;
1962 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1963 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1964 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1965 start = 0;
1da177e4
LT		 1966 break;
1967 default:
850f0e52
TI		 1968 return -EINVAL;
1969 }
1970
1971 snd_pcm_group_for_each_entry(s, substream) {
1972 if (s->pcm->card != substream->pcm->card)
1973 continue;
1974 azx_dev = get_azx_dev(s);
1975 sbits |= 1 << azx_dev->index;
1976 nsync++;
1977 snd_pcm_trigger_done(s, substream);
1978 }
1979
1980 spin_lock(&chip->reg_lock);
1981 if (nsync > 1) {
1982 /* first, set SYNC bits of corresponding streams */
8b0bd226
TI		 1983 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1984 azx_writel(chip, OLD_SSYNC,
1985 azx_readl(chip, OLD_SSYNC) | sbits);
1986 else
1987 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
850f0e52
TI		 1988 }
1989 snd_pcm_group_for_each_entry(s, substream) {
1990 if (s->pcm->card != substream->pcm->card)
1991 continue;
1992 azx_dev = get_azx_dev(s);
e5463720
JK		 1993 if (start) {
1994 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1995 if (!rstart)
1996 azx_dev->start_wallclk -=
1997 azx_dev->period_wallclk;
850f0e52 1998 azx_stream_start(chip, azx_dev);
e5463720 1999 } else {
850f0e52 2000 azx_stream_stop(chip, azx_dev);
e5463720 2001 }
850f0e52 2002 azx_dev->running = start;
1da177e4
LT		 2003 }
2004 spin_unlock(&chip->reg_lock);
850f0e52
TI		 2005 if (start) {
2006 if (nsync == 1)
2007 return 0;
2008 /* wait until all FIFOs get ready */
2009 for (timeout = 5000; timeout; timeout--) {
2010 nwait = 0;
2011 snd_pcm_group_for_each_entry(s, substream) {
2012 if (s->pcm->card != substream->pcm->card)
2013 continue;
2014 azx_dev = get_azx_dev(s);
2015 if (!(azx_sd_readb(azx_dev, SD_STS) &
2016 SD_STS_FIFO_READY))
2017 nwait++;
2018 }
2019 if (!nwait)
2020 break;
2021 cpu_relax();
2022 }
2023 } else {
2024 /* wait until all RUN bits are cleared */
2025 for (timeout = 5000; timeout; timeout--) {
2026 nwait = 0;
2027 snd_pcm_group_for_each_entry(s, substream) {
2028 if (s->pcm->card != substream->pcm->card)
2029 continue;
2030 azx_dev = get_azx_dev(s);
2031 if (azx_sd_readb(azx_dev, SD_CTL) &
2032 SD_CTL_DMA_START)
2033 nwait++;
2034 }
2035 if (!nwait)
2036 break;
2037 cpu_relax();
2038 }
1da177e4 2039 }
850f0e52
TI		 2040 if (nsync > 1) {
2041 spin_lock(&chip->reg_lock);
2042 /* reset SYNC bits */
8b0bd226
TI		 2043 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2044 azx_writel(chip, OLD_SSYNC,
2045 azx_readl(chip, OLD_SSYNC) & ~sbits);
2046 else
2047 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
850f0e52
TI		 2048 spin_unlock(&chip->reg_lock);
2049 }
2050 return 0;
1da177e4
LT		 2051}
2052
0e153474
JC		 2053/* get the current DMA position with correction on VIA chips */
2054static unsigned int azx_via_get_position(struct azx *chip,
2055 struct azx_dev *azx_dev)
2056{
2057 unsigned int link_pos, mini_pos, bound_pos;
2058 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2059 unsigned int fifo_size;
2060
2061 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2062 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2063 /* Playback, no problem using link position */
2064 return link_pos;
2065 }
2066
2067 /* Capture */
2068 /* For new chipset,
2069 * use mod to get the DMA position just like old chipset
2070 */
2071 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2072 mod_dma_pos %= azx_dev->period_bytes;
2073
2074 /* azx_dev->fifo_size can't get FIFO size of in stream.
2075 * Get from base address + offset.
2076 */
2077 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2078
2079 if (azx_dev->insufficient) {
2080 /* Link position never gather than FIFO size */
2081 if (link_pos <= fifo_size)
2082 return 0;
2083
2084 azx_dev->insufficient = 0;
2085 }
2086
2087 if (link_pos <= fifo_size)
2088 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2089 else
2090 mini_pos = link_pos - fifo_size;
2091
2092 /* Find nearest previous boudary */
2093 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2094 mod_link_pos = link_pos % azx_dev->period_bytes;
2095 if (mod_link_pos >= fifo_size)
2096 bound_pos = link_pos - mod_link_pos;
2097 else if (mod_dma_pos >= mod_mini_pos)
2098 bound_pos = mini_pos - mod_mini_pos;
2099 else {
2100 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2101 if (bound_pos >= azx_dev->bufsize)
2102 bound_pos = 0;
2103 }
2104
2105 /* Calculate real DMA position we want */
2106 return bound_pos + mod_dma_pos;
2107}
2108
9ad593f6 2109static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2110 struct azx_dev *azx_dev,
2111 bool with_check)
1da177e4 2112{
1da177e4 2113 unsigned int pos;
4cb36310 2114 int stream = azx_dev->substream->stream;
1da177e4 2115
4cb36310
DH		 2116 switch (chip->position_fix[stream]) {
2117 case POS_FIX_LPIB:
2118 /* read LPIB */
2119 pos = azx_sd_readl(azx_dev, SD_LPIB);
2120 break;
2121 case POS_FIX_VIACOMBO:
0e153474 2122 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2123 break;
2124 default:
2125 /* use the position buffer */
2126 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2127 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2128 if (!pos || pos == (u32)-1) {
2129 printk(KERN_WARNING
2130 "hda-intel: Invalid position buffer, "
2131 "using LPIB read method instead.\n");
2132 chip->position_fix[stream] = POS_FIX_LPIB;
2133 pos = azx_sd_readl(azx_dev, SD_LPIB);
2134 } else
2135 chip->position_fix[stream] = POS_FIX_POSBUF;
2136 }
2137 break;
c74db86b 2138 }
4cb36310 2139
1da177e4
LT		 2140 if (pos >= azx_dev->bufsize)
2141 pos = 0;
9ad593f6
TI		 2142 return pos;
2143}
2144
2145static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2146{
2147 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2148 struct azx *chip = apcm->chip;
2149 struct azx_dev *azx_dev = get_azx_dev(substream);
2150 return bytes_to_frames(substream->runtime,
798cb7e8 2151 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2152}
2153
2154/*
2155 * Check whether the current DMA position is acceptable for updating
2156 * periods. Returns non-zero if it's OK.
2157 *
2158 * Many HD-audio controllers appear pretty inaccurate about
2159 * the update-IRQ timing. The IRQ is issued before actually the
2160 * data is processed. So, we need to process it afterwords in a
2161 * workqueue.
2162 */
2163static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2164{
e5463720 2165 u32 wallclk;
9ad593f6 2166 unsigned int pos;
beaffc39 2167 int stream;
9ad593f6 2168
f48f606d
JK		 2169 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2170 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2171 return -1; /* bogus (too early) interrupt */
fa00e046 2172
beaffc39 2173 stream = azx_dev->substream->stream;
798cb7e8 2174 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2175
d6d8bf54
TI		 2176 if (WARN_ONCE(!azx_dev->period_bytes,
2177 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2178 return -1; /* this shouldn't happen! */
edb39935 2179 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2180 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2181 /* NG - it's below the first next period boundary */
2182 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2183 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2184 return 1; /* OK, it's fine */
2185}
2186
2187/*
2188 * The work for pending PCM period updates.
2189 */
2190static void azx_irq_pending_work(struct work_struct *work)
2191{
2192 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2193 int i, pending, ok;
9ad593f6 2194
a6a950a8
TI		 2195 if (!chip->irq_pending_warned) {
2196 printk(KERN_WARNING
2197 "hda-intel: IRQ timing workaround is activated "
2198 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2199 chip->card->number);
2200 chip->irq_pending_warned = 1;
2201 }
2202
9ad593f6
TI		 2203 for (;;) {
2204 pending = 0;
2205 spin_lock_irq(&chip->reg_lock);
2206 for (i = 0; i < chip->num_streams; i++) {
2207 struct azx_dev *azx_dev = &chip->azx_dev[i];
2208 if (!azx_dev->irq_pending ||
2209 !azx_dev->substream ||
2210 !azx_dev->running)
2211 continue;
e5463720
JK		 2212 ok = azx_position_ok(chip, azx_dev);
2213 if (ok > 0) {
9ad593f6
TI		 2214 azx_dev->irq_pending = 0;
2215 spin_unlock(&chip->reg_lock);
2216 snd_pcm_period_elapsed(azx_dev->substream);
2217 spin_lock(&chip->reg_lock);
e5463720
JK		 2218 } else if (ok < 0) {
2219 pending = 0; /* too early */
9ad593f6
TI		 2220 } else
2221 pending++;
2222 }
2223 spin_unlock_irq(&chip->reg_lock);
2224 if (!pending)
2225 return;
08af495f 2226 msleep(1);
9ad593f6
TI		 2227 }
2228}
2229
2230/* clear irq_pending flags and assure no on-going workq */
2231static void azx_clear_irq_pending(struct azx *chip)
2232{
2233 int i;
2234
2235 spin_lock_irq(&chip->reg_lock);
2236 for (i = 0; i < chip->num_streams; i++)
2237 chip->azx_dev[i].irq_pending = 0;
2238 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2239}
2240
27fe48d9
TI		 2241#ifdef CONFIG_X86
2242static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2243 struct vm_area_struct *area)
2244{
2245 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2246 struct azx *chip = apcm->chip;
2247 if (!azx_snoop(chip))
2248 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2249 return snd_pcm_lib_default_mmap(substream, area);
2250}
2251#else
2252#define azx_pcm_mmap NULL
2253#endif
2254
a98f90fd 2255static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2256 .open = azx_pcm_open,
2257 .close = azx_pcm_close,
2258 .ioctl = snd_pcm_lib_ioctl,
2259 .hw_params = azx_pcm_hw_params,
2260 .hw_free = azx_pcm_hw_free,
2261 .prepare = azx_pcm_prepare,
2262 .trigger = azx_pcm_trigger,
2263 .pointer = azx_pcm_pointer,
27fe48d9 2264 .mmap = azx_pcm_mmap,
4ce107b9 2265 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2266};
2267
a98f90fd 2268static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2269{
176d5335
TI		 2270 struct azx_pcm *apcm = pcm->private_data;
2271 if (apcm) {
01b65bfb 2272 list_del(&apcm->list);
176d5335
TI		 2273 kfree(apcm);
2274 }
1da177e4
LT		 2275}
2276
acfa634f
TI		 2277#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2278
176d5335 2279static int
33fa35ed
TI		 2280azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2281 struct hda_pcm *cpcm)
1da177e4 2282{
33fa35ed 2283 struct azx *chip = bus->private_data;
a98f90fd 2284 struct snd_pcm *pcm;
1da177e4 2285 struct azx_pcm *apcm;
176d5335 2286 int pcm_dev = cpcm->device;
acfa634f 2287 unsigned int size;
176d5335 2288 int s, err;
1da177e4 2289
01b65bfb
TI		 2290 list_for_each_entry(apcm, &chip->pcm_list, list) {
2291 if (apcm->pcm->device == pcm_dev) {
2292 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2293 return -EBUSY;
2294 }
176d5335
TI		 2295 }
2296 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2297 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2298 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2299 &pcm);
2300 if (err < 0)
2301 return err;
18cb7109 2302 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2303 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2304 if (apcm == NULL)
2305 return -ENOMEM;
2306 apcm->chip = chip;
01b65bfb 2307 apcm->pcm = pcm;
1da177e4 2308 apcm->codec = codec;
1da177e4
LT		 2309 pcm->private_data = apcm;
2310 pcm->private_free = azx_pcm_free;
176d5335
TI		 2311 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2312 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2313 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2314 cpcm->pcm = pcm;
2315 for (s = 0; s < 2; s++) {
2316 apcm->hinfo[s] = &cpcm->stream[s];
2317 if (cpcm->stream[s].substreams)
2318 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2319 }
2320 /* buffer pre-allocation */
acfa634f
TI		 2321 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2322 if (size > MAX_PREALLOC_SIZE)
2323 size = MAX_PREALLOC_SIZE;
4ce107b9 2324 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2325 snd_dma_pci_data(chip->pci),
acfa634f 2326 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2327 return 0;
2328}
2329
2330/*
2331 * mixer creation - all stuff is implemented in hda module
2332 */
a98f90fd 2333static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2334{
2335 return snd_hda_build_controls(chip->bus);
2336}
2337
2338
2339/*
2340 * initialize SD streams
2341 */
a98f90fd 2342static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2343{
2344 int i;
2345
2346 /* initialize each stream (aka device)
d01ce99f
TI		 2347 * assign the starting bdl address to each stream (device)
2348 * and initialize
1da177e4 2349 */
07e4ca50 2350 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2351 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2352 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2353 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2354 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2355 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2356 azx_dev->sd_int_sta_mask = 1 << i;
2357 /* stream tag: must be non-zero and unique */
2358 azx_dev->index = i;
2359 azx_dev->stream_tag = i + 1;
2360 }
2361
2362 return 0;
2363}
2364
68e7fffc
TI		 2365static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2366{
437a5a46
TI		 2367 if (request_irq(chip->pci->irq, azx_interrupt,
2368 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2369 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2370 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2371 "disabling device\n", chip->pci->irq);
2372 if (do_disconnect)
2373 snd_card_disconnect(chip->card);
2374 return -1;
2375 }
2376 chip->irq = chip->pci->irq;
69e13418 2377 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2378 return 0;
2379}
2380
1da177e4 2381
cb53c626
TI		 2382static void azx_stop_chip(struct azx *chip)
2383{
95e99fda 2384 if (!chip->initialized)
cb53c626
TI		 2385 return;
2386
2387 /* disable interrupts */
2388 azx_int_disable(chip);
2389 azx_int_clear(chip);
2390
2391 /* disable CORB/RIRB */
2392 azx_free_cmd_io(chip);
2393
2394 /* disable position buffer */
2395 azx_writel(chip, DPLBASE, 0);
2396 azx_writel(chip, DPUBASE, 0);
2397
2398 chip->initialized = 0;
2399}
2400
2401#ifdef CONFIG_SND_HDA_POWER_SAVE
2402/* power-up/down the controller */
33fa35ed 2403static void azx_power_notify(struct hda_bus *bus)
cb53c626 2404{
33fa35ed 2405 struct azx *chip = bus->private_data;
cb53c626
TI		 2406 struct hda_codec *c;
2407 int power_on = 0;
2408
33fa35ed 2409 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 2410 if (c->power_on) {
2411 power_on = 1;
2412 break;
2413 }
2414 }
2415 if (power_on)
cd508fe5 2416 azx_init_chip(chip, 1);
0287d970
WF		 2417 else if (chip->running && power_save_controller &&
2418 !bus->power_keep_link_on)
cb53c626 2419 azx_stop_chip(chip);
cb53c626 2420}
65fcd41d
TI		 2421
2422static DEFINE_MUTEX(card_list_lock);
2423static LIST_HEAD(card_list);
2424
2425static void azx_add_card_list(struct azx *chip)
2426{
2427 mutex_lock(&card_list_lock);
2428 list_add(&chip->list, &card_list);
2429 mutex_unlock(&card_list_lock);
2430}
2431
2432static void azx_del_card_list(struct azx *chip)
2433{
2434 mutex_lock(&card_list_lock);
2435 list_del_init(&chip->list);
2436 mutex_unlock(&card_list_lock);
2437}
2438
2439/* trigger power-save check at writing parameter */
2440static int param_set_xint(const char *val, const struct kernel_param *kp)
2441{
2442 struct azx *chip;
2443 struct hda_codec *c;
2444 int prev = power_save;
2445 int ret = param_set_int(val, kp);
2446
2447 if (ret || prev == power_save)
2448 return ret;
2449
2450 mutex_lock(&card_list_lock);
2451 list_for_each_entry(chip, &card_list, list) {
2452 if (!chip->bus || chip->disabled)
2453 continue;
2454 list_for_each_entry(c, &chip->bus->codec_list, list)
2455 snd_hda_power_sync(c);
2456 }
2457 mutex_unlock(&card_list_lock);
2458 return 0;
2459}
2460#else
2461#define azx_add_card_list(chip) /* NOP */
2462#define azx_del_card_list(chip) /* NOP */
5c0b9bec
TI		 2463#endif /* CONFIG_SND_HDA_POWER_SAVE */
2464
7ccbde57 2465#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 2466/*
2467 * power management
2468 */
68cb2b55 2469static int azx_suspend(struct device *dev)
1da177e4 2470{
68cb2b55
TI		 2471 struct pci_dev *pci = to_pci_dev(dev);
2472 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2473 struct azx *chip = card->private_data;
01b65bfb 2474 struct azx_pcm *p;
1da177e4 2475
421a1252 2476 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2477 azx_clear_irq_pending(chip);
01b65bfb
TI		 2478 list_for_each_entry(p, &chip->pcm_list, list)
2479 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2480 if (chip->initialized)
8dd78330 2481 snd_hda_suspend(chip->bus);
cb53c626 2482 azx_stop_chip(chip);
30b35399 2483 if (chip->irq >= 0) {
43001c95 2484 free_irq(chip->irq, chip);
30b35399
TI		 2485 chip->irq = -1;
2486 }
68e7fffc 2487 if (chip->msi)
43001c95 2488 pci_disable_msi(chip->pci);
421a1252
TI		 2489 pci_disable_device(pci);
2490 pci_save_state(pci);
68cb2b55 2491 pci_set_power_state(pci, PCI_D3hot);
1da177e4
LT		 2492 return 0;
2493}
2494
68cb2b55 2495static int azx_resume(struct device *dev)
1da177e4 2496{
68cb2b55
TI		 2497 struct pci_dev *pci = to_pci_dev(dev);
2498 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2499 struct azx *chip = card->private_data;
1da177e4 2500
d14a7e0b
TI		 2501 pci_set_power_state(pci, PCI_D0);
2502 pci_restore_state(pci);
30b35399
TI		 2503 if (pci_enable_device(pci) < 0) {
2504 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2505 "disabling device\n");
2506 snd_card_disconnect(card);
2507 return -EIO;
2508 }
2509 pci_set_master(pci);
68e7fffc
TI		 2510 if (chip->msi)
2511 if (pci_enable_msi(pci) < 0)
2512 chip->msi = 0;
2513 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2514 return -EIO;
cb53c626 2515 azx_init_pci(chip);
d804ad92 2516
7f30830b 2517 azx_init_chip(chip, 1);
d804ad92 2518
1da177e4 2519 snd_hda_resume(chip->bus);
421a1252 2520 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2521 return 0;
2522}
68cb2b55
TI		 2523static SIMPLE_DEV_PM_OPS(azx_pm, azx_suspend, azx_resume);
2524#define AZX_PM_OPS &azx_pm
2525#else
68cb2b55 2526#define AZX_PM_OPS NULL
7ccbde57 2527#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1da177e4
LT		 2528
2529
0cbf0098
TI		 2530/*
2531 * reboot notifier for hang-up problem at power-down
2532 */
2533static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2534{
2535 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2536 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2537 azx_stop_chip(chip);
2538 return NOTIFY_OK;
2539}
2540
2541static void azx_notifier_register(struct azx *chip)
2542{
2543 chip->reboot_notifier.notifier_call = azx_halt;
2544 register_reboot_notifier(&chip->reboot_notifier);
2545}
2546
2547static void azx_notifier_unregister(struct azx *chip)
2548{
2549 if (chip->reboot_notifier.notifier_call)
2550 unregister_reboot_notifier(&chip->reboot_notifier);
2551}
2552
a82d51ed
TI		 2553static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2554static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2555
8393ec4a 2556#ifdef SUPPORT_VGA_SWITCHEROO
a82d51ed
TI		 2557static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2558
a82d51ed
TI		 2559static void azx_vs_set_state(struct pci_dev *pci,
2560 enum vga_switcheroo_state state)
2561{
2562 struct snd_card *card = pci_get_drvdata(pci);
2563 struct azx *chip = card->private_data;
2564 bool disabled;
2565
2566 if (chip->init_failed)
2567 return;
2568
2569 disabled = (state == VGA_SWITCHEROO_OFF);
2570 if (chip->disabled == disabled)
2571 return;
2572
2573 if (!chip->bus) {
2574 chip->disabled = disabled;
2575 if (!disabled) {
2576 snd_printk(KERN_INFO SFX
2577 "%s: Start delayed initialization\n",
2578 pci_name(chip->pci));
2579 if (azx_first_init(chip) < 0 ||
2580 azx_probe_continue(chip) < 0) {
2581 snd_printk(KERN_ERR SFX
2582 "%s: initialization error\n",
2583 pci_name(chip->pci));
2584 chip->init_failed = true;
2585 }
2586 }
2587 } else {
2588 snd_printk(KERN_INFO SFX
2589 "%s %s via VGA-switcheroo\n",
2590 disabled ? "Disabling" : "Enabling",
2591 pci_name(chip->pci));
2592 if (disabled) {
68cb2b55 2593 azx_suspend(&pci->dev);
a82d51ed
TI		 2594 chip->disabled = true;
2595 snd_hda_lock_devices(chip->bus);
2596 } else {
2597 snd_hda_unlock_devices(chip->bus);
2598 chip->disabled = false;
68cb2b55 2599 azx_resume(&pci->dev);
a82d51ed
TI		 2600 }
2601 }
2602}
2603
2604static bool azx_vs_can_switch(struct pci_dev *pci)
2605{
2606 struct snd_card *card = pci_get_drvdata(pci);
2607 struct azx *chip = card->private_data;
2608
2609 if (chip->init_failed)
2610 return false;
2611 if (chip->disabled || !chip->bus)
2612 return true;
2613 if (snd_hda_lock_devices(chip->bus))
2614 return false;
2615 snd_hda_unlock_devices(chip->bus);
2616 return true;
2617}
2618
2619static void __devinit init_vga_switcheroo(struct azx *chip)
2620{
2621 struct pci_dev *p = get_bound_vga(chip->pci);
2622 if (p) {
2623 snd_printk(KERN_INFO SFX
2624 "%s: Handle VGA-switcheroo audio client\n",
2625 pci_name(chip->pci));
2626 chip->use_vga_switcheroo = 1;
2627 pci_dev_put(p);
2628 }
2629}
2630
2631static const struct vga_switcheroo_client_ops azx_vs_ops = {
2632 .set_gpu_state = azx_vs_set_state,
2633 .can_switch = azx_vs_can_switch,
2634};
2635
2636static int __devinit register_vga_switcheroo(struct azx *chip)
2637{
2638 if (!chip->use_vga_switcheroo)
2639 return 0;
2640 /* FIXME: currently only handling DIS controller
2641 * is there any machine with two switchable HDMI audio controllers?
2642 */
2643 return vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2644 VGA_SWITCHEROO_DIS,
2645 chip->bus != NULL);
2646}
2647#else
2648#define init_vga_switcheroo(chip) /* NOP */
2649#define register_vga_switcheroo(chip) 0
8393ec4a 2650#define check_hdmi_disabled(pci) false
a82d51ed
TI		 2651#endif /* SUPPORT_VGA_SWITCHER */
2652
1da177e4
LT		 2653/*
2654 * destructor
2655 */
a98f90fd 2656static int azx_free(struct azx *chip)
1da177e4 2657{
4ce107b9
TI		 2658 int i;
2659
65fcd41d
TI		 2660 azx_del_card_list(chip);
2661
0cbf0098
TI		 2662 azx_notifier_unregister(chip);
2663
a82d51ed
TI		 2664 if (use_vga_switcheroo(chip)) {
2665 if (chip->disabled && chip->bus)
2666 snd_hda_unlock_devices(chip->bus);
2667 vga_switcheroo_unregister_client(chip->pci);
2668 }
2669
ce43fbae 2670 if (chip->initialized) {
9ad593f6 2671 azx_clear_irq_pending(chip);
07e4ca50 2672 for (i = 0; i < chip->num_streams; i++)
1da177e4 2673 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2674 azx_stop_chip(chip);
1da177e4
LT		 2675 }
2676
f000fd80 2677 if (chip->irq >= 0)
1da177e4 2678 free_irq(chip->irq, (void*)chip);
68e7fffc 2679 if (chip->msi)
30b35399 2680 pci_disable_msi(chip->pci);
f079c25a
TI		 2681 if (chip->remap_addr)
2682 iounmap(chip->remap_addr);
1da177e4 2683
4ce107b9
TI		 2684 if (chip->azx_dev) {
2685 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 2686 if (chip->azx_dev[i].bdl.area) {
2687 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 2688 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 2689 }
4ce107b9 2690 }
27fe48d9
TI		 2691 if (chip->rb.area) {
2692 mark_pages_wc(chip, &chip->rb, false);
1da177e4 2693 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 2694 }
2695 if (chip->posbuf.area) {
2696 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 2697 snd_dma_free_pages(&chip->posbuf);
27fe48d9 2698 }
a82d51ed
TI		 2699 if (chip->region_requested)
2700 pci_release_regions(chip->pci);
1da177e4 2701 pci_disable_device(chip->pci);
07e4ca50 2702 kfree(chip->azx_dev);
4918cdab
TI		 2703#ifdef CONFIG_SND_HDA_PATCH_LOADER
2704 if (chip->fw)
2705 release_firmware(chip->fw);
2706#endif
1da177e4
LT		 2707 kfree(chip);
2708
2709 return 0;
2710}
2711
a98f90fd 2712static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2713{
2714 return azx_free(device->device_data);
2715}
2716
8393ec4a 2717#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 2718/*
2719 * Check of disabled HDMI controller by vga-switcheroo
2720 */
2721static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2722{
2723 struct pci_dev *p;
2724
2725 /* check only discrete GPU */
2726 switch (pci->vendor) {
2727 case PCI_VENDOR_ID_ATI:
2728 case PCI_VENDOR_ID_AMD:
2729 case PCI_VENDOR_ID_NVIDIA:
2730 if (pci->devfn == 1) {
2731 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2732 pci->bus->number, 0);
2733 if (p) {
2734 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2735 return p;
2736 pci_dev_put(p);
2737 }
2738 }
2739 break;
2740 }
2741 return NULL;
2742}
2743
2744static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2745{
2746 bool vga_inactive = false;
2747 struct pci_dev *p = get_bound_vga(pci);
2748
2749 if (p) {
12b78a7f 2750 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 2751 vga_inactive = true;
2752 pci_dev_put(p);
2753 }
2754 return vga_inactive;
2755}
8393ec4a 2756#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 2757
3372a153
TI		 2758/*
2759 * white/black-listing for position_fix
2760 */
623ec047 2761static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2762 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2763 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2764 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2765 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 2766 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 2767 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 2768 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 2769 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 2770 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 2771 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2772 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 2773 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 2774 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 2775 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 2776 {}
2777};
2778
2779static int __devinit check_position_fix(struct azx *chip, int fix)
2780{
2781 const struct snd_pci_quirk *q;
2782
c673ba1c
TI		 2783 switch (fix) {
2784 case POS_FIX_LPIB:
2785 case POS_FIX_POSBUF:
4cb36310 2786 case POS_FIX_VIACOMBO:
a6f2fd55 2787 case POS_FIX_COMBO:
c673ba1c
TI		 2788 return fix;
2789 }
2790
c673ba1c
TI		 2791 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2792 if (q) {
2793 printk(KERN_INFO
2794 "hda_intel: position_fix set to %d "
2795 "for device %04x:%04x\n",
2796 q->value, q->subvendor, q->subdevice);
2797 return q->value;
3372a153 2798 }
bdd9ef24
DH		 2799
2800 /* Check VIA/ATI HD Audio Controller exist */
9477c58e
TI		 2801 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2802 snd_printd(SFX "Using VIACOMBO position fix\n");
bdd9ef24 2803 return POS_FIX_VIACOMBO;
9477c58e
TI		 2804 }
2805 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2806 snd_printd(SFX "Using LPIB position fix\n");
50e3bbf9 2807 return POS_FIX_LPIB;
bdd9ef24 2808 }
c20c5a84
SH		 2809 if (chip->driver_caps & AZX_DCAPS_POSFIX_COMBO) {
2810 snd_printd(SFX "Using COMBO position fix\n");
2811 return POS_FIX_COMBO;
2812 }
c673ba1c 2813 return POS_FIX_AUTO;
3372a153
TI		 2814}
2815
669ba27a
TI		 2816/*
2817 * black-lists for probe_mask
2818 */
2819static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2820 /* Thinkpad often breaks the controller communication when accessing
2821 * to the non-working (or non-existing) modem codec slot.
2822 */
2823 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2824 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2825 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2826 /* broken BIOS */
2827 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2828 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2829 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2830 /* forced codec slots */
93574844 2831 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2832 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 2833 /* WinFast VP200 H (Teradici) user reported broken communication */
2834 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 2835 {}
2836};
2837
f1eaaeec
TI		 2838#define AZX_FORCE_CODEC_MASK 0x100
2839
5aba4f8e 2840static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2841{
2842 const struct snd_pci_quirk *q;
2843
f1eaaeec
TI		 2844 chip->codec_probe_mask = probe_mask[dev];
2845 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2846 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2847 if (q) {
2848 printk(KERN_INFO
2849 "hda_intel: probe_mask set to 0x%x "
2850 "for device %04x:%04x\n",
2851 q->value, q->subvendor, q->subdevice);
f1eaaeec 2852 chip->codec_probe_mask = q->value;
669ba27a
TI		 2853 }
2854 }
f1eaaeec
TI		 2855
2856 /* check forced option */
2857 if (chip->codec_probe_mask != -1 &&
2858 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2859 chip->codec_mask = chip->codec_probe_mask & 0xff;
2860 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2861 chip->codec_mask);
2862 }
669ba27a
TI		 2863}
2864
4d8e22e0 2865/*
71623855 2866 * white/black-list for enable_msi
4d8e22e0 2867 */
71623855 2868static struct snd_pci_quirk msi_black_list[] __devinitdata = {
9dc8398b 2869 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 2870 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 2871 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 2872 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 2873 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 2874 {}
2875};
2876
2877static void __devinit check_msi(struct azx *chip)
2878{
2879 const struct snd_pci_quirk *q;
2880
71623855
TI		 2881 if (enable_msi >= 0) {
2882 chip->msi = !!enable_msi;
4d8e22e0 2883 return;
71623855
TI		 2884 }
2885 chip->msi = 1; /* enable MSI as default */
2886 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 2887 if (q) {
2888 printk(KERN_INFO
2889 "hda_intel: msi for device %04x:%04x set to %d\n",
2890 q->subvendor, q->subdevice, q->value);
2891 chip->msi = q->value;
80c43ed7
TI		 2892 return;
2893 }
2894
2895 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 2896 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2897 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 2898 chip->msi = 0;
4d8e22e0
TI		 2899 }
2900}
2901
a1585d76
TI		 2902/* check the snoop mode availability */
2903static void __devinit azx_check_snoop_available(struct azx *chip)
2904{
2905 bool snoop = chip->snoop;
2906
2907 switch (chip->driver_type) {
2908 case AZX_DRIVER_VIA:
2909 /* force to non-snoop mode for a new VIA controller
2910 * when BIOS is set
2911 */
2912 if (snoop) {
2913 u8 val;
2914 pci_read_config_byte(chip->pci, 0x42, &val);
2915 if (!(val & 0x80) && chip->pci->revision == 0x30)
2916 snoop = false;
2917 }
2918 break;
2919 case AZX_DRIVER_ATIHDMI_NS:
2920 /* new ATI HDMI requires non-snoop */
2921 snoop = false;
2922 break;
2923 }
2924
2925 if (snoop != chip->snoop) {
2926 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2927 snoop ? "snoop" : "non-snoop");
2928 chip->snoop = snoop;
2929 }
2930}
669ba27a 2931
1da177e4
LT		 2932/*
2933 * constructor
2934 */
a98f90fd 2935static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
9477c58e 2936 int dev, unsigned int driver_caps,
a98f90fd 2937 struct azx **rchip)
1da177e4 2938{
a98f90fd 2939 static struct snd_device_ops ops = {
1da177e4
LT		 2940 .dev_free = azx_dev_free,
2941 };
a82d51ed
TI		 2942 struct azx *chip;
2943 int err;
1da177e4
LT		 2944
2945 *rchip = NULL;
bcd72003 2946
927fc866
PM		 2947 err = pci_enable_device(pci);
2948 if (err < 0)
1da177e4
LT		 2949 return err;
2950
e560d8d8 2951 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2952 if (!chip) {
1da177e4
LT		 2953 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2954 pci_disable_device(pci);
2955 return -ENOMEM;
2956 }
2957
2958 spin_lock_init(&chip->reg_lock);
62932df8 2959 mutex_init(&chip->open_mutex);
1da177e4
LT		 2960 chip->card = card;
2961 chip->pci = pci;
2962 chip->irq = -1;
9477c58e
TI		 2963 chip->driver_caps = driver_caps;
2964 chip->driver_type = driver_caps & 0xff;
4d8e22e0 2965 check_msi(chip);
555e219f 2966 chip->dev_index = dev;
9ad593f6 2967 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 2968 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 2969 INIT_LIST_HEAD(&chip->list);
a82d51ed 2970 init_vga_switcheroo(chip);
1da177e4 2971
beaffc39
SG		 2972 chip->position_fix[0] = chip->position_fix[1] =
2973 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 2974 /* combo mode uses LPIB for playback */
2975 if (chip->position_fix[0] == POS_FIX_COMBO) {
2976 chip->position_fix[0] = POS_FIX_LPIB;
2977 chip->position_fix[1] = POS_FIX_AUTO;
2978 }
2979
5aba4f8e 2980 check_probe_mask(chip, dev);
3372a153 2981
27346166 2982 chip->single_cmd = single_cmd;
27fe48d9 2983 chip->snoop = hda_snoop;
a1585d76 2984 azx_check_snoop_available(chip);
c74db86b 2985
5c0d7bc1
TI		 2986 if (bdl_pos_adj[dev] < 0) {
2987 switch (chip->driver_type) {
0c6341ac 2988 case AZX_DRIVER_ICH:
32679f95 2989 case AZX_DRIVER_PCH:
0c6341ac 2990 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2991 break;
2992 default:
0c6341ac 2993 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2994 break;
2995 }
2996 }
2997
a82d51ed
TI		 2998 if (check_hdmi_disabled(pci)) {
2999 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
3000 pci_name(pci));
3001 if (use_vga_switcheroo(chip)) {
3002 snd_printk(KERN_INFO SFX "Delaying initialization\n");
3003 chip->disabled = true;
3004 goto ok;
3005 }
3006 kfree(chip);
3007 pci_disable_device(pci);
3008 return -ENXIO;
3009 }
3010
3011 err = azx_first_init(chip);
3012 if (err < 0) {
3013 azx_free(chip);
3014 return err;
3015 }
3016
3017 ok:
3018 err = register_vga_switcheroo(chip);
3019 if (err < 0) {
3020 snd_printk(KERN_ERR SFX
3021 "Error registering VGA-switcheroo client\n");
3022 azx_free(chip);
3023 return err;
3024 }
3025
3026 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3027 if (err < 0) {
3028 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3029 azx_free(chip);
3030 return err;
3031 }
3032
3033 *rchip = chip;
3034 return 0;
3035}
3036
3037static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3038{
3039 int dev = chip->dev_index;
3040 struct pci_dev *pci = chip->pci;
3041 struct snd_card *card = chip->card;
3042 int i, err;
3043 unsigned short gcap;
3044
07e4ca50
TI		 3045#if BITS_PER_LONG != 64
3046 /* Fix up base address on ULI M5461 */
3047 if (chip->driver_type == AZX_DRIVER_ULI) {
3048 u16 tmp3;
3049 pci_read_config_word(pci, 0x40, &tmp3);
3050 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3051 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3052 }
3053#endif
3054
927fc866 3055 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 3056 if (err < 0)
1da177e4 3057 return err;
a82d51ed 3058 chip->region_requested = 1;
1da177e4 3059
927fc866 3060 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 3061 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 3062 if (chip->remap_addr == NULL) {
3063 snd_printk(KERN_ERR SFX "ioremap error\n");
a82d51ed 3064 return -ENXIO;
1da177e4
LT		 3065 }
3066
68e7fffc
TI		 3067 if (chip->msi)
3068 if (pci_enable_msi(pci) < 0)
3069 chip->msi = 0;
7376d013 3070
a82d51ed
TI		 3071 if (azx_acquire_irq(chip, 0) < 0)
3072 return -EBUSY;
1da177e4
LT		 3073
3074 pci_set_master(pci);
3075 synchronize_irq(chip->irq);
3076
bcd72003 3077 gcap = azx_readw(chip, GCAP);
4abc1cc2 3078 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 3079
dc4c2e6b 3080 /* disable SB600 64bit support for safety */
9477c58e 3081 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3082 struct pci_dev *p_smbus;
3083 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3084 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3085 NULL);
3086 if (p_smbus) {
3087 if (p_smbus->revision < 0x30)
3088 gcap &= ~ICH6_GCAP_64OK;
3089 pci_dev_put(p_smbus);
3090 }
3091 }
09240cf4 3092
9477c58e
TI		 3093 /* disable 64bit DMA address on some devices */
3094 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3095 snd_printd(SFX "Disabling 64bit DMA\n");
396087ea 3096 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3097 }
396087ea 3098
2ae66c26 3099 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3100 if (align_buffer_size >= 0)
3101 chip->align_buffer_size = !!align_buffer_size;
3102 else {
3103 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3104 chip->align_buffer_size = 0;
3105 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3106 chip->align_buffer_size = 1;
3107 else
3108 chip->align_buffer_size = 1;
3109 }
2ae66c26 3110
cf7aaca8 3111 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3112 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3113 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3114 else {
e930438c
YH		 3115 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3116 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3117 }
cf7aaca8 3118
8b6ed8e7
TI		 3119 /* read number of streams from GCAP register instead of using
3120 * hardcoded value
3121 */
3122 chip->capture_streams = (gcap >> 8) & 0x0f;
3123 chip->playback_streams = (gcap >> 12) & 0x0f;
3124 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3125 /* gcap didn't give any info, switching to old method */
3126
3127 switch (chip->driver_type) {
3128 case AZX_DRIVER_ULI:
3129 chip->playback_streams = ULI_NUM_PLAYBACK;
3130 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3131 break;
3132 case AZX_DRIVER_ATIHDMI:
1815b34a 3133 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3134 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3135 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3136 break;
c4da29ca 3137 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3138 default:
3139 chip->playback_streams = ICH6_NUM_PLAYBACK;
3140 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3141 break;
3142 }
07e4ca50 3143 }
8b6ed8e7
TI		 3144 chip->capture_index_offset = 0;
3145 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3146 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3147 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3148 GFP_KERNEL);
927fc866 3149 if (!chip->azx_dev) {
4abc1cc2 3150 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
a82d51ed 3151 return -ENOMEM;
07e4ca50
TI		 3152 }
3153
4ce107b9
TI		 3154 for (i = 0; i < chip->num_streams; i++) {
3155 /* allocate memory for the BDL for each stream */
3156 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3157 snd_dma_pci_data(chip->pci),
3158 BDL_SIZE, &chip->azx_dev[i].bdl);
3159 if (err < 0) {
3160 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
a82d51ed 3161 return -ENOMEM;
4ce107b9 3162 }
27fe48d9 3163 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3164 }
0be3b5d3 3165 /* allocate memory for the position buffer */
d01ce99f
TI		 3166 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3167 snd_dma_pci_data(chip->pci),
3168 chip->num_streams * 8, &chip->posbuf);
3169 if (err < 0) {
0be3b5d3 3170 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
a82d51ed 3171 return -ENOMEM;
1da177e4 3172 }
27fe48d9 3173 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3174 /* allocate CORB/RIRB */
81740861
TI		 3175 err = azx_alloc_cmd_io(chip);
3176 if (err < 0)
a82d51ed 3177 return err;
1da177e4
LT		 3178
3179 /* initialize streams */
3180 azx_init_stream(chip);
3181
3182 /* initialize chip */
cb53c626 3183 azx_init_pci(chip);
10e77dda 3184 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3185
3186 /* codec detection */
927fc866 3187 if (!chip->codec_mask) {
1da177e4 3188 snd_printk(KERN_ERR SFX "no codecs found!\n");
a82d51ed 3189 return -ENODEV;
1da177e4
LT		 3190 }
3191
07e4ca50 3192 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3193 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3194 sizeof(card->shortname));
3195 snprintf(card->longname, sizeof(card->longname),
3196 "%s at 0x%lx irq %i",
3197 card->shortname, chip->addr, chip->irq);
07e4ca50 3198
1da177e4 3199 return 0;
1da177e4
LT		 3200}
3201
cb53c626
TI		 3202static void power_down_all_codecs(struct azx *chip)
3203{
3204#ifdef CONFIG_SND_HDA_POWER_SAVE
3205 /* The codecs were powered up in snd_hda_codec_new().
3206 * Now all initialization done, so turn them down if possible
3207 */
3208 struct hda_codec *codec;
3209 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3210 snd_hda_power_down(codec);
3211 }
3212#endif
3213}
3214
97c6a3d1 3215#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 3216/* callback from request_firmware_nowait() */
3217static void azx_firmware_cb(const struct firmware *fw, void *context)
3218{
3219 struct snd_card *card = context;
3220 struct azx *chip = card->private_data;
3221 struct pci_dev *pci = chip->pci;
3222
3223 if (!fw) {
3224 snd_printk(KERN_ERR SFX "Cannot load firmware, aborting\n");
3225 goto error;
3226 }
3227
3228 chip->fw = fw;
3229 if (!chip->disabled) {
3230 /* continue probing */
3231 if (azx_probe_continue(chip))
3232 goto error;
3233 }
3234 return; /* OK */
3235
3236 error:
3237 snd_card_free(card);
3238 pci_set_drvdata(pci, NULL);
3239}
97c6a3d1 3240#endif
5cb543db 3241
d01ce99f
TI		 3242static int __devinit azx_probe(struct pci_dev *pci,
3243 const struct pci_device_id *pci_id)
1da177e4 3244{
5aba4f8e 3245 static int dev;
a98f90fd
TI		 3246 struct snd_card *card;
3247 struct azx *chip;
5cb543db 3248 bool probe_now;
927fc866 3249 int err;
1da177e4 3250
5aba4f8e
TI		 3251 if (dev >= SNDRV_CARDS)
3252 return -ENODEV;
3253 if (!enable[dev]) {
3254 dev++;
3255 return -ENOENT;
3256 }
3257
e58de7ba
TI		 3258 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3259 if (err < 0) {
1da177e4 3260 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 3261 return err;
1da177e4
LT		 3262 }
3263
4ea6fbc8
TI		 3264 snd_card_set_dev(card, &pci->dev);
3265
5aba4f8e 3266 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3267 if (err < 0)
3268 goto out_free;
421a1252 3269 card->private_data = chip;
5cb543db 3270 probe_now = !chip->disabled;
1da177e4 3271
4918cdab
TI		 3272#ifdef CONFIG_SND_HDA_PATCH_LOADER
3273 if (patch[dev] && *patch[dev]) {
3274 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3275 patch[dev]);
5cb543db
TI		 3276 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3277 &pci->dev, GFP_KERNEL, card,
3278 azx_firmware_cb);
4918cdab
TI		 3279 if (err < 0)
3280 goto out_free;
5cb543db 3281 probe_now = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 3282 }
3283#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3284
5cb543db 3285 if (probe_now) {
a82d51ed
TI		 3286 err = azx_probe_continue(chip);
3287 if (err < 0)
3288 goto out_free;
3289 }
3290
3291 pci_set_drvdata(pci, card);
3292
3293 dev++;
3294 return 0;
3295
3296out_free:
3297 snd_card_free(card);
3298 return err;
3299}
3300
3301static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3302{
3303 int dev = chip->dev_index;
3304 int err;
3305
2dca0bba
JK		 3306#ifdef CONFIG_SND_HDA_INPUT_BEEP
3307 chip->beep_mode = beep_mode[dev];
3308#endif
3309
1da177e4 3310 /* create codec instances */
a1e21c90 3311 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3312 if (err < 0)
3313 goto out_free;
4ea6fbc8 3314#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 3315 if (chip->fw) {
3316 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3317 chip->fw->data);
4ea6fbc8
TI		 3318 if (err < 0)
3319 goto out_free;
4918cdab
TI		 3320 release_firmware(chip->fw); /* no longer needed */
3321 chip->fw = NULL;
4ea6fbc8
TI		 3322 }
3323#endif
10e77dda 3324 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3325 err = azx_codec_configure(chip);
3326 if (err < 0)
3327 goto out_free;
3328 }
1da177e4
LT		 3329
3330 /* create PCM streams */
176d5335 3331 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3332 if (err < 0)
3333 goto out_free;
1da177e4
LT		 3334
3335 /* create mixer controls */
d01ce99f 3336 err = azx_mixer_create(chip);
41dda0fd
WF		 3337 if (err < 0)
3338 goto out_free;
1da177e4 3339
a82d51ed 3340 err = snd_card_register(chip->card);
41dda0fd
WF		 3341 if (err < 0)
3342 goto out_free;
1da177e4 3343
cb53c626
TI		 3344 chip->running = 1;
3345 power_down_all_codecs(chip);
0cbf0098 3346 azx_notifier_register(chip);
65fcd41d 3347 azx_add_card_list(chip);
1da177e4 3348
9121947d
TI		 3349 return 0;
3350
41dda0fd 3351out_free:
a82d51ed 3352 chip->init_failed = 1;
41dda0fd 3353 return err;
1da177e4
LT		 3354}
3355
3356static void __devexit azx_remove(struct pci_dev *pci)
3357{
9121947d
TI		 3358 struct snd_card *card = pci_get_drvdata(pci);
3359 if (card)
3360 snd_card_free(card);
1da177e4
LT		 3361 pci_set_drvdata(pci, NULL);
3362}
3363
3364/* PCI IDs */
cebe41d4 3365static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3366 /* CPT */
9477c58e 3367 { PCI_DEVICE(0x8086, 0x1c20),
2ae66c26 3368 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
c20c5a84 3369 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
cea310e8 3370 /* PBG */
9477c58e 3371 { PCI_DEVICE(0x8086, 0x1d20),
2ae66c26
PLB		 3372 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3373 AZX_DCAPS_BUFSIZE},
d2edeb7c 3374 /* Panther Point */
9477c58e 3375 { PCI_DEVICE(0x8086, 0x1e20),
2ae66c26 3376 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
c20c5a84 3377 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
8bc039a1
SH		 3378 /* Lynx Point */
3379 { PCI_DEVICE(0x8086, 0x8c20),
3380 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
c20c5a84 3381 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
144dad99
JR		 3382 /* Lynx Point-LP */
3383 { PCI_DEVICE(0x8086, 0x9c20),
3384 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3385 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3386 /* Lynx Point-LP */
3387 { PCI_DEVICE(0x8086, 0x9c21),
3388 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3389 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
e926f2c8
WX		 3390 /* Haswell */
3391 { PCI_DEVICE(0x8086, 0x0c0c),
bdbe34de 3392 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
e926f2c8 3393 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
87218e9c 3394 /* SCH */
9477c58e 3395 { PCI_DEVICE(0x8086, 0x811b),
2ae66c26 3396 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
645e9035 3397 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
09904b95
LP		 3398 { PCI_DEVICE(0x8086, 0x080a),
3399 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
716e5db4 3400 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
645e9035 3401 /* ICH */
8b0bd226 3402 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 3403 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3404 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 3405 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 3406 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3407 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 3408 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 3409 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3410 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 3411 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 3412 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3413 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 3414 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 3415 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3416 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3417 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 3418 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3419 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3420 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 3421 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3422 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 3423 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 3424 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3425 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 3426 /* Generic Intel */
3427 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3428 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3429 .class_mask = 0xffffff,
2ae66c26 3430 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 3431 /* ATI SB 450/600/700/800/900 */
3432 { PCI_DEVICE(0x1002, 0x437b),
3433 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3434 { PCI_DEVICE(0x1002, 0x4383),
3435 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3436 /* AMD Hudson */
3437 { PCI_DEVICE(0x1022, 0x780d),
3438 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 3439 /* ATI HDMI */
9477c58e
TI		 3440 { PCI_DEVICE(0x1002, 0x793b),
3441 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3442 { PCI_DEVICE(0x1002, 0x7919),
3443 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3444 { PCI_DEVICE(0x1002, 0x960f),
3445 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3446 { PCI_DEVICE(0x1002, 0x970f),
3447 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3448 { PCI_DEVICE(0x1002, 0xaa00),
3449 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3450 { PCI_DEVICE(0x1002, 0xaa08),
3451 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3452 { PCI_DEVICE(0x1002, 0xaa10),
3453 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3454 { PCI_DEVICE(0x1002, 0xaa18),
3455 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3456 { PCI_DEVICE(0x1002, 0xaa20),
3457 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3458 { PCI_DEVICE(0x1002, 0xaa28),
3459 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3460 { PCI_DEVICE(0x1002, 0xaa30),
3461 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3462 { PCI_DEVICE(0x1002, 0xaa38),
3463 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3464 { PCI_DEVICE(0x1002, 0xaa40),
3465 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3466 { PCI_DEVICE(0x1002, 0xaa48),
3467 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 3468 { PCI_DEVICE(0x1002, 0x9902),
3469 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3470 { PCI_DEVICE(0x1002, 0xaaa0),
3471 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3472 { PCI_DEVICE(0x1002, 0xaaa8),
3473 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3474 { PCI_DEVICE(0x1002, 0xaab0),
3475 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 3476 /* VIA VT8251/VT8237A */
9477c58e
TI		 3477 { PCI_DEVICE(0x1106, 0x3288),
3478 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 3479 /* VIA GFX VT7122/VX900 */
3480 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3481 /* VIA GFX VT6122/VX11 */
3482 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 3483 /* SIS966 */
3484 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3485 /* ULI M5461 */
3486 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3487 /* NVIDIA MCP */
0c2fd1bf
TI		 3488 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3489 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3490 .class_mask = 0xffffff,
9477c58e 3491 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 3492 /* Teradici */
9477c58e
TI		 3493 { PCI_DEVICE(0x6549, 0x1200),
3494 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 3495 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 3496 /* CTHDA chips */
3497 { PCI_DEVICE(0x1102, 0x0010),
3498 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3499 { PCI_DEVICE(0x1102, 0x0012),
3500 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
313f6e2d
TI		 3501#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3502 /* the following entry conflicts with snd-ctxfi driver,
3503 * as ctxfi driver mutates from HD-audio to native mode with
3504 * a special command sequence.
3505 */
4e01f54b
TI		 3506 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3507 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3508 .class_mask = 0xffffff,
9477c58e 3509 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3510 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 3511#else
3512 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 3513 { PCI_DEVICE(0x1102, 0x0009),
3514 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3515 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 3516#endif
e35d4b11
OS		 3517 /* Vortex86MX */
3518 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 3519 /* VMware HDAudio */
3520 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 3521 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 3522 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3523 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3524 .class_mask = 0xffffff,
9477c58e 3525 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 3526 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3527 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3528 .class_mask = 0xffffff,
9477c58e 3529 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 3530 { 0, }
3531};
3532MODULE_DEVICE_TABLE(pci, azx_ids);
3533
3534/* pci_driver definition */
e9f66d9b 3535static struct pci_driver azx_driver = {
3733e424 3536 .name = KBUILD_MODNAME,
1da177e4
LT		 3537 .id_table = azx_ids,
3538 .probe = azx_probe,
3539 .remove = __devexit_p(azx_remove),
68cb2b55
TI		 3540 .driver = {
3541 .pm = AZX_PM_OPS,
3542 },
1da177e4
LT		 3543};
3544
e9f66d9b 3545module_pci_driver(azx_driver);
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