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ALSA: hda - Add In-driver connection info
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4
LT		 64#include "hda_codec.h"
65
66
5aba4f8e
TI		 67static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
68static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 69static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 70static char *model[SNDRV_CARDS];
1dac6695 71static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 72static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 73static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 74static int probe_only[SNDRV_CARDS];
26a6cb6c 75static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 76static bool single_cmd;
71623855 77static int enable_msi = -1;
4ea6fbc8
TI		 78#ifdef CONFIG_SND_HDA_PATCH_LOADER
79static char *patch[SNDRV_CARDS];
80#endif
2dca0bba 81#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 82static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 83 CONFIG_SND_HDA_INPUT_BEEP_MODE};
84#endif
1da177e4 85
5aba4f8e 86module_param_array(index, int, NULL, 0444);
1da177e4 87MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 88module_param_array(id, charp, NULL, 0444);
1da177e4 89MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 90module_param_array(enable, bool, NULL, 0444);
91MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
92module_param_array(model, charp, NULL, 0444);
1da177e4 93MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 94module_param_array(position_fix, int, NULL, 0444);
4cb36310 95MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 96 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 97module_param_array(bdl_pos_adj, int, NULL, 0644);
98MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 99module_param_array(probe_mask, int, NULL, 0444);
606ad75f 100MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 101module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 102MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 103module_param_array(jackpoll_ms, int, NULL, 0444);
104MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 105module_param(single_cmd, bool, 0444);
d01ce99f
TI		 106MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
107 "(for debugging only).");
ac9ef6cf 108module_param(enable_msi, bint, 0444);
134a11f0 109MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 110#ifdef CONFIG_SND_HDA_PATCH_LOADER
111module_param_array(patch, charp, NULL, 0444);
112MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
113#endif
2dca0bba 114#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 115module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 116MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 117 "(0=off, 1=on) (default=1).");
2dca0bba 118#endif
606ad75f 119
83012a7c 120#ifdef CONFIG_PM
65fcd41d
TI		 121static int param_set_xint(const char *val, const struct kernel_param *kp);
122static struct kernel_param_ops param_ops_xint = {
123 .set = param_set_xint,
124 .get = param_get_int,
125};
126#define param_check_xint param_check_int
127
fee2fba3 128static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 129module_param(power_save, xint, 0644);
fee2fba3
TI		 130MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
131 "(in second, 0 = disable).");
1da177e4 132
dee1b66c
TI		 133/* reset the HD-audio controller in power save mode.
134 * this may give more power-saving, but will take longer time to
135 * wake up.
136 */
8fc24426
TI		 137static bool power_save_controller = 1;
138module_param(power_save_controller, bool, 0644);
dee1b66c 139MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
83012a7c 140#endif /* CONFIG_PM */
dee1b66c 141
7bfe059e
TI		 142static int align_buffer_size = -1;
143module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 144MODULE_PARM_DESC(align_buffer_size,
145 "Force buffer and period sizes to be multiple of 128 bytes.");
146
27fe48d9
TI		 147#ifdef CONFIG_X86
148static bool hda_snoop = true;
149module_param_named(snoop, hda_snoop, bool, 0444);
150MODULE_PARM_DESC(snoop, "Enable/disable snooping");
151#define azx_snoop(chip) (chip)->snoop
152#else
153#define hda_snoop true
154#define azx_snoop(chip) true
155#endif
156
157
1da177e4
LT		 158MODULE_LICENSE("GPL");
159MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
160 "{Intel, ICH6M},"
2f1b3818 161 "{Intel, ICH7},"
f5d40b30 162 "{Intel, ESB2},"
d2981393 163 "{Intel, ICH8},"
f9cc8a8b 164 "{Intel, ICH9},"
c34f5a04 165 "{Intel, ICH10},"
b29c2360 166 "{Intel, PCH},"
d2f2fcd2 167 "{Intel, CPT},"
d2edeb7c 168 "{Intel, PPT},"
8bc039a1 169 "{Intel, LPT},"
144dad99 170 "{Intel, LPT_LP},"
e926f2c8 171 "{Intel, HPT},"
cea310e8 172 "{Intel, PBG},"
4979bca9 173 "{Intel, SCH},"
fc20a562 174 "{ATI, SB450},"
89be83f8 175 "{ATI, SB600},"
778b6e1b 176 "{ATI, RS600},"
5b15c95f 177 "{ATI, RS690},"
e6db1119
WL		 178 "{ATI, RS780},"
179 "{ATI, R600},"
2797f724
HRK		 180 "{ATI, RV630},"
181 "{ATI, RV610},"
27da1834
WL		 182 "{ATI, RV670},"
183 "{ATI, RV635},"
184 "{ATI, RV620},"
185 "{ATI, RV770},"
fc20a562 186 "{VIA, VT8251},"
47672310 187 "{VIA, VT8237A},"
07e4ca50
TI		 188 "{SiS, SIS966},"
189 "{ULI, M5461}}");
1da177e4
LT		 190MODULE_DESCRIPTION("Intel HDA driver");
191
4abc1cc2
TI		 192#ifdef CONFIG_SND_VERBOSE_PRINTK
193#define SFX /* nop */
194#else
445a51b3 195#define SFX "hda-intel "
4abc1cc2 196#endif
cb53c626 197
a82d51ed
TI		 198#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
199#ifdef CONFIG_SND_HDA_CODEC_HDMI
200#define SUPPORT_VGA_SWITCHEROO
201#endif
202#endif
203
204
1da177e4
LT		 205/*
206 * registers
207 */
208#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 209#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
210#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
211#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
212#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
213#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 214#define ICH6_REG_VMIN 0x02
215#define ICH6_REG_VMAJ 0x03
216#define ICH6_REG_OUTPAY 0x04
217#define ICH6_REG_INPAY 0x06
218#define ICH6_REG_GCTL 0x08
8a933ece 219#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 220#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
221#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 222#define ICH6_REG_WAKEEN 0x0c
223#define ICH6_REG_STATESTS 0x0e
224#define ICH6_REG_GSTS 0x10
b21fadb9 225#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 226#define ICH6_REG_INTCTL 0x20
227#define ICH6_REG_INTSTS 0x24
e5463720 228#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 229#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
230#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 231#define ICH6_REG_CORBLBASE 0x40
232#define ICH6_REG_CORBUBASE 0x44
233#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 234#define ICH6_REG_CORBRP 0x4a
235#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 236#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 237#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
238#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 239#define ICH6_REG_CORBSTS 0x4d
b21fadb9 240#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 241#define ICH6_REG_CORBSIZE 0x4e
242
243#define ICH6_REG_RIRBLBASE 0x50
244#define ICH6_REG_RIRBUBASE 0x54
245#define ICH6_REG_RIRBWP 0x58
b21fadb9 246#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 247#define ICH6_REG_RINTCNT 0x5a
248#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 249#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
250#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
251#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 252#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 253#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
254#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 255#define ICH6_REG_RIRBSIZE 0x5e
256
257#define ICH6_REG_IC 0x60
258#define ICH6_REG_IR 0x64
259#define ICH6_REG_IRS 0x68
260#define ICH6_IRS_VALID (1<<1)
261#define ICH6_IRS_BUSY (1<<0)
262
263#define ICH6_REG_DPLBASE 0x70
264#define ICH6_REG_DPUBASE 0x74
265#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
266
267/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
268enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
269
270/* stream register offsets from stream base */
271#define ICH6_REG_SD_CTL 0x00
272#define ICH6_REG_SD_STS 0x03
273#define ICH6_REG_SD_LPIB 0x04
274#define ICH6_REG_SD_CBL 0x08
275#define ICH6_REG_SD_LVI 0x0c
276#define ICH6_REG_SD_FIFOW 0x0e
277#define ICH6_REG_SD_FIFOSIZE 0x10
278#define ICH6_REG_SD_FORMAT 0x12
279#define ICH6_REG_SD_BDLPL 0x18
280#define ICH6_REG_SD_BDLPU 0x1c
281
282/* PCI space */
283#define ICH6_PCIREG_TCSEL 0x44
284
285/*
286 * other constants
287 */
288
289/* max number of SDs */
07e4ca50 290/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 291#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 292#define ICH6_NUM_PLAYBACK 4
293
294/* ULI has 6 playback and 5 capture */
07e4ca50 295#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 296#define ULI_NUM_PLAYBACK 6
297
778b6e1b 298/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 299#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 300#define ATIHDMI_NUM_PLAYBACK 1
301
f269002e
KY		 302/* TERA has 4 playback and 3 capture */
303#define TERA_NUM_CAPTURE 3
304#define TERA_NUM_PLAYBACK 4
305
07e4ca50
TI		 306/* this number is statically defined for simplicity */
307#define MAX_AZX_DEV 16
308
1da177e4 309/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 310#define BDL_SIZE 4096
311#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
312#define AZX_MAX_FRAG 32
1da177e4
LT		 313/* max buffer size - no h/w limit, you can increase as you like */
314#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 315
316/* RIRB int mask: overrun[2], response[0] */
317#define RIRB_INT_RESPONSE 0x01
318#define RIRB_INT_OVERRUN 0x04
319#define RIRB_INT_MASK 0x05
320
2f5983f2 321/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 322#define AZX_MAX_CODECS 8
323#define AZX_DEFAULT_CODECS 4
deadff16 324#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 325
326/* SD_CTL bits */
327#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
328#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 329#define SD_CTL_STRIPE (3 << 16) /* stripe control */
330#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
331#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 332#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
333#define SD_CTL_STREAM_TAG_SHIFT 20
334
335/* SD_CTL and SD_STS */
336#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
337#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
338#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 339#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
340 SD_INT_COMPLETE)
1da177e4
LT		 341
342/* SD_STS */
343#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
344
345/* INTCTL and INTSTS */
d01ce99f
TI		 346#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
347#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
348#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 349
1da177e4
LT		 350/* below are so far hardcoded - should read registers in future */
351#define ICH6_MAX_CORB_ENTRIES 256
352#define ICH6_MAX_RIRB_ENTRIES 256
353
c74db86b
TI		 354/* position fix mode */
355enum {
0be3b5d3 356 POS_FIX_AUTO,
d2e1c973 357 POS_FIX_LPIB,
0be3b5d3 358 POS_FIX_POSBUF,
4cb36310 359 POS_FIX_VIACOMBO,
a6f2fd55 360 POS_FIX_COMBO,
c74db86b 361};
1da177e4 362
f5d40b30 363/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 364#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
365#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
366
da3fca21
V		 367/* Defines for Nvidia HDA support */
368#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
369#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 370#define NVIDIA_HDA_ISTRM_COH 0x4d
371#define NVIDIA_HDA_OSTRM_COH 0x4c
372#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 373
90a5ad52
TI		 374/* Defines for Intel SCH HDA snoop control */
375#define INTEL_SCH_HDA_DEVC 0x78
376#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
377
0e153474
JC		 378/* Define IN stream 0 FIFO size offset in VIA controller */
379#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
380/* Define VIA HD Audio Device ID*/
381#define VIA_HDAC_DEVICE_ID 0x3288
382
c4da29ca
YL		 383/* HD Audio class code */
384#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 385
1da177e4
LT		 386/*
387 */
388
a98f90fd 389struct azx_dev {
4ce107b9 390 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 391 u32 *posbuf; /* position buffer pointer */
1da177e4 392
d01ce99f 393 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 394 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 395 unsigned int frags; /* number for period in the play buffer */
396 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 397 unsigned long start_wallclk; /* start + minimum wallclk */
398 unsigned long period_wallclk; /* wallclk for period */
1da177e4 399
d01ce99f 400 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 401
d01ce99f 402 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 403
404 /* pcm support */
d01ce99f
TI		 405 struct snd_pcm_substream *substream; /* assigned substream,
406 * set in PCM open
407 */
408 unsigned int format_val; /* format value to be set in the
409 * controller and the codec
410 */
1da177e4
LT		 411 unsigned char stream_tag; /* assigned stream */
412 unsigned char index; /* stream index */
d5cf9911 413 int assigned_key; /* last device# key assigned to */
1da177e4 414
927fc866
PM		 415 unsigned int opened :1;
416 unsigned int running :1;
675f25d4 417 unsigned int irq_pending :1;
eb49faa6
TI		 418 unsigned int prepared:1;
419 unsigned int locked:1;
0e153474
JC		 420 /*
421 * For VIA:
422 * A flag to ensure DMA position is 0
423 * when link position is not greater than FIFO size
424 */
425 unsigned int insufficient :1;
27fe48d9 426 unsigned int wc_marked:1;
915bf29e 427 unsigned int no_period_wakeup:1;
5d890f59
PLB		 428
429 struct timecounter azx_tc;
430 struct cyclecounter azx_cc;
eb49faa6
TI		 431
432#ifdef CONFIG_SND_HDA_DSP_LOADER
433 struct mutex dsp_mutex;
434#endif
1da177e4
LT		 435};
436
eb49faa6
TI		 437/* DSP lock helpers */
438#ifdef CONFIG_SND_HDA_DSP_LOADER
439#define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
440#define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
441#define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
442#define dsp_is_locked(dev) ((dev)->locked)
443#else
444#define dsp_lock_init(dev) do {} while (0)
445#define dsp_lock(dev) do {} while (0)
446#define dsp_unlock(dev) do {} while (0)
447#define dsp_is_locked(dev) 0
448#endif
449
1da177e4 450/* CORB/RIRB */
a98f90fd 451struct azx_rb {
1da177e4
LT		 452 u32 *buf; /* CORB/RIRB buffer
453 * Each CORB entry is 4byte, RIRB is 8byte
454 */
455 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
456 /* for RIRB */
457 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 458 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
459 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 460};
461
01b65bfb
TI		 462struct azx_pcm {
463 struct azx *chip;
464 struct snd_pcm *pcm;
465 struct hda_codec *codec;
466 struct hda_pcm_stream *hinfo[2];
467 struct list_head list;
468};
469
a98f90fd
TI		 470struct azx {
471 struct snd_card *card;
1da177e4 472 struct pci_dev *pci;
555e219f 473 int dev_index;
1da177e4 474
07e4ca50
TI		 475 /* chip type specific */
476 int driver_type;
9477c58e 477 unsigned int driver_caps;
07e4ca50
TI		 478 int playback_streams;
479 int playback_index_offset;
480 int capture_streams;
481 int capture_index_offset;
482 int num_streams;
483
1da177e4
LT		 484 /* pci resources */
485 unsigned long addr;
486 void __iomem *remap_addr;
487 int irq;
488
489 /* locks */
490 spinlock_t reg_lock;
62932df8 491 struct mutex open_mutex;
f4c482a4 492 struct completion probe_wait;
1da177e4 493
07e4ca50 494 /* streams (x num_streams) */
a98f90fd 495 struct azx_dev *azx_dev;
1da177e4
LT		 496
497 /* PCM */
01b65bfb 498 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 499
500 /* HD codec */
501 unsigned short codec_mask;
f1eaaeec 502 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 503 struct hda_bus *bus;
2dca0bba 504 unsigned int beep_mode;
1da177e4
LT		 505
506 /* CORB/RIRB */
a98f90fd
TI		 507 struct azx_rb corb;
508 struct azx_rb rirb;
1da177e4 509
4ce107b9 510 /* CORB/RIRB and position buffers */
1da177e4
LT		 511 struct snd_dma_buffer rb;
512 struct snd_dma_buffer posbuf;
c74db86b 513
4918cdab
TI		 514#ifdef CONFIG_SND_HDA_PATCH_LOADER
515 const struct firmware *fw;
516#endif
517
c74db86b 518 /* flags */
beaffc39 519 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 520 int poll_count;
cb53c626 521 unsigned int running :1;
927fc866
PM		 522 unsigned int initialized :1;
523 unsigned int single_cmd :1;
524 unsigned int polling_mode :1;
68e7fffc 525 unsigned int msi :1;
a6a950a8 526 unsigned int irq_pending_warned :1;
6ce4a3bc 527 unsigned int probing :1; /* codec probing phase */
27fe48d9 528 unsigned int snoop:1;
52409aa6 529 unsigned int align_buffer_size:1;
a82d51ed
TI		 530 unsigned int region_requested:1;
531
532 /* VGA-switcheroo setup */
533 unsigned int use_vga_switcheroo:1;
128960a9 534 unsigned int vga_switcheroo_registered:1;
a82d51ed
TI		 535 unsigned int init_failed:1; /* delayed init failed */
536 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 537
538 /* for debugging */
feb27340 539 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 540
541 /* for pending irqs */
542 struct work_struct irq_pending_work;
0cbf0098
TI		 543
544 /* reboot notifier (for mysterious hangup problem at power-down) */
545 struct notifier_block reboot_notifier;
65fcd41d
TI		 546
547 /* card list (for power_save trigger) */
548 struct list_head list;
eb49faa6
TI		 549
550#ifdef CONFIG_SND_HDA_DSP_LOADER
551 struct azx_dev saved_azx_dev;
552#endif
1da177e4
LT		 553};
554
1a8506d4
TI		 555#define CREATE_TRACE_POINTS
556#include "hda_intel_trace.h"
557
07e4ca50
TI		 558/* driver types */
559enum {
560 AZX_DRIVER_ICH,
32679f95 561 AZX_DRIVER_PCH,
4979bca9 562 AZX_DRIVER_SCH,
07e4ca50 563 AZX_DRIVER_ATI,
778b6e1b 564 AZX_DRIVER_ATIHDMI,
1815b34a 565 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 566 AZX_DRIVER_VIA,
567 AZX_DRIVER_SIS,
568 AZX_DRIVER_ULI,
da3fca21 569 AZX_DRIVER_NVIDIA,
f269002e 570 AZX_DRIVER_TERA,
14d34f16 571 AZX_DRIVER_CTX,
5ae763b1 572 AZX_DRIVER_CTHDA,
c4da29ca 573 AZX_DRIVER_GENERIC,
2f5983f2 574 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 575};
576
9477c58e
TI		 577/* driver quirks (capabilities) */
578/* bits 0-7 are used for indicating driver type */
579#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
580#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
581#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
582#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
583#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
584#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
585#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
586#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
587#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
588#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
589#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
590#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 591#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 592#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 593#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 594#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
90accc58 595#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
2ea3c6a2
TI		 596#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
597
598/* quirks for Intel PCH */
d7dab4db 599#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 600 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 601 AZX_DCAPS_COUNT_LPIB_DELAY)
602
603#define AZX_DCAPS_INTEL_PCH \
604 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e
TI		 605
606/* quirks for ATI SB / AMD Hudson */
607#define AZX_DCAPS_PRESET_ATI_SB \
608 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
609 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
610
611/* quirks for ATI/AMD HDMI */
612#define AZX_DCAPS_PRESET_ATI_HDMI \
613 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
614
615/* quirks for Nvidia */
616#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 617 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
49d9e77e 618 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
9477c58e 619
5ae763b1
TI		 620#define AZX_DCAPS_PRESET_CTHDA \
621 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
622
a82d51ed
TI		 623/*
624 * VGA-switcher support
625 */
626#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 627#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
628#else
629#define use_vga_switcheroo(chip) 0
630#endif
631
48c8b0eb 632static char *driver_short_names[] = {
07e4ca50 633 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 634 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 635 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 636 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 637 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 638 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 639 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
640 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 641 [AZX_DRIVER_ULI] = "HDA ULI M5461",
642 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 643 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 644 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 645 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 646 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 647};
648
1da177e4
LT		 649/*
650 * macros for easy use
651 */
652#define azx_writel(chip,reg,value) \
653 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
654#define azx_readl(chip,reg) \
655 readl((chip)->remap_addr + ICH6_REG_##reg)
656#define azx_writew(chip,reg,value) \
657 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
658#define azx_readw(chip,reg) \
659 readw((chip)->remap_addr + ICH6_REG_##reg)
660#define azx_writeb(chip,reg,value) \
661 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
662#define azx_readb(chip,reg) \
663 readb((chip)->remap_addr + ICH6_REG_##reg)
664
665#define azx_sd_writel(dev,reg,value) \
666 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
667#define azx_sd_readl(dev,reg) \
668 readl((dev)->sd_addr + ICH6_REG_##reg)
669#define azx_sd_writew(dev,reg,value) \
670 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
671#define azx_sd_readw(dev,reg) \
672 readw((dev)->sd_addr + ICH6_REG_##reg)
673#define azx_sd_writeb(dev,reg,value) \
674 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
675#define azx_sd_readb(dev,reg) \
676 readb((dev)->sd_addr + ICH6_REG_##reg)
677
678/* for pcm support */
a98f90fd 679#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 680
27fe48d9 681#ifdef CONFIG_X86
9ddf1aeb 682static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 683{
9ddf1aeb
TI		 684 int pages;
685
27fe48d9
TI		 686 if (azx_snoop(chip))
687 return;
9ddf1aeb
TI		 688 if (!dmab || !dmab->area || !dmab->bytes)
689 return;
690
691#ifdef CONFIG_SND_DMA_SGBUF
692 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
693 struct snd_sg_buf *sgbuf = dmab->private_data;
27fe48d9 694 if (on)
9ddf1aeb 695 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 696 else
9ddf1aeb
TI		 697 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
698 return;
27fe48d9 699 }
9ddf1aeb
TI		 700#endif
701
702 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
703 if (on)
704 set_memory_wc((unsigned long)dmab->area, pages);
705 else
706 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 707}
708
709static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
710 bool on)
711{
9ddf1aeb 712 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 713}
714static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 715 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 716{
717 if (azx_dev->wc_marked != on) {
9ddf1aeb 718 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 719 azx_dev->wc_marked = on;
720 }
721}
722#else
723/* NOP for other archs */
724static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
725 bool on)
726{
727}
728static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 729 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 730{
731}
732#endif
733
68e7fffc 734static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 735static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 736/*
737 * Interface for HD codec
738 */
739
1da177e4
LT		 740/*
741 * CORB / RIRB interface
742 */
a98f90fd 743static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 744{
745 int err;
746
747 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 748 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
749 snd_dma_pci_data(chip->pci),
1da177e4
LT		 750 PAGE_SIZE, &chip->rb);
751 if (err < 0) {
445a51b3 752 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
1da177e4
LT		 753 return err;
754 }
27fe48d9 755 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 756 return 0;
757}
758
a98f90fd 759static void azx_init_cmd_io(struct azx *chip)
1da177e4 760{
cdb1fbf2 761 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 762 /* CORB set up */
763 chip->corb.addr = chip->rb.addr;
764 chip->corb.buf = (u32 *)chip->rb.area;
765 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 766 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 767
07e4ca50
TI		 768 /* set the corb size to 256 entries (ULI requires explicitly) */
769 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 770 /* set the corb write pointer to 0 */
771 azx_writew(chip, CORBWP, 0);
772 /* reset the corb hw read pointer */
b21fadb9 773 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 774 /* enable corb dma */
b21fadb9 775 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 776
777 /* RIRB set up */
778 chip->rirb.addr = chip->rb.addr + 2048;
779 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 780 chip->rirb.wp = chip->rirb.rp = 0;
781 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 782 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 783 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 784
07e4ca50
TI		 785 /* set the rirb size to 256 entries (ULI requires explicitly) */
786 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 787 /* reset the rirb hw write pointer */
b21fadb9 788 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 789 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 790 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 791 azx_writew(chip, RINTCNT, 0xc0);
792 else
793 azx_writew(chip, RINTCNT, 1);
1da177e4 794 /* enable rirb dma and response irq */
1da177e4 795 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 796 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 797}
798
a98f90fd 799static void azx_free_cmd_io(struct azx *chip)
1da177e4 800{
cdb1fbf2 801 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 802 /* disable ringbuffer DMAs */
803 azx_writeb(chip, RIRBCTL, 0);
804 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 805 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 806}
807
deadff16
WF		 808static unsigned int azx_command_addr(u32 cmd)
809{
810 unsigned int addr = cmd >> 28;
811
812 if (addr >= AZX_MAX_CODECS) {
813 snd_BUG();
814 addr = 0;
815 }
816
817 return addr;
818}
819
820static unsigned int azx_response_addr(u32 res)
821{
822 unsigned int addr = res & 0xf;
823
824 if (addr >= AZX_MAX_CODECS) {
825 snd_BUG();
826 addr = 0;
827 }
828
829 return addr;
1da177e4
LT		 830}
831
832/* send a command */
33fa35ed 833static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 834{
33fa35ed 835 struct azx *chip = bus->private_data;
deadff16 836 unsigned int addr = azx_command_addr(val);
3bcce5c0 837 unsigned int wp, rp;
1da177e4 838
c32649fe
WF		 839 spin_lock_irq(&chip->reg_lock);
840
1da177e4 841 /* add command to corb */
cc5ede3e
TI		 842 wp = azx_readw(chip, CORBWP);
843 if (wp == 0xffff) {
844 /* something wrong, controller likely turned to D3 */
845 spin_unlock_irq(&chip->reg_lock);
3bcce5c0 846 return -EIO;
cc5ede3e 847 }
1da177e4
LT		 848 wp++;
849 wp %= ICH6_MAX_CORB_ENTRIES;
850
3bcce5c0
TI		 851 rp = azx_readw(chip, CORBRP);
852 if (wp == rp) {
853 /* oops, it's full */
854 spin_unlock_irq(&chip->reg_lock);
855 return -EAGAIN;
856 }
857
deadff16 858 chip->rirb.cmds[addr]++;
1da177e4
LT		 859 chip->corb.buf[wp] = cpu_to_le32(val);
860 azx_writel(chip, CORBWP, wp);
c32649fe 861
1da177e4
LT		 862 spin_unlock_irq(&chip->reg_lock);
863
864 return 0;
865}
866
867#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
868
869/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 870static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 871{
872 unsigned int rp, wp;
deadff16 873 unsigned int addr;
1da177e4
LT		 874 u32 res, res_ex;
875
cc5ede3e
TI		 876 wp = azx_readw(chip, RIRBWP);
877 if (wp == 0xffff) {
878 /* something wrong, controller likely turned to D3 */
879 return;
880 }
881
1da177e4
LT		 882 if (wp == chip->rirb.wp)
883 return;
884 chip->rirb.wp = wp;
deadff16 885
1da177e4
LT		 886 while (chip->rirb.rp != wp) {
887 chip->rirb.rp++;
888 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
889
890 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
891 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
892 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 893 addr = azx_response_addr(res_ex);
1da177e4
LT		 894 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
895 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 896 else if (chip->rirb.cmds[addr]) {
897 chip->rirb.res[addr] = res;
2add9b92 898 smp_wmb();
deadff16 899 chip->rirb.cmds[addr]--;
e310bb06 900 } else
9e3d352b 901 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
e310bb06 902 "last cmd=%#08x\n",
9e3d352b 903 pci_name(chip->pci),
e310bb06
WF		 904 res, res_ex,
905 chip->last_cmd[addr]);
1da177e4
LT		 906 }
907}
908
909/* receive a response */
deadff16
WF		 910static unsigned int azx_rirb_get_response(struct hda_bus *bus,
911 unsigned int addr)
1da177e4 912{
33fa35ed 913 struct azx *chip = bus->private_data;
5c79b1f8 914 unsigned long timeout;
32cf4023 915 unsigned long loopcounter;
1eb6dc7d 916 int do_poll = 0;
1da177e4 917
5c79b1f8
TI		 918 again:
919 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 920
921 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 922 if (chip->polling_mode || do_poll) {
e96224ae
TI		 923 spin_lock_irq(&chip->reg_lock);
924 azx_update_rirb(chip);
925 spin_unlock_irq(&chip->reg_lock);
926 }
deadff16 927 if (!chip->rirb.cmds[addr]) {
2add9b92 928 smp_rmb();
b613291f 929 bus->rirb_error = 0;
1eb6dc7d
ML		 930
931 if (!do_poll)
932 chip->poll_count = 0;
deadff16 933 return chip->rirb.res[addr]; /* the last value */
2add9b92 934 }
28a0d9df
TI		 935 if (time_after(jiffies, timeout))
936 break;
32cf4023 937 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 938 msleep(2); /* temporary workaround */
939 else {
940 udelay(10);
941 cond_resched();
942 }
28a0d9df 943 }
5c79b1f8 944
63e51fd7
TI		 945 if (!bus->no_response_fallback)
946 return -1;
947
1eb6dc7d 948 if (!chip->polling_mode && chip->poll_count < 2) {
445a51b3 949 snd_printdd(SFX "%s: azx_get_response timeout, "
1eb6dc7d 950 "polling the codec once: last cmd=0x%08x\n",
445a51b3 951 pci_name(chip->pci), chip->last_cmd[addr]);
1eb6dc7d
ML		 952 do_poll = 1;
953 chip->poll_count++;
954 goto again;
955 }
956
957
23c4a881 958 if (!chip->polling_mode) {
445a51b3 959 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
23c4a881 960 "switching to polling mode: last cmd=0x%08x\n",
445a51b3 961 pci_name(chip->pci), chip->last_cmd[addr]);
23c4a881
TI		 962 chip->polling_mode = 1;
963 goto again;
964 }
965
68e7fffc 966 if (chip->msi) {
445a51b3 967 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
feb27340 968 "disabling MSI: last cmd=0x%08x\n",
445a51b3 969 pci_name(chip->pci), chip->last_cmd[addr]);
68e7fffc
TI		 970 free_irq(chip->irq, chip);
971 chip->irq = -1;
972 pci_disable_msi(chip->pci);
973 chip->msi = 0;
b613291f
TI		 974 if (azx_acquire_irq(chip, 1) < 0) {
975 bus->rirb_error = 1;
68e7fffc 976 return -1;
b613291f 977 }
68e7fffc
TI		 978 goto again;
979 }
980
6ce4a3bc
TI		 981 if (chip->probing) {
982 /* If this critical timeout happens during the codec probing
983 * phase, this is likely an access to a non-existing codec
984 * slot. Better to return an error and reset the system.
985 */
986 return -1;
987 }
988
8dd78330
TI		 989 /* a fatal communication error; need either to reset or to fallback
990 * to the single_cmd mode
991 */
b613291f 992 bus->rirb_error = 1;
b20f3b83 993 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 994 bus->response_reset = 1;
995 return -1; /* give a chance to retry */
996 }
997
998 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
999 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 1000 chip->last_cmd[addr]);
8dd78330
TI		 1001 chip->single_cmd = 1;
1002 bus->response_reset = 0;
1a696978 1003 /* release CORB/RIRB */
4fcd3920 1004 azx_free_cmd_io(chip);
1a696978
TI		 1005 /* disable unsolicited responses */
1006 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 1007 return -1;
1da177e4
LT		 1008}
1009
1da177e4
LT		 1010/*
1011 * Use the single immediate command instead of CORB/RIRB for simplicity
1012 *
1013 * Note: according to Intel, this is not preferred use. The command was
1014 * intended for the BIOS only, and may get confused with unsolicited
1015 * responses. So, we shouldn't use it for normal operation from the
1016 * driver.
1017 * I left the codes, however, for debugging/testing purposes.
1018 */
1019
b05a7d4f 1020/* receive a response */
deadff16 1021static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 1022{
1023 int timeout = 50;
1024
1025 while (timeout--) {
1026 /* check IRV busy bit */
1027 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1028 /* reuse rirb.res as the response return value */
deadff16 1029 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 1030 return 0;
1031 }
1032 udelay(1);
1033 }
1034 if (printk_ratelimit())
445a51b3
DB		 1035 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1036 pci_name(chip->pci), azx_readw(chip, IRS));
deadff16 1037 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 1038 return -EIO;
1039}
1040
1da177e4 1041/* send a command */
33fa35ed 1042static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 1043{
33fa35ed 1044 struct azx *chip = bus->private_data;
deadff16 1045 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 1046 int timeout = 50;
1047
8dd78330 1048 bus->rirb_error = 0;
1da177e4
LT		 1049 while (timeout--) {
1050 /* check ICB busy bit */
d01ce99f 1051 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 1052 /* Clear IRV valid bit */
d01ce99f
TI		 1053 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1054 ICH6_IRS_VALID);
1da177e4 1055 azx_writel(chip, IC, val);
d01ce99f
TI		 1056 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1057 ICH6_IRS_BUSY);
deadff16 1058 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 1059 }
1060 udelay(1);
1061 }
1cfd52bc 1062 if (printk_ratelimit())
445a51b3
DB		 1063 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1064 pci_name(chip->pci), azx_readw(chip, IRS), val);
1da177e4
LT		 1065 return -EIO;
1066}
1067
1068/* receive a response */
deadff16
WF		 1069static unsigned int azx_single_get_response(struct hda_bus *bus,
1070 unsigned int addr)
1da177e4 1071{
33fa35ed 1072 struct azx *chip = bus->private_data;
deadff16 1073 return chip->rirb.res[addr];
1da177e4
LT		 1074}
1075
111d3af5
TI		 1076/*
1077 * The below are the main callbacks from hda_codec.
1078 *
1079 * They are just the skeleton to call sub-callbacks according to the
1080 * current setting of chip->single_cmd.
1081 */
1082
1083/* send a command */
33fa35ed 1084static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 1085{
33fa35ed 1086 struct azx *chip = bus->private_data;
43bbb6cc 1087
a82d51ed
TI		 1088 if (chip->disabled)
1089 return 0;
feb27340 1090 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 1091 if (chip->single_cmd)
33fa35ed 1092 return azx_single_send_cmd(bus, val);
111d3af5 1093 else
33fa35ed 1094 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 1095}
1096
1097/* get a response */
deadff16
WF		 1098static unsigned int azx_get_response(struct hda_bus *bus,
1099 unsigned int addr)
111d3af5 1100{
33fa35ed 1101 struct azx *chip = bus->private_data;
a82d51ed
TI		 1102 if (chip->disabled)
1103 return 0;
111d3af5 1104 if (chip->single_cmd)
deadff16 1105 return azx_single_get_response(bus, addr);
111d3af5 1106 else
deadff16 1107 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1108}
1109
83012a7c 1110#ifdef CONFIG_PM
68467f51 1111static void azx_power_notify(struct hda_bus *bus, bool power_up);
cb53c626 1112#endif
111d3af5 1113
1d1a4564
TI		 1114#ifdef CONFIG_SND_HDA_DSP_LOADER
1115static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1116 unsigned int byte_size,
1117 struct snd_dma_buffer *bufp);
1118static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1119static void azx_load_dsp_cleanup(struct hda_bus *bus,
1120 struct snd_dma_buffer *dmab);
1121#endif
1122
3af3f356
ML		 1123/* enter link reset */
1124static void azx_reset_link(struct azx *chip)
1125{
1126 unsigned long timeout;
1127
1128 /* reset controller */
1129 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1130
1131 timeout = jiffies + msecs_to_jiffies(100);
1132 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
1133 time_before(jiffies, timeout))
1134 usleep_range(500, 1000);
1135}
1136
1da177e4 1137/* reset codec link */
cd508fe5 1138static int azx_reset(struct azx *chip, int full_reset)
1da177e4 1139{
fa348da5 1140 unsigned long timeout;
1da177e4 1141
cd508fe5
JK		 1142 if (!full_reset)
1143 goto __skip;
1144
e8a7f136
DT		 1145 /* clear STATESTS */
1146 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1147
1da177e4
LT		 1148 /* reset controller */
1149 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1150
fa348da5
ML		 1151 timeout = jiffies + msecs_to_jiffies(100);
1152 while (azx_readb(chip, GCTL) &&
1153 time_before(jiffies, timeout))
1154 usleep_range(500, 1000);
1da177e4
LT		 1155
1156 /* delay for >= 100us for codec PLL to settle per spec
1157 * Rev 0.9 section 5.5.1
1158 */
fa348da5 1159 usleep_range(500, 1000);
1da177e4
LT		 1160
1161 /* Bring controller out of reset */
1162 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1163
fa348da5
ML		 1164 timeout = jiffies + msecs_to_jiffies(100);
1165 while (!azx_readb(chip, GCTL) &&
1166 time_before(jiffies, timeout))
1167 usleep_range(500, 1000);
1da177e4 1168
927fc866 1169 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
fa348da5 1170 usleep_range(1000, 1200);
1da177e4 1171
cd508fe5 1172 __skip:
1da177e4 1173 /* check to see if controller is ready */
927fc866 1174 if (!azx_readb(chip, GCTL)) {
445a51b3 1175 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1da177e4
LT		 1176 return -EBUSY;
1177 }
1178
41e2fce4 1179 /* Accept unsolicited responses */
1a696978
TI		 1180 if (!chip->single_cmd)
1181 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1182 ICH6_GCTL_UNSOL);
41e2fce4 1183
1da177e4 1184 /* detect codecs */
927fc866 1185 if (!chip->codec_mask) {
1da177e4 1186 chip->codec_mask = azx_readw(chip, STATESTS);
445a51b3 1187 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1da177e4
LT		 1188 }
1189
1190 return 0;
1191}
1192
1193
1194/*
1195 * Lowlevel interface
1196 */
1197
1198/* enable interrupts */
a98f90fd 1199static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1200{
1201 /* enable controller CIE and GIE */
1202 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1203 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1204}
1205
1206/* disable interrupts */
a98f90fd 1207static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1208{
1209 int i;
1210
1211 /* disable interrupts in stream descriptor */
07e4ca50 1212 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1213 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1214 azx_sd_writeb(azx_dev, SD_CTL,
1215 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1216 }
1217
1218 /* disable SIE for all streams */
1219 azx_writeb(chip, INTCTL, 0);
1220
1221 /* disable controller CIE and GIE */
1222 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1223 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1224}
1225
1226/* clear interrupts */
a98f90fd 1227static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1228{
1229 int i;
1230
1231 /* clear stream status */
07e4ca50 1232 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1233 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1234 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1235 }
1236
1237 /* clear STATESTS */
1238 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1239
1240 /* clear rirb status */
1241 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1242
1243 /* clear int status */
1244 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1245}
1246
1247/* start a stream */
a98f90fd 1248static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1249{
0e153474
JC		 1250 /*
1251 * Before stream start, initialize parameter
1252 */
1253 azx_dev->insufficient = 1;
1254
1da177e4 1255 /* enable SIE */
ccc5df05
WN		 1256 azx_writel(chip, INTCTL,
1257 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1258 /* set DMA start and interrupt mask */
1259 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1260 SD_CTL_DMA_START | SD_INT_MASK);
1261}
1262
1dddab40
TI		 1263/* stop DMA */
1264static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1265{
1da177e4
LT		 1266 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1267 ~(SD_CTL_DMA_START | SD_INT_MASK));
1268 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1269}
1270
1271/* stop a stream */
1272static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1273{
1274 azx_stream_clear(chip, azx_dev);
1da177e4 1275 /* disable SIE */
ccc5df05
WN		 1276 azx_writel(chip, INTCTL,
1277 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1278}
1279
1280
1281/*
cb53c626 1282 * reset and start the controller registers
1da177e4 1283 */
cd508fe5 1284static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1285{
cb53c626
TI		 1286 if (chip->initialized)
1287 return;
1da177e4
LT		 1288
1289 /* reset controller */
cd508fe5 1290 azx_reset(chip, full_reset);
1da177e4
LT		 1291
1292 /* initialize interrupts */
1293 azx_int_clear(chip);
1294 azx_int_enable(chip);
1295
1296 /* initialize the codec command I/O */
1a696978
TI		 1297 if (!chip->single_cmd)
1298 azx_init_cmd_io(chip);
1da177e4 1299
0be3b5d3
TI		 1300 /* program the position buffer */
1301 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1302 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1303
cb53c626
TI		 1304 chip->initialized = 1;
1305}
1306
1307/*
1308 * initialize the PCI registers
1309 */
1310/* update bits in a PCI register byte */
1311static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1312 unsigned char mask, unsigned char val)
1313{
1314 unsigned char data;
1315
1316 pci_read_config_byte(pci, reg, &data);
1317 data &= ~mask;
1318 data |= (val & mask);
1319 pci_write_config_byte(pci, reg, data);
1320}
1321
1322static void azx_init_pci(struct azx *chip)
1323{
1324 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1325 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1326 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1327 * codecs.
1328 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1329 */
46f2cc80 1330 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
445a51b3 1331 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
a09e89f6 1332 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1333 }
cb53c626 1334
9477c58e
TI		 1335 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1336 * we need to enable snoop.
1337 */
1338 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
445a51b3 1339 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626 1340 update_pci_byte(chip->pci,
27fe48d9
TI		 1341 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1342 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1343 }
1344
1345 /* For NVIDIA HDA, enable snoop */
1346 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
445a51b3 1347 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626
TI		 1348 update_pci_byte(chip->pci,
1349 NVIDIA_HDA_TRANSREG_ADDR,
1350 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1351 update_pci_byte(chip->pci,
1352 NVIDIA_HDA_ISTRM_COH,
1353 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1354 update_pci_byte(chip->pci,
1355 NVIDIA_HDA_OSTRM_COH,
1356 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1357 }
1358
1359 /* Enable SCH/PCH snoop if needed */
1360 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1361 unsigned short snoop;
90a5ad52 1362 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1363 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1364 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1365 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1366 if (!azx_snoop(chip))
1367 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1368 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1369 pci_read_config_word(chip->pci,
1370 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1371 }
445a51b3
DB		 1372 snd_printdd(SFX "%s: SCH snoop: %s\n",
1373 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
27fe48d9 1374 ? "Disabled" : "Enabled");
da3fca21 1375 }
1da177e4
LT		 1376}
1377
1378
9ad593f6
TI		 1379static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1380
1da177e4
LT		 1381/*
1382 * interrupt handler
1383 */
7d12e780 1384static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1385{
a98f90fd
TI		 1386 struct azx *chip = dev_id;
1387 struct azx_dev *azx_dev;
1da177e4 1388 u32 status;
9ef04066 1389 u8 sd_status;
fa00e046 1390 int i, ok;
1da177e4 1391
b8dfc462
ML		 1392#ifdef CONFIG_PM_RUNTIME
1393 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1394 return IRQ_NONE;
1395#endif
1396
1da177e4
LT		 1397 spin_lock(&chip->reg_lock);
1398
60911062
DC		 1399 if (chip->disabled) {
1400 spin_unlock(&chip->reg_lock);
a82d51ed 1401 return IRQ_NONE;
60911062 1402 }
a82d51ed 1403
1da177e4
LT		 1404 status = azx_readl(chip, INTSTS);
1405 if (status == 0) {
1406 spin_unlock(&chip->reg_lock);
1407 return IRQ_NONE;
1408 }
1409
07e4ca50 1410 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1411 azx_dev = &chip->azx_dev[i];
1412 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1413 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1414 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1415 if (!azx_dev->substream || !azx_dev->running ||
1416 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1417 continue;
1418 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1419 ok = azx_position_ok(chip, azx_dev);
1420 if (ok == 1) {
9ad593f6 1421 azx_dev->irq_pending = 0;
1da177e4
LT		 1422 spin_unlock(&chip->reg_lock);
1423 snd_pcm_period_elapsed(azx_dev->substream);
1424 spin_lock(&chip->reg_lock);
fa00e046 1425 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1426 /* bogus IRQ, process it later */
1427 azx_dev->irq_pending = 1;
6acaed38
TI		 1428 queue_work(chip->bus->workq,
1429 &chip->irq_pending_work);
1da177e4
LT		 1430 }
1431 }
1432 }
1433
1434 /* clear rirb int */
1435 status = azx_readb(chip, RIRBSTS);
1436 if (status & RIRB_INT_MASK) {
14d34f16 1437 if (status & RIRB_INT_RESPONSE) {
9477c58e 1438 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1439 udelay(80);
1da177e4 1440 azx_update_rirb(chip);
14d34f16 1441 }
1da177e4
LT		 1442 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1443 }
1444
1445#if 0
1446 /* clear state status int */
1447 if (azx_readb(chip, STATESTS) & 0x04)
1448 azx_writeb(chip, STATESTS, 0x04);
1449#endif
1450 spin_unlock(&chip->reg_lock);
1451
1452 return IRQ_HANDLED;
1453}
1454
1455
675f25d4
TI		 1456/*
1457 * set up a BDL entry
1458 */
5ae763b1 1459static int setup_bdle(struct azx *chip,
1d1a4564 1460 struct snd_dma_buffer *dmab,
675f25d4
TI		 1461 struct azx_dev *azx_dev, u32 **bdlp,
1462 int ofs, int size, int with_ioc)
1463{
675f25d4
TI		 1464 u32 *bdl = *bdlp;
1465
1466 while (size > 0) {
1467 dma_addr_t addr;
1468 int chunk;
1469
1470 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1471 return -EINVAL;
1472
1d1a4564 1473 addr = snd_sgbuf_get_addr(dmab, ofs);
675f25d4
TI		 1474 /* program the address field of the BDL entry */
1475 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1476 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1477 /* program the size field of the BDL entry */
1d1a4564 1478 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
5ae763b1
TI		 1479 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1480 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1481 u32 remain = 0x1000 - (ofs & 0xfff);
1482 if (chunk > remain)
1483 chunk = remain;
1484 }
675f25d4
TI		 1485 bdl[2] = cpu_to_le32(chunk);
1486 /* program the IOC to enable interrupt
1487 * only when the whole fragment is processed
1488 */
1489 size -= chunk;
1490 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1491 bdl += 4;
1492 azx_dev->frags++;
1493 ofs += chunk;
1494 }
1495 *bdlp = bdl;
1496 return ofs;
1497}
1498
1da177e4
LT		 1499/*
1500 * set up BDL entries
1501 */
555e219f
TI		 1502static int azx_setup_periods(struct azx *chip,
1503 struct snd_pcm_substream *substream,
4ce107b9 1504 struct azx_dev *azx_dev)
1da177e4 1505{
4ce107b9
TI		 1506 u32 *bdl;
1507 int i, ofs, periods, period_bytes;
555e219f 1508 int pos_adj;
1da177e4
LT		 1509
1510 /* reset BDL address */
1511 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1512 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1513
97b71c94 1514 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1515 periods = azx_dev->bufsize / period_bytes;
1516
1da177e4 1517 /* program the initial BDL entries */
4ce107b9
TI		 1518 bdl = (u32 *)azx_dev->bdl.area;
1519 ofs = 0;
1520 azx_dev->frags = 0;
555e219f 1521 pos_adj = bdl_pos_adj[chip->dev_index];
915bf29e 1522 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
675f25d4 1523 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1524 int pos_align = pos_adj;
555e219f 1525 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1526 if (!pos_adj)
e785d3d8
TI		 1527 pos_adj = pos_align;
1528 else
1529 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1530 pos_align;
675f25d4
TI		 1531 pos_adj = frames_to_bytes(runtime, pos_adj);
1532 if (pos_adj >= period_bytes) {
445a51b3
DB		 1533 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1534 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1535 pos_adj = 0;
1536 } else {
1d1a4564
TI		 1537 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1538 azx_dev,
915bf29e 1539 &bdl, ofs, pos_adj, true);
675f25d4
TI		 1540 if (ofs < 0)
1541 goto error;
4ce107b9 1542 }
555e219f
TI		 1543 } else
1544 pos_adj = 0;
675f25d4
TI		 1545 for (i = 0; i < periods; i++) {
1546 if (i == periods - 1 && pos_adj)
1d1a4564
TI		 1547 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1548 azx_dev, &bdl, ofs,
675f25d4
TI		 1549 period_bytes - pos_adj, 0);
1550 else
1d1a4564
TI		 1551 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1552 azx_dev, &bdl, ofs,
7bb8fb70 1553 period_bytes,
915bf29e 1554 !azx_dev->no_period_wakeup);
675f25d4
TI		 1555 if (ofs < 0)
1556 goto error;
1da177e4 1557 }
4ce107b9 1558 return 0;
675f25d4
TI		 1559
1560 error:
445a51b3
DB		 1561 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1562 pci_name(chip->pci), azx_dev->bufsize, period_bytes);
675f25d4 1563 return -EINVAL;
1da177e4
LT		 1564}
1565
1dddab40
TI		 1566/* reset stream */
1567static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1568{
1569 unsigned char val;
1570 int timeout;
1571
1dddab40
TI		 1572 azx_stream_clear(chip, azx_dev);
1573
d01ce99f
TI		 1574 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1575 SD_CTL_STREAM_RESET);
1da177e4
LT		 1576 udelay(3);
1577 timeout = 300;
1578 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1579 --timeout)
1580 ;
1581 val &= ~SD_CTL_STREAM_RESET;
1582 azx_sd_writeb(azx_dev, SD_CTL, val);
1583 udelay(3);
1584
1585 timeout = 300;
1586 /* waiting for hardware to report that the stream is out of reset */
1587 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1588 --timeout)
1589 ;
fa00e046
JK		 1590
1591 /* reset first position - may not be synced with hw at this time */
1592 *azx_dev->posbuf = 0;
1dddab40 1593}
1da177e4 1594
1dddab40
TI		 1595/*
1596 * set up the SD for streaming
1597 */
1598static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1599{
27fe48d9 1600 unsigned int val;
1dddab40
TI		 1601 /* make sure the run bit is zero for SD */
1602 azx_stream_clear(chip, azx_dev);
1da177e4 1603 /* program the stream_tag */
27fe48d9
TI		 1604 val = azx_sd_readl(azx_dev, SD_CTL);
1605 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1606 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1607 if (!azx_snoop(chip))
1608 val |= SD_CTL_TRAFFIC_PRIO;
1609 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1610
1611 /* program the length of samples in cyclic buffer */
1612 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1613
1614 /* program the stream format */
1615 /* this value needs to be the same as the one programmed */
1616 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1617
1618 /* program the stream LVI (last valid index) of the BDL */
1619 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1620
1621 /* program the BDL address */
1622 /* lower BDL address */
4ce107b9 1623 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1624 /* upper BDL address */
766979e0 1625 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1626
0be3b5d3 1627 /* enable the position buffer */
4cb36310
DH		 1628 if (chip->position_fix[0] != POS_FIX_LPIB ||
1629 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1630 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1631 azx_writel(chip, DPLBASE,
1632 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1633 }
c74db86b 1634
1da177e4 1635 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1636 azx_sd_writel(azx_dev, SD_CTL,
1637 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1638
1639 return 0;
1640}
1641
6ce4a3bc
TI		 1642/*
1643 * Probe the given codec address
1644 */
1645static int probe_codec(struct azx *chip, int addr)
1646{
1647 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1648 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1649 unsigned int res;
1650
a678cdee 1651 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1652 chip->probing = 1;
1653 azx_send_cmd(chip->bus, cmd);
deadff16 1654 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1655 chip->probing = 0;
a678cdee 1656 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1657 if (res == -1)
1658 return -EIO;
445a51b3 1659 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
6ce4a3bc
TI		 1660 return 0;
1661}
1662
33fa35ed
TI		 1663static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1664 struct hda_pcm *cpcm);
6ce4a3bc 1665static void azx_stop_chip(struct azx *chip);
1da177e4 1666
8dd78330
TI		 1667static void azx_bus_reset(struct hda_bus *bus)
1668{
1669 struct azx *chip = bus->private_data;
8dd78330
TI		 1670
1671 bus->in_reset = 1;
1672 azx_stop_chip(chip);
cd508fe5 1673 azx_init_chip(chip, 1);
65f75983 1674#ifdef CONFIG_PM
8dd78330 1675 if (chip->initialized) {
01b65bfb
TI		 1676 struct azx_pcm *p;
1677 list_for_each_entry(p, &chip->pcm_list, list)
1678 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1679 snd_hda_suspend(chip->bus);
1680 snd_hda_resume(chip->bus);
1681 }
65f75983 1682#endif
8dd78330
TI		 1683 bus->in_reset = 0;
1684}
1685
26a6cb6c
DH		 1686static int get_jackpoll_interval(struct azx *chip)
1687{
1688 int i = jackpoll_ms[chip->dev_index];
1689 unsigned int j;
1690 if (i == 0)
1691 return 0;
1692 if (i < 50 || i > 60000)
1693 j = 0;
1694 else
1695 j = msecs_to_jiffies(i);
1696 if (j == 0)
1697 snd_printk(KERN_WARNING SFX
1698 "jackpoll_ms value out of range: %d\n", i);
1699 return j;
1700}
1701
1da177e4
LT		 1702/*
1703 * Codec initialization
1704 */
1705
2f5983f2 1706/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
48c8b0eb 1707static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
7445dfc1 1708 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1709 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1710};
1711
48c8b0eb 1712static int azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1713{
1714 struct hda_bus_template bus_temp;
34c25350
TI		 1715 int c, codecs, err;
1716 int max_slots;
1da177e4
LT		 1717
1718 memset(&bus_temp, 0, sizeof(bus_temp));
1719 bus_temp.private_data = chip;
1720 bus_temp.modelname = model;
1721 bus_temp.pci = chip->pci;
111d3af5
TI		 1722 bus_temp.ops.command = azx_send_cmd;
1723 bus_temp.ops.get_response = azx_get_response;
176d5335 1724 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1725 bus_temp.ops.bus_reset = azx_bus_reset;
83012a7c 1726#ifdef CONFIG_PM
11cd41b8 1727 bus_temp.power_save = &power_save;
cb53c626
TI		 1728 bus_temp.ops.pm_notify = azx_power_notify;
1729#endif
1d1a4564
TI		 1730#ifdef CONFIG_SND_HDA_DSP_LOADER
1731 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1732 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1733 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1734#endif
1da177e4 1735
d01ce99f
TI		 1736 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1737 if (err < 0)
1da177e4
LT		 1738 return err;
1739
9477c58e 1740 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
445a51b3 1741 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
dc9c8e21 1742 chip->bus->needs_damn_long_delay = 1;
9477c58e 1743 }
dc9c8e21 1744
34c25350 1745 codecs = 0;
2f5983f2
TI		 1746 max_slots = azx_max_codecs[chip->driver_type];
1747 if (!max_slots)
7445dfc1 1748 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1749
1750 /* First try to probe all given codec slots */
1751 for (c = 0; c < max_slots; c++) {
f1eaaeec 1752 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1753 if (probe_codec(chip, c) < 0) {
1754 /* Some BIOSen give you wrong codec addresses
1755 * that don't exist
1756 */
4abc1cc2 1757 snd_printk(KERN_WARNING SFX
445a51b3
DB		 1758 "%s: Codec #%d probe error; "
1759 "disabling it...\n", pci_name(chip->pci), c);
6ce4a3bc
TI		 1760 chip->codec_mask &= ~(1 << c);
1761 /* More badly, accessing to a non-existing
1762 * codec often screws up the controller chip,
2448158e 1763 * and disturbs the further communications.
6ce4a3bc
TI		 1764 * Thus if an error occurs during probing,
1765 * better to reset the controller chip to
1766 * get back to the sanity state.
1767 */
1768 azx_stop_chip(chip);
cd508fe5 1769 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1770 }
1771 }
1772 }
1773
d507cd66
TI		 1774 /* AMD chipsets often cause the communication stalls upon certain
1775 * sequence like the pin-detection. It seems that forcing the synced
1776 * access works around the stall. Grrr...
1777 */
9477c58e 1778 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
445a51b3
DB		 1779 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1780 pci_name(chip->pci));
d507cd66
TI		 1781 chip->bus->sync_write = 1;
1782 chip->bus->allow_bus_reset = 1;
1783 }
1784
6ce4a3bc 1785 /* Then create codec instances */
34c25350 1786 for (c = 0; c < max_slots; c++) {
f1eaaeec 1787 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1788 struct hda_codec *codec;
a1e21c90 1789 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1790 if (err < 0)
1791 continue;
26a6cb6c 1792 codec->jackpoll_interval = get_jackpoll_interval(chip);
2dca0bba 1793 codec->beep_mode = chip->beep_mode;
1da177e4 1794 codecs++;
19a982b6
TI		 1795 }
1796 }
1797 if (!codecs) {
445a51b3 1798 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1da177e4
LT		 1799 return -ENXIO;
1800 }
a1e21c90
TI		 1801 return 0;
1802}
1da177e4 1803
a1e21c90 1804/* configure each codec instance */
e23e7a14 1805static int azx_codec_configure(struct azx *chip)
a1e21c90
TI		 1806{
1807 struct hda_codec *codec;
1808 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1809 snd_hda_codec_configure(codec);
1810 }
1da177e4
LT		 1811 return 0;
1812}
1813
1814
1815/*
1816 * PCM support
1817 */
1818
1819/* assign a stream for the PCM */
ef18bede
WF		 1820static inline struct azx_dev *
1821azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1822{
07e4ca50 1823 int dev, i, nums;
ef18bede 1824 struct azx_dev *res = NULL;
d5cf9911
TI		 1825 /* make a non-zero unique key for the substream */
1826 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1827 (substream->stream + 1);
ef18bede
WF		 1828
1829 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1830 dev = chip->playback_index_offset;
1831 nums = chip->playback_streams;
1832 } else {
1833 dev = chip->capture_index_offset;
1834 nums = chip->capture_streams;
1835 }
eb49faa6
TI		 1836 for (i = 0; i < nums; i++, dev++) {
1837 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1838 dsp_lock(azx_dev);
1839 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1840 res = azx_dev;
1841 if (res->assigned_key == key) {
1842 res->opened = 1;
1843 res->assigned_key = key;
1844 dsp_unlock(azx_dev);
1845 return azx_dev;
1846 }
1da177e4 1847 }
eb49faa6
TI		 1848 dsp_unlock(azx_dev);
1849 }
ef18bede 1850 if (res) {
eb49faa6 1851 dsp_lock(res);
ef18bede 1852 res->opened = 1;
d5cf9911 1853 res->assigned_key = key;
eb49faa6 1854 dsp_unlock(res);
ef18bede
WF		 1855 }
1856 return res;
1da177e4
LT		 1857}
1858
1859/* release the assigned stream */
a98f90fd 1860static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1861{
1862 azx_dev->opened = 0;
1863}
1864
5d890f59
PLB		 1865static cycle_t azx_cc_read(const struct cyclecounter *cc)
1866{
1867 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1868 struct snd_pcm_substream *substream = azx_dev->substream;
1869 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1870 struct azx *chip = apcm->chip;
1871
1872 return azx_readl(chip, WALLCLK);
1873}
1874
1875static void azx_timecounter_init(struct snd_pcm_substream *substream,
1876 bool force, cycle_t last)
1877{
1878 struct azx_dev *azx_dev = get_azx_dev(substream);
1879 struct timecounter *tc = &azx_dev->azx_tc;
1880 struct cyclecounter *cc = &azx_dev->azx_cc;
1881 u64 nsec;
1882
1883 cc->read = azx_cc_read;
1884 cc->mask = CLOCKSOURCE_MASK(32);
1885
1886 /*
1887 * Converting from 24 MHz to ns means applying a 125/3 factor.
1888 * To avoid any saturation issues in intermediate operations,
1889 * the 125 factor is applied first. The division is applied
1890 * last after reading the timecounter value.
1891 * Applying the 1/3 factor as part of the multiplication
1892 * requires at least 20 bits for a decent precision, however
1893 * overflows occur after about 4 hours or less, not a option.
1894 */
1895
1896 cc->mult = 125; /* saturation after 195 years */
1897 cc->shift = 0;
1898
1899 nsec = 0; /* audio time is elapsed time since trigger */
1900 timecounter_init(tc, cc, nsec);
1901 if (force)
1902 /*
1903 * force timecounter to use predefined value,
1904 * used for synchronized starts
1905 */
1906 tc->cycle_last = last;
1907}
1908
ae03bbb8 1909static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
78daea29
DR		 1910 u64 nsec)
1911{
1912 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1913 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1914 u64 codec_frames, codec_nsecs;
1915
1916 if (!hinfo->ops.get_delay)
1917 return nsec;
1918
1919 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1920 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1921 substream->runtime->rate);
1922
ae03bbb8
DR		 1923 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1924 return nsec + codec_nsecs;
1925
78daea29
DR		 1926 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1927}
1928
5d890f59
PLB		 1929static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1930 struct timespec *ts)
1931{
1932 struct azx_dev *azx_dev = get_azx_dev(substream);
1933 u64 nsec;
1934
1935 nsec = timecounter_read(&azx_dev->azx_tc);
1936 nsec = div_u64(nsec, 3); /* can be optimized */
ae03bbb8 1937 nsec = azx_adjust_codec_delay(substream, nsec);
5d890f59
PLB		 1938
1939 *ts = ns_to_timespec(nsec);
1940
1941 return 0;
1942}
1943
a98f90fd 1944static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1945 .info = (SNDRV_PCM_INFO_MMAP |
1946 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1947 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1948 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1949 /* No full-resume yet implemented */
1950 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1951 SNDRV_PCM_INFO_PAUSE |
7bb8fb70 1952 SNDRV_PCM_INFO_SYNC_START |
5d890f59 1953 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
7bb8fb70 1954 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1955 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1956 .rates = SNDRV_PCM_RATE_48000,
1957 .rate_min = 48000,
1958 .rate_max = 48000,
1959 .channels_min = 2,
1960 .channels_max = 2,
1961 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1962 .period_bytes_min = 128,
1963 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1964 .periods_min = 2,
1965 .periods_max = AZX_MAX_FRAG,
1966 .fifo_size = 0,
1967};
1968
a98f90fd 1969static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1970{
1971 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1972 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1973 struct azx *chip = apcm->chip;
1974 struct azx_dev *azx_dev;
1975 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1976 unsigned long flags;
1977 int err;
2ae66c26 1978 int buff_step;
1da177e4 1979
62932df8 1980 mutex_lock(&chip->open_mutex);
ef18bede 1981 azx_dev = azx_assign_device(chip, substream);
1da177e4 1982 if (azx_dev == NULL) {
62932df8 1983 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1984 return -EBUSY;
1985 }
1986 runtime->hw = azx_pcm_hw;
1987 runtime->hw.channels_min = hinfo->channels_min;
1988 runtime->hw.channels_max = hinfo->channels_max;
1989 runtime->hw.formats = hinfo->formats;
1990 runtime->hw.rates = hinfo->rates;
1991 snd_pcm_limit_hw_rates(runtime);
1992 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5d890f59
PLB		 1993
1994 /* avoid wrap-around with wall-clock */
1995 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1996 20,
1997 178000000);
1998
52409aa6 1999 if (chip->align_buffer_size)
2ae66c26
PLB		 2000 /* constrain buffer sizes to be multiple of 128
2001 bytes. This is more efficient in terms of memory
2002 access but isn't required by the HDA spec and
2003 prevents users from specifying exact period/buffer
2004 sizes. For example for 44.1kHz, a period size set
2005 to 20ms will be rounded to 19.59ms. */
2006 buff_step = 128;
2007 else
2008 /* Don't enforce steps on buffer sizes, still need to
2009 be multiple of 4 bytes (HDA spec). Tested on Intel
2010 HDA controllers, may not work on all devices where
2011 option needs to be disabled */
2012 buff_step = 4;
2013
5f1545bc 2014 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 2015 buff_step);
5f1545bc 2016 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 2017 buff_step);
b4a91cf0 2018 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 2019 err = hinfo->ops.open(hinfo, apcm->codec, substream);
2020 if (err < 0) {
1da177e4 2021 azx_release_device(azx_dev);
cb53c626 2022 snd_hda_power_down(apcm->codec);
62932df8 2023 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2024 return err;
2025 }
70d321e6 2026 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 2027 /* sanity check */
2028 if (snd_BUG_ON(!runtime->hw.channels_min) ||
2029 snd_BUG_ON(!runtime->hw.channels_max) ||
2030 snd_BUG_ON(!runtime->hw.formats) ||
2031 snd_BUG_ON(!runtime->hw.rates)) {
2032 azx_release_device(azx_dev);
2033 hinfo->ops.close(hinfo, apcm->codec, substream);
2034 snd_hda_power_down(apcm->codec);
2035 mutex_unlock(&chip->open_mutex);
2036 return -EINVAL;
2037 }
5d890f59
PLB		 2038
2039 /* disable WALLCLOCK timestamps for capture streams
2040 until we figure out how to handle digital inputs */
2041 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2042 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2043
1da177e4
LT		 2044 spin_lock_irqsave(&chip->reg_lock, flags);
2045 azx_dev->substream = substream;
2046 azx_dev->running = 0;
2047 spin_unlock_irqrestore(&chip->reg_lock, flags);
2048
2049 runtime->private_data = azx_dev;
850f0e52 2050 snd_pcm_set_sync(substream);
62932df8 2051 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2052 return 0;
2053}
2054
a98f90fd 2055static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 2056{
2057 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2058 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 2059 struct azx *chip = apcm->chip;
2060 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 2061 unsigned long flags;
2062
62932df8 2063 mutex_lock(&chip->open_mutex);
1da177e4
LT		 2064 spin_lock_irqsave(&chip->reg_lock, flags);
2065 azx_dev->substream = NULL;
2066 azx_dev->running = 0;
2067 spin_unlock_irqrestore(&chip->reg_lock, flags);
2068 azx_release_device(azx_dev);
2069 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 2070 snd_hda_power_down(apcm->codec);
62932df8 2071 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2072 return 0;
2073}
2074
d01ce99f
TI		 2075static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2076 struct snd_pcm_hw_params *hw_params)
1da177e4 2077{
27fe48d9
TI		 2078 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2079 struct azx *chip = apcm->chip;
97b71c94 2080 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 2081 int ret;
97b71c94 2082
eb49faa6
TI		 2083 dsp_lock(azx_dev);
2084 if (dsp_is_locked(azx_dev)) {
2085 ret = -EBUSY;
2086 goto unlock;
2087 }
2088
9ddf1aeb 2089 mark_runtime_wc(chip, azx_dev, substream, false);
97b71c94
TI		 2090 azx_dev->bufsize = 0;
2091 azx_dev->period_bytes = 0;
2092 azx_dev->format_val = 0;
27fe48d9 2093 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 2094 params_buffer_bytes(hw_params));
27fe48d9 2095 if (ret < 0)
eb49faa6 2096 goto unlock;
9ddf1aeb 2097 mark_runtime_wc(chip, azx_dev, substream, true);
eb49faa6
TI		 2098 unlock:
2099 dsp_unlock(azx_dev);
27fe48d9 2100 return ret;
1da177e4
LT		 2101}
2102
a98f90fd 2103static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 2104{
2105 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2106 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 2107 struct azx *chip = apcm->chip;
1da177e4
LT		 2108 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2109
2110 /* reset BDL address */
eb49faa6
TI		 2111 dsp_lock(azx_dev);
2112 if (!dsp_is_locked(azx_dev)) {
2113 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2114 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2115 azx_sd_writel(azx_dev, SD_CTL, 0);
2116 azx_dev->bufsize = 0;
2117 azx_dev->period_bytes = 0;
2118 azx_dev->format_val = 0;
2119 }
1da177e4 2120
eb541337 2121 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 2122
9ddf1aeb 2123 mark_runtime_wc(chip, azx_dev, substream, false);
eb49faa6
TI		 2124 azx_dev->prepared = 0;
2125 dsp_unlock(azx_dev);
1da177e4
LT		 2126 return snd_pcm_lib_free_pages(substream);
2127}
2128
a98f90fd 2129static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 2130{
2131 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 2132 struct azx *chip = apcm->chip;
2133 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 2134 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 2135 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 2136 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 2137 int err;
7c935976
SW		 2138 struct hda_spdif_out *spdif =
2139 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2140 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 2141
eb49faa6
TI		 2142 dsp_lock(azx_dev);
2143 if (dsp_is_locked(azx_dev)) {
2144 err = -EBUSY;
2145 goto unlock;
2146 }
2147
fa00e046 2148 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 2149 format_val = snd_hda_calc_stream_format(runtime->rate,
2150 runtime->channels,
2151 runtime->format,
32c168c8 2152 hinfo->maxbps,
7c935976 2153 ctls);
97b71c94 2154 if (!format_val) {
d01ce99f 2155 snd_printk(KERN_ERR SFX
445a51b3
DB		 2156 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2157 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
eb49faa6
TI		 2158 err = -EINVAL;
2159 goto unlock;
1da177e4
LT		 2160 }
2161
97b71c94
TI		 2162 bufsize = snd_pcm_lib_buffer_bytes(substream);
2163 period_bytes = snd_pcm_lib_period_bytes(substream);
2164
445a51b3
DB		 2165 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2166 pci_name(chip->pci), bufsize, format_val);
97b71c94
TI		 2167
2168 if (bufsize != azx_dev->bufsize ||
2169 period_bytes != azx_dev->period_bytes ||
915bf29e
TI		 2170 format_val != azx_dev->format_val ||
2171 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
97b71c94
TI		 2172 azx_dev->bufsize = bufsize;
2173 azx_dev->period_bytes = period_bytes;
2174 azx_dev->format_val = format_val;
915bf29e 2175 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
97b71c94
TI		 2176 err = azx_setup_periods(chip, substream, azx_dev);
2177 if (err < 0)
eb49faa6 2178 goto unlock;
97b71c94
TI		 2179 }
2180
e5463720
JK		 2181 /* wallclk has 24Mhz clock source */
2182 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2183 runtime->rate) * 1000);
1da177e4
LT		 2184 azx_setup_controller(chip, azx_dev);
2185 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2186 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2187 else
2188 azx_dev->fifo_size = 0;
2189
62b7e5e0
TI		 2190 stream_tag = azx_dev->stream_tag;
2191 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 2192 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 2193 stream_tag > chip->capture_streams)
2194 stream_tag -= chip->capture_streams;
eb49faa6 2195 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 2196 azx_dev->format_val, substream);
eb49faa6
TI		 2197
2198 unlock:
2199 if (!err)
2200 azx_dev->prepared = 1;
2201 dsp_unlock(azx_dev);
2202 return err;
1da177e4
LT		 2203}
2204
a98f90fd 2205static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 2206{
2207 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2208 struct azx *chip = apcm->chip;
850f0e52
TI		 2209 struct azx_dev *azx_dev;
2210 struct snd_pcm_substream *s;
fa00e046 2211 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 2212 int nwait, timeout;
1da177e4 2213
1a8506d4
TI		 2214 azx_dev = get_azx_dev(substream);
2215 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2216
eb49faa6
TI		 2217 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2218 return -EPIPE;
2219
1da177e4 2220 switch (cmd) {
fa00e046
JK		 2221 case SNDRV_PCM_TRIGGER_START:
2222 rstart = 1;
1da177e4
LT		 2223 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2224 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 2225 start = 1;
1da177e4
LT		 2226 break;
2227 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 2228 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 2229 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 2230 start = 0;
1da177e4
LT		 2231 break;
2232 default:
850f0e52
TI		 2233 return -EINVAL;
2234 }
2235
2236 snd_pcm_group_for_each_entry(s, substream) {
2237 if (s->pcm->card != substream->pcm->card)
2238 continue;
2239 azx_dev = get_azx_dev(s);
2240 sbits |= 1 << azx_dev->index;
2241 nsync++;
2242 snd_pcm_trigger_done(s, substream);
2243 }
2244
2245 spin_lock(&chip->reg_lock);
172d3b20
PLB		 2246
2247 /* first, set SYNC bits of corresponding streams */
2248 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2249 azx_writel(chip, OLD_SSYNC,
2250 azx_readl(chip, OLD_SSYNC) | sbits);
2251 else
2252 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2253
850f0e52
TI		 2254 snd_pcm_group_for_each_entry(s, substream) {
2255 if (s->pcm->card != substream->pcm->card)
2256 continue;
2257 azx_dev = get_azx_dev(s);
e5463720
JK		 2258 if (start) {
2259 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2260 if (!rstart)
2261 azx_dev->start_wallclk -=
2262 azx_dev->period_wallclk;
850f0e52 2263 azx_stream_start(chip, azx_dev);
e5463720 2264 } else {
850f0e52 2265 azx_stream_stop(chip, azx_dev);
e5463720 2266 }
850f0e52 2267 azx_dev->running = start;
1da177e4
LT		 2268 }
2269 spin_unlock(&chip->reg_lock);
850f0e52 2270 if (start) {
850f0e52
TI		 2271 /* wait until all FIFOs get ready */
2272 for (timeout = 5000; timeout; timeout--) {
2273 nwait = 0;
2274 snd_pcm_group_for_each_entry(s, substream) {
2275 if (s->pcm->card != substream->pcm->card)
2276 continue;
2277 azx_dev = get_azx_dev(s);
2278 if (!(azx_sd_readb(azx_dev, SD_STS) &
2279 SD_STS_FIFO_READY))
2280 nwait++;
2281 }
2282 if (!nwait)
2283 break;
2284 cpu_relax();
2285 }
2286 } else {
2287 /* wait until all RUN bits are cleared */
2288 for (timeout = 5000; timeout; timeout--) {
2289 nwait = 0;
2290 snd_pcm_group_for_each_entry(s, substream) {
2291 if (s->pcm->card != substream->pcm->card)
2292 continue;
2293 azx_dev = get_azx_dev(s);
2294 if (azx_sd_readb(azx_dev, SD_CTL) &
2295 SD_CTL_DMA_START)
2296 nwait++;
2297 }
2298 if (!nwait)
2299 break;
2300 cpu_relax();
2301 }
1da177e4 2302 }
172d3b20
PLB		 2303 spin_lock(&chip->reg_lock);
2304 /* reset SYNC bits */
2305 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2306 azx_writel(chip, OLD_SSYNC,
2307 azx_readl(chip, OLD_SSYNC) & ~sbits);
2308 else
2309 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
5d890f59
PLB		 2310 if (start) {
2311 azx_timecounter_init(substream, 0, 0);
2312 if (nsync > 1) {
2313 cycle_t cycle_last;
2314
2315 /* same start cycle for master and group */
2316 azx_dev = get_azx_dev(substream);
2317 cycle_last = azx_dev->azx_tc.cycle_last;
2318
2319 snd_pcm_group_for_each_entry(s, substream) {
2320 if (s->pcm->card != substream->pcm->card)
2321 continue;
2322 azx_timecounter_init(s, 1, cycle_last);
2323 }
2324 }
2325 }
172d3b20 2326 spin_unlock(&chip->reg_lock);
850f0e52 2327 return 0;
1da177e4
LT		 2328}
2329
0e153474
JC		 2330/* get the current DMA position with correction on VIA chips */
2331static unsigned int azx_via_get_position(struct azx *chip,
2332 struct azx_dev *azx_dev)
2333{
2334 unsigned int link_pos, mini_pos, bound_pos;
2335 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2336 unsigned int fifo_size;
2337
2338 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2339 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2340 /* Playback, no problem using link position */
2341 return link_pos;
2342 }
2343
2344 /* Capture */
2345 /* For new chipset,
2346 * use mod to get the DMA position just like old chipset
2347 */
2348 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2349 mod_dma_pos %= azx_dev->period_bytes;
2350
2351 /* azx_dev->fifo_size can't get FIFO size of in stream.
2352 * Get from base address + offset.
2353 */
2354 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2355
2356 if (azx_dev->insufficient) {
2357 /* Link position never gather than FIFO size */
2358 if (link_pos <= fifo_size)
2359 return 0;
2360
2361 azx_dev->insufficient = 0;
2362 }
2363
2364 if (link_pos <= fifo_size)
2365 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2366 else
2367 mini_pos = link_pos - fifo_size;
2368
2369 /* Find nearest previous boudary */
2370 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2371 mod_link_pos = link_pos % azx_dev->period_bytes;
2372 if (mod_link_pos >= fifo_size)
2373 bound_pos = link_pos - mod_link_pos;
2374 else if (mod_dma_pos >= mod_mini_pos)
2375 bound_pos = mini_pos - mod_mini_pos;
2376 else {
2377 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2378 if (bound_pos >= azx_dev->bufsize)
2379 bound_pos = 0;
2380 }
2381
2382 /* Calculate real DMA position we want */
2383 return bound_pos + mod_dma_pos;
2384}
2385
9ad593f6 2386static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2387 struct azx_dev *azx_dev,
2388 bool with_check)
1da177e4 2389{
21229613
TI		 2390 struct snd_pcm_substream *substream = azx_dev->substream;
2391 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1da177e4 2392 unsigned int pos;
21229613
TI		 2393 int stream = substream->stream;
2394 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
1a8506d4 2395 int delay = 0;
1da177e4 2396
4cb36310
DH		 2397 switch (chip->position_fix[stream]) {
2398 case POS_FIX_LPIB:
2399 /* read LPIB */
2400 pos = azx_sd_readl(azx_dev, SD_LPIB);
2401 break;
2402 case POS_FIX_VIACOMBO:
0e153474 2403 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2404 break;
2405 default:
2406 /* use the position buffer */
2407 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2408 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2409 if (!pos || pos == (u32)-1) {
2410 printk(KERN_WARNING
2411 "hda-intel: Invalid position buffer, "
2412 "using LPIB read method instead.\n");
2413 chip->position_fix[stream] = POS_FIX_LPIB;
2414 pos = azx_sd_readl(azx_dev, SD_LPIB);
2415 } else
2416 chip->position_fix[stream] = POS_FIX_POSBUF;
2417 }
2418 break;
c74db86b 2419 }
4cb36310 2420
1da177e4
LT		 2421 if (pos >= azx_dev->bufsize)
2422 pos = 0;
90accc58
PLB		 2423
2424 /* calculate runtime delay from LPIB */
21229613 2425 if (substream->runtime &&
90accc58
PLB		 2426 chip->position_fix[stream] == POS_FIX_POSBUF &&
2427 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2428 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
90accc58
PLB		 2429 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2430 delay = pos - lpib_pos;
2431 else
2432 delay = lpib_pos - pos;
2433 if (delay < 0)
2434 delay += azx_dev->bufsize;
2435 if (delay >= azx_dev->period_bytes) {
1f04661f 2436 snd_printk(KERN_WARNING SFX
445a51b3 2437 "%s: Unstable LPIB (%d >= %d); "
1f04661f 2438 "disabling LPIB delay counting\n",
445a51b3 2439 pci_name(chip->pci), delay, azx_dev->period_bytes);
1f04661f
TI		 2440 delay = 0;
2441 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
90accc58 2442 }
21229613 2443 delay = bytes_to_frames(substream->runtime, delay);
90accc58 2444 }
21229613
TI		 2445
2446 if (substream->runtime) {
2447 if (hinfo->ops.get_delay)
2448 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2449 substream);
2450 substream->runtime->delay = delay;
2451 }
2452
1a8506d4 2453 trace_azx_get_position(chip, azx_dev, pos, delay);
9ad593f6
TI		 2454 return pos;
2455}
2456
2457static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2458{
2459 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2460 struct azx *chip = apcm->chip;
2461 struct azx_dev *azx_dev = get_azx_dev(substream);
2462 return bytes_to_frames(substream->runtime,
798cb7e8 2463 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2464}
2465
2466/*
2467 * Check whether the current DMA position is acceptable for updating
2468 * periods. Returns non-zero if it's OK.
2469 *
2470 * Many HD-audio controllers appear pretty inaccurate about
2471 * the update-IRQ timing. The IRQ is issued before actually the
2472 * data is processed. So, we need to process it afterwords in a
2473 * workqueue.
2474 */
2475static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2476{
e5463720 2477 u32 wallclk;
9ad593f6
TI		 2478 unsigned int pos;
2479
f48f606d
JK		 2480 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2481 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2482 return -1; /* bogus (too early) interrupt */
fa00e046 2483
798cb7e8 2484 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2485
d6d8bf54
TI		 2486 if (WARN_ONCE(!azx_dev->period_bytes,
2487 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2488 return -1; /* this shouldn't happen! */
edb39935 2489 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2490 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2491 /* NG - it's below the first next period boundary */
2492 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2493 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2494 return 1; /* OK, it's fine */
2495}
2496
2497/*
2498 * The work for pending PCM period updates.
2499 */
2500static void azx_irq_pending_work(struct work_struct *work)
2501{
2502 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2503 int i, pending, ok;
9ad593f6 2504
a6a950a8
TI		 2505 if (!chip->irq_pending_warned) {
2506 printk(KERN_WARNING
2507 "hda-intel: IRQ timing workaround is activated "
2508 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2509 chip->card->number);
2510 chip->irq_pending_warned = 1;
2511 }
2512
9ad593f6
TI		 2513 for (;;) {
2514 pending = 0;
2515 spin_lock_irq(&chip->reg_lock);
2516 for (i = 0; i < chip->num_streams; i++) {
2517 struct azx_dev *azx_dev = &chip->azx_dev[i];
2518 if (!azx_dev->irq_pending ||
2519 !azx_dev->substream ||
2520 !azx_dev->running)
2521 continue;
e5463720
JK		 2522 ok = azx_position_ok(chip, azx_dev);
2523 if (ok > 0) {
9ad593f6
TI		 2524 azx_dev->irq_pending = 0;
2525 spin_unlock(&chip->reg_lock);
2526 snd_pcm_period_elapsed(azx_dev->substream);
2527 spin_lock(&chip->reg_lock);
e5463720
JK		 2528 } else if (ok < 0) {
2529 pending = 0; /* too early */
9ad593f6
TI		 2530 } else
2531 pending++;
2532 }
2533 spin_unlock_irq(&chip->reg_lock);
2534 if (!pending)
2535 return;
08af495f 2536 msleep(1);
9ad593f6
TI		 2537 }
2538}
2539
2540/* clear irq_pending flags and assure no on-going workq */
2541static void azx_clear_irq_pending(struct azx *chip)
2542{
2543 int i;
2544
2545 spin_lock_irq(&chip->reg_lock);
2546 for (i = 0; i < chip->num_streams; i++)
2547 chip->azx_dev[i].irq_pending = 0;
2548 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2549}
2550
27fe48d9
TI		 2551#ifdef CONFIG_X86
2552static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2553 struct vm_area_struct *area)
2554{
2555 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2556 struct azx *chip = apcm->chip;
2557 if (!azx_snoop(chip))
2558 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2559 return snd_pcm_lib_default_mmap(substream, area);
2560}
2561#else
2562#define azx_pcm_mmap NULL
2563#endif
2564
a98f90fd 2565static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2566 .open = azx_pcm_open,
2567 .close = azx_pcm_close,
2568 .ioctl = snd_pcm_lib_ioctl,
2569 .hw_params = azx_pcm_hw_params,
2570 .hw_free = azx_pcm_hw_free,
2571 .prepare = azx_pcm_prepare,
2572 .trigger = azx_pcm_trigger,
2573 .pointer = azx_pcm_pointer,
5d890f59 2574 .wall_clock = azx_get_wallclock_tstamp,
27fe48d9 2575 .mmap = azx_pcm_mmap,
4ce107b9 2576 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2577};
2578
a98f90fd 2579static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2580{
176d5335
TI		 2581 struct azx_pcm *apcm = pcm->private_data;
2582 if (apcm) {
01b65bfb 2583 list_del(&apcm->list);
176d5335
TI		 2584 kfree(apcm);
2585 }
1da177e4
LT		 2586}
2587
acfa634f
TI		 2588#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2589
176d5335 2590static int
33fa35ed
TI		 2591azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2592 struct hda_pcm *cpcm)
1da177e4 2593{
33fa35ed 2594 struct azx *chip = bus->private_data;
a98f90fd 2595 struct snd_pcm *pcm;
1da177e4 2596 struct azx_pcm *apcm;
176d5335 2597 int pcm_dev = cpcm->device;
acfa634f 2598 unsigned int size;
176d5335 2599 int s, err;
1da177e4 2600
01b65bfb
TI		 2601 list_for_each_entry(apcm, &chip->pcm_list, list) {
2602 if (apcm->pcm->device == pcm_dev) {
445a51b3
DB		 2603 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2604 pci_name(chip->pci), pcm_dev);
01b65bfb
TI		 2605 return -EBUSY;
2606 }
176d5335
TI		 2607 }
2608 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2609 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2610 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2611 &pcm);
2612 if (err < 0)
2613 return err;
18cb7109 2614 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2615 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2616 if (apcm == NULL)
2617 return -ENOMEM;
2618 apcm->chip = chip;
01b65bfb 2619 apcm->pcm = pcm;
1da177e4 2620 apcm->codec = codec;
1da177e4
LT		 2621 pcm->private_data = apcm;
2622 pcm->private_free = azx_pcm_free;
176d5335
TI		 2623 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2624 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2625 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2626 cpcm->pcm = pcm;
2627 for (s = 0; s < 2; s++) {
2628 apcm->hinfo[s] = &cpcm->stream[s];
2629 if (cpcm->stream[s].substreams)
2630 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2631 }
2632 /* buffer pre-allocation */
acfa634f
TI		 2633 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2634 if (size > MAX_PREALLOC_SIZE)
2635 size = MAX_PREALLOC_SIZE;
4ce107b9 2636 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2637 snd_dma_pci_data(chip->pci),
acfa634f 2638 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2639 return 0;
2640}
2641
2642/*
2643 * mixer creation - all stuff is implemented in hda module
2644 */
e23e7a14 2645static int azx_mixer_create(struct azx *chip)
1da177e4
LT		 2646{
2647 return snd_hda_build_controls(chip->bus);
2648}
2649
2650
2651/*
2652 * initialize SD streams
2653 */
e23e7a14 2654static int azx_init_stream(struct azx *chip)
1da177e4
LT		 2655{
2656 int i;
2657
2658 /* initialize each stream (aka device)
d01ce99f
TI		 2659 * assign the starting bdl address to each stream (device)
2660 * and initialize
1da177e4 2661 */
07e4ca50 2662 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2663 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2664 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2665 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2666 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2667 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2668 azx_dev->sd_int_sta_mask = 1 << i;
2669 /* stream tag: must be non-zero and unique */
2670 azx_dev->index = i;
2671 azx_dev->stream_tag = i + 1;
2672 }
2673
2674 return 0;
2675}
2676
68e7fffc
TI		 2677static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2678{
437a5a46
TI		 2679 if (request_irq(chip->pci->irq, azx_interrupt,
2680 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2681 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2682 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2683 "disabling device\n", chip->pci->irq);
2684 if (do_disconnect)
2685 snd_card_disconnect(chip->card);
2686 return -1;
2687 }
2688 chip->irq = chip->pci->irq;
69e13418 2689 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2690 return 0;
2691}
2692
1da177e4 2693
cb53c626
TI		 2694static void azx_stop_chip(struct azx *chip)
2695{
95e99fda 2696 if (!chip->initialized)
cb53c626
TI		 2697 return;
2698
2699 /* disable interrupts */
2700 azx_int_disable(chip);
2701 azx_int_clear(chip);
2702
2703 /* disable CORB/RIRB */
2704 azx_free_cmd_io(chip);
2705
2706 /* disable position buffer */
2707 azx_writel(chip, DPLBASE, 0);
2708 azx_writel(chip, DPUBASE, 0);
2709
2710 chip->initialized = 0;
2711}
2712
1d1a4564
TI		 2713#ifdef CONFIG_SND_HDA_DSP_LOADER
2714/*
2715 * DSP loading code (e.g. for CA0132)
2716 */
2717
2718/* use the first stream for loading DSP */
2719static struct azx_dev *
2720azx_get_dsp_loader_dev(struct azx *chip)
2721{
2722 return &chip->azx_dev[chip->playback_index_offset];
2723}
2724
2725static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2726 unsigned int byte_size,
2727 struct snd_dma_buffer *bufp)
2728{
2729 u32 *bdl;
2730 struct azx *chip = bus->private_data;
2731 struct azx_dev *azx_dev;
2732 int err;
2733
eb49faa6
TI		 2734 azx_dev = azx_get_dsp_loader_dev(chip);
2735
2736 dsp_lock(azx_dev);
2737 spin_lock_irq(&chip->reg_lock);
2738 if (azx_dev->running || azx_dev->locked) {
2739 spin_unlock_irq(&chip->reg_lock);
2740 err = -EBUSY;
2741 goto unlock;
2742 }
2743 azx_dev->prepared = 0;
2744 chip->saved_azx_dev = *azx_dev;
2745 azx_dev->locked = 1;
2746 spin_unlock_irq(&chip->reg_lock);
1d1a4564
TI		 2747
2748 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2749 snd_dma_pci_data(chip->pci),
2750 byte_size, bufp);
2751 if (err < 0)
eb49faa6 2752 goto err_alloc;
1d1a4564 2753
b3667bd7 2754 mark_pages_wc(chip, bufp, true);
1d1a4564
TI		 2755 azx_dev->bufsize = byte_size;
2756 azx_dev->period_bytes = byte_size;
2757 azx_dev->format_val = format;
2758
2759 azx_stream_reset(chip, azx_dev);
2760
2761 /* reset BDL address */
2762 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2763 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2764
2765 azx_dev->frags = 0;
2766 bdl = (u32 *)azx_dev->bdl.area;
2767 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2768 if (err < 0)
2769 goto error;
2770
2771 azx_setup_controller(chip, azx_dev);
eb49faa6 2772 dsp_unlock(azx_dev);
1d1a4564
TI		 2773 return azx_dev->stream_tag;
2774
2775 error:
b3667bd7
TI		 2776 mark_pages_wc(chip, bufp, false);
2777 snd_dma_free_pages(bufp);
eb49faa6
TI		 2778 err_alloc:
2779 spin_lock_irq(&chip->reg_lock);
2780 if (azx_dev->opened)
2781 *azx_dev = chip->saved_azx_dev;
2782 azx_dev->locked = 0;
2783 spin_unlock_irq(&chip->reg_lock);
2784 unlock:
2785 dsp_unlock(azx_dev);
1d1a4564
TI		 2786 return err;
2787}
2788
2789static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2790{
2791 struct azx *chip = bus->private_data;
2792 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2793
2794 if (start)
2795 azx_stream_start(chip, azx_dev);
2796 else
2797 azx_stream_stop(chip, azx_dev);
2798 azx_dev->running = start;
2799}
2800
2801static void azx_load_dsp_cleanup(struct hda_bus *bus,
2802 struct snd_dma_buffer *dmab)
2803{
2804 struct azx *chip = bus->private_data;
2805 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2806
eb49faa6 2807 if (!dmab->area || !azx_dev->locked)
b3667bd7
TI		 2808 return;
2809
eb49faa6 2810 dsp_lock(azx_dev);
1d1a4564
TI		 2811 /* reset BDL address */
2812 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2813 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2814 azx_sd_writel(azx_dev, SD_CTL, 0);
2815 azx_dev->bufsize = 0;
2816 azx_dev->period_bytes = 0;
2817 azx_dev->format_val = 0;
2818
b3667bd7 2819 mark_pages_wc(chip, dmab, false);
1d1a4564 2820 snd_dma_free_pages(dmab);
b3667bd7 2821 dmab->area = NULL;
1d1a4564 2822
eb49faa6
TI		 2823 spin_lock_irq(&chip->reg_lock);
2824 if (azx_dev->opened)
2825 *azx_dev = chip->saved_azx_dev;
2826 azx_dev->locked = 0;
2827 spin_unlock_irq(&chip->reg_lock);
2828 dsp_unlock(azx_dev);
1d1a4564
TI		 2829}
2830#endif /* CONFIG_SND_HDA_DSP_LOADER */
2831
83012a7c 2832#ifdef CONFIG_PM
cb53c626 2833/* power-up/down the controller */
68467f51 2834static void azx_power_notify(struct hda_bus *bus, bool power_up)
cb53c626 2835{
33fa35ed 2836 struct azx *chip = bus->private_data;
cb53c626 2837
2ea3c6a2
TI		 2838 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2839 return;
2840
68467f51 2841 if (power_up)
b8dfc462
ML		 2842 pm_runtime_get_sync(&chip->pci->dev);
2843 else
2844 pm_runtime_put_sync(&chip->pci->dev);
cb53c626 2845}
65fcd41d
TI		 2846
2847static DEFINE_MUTEX(card_list_lock);
2848static LIST_HEAD(card_list);
2849
2850static void azx_add_card_list(struct azx *chip)
2851{
2852 mutex_lock(&card_list_lock);
2853 list_add(&chip->list, &card_list);
2854 mutex_unlock(&card_list_lock);
2855}
2856
2857static void azx_del_card_list(struct azx *chip)
2858{
2859 mutex_lock(&card_list_lock);
2860 list_del_init(&chip->list);
2861 mutex_unlock(&card_list_lock);
2862}
2863
2864/* trigger power-save check at writing parameter */
2865static int param_set_xint(const char *val, const struct kernel_param *kp)
2866{
2867 struct azx *chip;
2868 struct hda_codec *c;
2869 int prev = power_save;
2870 int ret = param_set_int(val, kp);
2871
2872 if (ret || prev == power_save)
2873 return ret;
2874
2875 mutex_lock(&card_list_lock);
2876 list_for_each_entry(chip, &card_list, list) {
2877 if (!chip->bus || chip->disabled)
2878 continue;
2879 list_for_each_entry(c, &chip->bus->codec_list, list)
2880 snd_hda_power_sync(c);
2881 }
2882 mutex_unlock(&card_list_lock);
2883 return 0;
2884}
2885#else
2886#define azx_add_card_list(chip) /* NOP */
2887#define azx_del_card_list(chip) /* NOP */
83012a7c 2888#endif /* CONFIG_PM */
5c0b9bec 2889
7ccbde57 2890#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 2891/*
2892 * power management
2893 */
68cb2b55 2894static int azx_suspend(struct device *dev)
1da177e4 2895{
68cb2b55
TI		 2896 struct pci_dev *pci = to_pci_dev(dev);
2897 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2898 struct azx *chip = card->private_data;
01b65bfb 2899 struct azx_pcm *p;
1da177e4 2900
c5c21523
TI		 2901 if (chip->disabled)
2902 return 0;
2903
421a1252 2904 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2905 azx_clear_irq_pending(chip);
01b65bfb
TI		 2906 list_for_each_entry(p, &chip->pcm_list, list)
2907 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2908 if (chip->initialized)
8dd78330 2909 snd_hda_suspend(chip->bus);
cb53c626 2910 azx_stop_chip(chip);
3af3f356 2911 azx_reset_link(chip);
30b35399 2912 if (chip->irq >= 0) {
43001c95 2913 free_irq(chip->irq, chip);
30b35399
TI		 2914 chip->irq = -1;
2915 }
68e7fffc 2916 if (chip->msi)
43001c95 2917 pci_disable_msi(chip->pci);
421a1252
TI		 2918 pci_disable_device(pci);
2919 pci_save_state(pci);
68cb2b55 2920 pci_set_power_state(pci, PCI_D3hot);
1da177e4
LT		 2921 return 0;
2922}
2923
68cb2b55 2924static int azx_resume(struct device *dev)
1da177e4 2925{
68cb2b55
TI		 2926 struct pci_dev *pci = to_pci_dev(dev);
2927 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2928 struct azx *chip = card->private_data;
1da177e4 2929
c5c21523
TI		 2930 if (chip->disabled)
2931 return 0;
2932
d14a7e0b
TI		 2933 pci_set_power_state(pci, PCI_D0);
2934 pci_restore_state(pci);
30b35399
TI		 2935 if (pci_enable_device(pci) < 0) {
2936 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2937 "disabling device\n");
2938 snd_card_disconnect(card);
2939 return -EIO;
2940 }
2941 pci_set_master(pci);
68e7fffc
TI		 2942 if (chip->msi)
2943 if (pci_enable_msi(pci) < 0)
2944 chip->msi = 0;
2945 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2946 return -EIO;
cb53c626 2947 azx_init_pci(chip);
d804ad92 2948
7f30830b 2949 azx_init_chip(chip, 1);
d804ad92 2950
1da177e4 2951 snd_hda_resume(chip->bus);
421a1252 2952 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2953 return 0;
2954}
b8dfc462
ML		 2955#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2956
2957#ifdef CONFIG_PM_RUNTIME
2958static int azx_runtime_suspend(struct device *dev)
2959{
2960 struct snd_card *card = dev_get_drvdata(dev);
2961 struct azx *chip = card->private_data;
2962
b8dfc462 2963 azx_stop_chip(chip);
3af3f356 2964 azx_reset_link(chip);
b8dfc462
ML		 2965 azx_clear_irq_pending(chip);
2966 return 0;
2967}
2968
2969static int azx_runtime_resume(struct device *dev)
2970{
2971 struct snd_card *card = dev_get_drvdata(dev);
2972 struct azx *chip = card->private_data;
2973
2974 azx_init_pci(chip);
2975 azx_init_chip(chip, 1);
2976 return 0;
2977}
6eb827d2
TI		 2978
2979static int azx_runtime_idle(struct device *dev)
2980{
2981 struct snd_card *card = dev_get_drvdata(dev);
2982 struct azx *chip = card->private_data;
2983
2984 if (!power_save_controller ||
2985 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2986 return -EBUSY;
2987
2988 return 0;
2989}
2990
b8dfc462
ML		 2991#endif /* CONFIG_PM_RUNTIME */
2992
2993#ifdef CONFIG_PM
2994static const struct dev_pm_ops azx_pm = {
2995 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 2996 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 2997};
2998
68cb2b55
TI		 2999#define AZX_PM_OPS &azx_pm
3000#else
68cb2b55 3001#define AZX_PM_OPS NULL
b8dfc462 3002#endif /* CONFIG_PM */
1da177e4
LT		 3003
3004
0cbf0098
TI		 3005/*
3006 * reboot notifier for hang-up problem at power-down
3007 */
3008static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3009{
3010 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 3011 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 3012 azx_stop_chip(chip);
3013 return NOTIFY_OK;
3014}
3015
3016static void azx_notifier_register(struct azx *chip)
3017{
3018 chip->reboot_notifier.notifier_call = azx_halt;
3019 register_reboot_notifier(&chip->reboot_notifier);
3020}
3021
3022static void azx_notifier_unregister(struct azx *chip)
3023{
3024 if (chip->reboot_notifier.notifier_call)
3025 unregister_reboot_notifier(&chip->reboot_notifier);
3026}
3027
48c8b0eb
TI		 3028static int azx_first_init(struct azx *chip);
3029static int azx_probe_continue(struct azx *chip);
a82d51ed 3030
8393ec4a 3031#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 3032static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 3033
a82d51ed
TI		 3034static void azx_vs_set_state(struct pci_dev *pci,
3035 enum vga_switcheroo_state state)
3036{
3037 struct snd_card *card = pci_get_drvdata(pci);
3038 struct azx *chip = card->private_data;
3039 bool disabled;
3040
f4c482a4 3041 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 3042 if (chip->init_failed)
3043 return;
3044
3045 disabled = (state == VGA_SWITCHEROO_OFF);
3046 if (chip->disabled == disabled)
3047 return;
3048
3049 if (!chip->bus) {
3050 chip->disabled = disabled;
3051 if (!disabled) {
3052 snd_printk(KERN_INFO SFX
3053 "%s: Start delayed initialization\n",
3054 pci_name(chip->pci));
3055 if (azx_first_init(chip) < 0 ||
3056 azx_probe_continue(chip) < 0) {
3057 snd_printk(KERN_ERR SFX
3058 "%s: initialization error\n",
3059 pci_name(chip->pci));
3060 chip->init_failed = true;
3061 }
3062 }
3063 } else {
3064 snd_printk(KERN_INFO SFX
445a51b3
DB		 3065 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3066 disabled ? "Disabling" : "Enabling");
a82d51ed 3067 if (disabled) {
68cb2b55 3068 azx_suspend(&pci->dev);
a82d51ed 3069 chip->disabled = true;
128960a9 3070 if (snd_hda_lock_devices(chip->bus))
445a51b3
DB		 3071 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3072 pci_name(chip->pci));
a82d51ed
TI		 3073 } else {
3074 snd_hda_unlock_devices(chip->bus);
3075 chip->disabled = false;
68cb2b55 3076 azx_resume(&pci->dev);
a82d51ed
TI		 3077 }
3078 }
3079}
3080
3081static bool azx_vs_can_switch(struct pci_dev *pci)
3082{
3083 struct snd_card *card = pci_get_drvdata(pci);
3084 struct azx *chip = card->private_data;
3085
f4c482a4 3086 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 3087 if (chip->init_failed)
3088 return false;
3089 if (chip->disabled || !chip->bus)
3090 return true;
3091 if (snd_hda_lock_devices(chip->bus))
3092 return false;
3093 snd_hda_unlock_devices(chip->bus);
3094 return true;
3095}
3096
e23e7a14 3097static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 3098{
3099 struct pci_dev *p = get_bound_vga(chip->pci);
3100 if (p) {
3101 snd_printk(KERN_INFO SFX
3102 "%s: Handle VGA-switcheroo audio client\n",
3103 pci_name(chip->pci));
3104 chip->use_vga_switcheroo = 1;
3105 pci_dev_put(p);
3106 }
3107}
3108
3109static const struct vga_switcheroo_client_ops azx_vs_ops = {
3110 .set_gpu_state = azx_vs_set_state,
3111 .can_switch = azx_vs_can_switch,
3112};
3113
e23e7a14 3114static int register_vga_switcheroo(struct azx *chip)
a82d51ed 3115{
128960a9
TI		 3116 int err;
3117
a82d51ed
TI		 3118 if (!chip->use_vga_switcheroo)
3119 return 0;
3120 /* FIXME: currently only handling DIS controller
3121 * is there any machine with two switchable HDMI audio controllers?
3122 */
128960a9 3123 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 3124 VGA_SWITCHEROO_DIS,
3125 chip->bus != NULL);
128960a9
TI		 3126 if (err < 0)
3127 return err;
3128 chip->vga_switcheroo_registered = 1;
3129 return 0;
a82d51ed
TI		 3130}
3131#else
3132#define init_vga_switcheroo(chip) /* NOP */
3133#define register_vga_switcheroo(chip) 0
8393ec4a 3134#define check_hdmi_disabled(pci) false
a82d51ed
TI		 3135#endif /* SUPPORT_VGA_SWITCHER */
3136
1da177e4
LT		 3137/*
3138 * destructor
3139 */
a98f90fd 3140static int azx_free(struct azx *chip)
1da177e4 3141{
4ce107b9
TI		 3142 int i;
3143
65fcd41d
TI		 3144 azx_del_card_list(chip);
3145
0cbf0098
TI		 3146 azx_notifier_unregister(chip);
3147
f4c482a4 3148 chip->init_failed = 1; /* to be sure */
44728e97 3149 complete_all(&chip->probe_wait);
f4c482a4 3150
a82d51ed
TI		 3151 if (use_vga_switcheroo(chip)) {
3152 if (chip->disabled && chip->bus)
3153 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 3154 if (chip->vga_switcheroo_registered)
3155 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 3156 }
3157
ce43fbae 3158 if (chip->initialized) {
9ad593f6 3159 azx_clear_irq_pending(chip);
07e4ca50 3160 for (i = 0; i < chip->num_streams; i++)
1da177e4 3161 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 3162 azx_stop_chip(chip);
1da177e4
LT		 3163 }
3164
f000fd80 3165 if (chip->irq >= 0)
1da177e4 3166 free_irq(chip->irq, (void*)chip);
68e7fffc 3167 if (chip->msi)
30b35399 3168 pci_disable_msi(chip->pci);
f079c25a
TI		 3169 if (chip->remap_addr)
3170 iounmap(chip->remap_addr);
1da177e4 3171
4ce107b9
TI		 3172 if (chip->azx_dev) {
3173 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 3174 if (chip->azx_dev[i].bdl.area) {
3175 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 3176 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 3177 }
4ce107b9 3178 }
27fe48d9
TI		 3179 if (chip->rb.area) {
3180 mark_pages_wc(chip, &chip->rb, false);
1da177e4 3181 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 3182 }
3183 if (chip->posbuf.area) {
3184 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 3185 snd_dma_free_pages(&chip->posbuf);
27fe48d9 3186 }
a82d51ed
TI		 3187 if (chip->region_requested)
3188 pci_release_regions(chip->pci);
1da177e4 3189 pci_disable_device(chip->pci);
07e4ca50 3190 kfree(chip->azx_dev);
4918cdab
TI		 3191#ifdef CONFIG_SND_HDA_PATCH_LOADER
3192 if (chip->fw)
3193 release_firmware(chip->fw);
3194#endif
1da177e4
LT		 3195 kfree(chip);
3196
3197 return 0;
3198}
3199
a98f90fd 3200static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 3201{
3202 return azx_free(device->device_data);
3203}
3204
8393ec4a 3205#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 3206/*
3207 * Check of disabled HDMI controller by vga-switcheroo
3208 */
e23e7a14 3209static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 3210{
3211 struct pci_dev *p;
3212
3213 /* check only discrete GPU */
3214 switch (pci->vendor) {
3215 case PCI_VENDOR_ID_ATI:
3216 case PCI_VENDOR_ID_AMD:
3217 case PCI_VENDOR_ID_NVIDIA:
3218 if (pci->devfn == 1) {
3219 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3220 pci->bus->number, 0);
3221 if (p) {
3222 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3223 return p;
3224 pci_dev_put(p);
3225 }
3226 }
3227 break;
3228 }
3229 return NULL;
3230}
3231
e23e7a14 3232static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 3233{
3234 bool vga_inactive = false;
3235 struct pci_dev *p = get_bound_vga(pci);
3236
3237 if (p) {
12b78a7f 3238 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 3239 vga_inactive = true;
3240 pci_dev_put(p);
3241 }
3242 return vga_inactive;
3243}
8393ec4a 3244#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 3245
3372a153
TI		 3246/*
3247 * white/black-listing for position_fix
3248 */
e23e7a14 3249static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 3250 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3251 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 3252 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 3253 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 3254 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 3255 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 3256 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 3257 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 3258 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 3259 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 3260 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 3261 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 3262 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 3263 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 3264 {}
3265};
3266
e23e7a14 3267static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 3268{
3269 const struct snd_pci_quirk *q;
3270
c673ba1c 3271 switch (fix) {
1dac6695 3272 case POS_FIX_AUTO:
c673ba1c
TI		 3273 case POS_FIX_LPIB:
3274 case POS_FIX_POSBUF:
4cb36310 3275 case POS_FIX_VIACOMBO:
a6f2fd55 3276 case POS_FIX_COMBO:
c673ba1c
TI		 3277 return fix;
3278 }
3279
c673ba1c
TI		 3280 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3281 if (q) {
3282 printk(KERN_INFO
3283 "hda_intel: position_fix set to %d "
3284 "for device %04x:%04x\n",
3285 q->value, q->subvendor, q->subdevice);
3286 return q->value;
3372a153 3287 }
bdd9ef24
DH		 3288
3289 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 3290 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
445a51b3 3291 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
bdd9ef24 3292 return POS_FIX_VIACOMBO;
9477c58e
TI		 3293 }
3294 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
445a51b3 3295 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
50e3bbf9 3296 return POS_FIX_LPIB;
bdd9ef24 3297 }
c673ba1c 3298 return POS_FIX_AUTO;
3372a153
TI		 3299}
3300
669ba27a
TI		 3301/*
3302 * black-lists for probe_mask
3303 */
e23e7a14 3304static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 3305 /* Thinkpad often breaks the controller communication when accessing
3306 * to the non-working (or non-existing) modem codec slot.
3307 */
3308 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3309 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3310 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 3311 /* broken BIOS */
3312 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 3313 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3314 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 3315 /* forced codec slots */
93574844 3316 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 3317 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 3318 /* WinFast VP200 H (Teradici) user reported broken communication */
3319 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 3320 {}
3321};
3322
f1eaaeec
TI		 3323#define AZX_FORCE_CODEC_MASK 0x100
3324
e23e7a14 3325static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 3326{
3327 const struct snd_pci_quirk *q;
3328
f1eaaeec
TI		 3329 chip->codec_probe_mask = probe_mask[dev];
3330 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 3331 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3332 if (q) {
3333 printk(KERN_INFO
3334 "hda_intel: probe_mask set to 0x%x "
3335 "for device %04x:%04x\n",
3336 q->value, q->subvendor, q->subdevice);
f1eaaeec 3337 chip->codec_probe_mask = q->value;
669ba27a
TI		 3338 }
3339 }
f1eaaeec
TI		 3340
3341 /* check forced option */
3342 if (chip->codec_probe_mask != -1 &&
3343 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3344 chip->codec_mask = chip->codec_probe_mask & 0xff;
3345 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3346 chip->codec_mask);
3347 }
669ba27a
TI		 3348}
3349
4d8e22e0 3350/*
71623855 3351 * white/black-list for enable_msi
4d8e22e0 3352 */
e23e7a14 3353static struct snd_pci_quirk msi_black_list[] = {
9dc8398b 3354 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 3355 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 3356 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 3357 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 3358 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 3359 {}
3360};
3361
e23e7a14 3362static void check_msi(struct azx *chip)
4d8e22e0
TI		 3363{
3364 const struct snd_pci_quirk *q;
3365
71623855
TI		 3366 if (enable_msi >= 0) {
3367 chip->msi = !!enable_msi;
4d8e22e0 3368 return;
71623855
TI		 3369 }
3370 chip->msi = 1; /* enable MSI as default */
3371 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 3372 if (q) {
3373 printk(KERN_INFO
3374 "hda_intel: msi for device %04x:%04x set to %d\n",
3375 q->subvendor, q->subdevice, q->value);
3376 chip->msi = q->value;
80c43ed7
TI		 3377 return;
3378 }
3379
3380 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 3381 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3382 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 3383 chip->msi = 0;
4d8e22e0
TI		 3384 }
3385}
3386
a1585d76 3387/* check the snoop mode availability */
e23e7a14 3388static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 3389{
3390 bool snoop = chip->snoop;
3391
3392 switch (chip->driver_type) {
3393 case AZX_DRIVER_VIA:
3394 /* force to non-snoop mode for a new VIA controller
3395 * when BIOS is set
3396 */
3397 if (snoop) {
3398 u8 val;
3399 pci_read_config_byte(chip->pci, 0x42, &val);
3400 if (!(val & 0x80) && chip->pci->revision == 0x30)
3401 snoop = false;
3402 }
3403 break;
3404 case AZX_DRIVER_ATIHDMI_NS:
3405 /* new ATI HDMI requires non-snoop */
3406 snoop = false;
3407 break;
c1279f87
TI		 3408 case AZX_DRIVER_CTHDA:
3409 snoop = false;
3410 break;
a1585d76
TI		 3411 }
3412
3413 if (snoop != chip->snoop) {
445a51b3
DB		 3414 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3415 pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
a1585d76
TI		 3416 chip->snoop = snoop;
3417 }
3418}
669ba27a 3419
1da177e4
LT		 3420/*
3421 * constructor
3422 */
e23e7a14
BP		 3423static int azx_create(struct snd_card *card, struct pci_dev *pci,
3424 int dev, unsigned int driver_caps,
3425 struct azx **rchip)
1da177e4 3426{
a98f90fd 3427 static struct snd_device_ops ops = {
1da177e4
LT		 3428 .dev_free = azx_dev_free,
3429 };
a82d51ed
TI		 3430 struct azx *chip;
3431 int err;
1da177e4
LT		 3432
3433 *rchip = NULL;
bcd72003 3434
927fc866
PM		 3435 err = pci_enable_device(pci);
3436 if (err < 0)
1da177e4
LT		 3437 return err;
3438
e560d8d8 3439 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 3440 if (!chip) {
445a51b3 3441 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
1da177e4
LT		 3442 pci_disable_device(pci);
3443 return -ENOMEM;
3444 }
3445
3446 spin_lock_init(&chip->reg_lock);
62932df8 3447 mutex_init(&chip->open_mutex);
1da177e4
LT		 3448 chip->card = card;
3449 chip->pci = pci;
3450 chip->irq = -1;
9477c58e
TI		 3451 chip->driver_caps = driver_caps;
3452 chip->driver_type = driver_caps & 0xff;
4d8e22e0 3453 check_msi(chip);
555e219f 3454 chip->dev_index = dev;
9ad593f6 3455 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 3456 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 3457 INIT_LIST_HEAD(&chip->list);
a82d51ed 3458 init_vga_switcheroo(chip);
f4c482a4 3459 init_completion(&chip->probe_wait);
1da177e4 3460
beaffc39
SG		 3461 chip->position_fix[0] = chip->position_fix[1] =
3462 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 3463 /* combo mode uses LPIB for playback */
3464 if (chip->position_fix[0] == POS_FIX_COMBO) {
3465 chip->position_fix[0] = POS_FIX_LPIB;
3466 chip->position_fix[1] = POS_FIX_AUTO;
3467 }
3468
5aba4f8e 3469 check_probe_mask(chip, dev);
3372a153 3470
27346166 3471 chip->single_cmd = single_cmd;
27fe48d9 3472 chip->snoop = hda_snoop;
a1585d76 3473 azx_check_snoop_available(chip);
c74db86b 3474
5c0d7bc1
TI		 3475 if (bdl_pos_adj[dev] < 0) {
3476 switch (chip->driver_type) {
0c6341ac 3477 case AZX_DRIVER_ICH:
32679f95 3478 case AZX_DRIVER_PCH:
0c6341ac 3479 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 3480 break;
3481 default:
0c6341ac 3482 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 3483 break;
3484 }
3485 }
3486
a82d51ed
TI		 3487 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3488 if (err < 0) {
445a51b3
DB		 3489 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3490 pci_name(chip->pci));
a82d51ed
TI		 3491 azx_free(chip);
3492 return err;
3493 }
3494
3495 *rchip = chip;
3496 return 0;
3497}
3498
48c8b0eb 3499static int azx_first_init(struct azx *chip)
a82d51ed
TI		 3500{
3501 int dev = chip->dev_index;
3502 struct pci_dev *pci = chip->pci;
3503 struct snd_card *card = chip->card;
3504 int i, err;
3505 unsigned short gcap;
3506
07e4ca50
TI		 3507#if BITS_PER_LONG != 64
3508 /* Fix up base address on ULI M5461 */
3509 if (chip->driver_type == AZX_DRIVER_ULI) {
3510 u16 tmp3;
3511 pci_read_config_word(pci, 0x40, &tmp3);
3512 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3513 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3514 }
3515#endif
3516
927fc866 3517 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 3518 if (err < 0)
1da177e4 3519 return err;
a82d51ed 3520 chip->region_requested = 1;
1da177e4 3521
927fc866 3522 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 3523 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 3524 if (chip->remap_addr == NULL) {
445a51b3 3525 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
a82d51ed 3526 return -ENXIO;
1da177e4
LT		 3527 }
3528
68e7fffc
TI		 3529 if (chip->msi)
3530 if (pci_enable_msi(pci) < 0)
3531 chip->msi = 0;
7376d013 3532
a82d51ed
TI		 3533 if (azx_acquire_irq(chip, 0) < 0)
3534 return -EBUSY;
1da177e4
LT		 3535
3536 pci_set_master(pci);
3537 synchronize_irq(chip->irq);
3538
bcd72003 3539 gcap = azx_readw(chip, GCAP);
445a51b3 3540 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
bcd72003 3541
dc4c2e6b 3542 /* disable SB600 64bit support for safety */
9477c58e 3543 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3544 struct pci_dev *p_smbus;
3545 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3546 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3547 NULL);
3548 if (p_smbus) {
3549 if (p_smbus->revision < 0x30)
3550 gcap &= ~ICH6_GCAP_64OK;
3551 pci_dev_put(p_smbus);
3552 }
3553 }
09240cf4 3554
9477c58e
TI		 3555 /* disable 64bit DMA address on some devices */
3556 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
445a51b3 3557 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
396087ea 3558 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3559 }
396087ea 3560
2ae66c26 3561 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3562 if (align_buffer_size >= 0)
3563 chip->align_buffer_size = !!align_buffer_size;
3564 else {
3565 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3566 chip->align_buffer_size = 0;
3567 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3568 chip->align_buffer_size = 1;
3569 else
3570 chip->align_buffer_size = 1;
3571 }
2ae66c26 3572
cf7aaca8 3573 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3574 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3575 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3576 else {
e930438c
YH		 3577 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3578 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3579 }
cf7aaca8 3580
8b6ed8e7
TI		 3581 /* read number of streams from GCAP register instead of using
3582 * hardcoded value
3583 */
3584 chip->capture_streams = (gcap >> 8) & 0x0f;
3585 chip->playback_streams = (gcap >> 12) & 0x0f;
3586 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3587 /* gcap didn't give any info, switching to old method */
3588
3589 switch (chip->driver_type) {
3590 case AZX_DRIVER_ULI:
3591 chip->playback_streams = ULI_NUM_PLAYBACK;
3592 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3593 break;
3594 case AZX_DRIVER_ATIHDMI:
1815b34a 3595 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3596 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3597 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3598 break;
c4da29ca 3599 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3600 default:
3601 chip->playback_streams = ICH6_NUM_PLAYBACK;
3602 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3603 break;
3604 }
07e4ca50 3605 }
8b6ed8e7
TI		 3606 chip->capture_index_offset = 0;
3607 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3608 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3609 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3610 GFP_KERNEL);
927fc866 3611 if (!chip->azx_dev) {
445a51b3 3612 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
a82d51ed 3613 return -ENOMEM;
07e4ca50
TI		 3614 }
3615
4ce107b9 3616 for (i = 0; i < chip->num_streams; i++) {
eb49faa6 3617 dsp_lock_init(&chip->azx_dev[i]);
4ce107b9
TI		 3618 /* allocate memory for the BDL for each stream */
3619 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3620 snd_dma_pci_data(chip->pci),
3621 BDL_SIZE, &chip->azx_dev[i].bdl);
3622 if (err < 0) {
445a51b3 3623 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
a82d51ed 3624 return -ENOMEM;
4ce107b9 3625 }
27fe48d9 3626 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3627 }
0be3b5d3 3628 /* allocate memory for the position buffer */
d01ce99f
TI		 3629 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3630 snd_dma_pci_data(chip->pci),
3631 chip->num_streams * 8, &chip->posbuf);
3632 if (err < 0) {
445a51b3 3633 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
a82d51ed 3634 return -ENOMEM;
1da177e4 3635 }
27fe48d9 3636 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3637 /* allocate CORB/RIRB */
81740861
TI		 3638 err = azx_alloc_cmd_io(chip);
3639 if (err < 0)
a82d51ed 3640 return err;
1da177e4
LT		 3641
3642 /* initialize streams */
3643 azx_init_stream(chip);
3644
3645 /* initialize chip */
cb53c626 3646 azx_init_pci(chip);
10e77dda 3647 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3648
3649 /* codec detection */
927fc866 3650 if (!chip->codec_mask) {
445a51b3 3651 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
a82d51ed 3652 return -ENODEV;
1da177e4
LT		 3653 }
3654
07e4ca50 3655 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3656 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3657 sizeof(card->shortname));
3658 snprintf(card->longname, sizeof(card->longname),
3659 "%s at 0x%lx irq %i",
3660 card->shortname, chip->addr, chip->irq);
07e4ca50 3661
1da177e4 3662 return 0;
1da177e4
LT		 3663}
3664
cb53c626
TI		 3665static void power_down_all_codecs(struct azx *chip)
3666{
83012a7c 3667#ifdef CONFIG_PM
cb53c626
TI		 3668 /* The codecs were powered up in snd_hda_codec_new().
3669 * Now all initialization done, so turn them down if possible
3670 */
3671 struct hda_codec *codec;
3672 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3673 snd_hda_power_down(codec);
3674 }
3675#endif
3676}
3677
97c6a3d1 3678#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 3679/* callback from request_firmware_nowait() */
3680static void azx_firmware_cb(const struct firmware *fw, void *context)
3681{
3682 struct snd_card *card = context;
3683 struct azx *chip = card->private_data;
3684 struct pci_dev *pci = chip->pci;
3685
3686 if (!fw) {
445a51b3
DB		 3687 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3688 pci_name(chip->pci));
5cb543db
TI		 3689 goto error;
3690 }
3691
3692 chip->fw = fw;
3693 if (!chip->disabled) {
3694 /* continue probing */
3695 if (azx_probe_continue(chip))
3696 goto error;
3697 }
3698 return; /* OK */
3699
3700 error:
3701 snd_card_free(card);
3702 pci_set_drvdata(pci, NULL);
3703}
97c6a3d1 3704#endif
5cb543db 3705
e23e7a14
BP		 3706static int azx_probe(struct pci_dev *pci,
3707 const struct pci_device_id *pci_id)
1da177e4 3708{
5aba4f8e 3709 static int dev;
a98f90fd
TI		 3710 struct snd_card *card;
3711 struct azx *chip;
5cb543db 3712 bool probe_now;
927fc866 3713 int err;
1da177e4 3714
5aba4f8e
TI		 3715 if (dev >= SNDRV_CARDS)
3716 return -ENODEV;
3717 if (!enable[dev]) {
3718 dev++;
3719 return -ENOENT;
3720 }
3721
e58de7ba
TI		 3722 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3723 if (err < 0) {
445a51b3 3724 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
e58de7ba 3725 return err;
1da177e4
LT		 3726 }
3727
4ea6fbc8
TI		 3728 snd_card_set_dev(card, &pci->dev);
3729
5aba4f8e 3730 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3731 if (err < 0)
3732 goto out_free;
421a1252 3733 card->private_data = chip;
f4c482a4
TI		 3734
3735 pci_set_drvdata(pci, card);
3736
3737 err = register_vga_switcheroo(chip);
3738 if (err < 0) {
3739 snd_printk(KERN_ERR SFX
445a51b3 3740 "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
f4c482a4
TI		 3741 goto out_free;
3742 }
3743
3744 if (check_hdmi_disabled(pci)) {
445a51b3 3745 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
f4c482a4 3746 pci_name(pci));
445a51b3 3747 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
f4c482a4
TI		 3748 chip->disabled = true;
3749 }
3750
5cb543db 3751 probe_now = !chip->disabled;
f4c482a4
TI		 3752 if (probe_now) {
3753 err = azx_first_init(chip);
3754 if (err < 0)
3755 goto out_free;
3756 }
1da177e4 3757
4918cdab
TI		 3758#ifdef CONFIG_SND_HDA_PATCH_LOADER
3759 if (patch[dev] && *patch[dev]) {
445a51b3
DB		 3760 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3761 pci_name(pci), patch[dev]);
5cb543db
TI		 3762 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3763 &pci->dev, GFP_KERNEL, card,
3764 azx_firmware_cb);
4918cdab
TI		 3765 if (err < 0)
3766 goto out_free;
5cb543db 3767 probe_now = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 3768 }
3769#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3770
5cb543db 3771 if (probe_now) {
a82d51ed
TI		 3772 err = azx_probe_continue(chip);
3773 if (err < 0)
3774 goto out_free;
3775 }
3776
b8dfc462
ML		 3777 if (pci_dev_run_wake(pci))
3778 pm_runtime_put_noidle(&pci->dev);
3779
a82d51ed 3780 dev++;
44728e97 3781 complete_all(&chip->probe_wait);
a82d51ed
TI		 3782 return 0;
3783
3784out_free:
3785 snd_card_free(card);
3786 return err;
3787}
3788
48c8b0eb 3789static int azx_probe_continue(struct azx *chip)
a82d51ed
TI		 3790{
3791 int dev = chip->dev_index;
3792 int err;
3793
2dca0bba
JK		 3794#ifdef CONFIG_SND_HDA_INPUT_BEEP
3795 chip->beep_mode = beep_mode[dev];
3796#endif
3797
1da177e4 3798 /* create codec instances */
a1e21c90 3799 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3800 if (err < 0)
3801 goto out_free;
4ea6fbc8 3802#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 3803 if (chip->fw) {
3804 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3805 chip->fw->data);
4ea6fbc8
TI		 3806 if (err < 0)
3807 goto out_free;
e39ae856 3808#ifndef CONFIG_PM
4918cdab
TI		 3809 release_firmware(chip->fw); /* no longer needed */
3810 chip->fw = NULL;
e39ae856 3811#endif
4ea6fbc8
TI		 3812 }
3813#endif
10e77dda 3814 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3815 err = azx_codec_configure(chip);
3816 if (err < 0)
3817 goto out_free;
3818 }
1da177e4
LT		 3819
3820 /* create PCM streams */
176d5335 3821 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3822 if (err < 0)
3823 goto out_free;
1da177e4
LT		 3824
3825 /* create mixer controls */
d01ce99f 3826 err = azx_mixer_create(chip);
41dda0fd
WF		 3827 if (err < 0)
3828 goto out_free;
1da177e4 3829
a82d51ed 3830 err = snd_card_register(chip->card);
41dda0fd
WF		 3831 if (err < 0)
3832 goto out_free;
1da177e4 3833
cb53c626
TI		 3834 chip->running = 1;
3835 power_down_all_codecs(chip);
0cbf0098 3836 azx_notifier_register(chip);
65fcd41d 3837 azx_add_card_list(chip);
1da177e4 3838
9121947d
TI		 3839 return 0;
3840
41dda0fd 3841out_free:
a82d51ed 3842 chip->init_failed = 1;
41dda0fd 3843 return err;
1da177e4
LT		 3844}
3845
e23e7a14 3846static void azx_remove(struct pci_dev *pci)
1da177e4 3847{
9121947d 3848 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462
ML		 3849
3850 if (pci_dev_run_wake(pci))
3851 pm_runtime_get_noresume(&pci->dev);
3852
9121947d
TI		 3853 if (card)
3854 snd_card_free(card);
1da177e4
LT		 3855}
3856
3857/* PCI IDs */
cebe41d4 3858static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3859 /* CPT */
9477c58e 3860 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 3861 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 3862 /* PBG */
9477c58e 3863 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 3864 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 3865 /* Panther Point */
9477c58e 3866 { PCI_DEVICE(0x8086, 0x1e20),
d7dab4db 3867 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 3868 /* Lynx Point */
3869 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 3870 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 3871 /* Wellsburg */
3872 { PCI_DEVICE(0x8086, 0x8d20),
3873 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3874 { PCI_DEVICE(0x8086, 0x8d21),
3875 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3876 /* Lynx Point-LP */
3877 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 3878 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3879 /* Lynx Point-LP */
3880 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 3881 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 3882 /* Haswell */
4a7c516b
WX		 3883 { PCI_DEVICE(0x8086, 0x0a0c),
3884 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 3885 { PCI_DEVICE(0x8086, 0x0c0c),
2ea3c6a2 3886 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
d279fae8 3887 { PCI_DEVICE(0x8086, 0x0d0c),
2ea3c6a2 3888 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
99df18b3
PLB		 3889 /* 5 Series/3400 */
3890 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 3891 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 3892 /* Poulsbo */
9477c58e 3893 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 3894 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3895 /* Oaktrail */
09904b95 3896 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 3897 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 3898 /* BayTrail */
3899 { PCI_DEVICE(0x8086, 0x0f04),
3900 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
645e9035 3901 /* ICH */
8b0bd226 3902 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 3903 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3904 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 3905 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 3906 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3907 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 3908 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 3909 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3910 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 3911 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 3912 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3913 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 3914 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 3915 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3916 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3917 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 3918 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3919 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3920 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 3921 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3922 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 3923 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 3924 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3925 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 3926 /* Generic Intel */
3927 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3928 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3929 .class_mask = 0xffffff,
2ae66c26 3930 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 3931 /* ATI SB 450/600/700/800/900 */
3932 { PCI_DEVICE(0x1002, 0x437b),
3933 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3934 { PCI_DEVICE(0x1002, 0x4383),
3935 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3936 /* AMD Hudson */
3937 { PCI_DEVICE(0x1022, 0x780d),
3938 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 3939 /* ATI HDMI */
9477c58e
TI		 3940 { PCI_DEVICE(0x1002, 0x793b),
3941 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3942 { PCI_DEVICE(0x1002, 0x7919),
3943 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3944 { PCI_DEVICE(0x1002, 0x960f),
3945 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3946 { PCI_DEVICE(0x1002, 0x970f),
3947 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3948 { PCI_DEVICE(0x1002, 0xaa00),
3949 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3950 { PCI_DEVICE(0x1002, 0xaa08),
3951 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3952 { PCI_DEVICE(0x1002, 0xaa10),
3953 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3954 { PCI_DEVICE(0x1002, 0xaa18),
3955 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3956 { PCI_DEVICE(0x1002, 0xaa20),
3957 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3958 { PCI_DEVICE(0x1002, 0xaa28),
3959 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3960 { PCI_DEVICE(0x1002, 0xaa30),
3961 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3962 { PCI_DEVICE(0x1002, 0xaa38),
3963 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3964 { PCI_DEVICE(0x1002, 0xaa40),
3965 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3966 { PCI_DEVICE(0x1002, 0xaa48),
3967 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 3968 { PCI_DEVICE(0x1002, 0x9902),
3969 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3970 { PCI_DEVICE(0x1002, 0xaaa0),
3971 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3972 { PCI_DEVICE(0x1002, 0xaaa8),
3973 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3974 { PCI_DEVICE(0x1002, 0xaab0),
3975 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 3976 /* VIA VT8251/VT8237A */
9477c58e
TI		 3977 { PCI_DEVICE(0x1106, 0x3288),
3978 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 3979 /* VIA GFX VT7122/VX900 */
3980 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3981 /* VIA GFX VT6122/VX11 */
3982 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 3983 /* SIS966 */
3984 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3985 /* ULI M5461 */
3986 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3987 /* NVIDIA MCP */
0c2fd1bf
TI		 3988 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3989 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3990 .class_mask = 0xffffff,
9477c58e 3991 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 3992 /* Teradici */
9477c58e
TI		 3993 { PCI_DEVICE(0x6549, 0x1200),
3994 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 3995 { PCI_DEVICE(0x6549, 0x2200),
3996 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 3997 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 3998 /* CTHDA chips */
3999 { PCI_DEVICE(0x1102, 0x0010),
4000 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4001 { PCI_DEVICE(0x1102, 0x0012),
4002 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
313f6e2d
TI		 4003#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
4004 /* the following entry conflicts with snd-ctxfi driver,
4005 * as ctxfi driver mutates from HD-audio to native mode with
4006 * a special command sequence.
4007 */
4e01f54b
TI		 4008 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4009 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4010 .class_mask = 0xffffff,
9477c58e 4011 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 4012 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 4013#else
4014 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 4015 { PCI_DEVICE(0x1102, 0x0009),
4016 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 4017 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 4018#endif
e35d4b11
OS		 4019 /* Vortex86MX */
4020 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 4021 /* VMware HDAudio */
4022 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 4023 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 4024 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4025 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4026 .class_mask = 0xffffff,
9477c58e 4027 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 4028 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4029 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4030 .class_mask = 0xffffff,
9477c58e 4031 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 4032 { 0, }
4033};
4034MODULE_DEVICE_TABLE(pci, azx_ids);
4035
4036/* pci_driver definition */
e9f66d9b 4037static struct pci_driver azx_driver = {
3733e424 4038 .name = KBUILD_MODNAME,
1da177e4
LT		 4039 .id_table = azx_ids,
4040 .probe = azx_probe,
e23e7a14 4041 .remove = azx_remove,
68cb2b55
TI		 4042 .driver = {
4043 .pm = AZX_PM_OPS,
4044 },
1da177e4
LT		 4045};
4046
e9f66d9b 4047module_pci_driver(azx_driver);
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