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ALSA: hda: add AMD Polaris-10/11 AZ PCI IDs with proper driver caps
[mirror_ubuntu-bionic-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
98d8fc6c
ML		 60#include <sound/hdaudio.h>
61#include <sound/hda_i915.h>
9121947d 62#include <linux/vgaarb.h>
a82d51ed 63#include <linux/vga_switcheroo.h>
4918cdab 64#include <linux/firmware.h>
1da177e4 65#include "hda_codec.h"
05e84878 66#include "hda_controller.h"
347de1f8 67#include "hda_intel.h"
1da177e4 68
785d8c4b
LY		 69#define CREATE_TRACE_POINTS
70#include "hda_intel_trace.h"
71
b6050ef6
TI		 72/* position fix mode */
73enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79};
80
9a34af4a
TI		 81/* Defines for ATI HD Audio support in SB450 south bridge */
82#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85/* Defines for Nvidia HDA support */
86#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88#define NVIDIA_HDA_ISTRM_COH 0x4d
89#define NVIDIA_HDA_OSTRM_COH 0x4c
90#define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 93#define INTEL_HDA_CGCTL 0x48
94#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 95#define INTEL_SCH_HDA_DEVC 0x78
96#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
97
98/* Define IN stream 0 FIFO size offset in VIA controller */
99#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
100/* Define VIA HD Audio Device ID*/
101#define VIA_HDAC_DEVICE_ID 0x3288
102
33124929
TI		 103/* max number of SDs */
104/* ICH, ATI and VIA have 4 playback and 4 capture */
105#define ICH6_NUM_CAPTURE 4
106#define ICH6_NUM_PLAYBACK 4
107
108/* ULI has 6 playback and 5 capture */
109#define ULI_NUM_CAPTURE 5
110#define ULI_NUM_PLAYBACK 6
111
112/* ATI HDMI may have up to 8 playbacks and 0 capture */
113#define ATIHDMI_NUM_CAPTURE 0
114#define ATIHDMI_NUM_PLAYBACK 8
115
116/* TERA has 4 playback and 3 capture */
117#define TERA_NUM_CAPTURE 3
118#define TERA_NUM_PLAYBACK 4
119
1da177e4 120
5aba4f8e
TI		 121static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
122static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 123static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 124static char *model[SNDRV_CARDS];
1dac6695 125static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 126static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 127static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 128static int probe_only[SNDRV_CARDS];
26a6cb6c 129static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 130static bool single_cmd;
71623855 131static int enable_msi = -1;
4ea6fbc8
TI		 132#ifdef CONFIG_SND_HDA_PATCH_LOADER
133static char *patch[SNDRV_CARDS];
134#endif
2dca0bba 135#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 136static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 137 CONFIG_SND_HDA_INPUT_BEEP_MODE};
138#endif
1da177e4 139
5aba4f8e 140module_param_array(index, int, NULL, 0444);
1da177e4 141MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 142module_param_array(id, charp, NULL, 0444);
1da177e4 143MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 144module_param_array(enable, bool, NULL, 0444);
145MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
146module_param_array(model, charp, NULL, 0444);
1da177e4 147MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 148module_param_array(position_fix, int, NULL, 0444);
4cb36310 149MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 150 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 151module_param_array(bdl_pos_adj, int, NULL, 0644);
152MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 153module_param_array(probe_mask, int, NULL, 0444);
606ad75f 154MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 155module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 156MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 157module_param_array(jackpoll_ms, int, NULL, 0444);
158MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 159module_param(single_cmd, bool, 0444);
d01ce99f
TI		 160MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
161 "(for debugging only).");
ac9ef6cf 162module_param(enable_msi, bint, 0444);
134a11f0 163MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 164#ifdef CONFIG_SND_HDA_PATCH_LOADER
165module_param_array(patch, charp, NULL, 0444);
166MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
167#endif
2dca0bba 168#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 169module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 170MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 171 "(0=off, 1=on) (default=1).");
2dca0bba 172#endif
606ad75f 173
83012a7c 174#ifdef CONFIG_PM
65fcd41d 175static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 176static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 177 .set = param_set_xint,
178 .get = param_get_int,
179};
180#define param_check_xint param_check_int
181
fee2fba3 182static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 183module_param(power_save, xint, 0644);
fee2fba3
TI		 184MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
185 "(in second, 0 = disable).");
1da177e4 186
dee1b66c
TI		 187/* reset the HD-audio controller in power save mode.
188 * this may give more power-saving, but will take longer time to
189 * wake up.
190 */
8fc24426
TI		 191static bool power_save_controller = 1;
192module_param(power_save_controller, bool, 0644);
dee1b66c 193MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 194#else
bb573928 195#define power_save 0
83012a7c 196#endif /* CONFIG_PM */
dee1b66c 197
7bfe059e
TI		 198static int align_buffer_size = -1;
199module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 200MODULE_PARM_DESC(align_buffer_size,
201 "Force buffer and period sizes to be multiple of 128 bytes.");
202
27fe48d9 203#ifdef CONFIG_X86
7c732015
TI		 204static int hda_snoop = -1;
205module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 206MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 207#else
208#define hda_snoop true
27fe48d9
TI		 209#endif
210
211
1da177e4
LT		 212MODULE_LICENSE("GPL");
213MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
214 "{Intel, ICH6M},"
2f1b3818 215 "{Intel, ICH7},"
f5d40b30 216 "{Intel, ESB2},"
d2981393 217 "{Intel, ICH8},"
f9cc8a8b 218 "{Intel, ICH9},"
c34f5a04 219 "{Intel, ICH10},"
b29c2360 220 "{Intel, PCH},"
d2f2fcd2 221 "{Intel, CPT},"
d2edeb7c 222 "{Intel, PPT},"
8bc039a1 223 "{Intel, LPT},"
144dad99 224 "{Intel, LPT_LP},"
4eeca499 225 "{Intel, WPT_LP},"
c8b00fd2 226 "{Intel, SPT},"
b4565913 227 "{Intel, SPT_LP},"
e926f2c8 228 "{Intel, HPT},"
cea310e8 229 "{Intel, PBG},"
4979bca9 230 "{Intel, SCH},"
fc20a562 231 "{ATI, SB450},"
89be83f8 232 "{ATI, SB600},"
778b6e1b 233 "{ATI, RS600},"
5b15c95f 234 "{ATI, RS690},"
e6db1119
WL		 235 "{ATI, RS780},"
236 "{ATI, R600},"
2797f724
HRK		 237 "{ATI, RV630},"
238 "{ATI, RV610},"
27da1834
WL		 239 "{ATI, RV670},"
240 "{ATI, RV635},"
241 "{ATI, RV620},"
242 "{ATI, RV770},"
fc20a562 243 "{VIA, VT8251},"
47672310 244 "{VIA, VT8237A},"
07e4ca50
TI		 245 "{SiS, SIS966},"
246 "{ULI, M5461}}");
1da177e4
LT		 247MODULE_DESCRIPTION("Intel HDA driver");
248
a82d51ed 249#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 250#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 251#define SUPPORT_VGA_SWITCHEROO
252#endif
253#endif
254
255
1da177e4 256/*
1da177e4 257 */
1da177e4 258
07e4ca50
TI		 259/* driver types */
260enum {
261 AZX_DRIVER_ICH,
32679f95 262 AZX_DRIVER_PCH,
4979bca9 263 AZX_DRIVER_SCH,
fab1285a 264 AZX_DRIVER_HDMI,
07e4ca50 265 AZX_DRIVER_ATI,
778b6e1b 266 AZX_DRIVER_ATIHDMI,
1815b34a 267 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 268 AZX_DRIVER_VIA,
269 AZX_DRIVER_SIS,
270 AZX_DRIVER_ULI,
da3fca21 271 AZX_DRIVER_NVIDIA,
f269002e 272 AZX_DRIVER_TERA,
14d34f16 273 AZX_DRIVER_CTX,
5ae763b1 274 AZX_DRIVER_CTHDA,
c563f473 275 AZX_DRIVER_CMEDIA,
c4da29ca 276 AZX_DRIVER_GENERIC,
2f5983f2 277 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 278};
279
37e661ee
TI		 280#define azx_get_snoop_type(chip) \
281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
282#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
283
b42b4afb
TI		 284/* quirks for old Intel chipsets */
285#define AZX_DCAPS_INTEL_ICH \
103884a3 286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 287
2ea3c6a2 288/* quirks for Intel PCH */
6603249d 289#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
bcb337d1 291 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 292
55913110 293/* PCH up to IVB; no runtime PM */
6603249d 294#define AZX_DCAPS_INTEL_PCH_NOPM \
55913110 295 (AZX_DCAPS_INTEL_PCH_BASE)
6603249d 296
55913110 297/* PCH for HSW/BDW; with runtime PM */
d7dab4db 298#define AZX_DCAPS_INTEL_PCH \
6603249d 299 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 300
6603249d 301/* HSW HDMI */
33499a15 302#define AZX_DCAPS_INTEL_HASWELL \
103884a3 303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
305 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 306
54a0405d
LY		 307/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
308#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 309 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 310 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
311 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 312
40cc2392
ML		 313#define AZX_DCAPS_INTEL_BAYTRAIL \
314 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
315
2d846c74
LY		 316#define AZX_DCAPS_INTEL_BRASWELL \
317 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
318
d6795827 319#define AZX_DCAPS_INTEL_SKYLAKE \
2d846c74
LY		 320 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
321 AZX_DCAPS_I915_POWERWELL)
d6795827 322
c87693da
LH		 323#define AZX_DCAPS_INTEL_BROXTON \
324 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
325 AZX_DCAPS_I915_POWERWELL)
326
9477c58e
TI		 327/* quirks for ATI SB / AMD Hudson */
328#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
330 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 331
332/* quirks for ATI/AMD HDMI */
333#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 334 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
335 AZX_DCAPS_NO_MSI64)
9477c58e 336
37e661ee
TI		 337/* quirks for ATI HDMI with snoop off */
338#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
339 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
340
9477c58e
TI		 341/* quirks for Nvidia */
342#define AZX_DCAPS_PRESET_NVIDIA \
7d9a1808 343 (AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
37e661ee
TI		 344 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
345 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 346
5ae763b1 347#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 348 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 349 AZX_DCAPS_NO_64BIT |\
37e661ee 350 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 351
a82d51ed 352/*
2b760d88 353 * vga_switcheroo support
a82d51ed
TI		 354 */
355#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 356#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
357#else
358#define use_vga_switcheroo(chip) 0
359#endif
360
03b135ce
LY		 361#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
362 ((pci)->device == 0x0c0c) || \
363 ((pci)->device == 0x0d0c) || \
364 ((pci)->device == 0x160c))
365
7e31a015
TI		 366#define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
367#define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
368#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
369#define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci))
7c23b7c1 370
48c8b0eb 371static char *driver_short_names[] = {
07e4ca50 372 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 373 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 374 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 375 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 376 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 377 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 378 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 379 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
380 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 381 [AZX_DRIVER_ULI] = "HDA ULI M5461",
382 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 383 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 384 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 385 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 386 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 387 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 388};
389
27fe48d9 390#ifdef CONFIG_X86
9ddf1aeb 391static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 392{
9ddf1aeb
TI		 393 int pages;
394
27fe48d9
TI		 395 if (azx_snoop(chip))
396 return;
9ddf1aeb
TI		 397 if (!dmab || !dmab->area || !dmab->bytes)
398 return;
399
400#ifdef CONFIG_SND_DMA_SGBUF
401 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
402 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 403 if (chip->driver_type == AZX_DRIVER_CMEDIA)
404 return; /* deal with only CORB/RIRB buffers */
27fe48d9 405 if (on)
9ddf1aeb 406 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 407 else
9ddf1aeb
TI		 408 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
409 return;
27fe48d9 410 }
9ddf1aeb
TI		 411#endif
412
413 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
414 if (on)
415 set_memory_wc((unsigned long)dmab->area, pages);
416 else
417 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 418}
419
420static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
421 bool on)
422{
9ddf1aeb 423 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 424}
425static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 426 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 427{
428 if (azx_dev->wc_marked != on) {
9ddf1aeb 429 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 430 azx_dev->wc_marked = on;
431 }
432}
433#else
434/* NOP for other archs */
435static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
436 bool on)
437{
438}
439static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 440 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 441{
442}
443#endif
444
68e7fffc 445static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 446
cb53c626
TI		 447/*
448 * initialize the PCI registers
449 */
450/* update bits in a PCI register byte */
451static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
452 unsigned char mask, unsigned char val)
453{
454 unsigned char data;
455
456 pci_read_config_byte(pci, reg, &data);
457 data &= ~mask;
458 data |= (val & mask);
459 pci_write_config_byte(pci, reg, data);
460}
461
462static void azx_init_pci(struct azx *chip)
463{
37e661ee
TI		 464 int snoop_type = azx_get_snoop_type(chip);
465
cb53c626
TI		 466 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
467 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
468 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 469 * codecs.
470 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 471 */
46f2cc80 472 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 473 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 474 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 475 }
cb53c626 476
9477c58e
TI		 477 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
478 * we need to enable snoop.
479 */
37e661ee 480 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 481 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
482 azx_snoop(chip));
cb53c626 483 update_pci_byte(chip->pci,
27fe48d9
TI		 484 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
485 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 486 }
487
488 /* For NVIDIA HDA, enable snoop */
37e661ee 489 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 490 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
491 azx_snoop(chip));
cb53c626
TI		 492 update_pci_byte(chip->pci,
493 NVIDIA_HDA_TRANSREG_ADDR,
494 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 495 update_pci_byte(chip->pci,
496 NVIDIA_HDA_ISTRM_COH,
497 0x01, NVIDIA_HDA_ENABLE_COHBIT);
498 update_pci_byte(chip->pci,
499 NVIDIA_HDA_OSTRM_COH,
500 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 501 }
502
503 /* Enable SCH/PCH snoop if needed */
37e661ee 504 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 505 unsigned short snoop;
90a5ad52 506 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 507 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
508 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
509 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
510 if (!azx_snoop(chip))
511 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
512 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 513 pci_read_config_word(chip->pci,
514 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 515 }
4e76a883
TI		 516 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
517 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
518 "Disabled" : "Enabled");
da3fca21 519 }
1da177e4
LT		 520}
521
7c23b7c1
LH		 522/*
523 * In BXT-P A0, HD-Audio DMA requests is later than expected,
524 * and makes an audio stream sensitive to system latencies when
525 * 24/32 bits are playing.
526 * Adjusting threshold of DMA fifo to force the DMA request
527 * sooner to improve latency tolerance at the expense of power.
528 */
529static void bxt_reduce_dma_latency(struct azx *chip)
530{
531 u32 val;
532
533 val = azx_readl(chip, SKL_EM4L);
534 val &= (0x3 << 20);
535 azx_writel(chip, SKL_EM4L, val);
536}
537
0a673521
LH		 538static void hda_intel_init_chip(struct azx *chip, bool full_reset)
539{
98d8fc6c 540 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 541 struct pci_dev *pci = chip->pci;
6639484d 542 u32 val;
0a673521
LH		 543
544 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 545 snd_hdac_set_codec_wakeup(bus, true);
7e31a015 546 if (IS_SKL_PLUS(pci)) {
6639484d
LY		 547 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
548 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
549 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
550 }
0a673521 551 azx_init_chip(chip, full_reset);
7e31a015 552 if (IS_SKL_PLUS(pci)) {
6639484d
LY		 553 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
554 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
555 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
556 }
0a673521 557 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 558 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 559
560 /* reduce dma latency to avoid noise */
7e31a015 561 if (IS_BXT(pci))
7c23b7c1 562 bxt_reduce_dma_latency(chip);
0a673521
LH		 563}
564
b6050ef6
TI		 565/* calculate runtime delay from LPIB */
566static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
567 unsigned int pos)
568{
7833c3f8 569 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 570 int stream = substream->stream;
571 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
572 int delay;
573
574 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
575 delay = pos - lpib_pos;
576 else
577 delay = lpib_pos - pos;
578 if (delay < 0) {
7833c3f8 579 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 580 delay = 0;
581 else
7833c3f8 582 delay += azx_dev->core.bufsize;
b6050ef6
TI		 583 }
584
7833c3f8 585 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 586 dev_info(chip->card->dev,
587 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 588 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 589 delay = 0;
590 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
591 chip->get_delay[stream] = NULL;
592 }
593
594 return bytes_to_frames(substream->runtime, delay);
595}
596
9ad593f6
TI		 597static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
598
7ca954a8
DR		 599/* called from IRQ */
600static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
601{
9a34af4a 602 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 603 int ok;
604
605 ok = azx_position_ok(chip, azx_dev);
606 if (ok == 1) {
607 azx_dev->irq_pending = 0;
608 return ok;
2f35c630 609 } else if (ok == 0) {
7ca954a8
DR		 610 /* bogus IRQ, process it later */
611 azx_dev->irq_pending = 1;
2f35c630 612 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 613 }
614 return 0;
615}
616
17eccb27
ML		 617/* Enable/disable i915 display power for the link */
618static int azx_intel_link_power(struct azx *chip, bool enable)
619{
98d8fc6c 620 struct hdac_bus *bus = azx_bus(chip);
17eccb27 621
98d8fc6c 622 return snd_hdac_display_power(bus, enable);
17eccb27
ML		 623}
624
9ad593f6
TI		 625/*
626 * Check whether the current DMA position is acceptable for updating
627 * periods. Returns non-zero if it's OK.
628 *
629 * Many HD-audio controllers appear pretty inaccurate about
630 * the update-IRQ timing. The IRQ is issued before actually the
631 * data is processed. So, we need to process it afterwords in a
632 * workqueue.
633 */
634static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
635{
7833c3f8 636 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 637 int stream = substream->stream;
e5463720 638 u32 wallclk;
9ad593f6
TI		 639 unsigned int pos;
640
7833c3f8
TI		 641 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
642 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 643 return -1; /* bogus (too early) interrupt */
fa00e046 644
b6050ef6
TI		 645 if (chip->get_position[stream])
646 pos = chip->get_position[stream](chip, azx_dev);
647 else { /* use the position buffer as default */
648 pos = azx_get_pos_posbuf(chip, azx_dev);
649 if (!pos || pos == (u32)-1) {
650 dev_info(chip->card->dev,
651 "Invalid position buffer, using LPIB read method instead.\n");
652 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 653 if (chip->get_position[0] == azx_get_pos_lpib &&
654 chip->get_position[1] == azx_get_pos_lpib)
655 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 656 pos = azx_get_pos_lpib(chip, azx_dev);
657 chip->get_delay[stream] = NULL;
658 } else {
659 chip->get_position[stream] = azx_get_pos_posbuf;
660 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
661 chip->get_delay[stream] = azx_get_delay_from_lpib;
662 }
663 }
664
7833c3f8 665 if (pos >= azx_dev->core.bufsize)
b6050ef6 666 pos = 0;
9ad593f6 667
7833c3f8 668 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 669 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 670 return -1; /* this shouldn't happen! */
7833c3f8
TI		 671 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
672 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 673 /* NG - it's below the first next period boundary */
4f0189be 674 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 675 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 676 return 1; /* OK, it's fine */
677}
678
679/*
680 * The work for pending PCM period updates.
681 */
682static void azx_irq_pending_work(struct work_struct *work)
683{
9a34af4a
TI		 684 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
685 struct azx *chip = &hda->chip;
7833c3f8
TI		 686 struct hdac_bus *bus = azx_bus(chip);
687 struct hdac_stream *s;
688 int pending, ok;
9ad593f6 689
9a34af4a 690 if (!hda->irq_pending_warned) {
4e76a883
TI		 691 dev_info(chip->card->dev,
692 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
693 chip->card->number);
9a34af4a 694 hda->irq_pending_warned = 1;
a6a950a8
TI		 695 }
696
9ad593f6
TI		 697 for (;;) {
698 pending = 0;
a41d1224 699 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 700 list_for_each_entry(s, &bus->stream_list, list) {
701 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 702 if (!azx_dev->irq_pending ||
7833c3f8
TI		 703 !s->substream ||
704 !s->running)
9ad593f6 705 continue;
e5463720
JK		 706 ok = azx_position_ok(chip, azx_dev);
707 if (ok > 0) {
9ad593f6 708 azx_dev->irq_pending = 0;
a41d1224 709 spin_unlock(&bus->reg_lock);
7833c3f8 710 snd_pcm_period_elapsed(s->substream);
a41d1224 711 spin_lock(&bus->reg_lock);
e5463720
JK		 712 } else if (ok < 0) {
713 pending = 0; /* too early */
9ad593f6
TI		 714 } else
715 pending++;
716 }
a41d1224 717 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 718 if (!pending)
719 return;
08af495f 720 msleep(1);
9ad593f6
TI		 721 }
722}
723
724/* clear irq_pending flags and assure no on-going workq */
725static void azx_clear_irq_pending(struct azx *chip)
726{
7833c3f8
TI		 727 struct hdac_bus *bus = azx_bus(chip);
728 struct hdac_stream *s;
9ad593f6 729
a41d1224 730 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 731 list_for_each_entry(s, &bus->stream_list, list) {
732 struct azx_dev *azx_dev = stream_to_azx_dev(s);
733 azx_dev->irq_pending = 0;
734 }
a41d1224 735 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 736}
737
68e7fffc
TI		 738static int azx_acquire_irq(struct azx *chip, int do_disconnect)
739{
a41d1224
TI		 740 struct hdac_bus *bus = azx_bus(chip);
741
437a5a46
TI		 742 if (request_irq(chip->pci->irq, azx_interrupt,
743 chip->msi ? 0 : IRQF_SHARED,
de65360b 744 chip->card->irq_descr, chip)) {
4e76a883
TI		 745 dev_err(chip->card->dev,
746 "unable to grab IRQ %d, disabling device\n",
747 chip->pci->irq);
68e7fffc
TI		 748 if (do_disconnect)
749 snd_card_disconnect(chip->card);
750 return -1;
751 }
a41d1224 752 bus->irq = chip->pci->irq;
69e13418 753 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 754 return 0;
755}
756
b6050ef6
TI		 757/* get the current DMA position with correction on VIA chips */
758static unsigned int azx_via_get_position(struct azx *chip,
759 struct azx_dev *azx_dev)
760{
761 unsigned int link_pos, mini_pos, bound_pos;
762 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
763 unsigned int fifo_size;
764
1604eeee 765 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 766 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 767 /* Playback, no problem using link position */
768 return link_pos;
769 }
770
771 /* Capture */
772 /* For new chipset,
773 * use mod to get the DMA position just like old chipset
774 */
7833c3f8
TI		 775 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
776 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 777
778 /* azx_dev->fifo_size can't get FIFO size of in stream.
779 * Get from base address + offset.
780 */
a41d1224
TI		 781 fifo_size = readw(azx_bus(chip)->remap_addr +
782 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 783
784 if (azx_dev->insufficient) {
785 /* Link position never gather than FIFO size */
786 if (link_pos <= fifo_size)
787 return 0;
788
789 azx_dev->insufficient = 0;
790 }
791
792 if (link_pos <= fifo_size)
7833c3f8 793 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 794 else
795 mini_pos = link_pos - fifo_size;
796
797 /* Find nearest previous boudary */
7833c3f8
TI		 798 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
799 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 800 if (mod_link_pos >= fifo_size)
801 bound_pos = link_pos - mod_link_pos;
802 else if (mod_dma_pos >= mod_mini_pos)
803 bound_pos = mini_pos - mod_mini_pos;
804 else {
7833c3f8
TI		 805 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
806 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 807 bound_pos = 0;
808 }
809
810 /* Calculate real DMA position we want */
811 return bound_pos + mod_dma_pos;
812}
813
83012a7c 814#ifdef CONFIG_PM
65fcd41d
TI		 815static DEFINE_MUTEX(card_list_lock);
816static LIST_HEAD(card_list);
817
818static void azx_add_card_list(struct azx *chip)
819{
9a34af4a 820 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 821 mutex_lock(&card_list_lock);
9a34af4a 822 list_add(&hda->list, &card_list);
65fcd41d
TI		 823 mutex_unlock(&card_list_lock);
824}
825
826static void azx_del_card_list(struct azx *chip)
827{
9a34af4a 828 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 829 mutex_lock(&card_list_lock);
9a34af4a 830 list_del_init(&hda->list);
65fcd41d
TI		 831 mutex_unlock(&card_list_lock);
832}
833
834/* trigger power-save check at writing parameter */
835static int param_set_xint(const char *val, const struct kernel_param *kp)
836{
9a34af4a 837 struct hda_intel *hda;
65fcd41d 838 struct azx *chip;
65fcd41d
TI		 839 int prev = power_save;
840 int ret = param_set_int(val, kp);
841
842 if (ret || prev == power_save)
843 return ret;
844
845 mutex_lock(&card_list_lock);
9a34af4a
TI		 846 list_for_each_entry(hda, &card_list, list) {
847 chip = &hda->chip;
a41d1224 848 if (!hda->probe_continued || chip->disabled)
65fcd41d 849 continue;
a41d1224 850 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 851 }
852 mutex_unlock(&card_list_lock);
853 return 0;
854}
855#else
856#define azx_add_card_list(chip) /* NOP */
857#define azx_del_card_list(chip) /* NOP */
83012a7c 858#endif /* CONFIG_PM */
5c0b9bec 859
98d8fc6c
ML		 860/* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
861 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
862 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
863 * BCLK = CDCLK * M / N
864 * The values will be lost when the display power well is disabled and need to
865 * be restored to avoid abnormal playback speed.
866 */
867static void haswell_set_bclk(struct hda_intel *hda)
868{
869 struct azx *chip = &hda->chip;
870 int cdclk_freq;
871 unsigned int bclk_m, bclk_n;
872
873 if (!hda->need_i915_power)
874 return;
875
876 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
877 switch (cdclk_freq) {
878 case 337500:
879 bclk_m = 16;
880 bclk_n = 225;
881 break;
882
883 case 450000:
884 default: /* default CDCLK 450MHz */
885 bclk_m = 4;
886 bclk_n = 75;
887 break;
888
889 case 540000:
890 bclk_m = 4;
891 bclk_n = 90;
892 break;
893
894 case 675000:
895 bclk_m = 8;
896 bclk_n = 225;
897 break;
898 }
899
900 azx_writew(chip, HSW_EM4, bclk_m);
901 azx_writew(chip, HSW_EM5, bclk_n);
902}
903
7ccbde57 904#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 905/*
906 * power management
907 */
68cb2b55 908static int azx_suspend(struct device *dev)
1da177e4 909{
68cb2b55 910 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 911 struct azx *chip;
912 struct hda_intel *hda;
a41d1224 913 struct hdac_bus *bus;
1da177e4 914
2d9772ef
TI		 915 if (!card)
916 return 0;
917
918 chip = card->private_data;
919 hda = container_of(chip, struct hda_intel, chip);
342e8449 920 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 921 return 0;
922
a41d1224 923 bus = azx_bus(chip);
421a1252 924 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 925 azx_clear_irq_pending(chip);
cb53c626 926 azx_stop_chip(chip);
7295b264 927 azx_enter_link_reset(chip);
a41d1224
TI		 928 if (bus->irq >= 0) {
929 free_irq(bus->irq, chip);
930 bus->irq = -1;
30b35399 931 }
a07187c9 932
68e7fffc 933 if (chip->msi)
43001c95 934 pci_disable_msi(chip->pci);
795614dd
ML		 935 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
936 && hda->need_i915_power)
98d8fc6c 937 snd_hdac_display_power(bus, false);
785d8c4b
LY		 938
939 trace_azx_suspend(chip);
1da177e4
LT		 940 return 0;
941}
942
68cb2b55 943static int azx_resume(struct device *dev)
1da177e4 944{
68cb2b55
TI		 945 struct pci_dev *pci = to_pci_dev(dev);
946 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 947 struct azx *chip;
948 struct hda_intel *hda;
949
950 if (!card)
951 return 0;
1da177e4 952
2d9772ef
TI		 953 chip = card->private_data;
954 hda = container_of(chip, struct hda_intel, chip);
342e8449 955 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 956 return 0;
957
795614dd
ML		 958 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
959 && hda->need_i915_power) {
98d8fc6c 960 snd_hdac_display_power(azx_bus(chip), true);
926981ae 961 haswell_set_bclk(hda);
a07187c9 962 }
68e7fffc
TI		 963 if (chip->msi)
964 if (pci_enable_msi(pci) < 0)
965 chip->msi = 0;
966 if (azx_acquire_irq(chip, 1) < 0)
30b35399 967 return -EIO;
cb53c626 968 azx_init_pci(chip);
d804ad92 969
0a673521 970 hda_intel_init_chip(chip, true);
d804ad92 971
421a1252 972 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 973
974 trace_azx_resume(chip);
1da177e4
LT		 975 return 0;
976}
b8dfc462
ML		 977#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
978
3e6db33a
XZ		 979#ifdef CONFIG_PM_SLEEP
980/* put codec down to D3 at hibernation for Intel SKL+;
981 * otherwise BIOS may still access the codec and screw up the driver
982 */
3e6db33a
XZ		 983static int azx_freeze_noirq(struct device *dev)
984{
985 struct pci_dev *pci = to_pci_dev(dev);
986
987 if (IS_SKL_PLUS(pci))
988 pci_set_power_state(pci, PCI_D3hot);
989
990 return 0;
991}
992
993static int azx_thaw_noirq(struct device *dev)
994{
995 struct pci_dev *pci = to_pci_dev(dev);
996
997 if (IS_SKL_PLUS(pci))
998 pci_set_power_state(pci, PCI_D0);
999
1000 return 0;
1001}
1002#endif /* CONFIG_PM_SLEEP */
1003
641d334b 1004#ifdef CONFIG_PM
b8dfc462
ML		 1005static int azx_runtime_suspend(struct device *dev)
1006{
1007 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1008 struct azx *chip;
1009 struct hda_intel *hda;
b8dfc462 1010
2d9772ef
TI		 1011 if (!card)
1012 return 0;
1013
1014 chip = card->private_data;
1015 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1016 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1017 return 0;
1018
364aa716 1019 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1020 return 0;
1021
7d4f606c
WX		 1022 /* enable controller wake up event */
1023 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1024 STATESTS_INT_MASK);
1025
b8dfc462 1026 azx_stop_chip(chip);
873ce8ad 1027 azx_enter_link_reset(chip);
b8dfc462 1028 azx_clear_irq_pending(chip);
795614dd
ML		 1029 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1030 && hda->need_i915_power)
98d8fc6c 1031 snd_hdac_display_power(azx_bus(chip), false);
e4d9e513 1032
785d8c4b 1033 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1034 return 0;
1035}
1036
1037static int azx_runtime_resume(struct device *dev)
1038{
1039 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1040 struct azx *chip;
1041 struct hda_intel *hda;
98d8fc6c 1042 struct hdac_bus *bus;
7d4f606c
WX		 1043 struct hda_codec *codec;
1044 int status;
b8dfc462 1045
2d9772ef
TI		 1046 if (!card)
1047 return 0;
1048
1049 chip = card->private_data;
1050 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1051 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1052 return 0;
1053
364aa716 1054 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1055 return 0;
1056
033ea349
DH		 1057 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1058 bus = azx_bus(chip);
1059 if (hda->need_i915_power) {
1060 snd_hdac_display_power(bus, true);
1061 haswell_set_bclk(hda);
1062 } else {
1063 /* toggle codec wakeup bit for STATESTS read */
1064 snd_hdac_set_codec_wakeup(bus, true);
1065 snd_hdac_set_codec_wakeup(bus, false);
1066 }
a07187c9 1067 }
7d4f606c
WX		 1068
1069 /* Read STATESTS before controller reset */
1070 status = azx_readw(chip, STATESTS);
1071
b8dfc462 1072 azx_init_pci(chip);
0a673521 1073 hda_intel_init_chip(chip, true);
7d4f606c 1074
a41d1224
TI		 1075 if (status) {
1076 list_for_each_codec(codec, &chip->bus)
7d4f606c 1077 if (status & (1 << codec->addr))
2f35c630
TI		 1078 schedule_delayed_work(&codec->jackpoll_work,
1079 codec->jackpoll_interval);
7d4f606c
WX		 1080 }
1081
1082 /* disable controller Wake Up event*/
1083 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1084 ~STATESTS_INT_MASK);
1085
785d8c4b 1086 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1087 return 0;
1088}
6eb827d2
TI		 1089
1090static int azx_runtime_idle(struct device *dev)
1091{
1092 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1093 struct azx *chip;
1094 struct hda_intel *hda;
1095
1096 if (!card)
1097 return 0;
6eb827d2 1098
2d9772ef
TI		 1099 chip = card->private_data;
1100 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1101 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1102 return 0;
1103
55ed9cd1 1104 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1105 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1106 return -EBUSY;
1107
1108 return 0;
1109}
1110
b8dfc462
ML		 1111static const struct dev_pm_ops azx_pm = {
1112 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1113#ifdef CONFIG_PM_SLEEP
1114 .freeze_noirq = azx_freeze_noirq,
1115 .thaw_noirq = azx_thaw_noirq,
1116#endif
6eb827d2 1117 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1118};
1119
68cb2b55
TI		 1120#define AZX_PM_OPS &azx_pm
1121#else
68cb2b55 1122#define AZX_PM_OPS NULL
b8dfc462 1123#endif /* CONFIG_PM */
1da177e4
LT		 1124
1125
48c8b0eb 1126static int azx_probe_continue(struct azx *chip);
a82d51ed 1127
8393ec4a 1128#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1129static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1130
a82d51ed
TI		 1131static void azx_vs_set_state(struct pci_dev *pci,
1132 enum vga_switcheroo_state state)
1133{
1134 struct snd_card *card = pci_get_drvdata(pci);
1135 struct azx *chip = card->private_data;
9a34af4a 1136 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1137 bool disabled;
1138
9a34af4a
TI		 1139 wait_for_completion(&hda->probe_wait);
1140 if (hda->init_failed)
a82d51ed
TI		 1141 return;
1142
1143 disabled = (state == VGA_SWITCHEROO_OFF);
1144 if (chip->disabled == disabled)
1145 return;
1146
a41d1224 1147 if (!hda->probe_continued) {
a82d51ed
TI		 1148 chip->disabled = disabled;
1149 if (!disabled) {
4e76a883
TI		 1150 dev_info(chip->card->dev,
1151 "Start delayed initialization\n");
5c90680e 1152 if (azx_probe_continue(chip) < 0) {
4e76a883 1153 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1154 hda->init_failed = true;
a82d51ed
TI		 1155 }
1156 }
1157 } else {
2b760d88 1158 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1159 disabled ? "Disabling" : "Enabling");
a82d51ed 1160 if (disabled) {
8928756d
DR		 1161 pm_runtime_put_sync_suspend(card->dev);
1162 azx_suspend(card->dev);
2b760d88 1163 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1164 * however we have no ACPI handle, so pci/acpi can't put us there,
1165 * put ourselves there */
1166 pci->current_state = PCI_D3cold;
a82d51ed 1167 chip->disabled = true;
a41d1224 1168 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1169 dev_warn(chip->card->dev,
1170 "Cannot lock devices!\n");
a82d51ed 1171 } else {
a41d1224 1172 snd_hda_unlock_devices(&chip->bus);
8928756d 1173 pm_runtime_get_noresume(card->dev);
a82d51ed 1174 chip->disabled = false;
8928756d 1175 azx_resume(card->dev);
a82d51ed
TI		 1176 }
1177 }
1178}
1179
1180static bool azx_vs_can_switch(struct pci_dev *pci)
1181{
1182 struct snd_card *card = pci_get_drvdata(pci);
1183 struct azx *chip = card->private_data;
9a34af4a 1184 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1185
9a34af4a
TI		 1186 wait_for_completion(&hda->probe_wait);
1187 if (hda->init_failed)
a82d51ed 1188 return false;
a41d1224 1189 if (chip->disabled || !hda->probe_continued)
a82d51ed 1190 return true;
a41d1224 1191 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1192 return false;
a41d1224 1193 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1194 return true;
1195}
1196
e23e7a14 1197static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1198{
9a34af4a 1199 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1200 struct pci_dev *p = get_bound_vga(chip->pci);
1201 if (p) {
4e76a883 1202 dev_info(chip->card->dev,
2b760d88 1203 "Handle vga_switcheroo audio client\n");
9a34af4a 1204 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1205 pci_dev_put(p);
1206 }
1207}
1208
1209static const struct vga_switcheroo_client_ops azx_vs_ops = {
1210 .set_gpu_state = azx_vs_set_state,
1211 .can_switch = azx_vs_can_switch,
1212};
1213
e23e7a14 1214static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1215{
9a34af4a 1216 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1217 int err;
1218
9a34af4a 1219 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1220 return 0;
1221 /* FIXME: currently only handling DIS controller
1222 * is there any machine with two switchable HDMI audio controllers?
1223 */
128960a9 1224 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
21b45676 1225 VGA_SWITCHEROO_DIS);
128960a9
TI		 1226 if (err < 0)
1227 return err;
9a34af4a 1228 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1229
1230 /* register as an optimus hdmi audio power domain */
8928756d 1231 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1232 &hda->hdmi_pm_domain);
128960a9 1233 return 0;
a82d51ed
TI		 1234}
1235#else
1236#define init_vga_switcheroo(chip) /* NOP */
1237#define register_vga_switcheroo(chip) 0
8393ec4a 1238#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1239#endif /* SUPPORT_VGA_SWITCHER */
1240
1da177e4
LT		 1241/*
1242 * destructor
1243 */
a98f90fd 1244static int azx_free(struct azx *chip)
1da177e4 1245{
c67e2228 1246 struct pci_dev *pci = chip->pci;
a07187c9 1247 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1248 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1249
364aa716 1250 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1251 pm_runtime_get_noresume(&pci->dev);
1252
65fcd41d
TI		 1253 azx_del_card_list(chip);
1254
9a34af4a
TI		 1255 hda->init_failed = 1; /* to be sure */
1256 complete_all(&hda->probe_wait);
f4c482a4 1257
9a34af4a 1258 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1259 if (chip->disabled && hda->probe_continued)
1260 snd_hda_unlock_devices(&chip->bus);
9a34af4a 1261 if (hda->vga_switcheroo_registered)
128960a9 1262 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1263 }
1264
a41d1224 1265 if (bus->chip_init) {
9ad593f6 1266 azx_clear_irq_pending(chip);
7833c3f8 1267 azx_stop_all_streams(chip);
cb53c626 1268 azx_stop_chip(chip);
1da177e4
LT		 1269 }
1270
a41d1224
TI		 1271 if (bus->irq >= 0)
1272 free_irq(bus->irq, (void*)chip);
68e7fffc 1273 if (chip->msi)
30b35399 1274 pci_disable_msi(chip->pci);
a41d1224 1275 iounmap(bus->remap_addr);
1da177e4 1276
67908994 1277 azx_free_stream_pages(chip);
a41d1224
TI		 1278 azx_free_streams(chip);
1279 snd_hdac_bus_exit(bus);
1280
a82d51ed
TI		 1281 if (chip->region_requested)
1282 pci_release_regions(chip->pci);
a41d1224 1283
1da177e4 1284 pci_disable_device(chip->pci);
4918cdab 1285#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1286 release_firmware(chip->fw);
4918cdab 1287#endif
98d8fc6c 1288
99a2008d 1289 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
795614dd 1290 if (hda->need_i915_power)
98d8fc6c
ML		 1291 snd_hdac_display_power(bus, false);
1292 snd_hdac_i915_exit(bus);
99a2008d 1293 }
a07187c9 1294 kfree(hda);
1da177e4
LT		 1295
1296 return 0;
1297}
1298
a41d1224
TI		 1299static int azx_dev_disconnect(struct snd_device *device)
1300{
1301 struct azx *chip = device->device_data;
1302
1303 chip->bus.shutdown = 1;
1304 return 0;
1305}
1306
a98f90fd 1307static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1308{
1309 return azx_free(device->device_data);
1310}
1311
8393ec4a 1312#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1313/*
2b760d88 1314 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1315 */
e23e7a14 1316static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1317{
1318 struct pci_dev *p;
1319
1320 /* check only discrete GPU */
1321 switch (pci->vendor) {
1322 case PCI_VENDOR_ID_ATI:
1323 case PCI_VENDOR_ID_AMD:
1324 case PCI_VENDOR_ID_NVIDIA:
1325 if (pci->devfn == 1) {
1326 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1327 pci->bus->number, 0);
1328 if (p) {
1329 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1330 return p;
1331 pci_dev_put(p);
1332 }
1333 }
1334 break;
1335 }
1336 return NULL;
1337}
1338
e23e7a14 1339static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1340{
1341 bool vga_inactive = false;
1342 struct pci_dev *p = get_bound_vga(pci);
1343
1344 if (p) {
12b78a7f 1345 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1346 vga_inactive = true;
1347 pci_dev_put(p);
1348 }
1349 return vga_inactive;
1350}
8393ec4a 1351#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1352
3372a153
TI		 1353/*
1354 * white/black-listing for position_fix
1355 */
e23e7a14 1356static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1357 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1358 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1359 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1360 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1361 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1362 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1363 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1364 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1365 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1366 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1367 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1368 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1369 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1370 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1371 {}
1372};
1373
e23e7a14 1374static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1375{
1376 const struct snd_pci_quirk *q;
1377
c673ba1c 1378 switch (fix) {
1dac6695 1379 case POS_FIX_AUTO:
c673ba1c
TI		 1380 case POS_FIX_LPIB:
1381 case POS_FIX_POSBUF:
4cb36310 1382 case POS_FIX_VIACOMBO:
a6f2fd55 1383 case POS_FIX_COMBO:
c673ba1c
TI		 1384 return fix;
1385 }
1386
c673ba1c
TI		 1387 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1388 if (q) {
4e76a883
TI		 1389 dev_info(chip->card->dev,
1390 "position_fix set to %d for device %04x:%04x\n",
1391 q->value, q->subvendor, q->subdevice);
c673ba1c 1392 return q->value;
3372a153 1393 }
bdd9ef24
DH		 1394
1395 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1396 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1397 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1398 return POS_FIX_VIACOMBO;
9477c58e
TI		 1399 }
1400 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1401 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1402 return POS_FIX_LPIB;
bdd9ef24 1403 }
c673ba1c 1404 return POS_FIX_AUTO;
3372a153
TI		 1405}
1406
b6050ef6
TI		 1407static void assign_position_fix(struct azx *chip, int fix)
1408{
1409 static azx_get_pos_callback_t callbacks[] = {
1410 [POS_FIX_AUTO] = NULL,
1411 [POS_FIX_LPIB] = azx_get_pos_lpib,
1412 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1413 [POS_FIX_VIACOMBO] = azx_via_get_position,
1414 [POS_FIX_COMBO] = azx_get_pos_lpib,
1415 };
1416
1417 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1418
1419 /* combo mode uses LPIB only for playback */
1420 if (fix == POS_FIX_COMBO)
1421 chip->get_position[1] = NULL;
1422
1423 if (fix == POS_FIX_POSBUF &&
1424 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1425 chip->get_delay[0] = chip->get_delay[1] =
1426 azx_get_delay_from_lpib;
1427 }
1428
1429}
1430
669ba27a
TI		 1431/*
1432 * black-lists for probe_mask
1433 */
e23e7a14 1434static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1435 /* Thinkpad often breaks the controller communication when accessing
1436 * to the non-working (or non-existing) modem codec slot.
1437 */
1438 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1439 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1440 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1441 /* broken BIOS */
1442 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1443 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1444 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1445 /* forced codec slots */
93574844 1446 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1447 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1448 /* WinFast VP200 H (Teradici) user reported broken communication */
1449 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1450 {}
1451};
1452
f1eaaeec
TI		 1453#define AZX_FORCE_CODEC_MASK 0x100
1454
e23e7a14 1455static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1456{
1457 const struct snd_pci_quirk *q;
1458
f1eaaeec
TI		 1459 chip->codec_probe_mask = probe_mask[dev];
1460 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1461 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1462 if (q) {
4e76a883
TI		 1463 dev_info(chip->card->dev,
1464 "probe_mask set to 0x%x for device %04x:%04x\n",
1465 q->value, q->subvendor, q->subdevice);
f1eaaeec 1466 chip->codec_probe_mask = q->value;
669ba27a
TI		 1467 }
1468 }
f1eaaeec
TI		 1469
1470 /* check forced option */
1471 if (chip->codec_probe_mask != -1 &&
1472 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1473 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1474 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1475 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1476 }
669ba27a
TI		 1477}
1478
4d8e22e0 1479/*
71623855 1480 * white/black-list for enable_msi
4d8e22e0 1481 */
e23e7a14 1482static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1483 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1484 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1485 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1486 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1487 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1488 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1489 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1490 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1491 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1492 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1493 {}
1494};
1495
e23e7a14 1496static void check_msi(struct azx *chip)
4d8e22e0
TI		 1497{
1498 const struct snd_pci_quirk *q;
1499
71623855
TI		 1500 if (enable_msi >= 0) {
1501 chip->msi = !!enable_msi;
4d8e22e0 1502 return;
71623855
TI		 1503 }
1504 chip->msi = 1; /* enable MSI as default */
1505 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1506 if (q) {
4e76a883
TI		 1507 dev_info(chip->card->dev,
1508 "msi for device %04x:%04x set to %d\n",
1509 q->subvendor, q->subdevice, q->value);
4d8e22e0 1510 chip->msi = q->value;
80c43ed7
TI		 1511 return;
1512 }
1513
1514 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1515 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1516 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1517 chip->msi = 0;
4d8e22e0
TI		 1518 }
1519}
1520
a1585d76 1521/* check the snoop mode availability */
e23e7a14 1522static void azx_check_snoop_available(struct azx *chip)
a1585d76 1523{
7c732015 1524 int snoop = hda_snoop;
a1585d76 1525
7c732015
TI		 1526 if (snoop >= 0) {
1527 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1528 snoop ? "snoop" : "non-snoop");
1529 chip->snoop = snoop;
1530 return;
1531 }
1532
1533 snoop = true;
37e661ee
TI		 1534 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1535 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1536 /* force to non-snoop mode for a new VIA controller
1537 * when BIOS is set
1538 */
7c732015
TI		 1539 u8 val;
1540 pci_read_config_byte(chip->pci, 0x42, &val);
1541 if (!(val & 0x80) && chip->pci->revision == 0x30)
1542 snoop = false;
a1585d76
TI		 1543 }
1544
37e661ee
TI		 1545 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1546 snoop = false;
1547
7c732015
TI		 1548 chip->snoop = snoop;
1549 if (!snoop)
1550 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1551}
669ba27a 1552
99a2008d
WX		 1553static void azx_probe_work(struct work_struct *work)
1554{
9a34af4a
TI		 1555 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1556 azx_probe_continue(&hda->chip);
99a2008d 1557}
99a2008d 1558
4f0189be
TI		 1559static int default_bdl_pos_adj(struct azx *chip)
1560{
2cf721db
TI		 1561 /* some exceptions: Atoms seem problematic with value 1 */
1562 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1563 switch (chip->pci->device) {
1564 case 0x0f04: /* Baytrail */
1565 case 0x2284: /* Braswell */
1566 return 32;
1567 }
1568 }
1569
4f0189be
TI		 1570 switch (chip->driver_type) {
1571 case AZX_DRIVER_ICH:
1572 case AZX_DRIVER_PCH:
1573 return 1;
1574 default:
1575 return 32;
1576 }
1577}
1578
1da177e4
LT		 1579/*
1580 * constructor
1581 */
a43ff5ba
TI		 1582static const struct hdac_io_ops pci_hda_io_ops;
1583static const struct hda_controller_ops pci_hda_ops;
1584
e23e7a14
BP		 1585static int azx_create(struct snd_card *card, struct pci_dev *pci,
1586 int dev, unsigned int driver_caps,
1587 struct azx **rchip)
1da177e4 1588{
a98f90fd 1589 static struct snd_device_ops ops = {
a41d1224 1590 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1591 .dev_free = azx_dev_free,
1592 };
a07187c9 1593 struct hda_intel *hda;
a82d51ed
TI		 1594 struct azx *chip;
1595 int err;
1da177e4
LT		 1596
1597 *rchip = NULL;
bcd72003 1598
927fc866
PM		 1599 err = pci_enable_device(pci);
1600 if (err < 0)
1da177e4
LT		 1601 return err;
1602
a07187c9
ML		 1603 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1604 if (!hda) {
1da177e4
LT		 1605 pci_disable_device(pci);
1606 return -ENOMEM;
1607 }
1608
a07187c9 1609 chip = &hda->chip;
62932df8 1610 mutex_init(&chip->open_mutex);
1da177e4
LT		 1611 chip->card = card;
1612 chip->pci = pci;
a43ff5ba 1613 chip->ops = &pci_hda_ops;
9477c58e
TI		 1614 chip->driver_caps = driver_caps;
1615 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1616 check_msi(chip);
555e219f 1617 chip->dev_index = dev;
749ee287 1618 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1619 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1620 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1621 INIT_LIST_HEAD(&hda->list);
a82d51ed 1622 init_vga_switcheroo(chip);
9a34af4a 1623 init_completion(&hda->probe_wait);
1da177e4 1624
b6050ef6 1625 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1626
5aba4f8e 1627 check_probe_mask(chip, dev);
3372a153 1628
27346166 1629 chip->single_cmd = single_cmd;
a1585d76 1630 azx_check_snoop_available(chip);
c74db86b 1631
4f0189be
TI		 1632 if (bdl_pos_adj[dev] < 0)
1633 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1634 else
1635 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1636
a41d1224
TI		 1637 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1638 if (err < 0) {
1639 kfree(hda);
1640 pci_disable_device(pci);
1641 return err;
1642 }
1643
7d9a1808
TI		 1644 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1645 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1646 chip->bus.needs_damn_long_delay = 1;
1647 }
1648
a82d51ed
TI		 1649 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1650 if (err < 0) {
4e76a883 1651 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1652 azx_free(chip);
1653 return err;
1654 }
1655
99a2008d 1656 /* continue probing in work context as may trigger request module */
9a34af4a 1657 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1658
a82d51ed 1659 *rchip = chip;
99a2008d 1660
a82d51ed
TI		 1661 return 0;
1662}
1663
48c8b0eb 1664static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1665{
1666 int dev = chip->dev_index;
1667 struct pci_dev *pci = chip->pci;
1668 struct snd_card *card = chip->card;
a41d1224 1669 struct hdac_bus *bus = azx_bus(chip);
67908994 1670 int err;
a82d51ed 1671 unsigned short gcap;
413cbf46 1672 unsigned int dma_bits = 64;
a82d51ed 1673
07e4ca50
TI		 1674#if BITS_PER_LONG != 64
1675 /* Fix up base address on ULI M5461 */
1676 if (chip->driver_type == AZX_DRIVER_ULI) {
1677 u16 tmp3;
1678 pci_read_config_word(pci, 0x40, &tmp3);
1679 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1680 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1681 }
1682#endif
1683
927fc866 1684 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1685 if (err < 0)
1da177e4 1686 return err;
a82d51ed 1687 chip->region_requested = 1;
1da177e4 1688
a41d1224
TI		 1689 bus->addr = pci_resource_start(pci, 0);
1690 bus->remap_addr = pci_ioremap_bar(pci, 0);
1691 if (bus->remap_addr == NULL) {
4e76a883 1692 dev_err(card->dev, "ioremap error\n");
a82d51ed 1693 return -ENXIO;
1da177e4
LT		 1694 }
1695
db79afa1
BH		 1696 if (chip->msi) {
1697 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1698 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1699 pci->no_64bit_msi = true;
1700 }
68e7fffc
TI		 1701 if (pci_enable_msi(pci) < 0)
1702 chip->msi = 0;
db79afa1 1703 }
7376d013 1704
a82d51ed
TI		 1705 if (azx_acquire_irq(chip, 0) < 0)
1706 return -EBUSY;
1da177e4
LT		 1707
1708 pci_set_master(pci);
a41d1224 1709 synchronize_irq(bus->irq);
1da177e4 1710
bcd72003 1711 gcap = azx_readw(chip, GCAP);
4e76a883 1712 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1713
413cbf46
TI		 1714 /* AMD devices support 40 or 48bit DMA, take the safe one */
1715 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1716 dma_bits = 40;
1717
dc4c2e6b 1718 /* disable SB600 64bit support for safety */
9477c58e 1719 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1720 struct pci_dev *p_smbus;
413cbf46 1721 dma_bits = 40;
dc4c2e6b
AB		 1722 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1723 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1724 NULL);
1725 if (p_smbus) {
1726 if (p_smbus->revision < 0x30)
fb1d8ac2 1727 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1728 pci_dev_put(p_smbus);
1729 }
1730 }
09240cf4 1731
9477c58e
TI		 1732 /* disable 64bit DMA address on some devices */
1733 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1734 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1735 gcap &= ~AZX_GCAP_64OK;
9477c58e 1736 }
396087ea 1737
2ae66c26 1738 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1739 if (align_buffer_size >= 0)
1740 chip->align_buffer_size = !!align_buffer_size;
1741 else {
103884a3 1742 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1743 chip->align_buffer_size = 0;
7bfe059e
TI		 1744 else
1745 chip->align_buffer_size = 1;
1746 }
2ae66c26 1747
cf7aaca8 1748 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1749 if (!(gcap & AZX_GCAP_64OK))
1750 dma_bits = 32;
412b979c
QL		 1751 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1752 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1753 } else {
412b979c
QL		 1754 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1755 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1756 }
cf7aaca8 1757
8b6ed8e7
TI		 1758 /* read number of streams from GCAP register instead of using
1759 * hardcoded value
1760 */
1761 chip->capture_streams = (gcap >> 8) & 0x0f;
1762 chip->playback_streams = (gcap >> 12) & 0x0f;
1763 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1764 /* gcap didn't give any info, switching to old method */
1765
1766 switch (chip->driver_type) {
1767 case AZX_DRIVER_ULI:
1768 chip->playback_streams = ULI_NUM_PLAYBACK;
1769 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1770 break;
1771 case AZX_DRIVER_ATIHDMI:
1815b34a 1772 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1773 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1774 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1775 break;
c4da29ca 1776 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1777 default:
1778 chip->playback_streams = ICH6_NUM_PLAYBACK;
1779 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1780 break;
1781 }
07e4ca50 1782 }
8b6ed8e7
TI		 1783 chip->capture_index_offset = 0;
1784 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1785 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1786
a41d1224
TI		 1787 /* initialize streams */
1788 err = azx_init_streams(chip);
81740861 1789 if (err < 0)
a82d51ed 1790 return err;
1da177e4 1791
a41d1224
TI		 1792 err = azx_alloc_stream_pages(chip);
1793 if (err < 0)
1794 return err;
1da177e4
LT		 1795
1796 /* initialize chip */
cb53c626 1797 azx_init_pci(chip);
e4d9e513 1798
926981ae
ID		 1799 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1800 struct hda_intel *hda;
1801
1802 hda = container_of(chip, struct hda_intel, chip);
1803 haswell_set_bclk(hda);
1804 }
e4d9e513 1805
0a673521 1806 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1807
1808 /* codec detection */
a41d1224 1809 if (!azx_bus(chip)->codec_mask) {
4e76a883 1810 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1811 return -ENODEV;
1da177e4
LT		 1812 }
1813
07e4ca50 1814 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1815 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1816 sizeof(card->shortname));
1817 snprintf(card->longname, sizeof(card->longname),
1818 "%s at 0x%lx irq %i",
a41d1224 1819 card->shortname, bus->addr, bus->irq);
07e4ca50 1820
1da177e4 1821 return 0;
1da177e4
LT		 1822}
1823
97c6a3d1 1824#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1825/* callback from request_firmware_nowait() */
1826static void azx_firmware_cb(const struct firmware *fw, void *context)
1827{
1828 struct snd_card *card = context;
1829 struct azx *chip = card->private_data;
1830 struct pci_dev *pci = chip->pci;
1831
1832 if (!fw) {
4e76a883 1833 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1834 goto error;
1835 }
1836
1837 chip->fw = fw;
1838 if (!chip->disabled) {
1839 /* continue probing */
1840 if (azx_probe_continue(chip))
1841 goto error;
1842 }
1843 return; /* OK */
1844
1845 error:
1846 snd_card_free(card);
1847 pci_set_drvdata(pci, NULL);
1848}
97c6a3d1 1849#endif
5cb543db 1850
40830813
DR		 1851/*
1852 * HDA controller ops.
1853 */
1854
1855/* PCI register access. */
db291e36 1856static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1857{
1858 writel(value, addr);
1859}
1860
db291e36 1861static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1862{
1863 return readl(addr);
1864}
1865
db291e36 1866static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1867{
1868 writew(value, addr);
1869}
1870
db291e36 1871static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1872{
1873 return readw(addr);
1874}
1875
db291e36 1876static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1877{
1878 writeb(value, addr);
1879}
1880
db291e36 1881static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1882{
1883 return readb(addr);
1884}
1885
f46ea609
DR		 1886static int disable_msi_reset_irq(struct azx *chip)
1887{
a41d1224 1888 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 1889 int err;
1890
a41d1224
TI		 1891 free_irq(bus->irq, chip);
1892 bus->irq = -1;
f46ea609
DR		 1893 pci_disable_msi(chip->pci);
1894 chip->msi = 0;
1895 err = azx_acquire_irq(chip, 1);
1896 if (err < 0)
1897 return err;
1898
1899 return 0;
1900}
1901
b419b35b 1902/* DMA page allocation helpers. */
a43ff5ba 1903static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 1904 int type,
1905 size_t size,
1906 struct snd_dma_buffer *buf)
1907{
a41d1224 1908 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 1909 int err;
1910
1911 err = snd_dma_alloc_pages(type,
a43ff5ba 1912 bus->dev,
b419b35b
DR		 1913 size, buf);
1914 if (err < 0)
1915 return err;
1916 mark_pages_wc(chip, buf, true);
1917 return 0;
1918}
1919
a43ff5ba 1920static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 1921{
a41d1224 1922 struct azx *chip = bus_to_azx(bus);
a43ff5ba 1923
b419b35b
DR		 1924 mark_pages_wc(chip, buf, false);
1925 snd_dma_free_pages(buf);
1926}
1927
1928static int substream_alloc_pages(struct azx *chip,
1929 struct snd_pcm_substream *substream,
1930 size_t size)
1931{
1932 struct azx_dev *azx_dev = get_azx_dev(substream);
1933 int ret;
1934
1935 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 1936 ret = snd_pcm_lib_malloc_pages(substream, size);
1937 if (ret < 0)
1938 return ret;
1939 mark_runtime_wc(chip, azx_dev, substream, true);
1940 return 0;
1941}
1942
1943static int substream_free_pages(struct azx *chip,
1944 struct snd_pcm_substream *substream)
1945{
1946 struct azx_dev *azx_dev = get_azx_dev(substream);
1947 mark_runtime_wc(chip, azx_dev, substream, false);
1948 return snd_pcm_lib_free_pages(substream);
1949}
1950
8769b278
DR		 1951static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1952 struct vm_area_struct *area)
1953{
1954#ifdef CONFIG_X86
1955 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1956 struct azx *chip = apcm->chip;
3b70bdba 1957 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 1958 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1959#endif
1960}
1961
a43ff5ba 1962static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 1963 .reg_writel = pci_azx_writel,
1964 .reg_readl = pci_azx_readl,
1965 .reg_writew = pci_azx_writew,
1966 .reg_readw = pci_azx_readw,
1967 .reg_writeb = pci_azx_writeb,
1968 .reg_readb = pci_azx_readb,
b419b35b
DR		 1969 .dma_alloc_pages = dma_alloc_pages,
1970 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 1971};
1972
1973static const struct hda_controller_ops pci_hda_ops = {
1974 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1975 .substream_alloc_pages = substream_alloc_pages,
1976 .substream_free_pages = substream_free_pages,
8769b278 1977 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1978 .position_check = azx_position_check,
17eccb27 1979 .link_power = azx_intel_link_power,
40830813
DR		 1980};
1981
e23e7a14
BP		 1982static int azx_probe(struct pci_dev *pci,
1983 const struct pci_device_id *pci_id)
1da177e4 1984{
5aba4f8e 1985 static int dev;
a98f90fd 1986 struct snd_card *card;
9a34af4a 1987 struct hda_intel *hda;
a98f90fd 1988 struct azx *chip;
aad730d0 1989 bool schedule_probe;
927fc866 1990 int err;
1da177e4 1991
5aba4f8e
TI		 1992 if (dev >= SNDRV_CARDS)
1993 return -ENODEV;
1994 if (!enable[dev]) {
1995 dev++;
1996 return -ENOENT;
1997 }
1998
60c5772b
TI		 1999 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2000 0, &card);
e58de7ba 2001 if (err < 0) {
4e76a883 2002 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2003 return err;
1da177e4
LT		 2004 }
2005
a43ff5ba 2006 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2007 if (err < 0)
2008 goto out_free;
421a1252 2009 card->private_data = chip;
9a34af4a 2010 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2011
2012 pci_set_drvdata(pci, card);
2013
2014 err = register_vga_switcheroo(chip);
2015 if (err < 0) {
2b760d88 2016 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2017 goto out_free;
2018 }
2019
2020 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2021 dev_info(card->dev, "VGA controller is disabled\n");
2022 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2023 chip->disabled = true;
2024 }
2025
aad730d0 2026 schedule_probe = !chip->disabled;
1da177e4 2027
4918cdab
TI		 2028#ifdef CONFIG_SND_HDA_PATCH_LOADER
2029 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2030 dev_info(card->dev, "Applying patch firmware '%s'\n",
2031 patch[dev]);
5cb543db
TI		 2032 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2033 &pci->dev, GFP_KERNEL, card,
2034 azx_firmware_cb);
4918cdab
TI		 2035 if (err < 0)
2036 goto out_free;
aad730d0 2037 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2038 }
2039#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2040
aad730d0 2041#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2042 if (CONTROLLER_IN_GPU(pci))
2043 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2044#endif
99a2008d 2045
aad730d0 2046 if (schedule_probe)
9a34af4a 2047 schedule_work(&hda->probe_work);
a82d51ed 2048
a82d51ed 2049 dev++;
88d071fc 2050 if (chip->disabled)
9a34af4a 2051 complete_all(&hda->probe_wait);
a82d51ed
TI		 2052 return 0;
2053
2054out_free:
2055 snd_card_free(card);
2056 return err;
2057}
2058
e62a42ae
DR		 2059/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2060static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2061 [AZX_DRIVER_NVIDIA] = 8,
2062 [AZX_DRIVER_TERA] = 1,
2063};
2064
48c8b0eb 2065static int azx_probe_continue(struct azx *chip)
a82d51ed 2066{
9a34af4a 2067 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2068 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2069 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2070 int dev = chip->dev_index;
2071 int err;
2072
a41d1224 2073 hda->probe_continued = 1;
795614dd
ML		 2074
2075 /* Request display power well for the HDA controller or codec. For
2076 * Haswell/Broadwell, both the display HDA controller and codec need
2077 * this power. For other platforms, like Baytrail/Braswell, only the
2078 * display codec needs the power and it can be released after probe.
2079 */
99a2008d 2080 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
03b135ce
LY		 2081 /* HSW/BDW controllers need this power */
2082 if (CONTROLLER_IN_GPU(pci))
2bd1f73f
ML		 2083 hda->need_i915_power = 1;
2084
98d8fc6c 2085 err = snd_hdac_i915_init(bus);
535115b5
TI		 2086 if (err < 0) {
2087 /* if the controller is bound only with HDMI/DP
2088 * (for HSW and BDW), we need to abort the probe;
2089 * for other chips, still continue probing as other
2090 * codecs can be on the same link.
2091 */
bed2e98e
TI		 2092 if (CONTROLLER_IN_GPU(pci)) {
2093 dev_err(chip->card->dev,
2094 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2095 goto out_free;
bed2e98e 2096 } else
535115b5
TI		 2097 goto skip_i915;
2098 }
795614dd 2099
98d8fc6c 2100 err = snd_hdac_display_power(bus, true);
74b0c2d7
TI		 2101 if (err < 0) {
2102 dev_err(chip->card->dev,
2103 "Cannot turn on display power on i915\n");
795614dd 2104 goto i915_power_fail;
74b0c2d7 2105 }
99a2008d
WX		 2106 }
2107
bf06848b 2108 skip_i915:
5c90680e
TI		 2109 err = azx_first_init(chip);
2110 if (err < 0)
2111 goto out_free;
2112
2dca0bba
JK		 2113#ifdef CONFIG_SND_HDA_INPUT_BEEP
2114 chip->beep_mode = beep_mode[dev];
2115#endif
2116
1da177e4 2117 /* create codec instances */
96d2bd6e 2118 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2119 if (err < 0)
2120 goto out_free;
96d2bd6e 2121
4ea6fbc8 2122#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2123 if (chip->fw) {
a41d1224 2124 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2125 chip->fw->data);
4ea6fbc8
TI		 2126 if (err < 0)
2127 goto out_free;
e39ae856 2128#ifndef CONFIG_PM
4918cdab
TI		 2129 release_firmware(chip->fw); /* no longer needed */
2130 chip->fw = NULL;
e39ae856 2131#endif
4ea6fbc8
TI		 2132 }
2133#endif
10e77dda 2134 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2135 err = azx_codec_configure(chip);
2136 if (err < 0)
2137 goto out_free;
2138 }
1da177e4 2139
a82d51ed 2140 err = snd_card_register(chip->card);
41dda0fd
WF		 2141 if (err < 0)
2142 goto out_free;
1da177e4 2143
cb53c626 2144 chip->running = 1;
65fcd41d 2145 azx_add_card_list(chip);
a41d1224 2146 snd_hda_set_power_save(&chip->bus, power_save * 1000);
364aa716 2147 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
30ff5957 2148 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2149
41dda0fd 2150out_free:
795614dd
ML		 2151 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2152 && !hda->need_i915_power)
98d8fc6c 2153 snd_hdac_display_power(bus, false);
795614dd
ML		 2154
2155i915_power_fail:
88d071fc 2156 if (err < 0)
9a34af4a
TI		 2157 hda->init_failed = 1;
2158 complete_all(&hda->probe_wait);
41dda0fd 2159 return err;
1da177e4
LT		 2160}
2161
e23e7a14 2162static void azx_remove(struct pci_dev *pci)
1da177e4 2163{
9121947d 2164 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2165 struct azx *chip;
2166 struct hda_intel *hda;
2167
2168 if (card) {
0b8c8219 2169 /* cancel the pending probing work */
991f86d7
TI		 2170 chip = card->private_data;
2171 hda = container_of(chip, struct hda_intel, chip);
0b8c8219 2172 cancel_work_sync(&hda->probe_work);
b8dfc462 2173
9121947d 2174 snd_card_free(card);
991f86d7 2175 }
1da177e4
LT		 2176}
2177
b2a0bafa
TI		 2178static void azx_shutdown(struct pci_dev *pci)
2179{
2180 struct snd_card *card = pci_get_drvdata(pci);
2181 struct azx *chip;
2182
2183 if (!card)
2184 return;
2185 chip = card->private_data;
2186 if (chip && chip->running)
2187 azx_stop_chip(chip);
2188}
2189
1da177e4 2190/* PCI IDs */
6f51f6cf 2191static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2192 /* CPT */
9477c58e 2193 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2194 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2195 /* PBG */
9477c58e 2196 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2197 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2198 /* Panther Point */
9477c58e 2199 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2200 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2201 /* Lynx Point */
2202 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2203 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2204 /* 9 Series */
2205 { PCI_DEVICE(0x8086, 0x8ca0),
2206 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2207 /* Wellsburg */
2208 { PCI_DEVICE(0x8086, 0x8d20),
2209 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2210 { PCI_DEVICE(0x8086, 0x8d21),
2211 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2212 /* Lewisburg */
2213 { PCI_DEVICE(0x8086, 0xa1f0),
2214 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2215 { PCI_DEVICE(0x8086, 0xa270),
2216 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2217 /* Lynx Point-LP */
2218 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2219 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2220 /* Lynx Point-LP */
2221 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2222 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2223 /* Wildcat Point-LP */
2224 { PCI_DEVICE(0x8086, 0x9ca0),
2225 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2226 /* Sunrise Point */
2227 { PCI_DEVICE(0x8086, 0xa170),
db48abf4 2228 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2229 /* Sunrise Point-LP */
2230 { PCI_DEVICE(0x8086, 0x9d70),
d6795827 2231 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
c87693da
LH		 2232 /* Broxton-P(Apollolake) */
2233 { PCI_DEVICE(0x8086, 0x5a98),
2234 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2235 /* Haswell */
4a7c516b 2236 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2237 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2238 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2239 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2240 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2241 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2242 /* Broadwell */
2243 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2244 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2245 /* 5 Series/3400 */
2246 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2247 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2248 /* Poulsbo */
9477c58e 2249 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2250 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2251 /* Oaktrail */
09904b95 2252 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2253 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2254 /* BayTrail */
2255 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2256 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2257 /* Braswell */
2258 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2259 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2260 /* ICH6 */
8b0bd226 2261 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2262 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2263 /* ICH7 */
8b0bd226 2264 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2265 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2266 /* ESB2 */
8b0bd226 2267 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2268 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2269 /* ICH8 */
8b0bd226 2270 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2271 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2272 /* ICH9 */
8b0bd226 2273 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2274 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2275 /* ICH9 */
8b0bd226 2276 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2277 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2278 /* ICH10 */
8b0bd226 2279 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2280 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2281 /* ICH10 */
8b0bd226 2282 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2283 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2284 /* Generic Intel */
2285 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2286 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2287 .class_mask = 0xffffff,
103884a3 2288 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2289 /* ATI SB 450/600/700/800/900 */
2290 { PCI_DEVICE(0x1002, 0x437b),
2291 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2292 { PCI_DEVICE(0x1002, 0x4383),
2293 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2294 /* AMD Hudson */
2295 { PCI_DEVICE(0x1022, 0x780d),
2296 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2297 /* ATI HDMI */
650474fb
AD		 2298 { PCI_DEVICE(0x1002, 0x1308),
2299 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2300 { PCI_DEVICE(0x1002, 0x157a),
2301 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2302 { PCI_DEVICE(0x1002, 0x793b),
2303 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2304 { PCI_DEVICE(0x1002, 0x7919),
2305 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2306 { PCI_DEVICE(0x1002, 0x960f),
2307 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2308 { PCI_DEVICE(0x1002, 0x970f),
2309 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2310 { PCI_DEVICE(0x1002, 0x9840),
2311 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2312 { PCI_DEVICE(0x1002, 0xaa00),
2313 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2314 { PCI_DEVICE(0x1002, 0xaa08),
2315 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2316 { PCI_DEVICE(0x1002, 0xaa10),
2317 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2318 { PCI_DEVICE(0x1002, 0xaa18),
2319 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2320 { PCI_DEVICE(0x1002, 0xaa20),
2321 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2322 { PCI_DEVICE(0x1002, 0xaa28),
2323 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2324 { PCI_DEVICE(0x1002, 0xaa30),
2325 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2326 { PCI_DEVICE(0x1002, 0xaa38),
2327 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2328 { PCI_DEVICE(0x1002, 0xaa40),
2329 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2330 { PCI_DEVICE(0x1002, 0xaa48),
2331 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2332 { PCI_DEVICE(0x1002, 0xaa50),
2333 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2334 { PCI_DEVICE(0x1002, 0xaa58),
2335 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2336 { PCI_DEVICE(0x1002, 0xaa60),
2337 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2338 { PCI_DEVICE(0x1002, 0xaa68),
2339 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2340 { PCI_DEVICE(0x1002, 0xaa80),
2341 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2342 { PCI_DEVICE(0x1002, 0xaa88),
2343 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2344 { PCI_DEVICE(0x1002, 0xaa90),
2345 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2346 { PCI_DEVICE(0x1002, 0xaa98),
2347 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2348 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2349 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2350 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2351 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2352 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2353 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2354 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2355 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2356 { PCI_DEVICE(0x1002, 0xaac0),
2357 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2358 { PCI_DEVICE(0x1002, 0xaac8),
2359 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2360 { PCI_DEVICE(0x1002, 0xaad8),
2361 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2362 { PCI_DEVICE(0x1002, 0xaae8),
2363 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
8eb22214
MSB		 2364 { PCI_DEVICE(0x1002, 0xaae0),
2365 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2366 { PCI_DEVICE(0x1002, 0xaaf0),
2367 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2368 /* VIA VT8251/VT8237A */
26f05717 2369 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2370 /* VIA GFX VT7122/VX900 */
2371 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2372 /* VIA GFX VT6122/VX11 */
2373 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2374 /* SIS966 */
2375 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2376 /* ULI M5461 */
2377 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2378 /* NVIDIA MCP */
0c2fd1bf
TI		 2379 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2380 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2381 .class_mask = 0xffffff,
9477c58e 2382 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2383 /* Teradici */
9477c58e
TI		 2384 { PCI_DEVICE(0x6549, 0x1200),
2385 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2386 { PCI_DEVICE(0x6549, 0x2200),
2387 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2388 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2389 /* CTHDA chips */
2390 { PCI_DEVICE(0x1102, 0x0010),
2391 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2392 { PCI_DEVICE(0x1102, 0x0012),
2393 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2394#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2395 /* the following entry conflicts with snd-ctxfi driver,
2396 * as ctxfi driver mutates from HD-audio to native mode with
2397 * a special command sequence.
2398 */
4e01f54b
TI		 2399 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2400 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2401 .class_mask = 0xffffff,
9477c58e 2402 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2403 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2404#else
2405 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2406 { PCI_DEVICE(0x1102, 0x0009),
2407 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2408 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2409#endif
c563f473
TI		 2410 /* CM8888 */
2411 { PCI_DEVICE(0x13f6, 0x5011),
2412 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2413 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2414 /* Vortex86MX */
2415 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2416 /* VMware HDAudio */
2417 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2418 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2419 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2420 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2421 .class_mask = 0xffffff,
9477c58e 2422 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2423 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2424 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2425 .class_mask = 0xffffff,
9477c58e 2426 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2427 { 0, }
2428};
2429MODULE_DEVICE_TABLE(pci, azx_ids);
2430
2431/* pci_driver definition */
e9f66d9b 2432static struct pci_driver azx_driver = {
3733e424 2433 .name = KBUILD_MODNAME,
1da177e4
LT		 2434 .id_table = azx_ids,
2435 .probe = azx_probe,
e23e7a14 2436 .remove = azx_remove,
b2a0bafa 2437 .shutdown = azx_shutdown,
68cb2b55
TI		 2438 .driver = {
2439 .pm = AZX_PM_OPS,
2440 },
1da177e4
LT		 2441};
2442
e9f66d9b 2443module_pci_driver(azx_driver);
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