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ALSA: usb-audio: Check mapping at creating connector controls, too
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 *
d01ce99f
TI		 4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
1da177e4
LT		 6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
1da177e4
LT		 12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
1da177e4
LT		 21 */
22
1da177e4
LT		 23#include <linux/delay.h>
24#include <linux/interrupt.h>
362775e2 25#include <linux/kernel.h>
1da177e4 26#include <linux/module.h>
24982c5f 27#include <linux/dma-mapping.h>
1da177e4
LT		 28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/slab.h>
31#include <linux/pci.h>
62932df8 32#include <linux/mutex.h>
27fe48d9 33#include <linux/io.h>
b8dfc462 34#include <linux/pm_runtime.h>
5d890f59
PLB		 35#include <linux/clocksource.h>
36#include <linux/time.h>
f4c482a4 37#include <linux/completion.h>
586bc4aa 38#include <linux/acpi.h>
5d890f59 39
27fe48d9
TI		 40#ifdef CONFIG_X86
41/* for snoop control */
42#include <asm/pgtable.h>
7f80f513 43#include <asm/set_memory.h>
50279d9b 44#include <asm/cpufeature.h>
27fe48d9 45#endif
1da177e4
LT		 46#include <sound/core.h>
47#include <sound/initval.h>
98d8fc6c
ML		 48#include <sound/hdaudio.h>
49#include <sound/hda_i915.h>
82d9d54a 50#include <sound/intel-dsp-config.h>
9121947d 51#include <linux/vgaarb.h>
a82d51ed 52#include <linux/vga_switcheroo.h>
4918cdab 53#include <linux/firmware.h>
be57bfff 54#include <sound/hda_codec.h>
05e84878 55#include "hda_controller.h"
347de1f8 56#include "hda_intel.h"
1da177e4 57
785d8c4b
LY		 58#define CREATE_TRACE_POINTS
59#include "hda_intel_trace.h"
60
b6050ef6
TI		 61/* position fix mode */
62enum {
63 POS_FIX_AUTO,
64 POS_FIX_LPIB,
65 POS_FIX_POSBUF,
66 POS_FIX_VIACOMBO,
67 POS_FIX_COMBO,
f87e7f25 68 POS_FIX_SKL,
c02f77d3 69 POS_FIX_FIFO,
b6050ef6
TI		 70};
71
9a34af4a
TI		 72/* Defines for ATI HD Audio support in SB450 south bridge */
73#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
74#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
75
76/* Defines for Nvidia HDA support */
77#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
78#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
79#define NVIDIA_HDA_ISTRM_COH 0x4d
80#define NVIDIA_HDA_OSTRM_COH 0x4c
81#define NVIDIA_HDA_ENABLE_COHBIT 0x01
82
83/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 84#define INTEL_HDA_CGCTL 0x48
85#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 86#define INTEL_SCH_HDA_DEVC 0x78
87#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
88
9a34af4a
TI		 89/* Define VIA HD Audio Device ID*/
90#define VIA_HDAC_DEVICE_ID 0x3288
91
33124929
TI		 92/* max number of SDs */
93/* ICH, ATI and VIA have 4 playback and 4 capture */
94#define ICH6_NUM_CAPTURE 4
95#define ICH6_NUM_PLAYBACK 4
96
97/* ULI has 6 playback and 5 capture */
98#define ULI_NUM_CAPTURE 5
99#define ULI_NUM_PLAYBACK 6
100
101/* ATI HDMI may have up to 8 playbacks and 0 capture */
102#define ATIHDMI_NUM_CAPTURE 0
103#define ATIHDMI_NUM_PLAYBACK 8
104
105/* TERA has 4 playback and 3 capture */
106#define TERA_NUM_CAPTURE 3
107#define TERA_NUM_PLAYBACK 4
108
1da177e4 109
5aba4f8e
TI		 110static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
111static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 112static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 113static char *model[SNDRV_CARDS];
1dac6695 114static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 115static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 116static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 117static int probe_only[SNDRV_CARDS];
26a6cb6c 118static int jackpoll_ms[SNDRV_CARDS];
41438f13 119static int single_cmd = -1;
71623855 120static int enable_msi = -1;
4ea6fbc8
TI		 121#ifdef CONFIG_SND_HDA_PATCH_LOADER
122static char *patch[SNDRV_CARDS];
123#endif
2dca0bba 124#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 125static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 126 CONFIG_SND_HDA_INPUT_BEEP_MODE};
127#endif
7fba6aea 128static bool dmic_detect = 1;
1da177e4 129
5aba4f8e 130module_param_array(index, int, NULL, 0444);
1da177e4 131MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 132module_param_array(id, charp, NULL, 0444);
1da177e4 133MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 134module_param_array(enable, bool, NULL, 0444);
135MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
136module_param_array(model, charp, NULL, 0444);
1da177e4 137MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 138module_param_array(position_fix, int, NULL, 0444);
4cb36310 139MODULE_PARM_DESC(position_fix, "DMA pointer read method."
c02f77d3 140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
555e219f
TI		 141module_param_array(bdl_pos_adj, int, NULL, 0644);
142MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 143module_param_array(probe_mask, int, NULL, 0444);
606ad75f 144MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 145module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 146MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 147module_param_array(jackpoll_ms, int, NULL, 0444);
148MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 149module_param(single_cmd, bint, 0444);
d01ce99f
TI		 150MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
151 "(for debugging only).");
ac9ef6cf 152module_param(enable_msi, bint, 0444);
134a11f0 153MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 154#ifdef CONFIG_SND_HDA_PATCH_LOADER
155module_param_array(patch, charp, NULL, 0444);
156MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
157#endif
2dca0bba 158#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 159module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 160MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 161 "(0=off, 1=on) (default=1).");
2dca0bba 162#endif
7fba6aea
TI		 163module_param(dmic_detect, bool, 0444);
164MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
165 "(0=off, 1=on) (default=1); "
166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
606ad75f 167
83012a7c 168#ifdef CONFIG_PM
65fcd41d 169static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 170static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 171 .set = param_set_xint,
172 .get = param_get_int,
173};
174#define param_check_xint param_check_int
175
fee2fba3 176static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 177module_param(power_save, xint, 0644);
fee2fba3
TI		 178MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
179 "(in second, 0 = disable).");
1da177e4 180
40088dc4
TI		 181static bool pm_blacklist = true;
182module_param(pm_blacklist, bool, 0644);
183MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
184
dee1b66c
TI		 185/* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
8fc24426
TI		 189static bool power_save_controller = 1;
190module_param(power_save_controller, bool, 0644);
dee1b66c 191MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 192#else
bb573928 193#define power_save 0
83012a7c 194#endif /* CONFIG_PM */
dee1b66c 195
7bfe059e
TI		 196static int align_buffer_size = -1;
197module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 198MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
27fe48d9 201#ifdef CONFIG_X86
7c732015
TI		 202static int hda_snoop = -1;
203module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 204MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 205#else
206#define hda_snoop true
27fe48d9
TI		 207#endif
208
209
1da177e4
LT		 210MODULE_LICENSE("GPL");
211MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212 "{Intel, ICH6M},"
2f1b3818 213 "{Intel, ICH7},"
f5d40b30 214 "{Intel, ESB2},"
d2981393 215 "{Intel, ICH8},"
f9cc8a8b 216 "{Intel, ICH9},"
c34f5a04 217 "{Intel, ICH10},"
b29c2360 218 "{Intel, PCH},"
d2f2fcd2 219 "{Intel, CPT},"
d2edeb7c 220 "{Intel, PPT},"
8bc039a1 221 "{Intel, LPT},"
144dad99 222 "{Intel, LPT_LP},"
4eeca499 223 "{Intel, WPT_LP},"
c8b00fd2 224 "{Intel, SPT},"
b4565913 225 "{Intel, SPT_LP},"
e926f2c8 226 "{Intel, HPT},"
cea310e8 227 "{Intel, PBG},"
4979bca9 228 "{Intel, SCH},"
fc20a562 229 "{ATI, SB450},"
89be83f8 230 "{ATI, SB600},"
778b6e1b 231 "{ATI, RS600},"
5b15c95f 232 "{ATI, RS690},"
e6db1119
WL		 233 "{ATI, RS780},"
234 "{ATI, R600},"
2797f724
HRK		 235 "{ATI, RV630},"
236 "{ATI, RV610},"
27da1834
WL		 237 "{ATI, RV670},"
238 "{ATI, RV635},"
239 "{ATI, RV620},"
240 "{ATI, RV770},"
fc20a562 241 "{VIA, VT8251},"
47672310 242 "{VIA, VT8237A},"
07e4ca50
TI		 243 "{SiS, SIS966},"
244 "{ULI, M5461}}");
1da177e4
LT		 245MODULE_DESCRIPTION("Intel HDA driver");
246
a82d51ed 247#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 248#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 249#define SUPPORT_VGA_SWITCHEROO
250#endif
251#endif
252
253
1da177e4 254/*
1da177e4 255 */
1da177e4 256
07e4ca50
TI		 257/* driver types */
258enum {
259 AZX_DRIVER_ICH,
32679f95 260 AZX_DRIVER_PCH,
4979bca9 261 AZX_DRIVER_SCH,
a4b4793f 262 AZX_DRIVER_SKL,
fab1285a 263 AZX_DRIVER_HDMI,
07e4ca50 264 AZX_DRIVER_ATI,
778b6e1b 265 AZX_DRIVER_ATIHDMI,
1815b34a 266 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 267 AZX_DRIVER_VIA,
268 AZX_DRIVER_SIS,
269 AZX_DRIVER_ULI,
da3fca21 270 AZX_DRIVER_NVIDIA,
f269002e 271 AZX_DRIVER_TERA,
14d34f16 272 AZX_DRIVER_CTX,
5ae763b1 273 AZX_DRIVER_CTHDA,
c563f473 274 AZX_DRIVER_CMEDIA,
b6fcab14 275 AZX_DRIVER_ZHAOXIN,
c4da29ca 276 AZX_DRIVER_GENERIC,
2f5983f2 277 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 278};
279
37e661ee
TI		 280#define azx_get_snoop_type(chip) \
281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
282#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
283
b42b4afb
TI		 284/* quirks for old Intel chipsets */
285#define AZX_DCAPS_INTEL_ICH \
c366b3db
TI		 286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE |\
287 AZX_DCAPS_SYNC_WRITE)
b42b4afb 288
2ea3c6a2 289/* quirks for Intel PCH */
6603249d 290#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 291 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
c366b3db 292 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
d7dab4db 293
dba9b7b6 294/* PCH up to IVB; no runtime PM; bind with i915 gfx */
6603249d 295#define AZX_DCAPS_INTEL_PCH_NOPM \
dba9b7b6 296 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
6603249d 297
55913110 298/* PCH for HSW/BDW; with runtime PM */
dba9b7b6 299/* no i915 binding for this as HSW/BDW has another controller for HDMI */
d7dab4db 300#define AZX_DCAPS_INTEL_PCH \
6603249d 301 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 302
6603249d 303/* HSW HDMI */
33499a15 304#define AZX_DCAPS_INTEL_HASWELL \
103884a3 305 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
dba9b7b6 306 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
c366b3db 307 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
33499a15 308
54a0405d
LY		 309/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
310#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
dba9b7b6 312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
c366b3db 313 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
54a0405d 314
40cc2392 315#define AZX_DCAPS_INTEL_BAYTRAIL \
e454ff8e 316 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
40cc2392 317
2d846c74 318#define AZX_DCAPS_INTEL_BRASWELL \
dba9b7b6 319 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 320 AZX_DCAPS_I915_COMPONENT)
2d846c74 321
d6795827 322#define AZX_DCAPS_INTEL_SKYLAKE \
dba9b7b6 323 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
2756d914 324 AZX_DCAPS_SYNC_WRITE |\
e454ff8e 325 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
d6795827 326
2756d914 327#define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
c87693da 328
9477c58e
TI		 329/* quirks for ATI SB / AMD Hudson */
330#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 331 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
332 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 333
334/* quirks for ATI/AMD HDMI */
335#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 336 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
337 AZX_DCAPS_NO_MSI64)
9477c58e 338
37e661ee
TI		 339/* quirks for ATI HDMI with snoop off */
340#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
341 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
342
c02f77d3
TI		 343/* quirks for AMD SB */
344#define AZX_DCAPS_PRESET_AMD_SB \
345 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
346 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
347
9477c58e
TI		 348/* quirks for Nvidia */
349#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 350 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 351 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 352
5ae763b1 353#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 354 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 355 AZX_DCAPS_NO_64BIT |\
37e661ee 356 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 357
a82d51ed 358/*
2b760d88 359 * vga_switcheroo support
a82d51ed
TI		 360 */
361#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db 362#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
dd23e1d5 363#define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
5cb543db
TI		 364#else
365#define use_vga_switcheroo(chip) 0
37a3a98e 366#define needs_eld_notify_link(chip) false
5cb543db
TI		 367#endif
368
03b135ce
LY		 369#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
370 ((pci)->device == 0x0c0c) || \
371 ((pci)->device == 0x0d0c) || \
372 ((pci)->device == 0x160c))
373
7e31a015 374#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
7c23b7c1 375
bf82326f 376static const char * const driver_short_names[] = {
07e4ca50 377 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 378 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 379 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 380 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 381 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 382 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 383 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 384 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 385 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
386 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 387 [AZX_DRIVER_ULI] = "HDA ULI M5461",
388 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 389 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 390 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 391 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 392 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
b6fcab14 393 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
c4da29ca 394 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 395};
396
68e7fffc 397static int azx_acquire_irq(struct azx *chip, int do_disconnect);
37a3a98e 398static void set_default_power_save(struct azx *chip);
111d3af5 399
cb53c626
TI		 400/*
401 * initialize the PCI registers
402 */
403/* update bits in a PCI register byte */
404static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
405 unsigned char mask, unsigned char val)
406{
407 unsigned char data;
408
409 pci_read_config_byte(pci, reg, &data);
410 data &= ~mask;
411 data |= (val & mask);
412 pci_write_config_byte(pci, reg, data);
413}
414
415static void azx_init_pci(struct azx *chip)
416{
37e661ee
TI		 417 int snoop_type = azx_get_snoop_type(chip);
418
cb53c626
TI		 419 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
420 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
421 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 422 * codecs.
423 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 424 */
46f2cc80 425 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 426 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 427 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 428 }
cb53c626 429
9477c58e
TI		 430 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
431 * we need to enable snoop.
432 */
37e661ee 433 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 434 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
435 azx_snoop(chip));
cb53c626 436 update_pci_byte(chip->pci,
27fe48d9
TI		 437 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
438 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 439 }
440
441 /* For NVIDIA HDA, enable snoop */
37e661ee 442 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 443 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
444 azx_snoop(chip));
cb53c626
TI		 445 update_pci_byte(chip->pci,
446 NVIDIA_HDA_TRANSREG_ADDR,
447 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 448 update_pci_byte(chip->pci,
449 NVIDIA_HDA_ISTRM_COH,
450 0x01, NVIDIA_HDA_ENABLE_COHBIT);
451 update_pci_byte(chip->pci,
452 NVIDIA_HDA_OSTRM_COH,
453 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 454 }
455
456 /* Enable SCH/PCH snoop if needed */
37e661ee 457 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 458 unsigned short snoop;
90a5ad52 459 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 460 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
461 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
462 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
463 if (!azx_snoop(chip))
464 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
465 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 466 pci_read_config_word(chip->pci,
467 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 468 }
4e76a883
TI		 469 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
470 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
471 "Disabled" : "Enabled");
da3fca21 472 }
1da177e4
LT		 473}
474
7c23b7c1
LH		 475/*
476 * In BXT-P A0, HD-Audio DMA requests is later than expected,
477 * and makes an audio stream sensitive to system latencies when
478 * 24/32 bits are playing.
479 * Adjusting threshold of DMA fifo to force the DMA request
480 * sooner to improve latency tolerance at the expense of power.
481 */
482static void bxt_reduce_dma_latency(struct azx *chip)
483{
484 u32 val;
485
70eafad8 486 val = azx_readl(chip, VS_EM4L);
7c23b7c1 487 val &= (0x3 << 20);
70eafad8 488 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 489}
490
1f9d3d98
LY		 491/*
492 * ML_LCAP bits:
493 * bit 0: 6 MHz Supported
494 * bit 1: 12 MHz Supported
495 * bit 2: 24 MHz Supported
496 * bit 3: 48 MHz Supported
497 * bit 4: 96 MHz Supported
498 * bit 5: 192 MHz Supported
499 */
500static int intel_get_lctl_scf(struct azx *chip)
501{
502 struct hdac_bus *bus = azx_bus(chip);
bf82326f 503 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
1f9d3d98
LY		 504 u32 val, t;
505 int i;
506
507 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
508
509 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
510 t = preferred_bits[i];
511 if (val & (1 << t))
512 return t;
513 }
514
515 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
516 return 0;
517}
518
519static int intel_ml_lctl_set_power(struct azx *chip, int state)
520{
521 struct hdac_bus *bus = azx_bus(chip);
522 u32 val;
523 int timeout;
524
525 /*
526 * the codecs are sharing the first link setting by default
527 * If other links are enabled for stream, they need similar fix
528 */
529 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
530 val &= ~AZX_MLCTL_SPA;
531 val |= state << AZX_MLCTL_SPA_SHIFT;
532 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
533 /* wait for CPA */
534 timeout = 50;
535 while (timeout) {
536 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
537 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
538 return 0;
539 timeout--;
540 udelay(10);
541 }
542
543 return -1;
544}
545
546static void intel_init_lctl(struct azx *chip)
547{
548 struct hdac_bus *bus = azx_bus(chip);
549 u32 val;
550 int ret;
551
552 /* 0. check lctl register value is correct or not */
553 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
554 /* if SCF is already set, let's use it */
555 if ((val & ML_LCTL_SCF_MASK) != 0)
556 return;
557
558 /*
559 * Before operating on SPA, CPA must match SPA.
560 * Any deviation may result in undefined behavior.
561 */
562 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
563 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
564 return;
565
566 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
567 ret = intel_ml_lctl_set_power(chip, 0);
568 udelay(100);
569 if (ret)
570 goto set_spa;
571
572 /* 2. update SCF to select a properly audio clock*/
573 val &= ~ML_LCTL_SCF_MASK;
574 val |= intel_get_lctl_scf(chip);
575 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
576
577set_spa:
578 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
579 intel_ml_lctl_set_power(chip, 1);
580 udelay(100);
581}
582
0a673521
LH		 583static void hda_intel_init_chip(struct azx *chip, bool full_reset)
584{
98d8fc6c 585 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 586 struct pci_dev *pci = chip->pci;
6639484d 587 u32 val;
0a673521 588
e454ff8e 589 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 590 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 591 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
592 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
593 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
594 }
0a673521 595 azx_init_chip(chip, full_reset);
a4b4793f 596 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 597 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
598 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
599 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
600 }
e454ff8e
TI		 601
602 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 603
604 /* reduce dma latency to avoid noise */
7e31a015 605 if (IS_BXT(pci))
7c23b7c1 606 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 607
608 if (bus->mlcap != NULL)
609 intel_init_lctl(chip);
0a673521
LH		 610}
611
b6050ef6
TI		 612/* calculate runtime delay from LPIB */
613static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
614 unsigned int pos)
615{
7833c3f8 616 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 617 int stream = substream->stream;
618 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
619 int delay;
620
621 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
622 delay = pos - lpib_pos;
623 else
624 delay = lpib_pos - pos;
625 if (delay < 0) {
7833c3f8 626 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 627 delay = 0;
628 else
7833c3f8 629 delay += azx_dev->core.bufsize;
b6050ef6
TI		 630 }
631
7833c3f8 632 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 633 dev_info(chip->card->dev,
634 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 635 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 636 delay = 0;
637 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
638 chip->get_delay[stream] = NULL;
639 }
640
641 return bytes_to_frames(substream->runtime, delay);
642}
643
9ad593f6
TI		 644static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
645
7ca954a8
DR		 646/* called from IRQ */
647static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
648{
9a34af4a 649 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 650 int ok;
651
652 ok = azx_position_ok(chip, azx_dev);
653 if (ok == 1) {
654 azx_dev->irq_pending = 0;
655 return ok;
2f35c630 656 } else if (ok == 0) {
7ca954a8
DR		 657 /* bogus IRQ, process it later */
658 azx_dev->irq_pending = 1;
2f35c630 659 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 660 }
661 return 0;
662}
663
029d92c2
TI		 664#define display_power(chip, enable) \
665 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
17eccb27 666
9ad593f6
TI		 667/*
668 * Check whether the current DMA position is acceptable for updating
669 * periods. Returns non-zero if it's OK.
670 *
671 * Many HD-audio controllers appear pretty inaccurate about
672 * the update-IRQ timing. The IRQ is issued before actually the
673 * data is processed. So, we need to process it afterwords in a
674 * workqueue.
675 */
676static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
677{
7833c3f8 678 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 679 int stream = substream->stream;
e5463720 680 u32 wallclk;
9ad593f6
TI		 681 unsigned int pos;
682
7833c3f8
TI		 683 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
684 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 685 return -1; /* bogus (too early) interrupt */
fa00e046 686
b6050ef6
TI		 687 if (chip->get_position[stream])
688 pos = chip->get_position[stream](chip, azx_dev);
689 else { /* use the position buffer as default */
690 pos = azx_get_pos_posbuf(chip, azx_dev);
691 if (!pos || pos == (u32)-1) {
692 dev_info(chip->card->dev,
693 "Invalid position buffer, using LPIB read method instead.\n");
694 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 695 if (chip->get_position[0] == azx_get_pos_lpib &&
696 chip->get_position[1] == azx_get_pos_lpib)
697 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 698 pos = azx_get_pos_lpib(chip, azx_dev);
699 chip->get_delay[stream] = NULL;
700 } else {
701 chip->get_position[stream] = azx_get_pos_posbuf;
702 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
703 chip->get_delay[stream] = azx_get_delay_from_lpib;
704 }
705 }
706
7833c3f8 707 if (pos >= azx_dev->core.bufsize)
b6050ef6 708 pos = 0;
9ad593f6 709
7833c3f8 710 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 711 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 712 return -1; /* this shouldn't happen! */
7833c3f8
TI		 713 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
714 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 715 /* NG - it's below the first next period boundary */
4f0189be 716 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 717 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 718 return 1; /* OK, it's fine */
719}
720
721/*
722 * The work for pending PCM period updates.
723 */
724static void azx_irq_pending_work(struct work_struct *work)
725{
9a34af4a
TI		 726 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
727 struct azx *chip = &hda->chip;
7833c3f8
TI		 728 struct hdac_bus *bus = azx_bus(chip);
729 struct hdac_stream *s;
730 int pending, ok;
9ad593f6 731
9a34af4a 732 if (!hda->irq_pending_warned) {
4e76a883
TI		 733 dev_info(chip->card->dev,
734 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
735 chip->card->number);
9a34af4a 736 hda->irq_pending_warned = 1;
a6a950a8
TI		 737 }
738
9ad593f6
TI		 739 for (;;) {
740 pending = 0;
a41d1224 741 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 742 list_for_each_entry(s, &bus->stream_list, list) {
743 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 744 if (!azx_dev->irq_pending ||
7833c3f8
TI		 745 !s->substream ||
746 !s->running)
9ad593f6 747 continue;
e5463720
JK		 748 ok = azx_position_ok(chip, azx_dev);
749 if (ok > 0) {
9ad593f6 750 azx_dev->irq_pending = 0;
a41d1224 751 spin_unlock(&bus->reg_lock);
7833c3f8 752 snd_pcm_period_elapsed(s->substream);
a41d1224 753 spin_lock(&bus->reg_lock);
e5463720
JK		 754 } else if (ok < 0) {
755 pending = 0; /* too early */
9ad593f6
TI		 756 } else
757 pending++;
758 }
a41d1224 759 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 760 if (!pending)
761 return;
08af495f 762 msleep(1);
9ad593f6
TI		 763 }
764}
765
766/* clear irq_pending flags and assure no on-going workq */
767static void azx_clear_irq_pending(struct azx *chip)
768{
7833c3f8
TI		 769 struct hdac_bus *bus = azx_bus(chip);
770 struct hdac_stream *s;
9ad593f6 771
a41d1224 772 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 773 list_for_each_entry(s, &bus->stream_list, list) {
774 struct azx_dev *azx_dev = stream_to_azx_dev(s);
775 azx_dev->irq_pending = 0;
776 }
a41d1224 777 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 778}
779
68e7fffc
TI		 780static int azx_acquire_irq(struct azx *chip, int do_disconnect)
781{
a41d1224
TI		 782 struct hdac_bus *bus = azx_bus(chip);
783
437a5a46
TI		 784 if (request_irq(chip->pci->irq, azx_interrupt,
785 chip->msi ? 0 : IRQF_SHARED,
de65360b 786 chip->card->irq_descr, chip)) {
4e76a883
TI		 787 dev_err(chip->card->dev,
788 "unable to grab IRQ %d, disabling device\n",
789 chip->pci->irq);
68e7fffc
TI		 790 if (do_disconnect)
791 snd_card_disconnect(chip->card);
792 return -1;
793 }
a41d1224 794 bus->irq = chip->pci->irq;
f36da940 795 chip->card->sync_irq = bus->irq;
69e13418 796 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 797 return 0;
798}
799
b6050ef6
TI		 800/* get the current DMA position with correction on VIA chips */
801static unsigned int azx_via_get_position(struct azx *chip,
802 struct azx_dev *azx_dev)
803{
804 unsigned int link_pos, mini_pos, bound_pos;
805 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
806 unsigned int fifo_size;
807
1604eeee 808 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 809 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 810 /* Playback, no problem using link position */
811 return link_pos;
812 }
813
814 /* Capture */
815 /* For new chipset,
816 * use mod to get the DMA position just like old chipset
817 */
7833c3f8
TI		 818 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
819 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6 820
7da20788 821 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
b6050ef6
TI		 822
823 if (azx_dev->insufficient) {
824 /* Link position never gather than FIFO size */
825 if (link_pos <= fifo_size)
826 return 0;
827
828 azx_dev->insufficient = 0;
829 }
830
831 if (link_pos <= fifo_size)
7833c3f8 832 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 833 else
834 mini_pos = link_pos - fifo_size;
835
836 /* Find nearest previous boudary */
7833c3f8
TI		 837 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
838 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 839 if (mod_link_pos >= fifo_size)
840 bound_pos = link_pos - mod_link_pos;
841 else if (mod_dma_pos >= mod_mini_pos)
842 bound_pos = mini_pos - mod_mini_pos;
843 else {
7833c3f8
TI		 844 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
845 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 846 bound_pos = 0;
847 }
848
849 /* Calculate real DMA position we want */
850 return bound_pos + mod_dma_pos;
851}
852
c02f77d3
TI		 853#define AMD_FIFO_SIZE 32
854
855/* get the current DMA position with FIFO size correction */
856static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
857{
858 struct snd_pcm_substream *substream = azx_dev->core.substream;
859 struct snd_pcm_runtime *runtime = substream->runtime;
860 unsigned int pos, delay;
861
862 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
863 if (!runtime)
864 return pos;
865
866 runtime->delay = AMD_FIFO_SIZE;
867 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
868 if (azx_dev->insufficient) {
869 if (pos < delay) {
870 delay = pos;
871 runtime->delay = bytes_to_frames(runtime, pos);
872 } else {
873 azx_dev->insufficient = 0;
874 }
875 }
876
877 /* correct the DMA position for capture stream */
878 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
879 if (pos < delay)
880 pos += azx_dev->core.bufsize;
881 pos -= delay;
882 }
883
884 return pos;
885}
886
887static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
888 unsigned int pos)
889{
890 struct snd_pcm_substream *substream = azx_dev->core.substream;
891
892 /* just read back the calculated value in the above */
893 return substream->runtime->delay;
894}
895
f87e7f25
TI		 896static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
897 struct azx_dev *azx_dev)
898{
899 return _snd_hdac_chip_readl(azx_bus(chip),
900 AZX_REG_VS_SDXDPIB_XBASE +
901 (AZX_REG_VS_SDXDPIB_XINTERVAL *
902 azx_dev->core.index));
903}
904
905/* get the current DMA position with correction on SKL+ chips */
906static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
907{
908 /* DPIB register gives a more accurate position for playback */
909 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
910 return azx_skl_get_dpib_pos(chip, azx_dev);
911
912 /* For capture, we need to read posbuf, but it requires a delay
913 * for the possible boundary overlap; the read of DPIB fetches the
914 * actual posbuf
915 */
916 udelay(20);
917 azx_skl_get_dpib_pos(chip, azx_dev);
918 return azx_get_pos_posbuf(chip, azx_dev);
919}
920
83012a7c 921#ifdef CONFIG_PM
65fcd41d
TI		 922static DEFINE_MUTEX(card_list_lock);
923static LIST_HEAD(card_list);
924
925static void azx_add_card_list(struct azx *chip)
926{
9a34af4a 927 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 928 mutex_lock(&card_list_lock);
9a34af4a 929 list_add(&hda->list, &card_list);
65fcd41d
TI		 930 mutex_unlock(&card_list_lock);
931}
932
933static void azx_del_card_list(struct azx *chip)
934{
9a34af4a 935 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 936 mutex_lock(&card_list_lock);
9a34af4a 937 list_del_init(&hda->list);
65fcd41d
TI		 938 mutex_unlock(&card_list_lock);
939}
940
941/* trigger power-save check at writing parameter */
942static int param_set_xint(const char *val, const struct kernel_param *kp)
943{
9a34af4a 944 struct hda_intel *hda;
65fcd41d 945 struct azx *chip;
65fcd41d
TI		 946 int prev = power_save;
947 int ret = param_set_int(val, kp);
948
949 if (ret || prev == power_save)
950 return ret;
951
952 mutex_lock(&card_list_lock);
9a34af4a
TI		 953 list_for_each_entry(hda, &card_list, list) {
954 chip = &hda->chip;
a41d1224 955 if (!hda->probe_continued || chip->disabled)
65fcd41d 956 continue;
a41d1224 957 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 958 }
959 mutex_unlock(&card_list_lock);
960 return 0;
961}
5c0b9bec 962
5c0b9bec
TI		 963/*
964 * power management
965 */
3baffc4a 966static bool azx_is_pm_ready(struct snd_card *card)
1da177e4 967{
2d9772ef
TI		 968 struct azx *chip;
969 struct hda_intel *hda;
1da177e4 970
2d9772ef 971 if (!card)
3baffc4a 972 return false;
2d9772ef
TI		 973 chip = card->private_data;
974 hda = container_of(chip, struct hda_intel, chip);
342e8449 975 if (chip->disabled || hda->init_failed || !chip->running)
3baffc4a
TI		 976 return false;
977 return true;
978}
979
980static void __azx_runtime_suspend(struct azx *chip)
981{
3baffc4a
TI		 982 azx_stop_chip(chip);
983 azx_enter_link_reset(chip);
984 azx_clear_irq_pending(chip);
e454ff8e 985 display_power(chip, false);
3baffc4a
TI		 986}
987
744c67ff 988static void __azx_runtime_resume(struct azx *chip, bool from_rt)
3baffc4a
TI		 989{
990 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
991 struct hdac_bus *bus = azx_bus(chip);
992 struct hda_codec *codec;
993 int status;
994
e454ff8e
TI		 995 display_power(chip, true);
996 if (hda->need_i915_power)
997 snd_hdac_i915_set_bclk(bus);
3baffc4a
TI		 998
999 /* Read STATESTS before controller reset */
1000 status = azx_readw(chip, STATESTS);
1001
1002 azx_init_pci(chip);
1003 hda_intel_init_chip(chip, true);
1004
744c67ff 1005 if (status && from_rt) {
3baffc4a
TI		 1006 list_for_each_codec(codec, &chip->bus)
1007 if (status & (1 << codec->addr))
1008 schedule_delayed_work(&codec->jackpoll_work,
1009 codec->jackpoll_interval);
1010 }
1011
1012 /* power down again for link-controlled chips */
e454ff8e 1013 if (!hda->need_i915_power)
029d92c2 1014 display_power(chip, false);
3baffc4a
TI		 1015}
1016
1017#ifdef CONFIG_PM_SLEEP
1018static int azx_suspend(struct device *dev)
1019{
1020 struct snd_card *card = dev_get_drvdata(dev);
1021 struct azx *chip;
1022 struct hdac_bus *bus;
1023
1024 if (!azx_is_pm_ready(card))
c5c21523
TI		 1025 return 0;
1026
3baffc4a 1027 chip = card->private_data;
a41d1224 1028 bus = azx_bus(chip);
421a1252 1029 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3baffc4a 1030 __azx_runtime_suspend(chip);
a41d1224
TI		 1031 if (bus->irq >= 0) {
1032 free_irq(bus->irq, chip);
1033 bus->irq = -1;
f36da940 1034 chip->card->sync_irq = -1;
30b35399 1035 }
a07187c9 1036
68e7fffc 1037 if (chip->msi)
43001c95 1038 pci_disable_msi(chip->pci);
785d8c4b
LY		 1039
1040 trace_azx_suspend(chip);
1da177e4
LT		 1041 return 0;
1042}
1043
68cb2b55 1044static int azx_resume(struct device *dev)
1da177e4 1045{
68cb2b55 1046 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1047 struct azx *chip;
2d9772ef 1048
3baffc4a 1049 if (!azx_is_pm_ready(card))
2d9772ef 1050 return 0;
1da177e4 1051
2d9772ef 1052 chip = card->private_data;
68e7fffc 1053 if (chip->msi)
3baffc4a 1054 if (pci_enable_msi(chip->pci) < 0)
68e7fffc
TI		 1055 chip->msi = 0;
1056 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1057 return -EIO;
744c67ff 1058 __azx_runtime_resume(chip, false);
421a1252 1059 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 1060
1061 trace_azx_resume(chip);
1da177e4
LT		 1062 return 0;
1063}
b8dfc462 1064
3e6db33a
XZ		 1065/* put codec down to D3 at hibernation for Intel SKL+;
1066 * otherwise BIOS may still access the codec and screw up the driver
1067 */
3e6db33a
XZ		 1068static int azx_freeze_noirq(struct device *dev)
1069{
a4b4793f
TI		 1070 struct snd_card *card = dev_get_drvdata(dev);
1071 struct azx *chip = card->private_data;
3e6db33a
XZ		 1072 struct pci_dev *pci = to_pci_dev(dev);
1073
a4b4793f 1074 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1075 pci_set_power_state(pci, PCI_D3hot);
1076
1077 return 0;
1078}
1079
1080static int azx_thaw_noirq(struct device *dev)
1081{
a4b4793f
TI		 1082 struct snd_card *card = dev_get_drvdata(dev);
1083 struct azx *chip = card->private_data;
3e6db33a
XZ		 1084 struct pci_dev *pci = to_pci_dev(dev);
1085
a4b4793f 1086 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1087 pci_set_power_state(pci, PCI_D0);
1088
1089 return 0;
1090}
1091#endif /* CONFIG_PM_SLEEP */
1092
b8dfc462
ML		 1093static int azx_runtime_suspend(struct device *dev)
1094{
1095 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1096 struct azx *chip;
b8dfc462 1097
3baffc4a 1098 if (!azx_is_pm_ready(card))
2d9772ef 1099 return 0;
2d9772ef 1100 chip = card->private_data;
364aa716 1101 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1102 return 0;
1103
7d4f606c
WX		 1104 /* enable controller wake up event */
1105 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1106 STATESTS_INT_MASK);
1107
3baffc4a 1108 __azx_runtime_suspend(chip);
785d8c4b 1109 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1110 return 0;
1111}
1112
1113static int azx_runtime_resume(struct device *dev)
1114{
1115 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1116 struct azx *chip;
b8dfc462 1117
3baffc4a 1118 if (!azx_is_pm_ready(card))
2d9772ef 1119 return 0;
2d9772ef 1120 chip = card->private_data;
364aa716 1121 if (!azx_has_pm_runtime(chip))
246efa4a 1122 return 0;
744c67ff 1123 __azx_runtime_resume(chip, true);
7d4f606c
WX		 1124
1125 /* disable controller Wake Up event*/
1126 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1127 ~STATESTS_INT_MASK);
1128
785d8c4b 1129 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1130 return 0;
1131}
6eb827d2
TI		 1132
1133static int azx_runtime_idle(struct device *dev)
1134{
1135 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1136 struct azx *chip;
1137 struct hda_intel *hda;
1138
1139 if (!card)
1140 return 0;
6eb827d2 1141
2d9772ef
TI		 1142 chip = card->private_data;
1143 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1144 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1145 return 0;
1146
55ed9cd1 1147 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1148 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1149 return -EBUSY;
1150
37a3a98e 1151 /* ELD notification gets broken when HD-audio bus is off */
dd23e1d5 1152 if (needs_eld_notify_link(chip))
37a3a98e
TI		 1153 return -EBUSY;
1154
6eb827d2
TI		 1155 return 0;
1156}
1157
b8dfc462
ML		 1158static const struct dev_pm_ops azx_pm = {
1159 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1160#ifdef CONFIG_PM_SLEEP
1161 .freeze_noirq = azx_freeze_noirq,
1162 .thaw_noirq = azx_thaw_noirq,
1163#endif
6eb827d2 1164 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1165};
1166
68cb2b55
TI		 1167#define AZX_PM_OPS &azx_pm
1168#else
3baffc4a
TI		 1169#define azx_add_card_list(chip) /* NOP */
1170#define azx_del_card_list(chip) /* NOP */
68cb2b55 1171#define AZX_PM_OPS NULL
b8dfc462 1172#endif /* CONFIG_PM */
1da177e4
LT		 1173
1174
48c8b0eb 1175static int azx_probe_continue(struct azx *chip);
a82d51ed 1176
8393ec4a 1177#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1178static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1179
a82d51ed
TI		 1180static void azx_vs_set_state(struct pci_dev *pci,
1181 enum vga_switcheroo_state state)
1182{
1183 struct snd_card *card = pci_get_drvdata(pci);
1184 struct azx *chip = card->private_data;
9a34af4a 1185 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
07f4f97d 1186 struct hda_codec *codec;
a82d51ed
TI		 1187 bool disabled;
1188
9a34af4a
TI		 1189 wait_for_completion(&hda->probe_wait);
1190 if (hda->init_failed)
a82d51ed
TI		 1191 return;
1192
1193 disabled = (state == VGA_SWITCHEROO_OFF);
1194 if (chip->disabled == disabled)
1195 return;
1196
a41d1224 1197 if (!hda->probe_continued) {
a82d51ed
TI		 1198 chip->disabled = disabled;
1199 if (!disabled) {
4e76a883
TI		 1200 dev_info(chip->card->dev,
1201 "Start delayed initialization\n");
5c90680e 1202 if (azx_probe_continue(chip) < 0) {
4e76a883 1203 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1204 hda->init_failed = true;
a82d51ed
TI		 1205 }
1206 }
1207 } else {
2b760d88 1208 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1209 disabled ? "Disabling" : "Enabling");
a82d51ed 1210 if (disabled) {
07f4f97d
LW		 1211 list_for_each_codec(codec, &chip->bus) {
1212 pm_runtime_suspend(hda_codec_dev(codec));
1213 pm_runtime_disable(hda_codec_dev(codec));
1214 }
1215 pm_runtime_suspend(card->dev);
1216 pm_runtime_disable(card->dev);
2b760d88 1217 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1218 * however we have no ACPI handle, so pci/acpi can't put us there,
1219 * put ourselves there */
1220 pci->current_state = PCI_D3cold;
a82d51ed 1221 chip->disabled = true;
a41d1224 1222 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1223 dev_warn(chip->card->dev,
1224 "Cannot lock devices!\n");
a82d51ed 1225 } else {
a41d1224 1226 snd_hda_unlock_devices(&chip->bus);
a82d51ed 1227 chip->disabled = false;
07f4f97d
LW		 1228 pm_runtime_enable(card->dev);
1229 list_for_each_codec(codec, &chip->bus) {
1230 pm_runtime_enable(hda_codec_dev(codec));
1231 pm_runtime_resume(hda_codec_dev(codec));
1232 }
a82d51ed
TI		 1233 }
1234 }
1235}
1236
1237static bool azx_vs_can_switch(struct pci_dev *pci)
1238{
1239 struct snd_card *card = pci_get_drvdata(pci);
1240 struct azx *chip = card->private_data;
9a34af4a 1241 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1242
9a34af4a
TI		 1243 wait_for_completion(&hda->probe_wait);
1244 if (hda->init_failed)
a82d51ed 1245 return false;
a41d1224 1246 if (chip->disabled || !hda->probe_continued)
a82d51ed 1247 return true;
a41d1224 1248 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1249 return false;
a41d1224 1250 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1251 return true;
1252}
1253
37a3a98e
TI		 1254/*
1255 * The discrete GPU cannot power down unless the HDA controller runtime
1256 * suspends, so activate runtime PM on codecs even if power_save == 0.
1257 */
1258static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1259{
1260 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1261 struct hda_codec *codec;
1262
dd23e1d5 1263 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
37a3a98e
TI		 1264 list_for_each_codec(codec, &chip->bus)
1265 codec->auto_runtime_pm = 1;
1266 /* reset the power save setup */
1267 if (chip->running)
1268 set_default_power_save(chip);
1269 }
1270}
1271
1272static void azx_vs_gpu_bound(struct pci_dev *pci,
1273 enum vga_switcheroo_client_id client_id)
1274{
1275 struct snd_card *card = pci_get_drvdata(pci);
1276 struct azx *chip = card->private_data;
37a3a98e
TI		 1277
1278 if (client_id == VGA_SWITCHEROO_DIS)
dd23e1d5 1279 chip->bus.keep_power = 0;
37a3a98e
TI		 1280 setup_vga_switcheroo_runtime_pm(chip);
1281}
1282
e23e7a14 1283static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1284{
9a34af4a 1285 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1286 struct pci_dev *p = get_bound_vga(chip->pci);
bacd8614 1287 struct pci_dev *parent;
a82d51ed 1288 if (p) {
4e76a883 1289 dev_info(chip->card->dev,
2b760d88 1290 "Handle vga_switcheroo audio client\n");
9a34af4a 1291 hda->use_vga_switcheroo = 1;
bacd8614
KHF		 1292
1293 /* cleared in either gpu_bound op or codec probe, or when its
1294 * upstream port has _PR3 (i.e. dGPU).
1295 */
1296 parent = pci_upstream_bridge(p);
1297 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
07f4f97d 1298 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
a82d51ed
TI		 1299 pci_dev_put(p);
1300 }
1301}
1302
1303static const struct vga_switcheroo_client_ops azx_vs_ops = {
1304 .set_gpu_state = azx_vs_set_state,
1305 .can_switch = azx_vs_can_switch,
37a3a98e 1306 .gpu_bound = azx_vs_gpu_bound,
a82d51ed
TI		 1307};
1308
e23e7a14 1309static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1310{
9a34af4a 1311 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4aaf448f 1312 struct pci_dev *p;
128960a9
TI		 1313 int err;
1314
9a34af4a 1315 if (!hda->use_vga_switcheroo)
a82d51ed 1316 return 0;
4aaf448f
JQ		 1317
1318 p = get_bound_vga(chip->pci);
1319 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1320 pci_dev_put(p);
1321
128960a9
TI		 1322 if (err < 0)
1323 return err;
9a34af4a 1324 hda->vga_switcheroo_registered = 1;
246efa4a 1325
128960a9 1326 return 0;
a82d51ed
TI		 1327}
1328#else
1329#define init_vga_switcheroo(chip) /* NOP */
1330#define register_vga_switcheroo(chip) 0
8393ec4a 1331#define check_hdmi_disabled(pci) false
37a3a98e 1332#define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
a82d51ed
TI		 1333#endif /* SUPPORT_VGA_SWITCHER */
1334
1da177e4
LT		 1335/*
1336 * destructor
1337 */
a98f90fd 1338static int azx_free(struct azx *chip)
1da177e4 1339{
c67e2228 1340 struct pci_dev *pci = chip->pci;
a07187c9 1341 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1342 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1343
364aa716 1344 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228 1345 pm_runtime_get_noresume(&pci->dev);
37a3a98e 1346 chip->running = 0;
c67e2228 1347
65fcd41d
TI		 1348 azx_del_card_list(chip);
1349
9a34af4a
TI		 1350 hda->init_failed = 1; /* to be sure */
1351 complete_all(&hda->probe_wait);
f4c482a4 1352
9a34af4a 1353 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1354 if (chip->disabled && hda->probe_continued)
1355 snd_hda_unlock_devices(&chip->bus);
07f4f97d 1356 if (hda->vga_switcheroo_registered)
128960a9 1357 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1358 }
1359
a41d1224 1360 if (bus->chip_init) {
9ad593f6 1361 azx_clear_irq_pending(chip);
7833c3f8 1362 azx_stop_all_streams(chip);
1a7f60b9 1363 azx_stop_chip(chip);
1da177e4
LT		 1364 }
1365
a41d1224
TI		 1366 if (bus->irq >= 0)
1367 free_irq(bus->irq, (void*)chip);
68e7fffc 1368 if (chip->msi)
30b35399 1369 pci_disable_msi(chip->pci);
a41d1224 1370 iounmap(bus->remap_addr);
1da177e4 1371
67908994 1372 azx_free_stream_pages(chip);
a41d1224
TI		 1373 azx_free_streams(chip);
1374 snd_hdac_bus_exit(bus);
1375
a82d51ed
TI		 1376 if (chip->region_requested)
1377 pci_release_regions(chip->pci);
a41d1224 1378
1da177e4 1379 pci_disable_device(chip->pci);
4918cdab 1380#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1381 release_firmware(chip->fw);
4918cdab 1382#endif
e454ff8e 1383 display_power(chip, false);
98d8fc6c 1384
fc18282c 1385 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
fcc88d91 1386 snd_hdac_i915_exit(bus);
a07187c9 1387 kfree(hda);
1da177e4
LT		 1388
1389 return 0;
1390}
1391
a41d1224
TI		 1392static int azx_dev_disconnect(struct snd_device *device)
1393{
1394 struct azx *chip = device->device_data;
ca58f551 1395 struct hdac_bus *bus = azx_bus(chip);
a41d1224
TI		 1396
1397 chip->bus.shutdown = 1;
ca58f551
TI		 1398 cancel_work_sync(&bus->unsol_work);
1399
a41d1224
TI		 1400 return 0;
1401}
1402
a98f90fd 1403static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1404{
1405 return azx_free(device->device_data);
1406}
1407
8393ec4a 1408#ifdef SUPPORT_VGA_SWITCHEROO
586bc4aa
AD		 1409#ifdef CONFIG_ACPI
1410/* ATPX is in the integrated GPU's namespace */
1411static bool atpx_present(void)
1412{
1413 struct pci_dev *pdev = NULL;
1414 acpi_handle dhandle, atpx_handle;
1415 acpi_status status;
1416
8cc0991c
AD		 1417 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1418 dhandle = ACPI_HANDLE(&pdev->dev);
1419 if (dhandle) {
1420 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1421 if (!ACPI_FAILURE(status)) {
1422 pci_dev_put(pdev);
1423 return true;
1424 }
1425 }
1426 }
1427 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
586bc4aa
AD		 1428 dhandle = ACPI_HANDLE(&pdev->dev);
1429 if (dhandle) {
1430 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1431 if (!ACPI_FAILURE(status)) {
1432 pci_dev_put(pdev);
1433 return true;
1434 }
1435 }
586bc4aa
AD		 1436 }
1437 return false;
1438}
1439#else
1440static bool atpx_present(void)
1441{
1442 return false;
1443}
1444#endif
1445
9121947d 1446/*
2b760d88 1447 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1448 */
e23e7a14 1449static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1450{
1451 struct pci_dev *p;
1452
1453 /* check only discrete GPU */
1454 switch (pci->vendor) {
1455 case PCI_VENDOR_ID_ATI:
1456 case PCI_VENDOR_ID_AMD:
586bc4aa
AD		 1457 if (pci->devfn == 1) {
1458 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1459 pci->bus->number, 0);
1460 if (p) {
1461 /* ATPX is in the integrated GPU's ACPI namespace
1462 * rather than the dGPU's namespace. However,
1463 * the dGPU is the one who is involved in
1464 * vgaswitcheroo.
1465 */
1466 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1467 atpx_present())
1468 return p;
1469 pci_dev_put(p);
1470 }
1471 }
1472 break;
9121947d
TI		 1473 case PCI_VENDOR_ID_NVIDIA:
1474 if (pci->devfn == 1) {
1475 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1476 pci->bus->number, 0);
1477 if (p) {
b6d7b362 1478 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
9121947d
TI		 1479 return p;
1480 pci_dev_put(p);
1481 }
1482 }
1483 break;
1484 }
1485 return NULL;
1486}
1487
e23e7a14 1488static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1489{
1490 bool vga_inactive = false;
1491 struct pci_dev *p = get_bound_vga(pci);
1492
1493 if (p) {
12b78a7f 1494 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1495 vga_inactive = true;
1496 pci_dev_put(p);
1497 }
1498 return vga_inactive;
1499}
8393ec4a 1500#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1501
3372a153
TI		 1502/*
1503 * white/black-listing for position_fix
1504 */
a5dc05e4 1505static const struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1506 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1507 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1508 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1509 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1510 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1511 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1512 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1513 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1514 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1515 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1516 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1517 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1518 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1519 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1520 {}
1521};
1522
e23e7a14 1523static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1524{
1525 const struct snd_pci_quirk *q;
1526
c673ba1c 1527 switch (fix) {
1dac6695 1528 case POS_FIX_AUTO:
c673ba1c
TI		 1529 case POS_FIX_LPIB:
1530 case POS_FIX_POSBUF:
4cb36310 1531 case POS_FIX_VIACOMBO:
a6f2fd55 1532 case POS_FIX_COMBO:
f87e7f25 1533 case POS_FIX_SKL:
c02f77d3 1534 case POS_FIX_FIFO:
c673ba1c
TI		 1535 return fix;
1536 }
1537
c673ba1c
TI		 1538 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1539 if (q) {
4e76a883
TI		 1540 dev_info(chip->card->dev,
1541 "position_fix set to %d for device %04x:%04x\n",
1542 q->value, q->subvendor, q->subdevice);
c673ba1c 1543 return q->value;
3372a153 1544 }
bdd9ef24
DH		 1545
1546 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1547 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1548 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1549 return POS_FIX_VIACOMBO;
9477c58e 1550 }
c02f77d3
TI		 1551 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1552 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1553 return POS_FIX_FIFO;
1554 }
9477c58e 1555 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1556 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1557 return POS_FIX_LPIB;
bdd9ef24 1558 }
a4b4793f 1559 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1560 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1561 return POS_FIX_SKL;
1562 }
c673ba1c 1563 return POS_FIX_AUTO;
3372a153
TI		 1564}
1565
b6050ef6
TI		 1566static void assign_position_fix(struct azx *chip, int fix)
1567{
bf82326f 1568 static const azx_get_pos_callback_t callbacks[] = {
b6050ef6
TI		 1569 [POS_FIX_AUTO] = NULL,
1570 [POS_FIX_LPIB] = azx_get_pos_lpib,
1571 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1572 [POS_FIX_VIACOMBO] = azx_via_get_position,
1573 [POS_FIX_COMBO] = azx_get_pos_lpib,
f87e7f25 1574 [POS_FIX_SKL] = azx_get_pos_skl,
c02f77d3 1575 [POS_FIX_FIFO] = azx_get_pos_fifo,
b6050ef6
TI		 1576 };
1577
1578 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1579
1580 /* combo mode uses LPIB only for playback */
1581 if (fix == POS_FIX_COMBO)
1582 chip->get_position[1] = NULL;
1583
f87e7f25 1584 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1585 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1586 chip->get_delay[0] = chip->get_delay[1] =
1587 azx_get_delay_from_lpib;
1588 }
1589
c02f77d3
TI		 1590 if (fix == POS_FIX_FIFO)
1591 chip->get_delay[0] = chip->get_delay[1] =
1592 azx_get_delay_from_fifo;
b6050ef6
TI		 1593}
1594
669ba27a
TI		 1595/*
1596 * black-lists for probe_mask
1597 */
a5dc05e4 1598static const struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1599 /* Thinkpad often breaks the controller communication when accessing
1600 * to the non-working (or non-existing) modem codec slot.
1601 */
1602 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1603 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1604 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1605 /* broken BIOS */
1606 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1607 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1608 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1609 /* forced codec slots */
93574844 1610 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1611 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1612 /* WinFast VP200 H (Teradici) user reported broken communication */
1613 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1614 {}
1615};
1616
f1eaaeec
TI		 1617#define AZX_FORCE_CODEC_MASK 0x100
1618
e23e7a14 1619static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1620{
1621 const struct snd_pci_quirk *q;
1622
f1eaaeec
TI		 1623 chip->codec_probe_mask = probe_mask[dev];
1624 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1625 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1626 if (q) {
4e76a883
TI		 1627 dev_info(chip->card->dev,
1628 "probe_mask set to 0x%x for device %04x:%04x\n",
1629 q->value, q->subvendor, q->subdevice);
f1eaaeec 1630 chip->codec_probe_mask = q->value;
669ba27a
TI		 1631 }
1632 }
f1eaaeec
TI		 1633
1634 /* check forced option */
1635 if (chip->codec_probe_mask != -1 &&
1636 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1637 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1638 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1639 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1640 }
669ba27a
TI		 1641}
1642
4d8e22e0 1643/*
71623855 1644 * white/black-list for enable_msi
4d8e22e0 1645 */
a5dc05e4 1646static const struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1647 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1648 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1649 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1650 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1651 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1652 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1653 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1654 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1655 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1656 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1657 {}
1658};
1659
e23e7a14 1660static void check_msi(struct azx *chip)
4d8e22e0
TI		 1661{
1662 const struct snd_pci_quirk *q;
1663
71623855
TI		 1664 if (enable_msi >= 0) {
1665 chip->msi = !!enable_msi;
4d8e22e0 1666 return;
71623855
TI		 1667 }
1668 chip->msi = 1; /* enable MSI as default */
1669 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1670 if (q) {
4e76a883
TI		 1671 dev_info(chip->card->dev,
1672 "msi for device %04x:%04x set to %d\n",
1673 q->subvendor, q->subdevice, q->value);
4d8e22e0 1674 chip->msi = q->value;
80c43ed7
TI		 1675 return;
1676 }
1677
1678 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1679 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1680 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1681 chip->msi = 0;
4d8e22e0
TI		 1682 }
1683}
1684
a1585d76 1685/* check the snoop mode availability */
e23e7a14 1686static void azx_check_snoop_available(struct azx *chip)
a1585d76 1687{
7c732015 1688 int snoop = hda_snoop;
a1585d76 1689
7c732015
TI		 1690 if (snoop >= 0) {
1691 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1692 snoop ? "snoop" : "non-snoop");
1693 chip->snoop = snoop;
78c9be61 1694 chip->uc_buffer = !snoop;
7c732015
TI		 1695 return;
1696 }
1697
1698 snoop = true;
37e661ee
TI		 1699 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1700 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1701 /* force to non-snoop mode for a new VIA controller
1702 * when BIOS is set
1703 */
7c732015
TI		 1704 u8 val;
1705 pci_read_config_byte(chip->pci, 0x42, &val);
af52f998
DW		 1706 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1707 chip->pci->revision == 0x20))
7c732015 1708 snoop = false;
a1585d76
TI		 1709 }
1710
37e661ee
TI		 1711 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1712 snoop = false;
1713
7c732015 1714 chip->snoop = snoop;
78c9be61 1715 if (!snoop) {
7c732015 1716 dev_info(chip->card->dev, "Force to non-snoop mode\n");
78c9be61
TI		 1717 /* C-Media requires non-cached pages only for CORB/RIRB */
1718 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1719 chip->uc_buffer = true;
1720 }
a1585d76 1721}
669ba27a 1722
99a2008d
WX		 1723static void azx_probe_work(struct work_struct *work)
1724{
9a34af4a
TI		 1725 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1726 azx_probe_continue(&hda->chip);
99a2008d 1727}
99a2008d 1728
4f0189be
TI		 1729static int default_bdl_pos_adj(struct azx *chip)
1730{
2cf721db
TI		 1731 /* some exceptions: Atoms seem problematic with value 1 */
1732 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1733 switch (chip->pci->device) {
1734 case 0x0f04: /* Baytrail */
1735 case 0x2284: /* Braswell */
1736 return 32;
1737 }
1738 }
1739
4f0189be
TI		 1740 switch (chip->driver_type) {
1741 case AZX_DRIVER_ICH:
1742 case AZX_DRIVER_PCH:
1743 return 1;
1744 default:
1745 return 32;
1746 }
1747}
1748
1da177e4
LT		 1749/*
1750 * constructor
1751 */
a43ff5ba
TI		 1752static const struct hda_controller_ops pci_hda_ops;
1753
e23e7a14
BP		 1754static int azx_create(struct snd_card *card, struct pci_dev *pci,
1755 int dev, unsigned int driver_caps,
1756 struct azx **rchip)
1da177e4 1757{
41f394a8 1758 static const struct snd_device_ops ops = {
a41d1224 1759 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1760 .dev_free = azx_dev_free,
1761 };
a07187c9 1762 struct hda_intel *hda;
a82d51ed
TI		 1763 struct azx *chip;
1764 int err;
1da177e4
LT		 1765
1766 *rchip = NULL;
bcd72003 1767
927fc866
PM		 1768 err = pci_enable_device(pci);
1769 if (err < 0)
1da177e4
LT		 1770 return err;
1771
a07187c9
ML		 1772 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1773 if (!hda) {
1da177e4
LT		 1774 pci_disable_device(pci);
1775 return -ENOMEM;
1776 }
1777
a07187c9 1778 chip = &hda->chip;
62932df8 1779 mutex_init(&chip->open_mutex);
1da177e4
LT		 1780 chip->card = card;
1781 chip->pci = pci;
a43ff5ba 1782 chip->ops = &pci_hda_ops;
9477c58e
TI		 1783 chip->driver_caps = driver_caps;
1784 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1785 check_msi(chip);
555e219f 1786 chip->dev_index = dev;
3a182c84
TI		 1787 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1788 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
01b65bfb 1789 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1790 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1791 INIT_LIST_HEAD(&hda->list);
a82d51ed 1792 init_vga_switcheroo(chip);
9a34af4a 1793 init_completion(&hda->probe_wait);
1da177e4 1794
b6050ef6 1795 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1796
5aba4f8e 1797 check_probe_mask(chip, dev);
3372a153 1798
41438f13
TI		 1799 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1800 chip->fallback_to_single_cmd = 1;
1801 else /* explicitly set to single_cmd or not */
1802 chip->single_cmd = single_cmd;
1803
a1585d76 1804 azx_check_snoop_available(chip);
c74db86b 1805
4f0189be
TI		 1806 if (bdl_pos_adj[dev] < 0)
1807 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1808 else
1809 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1810
19abfefd 1811 err = azx_bus_init(chip, model[dev]);
a41d1224
TI		 1812 if (err < 0) {
1813 kfree(hda);
1814 pci_disable_device(pci);
1815 return err;
1816 }
1817
619a1f19
TI		 1818 /* use the non-cached pages in non-snoop mode */
1819 if (!azx_snoop(chip))
1820 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1821
7d9a1808
TI		 1822 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1823 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
5f2cb361 1824 chip->bus.core.needs_damn_long_delay = 1;
7d9a1808
TI		 1825 }
1826
a82d51ed
TI		 1827 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1828 if (err < 0) {
4e76a883 1829 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1830 azx_free(chip);
1831 return err;
1832 }
1833
99a2008d 1834 /* continue probing in work context as may trigger request module */
9a34af4a 1835 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1836
a82d51ed 1837 *rchip = chip;
99a2008d 1838
a82d51ed
TI		 1839 return 0;
1840}
1841
48c8b0eb 1842static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1843{
1844 int dev = chip->dev_index;
1845 struct pci_dev *pci = chip->pci;
1846 struct snd_card *card = chip->card;
a41d1224 1847 struct hdac_bus *bus = azx_bus(chip);
67908994 1848 int err;
a82d51ed 1849 unsigned short gcap;
413cbf46 1850 unsigned int dma_bits = 64;
a82d51ed 1851
07e4ca50
TI		 1852#if BITS_PER_LONG != 64
1853 /* Fix up base address on ULI M5461 */
1854 if (chip->driver_type == AZX_DRIVER_ULI) {
1855 u16 tmp3;
1856 pci_read_config_word(pci, 0x40, &tmp3);
1857 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1858 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1859 }
1860#endif
1861
927fc866 1862 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1863 if (err < 0)
1da177e4 1864 return err;
a82d51ed 1865 chip->region_requested = 1;
1da177e4 1866
a41d1224
TI		 1867 bus->addr = pci_resource_start(pci, 0);
1868 bus->remap_addr = pci_ioremap_bar(pci, 0);
1869 if (bus->remap_addr == NULL) {
4e76a883 1870 dev_err(card->dev, "ioremap error\n");
a82d51ed 1871 return -ENXIO;
1da177e4
LT		 1872 }
1873
a4b4793f 1874 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1875 snd_hdac_bus_parse_capabilities(bus);
1876
1877 /*
1878 * Some Intel CPUs has always running timer (ART) feature and
1879 * controller may have Global time sync reporting capability, so
1880 * check both of these before declaring synchronized time reporting
1881 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1882 */
1883 chip->gts_present = false;
1884
1885#ifdef CONFIG_X86
1886 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1887 chip->gts_present = true;
1888#endif
1889
db79afa1
BH		 1890 if (chip->msi) {
1891 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1892 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1893 pci->no_64bit_msi = true;
1894 }
68e7fffc
TI		 1895 if (pci_enable_msi(pci) < 0)
1896 chip->msi = 0;
db79afa1 1897 }
7376d013 1898
1da177e4 1899 pci_set_master(pci);
1da177e4 1900
bcd72003 1901 gcap = azx_readw(chip, GCAP);
4e76a883 1902 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1903
413cbf46
TI		 1904 /* AMD devices support 40 or 48bit DMA, take the safe one */
1905 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1906 dma_bits = 40;
1907
dc4c2e6b 1908 /* disable SB600 64bit support for safety */
9477c58e 1909 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1910 struct pci_dev *p_smbus;
413cbf46 1911 dma_bits = 40;
dc4c2e6b
AB		 1912 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1913 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1914 NULL);
1915 if (p_smbus) {
1916 if (p_smbus->revision < 0x30)
fb1d8ac2 1917 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1918 pci_dev_put(p_smbus);
1919 }
1920 }
09240cf4 1921
3ab7511e
AB		 1922 /* NVidia hardware normally only supports up to 40 bits of DMA */
1923 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1924 dma_bits = 40;
1925
9477c58e
TI		 1926 /* disable 64bit DMA address on some devices */
1927 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1928 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1929 gcap &= ~AZX_GCAP_64OK;
9477c58e 1930 }
396087ea 1931
2ae66c26 1932 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1933 if (align_buffer_size >= 0)
1934 chip->align_buffer_size = !!align_buffer_size;
1935 else {
103884a3 1936 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1937 chip->align_buffer_size = 0;
7bfe059e
TI		 1938 else
1939 chip->align_buffer_size = 1;
1940 }
2ae66c26 1941
cf7aaca8 1942 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1943 if (!(gcap & AZX_GCAP_64OK))
1944 dma_bits = 32;
412b979c
QL		 1945 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1946 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1947 } else {
412b979c
QL		 1948 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1949 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1950 }
cf7aaca8 1951
8b6ed8e7
TI		 1952 /* read number of streams from GCAP register instead of using
1953 * hardcoded value
1954 */
1955 chip->capture_streams = (gcap >> 8) & 0x0f;
1956 chip->playback_streams = (gcap >> 12) & 0x0f;
1957 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1958 /* gcap didn't give any info, switching to old method */
1959
1960 switch (chip->driver_type) {
1961 case AZX_DRIVER_ULI:
1962 chip->playback_streams = ULI_NUM_PLAYBACK;
1963 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1964 break;
1965 case AZX_DRIVER_ATIHDMI:
1815b34a 1966 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1967 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1968 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1969 break;
c4da29ca 1970 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1971 default:
1972 chip->playback_streams = ICH6_NUM_PLAYBACK;
1973 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1974 break;
1975 }
07e4ca50 1976 }
8b6ed8e7
TI		 1977 chip->capture_index_offset = 0;
1978 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1979 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1980
df56c3db
JK		 1981 /* sanity check for the SDxCTL.STRM field overflow */
1982 if (chip->num_streams > 15 &&
1983 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1984 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1985 "forcing separate stream tags", chip->num_streams);
1986 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1987 }
1988
a41d1224
TI		 1989 /* initialize streams */
1990 err = azx_init_streams(chip);
81740861 1991 if (err < 0)
a82d51ed 1992 return err;
1da177e4 1993
a41d1224
TI		 1994 err = azx_alloc_stream_pages(chip);
1995 if (err < 0)
1996 return err;
1da177e4
LT		 1997
1998 /* initialize chip */
cb53c626 1999 azx_init_pci(chip);
e4d9e513 2000
e454ff8e 2001 snd_hdac_i915_set_bclk(bus);
e4d9e513 2002
0a673521 2003 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 2004
2005 /* codec detection */
a41d1224 2006 if (!azx_bus(chip)->codec_mask) {
4e76a883 2007 dev_err(card->dev, "no codecs found!\n");
a82d51ed 2008 return -ENODEV;
1da177e4
LT		 2009 }
2010
f495222e
TI		 2011 if (azx_acquire_irq(chip, 0) < 0)
2012 return -EBUSY;
2013
07e4ca50 2014 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 2015 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2016 sizeof(card->shortname));
2017 snprintf(card->longname, sizeof(card->longname),
2018 "%s at 0x%lx irq %i",
a41d1224 2019 card->shortname, bus->addr, bus->irq);
07e4ca50 2020
1da177e4 2021 return 0;
1da177e4
LT		 2022}
2023
97c6a3d1 2024#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 2025/* callback from request_firmware_nowait() */
2026static void azx_firmware_cb(const struct firmware *fw, void *context)
2027{
2028 struct snd_card *card = context;
2029 struct azx *chip = card->private_data;
2030 struct pci_dev *pci = chip->pci;
2031
2032 if (!fw) {
4e76a883 2033 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 2034 goto error;
2035 }
2036
2037 chip->fw = fw;
2038 if (!chip->disabled) {
2039 /* continue probing */
2040 if (azx_probe_continue(chip))
2041 goto error;
2042 }
2043 return; /* OK */
2044
2045 error:
2046 snd_card_free(card);
2047 pci_set_drvdata(pci, NULL);
2048}
97c6a3d1 2049#endif
5cb543db 2050
f46ea609
DR		 2051static int disable_msi_reset_irq(struct azx *chip)
2052{
a41d1224 2053 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 2054 int err;
2055
a41d1224
TI		 2056 free_irq(bus->irq, chip);
2057 bus->irq = -1;
f36da940 2058 chip->card->sync_irq = -1;
f46ea609
DR		 2059 pci_disable_msi(chip->pci);
2060 chip->msi = 0;
2061 err = azx_acquire_irq(chip, 1);
2062 if (err < 0)
2063 return err;
2064
2065 return 0;
2066}
2067
8769b278
DR		 2068static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2069 struct vm_area_struct *area)
2070{
2071#ifdef CONFIG_X86
2072 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2073 struct azx *chip = apcm->chip;
78c9be61 2074 if (chip->uc_buffer)
8769b278
DR		 2075 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2076#endif
2077}
2078
3c6fd1f0
TI		 2079/* Blacklist for skipping the whole probe:
2080 * some HD-audio PCI entries are exposed without any codecs, and such devices
2081 * should be ignored from the beginning.
2082 */
2083static const struct snd_pci_quirk driver_blacklist[] = {
2084 SND_PCI_QUIRK(0x1043, 0x874f, "ASUS ROG Zenith II / Strix", 0),
2085 SND_PCI_QUIRK(0x1462, 0xcb59, "MSI TRX40 Creator", 0),
2086 SND_PCI_QUIRK(0x1462, 0xcb60, "MSI TRX40", 0),
2087 {}
2088};
2089
a43ff5ba
TI		 2090static const struct hda_controller_ops pci_hda_ops = {
2091 .disable_msi_reset_irq = disable_msi_reset_irq,
8769b278 2092 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 2093 .position_check = azx_position_check,
40830813
DR		 2094};
2095
e23e7a14
BP		 2096static int azx_probe(struct pci_dev *pci,
2097 const struct pci_device_id *pci_id)
1da177e4 2098{
5aba4f8e 2099 static int dev;
a98f90fd 2100 struct snd_card *card;
9a34af4a 2101 struct hda_intel *hda;
a98f90fd 2102 struct azx *chip;
aad730d0 2103 bool schedule_probe;
927fc866 2104 int err;
1da177e4 2105
3c6fd1f0
TI		 2106 if (snd_pci_quirk_lookup(pci, driver_blacklist)) {
2107 dev_info(&pci->dev, "Skipping the blacklisted device\n");
2108 return -ENODEV;
2109 }
2110
5aba4f8e
TI		 2111 if (dev >= SNDRV_CARDS)
2112 return -ENODEV;
2113 if (!enable[dev]) {
2114 dev++;
2115 return -ENOENT;
2116 }
2117
82d9d54a
JK		 2118 /*
2119 * stop probe if another Intel's DSP driver should be activated
2120 */
7fba6aea 2121 if (dmic_detect) {
82d9d54a
JK		 2122 err = snd_intel_dsp_driver_probe(pci);
2123 if (err != SND_INTEL_DSP_DRIVER_ANY &&
2124 err != SND_INTEL_DSP_DRIVER_LEGACY)
2125 return -ENODEV;
7fba6aea
TI		 2126 } else {
2127 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
82d9d54a
JK		 2128 }
2129
60c5772b
TI		 2130 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2131 0, &card);
e58de7ba 2132 if (err < 0) {
4e76a883 2133 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2134 return err;
1da177e4
LT		 2135 }
2136
a43ff5ba 2137 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2138 if (err < 0)
2139 goto out_free;
421a1252 2140 card->private_data = chip;
9a34af4a 2141 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2142
2143 pci_set_drvdata(pci, card);
2144
2145 err = register_vga_switcheroo(chip);
2146 if (err < 0) {
2b760d88 2147 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2148 goto out_free;
2149 }
2150
2151 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2152 dev_info(card->dev, "VGA controller is disabled\n");
2153 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2154 chip->disabled = true;
2155 }
2156
aad730d0 2157 schedule_probe = !chip->disabled;
1da177e4 2158
4918cdab
TI		 2159#ifdef CONFIG_SND_HDA_PATCH_LOADER
2160 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2161 dev_info(card->dev, "Applying patch firmware '%s'\n",
2162 patch[dev]);
5cb543db
TI		 2163 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2164 &pci->dev, GFP_KERNEL, card,
2165 azx_firmware_cb);
4918cdab
TI		 2166 if (err < 0)
2167 goto out_free;
aad730d0 2168 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2169 }
2170#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2171
aad730d0 2172#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2173 if (CONTROLLER_IN_GPU(pci))
2174 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2175#endif
99a2008d 2176
aad730d0 2177 if (schedule_probe)
9a34af4a 2178 schedule_work(&hda->probe_work);
a82d51ed 2179
a82d51ed 2180 dev++;
88d071fc 2181 if (chip->disabled)
9a34af4a 2182 complete_all(&hda->probe_wait);
a82d51ed
TI		 2183 return 0;
2184
2185out_free:
2186 snd_card_free(card);
2187 return err;
2188}
2189
1ba8f9d3
HG		 2190#ifdef CONFIG_PM
2191/* On some boards setting power_save to a non 0 value leads to clicking /
2192 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2193 * figure out how to avoid these sounds, but that is not always feasible.
2194 * So we keep a list of devices where we disable powersaving as its known
2195 * to causes problems on these devices.
2196 */
a5dc05e4 2197static const struct snd_pci_quirk power_save_blacklist[] = {
1ba8f9d3 2198 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
8e82a728 2199 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
1ba8f9d3 2200 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
39070a98
HG		 2201 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2202 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
45e5fbc2
HG		 2203 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2204 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
1ba8f9d3 2205 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
b529ef24
HG		 2206 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2207 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
38d9c12c 2208 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
d8feb608
HG		 2209 SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0),
2210 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
5cb6b5fc
HG		 2211 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2212 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
38d9c12c
HG		 2213 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2214 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
5cb6b5fc
HG		 2215 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2216 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
f91f1806
HG		 2217 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2218 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
cae30527
HW		 2219 /* https://bugs.launchpad.net/bugs/1821663 */
2220 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
dd6dd536
HG		 2221 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2222 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
1ba8f9d3
HG		 2223 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2224 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
721f1e6c
JK		 2225 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2226 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2227 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2228 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
cae30527
HW		 2229 /* https://bugs.launchpad.net/bugs/1821663 */
2230 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
1ba8f9d3
HG		 2231 {}
2232};
2233#endif /* CONFIG_PM */
2234
37a3a98e
TI		 2235static void set_default_power_save(struct azx *chip)
2236{
2237 int val = power_save;
2238
2239#ifdef CONFIG_PM
2240 if (pm_blacklist) {
2241 const struct snd_pci_quirk *q;
2242
2243 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2244 if (q && val) {
2245 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2246 q->subvendor, q->subdevice);
2247 val = 0;
2248 }
2249 }
2250#endif /* CONFIG_PM */
2251 snd_hda_set_power_save(&chip->bus, val * 1000);
2252}
2253
e62a42ae 2254/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
bf82326f 2255static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
e62a42ae
DR		 2256 [AZX_DRIVER_NVIDIA] = 8,
2257 [AZX_DRIVER_TERA] = 1,
2258};
2259
48c8b0eb 2260static int azx_probe_continue(struct azx *chip)
a82d51ed 2261{
9a34af4a 2262 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2263 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2264 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2265 int dev = chip->dev_index;
2266 int err;
2267
305a0ade 2268 to_hda_bus(bus)->bus_probing = 1;
a41d1224 2269 hda->probe_continued = 1;
795614dd 2270
fcc88d91 2271 /* bind with i915 if needed */
dba9b7b6 2272 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
98d8fc6c 2273 err = snd_hdac_i915_init(bus);
535115b5
TI		 2274 if (err < 0) {
2275 /* if the controller is bound only with HDMI/DP
2276 * (for HSW and BDW), we need to abort the probe;
2277 * for other chips, still continue probing as other
2278 * codecs can be on the same link.
2279 */
bed2e98e
TI		 2280 if (CONTROLLER_IN_GPU(pci)) {
2281 dev_err(chip->card->dev,
2282 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2283 goto out_free;
fcc88d91
TI		 2284 } else {
2285 /* don't bother any longer */
e454ff8e 2286 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
fcc88d91 2287 }
535115b5 2288 }
e454ff8e
TI		 2289
2290 /* HSW/BDW controllers need this power */
2291 if (CONTROLLER_IN_GPU(pci))
2292 hda->need_i915_power = 1;
fcc88d91
TI		 2293 }
2294
2295 /* Request display power well for the HDA controller or codec. For
2296 * Haswell/Broadwell, both the display HDA controller and codec need
2297 * this power. For other platforms, like Baytrail/Braswell, only the
2298 * display codec needs the power and it can be released after probe.
2299 */
4f799e73 2300 display_power(chip, true);
99a2008d 2301
5c90680e
TI		 2302 err = azx_first_init(chip);
2303 if (err < 0)
2304 goto out_free;
2305
2dca0bba
JK		 2306#ifdef CONFIG_SND_HDA_INPUT_BEEP
2307 chip->beep_mode = beep_mode[dev];
2308#endif
2309
1da177e4 2310 /* create codec instances */
96d2bd6e 2311 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2312 if (err < 0)
2313 goto out_free;
96d2bd6e 2314
4ea6fbc8 2315#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2316 if (chip->fw) {
a41d1224 2317 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2318 chip->fw->data);
4ea6fbc8
TI		 2319 if (err < 0)
2320 goto out_free;
e39ae856 2321#ifndef CONFIG_PM
4918cdab
TI		 2322 release_firmware(chip->fw); /* no longer needed */
2323 chip->fw = NULL;
e39ae856 2324#endif
4ea6fbc8
TI		 2325 }
2326#endif
10e77dda 2327 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2328 err = azx_codec_configure(chip);
2329 if (err < 0)
2330 goto out_free;
2331 }
1da177e4 2332
a82d51ed 2333 err = snd_card_register(chip->card);
41dda0fd
WF		 2334 if (err < 0)
2335 goto out_free;
1da177e4 2336
37a3a98e
TI		 2337 setup_vga_switcheroo_runtime_pm(chip);
2338
cb53c626 2339 chip->running = 1;
65fcd41d 2340 azx_add_card_list(chip);
07f4f97d 2341
37a3a98e 2342 set_default_power_save(chip);
07f4f97d 2343
07f4f97d 2344 if (azx_has_pm_runtime(chip))
30ff5957 2345 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2346
41dda0fd 2347out_free:
457f3c86 2348 if (err < 0 || !hda->need_i915_power)
029d92c2 2349 display_power(chip, false);
88d071fc 2350 if (err < 0)
9a34af4a
TI		 2351 hda->init_failed = 1;
2352 complete_all(&hda->probe_wait);
305a0ade 2353 to_hda_bus(bus)->bus_probing = 0;
41dda0fd 2354 return err;
1da177e4
LT		 2355}
2356
e23e7a14 2357static void azx_remove(struct pci_dev *pci)
1da177e4 2358{
9121947d 2359 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2360 struct azx *chip;
2361 struct hda_intel *hda;
2362
2363 if (card) {
0b8c8219 2364 /* cancel the pending probing work */
991f86d7
TI		 2365 chip = card->private_data;
2366 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2367 /* FIXME: below is an ugly workaround.
2368 * Both device_release_driver() and driver_probe_device()
2369 * take *both* the device's and its parent's lock before
2370 * calling the remove() and probe() callbacks. The codec
2371 * probe takes the locks of both the codec itself and its
2372 * parent, i.e. the PCI controller dev. Meanwhile, when
2373 * the PCI controller is unbound, it takes its lock, too
2374 * ==> ouch, a deadlock!
2375 * As a workaround, we unlock temporarily here the controller
2376 * device during cancel_work_sync() call.
2377 */
2378 device_unlock(&pci->dev);
0b8c8219 2379 cancel_work_sync(&hda->probe_work);
ab949d51 2380 device_lock(&pci->dev);
b8dfc462 2381
9121947d 2382 snd_card_free(card);
991f86d7 2383 }
1da177e4
LT		 2384}
2385
b2a0bafa
TI		 2386static void azx_shutdown(struct pci_dev *pci)
2387{
2388 struct snd_card *card = pci_get_drvdata(pci);
2389 struct azx *chip;
2390
2391 if (!card)
2392 return;
2393 chip = card->private_data;
2394 if (chip && chip->running)
2395 azx_stop_chip(chip);
2396}
2397
1da177e4 2398/* PCI IDs */
6f51f6cf 2399static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2400 /* CPT */
9477c58e 2401 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2402 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2403 /* PBG */
9477c58e 2404 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2405 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2406 /* Panther Point */
9477c58e 2407 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2408 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2409 /* Lynx Point */
2410 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2411 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2412 /* 9 Series */
2413 { PCI_DEVICE(0x8086, 0x8ca0),
2414 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2415 /* Wellsburg */
2416 { PCI_DEVICE(0x8086, 0x8d20),
2417 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2418 { PCI_DEVICE(0x8086, 0x8d21),
2419 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2420 /* Lewisburg */
2421 { PCI_DEVICE(0x8086, 0xa1f0),
e7480b34 2422 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
5cf92c8b 2423 { PCI_DEVICE(0x8086, 0xa270),
e7480b34 2424 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
144dad99
JR		 2425 /* Lynx Point-LP */
2426 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2427 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2428 /* Lynx Point-LP */
2429 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2430 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2431 /* Wildcat Point-LP */
2432 { PCI_DEVICE(0x8086, 0x9ca0),
2433 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2434 /* Sunrise Point */
2435 { PCI_DEVICE(0x8086, 0xa170),
a4b4793f 2436 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2437 /* Sunrise Point-LP */
2438 { PCI_DEVICE(0x8086, 0x9d70),
3e9ad24b 2439 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2440 /* Kabylake */
2441 { PCI_DEVICE(0x8086, 0xa171),
a4b4793f 2442 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2443 /* Kabylake-LP */
2444 { PCI_DEVICE(0x8086, 0x9d71),
3e9ad24b 2445 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2446 /* Kabylake-H */
2447 { PCI_DEVICE(0x8086, 0xa2f0),
a4b4793f 2448 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
e79b0006
MD		 2449 /* Coffelake */
2450 { PCI_DEVICE(0x8086, 0xa348),
3e9ad24b 2451 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2357f6f0
GS		 2452 /* Cannonlake */
2453 { PCI_DEVICE(0x8086, 0x9dc8),
3e9ad24b 2454 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
d4c2ccdb
PLB		 2455 /* CometLake-LP */
2456 { PCI_DEVICE(0x8086, 0x02C8),
2457 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2458 /* CometLake-H */
2459 { PCI_DEVICE(0x8086, 0x06C8),
2460 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
b73a5854
CC		 2461 /* CometLake-S */
2462 { PCI_DEVICE(0x8086, 0xa3f0),
2463 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
491f8331
GS		 2464 /* Icelake */
2465 { PCI_DEVICE(0x8086, 0x34c8),
3e9ad24b 2466 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
4750c212
PX		 2467 /* Jasperlake */
2468 { PCI_DEVICE(0x8086, 0x38c8),
2469 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
78be2228
YZ		 2470 { PCI_DEVICE(0x8086, 0x4dc8),
2471 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
4750c212
PX		 2472 /* Tigerlake */
2473 { PCI_DEVICE(0x8086, 0xa0c8),
2474 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
f94287b6
LPS		 2475 /* Elkhart Lake */
2476 { PCI_DEVICE(0x8086, 0x4b55),
2477 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
c87693da
LH		 2478 /* Broxton-P(Apollolake) */
2479 { PCI_DEVICE(0x8086, 0x5a98),
3e9ad24b 2480 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2481 /* Broxton-T */
2482 { PCI_DEVICE(0x8086, 0x1a98),
a4b4793f 2483 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
44b46d73
VK		 2484 /* Gemini-Lake */
2485 { PCI_DEVICE(0x8086, 0x3198),
3e9ad24b 2486 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2487 /* Haswell */
4a7c516b 2488 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2489 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2490 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2491 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2492 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2493 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2494 /* Broadwell */
2495 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2496 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2497 /* 5 Series/3400 */
2498 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2499 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2500 /* Poulsbo */
9477c58e 2501 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2502 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2503 /* Oaktrail */
09904b95 2504 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2505 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2506 /* BayTrail */
2507 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2508 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2509 /* Braswell */
2510 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2511 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2512 /* ICH6 */
8b0bd226 2513 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2514 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2515 /* ICH7 */
8b0bd226 2516 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2517 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2518 /* ESB2 */
8b0bd226 2519 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2520 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2521 /* ICH8 */
8b0bd226 2522 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2523 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2524 /* ICH9 */
8b0bd226 2525 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2526 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2527 /* ICH9 */
8b0bd226 2528 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2529 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2530 /* ICH10 */
8b0bd226 2531 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2532 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2533 /* ICH10 */
8b0bd226 2534 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2535 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2536 /* Generic Intel */
2537 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2538 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2539 .class_mask = 0xffffff,
103884a3 2540 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2541 /* ATI SB 450/600/700/800/900 */
2542 { PCI_DEVICE(0x1002, 0x437b),
2543 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2544 { PCI_DEVICE(0x1002, 0x4383),
2545 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2546 /* AMD Hudson */
2547 { PCI_DEVICE(0x1022, 0x780d),
2548 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
c02f77d3
TI		 2549 /* AMD, X370 & co */
2550 { PCI_DEVICE(0x1022, 0x1457),
2551 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
de768ce4
TI		 2552 /* AMD, X570 & co */
2553 { PCI_DEVICE(0x1022, 0x1487),
2554 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
3deef52c
KHF		 2555 /* AMD Stoney */
2556 { PCI_DEVICE(0x1022, 0x157a),
2557 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2558 AZX_DCAPS_PM_RUNTIME },
9ceace3c
VM		 2559 /* AMD Raven */
2560 { PCI_DEVICE(0x1022, 0x15e3),
d2c63b7d 2561 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
87218e9c 2562 /* ATI HDMI */
fd48331f
MSB		 2563 { PCI_DEVICE(0x1002, 0x0002),
2564 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
650474fb
AD		 2565 { PCI_DEVICE(0x1002, 0x1308),
2566 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2567 { PCI_DEVICE(0x1002, 0x157a),
2568 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
d716fb03
AB		 2569 { PCI_DEVICE(0x1002, 0x15b3),
2570 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2571 { PCI_DEVICE(0x1002, 0x793b),
2572 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2573 { PCI_DEVICE(0x1002, 0x7919),
2574 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2575 { PCI_DEVICE(0x1002, 0x960f),
2576 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2577 { PCI_DEVICE(0x1002, 0x970f),
2578 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2579 { PCI_DEVICE(0x1002, 0x9840),
2580 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2581 { PCI_DEVICE(0x1002, 0xaa00),
2582 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2583 { PCI_DEVICE(0x1002, 0xaa08),
2584 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2585 { PCI_DEVICE(0x1002, 0xaa10),
2586 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2587 { PCI_DEVICE(0x1002, 0xaa18),
2588 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2589 { PCI_DEVICE(0x1002, 0xaa20),
2590 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2591 { PCI_DEVICE(0x1002, 0xaa28),
2592 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2593 { PCI_DEVICE(0x1002, 0xaa30),
2594 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2595 { PCI_DEVICE(0x1002, 0xaa38),
2596 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2597 { PCI_DEVICE(0x1002, 0xaa40),
2598 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2599 { PCI_DEVICE(0x1002, 0xaa48),
2600 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2601 { PCI_DEVICE(0x1002, 0xaa50),
2602 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2603 { PCI_DEVICE(0x1002, 0xaa58),
2604 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2605 { PCI_DEVICE(0x1002, 0xaa60),
2606 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2607 { PCI_DEVICE(0x1002, 0xaa68),
2608 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2609 { PCI_DEVICE(0x1002, 0xaa80),
2610 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2611 { PCI_DEVICE(0x1002, 0xaa88),
2612 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2613 { PCI_DEVICE(0x1002, 0xaa90),
2614 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2615 { PCI_DEVICE(0x1002, 0xaa98),
2616 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2617 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2618 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2619 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2620 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2621 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2622 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2623 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2624 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2625 { PCI_DEVICE(0x1002, 0xaac0),
2626 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2627 { PCI_DEVICE(0x1002, 0xaac8),
2628 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d 2629 { PCI_DEVICE(0x1002, 0xaad8),
73b1422b
AD		 2630 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2631 AZX_DCAPS_PM_RUNTIME },
8eb22214 2632 { PCI_DEVICE(0x1002, 0xaae0),
73b1422b
AD		 2633 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2634 AZX_DCAPS_PM_RUNTIME },
2635 { PCI_DEVICE(0x1002, 0xaae8),
2636 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2637 AZX_DCAPS_PM_RUNTIME },
8eb22214 2638 { PCI_DEVICE(0x1002, 0xaaf0),
73b1422b
AD		 2639 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2640 AZX_DCAPS_PM_RUNTIME },
8d68a872 2641 { PCI_DEVICE(0x1002, 0xaaf8),
73b1422b
AD		 2642 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2643 AZX_DCAPS_PM_RUNTIME },
8d68a872 2644 { PCI_DEVICE(0x1002, 0xab00),
73b1422b
AD		 2645 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2646 AZX_DCAPS_PM_RUNTIME },
8d68a872 2647 { PCI_DEVICE(0x1002, 0xab08),
73b1422b
AD		 2648 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2649 AZX_DCAPS_PM_RUNTIME },
8d68a872 2650 { PCI_DEVICE(0x1002, 0xab10),
73b1422b
AD		 2651 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2652 AZX_DCAPS_PM_RUNTIME },
8d68a872 2653 { PCI_DEVICE(0x1002, 0xab18),
73b1422b
AD		 2654 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2655 AZX_DCAPS_PM_RUNTIME },
8d68a872 2656 { PCI_DEVICE(0x1002, 0xab20),
73b1422b
AD		 2657 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2658 AZX_DCAPS_PM_RUNTIME },
8d68a872 2659 { PCI_DEVICE(0x1002, 0xab38),
73b1422b
AD		 2660 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2661 AZX_DCAPS_PM_RUNTIME },
87218e9c 2662 /* VIA VT8251/VT8237A */
26f05717 2663 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2664 /* VIA GFX VT7122/VX900 */
2665 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2666 /* VIA GFX VT6122/VX11 */
2667 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2668 /* SIS966 */
2669 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2670 /* ULI M5461 */
2671 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2672 /* NVIDIA MCP */
0c2fd1bf
TI		 2673 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2674 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2675 .class_mask = 0xffffff,
9477c58e 2676 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2677 /* Teradici */
9477c58e
TI		 2678 { PCI_DEVICE(0x6549, 0x1200),
2679 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2680 { PCI_DEVICE(0x6549, 0x2200),
2681 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2682 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2683 /* CTHDA chips */
2684 { PCI_DEVICE(0x1102, 0x0010),
2685 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2686 { PCI_DEVICE(0x1102, 0x0012),
2687 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2688#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2689 /* the following entry conflicts with snd-ctxfi driver,
2690 * as ctxfi driver mutates from HD-audio to native mode with
2691 * a special command sequence.
2692 */
4e01f54b
TI		 2693 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2694 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2695 .class_mask = 0xffffff,
9477c58e 2696 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2697 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2698#else
2699 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2700 { PCI_DEVICE(0x1102, 0x0009),
2701 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2702 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2703#endif
c563f473
TI		 2704 /* CM8888 */
2705 { PCI_DEVICE(0x13f6, 0x5011),
2706 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2707 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2708 /* Vortex86MX */
2709 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2710 /* VMware HDAudio */
2711 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2712 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2713 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2714 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2715 .class_mask = 0xffffff,
9477c58e 2716 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2717 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2718 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2719 .class_mask = 0xffffff,
9477c58e 2720 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
b6fcab14
TW		 2721 /* Zhaoxin */
2722 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
1da177e4
LT		 2723 { 0, }
2724};
2725MODULE_DEVICE_TABLE(pci, azx_ids);
2726
2727/* pci_driver definition */
e9f66d9b 2728static struct pci_driver azx_driver = {
3733e424 2729 .name = KBUILD_MODNAME,
1da177e4
LT		 2730 .id_table = azx_ids,
2731 .probe = azx_probe,
e23e7a14 2732 .remove = azx_remove,
b2a0bafa 2733 .shutdown = azx_shutdown,
68cb2b55
TI		 2734 .driver = {
2735 .pm = AZX_PM_OPS,
2736 },
1da177e4
LT		 2737};
2738
e9f66d9b 2739module_pci_driver(azx_driver);
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