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ALSA: hda - Introduce the bitmask for excluding output volume
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4 64#include "hda_codec.h"
99a2008d 65#include "hda_i915.h"
1da177e4
LT		 66
67
5aba4f8e
TI		 68static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
69static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 70static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 71static char *model[SNDRV_CARDS];
1dac6695 72static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 73static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 74static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 75static int probe_only[SNDRV_CARDS];
26a6cb6c 76static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 77static bool single_cmd;
71623855 78static int enable_msi = -1;
4ea6fbc8
TI		 79#ifdef CONFIG_SND_HDA_PATCH_LOADER
80static char *patch[SNDRV_CARDS];
81#endif
2dca0bba 82#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 83static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 84 CONFIG_SND_HDA_INPUT_BEEP_MODE};
85#endif
1da177e4 86
5aba4f8e 87module_param_array(index, int, NULL, 0444);
1da177e4 88MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 89module_param_array(id, charp, NULL, 0444);
1da177e4 90MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 91module_param_array(enable, bool, NULL, 0444);
92MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
93module_param_array(model, charp, NULL, 0444);
1da177e4 94MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 95module_param_array(position_fix, int, NULL, 0444);
4cb36310 96MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 97 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 98module_param_array(bdl_pos_adj, int, NULL, 0644);
99MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 100module_param_array(probe_mask, int, NULL, 0444);
606ad75f 101MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 102module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 103MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 104module_param_array(jackpoll_ms, int, NULL, 0444);
105MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 106module_param(single_cmd, bool, 0444);
d01ce99f
TI		 107MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
108 "(for debugging only).");
ac9ef6cf 109module_param(enable_msi, bint, 0444);
134a11f0 110MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 111#ifdef CONFIG_SND_HDA_PATCH_LOADER
112module_param_array(patch, charp, NULL, 0444);
113MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
114#endif
2dca0bba 115#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 116module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 117MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 118 "(0=off, 1=on) (default=1).");
2dca0bba 119#endif
606ad75f 120
83012a7c 121#ifdef CONFIG_PM
65fcd41d
TI		 122static int param_set_xint(const char *val, const struct kernel_param *kp);
123static struct kernel_param_ops param_ops_xint = {
124 .set = param_set_xint,
125 .get = param_get_int,
126};
127#define param_check_xint param_check_int
128
fee2fba3 129static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 130module_param(power_save, xint, 0644);
fee2fba3
TI		 131MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
132 "(in second, 0 = disable).");
1da177e4 133
dee1b66c
TI		 134/* reset the HD-audio controller in power save mode.
135 * this may give more power-saving, but will take longer time to
136 * wake up.
137 */
8fc24426
TI		 138static bool power_save_controller = 1;
139module_param(power_save_controller, bool, 0644);
dee1b66c 140MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
83012a7c 141#endif /* CONFIG_PM */
dee1b66c 142
7bfe059e
TI		 143static int align_buffer_size = -1;
144module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 145MODULE_PARM_DESC(align_buffer_size,
146 "Force buffer and period sizes to be multiple of 128 bytes.");
147
27fe48d9
TI		 148#ifdef CONFIG_X86
149static bool hda_snoop = true;
150module_param_named(snoop, hda_snoop, bool, 0444);
151MODULE_PARM_DESC(snoop, "Enable/disable snooping");
152#define azx_snoop(chip) (chip)->snoop
153#else
154#define hda_snoop true
155#define azx_snoop(chip) true
156#endif
157
158
1da177e4
LT		 159MODULE_LICENSE("GPL");
160MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
161 "{Intel, ICH6M},"
2f1b3818 162 "{Intel, ICH7},"
f5d40b30 163 "{Intel, ESB2},"
d2981393 164 "{Intel, ICH8},"
f9cc8a8b 165 "{Intel, ICH9},"
c34f5a04 166 "{Intel, ICH10},"
b29c2360 167 "{Intel, PCH},"
d2f2fcd2 168 "{Intel, CPT},"
d2edeb7c 169 "{Intel, PPT},"
8bc039a1 170 "{Intel, LPT},"
144dad99 171 "{Intel, LPT_LP},"
4eeca499 172 "{Intel, WPT_LP},"
e926f2c8 173 "{Intel, HPT},"
cea310e8 174 "{Intel, PBG},"
4979bca9 175 "{Intel, SCH},"
fc20a562 176 "{ATI, SB450},"
89be83f8 177 "{ATI, SB600},"
778b6e1b 178 "{ATI, RS600},"
5b15c95f 179 "{ATI, RS690},"
e6db1119
WL		 180 "{ATI, RS780},"
181 "{ATI, R600},"
2797f724
HRK		 182 "{ATI, RV630},"
183 "{ATI, RV610},"
27da1834
WL		 184 "{ATI, RV670},"
185 "{ATI, RV635},"
186 "{ATI, RV620},"
187 "{ATI, RV770},"
fc20a562 188 "{VIA, VT8251},"
47672310 189 "{VIA, VT8237A},"
07e4ca50
TI		 190 "{SiS, SIS966},"
191 "{ULI, M5461}}");
1da177e4
LT		 192MODULE_DESCRIPTION("Intel HDA driver");
193
4abc1cc2
TI		 194#ifdef CONFIG_SND_VERBOSE_PRINTK
195#define SFX /* nop */
196#else
445a51b3 197#define SFX "hda-intel "
4abc1cc2 198#endif
cb53c626 199
a82d51ed
TI		 200#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
201#ifdef CONFIG_SND_HDA_CODEC_HDMI
202#define SUPPORT_VGA_SWITCHEROO
203#endif
204#endif
205
206
1da177e4
LT		 207/*
208 * registers
209 */
210#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 211#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
212#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
213#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
214#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
215#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 216#define ICH6_REG_VMIN 0x02
217#define ICH6_REG_VMAJ 0x03
218#define ICH6_REG_OUTPAY 0x04
219#define ICH6_REG_INPAY 0x06
220#define ICH6_REG_GCTL 0x08
8a933ece 221#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 222#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
223#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 224#define ICH6_REG_WAKEEN 0x0c
225#define ICH6_REG_STATESTS 0x0e
226#define ICH6_REG_GSTS 0x10
b21fadb9 227#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 228#define ICH6_REG_INTCTL 0x20
229#define ICH6_REG_INTSTS 0x24
e5463720 230#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 231#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
232#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 233#define ICH6_REG_CORBLBASE 0x40
234#define ICH6_REG_CORBUBASE 0x44
235#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 236#define ICH6_REG_CORBRP 0x4a
237#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 238#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 239#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
240#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 241#define ICH6_REG_CORBSTS 0x4d
b21fadb9 242#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 243#define ICH6_REG_CORBSIZE 0x4e
244
245#define ICH6_REG_RIRBLBASE 0x50
246#define ICH6_REG_RIRBUBASE 0x54
247#define ICH6_REG_RIRBWP 0x58
b21fadb9 248#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 249#define ICH6_REG_RINTCNT 0x5a
250#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 251#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
252#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
253#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 254#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 255#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
256#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 257#define ICH6_REG_RIRBSIZE 0x5e
258
259#define ICH6_REG_IC 0x60
260#define ICH6_REG_IR 0x64
261#define ICH6_REG_IRS 0x68
262#define ICH6_IRS_VALID (1<<1)
263#define ICH6_IRS_BUSY (1<<0)
264
265#define ICH6_REG_DPLBASE 0x70
266#define ICH6_REG_DPUBASE 0x74
267#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
268
269/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
270enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
271
272/* stream register offsets from stream base */
273#define ICH6_REG_SD_CTL 0x00
274#define ICH6_REG_SD_STS 0x03
275#define ICH6_REG_SD_LPIB 0x04
276#define ICH6_REG_SD_CBL 0x08
277#define ICH6_REG_SD_LVI 0x0c
278#define ICH6_REG_SD_FIFOW 0x0e
279#define ICH6_REG_SD_FIFOSIZE 0x10
280#define ICH6_REG_SD_FORMAT 0x12
281#define ICH6_REG_SD_BDLPL 0x18
282#define ICH6_REG_SD_BDLPU 0x1c
283
284/* PCI space */
285#define ICH6_PCIREG_TCSEL 0x44
286
287/*
288 * other constants
289 */
290
291/* max number of SDs */
07e4ca50 292/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 293#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 294#define ICH6_NUM_PLAYBACK 4
295
296/* ULI has 6 playback and 5 capture */
07e4ca50 297#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 298#define ULI_NUM_PLAYBACK 6
299
778b6e1b 300/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 301#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 302#define ATIHDMI_NUM_PLAYBACK 1
303
f269002e
KY		 304/* TERA has 4 playback and 3 capture */
305#define TERA_NUM_CAPTURE 3
306#define TERA_NUM_PLAYBACK 4
307
07e4ca50
TI		 308/* this number is statically defined for simplicity */
309#define MAX_AZX_DEV 16
310
1da177e4 311/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 312#define BDL_SIZE 4096
313#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
314#define AZX_MAX_FRAG 32
1da177e4
LT		 315/* max buffer size - no h/w limit, you can increase as you like */
316#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 317
318/* RIRB int mask: overrun[2], response[0] */
319#define RIRB_INT_RESPONSE 0x01
320#define RIRB_INT_OVERRUN 0x04
321#define RIRB_INT_MASK 0x05
322
2f5983f2 323/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 324#define AZX_MAX_CODECS 8
325#define AZX_DEFAULT_CODECS 4
deadff16 326#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 327
328/* SD_CTL bits */
329#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
330#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 331#define SD_CTL_STRIPE (3 << 16) /* stripe control */
332#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
333#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 334#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
335#define SD_CTL_STREAM_TAG_SHIFT 20
336
337/* SD_CTL and SD_STS */
338#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
339#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
340#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 341#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
342 SD_INT_COMPLETE)
1da177e4
LT		 343
344/* SD_STS */
345#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
346
347/* INTCTL and INTSTS */
d01ce99f
TI		 348#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
349#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
350#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 351
1da177e4
LT		 352/* below are so far hardcoded - should read registers in future */
353#define ICH6_MAX_CORB_ENTRIES 256
354#define ICH6_MAX_RIRB_ENTRIES 256
355
c74db86b
TI		 356/* position fix mode */
357enum {
0be3b5d3 358 POS_FIX_AUTO,
d2e1c973 359 POS_FIX_LPIB,
0be3b5d3 360 POS_FIX_POSBUF,
4cb36310 361 POS_FIX_VIACOMBO,
a6f2fd55 362 POS_FIX_COMBO,
c74db86b 363};
1da177e4 364
f5d40b30 365/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 366#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
367#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
368
da3fca21
V		 369/* Defines for Nvidia HDA support */
370#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
371#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 372#define NVIDIA_HDA_ISTRM_COH 0x4d
373#define NVIDIA_HDA_OSTRM_COH 0x4c
374#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 375
90a5ad52
TI		 376/* Defines for Intel SCH HDA snoop control */
377#define INTEL_SCH_HDA_DEVC 0x78
378#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
379
0e153474
JC		 380/* Define IN stream 0 FIFO size offset in VIA controller */
381#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
382/* Define VIA HD Audio Device ID*/
383#define VIA_HDAC_DEVICE_ID 0x3288
384
c4da29ca
YL		 385/* HD Audio class code */
386#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 387
1da177e4
LT		 388/*
389 */
390
a98f90fd 391struct azx_dev {
4ce107b9 392 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 393 u32 *posbuf; /* position buffer pointer */
1da177e4 394
d01ce99f 395 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 396 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 397 unsigned int frags; /* number for period in the play buffer */
398 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 399 unsigned long start_wallclk; /* start + minimum wallclk */
400 unsigned long period_wallclk; /* wallclk for period */
1da177e4 401
d01ce99f 402 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 403
d01ce99f 404 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 405
406 /* pcm support */
d01ce99f
TI		 407 struct snd_pcm_substream *substream; /* assigned substream,
408 * set in PCM open
409 */
410 unsigned int format_val; /* format value to be set in the
411 * controller and the codec
412 */
1da177e4
LT		 413 unsigned char stream_tag; /* assigned stream */
414 unsigned char index; /* stream index */
d5cf9911 415 int assigned_key; /* last device# key assigned to */
1da177e4 416
927fc866
PM		 417 unsigned int opened :1;
418 unsigned int running :1;
675f25d4 419 unsigned int irq_pending :1;
eb49faa6
TI		 420 unsigned int prepared:1;
421 unsigned int locked:1;
0e153474
JC		 422 /*
423 * For VIA:
424 * A flag to ensure DMA position is 0
425 * when link position is not greater than FIFO size
426 */
427 unsigned int insufficient :1;
27fe48d9 428 unsigned int wc_marked:1;
915bf29e 429 unsigned int no_period_wakeup:1;
5d890f59
PLB		 430
431 struct timecounter azx_tc;
432 struct cyclecounter azx_cc;
eb49faa6
TI		 433
434#ifdef CONFIG_SND_HDA_DSP_LOADER
435 struct mutex dsp_mutex;
436#endif
1da177e4
LT		 437};
438
eb49faa6
TI		 439/* DSP lock helpers */
440#ifdef CONFIG_SND_HDA_DSP_LOADER
441#define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
442#define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
443#define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
444#define dsp_is_locked(dev) ((dev)->locked)
445#else
446#define dsp_lock_init(dev) do {} while (0)
447#define dsp_lock(dev) do {} while (0)
448#define dsp_unlock(dev) do {} while (0)
449#define dsp_is_locked(dev) 0
450#endif
451
1da177e4 452/* CORB/RIRB */
a98f90fd 453struct azx_rb {
1da177e4
LT		 454 u32 *buf; /* CORB/RIRB buffer
455 * Each CORB entry is 4byte, RIRB is 8byte
456 */
457 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
458 /* for RIRB */
459 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 460 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
461 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 462};
463
01b65bfb
TI		 464struct azx_pcm {
465 struct azx *chip;
466 struct snd_pcm *pcm;
467 struct hda_codec *codec;
468 struct hda_pcm_stream *hinfo[2];
469 struct list_head list;
470};
471
a98f90fd
TI		 472struct azx {
473 struct snd_card *card;
1da177e4 474 struct pci_dev *pci;
555e219f 475 int dev_index;
1da177e4 476
07e4ca50
TI		 477 /* chip type specific */
478 int driver_type;
9477c58e 479 unsigned int driver_caps;
07e4ca50
TI		 480 int playback_streams;
481 int playback_index_offset;
482 int capture_streams;
483 int capture_index_offset;
484 int num_streams;
485
1da177e4
LT		 486 /* pci resources */
487 unsigned long addr;
488 void __iomem *remap_addr;
489 int irq;
490
491 /* locks */
492 spinlock_t reg_lock;
62932df8 493 struct mutex open_mutex;
f4c482a4 494 struct completion probe_wait;
1da177e4 495
07e4ca50 496 /* streams (x num_streams) */
a98f90fd 497 struct azx_dev *azx_dev;
1da177e4
LT		 498
499 /* PCM */
01b65bfb 500 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 501
502 /* HD codec */
503 unsigned short codec_mask;
f1eaaeec 504 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 505 struct hda_bus *bus;
2dca0bba 506 unsigned int beep_mode;
1da177e4
LT		 507
508 /* CORB/RIRB */
a98f90fd
TI		 509 struct azx_rb corb;
510 struct azx_rb rirb;
1da177e4 511
4ce107b9 512 /* CORB/RIRB and position buffers */
1da177e4
LT		 513 struct snd_dma_buffer rb;
514 struct snd_dma_buffer posbuf;
c74db86b 515
4918cdab
TI		 516#ifdef CONFIG_SND_HDA_PATCH_LOADER
517 const struct firmware *fw;
518#endif
519
c74db86b 520 /* flags */
beaffc39 521 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 522 int poll_count;
cb53c626 523 unsigned int running :1;
927fc866
PM		 524 unsigned int initialized :1;
525 unsigned int single_cmd :1;
526 unsigned int polling_mode :1;
68e7fffc 527 unsigned int msi :1;
a6a950a8 528 unsigned int irq_pending_warned :1;
6ce4a3bc 529 unsigned int probing :1; /* codec probing phase */
27fe48d9 530 unsigned int snoop:1;
52409aa6 531 unsigned int align_buffer_size:1;
a82d51ed
TI		 532 unsigned int region_requested:1;
533
534 /* VGA-switcheroo setup */
535 unsigned int use_vga_switcheroo:1;
128960a9 536 unsigned int vga_switcheroo_registered:1;
a82d51ed
TI		 537 unsigned int init_failed:1; /* delayed init failed */
538 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 539
540 /* for debugging */
feb27340 541 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 542
543 /* for pending irqs */
544 struct work_struct irq_pending_work;
0cbf0098 545
99a2008d
WX		 546#ifdef CONFIG_SND_HDA_I915
547 struct work_struct probe_work;
548#endif
549
0cbf0098
TI		 550 /* reboot notifier (for mysterious hangup problem at power-down) */
551 struct notifier_block reboot_notifier;
65fcd41d
TI		 552
553 /* card list (for power_save trigger) */
554 struct list_head list;
eb49faa6
TI		 555
556#ifdef CONFIG_SND_HDA_DSP_LOADER
557 struct azx_dev saved_azx_dev;
558#endif
246efa4a
DA		 559
560 /* secondary power domain for hdmi audio under vga device */
561 struct dev_pm_domain hdmi_pm_domain;
1da177e4
LT		 562};
563
1a8506d4
TI		 564#define CREATE_TRACE_POINTS
565#include "hda_intel_trace.h"
566
07e4ca50
TI		 567/* driver types */
568enum {
569 AZX_DRIVER_ICH,
32679f95 570 AZX_DRIVER_PCH,
4979bca9 571 AZX_DRIVER_SCH,
07e4ca50 572 AZX_DRIVER_ATI,
778b6e1b 573 AZX_DRIVER_ATIHDMI,
1815b34a 574 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 575 AZX_DRIVER_VIA,
576 AZX_DRIVER_SIS,
577 AZX_DRIVER_ULI,
da3fca21 578 AZX_DRIVER_NVIDIA,
f269002e 579 AZX_DRIVER_TERA,
14d34f16 580 AZX_DRIVER_CTX,
5ae763b1 581 AZX_DRIVER_CTHDA,
c4da29ca 582 AZX_DRIVER_GENERIC,
2f5983f2 583 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 584};
585
9477c58e
TI		 586/* driver quirks (capabilities) */
587/* bits 0-7 are used for indicating driver type */
588#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
589#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
590#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
591#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
592#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
593#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
594#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
595#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
596#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
597#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
598#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
599#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 600#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 601#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 602#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 603#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
90accc58 604#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
2ea3c6a2 605#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
99a2008d 606#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 power well support */
2ea3c6a2
TI		 607
608/* quirks for Intel PCH */
d7dab4db 609#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 610 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 611 AZX_DCAPS_COUNT_LPIB_DELAY)
612
613#define AZX_DCAPS_INTEL_PCH \
614 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e
TI		 615
616/* quirks for ATI SB / AMD Hudson */
617#define AZX_DCAPS_PRESET_ATI_SB \
618 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
619 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
620
621/* quirks for ATI/AMD HDMI */
622#define AZX_DCAPS_PRESET_ATI_HDMI \
623 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
624
625/* quirks for Nvidia */
626#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 627 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
49d9e77e 628 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
9477c58e 629
5ae763b1
TI		 630#define AZX_DCAPS_PRESET_CTHDA \
631 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
632
a82d51ed
TI		 633/*
634 * VGA-switcher support
635 */
636#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 637#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
638#else
639#define use_vga_switcheroo(chip) 0
640#endif
641
48c8b0eb 642static char *driver_short_names[] = {
07e4ca50 643 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 644 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 645 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 646 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 647 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 648 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 649 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
650 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 651 [AZX_DRIVER_ULI] = "HDA ULI M5461",
652 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 653 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 654 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 655 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 656 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 657};
658
1da177e4
LT		 659/*
660 * macros for easy use
661 */
662#define azx_writel(chip,reg,value) \
663 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
664#define azx_readl(chip,reg) \
665 readl((chip)->remap_addr + ICH6_REG_##reg)
666#define azx_writew(chip,reg,value) \
667 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
668#define azx_readw(chip,reg) \
669 readw((chip)->remap_addr + ICH6_REG_##reg)
670#define azx_writeb(chip,reg,value) \
671 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
672#define azx_readb(chip,reg) \
673 readb((chip)->remap_addr + ICH6_REG_##reg)
674
675#define azx_sd_writel(dev,reg,value) \
676 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
677#define azx_sd_readl(dev,reg) \
678 readl((dev)->sd_addr + ICH6_REG_##reg)
679#define azx_sd_writew(dev,reg,value) \
680 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
681#define azx_sd_readw(dev,reg) \
682 readw((dev)->sd_addr + ICH6_REG_##reg)
683#define azx_sd_writeb(dev,reg,value) \
684 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
685#define azx_sd_readb(dev,reg) \
686 readb((dev)->sd_addr + ICH6_REG_##reg)
687
688/* for pcm support */
a98f90fd 689#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 690
27fe48d9 691#ifdef CONFIG_X86
9ddf1aeb 692static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 693{
9ddf1aeb
TI		 694 int pages;
695
27fe48d9
TI		 696 if (azx_snoop(chip))
697 return;
9ddf1aeb
TI		 698 if (!dmab || !dmab->area || !dmab->bytes)
699 return;
700
701#ifdef CONFIG_SND_DMA_SGBUF
702 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
703 struct snd_sg_buf *sgbuf = dmab->private_data;
27fe48d9 704 if (on)
9ddf1aeb 705 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 706 else
9ddf1aeb
TI		 707 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
708 return;
27fe48d9 709 }
9ddf1aeb
TI		 710#endif
711
712 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
713 if (on)
714 set_memory_wc((unsigned long)dmab->area, pages);
715 else
716 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 717}
718
719static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
720 bool on)
721{
9ddf1aeb 722 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 723}
724static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 725 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 726{
727 if (azx_dev->wc_marked != on) {
9ddf1aeb 728 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 729 azx_dev->wc_marked = on;
730 }
731}
732#else
733/* NOP for other archs */
734static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
735 bool on)
736{
737}
738static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 739 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 740{
741}
742#endif
743
68e7fffc 744static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 745static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 746/*
747 * Interface for HD codec
748 */
749
1da177e4
LT		 750/*
751 * CORB / RIRB interface
752 */
a98f90fd 753static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 754{
755 int err;
756
757 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 758 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
759 snd_dma_pci_data(chip->pci),
1da177e4
LT		 760 PAGE_SIZE, &chip->rb);
761 if (err < 0) {
445a51b3 762 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
1da177e4
LT		 763 return err;
764 }
27fe48d9 765 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 766 return 0;
767}
768
a98f90fd 769static void azx_init_cmd_io(struct azx *chip)
1da177e4 770{
cdb1fbf2 771 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 772 /* CORB set up */
773 chip->corb.addr = chip->rb.addr;
774 chip->corb.buf = (u32 *)chip->rb.area;
775 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 776 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 777
07e4ca50
TI		 778 /* set the corb size to 256 entries (ULI requires explicitly) */
779 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 780 /* set the corb write pointer to 0 */
781 azx_writew(chip, CORBWP, 0);
782 /* reset the corb hw read pointer */
b21fadb9 783 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 784 /* enable corb dma */
b21fadb9 785 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 786
787 /* RIRB set up */
788 chip->rirb.addr = chip->rb.addr + 2048;
789 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 790 chip->rirb.wp = chip->rirb.rp = 0;
791 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 792 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 793 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 794
07e4ca50
TI		 795 /* set the rirb size to 256 entries (ULI requires explicitly) */
796 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 797 /* reset the rirb hw write pointer */
b21fadb9 798 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 799 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 800 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 801 azx_writew(chip, RINTCNT, 0xc0);
802 else
803 azx_writew(chip, RINTCNT, 1);
1da177e4 804 /* enable rirb dma and response irq */
1da177e4 805 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 806 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 807}
808
a98f90fd 809static void azx_free_cmd_io(struct azx *chip)
1da177e4 810{
cdb1fbf2 811 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 812 /* disable ringbuffer DMAs */
813 azx_writeb(chip, RIRBCTL, 0);
814 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 815 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 816}
817
deadff16
WF		 818static unsigned int azx_command_addr(u32 cmd)
819{
820 unsigned int addr = cmd >> 28;
821
822 if (addr >= AZX_MAX_CODECS) {
823 snd_BUG();
824 addr = 0;
825 }
826
827 return addr;
828}
829
830static unsigned int azx_response_addr(u32 res)
831{
832 unsigned int addr = res & 0xf;
833
834 if (addr >= AZX_MAX_CODECS) {
835 snd_BUG();
836 addr = 0;
837 }
838
839 return addr;
1da177e4
LT		 840}
841
842/* send a command */
33fa35ed 843static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 844{
33fa35ed 845 struct azx *chip = bus->private_data;
deadff16 846 unsigned int addr = azx_command_addr(val);
3bcce5c0 847 unsigned int wp, rp;
1da177e4 848
c32649fe
WF		 849 spin_lock_irq(&chip->reg_lock);
850
1da177e4 851 /* add command to corb */
cc5ede3e
TI		 852 wp = azx_readw(chip, CORBWP);
853 if (wp == 0xffff) {
854 /* something wrong, controller likely turned to D3 */
855 spin_unlock_irq(&chip->reg_lock);
3bcce5c0 856 return -EIO;
cc5ede3e 857 }
1da177e4
LT		 858 wp++;
859 wp %= ICH6_MAX_CORB_ENTRIES;
860
3bcce5c0
TI		 861 rp = azx_readw(chip, CORBRP);
862 if (wp == rp) {
863 /* oops, it's full */
864 spin_unlock_irq(&chip->reg_lock);
865 return -EAGAIN;
866 }
867
deadff16 868 chip->rirb.cmds[addr]++;
1da177e4
LT		 869 chip->corb.buf[wp] = cpu_to_le32(val);
870 azx_writel(chip, CORBWP, wp);
c32649fe 871
1da177e4
LT		 872 spin_unlock_irq(&chip->reg_lock);
873
874 return 0;
875}
876
877#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
878
879/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 880static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 881{
882 unsigned int rp, wp;
deadff16 883 unsigned int addr;
1da177e4
LT		 884 u32 res, res_ex;
885
cc5ede3e
TI		 886 wp = azx_readw(chip, RIRBWP);
887 if (wp == 0xffff) {
888 /* something wrong, controller likely turned to D3 */
889 return;
890 }
891
1da177e4
LT		 892 if (wp == chip->rirb.wp)
893 return;
894 chip->rirb.wp = wp;
deadff16 895
1da177e4
LT		 896 while (chip->rirb.rp != wp) {
897 chip->rirb.rp++;
898 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
899
900 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
901 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
902 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 903 addr = azx_response_addr(res_ex);
1da177e4
LT		 904 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
905 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 906 else if (chip->rirb.cmds[addr]) {
907 chip->rirb.res[addr] = res;
2add9b92 908 smp_wmb();
deadff16 909 chip->rirb.cmds[addr]--;
e310bb06 910 } else
9e3d352b 911 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
e310bb06 912 "last cmd=%#08x\n",
9e3d352b 913 pci_name(chip->pci),
e310bb06
WF		 914 res, res_ex,
915 chip->last_cmd[addr]);
1da177e4
LT		 916 }
917}
918
919/* receive a response */
deadff16
WF		 920static unsigned int azx_rirb_get_response(struct hda_bus *bus,
921 unsigned int addr)
1da177e4 922{
33fa35ed 923 struct azx *chip = bus->private_data;
5c79b1f8 924 unsigned long timeout;
32cf4023 925 unsigned long loopcounter;
1eb6dc7d 926 int do_poll = 0;
1da177e4 927
5c79b1f8
TI		 928 again:
929 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 930
931 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 932 if (chip->polling_mode || do_poll) {
e96224ae
TI		 933 spin_lock_irq(&chip->reg_lock);
934 azx_update_rirb(chip);
935 spin_unlock_irq(&chip->reg_lock);
936 }
deadff16 937 if (!chip->rirb.cmds[addr]) {
2add9b92 938 smp_rmb();
b613291f 939 bus->rirb_error = 0;
1eb6dc7d
ML		 940
941 if (!do_poll)
942 chip->poll_count = 0;
deadff16 943 return chip->rirb.res[addr]; /* the last value */
2add9b92 944 }
28a0d9df
TI		 945 if (time_after(jiffies, timeout))
946 break;
32cf4023 947 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 948 msleep(2); /* temporary workaround */
949 else {
950 udelay(10);
951 cond_resched();
952 }
28a0d9df 953 }
5c79b1f8 954
63e51fd7
TI		 955 if (!bus->no_response_fallback)
956 return -1;
957
1eb6dc7d 958 if (!chip->polling_mode && chip->poll_count < 2) {
445a51b3 959 snd_printdd(SFX "%s: azx_get_response timeout, "
1eb6dc7d 960 "polling the codec once: last cmd=0x%08x\n",
445a51b3 961 pci_name(chip->pci), chip->last_cmd[addr]);
1eb6dc7d
ML		 962 do_poll = 1;
963 chip->poll_count++;
964 goto again;
965 }
966
967
23c4a881 968 if (!chip->polling_mode) {
445a51b3 969 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
23c4a881 970 "switching to polling mode: last cmd=0x%08x\n",
445a51b3 971 pci_name(chip->pci), chip->last_cmd[addr]);
23c4a881
TI		 972 chip->polling_mode = 1;
973 goto again;
974 }
975
68e7fffc 976 if (chip->msi) {
445a51b3 977 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
feb27340 978 "disabling MSI: last cmd=0x%08x\n",
445a51b3 979 pci_name(chip->pci), chip->last_cmd[addr]);
68e7fffc
TI		 980 free_irq(chip->irq, chip);
981 chip->irq = -1;
982 pci_disable_msi(chip->pci);
983 chip->msi = 0;
b613291f
TI		 984 if (azx_acquire_irq(chip, 1) < 0) {
985 bus->rirb_error = 1;
68e7fffc 986 return -1;
b613291f 987 }
68e7fffc
TI		 988 goto again;
989 }
990
6ce4a3bc
TI		 991 if (chip->probing) {
992 /* If this critical timeout happens during the codec probing
993 * phase, this is likely an access to a non-existing codec
994 * slot. Better to return an error and reset the system.
995 */
996 return -1;
997 }
998
8dd78330
TI		 999 /* a fatal communication error; need either to reset or to fallback
1000 * to the single_cmd mode
1001 */
b613291f 1002 bus->rirb_error = 1;
b20f3b83 1003 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 1004 bus->response_reset = 1;
1005 return -1; /* give a chance to retry */
1006 }
1007
1008 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
1009 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 1010 chip->last_cmd[addr]);
8dd78330
TI		 1011 chip->single_cmd = 1;
1012 bus->response_reset = 0;
1a696978 1013 /* release CORB/RIRB */
4fcd3920 1014 azx_free_cmd_io(chip);
1a696978
TI		 1015 /* disable unsolicited responses */
1016 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 1017 return -1;
1da177e4
LT		 1018}
1019
1da177e4
LT		 1020/*
1021 * Use the single immediate command instead of CORB/RIRB for simplicity
1022 *
1023 * Note: according to Intel, this is not preferred use. The command was
1024 * intended for the BIOS only, and may get confused with unsolicited
1025 * responses. So, we shouldn't use it for normal operation from the
1026 * driver.
1027 * I left the codes, however, for debugging/testing purposes.
1028 */
1029
b05a7d4f 1030/* receive a response */
deadff16 1031static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 1032{
1033 int timeout = 50;
1034
1035 while (timeout--) {
1036 /* check IRV busy bit */
1037 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1038 /* reuse rirb.res as the response return value */
deadff16 1039 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 1040 return 0;
1041 }
1042 udelay(1);
1043 }
1044 if (printk_ratelimit())
445a51b3
DB		 1045 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1046 pci_name(chip->pci), azx_readw(chip, IRS));
deadff16 1047 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 1048 return -EIO;
1049}
1050
1da177e4 1051/* send a command */
33fa35ed 1052static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 1053{
33fa35ed 1054 struct azx *chip = bus->private_data;
deadff16 1055 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 1056 int timeout = 50;
1057
8dd78330 1058 bus->rirb_error = 0;
1da177e4
LT		 1059 while (timeout--) {
1060 /* check ICB busy bit */
d01ce99f 1061 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 1062 /* Clear IRV valid bit */
d01ce99f
TI		 1063 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1064 ICH6_IRS_VALID);
1da177e4 1065 azx_writel(chip, IC, val);
d01ce99f
TI		 1066 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1067 ICH6_IRS_BUSY);
deadff16 1068 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 1069 }
1070 udelay(1);
1071 }
1cfd52bc 1072 if (printk_ratelimit())
445a51b3
DB		 1073 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1074 pci_name(chip->pci), azx_readw(chip, IRS), val);
1da177e4
LT		 1075 return -EIO;
1076}
1077
1078/* receive a response */
deadff16
WF		 1079static unsigned int azx_single_get_response(struct hda_bus *bus,
1080 unsigned int addr)
1da177e4 1081{
33fa35ed 1082 struct azx *chip = bus->private_data;
deadff16 1083 return chip->rirb.res[addr];
1da177e4
LT		 1084}
1085
111d3af5
TI		 1086/*
1087 * The below are the main callbacks from hda_codec.
1088 *
1089 * They are just the skeleton to call sub-callbacks according to the
1090 * current setting of chip->single_cmd.
1091 */
1092
1093/* send a command */
33fa35ed 1094static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 1095{
33fa35ed 1096 struct azx *chip = bus->private_data;
43bbb6cc 1097
a82d51ed
TI		 1098 if (chip->disabled)
1099 return 0;
feb27340 1100 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 1101 if (chip->single_cmd)
33fa35ed 1102 return azx_single_send_cmd(bus, val);
111d3af5 1103 else
33fa35ed 1104 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 1105}
1106
1107/* get a response */
deadff16
WF		 1108static unsigned int azx_get_response(struct hda_bus *bus,
1109 unsigned int addr)
111d3af5 1110{
33fa35ed 1111 struct azx *chip = bus->private_data;
a82d51ed
TI		 1112 if (chip->disabled)
1113 return 0;
111d3af5 1114 if (chip->single_cmd)
deadff16 1115 return azx_single_get_response(bus, addr);
111d3af5 1116 else
deadff16 1117 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1118}
1119
83012a7c 1120#ifdef CONFIG_PM
68467f51 1121static void azx_power_notify(struct hda_bus *bus, bool power_up);
cb53c626 1122#endif
111d3af5 1123
1d1a4564
TI		 1124#ifdef CONFIG_SND_HDA_DSP_LOADER
1125static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1126 unsigned int byte_size,
1127 struct snd_dma_buffer *bufp);
1128static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1129static void azx_load_dsp_cleanup(struct hda_bus *bus,
1130 struct snd_dma_buffer *dmab);
1131#endif
1132
3af3f356 1133/* enter link reset */
7295b264 1134static void azx_enter_link_reset(struct azx *chip)
3af3f356
ML		 1135{
1136 unsigned long timeout;
1137
1138 /* reset controller */
1139 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1140
1141 timeout = jiffies + msecs_to_jiffies(100);
1142 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
1143 time_before(jiffies, timeout))
1144 usleep_range(500, 1000);
1145}
1146
7295b264
ML		 1147/* exit link reset */
1148static void azx_exit_link_reset(struct azx *chip)
1da177e4 1149{
fa348da5 1150 unsigned long timeout;
1da177e4 1151
7295b264
ML		 1152 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1153
1154 timeout = jiffies + msecs_to_jiffies(100);
1155 while (!azx_readb(chip, GCTL) &&
1156 time_before(jiffies, timeout))
1157 usleep_range(500, 1000);
1158}
1159
1160/* reset codec link */
1161static int azx_reset(struct azx *chip, int full_reset)
1162{
cd508fe5
JK		 1163 if (!full_reset)
1164 goto __skip;
1165
e8a7f136 1166 /* clear STATESTS */
da7db6ad 1167 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
e8a7f136 1168
1da177e4 1169 /* reset controller */
7295b264 1170 azx_enter_link_reset(chip);
1da177e4
LT		 1171
1172 /* delay for >= 100us for codec PLL to settle per spec
1173 * Rev 0.9 section 5.5.1
1174 */
fa348da5 1175 usleep_range(500, 1000);
1da177e4
LT		 1176
1177 /* Bring controller out of reset */
7295b264 1178 azx_exit_link_reset(chip);
1da177e4 1179
927fc866 1180 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
fa348da5 1181 usleep_range(1000, 1200);
1da177e4 1182
cd508fe5 1183 __skip:
1da177e4 1184 /* check to see if controller is ready */
927fc866 1185 if (!azx_readb(chip, GCTL)) {
445a51b3 1186 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1da177e4
LT		 1187 return -EBUSY;
1188 }
1189
41e2fce4 1190 /* Accept unsolicited responses */
1a696978
TI		 1191 if (!chip->single_cmd)
1192 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1193 ICH6_GCTL_UNSOL);
41e2fce4 1194
1da177e4 1195 /* detect codecs */
927fc866 1196 if (!chip->codec_mask) {
1da177e4 1197 chip->codec_mask = azx_readw(chip, STATESTS);
445a51b3 1198 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1da177e4
LT		 1199 }
1200
1201 return 0;
1202}
1203
1204
1205/*
1206 * Lowlevel interface
1207 */
1208
1209/* enable interrupts */
a98f90fd 1210static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1211{
1212 /* enable controller CIE and GIE */
1213 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1214 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1215}
1216
1217/* disable interrupts */
a98f90fd 1218static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1219{
1220 int i;
1221
1222 /* disable interrupts in stream descriptor */
07e4ca50 1223 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1224 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1225 azx_sd_writeb(azx_dev, SD_CTL,
1226 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1227 }
1228
1229 /* disable SIE for all streams */
1230 azx_writeb(chip, INTCTL, 0);
1231
1232 /* disable controller CIE and GIE */
1233 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1234 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1235}
1236
1237/* clear interrupts */
a98f90fd 1238static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1239{
1240 int i;
1241
1242 /* clear stream status */
07e4ca50 1243 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1244 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1245 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1246 }
1247
1248 /* clear STATESTS */
da7db6ad 1249 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1da177e4
LT		 1250
1251 /* clear rirb status */
1252 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1253
1254 /* clear int status */
1255 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1256}
1257
1258/* start a stream */
a98f90fd 1259static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1260{
0e153474
JC		 1261 /*
1262 * Before stream start, initialize parameter
1263 */
1264 azx_dev->insufficient = 1;
1265
1da177e4 1266 /* enable SIE */
ccc5df05
WN		 1267 azx_writel(chip, INTCTL,
1268 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1269 /* set DMA start and interrupt mask */
1270 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1271 SD_CTL_DMA_START | SD_INT_MASK);
1272}
1273
1dddab40
TI		 1274/* stop DMA */
1275static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1276{
1da177e4
LT		 1277 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1278 ~(SD_CTL_DMA_START | SD_INT_MASK));
1279 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1280}
1281
1282/* stop a stream */
1283static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1284{
1285 azx_stream_clear(chip, azx_dev);
1da177e4 1286 /* disable SIE */
ccc5df05
WN		 1287 azx_writel(chip, INTCTL,
1288 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1289}
1290
1291
1292/*
cb53c626 1293 * reset and start the controller registers
1da177e4 1294 */
cd508fe5 1295static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1296{
cb53c626
TI		 1297 if (chip->initialized)
1298 return;
1da177e4
LT		 1299
1300 /* reset controller */
cd508fe5 1301 azx_reset(chip, full_reset);
1da177e4
LT		 1302
1303 /* initialize interrupts */
1304 azx_int_clear(chip);
1305 azx_int_enable(chip);
1306
1307 /* initialize the codec command I/O */
1a696978
TI		 1308 if (!chip->single_cmd)
1309 azx_init_cmd_io(chip);
1da177e4 1310
0be3b5d3
TI		 1311 /* program the position buffer */
1312 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1313 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1314
cb53c626
TI		 1315 chip->initialized = 1;
1316}
1317
1318/*
1319 * initialize the PCI registers
1320 */
1321/* update bits in a PCI register byte */
1322static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1323 unsigned char mask, unsigned char val)
1324{
1325 unsigned char data;
1326
1327 pci_read_config_byte(pci, reg, &data);
1328 data &= ~mask;
1329 data |= (val & mask);
1330 pci_write_config_byte(pci, reg, data);
1331}
1332
1333static void azx_init_pci(struct azx *chip)
1334{
1335 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1336 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1337 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1338 * codecs.
1339 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1340 */
46f2cc80 1341 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
445a51b3 1342 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
a09e89f6 1343 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1344 }
cb53c626 1345
9477c58e
TI		 1346 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1347 * we need to enable snoop.
1348 */
1349 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
445a51b3 1350 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626 1351 update_pci_byte(chip->pci,
27fe48d9
TI		 1352 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1353 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1354 }
1355
1356 /* For NVIDIA HDA, enable snoop */
1357 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
445a51b3 1358 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626
TI		 1359 update_pci_byte(chip->pci,
1360 NVIDIA_HDA_TRANSREG_ADDR,
1361 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1362 update_pci_byte(chip->pci,
1363 NVIDIA_HDA_ISTRM_COH,
1364 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1365 update_pci_byte(chip->pci,
1366 NVIDIA_HDA_OSTRM_COH,
1367 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1368 }
1369
1370 /* Enable SCH/PCH snoop if needed */
1371 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1372 unsigned short snoop;
90a5ad52 1373 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1374 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1375 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1376 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1377 if (!azx_snoop(chip))
1378 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1379 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1380 pci_read_config_word(chip->pci,
1381 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1382 }
445a51b3
DB		 1383 snd_printdd(SFX "%s: SCH snoop: %s\n",
1384 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
27fe48d9 1385 ? "Disabled" : "Enabled");
da3fca21 1386 }
1da177e4
LT		 1387}
1388
1389
9ad593f6
TI		 1390static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1391
1da177e4
LT		 1392/*
1393 * interrupt handler
1394 */
7d12e780 1395static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1396{
a98f90fd
TI		 1397 struct azx *chip = dev_id;
1398 struct azx_dev *azx_dev;
1da177e4 1399 u32 status;
9ef04066 1400 u8 sd_status;
fa00e046 1401 int i, ok;
1da177e4 1402
b8dfc462 1403#ifdef CONFIG_PM_RUNTIME
246efa4a
DA		 1404 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1405 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1406 return IRQ_NONE;
b8dfc462
ML		 1407#endif
1408
1da177e4
LT		 1409 spin_lock(&chip->reg_lock);
1410
60911062
DC		 1411 if (chip->disabled) {
1412 spin_unlock(&chip->reg_lock);
a82d51ed 1413 return IRQ_NONE;
60911062 1414 }
a82d51ed 1415
1da177e4 1416 status = azx_readl(chip, INTSTS);
246efa4a 1417 if (status == 0 || status == 0xffffffff) {
1da177e4
LT		 1418 spin_unlock(&chip->reg_lock);
1419 return IRQ_NONE;
1420 }
1421
07e4ca50 1422 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1423 azx_dev = &chip->azx_dev[i];
1424 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1425 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1426 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1427 if (!azx_dev->substream || !azx_dev->running ||
1428 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1429 continue;
1430 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1431 ok = azx_position_ok(chip, azx_dev);
1432 if (ok == 1) {
9ad593f6 1433 azx_dev->irq_pending = 0;
1da177e4
LT		 1434 spin_unlock(&chip->reg_lock);
1435 snd_pcm_period_elapsed(azx_dev->substream);
1436 spin_lock(&chip->reg_lock);
fa00e046 1437 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1438 /* bogus IRQ, process it later */
1439 azx_dev->irq_pending = 1;
6acaed38
TI		 1440 queue_work(chip->bus->workq,
1441 &chip->irq_pending_work);
1da177e4
LT		 1442 }
1443 }
1444 }
1445
1446 /* clear rirb int */
1447 status = azx_readb(chip, RIRBSTS);
1448 if (status & RIRB_INT_MASK) {
14d34f16 1449 if (status & RIRB_INT_RESPONSE) {
9477c58e 1450 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1451 udelay(80);
1da177e4 1452 azx_update_rirb(chip);
14d34f16 1453 }
1da177e4
LT		 1454 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1455 }
1456
1457#if 0
1458 /* clear state status int */
da7db6ad
WX		 1459 if (azx_readw(chip, STATESTS) & 0x04)
1460 azx_writew(chip, STATESTS, 0x04);
1da177e4
LT		 1461#endif
1462 spin_unlock(&chip->reg_lock);
1463
1464 return IRQ_HANDLED;
1465}
1466
1467
675f25d4
TI		 1468/*
1469 * set up a BDL entry
1470 */
5ae763b1 1471static int setup_bdle(struct azx *chip,
1d1a4564 1472 struct snd_dma_buffer *dmab,
675f25d4
TI		 1473 struct azx_dev *azx_dev, u32 **bdlp,
1474 int ofs, int size, int with_ioc)
1475{
675f25d4
TI		 1476 u32 *bdl = *bdlp;
1477
1478 while (size > 0) {
1479 dma_addr_t addr;
1480 int chunk;
1481
1482 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1483 return -EINVAL;
1484
1d1a4564 1485 addr = snd_sgbuf_get_addr(dmab, ofs);
675f25d4
TI		 1486 /* program the address field of the BDL entry */
1487 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1488 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1489 /* program the size field of the BDL entry */
1d1a4564 1490 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
5ae763b1
TI		 1491 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1492 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1493 u32 remain = 0x1000 - (ofs & 0xfff);
1494 if (chunk > remain)
1495 chunk = remain;
1496 }
675f25d4
TI		 1497 bdl[2] = cpu_to_le32(chunk);
1498 /* program the IOC to enable interrupt
1499 * only when the whole fragment is processed
1500 */
1501 size -= chunk;
1502 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1503 bdl += 4;
1504 azx_dev->frags++;
1505 ofs += chunk;
1506 }
1507 *bdlp = bdl;
1508 return ofs;
1509}
1510
1da177e4
LT		 1511/*
1512 * set up BDL entries
1513 */
555e219f
TI		 1514static int azx_setup_periods(struct azx *chip,
1515 struct snd_pcm_substream *substream,
4ce107b9 1516 struct azx_dev *azx_dev)
1da177e4 1517{
4ce107b9
TI		 1518 u32 *bdl;
1519 int i, ofs, periods, period_bytes;
555e219f 1520 int pos_adj;
1da177e4
LT		 1521
1522 /* reset BDL address */
1523 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1524 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1525
97b71c94 1526 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1527 periods = azx_dev->bufsize / period_bytes;
1528
1da177e4 1529 /* program the initial BDL entries */
4ce107b9
TI		 1530 bdl = (u32 *)azx_dev->bdl.area;
1531 ofs = 0;
1532 azx_dev->frags = 0;
555e219f 1533 pos_adj = bdl_pos_adj[chip->dev_index];
915bf29e 1534 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
675f25d4 1535 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1536 int pos_align = pos_adj;
555e219f 1537 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1538 if (!pos_adj)
e785d3d8
TI		 1539 pos_adj = pos_align;
1540 else
1541 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1542 pos_align;
675f25d4
TI		 1543 pos_adj = frames_to_bytes(runtime, pos_adj);
1544 if (pos_adj >= period_bytes) {
445a51b3
DB		 1545 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1546 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1547 pos_adj = 0;
1548 } else {
1d1a4564
TI		 1549 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1550 azx_dev,
915bf29e 1551 &bdl, ofs, pos_adj, true);
675f25d4
TI		 1552 if (ofs < 0)
1553 goto error;
4ce107b9 1554 }
555e219f
TI		 1555 } else
1556 pos_adj = 0;
675f25d4
TI		 1557 for (i = 0; i < periods; i++) {
1558 if (i == periods - 1 && pos_adj)
1d1a4564
TI		 1559 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1560 azx_dev, &bdl, ofs,
675f25d4
TI		 1561 period_bytes - pos_adj, 0);
1562 else
1d1a4564
TI		 1563 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1564 azx_dev, &bdl, ofs,
7bb8fb70 1565 period_bytes,
915bf29e 1566 !azx_dev->no_period_wakeup);
675f25d4
TI		 1567 if (ofs < 0)
1568 goto error;
1da177e4 1569 }
4ce107b9 1570 return 0;
675f25d4
TI		 1571
1572 error:
445a51b3
DB		 1573 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1574 pci_name(chip->pci), azx_dev->bufsize, period_bytes);
675f25d4 1575 return -EINVAL;
1da177e4
LT		 1576}
1577
1dddab40
TI		 1578/* reset stream */
1579static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1580{
1581 unsigned char val;
1582 int timeout;
1583
1dddab40
TI		 1584 azx_stream_clear(chip, azx_dev);
1585
d01ce99f
TI		 1586 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1587 SD_CTL_STREAM_RESET);
1da177e4
LT		 1588 udelay(3);
1589 timeout = 300;
1590 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1591 --timeout)
1592 ;
1593 val &= ~SD_CTL_STREAM_RESET;
1594 azx_sd_writeb(azx_dev, SD_CTL, val);
1595 udelay(3);
1596
1597 timeout = 300;
1598 /* waiting for hardware to report that the stream is out of reset */
1599 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1600 --timeout)
1601 ;
fa00e046
JK		 1602
1603 /* reset first position - may not be synced with hw at this time */
1604 *azx_dev->posbuf = 0;
1dddab40 1605}
1da177e4 1606
1dddab40
TI		 1607/*
1608 * set up the SD for streaming
1609 */
1610static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1611{
27fe48d9 1612 unsigned int val;
1dddab40
TI		 1613 /* make sure the run bit is zero for SD */
1614 azx_stream_clear(chip, azx_dev);
1da177e4 1615 /* program the stream_tag */
27fe48d9
TI		 1616 val = azx_sd_readl(azx_dev, SD_CTL);
1617 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1618 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1619 if (!azx_snoop(chip))
1620 val |= SD_CTL_TRAFFIC_PRIO;
1621 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1622
1623 /* program the length of samples in cyclic buffer */
1624 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1625
1626 /* program the stream format */
1627 /* this value needs to be the same as the one programmed */
1628 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1629
1630 /* program the stream LVI (last valid index) of the BDL */
1631 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1632
1633 /* program the BDL address */
1634 /* lower BDL address */
4ce107b9 1635 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1636 /* upper BDL address */
766979e0 1637 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1638
0be3b5d3 1639 /* enable the position buffer */
4cb36310
DH		 1640 if (chip->position_fix[0] != POS_FIX_LPIB ||
1641 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1642 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1643 azx_writel(chip, DPLBASE,
1644 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1645 }
c74db86b 1646
1da177e4 1647 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1648 azx_sd_writel(azx_dev, SD_CTL,
1649 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1650
1651 return 0;
1652}
1653
6ce4a3bc
TI		 1654/*
1655 * Probe the given codec address
1656 */
1657static int probe_codec(struct azx *chip, int addr)
1658{
1659 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1660 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1661 unsigned int res;
1662
a678cdee 1663 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1664 chip->probing = 1;
1665 azx_send_cmd(chip->bus, cmd);
deadff16 1666 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1667 chip->probing = 0;
a678cdee 1668 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1669 if (res == -1)
1670 return -EIO;
445a51b3 1671 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
6ce4a3bc
TI		 1672 return 0;
1673}
1674
33fa35ed
TI		 1675static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1676 struct hda_pcm *cpcm);
6ce4a3bc 1677static void azx_stop_chip(struct azx *chip);
1da177e4 1678
8dd78330
TI		 1679static void azx_bus_reset(struct hda_bus *bus)
1680{
1681 struct azx *chip = bus->private_data;
8dd78330
TI		 1682
1683 bus->in_reset = 1;
1684 azx_stop_chip(chip);
cd508fe5 1685 azx_init_chip(chip, 1);
65f75983 1686#ifdef CONFIG_PM
8dd78330 1687 if (chip->initialized) {
01b65bfb
TI		 1688 struct azx_pcm *p;
1689 list_for_each_entry(p, &chip->pcm_list, list)
1690 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1691 snd_hda_suspend(chip->bus);
1692 snd_hda_resume(chip->bus);
1693 }
65f75983 1694#endif
8dd78330
TI		 1695 bus->in_reset = 0;
1696}
1697
26a6cb6c
DH		 1698static int get_jackpoll_interval(struct azx *chip)
1699{
1700 int i = jackpoll_ms[chip->dev_index];
1701 unsigned int j;
1702 if (i == 0)
1703 return 0;
1704 if (i < 50 || i > 60000)
1705 j = 0;
1706 else
1707 j = msecs_to_jiffies(i);
1708 if (j == 0)
1709 snd_printk(KERN_WARNING SFX
1710 "jackpoll_ms value out of range: %d\n", i);
1711 return j;
1712}
1713
1da177e4
LT		 1714/*
1715 * Codec initialization
1716 */
1717
2f5983f2 1718/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
48c8b0eb 1719static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
7445dfc1 1720 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1721 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1722};
1723
48c8b0eb 1724static int azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1725{
1726 struct hda_bus_template bus_temp;
34c25350
TI		 1727 int c, codecs, err;
1728 int max_slots;
1da177e4
LT		 1729
1730 memset(&bus_temp, 0, sizeof(bus_temp));
1731 bus_temp.private_data = chip;
1732 bus_temp.modelname = model;
1733 bus_temp.pci = chip->pci;
111d3af5
TI		 1734 bus_temp.ops.command = azx_send_cmd;
1735 bus_temp.ops.get_response = azx_get_response;
176d5335 1736 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1737 bus_temp.ops.bus_reset = azx_bus_reset;
83012a7c 1738#ifdef CONFIG_PM
11cd41b8 1739 bus_temp.power_save = &power_save;
cb53c626
TI		 1740 bus_temp.ops.pm_notify = azx_power_notify;
1741#endif
1d1a4564
TI		 1742#ifdef CONFIG_SND_HDA_DSP_LOADER
1743 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1744 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1745 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1746#endif
1da177e4 1747
d01ce99f
TI		 1748 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1749 if (err < 0)
1da177e4
LT		 1750 return err;
1751
9477c58e 1752 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
445a51b3 1753 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
dc9c8e21 1754 chip->bus->needs_damn_long_delay = 1;
9477c58e 1755 }
dc9c8e21 1756
34c25350 1757 codecs = 0;
2f5983f2
TI		 1758 max_slots = azx_max_codecs[chip->driver_type];
1759 if (!max_slots)
7445dfc1 1760 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1761
1762 /* First try to probe all given codec slots */
1763 for (c = 0; c < max_slots; c++) {
f1eaaeec 1764 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1765 if (probe_codec(chip, c) < 0) {
1766 /* Some BIOSen give you wrong codec addresses
1767 * that don't exist
1768 */
4abc1cc2 1769 snd_printk(KERN_WARNING SFX
445a51b3
DB		 1770 "%s: Codec #%d probe error; "
1771 "disabling it...\n", pci_name(chip->pci), c);
6ce4a3bc
TI		 1772 chip->codec_mask &= ~(1 << c);
1773 /* More badly, accessing to a non-existing
1774 * codec often screws up the controller chip,
2448158e 1775 * and disturbs the further communications.
6ce4a3bc
TI		 1776 * Thus if an error occurs during probing,
1777 * better to reset the controller chip to
1778 * get back to the sanity state.
1779 */
1780 azx_stop_chip(chip);
cd508fe5 1781 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1782 }
1783 }
1784 }
1785
d507cd66
TI		 1786 /* AMD chipsets often cause the communication stalls upon certain
1787 * sequence like the pin-detection. It seems that forcing the synced
1788 * access works around the stall. Grrr...
1789 */
9477c58e 1790 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
445a51b3
DB		 1791 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1792 pci_name(chip->pci));
d507cd66
TI		 1793 chip->bus->sync_write = 1;
1794 chip->bus->allow_bus_reset = 1;
1795 }
1796
6ce4a3bc 1797 /* Then create codec instances */
34c25350 1798 for (c = 0; c < max_slots; c++) {
f1eaaeec 1799 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1800 struct hda_codec *codec;
a1e21c90 1801 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1802 if (err < 0)
1803 continue;
26a6cb6c 1804 codec->jackpoll_interval = get_jackpoll_interval(chip);
2dca0bba 1805 codec->beep_mode = chip->beep_mode;
1da177e4 1806 codecs++;
19a982b6
TI		 1807 }
1808 }
1809 if (!codecs) {
445a51b3 1810 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1da177e4
LT		 1811 return -ENXIO;
1812 }
a1e21c90
TI		 1813 return 0;
1814}
1da177e4 1815
a1e21c90 1816/* configure each codec instance */
e23e7a14 1817static int azx_codec_configure(struct azx *chip)
a1e21c90
TI		 1818{
1819 struct hda_codec *codec;
1820 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1821 snd_hda_codec_configure(codec);
1822 }
1da177e4
LT		 1823 return 0;
1824}
1825
1826
1827/*
1828 * PCM support
1829 */
1830
1831/* assign a stream for the PCM */
ef18bede
WF		 1832static inline struct azx_dev *
1833azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1834{
07e4ca50 1835 int dev, i, nums;
ef18bede 1836 struct azx_dev *res = NULL;
d5cf9911
TI		 1837 /* make a non-zero unique key for the substream */
1838 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1839 (substream->stream + 1);
ef18bede
WF		 1840
1841 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1842 dev = chip->playback_index_offset;
1843 nums = chip->playback_streams;
1844 } else {
1845 dev = chip->capture_index_offset;
1846 nums = chip->capture_streams;
1847 }
eb49faa6
TI		 1848 for (i = 0; i < nums; i++, dev++) {
1849 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1850 dsp_lock(azx_dev);
1851 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1852 res = azx_dev;
1853 if (res->assigned_key == key) {
1854 res->opened = 1;
1855 res->assigned_key = key;
1856 dsp_unlock(azx_dev);
1857 return azx_dev;
1858 }
1da177e4 1859 }
eb49faa6
TI		 1860 dsp_unlock(azx_dev);
1861 }
ef18bede 1862 if (res) {
eb49faa6 1863 dsp_lock(res);
ef18bede 1864 res->opened = 1;
d5cf9911 1865 res->assigned_key = key;
eb49faa6 1866 dsp_unlock(res);
ef18bede
WF		 1867 }
1868 return res;
1da177e4
LT		 1869}
1870
1871/* release the assigned stream */
a98f90fd 1872static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1873{
1874 azx_dev->opened = 0;
1875}
1876
5d890f59
PLB		 1877static cycle_t azx_cc_read(const struct cyclecounter *cc)
1878{
1879 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1880 struct snd_pcm_substream *substream = azx_dev->substream;
1881 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1882 struct azx *chip = apcm->chip;
1883
1884 return azx_readl(chip, WALLCLK);
1885}
1886
1887static void azx_timecounter_init(struct snd_pcm_substream *substream,
1888 bool force, cycle_t last)
1889{
1890 struct azx_dev *azx_dev = get_azx_dev(substream);
1891 struct timecounter *tc = &azx_dev->azx_tc;
1892 struct cyclecounter *cc = &azx_dev->azx_cc;
1893 u64 nsec;
1894
1895 cc->read = azx_cc_read;
1896 cc->mask = CLOCKSOURCE_MASK(32);
1897
1898 /*
1899 * Converting from 24 MHz to ns means applying a 125/3 factor.
1900 * To avoid any saturation issues in intermediate operations,
1901 * the 125 factor is applied first. The division is applied
1902 * last after reading the timecounter value.
1903 * Applying the 1/3 factor as part of the multiplication
1904 * requires at least 20 bits for a decent precision, however
1905 * overflows occur after about 4 hours or less, not a option.
1906 */
1907
1908 cc->mult = 125; /* saturation after 195 years */
1909 cc->shift = 0;
1910
1911 nsec = 0; /* audio time is elapsed time since trigger */
1912 timecounter_init(tc, cc, nsec);
1913 if (force)
1914 /*
1915 * force timecounter to use predefined value,
1916 * used for synchronized starts
1917 */
1918 tc->cycle_last = last;
1919}
1920
ae03bbb8 1921static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
78daea29
DR		 1922 u64 nsec)
1923{
1924 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1925 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1926 u64 codec_frames, codec_nsecs;
1927
1928 if (!hinfo->ops.get_delay)
1929 return nsec;
1930
1931 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1932 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1933 substream->runtime->rate);
1934
ae03bbb8
DR		 1935 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1936 return nsec + codec_nsecs;
1937
78daea29
DR		 1938 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1939}
1940
5d890f59
PLB		 1941static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1942 struct timespec *ts)
1943{
1944 struct azx_dev *azx_dev = get_azx_dev(substream);
1945 u64 nsec;
1946
1947 nsec = timecounter_read(&azx_dev->azx_tc);
1948 nsec = div_u64(nsec, 3); /* can be optimized */
ae03bbb8 1949 nsec = azx_adjust_codec_delay(substream, nsec);
5d890f59
PLB		 1950
1951 *ts = ns_to_timespec(nsec);
1952
1953 return 0;
1954}
1955
a98f90fd 1956static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1957 .info = (SNDRV_PCM_INFO_MMAP |
1958 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1959 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1960 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1961 /* No full-resume yet implemented */
1962 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1963 SNDRV_PCM_INFO_PAUSE |
7bb8fb70 1964 SNDRV_PCM_INFO_SYNC_START |
5d890f59 1965 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
7bb8fb70 1966 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1967 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1968 .rates = SNDRV_PCM_RATE_48000,
1969 .rate_min = 48000,
1970 .rate_max = 48000,
1971 .channels_min = 2,
1972 .channels_max = 2,
1973 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1974 .period_bytes_min = 128,
1975 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1976 .periods_min = 2,
1977 .periods_max = AZX_MAX_FRAG,
1978 .fifo_size = 0,
1979};
1980
a98f90fd 1981static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1982{
1983 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1984 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1985 struct azx *chip = apcm->chip;
1986 struct azx_dev *azx_dev;
1987 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1988 unsigned long flags;
1989 int err;
2ae66c26 1990 int buff_step;
1da177e4 1991
62932df8 1992 mutex_lock(&chip->open_mutex);
ef18bede 1993 azx_dev = azx_assign_device(chip, substream);
1da177e4 1994 if (azx_dev == NULL) {
62932df8 1995 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1996 return -EBUSY;
1997 }
1998 runtime->hw = azx_pcm_hw;
1999 runtime->hw.channels_min = hinfo->channels_min;
2000 runtime->hw.channels_max = hinfo->channels_max;
2001 runtime->hw.formats = hinfo->formats;
2002 runtime->hw.rates = hinfo->rates;
2003 snd_pcm_limit_hw_rates(runtime);
2004 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5d890f59
PLB		 2005
2006 /* avoid wrap-around with wall-clock */
2007 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
2008 20,
2009 178000000);
2010
52409aa6 2011 if (chip->align_buffer_size)
2ae66c26
PLB		 2012 /* constrain buffer sizes to be multiple of 128
2013 bytes. This is more efficient in terms of memory
2014 access but isn't required by the HDA spec and
2015 prevents users from specifying exact period/buffer
2016 sizes. For example for 44.1kHz, a period size set
2017 to 20ms will be rounded to 19.59ms. */
2018 buff_step = 128;
2019 else
2020 /* Don't enforce steps on buffer sizes, still need to
2021 be multiple of 4 bytes (HDA spec). Tested on Intel
2022 HDA controllers, may not work on all devices where
2023 option needs to be disabled */
2024 buff_step = 4;
2025
5f1545bc 2026 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 2027 buff_step);
5f1545bc 2028 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 2029 buff_step);
b4a91cf0 2030 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 2031 err = hinfo->ops.open(hinfo, apcm->codec, substream);
2032 if (err < 0) {
1da177e4 2033 azx_release_device(azx_dev);
cb53c626 2034 snd_hda_power_down(apcm->codec);
62932df8 2035 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2036 return err;
2037 }
70d321e6 2038 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 2039 /* sanity check */
2040 if (snd_BUG_ON(!runtime->hw.channels_min) ||
2041 snd_BUG_ON(!runtime->hw.channels_max) ||
2042 snd_BUG_ON(!runtime->hw.formats) ||
2043 snd_BUG_ON(!runtime->hw.rates)) {
2044 azx_release_device(azx_dev);
2045 hinfo->ops.close(hinfo, apcm->codec, substream);
2046 snd_hda_power_down(apcm->codec);
2047 mutex_unlock(&chip->open_mutex);
2048 return -EINVAL;
2049 }
5d890f59
PLB		 2050
2051 /* disable WALLCLOCK timestamps for capture streams
2052 until we figure out how to handle digital inputs */
2053 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2054 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2055
1da177e4
LT		 2056 spin_lock_irqsave(&chip->reg_lock, flags);
2057 azx_dev->substream = substream;
2058 azx_dev->running = 0;
2059 spin_unlock_irqrestore(&chip->reg_lock, flags);
2060
2061 runtime->private_data = azx_dev;
850f0e52 2062 snd_pcm_set_sync(substream);
62932df8 2063 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2064 return 0;
2065}
2066
a98f90fd 2067static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 2068{
2069 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2070 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 2071 struct azx *chip = apcm->chip;
2072 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 2073 unsigned long flags;
2074
62932df8 2075 mutex_lock(&chip->open_mutex);
1da177e4
LT		 2076 spin_lock_irqsave(&chip->reg_lock, flags);
2077 azx_dev->substream = NULL;
2078 azx_dev->running = 0;
2079 spin_unlock_irqrestore(&chip->reg_lock, flags);
2080 azx_release_device(azx_dev);
2081 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 2082 snd_hda_power_down(apcm->codec);
62932df8 2083 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2084 return 0;
2085}
2086
d01ce99f
TI		 2087static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2088 struct snd_pcm_hw_params *hw_params)
1da177e4 2089{
27fe48d9
TI		 2090 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2091 struct azx *chip = apcm->chip;
97b71c94 2092 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 2093 int ret;
97b71c94 2094
eb49faa6
TI		 2095 dsp_lock(azx_dev);
2096 if (dsp_is_locked(azx_dev)) {
2097 ret = -EBUSY;
2098 goto unlock;
2099 }
2100
9ddf1aeb 2101 mark_runtime_wc(chip, azx_dev, substream, false);
97b71c94
TI		 2102 azx_dev->bufsize = 0;
2103 azx_dev->period_bytes = 0;
2104 azx_dev->format_val = 0;
27fe48d9 2105 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 2106 params_buffer_bytes(hw_params));
27fe48d9 2107 if (ret < 0)
eb49faa6 2108 goto unlock;
9ddf1aeb 2109 mark_runtime_wc(chip, azx_dev, substream, true);
eb49faa6
TI		 2110 unlock:
2111 dsp_unlock(azx_dev);
27fe48d9 2112 return ret;
1da177e4
LT		 2113}
2114
a98f90fd 2115static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 2116{
2117 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2118 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 2119 struct azx *chip = apcm->chip;
1da177e4
LT		 2120 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2121
2122 /* reset BDL address */
eb49faa6
TI		 2123 dsp_lock(azx_dev);
2124 if (!dsp_is_locked(azx_dev)) {
2125 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2126 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2127 azx_sd_writel(azx_dev, SD_CTL, 0);
2128 azx_dev->bufsize = 0;
2129 azx_dev->period_bytes = 0;
2130 azx_dev->format_val = 0;
2131 }
1da177e4 2132
eb541337 2133 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 2134
9ddf1aeb 2135 mark_runtime_wc(chip, azx_dev, substream, false);
eb49faa6
TI		 2136 azx_dev->prepared = 0;
2137 dsp_unlock(azx_dev);
1da177e4
LT		 2138 return snd_pcm_lib_free_pages(substream);
2139}
2140
a98f90fd 2141static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 2142{
2143 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 2144 struct azx *chip = apcm->chip;
2145 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 2146 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 2147 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 2148 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 2149 int err;
7c935976
SW		 2150 struct hda_spdif_out *spdif =
2151 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2152 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 2153
eb49faa6
TI		 2154 dsp_lock(azx_dev);
2155 if (dsp_is_locked(azx_dev)) {
2156 err = -EBUSY;
2157 goto unlock;
2158 }
2159
fa00e046 2160 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 2161 format_val = snd_hda_calc_stream_format(runtime->rate,
2162 runtime->channels,
2163 runtime->format,
32c168c8 2164 hinfo->maxbps,
7c935976 2165 ctls);
97b71c94 2166 if (!format_val) {
d01ce99f 2167 snd_printk(KERN_ERR SFX
445a51b3
DB		 2168 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2169 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
eb49faa6
TI		 2170 err = -EINVAL;
2171 goto unlock;
1da177e4
LT		 2172 }
2173
97b71c94
TI		 2174 bufsize = snd_pcm_lib_buffer_bytes(substream);
2175 period_bytes = snd_pcm_lib_period_bytes(substream);
2176
445a51b3
DB		 2177 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2178 pci_name(chip->pci), bufsize, format_val);
97b71c94
TI		 2179
2180 if (bufsize != azx_dev->bufsize ||
2181 period_bytes != azx_dev->period_bytes ||
915bf29e
TI		 2182 format_val != azx_dev->format_val ||
2183 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
97b71c94
TI		 2184 azx_dev->bufsize = bufsize;
2185 azx_dev->period_bytes = period_bytes;
2186 azx_dev->format_val = format_val;
915bf29e 2187 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
97b71c94
TI		 2188 err = azx_setup_periods(chip, substream, azx_dev);
2189 if (err < 0)
eb49faa6 2190 goto unlock;
97b71c94
TI		 2191 }
2192
e5463720
JK		 2193 /* wallclk has 24Mhz clock source */
2194 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2195 runtime->rate) * 1000);
1da177e4
LT		 2196 azx_setup_controller(chip, azx_dev);
2197 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2198 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2199 else
2200 azx_dev->fifo_size = 0;
2201
62b7e5e0
TI		 2202 stream_tag = azx_dev->stream_tag;
2203 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 2204 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 2205 stream_tag > chip->capture_streams)
2206 stream_tag -= chip->capture_streams;
eb49faa6 2207 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 2208 azx_dev->format_val, substream);
eb49faa6
TI		 2209
2210 unlock:
2211 if (!err)
2212 azx_dev->prepared = 1;
2213 dsp_unlock(azx_dev);
2214 return err;
1da177e4
LT		 2215}
2216
a98f90fd 2217static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 2218{
2219 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2220 struct azx *chip = apcm->chip;
850f0e52
TI		 2221 struct azx_dev *azx_dev;
2222 struct snd_pcm_substream *s;
fa00e046 2223 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 2224 int nwait, timeout;
1da177e4 2225
1a8506d4
TI		 2226 azx_dev = get_azx_dev(substream);
2227 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2228
eb49faa6
TI		 2229 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2230 return -EPIPE;
2231
1da177e4 2232 switch (cmd) {
fa00e046
JK		 2233 case SNDRV_PCM_TRIGGER_START:
2234 rstart = 1;
1da177e4
LT		 2235 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2236 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 2237 start = 1;
1da177e4
LT		 2238 break;
2239 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 2240 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 2241 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 2242 start = 0;
1da177e4
LT		 2243 break;
2244 default:
850f0e52
TI		 2245 return -EINVAL;
2246 }
2247
2248 snd_pcm_group_for_each_entry(s, substream) {
2249 if (s->pcm->card != substream->pcm->card)
2250 continue;
2251 azx_dev = get_azx_dev(s);
2252 sbits |= 1 << azx_dev->index;
2253 nsync++;
2254 snd_pcm_trigger_done(s, substream);
2255 }
2256
2257 spin_lock(&chip->reg_lock);
172d3b20
PLB		 2258
2259 /* first, set SYNC bits of corresponding streams */
2260 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2261 azx_writel(chip, OLD_SSYNC,
2262 azx_readl(chip, OLD_SSYNC) | sbits);
2263 else
2264 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2265
850f0e52
TI		 2266 snd_pcm_group_for_each_entry(s, substream) {
2267 if (s->pcm->card != substream->pcm->card)
2268 continue;
2269 azx_dev = get_azx_dev(s);
e5463720
JK		 2270 if (start) {
2271 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2272 if (!rstart)
2273 azx_dev->start_wallclk -=
2274 azx_dev->period_wallclk;
850f0e52 2275 azx_stream_start(chip, azx_dev);
e5463720 2276 } else {
850f0e52 2277 azx_stream_stop(chip, azx_dev);
e5463720 2278 }
850f0e52 2279 azx_dev->running = start;
1da177e4
LT		 2280 }
2281 spin_unlock(&chip->reg_lock);
850f0e52 2282 if (start) {
850f0e52
TI		 2283 /* wait until all FIFOs get ready */
2284 for (timeout = 5000; timeout; timeout--) {
2285 nwait = 0;
2286 snd_pcm_group_for_each_entry(s, substream) {
2287 if (s->pcm->card != substream->pcm->card)
2288 continue;
2289 azx_dev = get_azx_dev(s);
2290 if (!(azx_sd_readb(azx_dev, SD_STS) &
2291 SD_STS_FIFO_READY))
2292 nwait++;
2293 }
2294 if (!nwait)
2295 break;
2296 cpu_relax();
2297 }
2298 } else {
2299 /* wait until all RUN bits are cleared */
2300 for (timeout = 5000; timeout; timeout--) {
2301 nwait = 0;
2302 snd_pcm_group_for_each_entry(s, substream) {
2303 if (s->pcm->card != substream->pcm->card)
2304 continue;
2305 azx_dev = get_azx_dev(s);
2306 if (azx_sd_readb(azx_dev, SD_CTL) &
2307 SD_CTL_DMA_START)
2308 nwait++;
2309 }
2310 if (!nwait)
2311 break;
2312 cpu_relax();
2313 }
1da177e4 2314 }
172d3b20
PLB		 2315 spin_lock(&chip->reg_lock);
2316 /* reset SYNC bits */
2317 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2318 azx_writel(chip, OLD_SSYNC,
2319 azx_readl(chip, OLD_SSYNC) & ~sbits);
2320 else
2321 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
5d890f59
PLB		 2322 if (start) {
2323 azx_timecounter_init(substream, 0, 0);
2324 if (nsync > 1) {
2325 cycle_t cycle_last;
2326
2327 /* same start cycle for master and group */
2328 azx_dev = get_azx_dev(substream);
2329 cycle_last = azx_dev->azx_tc.cycle_last;
2330
2331 snd_pcm_group_for_each_entry(s, substream) {
2332 if (s->pcm->card != substream->pcm->card)
2333 continue;
2334 azx_timecounter_init(s, 1, cycle_last);
2335 }
2336 }
2337 }
172d3b20 2338 spin_unlock(&chip->reg_lock);
850f0e52 2339 return 0;
1da177e4
LT		 2340}
2341
0e153474
JC		 2342/* get the current DMA position with correction on VIA chips */
2343static unsigned int azx_via_get_position(struct azx *chip,
2344 struct azx_dev *azx_dev)
2345{
2346 unsigned int link_pos, mini_pos, bound_pos;
2347 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2348 unsigned int fifo_size;
2349
2350 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2351 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2352 /* Playback, no problem using link position */
2353 return link_pos;
2354 }
2355
2356 /* Capture */
2357 /* For new chipset,
2358 * use mod to get the DMA position just like old chipset
2359 */
2360 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2361 mod_dma_pos %= azx_dev->period_bytes;
2362
2363 /* azx_dev->fifo_size can't get FIFO size of in stream.
2364 * Get from base address + offset.
2365 */
2366 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2367
2368 if (azx_dev->insufficient) {
2369 /* Link position never gather than FIFO size */
2370 if (link_pos <= fifo_size)
2371 return 0;
2372
2373 azx_dev->insufficient = 0;
2374 }
2375
2376 if (link_pos <= fifo_size)
2377 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2378 else
2379 mini_pos = link_pos - fifo_size;
2380
2381 /* Find nearest previous boudary */
2382 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2383 mod_link_pos = link_pos % azx_dev->period_bytes;
2384 if (mod_link_pos >= fifo_size)
2385 bound_pos = link_pos - mod_link_pos;
2386 else if (mod_dma_pos >= mod_mini_pos)
2387 bound_pos = mini_pos - mod_mini_pos;
2388 else {
2389 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2390 if (bound_pos >= azx_dev->bufsize)
2391 bound_pos = 0;
2392 }
2393
2394 /* Calculate real DMA position we want */
2395 return bound_pos + mod_dma_pos;
2396}
2397
9ad593f6 2398static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2399 struct azx_dev *azx_dev,
2400 bool with_check)
1da177e4 2401{
21229613
TI		 2402 struct snd_pcm_substream *substream = azx_dev->substream;
2403 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1da177e4 2404 unsigned int pos;
21229613
TI		 2405 int stream = substream->stream;
2406 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
1a8506d4 2407 int delay = 0;
1da177e4 2408
4cb36310
DH		 2409 switch (chip->position_fix[stream]) {
2410 case POS_FIX_LPIB:
2411 /* read LPIB */
2412 pos = azx_sd_readl(azx_dev, SD_LPIB);
2413 break;
2414 case POS_FIX_VIACOMBO:
0e153474 2415 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2416 break;
2417 default:
2418 /* use the position buffer */
2419 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2420 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2421 if (!pos || pos == (u32)-1) {
2422 printk(KERN_WARNING
2423 "hda-intel: Invalid position buffer, "
2424 "using LPIB read method instead.\n");
2425 chip->position_fix[stream] = POS_FIX_LPIB;
2426 pos = azx_sd_readl(azx_dev, SD_LPIB);
2427 } else
2428 chip->position_fix[stream] = POS_FIX_POSBUF;
2429 }
2430 break;
c74db86b 2431 }
4cb36310 2432
1da177e4
LT		 2433 if (pos >= azx_dev->bufsize)
2434 pos = 0;
90accc58
PLB		 2435
2436 /* calculate runtime delay from LPIB */
21229613 2437 if (substream->runtime &&
90accc58
PLB		 2438 chip->position_fix[stream] == POS_FIX_POSBUF &&
2439 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2440 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
90accc58
PLB		 2441 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2442 delay = pos - lpib_pos;
2443 else
2444 delay = lpib_pos - pos;
2445 if (delay < 0)
2446 delay += azx_dev->bufsize;
2447 if (delay >= azx_dev->period_bytes) {
1f04661f 2448 snd_printk(KERN_WARNING SFX
445a51b3 2449 "%s: Unstable LPIB (%d >= %d); "
1f04661f 2450 "disabling LPIB delay counting\n",
445a51b3 2451 pci_name(chip->pci), delay, azx_dev->period_bytes);
1f04661f
TI		 2452 delay = 0;
2453 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
90accc58 2454 }
21229613 2455 delay = bytes_to_frames(substream->runtime, delay);
90accc58 2456 }
21229613
TI		 2457
2458 if (substream->runtime) {
2459 if (hinfo->ops.get_delay)
2460 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2461 substream);
2462 substream->runtime->delay = delay;
2463 }
2464
1a8506d4 2465 trace_azx_get_position(chip, azx_dev, pos, delay);
9ad593f6
TI		 2466 return pos;
2467}
2468
2469static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2470{
2471 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2472 struct azx *chip = apcm->chip;
2473 struct azx_dev *azx_dev = get_azx_dev(substream);
2474 return bytes_to_frames(substream->runtime,
798cb7e8 2475 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2476}
2477
2478/*
2479 * Check whether the current DMA position is acceptable for updating
2480 * periods. Returns non-zero if it's OK.
2481 *
2482 * Many HD-audio controllers appear pretty inaccurate about
2483 * the update-IRQ timing. The IRQ is issued before actually the
2484 * data is processed. So, we need to process it afterwords in a
2485 * workqueue.
2486 */
2487static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2488{
e5463720 2489 u32 wallclk;
9ad593f6
TI		 2490 unsigned int pos;
2491
f48f606d
JK		 2492 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2493 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2494 return -1; /* bogus (too early) interrupt */
fa00e046 2495
798cb7e8 2496 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2497
d6d8bf54
TI		 2498 if (WARN_ONCE(!azx_dev->period_bytes,
2499 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2500 return -1; /* this shouldn't happen! */
edb39935 2501 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2502 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2503 /* NG - it's below the first next period boundary */
2504 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2505 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2506 return 1; /* OK, it's fine */
2507}
2508
2509/*
2510 * The work for pending PCM period updates.
2511 */
2512static void azx_irq_pending_work(struct work_struct *work)
2513{
2514 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2515 int i, pending, ok;
9ad593f6 2516
a6a950a8
TI		 2517 if (!chip->irq_pending_warned) {
2518 printk(KERN_WARNING
2519 "hda-intel: IRQ timing workaround is activated "
2520 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2521 chip->card->number);
2522 chip->irq_pending_warned = 1;
2523 }
2524
9ad593f6
TI		 2525 for (;;) {
2526 pending = 0;
2527 spin_lock_irq(&chip->reg_lock);
2528 for (i = 0; i < chip->num_streams; i++) {
2529 struct azx_dev *azx_dev = &chip->azx_dev[i];
2530 if (!azx_dev->irq_pending ||
2531 !azx_dev->substream ||
2532 !azx_dev->running)
2533 continue;
e5463720
JK		 2534 ok = azx_position_ok(chip, azx_dev);
2535 if (ok > 0) {
9ad593f6
TI		 2536 azx_dev->irq_pending = 0;
2537 spin_unlock(&chip->reg_lock);
2538 snd_pcm_period_elapsed(azx_dev->substream);
2539 spin_lock(&chip->reg_lock);
e5463720
JK		 2540 } else if (ok < 0) {
2541 pending = 0; /* too early */
9ad593f6
TI		 2542 } else
2543 pending++;
2544 }
2545 spin_unlock_irq(&chip->reg_lock);
2546 if (!pending)
2547 return;
08af495f 2548 msleep(1);
9ad593f6
TI		 2549 }
2550}
2551
2552/* clear irq_pending flags and assure no on-going workq */
2553static void azx_clear_irq_pending(struct azx *chip)
2554{
2555 int i;
2556
2557 spin_lock_irq(&chip->reg_lock);
2558 for (i = 0; i < chip->num_streams; i++)
2559 chip->azx_dev[i].irq_pending = 0;
2560 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2561}
2562
27fe48d9
TI		 2563#ifdef CONFIG_X86
2564static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2565 struct vm_area_struct *area)
2566{
2567 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2568 struct azx *chip = apcm->chip;
2569 if (!azx_snoop(chip))
2570 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2571 return snd_pcm_lib_default_mmap(substream, area);
2572}
2573#else
2574#define azx_pcm_mmap NULL
2575#endif
2576
a98f90fd 2577static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2578 .open = azx_pcm_open,
2579 .close = azx_pcm_close,
2580 .ioctl = snd_pcm_lib_ioctl,
2581 .hw_params = azx_pcm_hw_params,
2582 .hw_free = azx_pcm_hw_free,
2583 .prepare = azx_pcm_prepare,
2584 .trigger = azx_pcm_trigger,
2585 .pointer = azx_pcm_pointer,
5d890f59 2586 .wall_clock = azx_get_wallclock_tstamp,
27fe48d9 2587 .mmap = azx_pcm_mmap,
4ce107b9 2588 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2589};
2590
a98f90fd 2591static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2592{
176d5335
TI		 2593 struct azx_pcm *apcm = pcm->private_data;
2594 if (apcm) {
01b65bfb 2595 list_del(&apcm->list);
176d5335
TI		 2596 kfree(apcm);
2597 }
1da177e4
LT		 2598}
2599
acfa634f
TI		 2600#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2601
176d5335 2602static int
33fa35ed
TI		 2603azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2604 struct hda_pcm *cpcm)
1da177e4 2605{
33fa35ed 2606 struct azx *chip = bus->private_data;
a98f90fd 2607 struct snd_pcm *pcm;
1da177e4 2608 struct azx_pcm *apcm;
176d5335 2609 int pcm_dev = cpcm->device;
acfa634f 2610 unsigned int size;
176d5335 2611 int s, err;
1da177e4 2612
01b65bfb
TI		 2613 list_for_each_entry(apcm, &chip->pcm_list, list) {
2614 if (apcm->pcm->device == pcm_dev) {
445a51b3
DB		 2615 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2616 pci_name(chip->pci), pcm_dev);
01b65bfb
TI		 2617 return -EBUSY;
2618 }
176d5335
TI		 2619 }
2620 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2621 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2622 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2623 &pcm);
2624 if (err < 0)
2625 return err;
18cb7109 2626 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2627 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2628 if (apcm == NULL)
2629 return -ENOMEM;
2630 apcm->chip = chip;
01b65bfb 2631 apcm->pcm = pcm;
1da177e4 2632 apcm->codec = codec;
1da177e4
LT		 2633 pcm->private_data = apcm;
2634 pcm->private_free = azx_pcm_free;
176d5335
TI		 2635 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2636 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2637 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2638 cpcm->pcm = pcm;
2639 for (s = 0; s < 2; s++) {
2640 apcm->hinfo[s] = &cpcm->stream[s];
2641 if (cpcm->stream[s].substreams)
2642 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2643 }
2644 /* buffer pre-allocation */
acfa634f
TI		 2645 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2646 if (size > MAX_PREALLOC_SIZE)
2647 size = MAX_PREALLOC_SIZE;
4ce107b9 2648 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2649 snd_dma_pci_data(chip->pci),
acfa634f 2650 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2651 return 0;
2652}
2653
2654/*
2655 * mixer creation - all stuff is implemented in hda module
2656 */
e23e7a14 2657static int azx_mixer_create(struct azx *chip)
1da177e4
LT		 2658{
2659 return snd_hda_build_controls(chip->bus);
2660}
2661
2662
2663/*
2664 * initialize SD streams
2665 */
e23e7a14 2666static int azx_init_stream(struct azx *chip)
1da177e4
LT		 2667{
2668 int i;
2669
2670 /* initialize each stream (aka device)
d01ce99f
TI		 2671 * assign the starting bdl address to each stream (device)
2672 * and initialize
1da177e4 2673 */
07e4ca50 2674 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2675 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2676 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2677 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2678 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2679 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2680 azx_dev->sd_int_sta_mask = 1 << i;
2681 /* stream tag: must be non-zero and unique */
2682 azx_dev->index = i;
2683 azx_dev->stream_tag = i + 1;
2684 }
2685
2686 return 0;
2687}
2688
68e7fffc
TI		 2689static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2690{
437a5a46
TI		 2691 if (request_irq(chip->pci->irq, azx_interrupt,
2692 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2693 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2694 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2695 "disabling device\n", chip->pci->irq);
2696 if (do_disconnect)
2697 snd_card_disconnect(chip->card);
2698 return -1;
2699 }
2700 chip->irq = chip->pci->irq;
69e13418 2701 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2702 return 0;
2703}
2704
1da177e4 2705
cb53c626
TI		 2706static void azx_stop_chip(struct azx *chip)
2707{
95e99fda 2708 if (!chip->initialized)
cb53c626
TI		 2709 return;
2710
2711 /* disable interrupts */
2712 azx_int_disable(chip);
2713 azx_int_clear(chip);
2714
2715 /* disable CORB/RIRB */
2716 azx_free_cmd_io(chip);
2717
2718 /* disable position buffer */
2719 azx_writel(chip, DPLBASE, 0);
2720 azx_writel(chip, DPUBASE, 0);
2721
2722 chip->initialized = 0;
2723}
2724
1d1a4564
TI		 2725#ifdef CONFIG_SND_HDA_DSP_LOADER
2726/*
2727 * DSP loading code (e.g. for CA0132)
2728 */
2729
2730/* use the first stream for loading DSP */
2731static struct azx_dev *
2732azx_get_dsp_loader_dev(struct azx *chip)
2733{
2734 return &chip->azx_dev[chip->playback_index_offset];
2735}
2736
2737static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2738 unsigned int byte_size,
2739 struct snd_dma_buffer *bufp)
2740{
2741 u32 *bdl;
2742 struct azx *chip = bus->private_data;
2743 struct azx_dev *azx_dev;
2744 int err;
2745
eb49faa6
TI		 2746 azx_dev = azx_get_dsp_loader_dev(chip);
2747
2748 dsp_lock(azx_dev);
2749 spin_lock_irq(&chip->reg_lock);
2750 if (azx_dev->running || azx_dev->locked) {
2751 spin_unlock_irq(&chip->reg_lock);
2752 err = -EBUSY;
2753 goto unlock;
2754 }
2755 azx_dev->prepared = 0;
2756 chip->saved_azx_dev = *azx_dev;
2757 azx_dev->locked = 1;
2758 spin_unlock_irq(&chip->reg_lock);
1d1a4564
TI		 2759
2760 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2761 snd_dma_pci_data(chip->pci),
2762 byte_size, bufp);
2763 if (err < 0)
eb49faa6 2764 goto err_alloc;
1d1a4564 2765
b3667bd7 2766 mark_pages_wc(chip, bufp, true);
1d1a4564
TI		 2767 azx_dev->bufsize = byte_size;
2768 azx_dev->period_bytes = byte_size;
2769 azx_dev->format_val = format;
2770
2771 azx_stream_reset(chip, azx_dev);
2772
2773 /* reset BDL address */
2774 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2775 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2776
2777 azx_dev->frags = 0;
2778 bdl = (u32 *)azx_dev->bdl.area;
2779 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2780 if (err < 0)
2781 goto error;
2782
2783 azx_setup_controller(chip, azx_dev);
eb49faa6 2784 dsp_unlock(azx_dev);
1d1a4564
TI		 2785 return azx_dev->stream_tag;
2786
2787 error:
b3667bd7
TI		 2788 mark_pages_wc(chip, bufp, false);
2789 snd_dma_free_pages(bufp);
eb49faa6
TI		 2790 err_alloc:
2791 spin_lock_irq(&chip->reg_lock);
2792 if (azx_dev->opened)
2793 *azx_dev = chip->saved_azx_dev;
2794 azx_dev->locked = 0;
2795 spin_unlock_irq(&chip->reg_lock);
2796 unlock:
2797 dsp_unlock(azx_dev);
1d1a4564
TI		 2798 return err;
2799}
2800
2801static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2802{
2803 struct azx *chip = bus->private_data;
2804 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2805
2806 if (start)
2807 azx_stream_start(chip, azx_dev);
2808 else
2809 azx_stream_stop(chip, azx_dev);
2810 azx_dev->running = start;
2811}
2812
2813static void azx_load_dsp_cleanup(struct hda_bus *bus,
2814 struct snd_dma_buffer *dmab)
2815{
2816 struct azx *chip = bus->private_data;
2817 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2818
eb49faa6 2819 if (!dmab->area || !azx_dev->locked)
b3667bd7
TI		 2820 return;
2821
eb49faa6 2822 dsp_lock(azx_dev);
1d1a4564
TI		 2823 /* reset BDL address */
2824 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2825 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2826 azx_sd_writel(azx_dev, SD_CTL, 0);
2827 azx_dev->bufsize = 0;
2828 azx_dev->period_bytes = 0;
2829 azx_dev->format_val = 0;
2830
b3667bd7 2831 mark_pages_wc(chip, dmab, false);
1d1a4564 2832 snd_dma_free_pages(dmab);
b3667bd7 2833 dmab->area = NULL;
1d1a4564 2834
eb49faa6
TI		 2835 spin_lock_irq(&chip->reg_lock);
2836 if (azx_dev->opened)
2837 *azx_dev = chip->saved_azx_dev;
2838 azx_dev->locked = 0;
2839 spin_unlock_irq(&chip->reg_lock);
2840 dsp_unlock(azx_dev);
1d1a4564
TI		 2841}
2842#endif /* CONFIG_SND_HDA_DSP_LOADER */
2843
83012a7c 2844#ifdef CONFIG_PM
cb53c626 2845/* power-up/down the controller */
68467f51 2846static void azx_power_notify(struct hda_bus *bus, bool power_up)
cb53c626 2847{
33fa35ed 2848 struct azx *chip = bus->private_data;
cb53c626 2849
2ea3c6a2
TI		 2850 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2851 return;
2852
68467f51 2853 if (power_up)
b8dfc462
ML		 2854 pm_runtime_get_sync(&chip->pci->dev);
2855 else
2856 pm_runtime_put_sync(&chip->pci->dev);
cb53c626 2857}
65fcd41d
TI		 2858
2859static DEFINE_MUTEX(card_list_lock);
2860static LIST_HEAD(card_list);
2861
2862static void azx_add_card_list(struct azx *chip)
2863{
2864 mutex_lock(&card_list_lock);
2865 list_add(&chip->list, &card_list);
2866 mutex_unlock(&card_list_lock);
2867}
2868
2869static void azx_del_card_list(struct azx *chip)
2870{
2871 mutex_lock(&card_list_lock);
2872 list_del_init(&chip->list);
2873 mutex_unlock(&card_list_lock);
2874}
2875
2876/* trigger power-save check at writing parameter */
2877static int param_set_xint(const char *val, const struct kernel_param *kp)
2878{
2879 struct azx *chip;
2880 struct hda_codec *c;
2881 int prev = power_save;
2882 int ret = param_set_int(val, kp);
2883
2884 if (ret || prev == power_save)
2885 return ret;
2886
2887 mutex_lock(&card_list_lock);
2888 list_for_each_entry(chip, &card_list, list) {
2889 if (!chip->bus || chip->disabled)
2890 continue;
2891 list_for_each_entry(c, &chip->bus->codec_list, list)
2892 snd_hda_power_sync(c);
2893 }
2894 mutex_unlock(&card_list_lock);
2895 return 0;
2896}
2897#else
2898#define azx_add_card_list(chip) /* NOP */
2899#define azx_del_card_list(chip) /* NOP */
83012a7c 2900#endif /* CONFIG_PM */
5c0b9bec 2901
7ccbde57 2902#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 2903/*
2904 * power management
2905 */
68cb2b55 2906static int azx_suspend(struct device *dev)
1da177e4 2907{
68cb2b55
TI		 2908 struct pci_dev *pci = to_pci_dev(dev);
2909 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2910 struct azx *chip = card->private_data;
01b65bfb 2911 struct azx_pcm *p;
1da177e4 2912
c5c21523
TI		 2913 if (chip->disabled)
2914 return 0;
2915
421a1252 2916 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2917 azx_clear_irq_pending(chip);
01b65bfb
TI		 2918 list_for_each_entry(p, &chip->pcm_list, list)
2919 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2920 if (chip->initialized)
8dd78330 2921 snd_hda_suspend(chip->bus);
cb53c626 2922 azx_stop_chip(chip);
7295b264 2923 azx_enter_link_reset(chip);
30b35399 2924 if (chip->irq >= 0) {
43001c95 2925 free_irq(chip->irq, chip);
30b35399
TI		 2926 chip->irq = -1;
2927 }
68e7fffc 2928 if (chip->msi)
43001c95 2929 pci_disable_msi(chip->pci);
421a1252
TI		 2930 pci_disable_device(pci);
2931 pci_save_state(pci);
68cb2b55 2932 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 2933 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2934 hda_display_power(false);
1da177e4
LT		 2935 return 0;
2936}
2937
68cb2b55 2938static int azx_resume(struct device *dev)
1da177e4 2939{
68cb2b55
TI		 2940 struct pci_dev *pci = to_pci_dev(dev);
2941 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2942 struct azx *chip = card->private_data;
1da177e4 2943
c5c21523
TI		 2944 if (chip->disabled)
2945 return 0;
2946
99a2008d
WX		 2947 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2948 hda_display_power(true);
d14a7e0b
TI		 2949 pci_set_power_state(pci, PCI_D0);
2950 pci_restore_state(pci);
30b35399
TI		 2951 if (pci_enable_device(pci) < 0) {
2952 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2953 "disabling device\n");
2954 snd_card_disconnect(card);
2955 return -EIO;
2956 }
2957 pci_set_master(pci);
68e7fffc
TI		 2958 if (chip->msi)
2959 if (pci_enable_msi(pci) < 0)
2960 chip->msi = 0;
2961 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2962 return -EIO;
cb53c626 2963 azx_init_pci(chip);
d804ad92 2964
7f30830b 2965 azx_init_chip(chip, 1);
d804ad92 2966
1da177e4 2967 snd_hda_resume(chip->bus);
421a1252 2968 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2969 return 0;
2970}
b8dfc462
ML		 2971#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2972
2973#ifdef CONFIG_PM_RUNTIME
2974static int azx_runtime_suspend(struct device *dev)
2975{
2976 struct snd_card *card = dev_get_drvdata(dev);
2977 struct azx *chip = card->private_data;
2978
246efa4a
DA		 2979 if (chip->disabled)
2980 return 0;
2981
2982 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2983 return 0;
2984
7d4f606c
WX		 2985 /* enable controller wake up event */
2986 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
2987 STATESTS_INT_MASK);
2988
b8dfc462 2989 azx_stop_chip(chip);
95f74c41
TI		 2990 if (!chip->bus->avoid_link_reset)
2991 azx_enter_link_reset(chip);
b8dfc462 2992 azx_clear_irq_pending(chip);
99a2008d
WX		 2993 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2994 hda_display_power(false);
b8dfc462
ML		 2995 return 0;
2996}
2997
2998static int azx_runtime_resume(struct device *dev)
2999{
3000 struct snd_card *card = dev_get_drvdata(dev);
3001 struct azx *chip = card->private_data;
7d4f606c
WX		 3002 struct hda_bus *bus;
3003 struct hda_codec *codec;
3004 int status;
b8dfc462 3005
246efa4a
DA		 3006 if (chip->disabled)
3007 return 0;
3008
3009 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3010 return 0;
3011
99a2008d
WX		 3012 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3013 hda_display_power(true);
7d4f606c
WX		 3014
3015 /* Read STATESTS before controller reset */
3016 status = azx_readw(chip, STATESTS);
3017
b8dfc462
ML		 3018 azx_init_pci(chip);
3019 azx_init_chip(chip, 1);
7d4f606c
WX		 3020
3021 bus = chip->bus;
3022 if (status && bus) {
3023 list_for_each_entry(codec, &bus->codec_list, list)
3024 if (status & (1 << codec->addr))
3025 queue_delayed_work(codec->bus->workq,
3026 &codec->jackpoll_work, codec->jackpoll_interval);
3027 }
3028
3029 /* disable controller Wake Up event*/
3030 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
3031 ~STATESTS_INT_MASK);
3032
b8dfc462
ML		 3033 return 0;
3034}
6eb827d2
TI		 3035
3036static int azx_runtime_idle(struct device *dev)
3037{
3038 struct snd_card *card = dev_get_drvdata(dev);
3039 struct azx *chip = card->private_data;
3040
246efa4a
DA		 3041 if (chip->disabled)
3042 return 0;
3043
6eb827d2
TI		 3044 if (!power_save_controller ||
3045 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3046 return -EBUSY;
3047
3048 return 0;
3049}
3050
b8dfc462
ML		 3051#endif /* CONFIG_PM_RUNTIME */
3052
3053#ifdef CONFIG_PM
3054static const struct dev_pm_ops azx_pm = {
3055 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 3056 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 3057};
3058
68cb2b55
TI		 3059#define AZX_PM_OPS &azx_pm
3060#else
68cb2b55 3061#define AZX_PM_OPS NULL
b8dfc462 3062#endif /* CONFIG_PM */
1da177e4
LT		 3063
3064
0cbf0098
TI		 3065/*
3066 * reboot notifier for hang-up problem at power-down
3067 */
3068static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3069{
3070 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 3071 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 3072 azx_stop_chip(chip);
3073 return NOTIFY_OK;
3074}
3075
3076static void azx_notifier_register(struct azx *chip)
3077{
3078 chip->reboot_notifier.notifier_call = azx_halt;
3079 register_reboot_notifier(&chip->reboot_notifier);
3080}
3081
3082static void azx_notifier_unregister(struct azx *chip)
3083{
3084 if (chip->reboot_notifier.notifier_call)
3085 unregister_reboot_notifier(&chip->reboot_notifier);
3086}
3087
48c8b0eb 3088static int azx_probe_continue(struct azx *chip);
a82d51ed 3089
8393ec4a 3090#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 3091static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 3092
a82d51ed
TI		 3093static void azx_vs_set_state(struct pci_dev *pci,
3094 enum vga_switcheroo_state state)
3095{
3096 struct snd_card *card = pci_get_drvdata(pci);
3097 struct azx *chip = card->private_data;
3098 bool disabled;
3099
f4c482a4 3100 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 3101 if (chip->init_failed)
3102 return;
3103
3104 disabled = (state == VGA_SWITCHEROO_OFF);
3105 if (chip->disabled == disabled)
3106 return;
3107
3108 if (!chip->bus) {
3109 chip->disabled = disabled;
3110 if (!disabled) {
3111 snd_printk(KERN_INFO SFX
3112 "%s: Start delayed initialization\n",
3113 pci_name(chip->pci));
5c90680e 3114 if (azx_probe_continue(chip) < 0) {
a82d51ed
TI		 3115 snd_printk(KERN_ERR SFX
3116 "%s: initialization error\n",
3117 pci_name(chip->pci));
3118 chip->init_failed = true;
3119 }
3120 }
3121 } else {
3122 snd_printk(KERN_INFO SFX
445a51b3
DB		 3123 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3124 disabled ? "Disabling" : "Enabling");
a82d51ed 3125 if (disabled) {
246efa4a 3126 pm_runtime_put_sync_suspend(&pci->dev);
68cb2b55 3127 azx_suspend(&pci->dev);
246efa4a
DA		 3128 /* when we get suspended by vga switcheroo we end up in D3cold,
3129 * however we have no ACPI handle, so pci/acpi can't put us there,
3130 * put ourselves there */
3131 pci->current_state = PCI_D3cold;
a82d51ed 3132 chip->disabled = true;
128960a9 3133 if (snd_hda_lock_devices(chip->bus))
445a51b3
DB		 3134 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3135 pci_name(chip->pci));
a82d51ed
TI		 3136 } else {
3137 snd_hda_unlock_devices(chip->bus);
246efa4a 3138 pm_runtime_get_noresume(&pci->dev);
a82d51ed 3139 chip->disabled = false;
68cb2b55 3140 azx_resume(&pci->dev);
a82d51ed
TI		 3141 }
3142 }
3143}
3144
3145static bool azx_vs_can_switch(struct pci_dev *pci)
3146{
3147 struct snd_card *card = pci_get_drvdata(pci);
3148 struct azx *chip = card->private_data;
3149
f4c482a4 3150 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 3151 if (chip->init_failed)
3152 return false;
3153 if (chip->disabled || !chip->bus)
3154 return true;
3155 if (snd_hda_lock_devices(chip->bus))
3156 return false;
3157 snd_hda_unlock_devices(chip->bus);
3158 return true;
3159}
3160
e23e7a14 3161static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 3162{
3163 struct pci_dev *p = get_bound_vga(chip->pci);
3164 if (p) {
3165 snd_printk(KERN_INFO SFX
3166 "%s: Handle VGA-switcheroo audio client\n",
3167 pci_name(chip->pci));
3168 chip->use_vga_switcheroo = 1;
3169 pci_dev_put(p);
3170 }
3171}
3172
3173static const struct vga_switcheroo_client_ops azx_vs_ops = {
3174 .set_gpu_state = azx_vs_set_state,
3175 .can_switch = azx_vs_can_switch,
3176};
3177
e23e7a14 3178static int register_vga_switcheroo(struct azx *chip)
a82d51ed 3179{
128960a9
TI		 3180 int err;
3181
a82d51ed
TI		 3182 if (!chip->use_vga_switcheroo)
3183 return 0;
3184 /* FIXME: currently only handling DIS controller
3185 * is there any machine with two switchable HDMI audio controllers?
3186 */
128960a9 3187 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 3188 VGA_SWITCHEROO_DIS,
3189 chip->bus != NULL);
128960a9
TI		 3190 if (err < 0)
3191 return err;
3192 chip->vga_switcheroo_registered = 1;
246efa4a
DA		 3193
3194 /* register as an optimus hdmi audio power domain */
3195 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(&chip->pci->dev, &chip->hdmi_pm_domain);
128960a9 3196 return 0;
a82d51ed
TI		 3197}
3198#else
3199#define init_vga_switcheroo(chip) /* NOP */
3200#define register_vga_switcheroo(chip) 0
8393ec4a 3201#define check_hdmi_disabled(pci) false
a82d51ed
TI		 3202#endif /* SUPPORT_VGA_SWITCHER */
3203
1da177e4
LT		 3204/*
3205 * destructor
3206 */
a98f90fd 3207static int azx_free(struct azx *chip)
1da177e4 3208{
c67e2228 3209 struct pci_dev *pci = chip->pci;
4ce107b9
TI		 3210 int i;
3211
c67e2228
WX		 3212 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
3213 && chip->running)
3214 pm_runtime_get_noresume(&pci->dev);
3215
65fcd41d
TI		 3216 azx_del_card_list(chip);
3217
0cbf0098
TI		 3218 azx_notifier_unregister(chip);
3219
f4c482a4 3220 chip->init_failed = 1; /* to be sure */
44728e97 3221 complete_all(&chip->probe_wait);
f4c482a4 3222
a82d51ed
TI		 3223 if (use_vga_switcheroo(chip)) {
3224 if (chip->disabled && chip->bus)
3225 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 3226 if (chip->vga_switcheroo_registered)
3227 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 3228 }
3229
ce43fbae 3230 if (chip->initialized) {
9ad593f6 3231 azx_clear_irq_pending(chip);
07e4ca50 3232 for (i = 0; i < chip->num_streams; i++)
1da177e4 3233 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 3234 azx_stop_chip(chip);
1da177e4
LT		 3235 }
3236
f000fd80 3237 if (chip->irq >= 0)
1da177e4 3238 free_irq(chip->irq, (void*)chip);
68e7fffc 3239 if (chip->msi)
30b35399 3240 pci_disable_msi(chip->pci);
f079c25a
TI		 3241 if (chip->remap_addr)
3242 iounmap(chip->remap_addr);
1da177e4 3243
4ce107b9
TI		 3244 if (chip->azx_dev) {
3245 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 3246 if (chip->azx_dev[i].bdl.area) {
3247 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 3248 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 3249 }
4ce107b9 3250 }
27fe48d9
TI		 3251 if (chip->rb.area) {
3252 mark_pages_wc(chip, &chip->rb, false);
1da177e4 3253 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 3254 }
3255 if (chip->posbuf.area) {
3256 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 3257 snd_dma_free_pages(&chip->posbuf);
27fe48d9 3258 }
a82d51ed
TI		 3259 if (chip->region_requested)
3260 pci_release_regions(chip->pci);
1da177e4 3261 pci_disable_device(chip->pci);
07e4ca50 3262 kfree(chip->azx_dev);
4918cdab
TI		 3263#ifdef CONFIG_SND_HDA_PATCH_LOADER
3264 if (chip->fw)
3265 release_firmware(chip->fw);
3266#endif
99a2008d
WX		 3267 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3268 hda_display_power(false);
3269 hda_i915_exit();
3270 }
1da177e4
LT		 3271 kfree(chip);
3272
3273 return 0;
3274}
3275
a98f90fd 3276static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 3277{
3278 return azx_free(device->device_data);
3279}
3280
8393ec4a 3281#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 3282/*
3283 * Check of disabled HDMI controller by vga-switcheroo
3284 */
e23e7a14 3285static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 3286{
3287 struct pci_dev *p;
3288
3289 /* check only discrete GPU */
3290 switch (pci->vendor) {
3291 case PCI_VENDOR_ID_ATI:
3292 case PCI_VENDOR_ID_AMD:
3293 case PCI_VENDOR_ID_NVIDIA:
3294 if (pci->devfn == 1) {
3295 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3296 pci->bus->number, 0);
3297 if (p) {
3298 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3299 return p;
3300 pci_dev_put(p);
3301 }
3302 }
3303 break;
3304 }
3305 return NULL;
3306}
3307
e23e7a14 3308static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 3309{
3310 bool vga_inactive = false;
3311 struct pci_dev *p = get_bound_vga(pci);
3312
3313 if (p) {
12b78a7f 3314 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 3315 vga_inactive = true;
3316 pci_dev_put(p);
3317 }
3318 return vga_inactive;
3319}
8393ec4a 3320#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 3321
3372a153
TI		 3322/*
3323 * white/black-listing for position_fix
3324 */
e23e7a14 3325static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 3326 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3327 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 3328 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 3329 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 3330 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 3331 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 3332 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 3333 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 3334 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 3335 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 3336 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 3337 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 3338 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 3339 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 3340 {}
3341};
3342
e23e7a14 3343static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 3344{
3345 const struct snd_pci_quirk *q;
3346
c673ba1c 3347 switch (fix) {
1dac6695 3348 case POS_FIX_AUTO:
c673ba1c
TI		 3349 case POS_FIX_LPIB:
3350 case POS_FIX_POSBUF:
4cb36310 3351 case POS_FIX_VIACOMBO:
a6f2fd55 3352 case POS_FIX_COMBO:
c673ba1c
TI		 3353 return fix;
3354 }
3355
c673ba1c
TI		 3356 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3357 if (q) {
3358 printk(KERN_INFO
3359 "hda_intel: position_fix set to %d "
3360 "for device %04x:%04x\n",
3361 q->value, q->subvendor, q->subdevice);
3362 return q->value;
3372a153 3363 }
bdd9ef24
DH		 3364
3365 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 3366 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
445a51b3 3367 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
bdd9ef24 3368 return POS_FIX_VIACOMBO;
9477c58e
TI		 3369 }
3370 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
445a51b3 3371 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
50e3bbf9 3372 return POS_FIX_LPIB;
bdd9ef24 3373 }
c673ba1c 3374 return POS_FIX_AUTO;
3372a153
TI		 3375}
3376
669ba27a
TI		 3377/*
3378 * black-lists for probe_mask
3379 */
e23e7a14 3380static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 3381 /* Thinkpad often breaks the controller communication when accessing
3382 * to the non-working (or non-existing) modem codec slot.
3383 */
3384 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3385 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3386 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 3387 /* broken BIOS */
3388 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 3389 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3390 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 3391 /* forced codec slots */
93574844 3392 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 3393 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 3394 /* WinFast VP200 H (Teradici) user reported broken communication */
3395 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 3396 {}
3397};
3398
f1eaaeec
TI		 3399#define AZX_FORCE_CODEC_MASK 0x100
3400
e23e7a14 3401static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 3402{
3403 const struct snd_pci_quirk *q;
3404
f1eaaeec
TI		 3405 chip->codec_probe_mask = probe_mask[dev];
3406 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 3407 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3408 if (q) {
3409 printk(KERN_INFO
3410 "hda_intel: probe_mask set to 0x%x "
3411 "for device %04x:%04x\n",
3412 q->value, q->subvendor, q->subdevice);
f1eaaeec 3413 chip->codec_probe_mask = q->value;
669ba27a
TI		 3414 }
3415 }
f1eaaeec
TI		 3416
3417 /* check forced option */
3418 if (chip->codec_probe_mask != -1 &&
3419 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3420 chip->codec_mask = chip->codec_probe_mask & 0xff;
3421 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3422 chip->codec_mask);
3423 }
669ba27a
TI		 3424}
3425
4d8e22e0 3426/*
71623855 3427 * white/black-list for enable_msi
4d8e22e0 3428 */
e23e7a14 3429static struct snd_pci_quirk msi_black_list[] = {
9dc8398b 3430 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 3431 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 3432 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 3433 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 3434 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 3435 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 3436 {}
3437};
3438
e23e7a14 3439static void check_msi(struct azx *chip)
4d8e22e0
TI		 3440{
3441 const struct snd_pci_quirk *q;
3442
71623855
TI		 3443 if (enable_msi >= 0) {
3444 chip->msi = !!enable_msi;
4d8e22e0 3445 return;
71623855
TI		 3446 }
3447 chip->msi = 1; /* enable MSI as default */
3448 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 3449 if (q) {
3450 printk(KERN_INFO
3451 "hda_intel: msi for device %04x:%04x set to %d\n",
3452 q->subvendor, q->subdevice, q->value);
3453 chip->msi = q->value;
80c43ed7
TI		 3454 return;
3455 }
3456
3457 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 3458 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3459 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 3460 chip->msi = 0;
4d8e22e0
TI		 3461 }
3462}
3463
a1585d76 3464/* check the snoop mode availability */
e23e7a14 3465static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 3466{
3467 bool snoop = chip->snoop;
3468
3469 switch (chip->driver_type) {
3470 case AZX_DRIVER_VIA:
3471 /* force to non-snoop mode for a new VIA controller
3472 * when BIOS is set
3473 */
3474 if (snoop) {
3475 u8 val;
3476 pci_read_config_byte(chip->pci, 0x42, &val);
3477 if (!(val & 0x80) && chip->pci->revision == 0x30)
3478 snoop = false;
3479 }
3480 break;
3481 case AZX_DRIVER_ATIHDMI_NS:
3482 /* new ATI HDMI requires non-snoop */
3483 snoop = false;
3484 break;
c1279f87
TI		 3485 case AZX_DRIVER_CTHDA:
3486 snoop = false;
3487 break;
a1585d76
TI		 3488 }
3489
3490 if (snoop != chip->snoop) {
445a51b3
DB		 3491 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3492 pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
a1585d76
TI		 3493 chip->snoop = snoop;
3494 }
3495}
669ba27a 3496
99a2008d
WX		 3497#ifdef CONFIG_SND_HDA_I915
3498static void azx_probe_work(struct work_struct *work)
3499{
3500 azx_probe_continue(container_of(work, struct azx, probe_work));
3501}
3502#endif
3503
1da177e4
LT		 3504/*
3505 * constructor
3506 */
e23e7a14
BP		 3507static int azx_create(struct snd_card *card, struct pci_dev *pci,
3508 int dev, unsigned int driver_caps,
3509 struct azx **rchip)
1da177e4 3510{
a98f90fd 3511 static struct snd_device_ops ops = {
1da177e4
LT		 3512 .dev_free = azx_dev_free,
3513 };
a82d51ed
TI		 3514 struct azx *chip;
3515 int err;
1da177e4
LT		 3516
3517 *rchip = NULL;
bcd72003 3518
927fc866
PM		 3519 err = pci_enable_device(pci);
3520 if (err < 0)
1da177e4
LT		 3521 return err;
3522
e560d8d8 3523 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 3524 if (!chip) {
445a51b3 3525 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
1da177e4
LT		 3526 pci_disable_device(pci);
3527 return -ENOMEM;
3528 }
3529
3530 spin_lock_init(&chip->reg_lock);
62932df8 3531 mutex_init(&chip->open_mutex);
1da177e4
LT		 3532 chip->card = card;
3533 chip->pci = pci;
3534 chip->irq = -1;
9477c58e
TI		 3535 chip->driver_caps = driver_caps;
3536 chip->driver_type = driver_caps & 0xff;
4d8e22e0 3537 check_msi(chip);
555e219f 3538 chip->dev_index = dev;
9ad593f6 3539 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 3540 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 3541 INIT_LIST_HEAD(&chip->list);
a82d51ed 3542 init_vga_switcheroo(chip);
f4c482a4 3543 init_completion(&chip->probe_wait);
1da177e4 3544
beaffc39
SG		 3545 chip->position_fix[0] = chip->position_fix[1] =
3546 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 3547 /* combo mode uses LPIB for playback */
3548 if (chip->position_fix[0] == POS_FIX_COMBO) {
3549 chip->position_fix[0] = POS_FIX_LPIB;
3550 chip->position_fix[1] = POS_FIX_AUTO;
3551 }
3552
5aba4f8e 3553 check_probe_mask(chip, dev);
3372a153 3554
27346166 3555 chip->single_cmd = single_cmd;
27fe48d9 3556 chip->snoop = hda_snoop;
a1585d76 3557 azx_check_snoop_available(chip);
c74db86b 3558
5c0d7bc1
TI		 3559 if (bdl_pos_adj[dev] < 0) {
3560 switch (chip->driver_type) {
0c6341ac 3561 case AZX_DRIVER_ICH:
32679f95 3562 case AZX_DRIVER_PCH:
0c6341ac 3563 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 3564 break;
3565 default:
0c6341ac 3566 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 3567 break;
3568 }
3569 }
3570
a82d51ed
TI		 3571 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3572 if (err < 0) {
445a51b3
DB		 3573 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3574 pci_name(chip->pci));
a82d51ed
TI		 3575 azx_free(chip);
3576 return err;
3577 }
3578
99a2008d
WX		 3579#ifdef CONFIG_SND_HDA_I915
3580 /* continue probing in work context as may trigger request module */
3581 INIT_WORK(&chip->probe_work, azx_probe_work);
3582#endif
3583
a82d51ed 3584 *rchip = chip;
99a2008d 3585
a82d51ed
TI		 3586 return 0;
3587}
3588
48c8b0eb 3589static int azx_first_init(struct azx *chip)
a82d51ed
TI		 3590{
3591 int dev = chip->dev_index;
3592 struct pci_dev *pci = chip->pci;
3593 struct snd_card *card = chip->card;
3594 int i, err;
3595 unsigned short gcap;
3596
07e4ca50
TI		 3597#if BITS_PER_LONG != 64
3598 /* Fix up base address on ULI M5461 */
3599 if (chip->driver_type == AZX_DRIVER_ULI) {
3600 u16 tmp3;
3601 pci_read_config_word(pci, 0x40, &tmp3);
3602 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3603 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3604 }
3605#endif
3606
927fc866 3607 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 3608 if (err < 0)
1da177e4 3609 return err;
a82d51ed 3610 chip->region_requested = 1;
1da177e4 3611
927fc866 3612 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 3613 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 3614 if (chip->remap_addr == NULL) {
445a51b3 3615 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
a82d51ed 3616 return -ENXIO;
1da177e4
LT		 3617 }
3618
68e7fffc
TI		 3619 if (chip->msi)
3620 if (pci_enable_msi(pci) < 0)
3621 chip->msi = 0;
7376d013 3622
a82d51ed
TI		 3623 if (azx_acquire_irq(chip, 0) < 0)
3624 return -EBUSY;
1da177e4
LT		 3625
3626 pci_set_master(pci);
3627 synchronize_irq(chip->irq);
3628
bcd72003 3629 gcap = azx_readw(chip, GCAP);
445a51b3 3630 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
bcd72003 3631
dc4c2e6b 3632 /* disable SB600 64bit support for safety */
9477c58e 3633 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3634 struct pci_dev *p_smbus;
3635 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3636 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3637 NULL);
3638 if (p_smbus) {
3639 if (p_smbus->revision < 0x30)
3640 gcap &= ~ICH6_GCAP_64OK;
3641 pci_dev_put(p_smbus);
3642 }
3643 }
09240cf4 3644
9477c58e
TI		 3645 /* disable 64bit DMA address on some devices */
3646 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
445a51b3 3647 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
396087ea 3648 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3649 }
396087ea 3650
2ae66c26 3651 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3652 if (align_buffer_size >= 0)
3653 chip->align_buffer_size = !!align_buffer_size;
3654 else {
3655 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3656 chip->align_buffer_size = 0;
3657 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3658 chip->align_buffer_size = 1;
3659 else
3660 chip->align_buffer_size = 1;
3661 }
2ae66c26 3662
cf7aaca8 3663 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3664 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3665 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3666 else {
e930438c
YH		 3667 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3668 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3669 }
cf7aaca8 3670
8b6ed8e7
TI		 3671 /* read number of streams from GCAP register instead of using
3672 * hardcoded value
3673 */
3674 chip->capture_streams = (gcap >> 8) & 0x0f;
3675 chip->playback_streams = (gcap >> 12) & 0x0f;
3676 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3677 /* gcap didn't give any info, switching to old method */
3678
3679 switch (chip->driver_type) {
3680 case AZX_DRIVER_ULI:
3681 chip->playback_streams = ULI_NUM_PLAYBACK;
3682 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3683 break;
3684 case AZX_DRIVER_ATIHDMI:
1815b34a 3685 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3686 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3687 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3688 break;
c4da29ca 3689 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3690 default:
3691 chip->playback_streams = ICH6_NUM_PLAYBACK;
3692 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3693 break;
3694 }
07e4ca50 3695 }
8b6ed8e7
TI		 3696 chip->capture_index_offset = 0;
3697 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3698 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3699 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3700 GFP_KERNEL);
927fc866 3701 if (!chip->azx_dev) {
445a51b3 3702 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
a82d51ed 3703 return -ENOMEM;
07e4ca50
TI		 3704 }
3705
4ce107b9 3706 for (i = 0; i < chip->num_streams; i++) {
eb49faa6 3707 dsp_lock_init(&chip->azx_dev[i]);
4ce107b9
TI		 3708 /* allocate memory for the BDL for each stream */
3709 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3710 snd_dma_pci_data(chip->pci),
3711 BDL_SIZE, &chip->azx_dev[i].bdl);
3712 if (err < 0) {
445a51b3 3713 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
a82d51ed 3714 return -ENOMEM;
4ce107b9 3715 }
27fe48d9 3716 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3717 }
0be3b5d3 3718 /* allocate memory for the position buffer */
d01ce99f
TI		 3719 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3720 snd_dma_pci_data(chip->pci),
3721 chip->num_streams * 8, &chip->posbuf);
3722 if (err < 0) {
445a51b3 3723 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
a82d51ed 3724 return -ENOMEM;
1da177e4 3725 }
27fe48d9 3726 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3727 /* allocate CORB/RIRB */
81740861
TI		 3728 err = azx_alloc_cmd_io(chip);
3729 if (err < 0)
a82d51ed 3730 return err;
1da177e4
LT		 3731
3732 /* initialize streams */
3733 azx_init_stream(chip);
3734
3735 /* initialize chip */
cb53c626 3736 azx_init_pci(chip);
10e77dda 3737 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3738
3739 /* codec detection */
927fc866 3740 if (!chip->codec_mask) {
445a51b3 3741 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
a82d51ed 3742 return -ENODEV;
1da177e4
LT		 3743 }
3744
07e4ca50 3745 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3746 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3747 sizeof(card->shortname));
3748 snprintf(card->longname, sizeof(card->longname),
3749 "%s at 0x%lx irq %i",
3750 card->shortname, chip->addr, chip->irq);
07e4ca50 3751
1da177e4 3752 return 0;
1da177e4
LT		 3753}
3754
cb53c626
TI		 3755static void power_down_all_codecs(struct azx *chip)
3756{
83012a7c 3757#ifdef CONFIG_PM
cb53c626
TI		 3758 /* The codecs were powered up in snd_hda_codec_new().
3759 * Now all initialization done, so turn them down if possible
3760 */
3761 struct hda_codec *codec;
3762 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3763 snd_hda_power_down(codec);
3764 }
3765#endif
3766}
3767
97c6a3d1 3768#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 3769/* callback from request_firmware_nowait() */
3770static void azx_firmware_cb(const struct firmware *fw, void *context)
3771{
3772 struct snd_card *card = context;
3773 struct azx *chip = card->private_data;
3774 struct pci_dev *pci = chip->pci;
3775
3776 if (!fw) {
445a51b3
DB		 3777 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3778 pci_name(chip->pci));
5cb543db
TI		 3779 goto error;
3780 }
3781
3782 chip->fw = fw;
3783 if (!chip->disabled) {
3784 /* continue probing */
3785 if (azx_probe_continue(chip))
3786 goto error;
3787 }
3788 return; /* OK */
3789
3790 error:
3791 snd_card_free(card);
3792 pci_set_drvdata(pci, NULL);
3793}
97c6a3d1 3794#endif
5cb543db 3795
e23e7a14
BP		 3796static int azx_probe(struct pci_dev *pci,
3797 const struct pci_device_id *pci_id)
1da177e4 3798{
5aba4f8e 3799 static int dev;
a98f90fd
TI		 3800 struct snd_card *card;
3801 struct azx *chip;
5cb543db 3802 bool probe_now;
927fc866 3803 int err;
1da177e4 3804
5aba4f8e
TI		 3805 if (dev >= SNDRV_CARDS)
3806 return -ENODEV;
3807 if (!enable[dev]) {
3808 dev++;
3809 return -ENOENT;
3810 }
3811
e58de7ba
TI		 3812 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3813 if (err < 0) {
445a51b3 3814 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
e58de7ba 3815 return err;
1da177e4
LT		 3816 }
3817
4ea6fbc8
TI		 3818 snd_card_set_dev(card, &pci->dev);
3819
5aba4f8e 3820 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3821 if (err < 0)
3822 goto out_free;
421a1252 3823 card->private_data = chip;
f4c482a4
TI		 3824
3825 pci_set_drvdata(pci, card);
3826
3827 err = register_vga_switcheroo(chip);
3828 if (err < 0) {
3829 snd_printk(KERN_ERR SFX
445a51b3 3830 "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
f4c482a4
TI		 3831 goto out_free;
3832 }
3833
3834 if (check_hdmi_disabled(pci)) {
445a51b3 3835 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
f4c482a4 3836 pci_name(pci));
445a51b3 3837 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
f4c482a4
TI		 3838 chip->disabled = true;
3839 }
3840
5cb543db 3841 probe_now = !chip->disabled;
1da177e4 3842
4918cdab
TI		 3843#ifdef CONFIG_SND_HDA_PATCH_LOADER
3844 if (patch[dev] && *patch[dev]) {
445a51b3
DB		 3845 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3846 pci_name(pci), patch[dev]);
5cb543db
TI		 3847 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3848 &pci->dev, GFP_KERNEL, card,
3849 azx_firmware_cb);
4918cdab
TI		 3850 if (err < 0)
3851 goto out_free;
5cb543db 3852 probe_now = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 3853 }
3854#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3855
99a2008d
WX		 3856 /* continue probing in work context, avoid request_module deadlock */
3857 if (probe_now && (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)) {
3858#ifdef CONFIG_SND_HDA_I915
3859 probe_now = false;
3860 schedule_work(&chip->probe_work);
3861#else
3862 snd_printk(KERN_ERR SFX "Haswell must build in CONFIG_SND_HDA_I915\n");
3863#endif
3864 }
3865
5cb543db 3866 if (probe_now) {
a82d51ed
TI		 3867 err = azx_probe_continue(chip);
3868 if (err < 0)
3869 goto out_free;
3870 }
3871
a82d51ed 3872 dev++;
44728e97 3873 complete_all(&chip->probe_wait);
a82d51ed
TI		 3874 return 0;
3875
3876out_free:
3877 snd_card_free(card);
3878 return err;
3879}
3880
48c8b0eb 3881static int azx_probe_continue(struct azx *chip)
a82d51ed 3882{
c67e2228 3883 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 3884 int dev = chip->dev_index;
3885 int err;
3886
99a2008d
WX		 3887 /* Request power well for Haswell HDA controller and codec */
3888 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 3889#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 3890 err = hda_i915_init();
3891 if (err < 0) {
3892 snd_printk(KERN_ERR SFX "Error request power-well from i915\n");
3893 goto out_free;
3894 }
c841ad2a 3895#endif
99a2008d
WX		 3896 hda_display_power(true);
3897 }
3898
5c90680e
TI		 3899 err = azx_first_init(chip);
3900 if (err < 0)
3901 goto out_free;
3902
2dca0bba
JK		 3903#ifdef CONFIG_SND_HDA_INPUT_BEEP
3904 chip->beep_mode = beep_mode[dev];
3905#endif
3906
1da177e4 3907 /* create codec instances */
a1e21c90 3908 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3909 if (err < 0)
3910 goto out_free;
4ea6fbc8 3911#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 3912 if (chip->fw) {
3913 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3914 chip->fw->data);
4ea6fbc8
TI		 3915 if (err < 0)
3916 goto out_free;
e39ae856 3917#ifndef CONFIG_PM
4918cdab
TI		 3918 release_firmware(chip->fw); /* no longer needed */
3919 chip->fw = NULL;
e39ae856 3920#endif
4ea6fbc8
TI		 3921 }
3922#endif
10e77dda 3923 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3924 err = azx_codec_configure(chip);
3925 if (err < 0)
3926 goto out_free;
3927 }
1da177e4
LT		 3928
3929 /* create PCM streams */
176d5335 3930 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3931 if (err < 0)
3932 goto out_free;
1da177e4
LT		 3933
3934 /* create mixer controls */
d01ce99f 3935 err = azx_mixer_create(chip);
41dda0fd
WF		 3936 if (err < 0)
3937 goto out_free;
1da177e4 3938
a82d51ed 3939 err = snd_card_register(chip->card);
41dda0fd
WF		 3940 if (err < 0)
3941 goto out_free;
1da177e4 3942
cb53c626
TI		 3943 chip->running = 1;
3944 power_down_all_codecs(chip);
0cbf0098 3945 azx_notifier_register(chip);
65fcd41d 3946 azx_add_card_list(chip);
246efa4a 3947 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
c67e2228 3948 pm_runtime_put_noidle(&pci->dev);
1da177e4 3949
9121947d
TI		 3950 return 0;
3951
41dda0fd 3952out_free:
a82d51ed 3953 chip->init_failed = 1;
41dda0fd 3954 return err;
1da177e4
LT		 3955}
3956
e23e7a14 3957static void azx_remove(struct pci_dev *pci)
1da177e4 3958{
9121947d 3959 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 3960
9121947d
TI		 3961 if (card)
3962 snd_card_free(card);
1da177e4
LT		 3963}
3964
3965/* PCI IDs */
cebe41d4 3966static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3967 /* CPT */
9477c58e 3968 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 3969 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 3970 /* PBG */
9477c58e 3971 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 3972 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 3973 /* Panther Point */
9477c58e 3974 { PCI_DEVICE(0x8086, 0x1e20),
d7dab4db 3975 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 3976 /* Lynx Point */
3977 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 3978 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 3979 /* Wellsburg */
3980 { PCI_DEVICE(0x8086, 0x8d20),
3981 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3982 { PCI_DEVICE(0x8086, 0x8d21),
3983 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3984 /* Lynx Point-LP */
3985 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 3986 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3987 /* Lynx Point-LP */
3988 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 3989 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 3990 /* Wildcat Point-LP */
3991 { PCI_DEVICE(0x8086, 0x9ca0),
3992 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 3993 /* Haswell */
4a7c516b 3994 { PCI_DEVICE(0x8086, 0x0a0c),
99a2008d
WX		 3995 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
3996 AZX_DCAPS_I915_POWERWELL },
e926f2c8 3997 { PCI_DEVICE(0x8086, 0x0c0c),
99a2008d
WX		 3998 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
3999 AZX_DCAPS_I915_POWERWELL },
d279fae8 4000 { PCI_DEVICE(0x8086, 0x0d0c),
99a2008d
WX		 4001 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
4002 AZX_DCAPS_I915_POWERWELL },
99df18b3
PLB		 4003 /* 5 Series/3400 */
4004 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 4005 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 4006 /* Poulsbo */
9477c58e 4007 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 4008 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4009 /* Oaktrail */
09904b95 4010 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 4011 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 4012 /* BayTrail */
4013 { PCI_DEVICE(0x8086, 0x0f04),
4014 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
645e9035 4015 /* ICH */
8b0bd226 4016 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 4017 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4018 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 4019 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 4020 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4021 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 4022 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 4023 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4024 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 4025 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 4026 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4027 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 4028 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 4029 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4030 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 4031 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 4032 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4033 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 4034 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 4035 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4036 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 4037 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 4038 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4039 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 4040 /* Generic Intel */
4041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
4042 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4043 .class_mask = 0xffffff,
2ae66c26 4044 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 4045 /* ATI SB 450/600/700/800/900 */
4046 { PCI_DEVICE(0x1002, 0x437b),
4047 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4048 { PCI_DEVICE(0x1002, 0x4383),
4049 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4050 /* AMD Hudson */
4051 { PCI_DEVICE(0x1022, 0x780d),
4052 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 4053 /* ATI HDMI */
9477c58e
TI		 4054 { PCI_DEVICE(0x1002, 0x793b),
4055 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4056 { PCI_DEVICE(0x1002, 0x7919),
4057 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4058 { PCI_DEVICE(0x1002, 0x960f),
4059 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4060 { PCI_DEVICE(0x1002, 0x970f),
4061 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4062 { PCI_DEVICE(0x1002, 0xaa00),
4063 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4064 { PCI_DEVICE(0x1002, 0xaa08),
4065 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4066 { PCI_DEVICE(0x1002, 0xaa10),
4067 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4068 { PCI_DEVICE(0x1002, 0xaa18),
4069 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4070 { PCI_DEVICE(0x1002, 0xaa20),
4071 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4072 { PCI_DEVICE(0x1002, 0xaa28),
4073 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4074 { PCI_DEVICE(0x1002, 0xaa30),
4075 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4076 { PCI_DEVICE(0x1002, 0xaa38),
4077 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4078 { PCI_DEVICE(0x1002, 0xaa40),
4079 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4080 { PCI_DEVICE(0x1002, 0xaa48),
4081 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 4082 { PCI_DEVICE(0x1002, 0x9902),
4083 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4084 { PCI_DEVICE(0x1002, 0xaaa0),
4085 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4086 { PCI_DEVICE(0x1002, 0xaaa8),
4087 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4088 { PCI_DEVICE(0x1002, 0xaab0),
4089 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 4090 /* VIA VT8251/VT8237A */
9477c58e
TI		 4091 { PCI_DEVICE(0x1106, 0x3288),
4092 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 4093 /* VIA GFX VT7122/VX900 */
4094 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
4095 /* VIA GFX VT6122/VX11 */
4096 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 4097 /* SIS966 */
4098 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
4099 /* ULI M5461 */
4100 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
4101 /* NVIDIA MCP */
0c2fd1bf
TI		 4102 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
4103 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4104 .class_mask = 0xffffff,
9477c58e 4105 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 4106 /* Teradici */
9477c58e
TI		 4107 { PCI_DEVICE(0x6549, 0x1200),
4108 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 4109 { PCI_DEVICE(0x6549, 0x2200),
4110 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 4111 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 4112 /* CTHDA chips */
4113 { PCI_DEVICE(0x1102, 0x0010),
4114 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4115 { PCI_DEVICE(0x1102, 0x0012),
4116 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
313f6e2d
TI		 4117#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
4118 /* the following entry conflicts with snd-ctxfi driver,
4119 * as ctxfi driver mutates from HD-audio to native mode with
4120 * a special command sequence.
4121 */
4e01f54b
TI		 4122 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4123 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4124 .class_mask = 0xffffff,
9477c58e 4125 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 4126 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 4127#else
4128 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 4129 { PCI_DEVICE(0x1102, 0x0009),
4130 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 4131 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 4132#endif
e35d4b11
OS		 4133 /* Vortex86MX */
4134 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 4135 /* VMware HDAudio */
4136 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 4137 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 4138 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4139 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4140 .class_mask = 0xffffff,
9477c58e 4141 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 4142 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4143 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4144 .class_mask = 0xffffff,
9477c58e 4145 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 4146 { 0, }
4147};
4148MODULE_DEVICE_TABLE(pci, azx_ids);
4149
4150/* pci_driver definition */
e9f66d9b 4151static struct pci_driver azx_driver = {
3733e424 4152 .name = KBUILD_MODNAME,
1da177e4
LT		 4153 .id_table = azx_ids,
4154 .probe = azx_probe,
e23e7a14 4155 .remove = azx_remove,
68cb2b55
TI		 4156 .driver = {
4157 .pm = AZX_PM_OPS,
4158 },
1da177e4
LT		 4159};
4160
e9f66d9b 4161module_pci_driver(azx_driver);
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