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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * | |
3 | * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio. | |
4 | * | |
5 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
8 | * PeiSen Hou <pshou@realtek.com.tw> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the Free | |
12 | * Software Foundation; either version 2 of the License, or (at your option) | |
13 | * any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
18 | * more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along with | |
21 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
22 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
23 | * | |
24 | * CONTACTS: | |
25 | * | |
26 | * Matt Jared matt.jared@intel.com | |
27 | * Andy Kopp andy.kopp@intel.com | |
28 | * Dan Kogan dan.d.kogan@intel.com | |
29 | * | |
30 | * CHANGES: | |
31 | * | |
32 | * 2004.12.01 Major rewrite by tiwai, merged the work of pshou | |
33 | * | |
34 | */ | |
35 | ||
36 | #include <sound/driver.h> | |
37 | #include <asm/io.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
362775e2 | 40 | #include <linux/kernel.h> |
1da177e4 LT |
41 | #include <linux/module.h> |
42 | #include <linux/moduleparam.h> | |
43 | #include <linux/init.h> | |
44 | #include <linux/slab.h> | |
45 | #include <linux/pci.h> | |
62932df8 | 46 | #include <linux/mutex.h> |
1da177e4 LT |
47 | #include <sound/core.h> |
48 | #include <sound/initval.h> | |
49 | #include "hda_codec.h" | |
50 | ||
51 | ||
b7fe4622 CL |
52 | static int index = SNDRV_DEFAULT_IDX1; |
53 | static char *id = SNDRV_DEFAULT_STR1; | |
54 | static char *model; | |
55 | static int position_fix; | |
954fa19a | 56 | static int probe_mask = -1; |
27346166 | 57 | static int single_cmd; |
134a11f0 | 58 | static int enable_msi; |
1da177e4 | 59 | |
b7fe4622 | 60 | module_param(index, int, 0444); |
1da177e4 | 61 | MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); |
b7fe4622 | 62 | module_param(id, charp, 0444); |
1da177e4 | 63 | MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); |
b7fe4622 | 64 | module_param(model, charp, 0444); |
1da177e4 | 65 | MODULE_PARM_DESC(model, "Use the given board model."); |
b7fe4622 | 66 | module_param(position_fix, int, 0444); |
0be3b5d3 | 67 | MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size)."); |
606ad75f TI |
68 | module_param(probe_mask, int, 0444); |
69 | MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); | |
27346166 TI |
70 | module_param(single_cmd, bool, 0444); |
71 | MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs (for debugging only)."); | |
134a11f0 TI |
72 | module_param(enable_msi, int, 0); |
73 | MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); | |
606ad75f | 74 | |
1da177e4 | 75 | |
2b3e584b TI |
76 | /* just for backward compatibility */ |
77 | static int enable; | |
698444f3 | 78 | module_param(enable, bool, 0444); |
2b3e584b | 79 | |
1da177e4 LT |
80 | MODULE_LICENSE("GPL"); |
81 | MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," | |
82 | "{Intel, ICH6M}," | |
2f1b3818 | 83 | "{Intel, ICH7}," |
f5d40b30 | 84 | "{Intel, ESB2}," |
d2981393 | 85 | "{Intel, ICH8}," |
f9cc8a8b | 86 | "{Intel, ICH9}," |
fc20a562 | 87 | "{ATI, SB450}," |
89be83f8 | 88 | "{ATI, SB600}," |
778b6e1b | 89 | "{ATI, RS600}," |
5b15c95f | 90 | "{ATI, RS690}," |
fc20a562 | 91 | "{VIA, VT8251}," |
47672310 | 92 | "{VIA, VT8237A}," |
07e4ca50 TI |
93 | "{SiS, SIS966}," |
94 | "{ULI, M5461}}"); | |
1da177e4 LT |
95 | MODULE_DESCRIPTION("Intel HDA driver"); |
96 | ||
97 | #define SFX "hda-intel: " | |
98 | ||
99 | /* | |
100 | * registers | |
101 | */ | |
102 | #define ICH6_REG_GCAP 0x00 | |
103 | #define ICH6_REG_VMIN 0x02 | |
104 | #define ICH6_REG_VMAJ 0x03 | |
105 | #define ICH6_REG_OUTPAY 0x04 | |
106 | #define ICH6_REG_INPAY 0x06 | |
107 | #define ICH6_REG_GCTL 0x08 | |
108 | #define ICH6_REG_WAKEEN 0x0c | |
109 | #define ICH6_REG_STATESTS 0x0e | |
110 | #define ICH6_REG_GSTS 0x10 | |
111 | #define ICH6_REG_INTCTL 0x20 | |
112 | #define ICH6_REG_INTSTS 0x24 | |
113 | #define ICH6_REG_WALCLK 0x30 | |
114 | #define ICH6_REG_SYNC 0x34 | |
115 | #define ICH6_REG_CORBLBASE 0x40 | |
116 | #define ICH6_REG_CORBUBASE 0x44 | |
117 | #define ICH6_REG_CORBWP 0x48 | |
118 | #define ICH6_REG_CORBRP 0x4A | |
119 | #define ICH6_REG_CORBCTL 0x4c | |
120 | #define ICH6_REG_CORBSTS 0x4d | |
121 | #define ICH6_REG_CORBSIZE 0x4e | |
122 | ||
123 | #define ICH6_REG_RIRBLBASE 0x50 | |
124 | #define ICH6_REG_RIRBUBASE 0x54 | |
125 | #define ICH6_REG_RIRBWP 0x58 | |
126 | #define ICH6_REG_RINTCNT 0x5a | |
127 | #define ICH6_REG_RIRBCTL 0x5c | |
128 | #define ICH6_REG_RIRBSTS 0x5d | |
129 | #define ICH6_REG_RIRBSIZE 0x5e | |
130 | ||
131 | #define ICH6_REG_IC 0x60 | |
132 | #define ICH6_REG_IR 0x64 | |
133 | #define ICH6_REG_IRS 0x68 | |
134 | #define ICH6_IRS_VALID (1<<1) | |
135 | #define ICH6_IRS_BUSY (1<<0) | |
136 | ||
137 | #define ICH6_REG_DPLBASE 0x70 | |
138 | #define ICH6_REG_DPUBASE 0x74 | |
139 | #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ | |
140 | ||
141 | /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ | |
142 | enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; | |
143 | ||
144 | /* stream register offsets from stream base */ | |
145 | #define ICH6_REG_SD_CTL 0x00 | |
146 | #define ICH6_REG_SD_STS 0x03 | |
147 | #define ICH6_REG_SD_LPIB 0x04 | |
148 | #define ICH6_REG_SD_CBL 0x08 | |
149 | #define ICH6_REG_SD_LVI 0x0c | |
150 | #define ICH6_REG_SD_FIFOW 0x0e | |
151 | #define ICH6_REG_SD_FIFOSIZE 0x10 | |
152 | #define ICH6_REG_SD_FORMAT 0x12 | |
153 | #define ICH6_REG_SD_BDLPL 0x18 | |
154 | #define ICH6_REG_SD_BDLPU 0x1c | |
155 | ||
156 | /* PCI space */ | |
157 | #define ICH6_PCIREG_TCSEL 0x44 | |
158 | ||
159 | /* | |
160 | * other constants | |
161 | */ | |
162 | ||
163 | /* max number of SDs */ | |
07e4ca50 TI |
164 | /* ICH, ATI and VIA have 4 playback and 4 capture */ |
165 | #define ICH6_CAPTURE_INDEX 0 | |
166 | #define ICH6_NUM_CAPTURE 4 | |
167 | #define ICH6_PLAYBACK_INDEX 4 | |
168 | #define ICH6_NUM_PLAYBACK 4 | |
169 | ||
170 | /* ULI has 6 playback and 5 capture */ | |
171 | #define ULI_CAPTURE_INDEX 0 | |
172 | #define ULI_NUM_CAPTURE 5 | |
173 | #define ULI_PLAYBACK_INDEX 5 | |
174 | #define ULI_NUM_PLAYBACK 6 | |
175 | ||
778b6e1b FK |
176 | /* ATI HDMI has 1 playback and 0 capture */ |
177 | #define ATIHDMI_CAPTURE_INDEX 0 | |
178 | #define ATIHDMI_NUM_CAPTURE 0 | |
179 | #define ATIHDMI_PLAYBACK_INDEX 0 | |
180 | #define ATIHDMI_NUM_PLAYBACK 1 | |
181 | ||
07e4ca50 TI |
182 | /* this number is statically defined for simplicity */ |
183 | #define MAX_AZX_DEV 16 | |
184 | ||
1da177e4 | 185 | /* max number of fragments - we may use more if allocating more pages for BDL */ |
07e4ca50 TI |
186 | #define BDL_SIZE PAGE_ALIGN(8192) |
187 | #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16)) | |
1da177e4 LT |
188 | /* max buffer size - no h/w limit, you can increase as you like */ |
189 | #define AZX_MAX_BUF_SIZE (1024*1024*1024) | |
190 | /* max number of PCM devics per card */ | |
ec9e1c5c TI |
191 | #define AZX_MAX_AUDIO_PCMS 6 |
192 | #define AZX_MAX_MODEM_PCMS 2 | |
193 | #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS) | |
1da177e4 LT |
194 | |
195 | /* RIRB int mask: overrun[2], response[0] */ | |
196 | #define RIRB_INT_RESPONSE 0x01 | |
197 | #define RIRB_INT_OVERRUN 0x04 | |
198 | #define RIRB_INT_MASK 0x05 | |
199 | ||
200 | /* STATESTS int mask: SD2,SD1,SD0 */ | |
201 | #define STATESTS_INT_MASK 0x07 | |
1da177e4 LT |
202 | |
203 | /* SD_CTL bits */ | |
204 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ | |
205 | #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ | |
206 | #define SD_CTL_STREAM_TAG_MASK (0xf << 20) | |
207 | #define SD_CTL_STREAM_TAG_SHIFT 20 | |
208 | ||
209 | /* SD_CTL and SD_STS */ | |
210 | #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ | |
211 | #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ | |
212 | #define SD_INT_COMPLETE 0x04 /* completion interrupt */ | |
213 | #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE) | |
214 | ||
215 | /* SD_STS */ | |
216 | #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ | |
217 | ||
218 | /* INTCTL and INTSTS */ | |
219 | #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ | |
220 | #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ | |
221 | #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ | |
222 | ||
41e2fce4 M |
223 | /* GCTL unsolicited response enable bit */ |
224 | #define ICH6_GCTL_UREN (1<<8) | |
225 | ||
1da177e4 LT |
226 | /* GCTL reset bit */ |
227 | #define ICH6_GCTL_RESET (1<<0) | |
228 | ||
229 | /* CORB/RIRB control, read/write pointer */ | |
230 | #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */ | |
231 | #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */ | |
232 | #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */ | |
233 | /* below are so far hardcoded - should read registers in future */ | |
234 | #define ICH6_MAX_CORB_ENTRIES 256 | |
235 | #define ICH6_MAX_RIRB_ENTRIES 256 | |
236 | ||
c74db86b TI |
237 | /* position fix mode */ |
238 | enum { | |
0be3b5d3 | 239 | POS_FIX_AUTO, |
c74db86b | 240 | POS_FIX_NONE, |
0be3b5d3 TI |
241 | POS_FIX_POSBUF, |
242 | POS_FIX_FIFO, | |
c74db86b | 243 | }; |
1da177e4 | 244 | |
f5d40b30 | 245 | /* Defines for ATI HD Audio support in SB450 south bridge */ |
f5d40b30 FL |
246 | #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 |
247 | #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 | |
248 | ||
da3fca21 V |
249 | /* Defines for Nvidia HDA support */ |
250 | #define NVIDIA_HDA_TRANSREG_ADDR 0x4e | |
251 | #define NVIDIA_HDA_ENABLE_COHBITS 0x0f | |
f5d40b30 | 252 | |
1da177e4 LT |
253 | /* |
254 | */ | |
255 | ||
a98f90fd | 256 | struct azx_dev { |
1da177e4 LT |
257 | u32 *bdl; /* virtual address of the BDL */ |
258 | dma_addr_t bdl_addr; /* physical address of the BDL */ | |
929861c6 | 259 | u32 *posbuf; /* position buffer pointer */ |
1da177e4 LT |
260 | |
261 | unsigned int bufsize; /* size of the play buffer in bytes */ | |
262 | unsigned int fragsize; /* size of each period in bytes */ | |
263 | unsigned int frags; /* number for period in the play buffer */ | |
264 | unsigned int fifo_size; /* FIFO size */ | |
265 | ||
266 | void __iomem *sd_addr; /* stream descriptor pointer */ | |
267 | ||
268 | u32 sd_int_sta_mask; /* stream int status mask */ | |
269 | ||
270 | /* pcm support */ | |
a98f90fd | 271 | struct snd_pcm_substream *substream; /* assigned substream, set in PCM open */ |
1da177e4 LT |
272 | unsigned int format_val; /* format value to be set in the controller and the codec */ |
273 | unsigned char stream_tag; /* assigned stream */ | |
274 | unsigned char index; /* stream index */ | |
1a56f8d6 TI |
275 | /* for sanity check of position buffer */ |
276 | unsigned int period_intr; | |
1da177e4 | 277 | |
927fc866 PM |
278 | unsigned int opened :1; |
279 | unsigned int running :1; | |
1da177e4 LT |
280 | }; |
281 | ||
282 | /* CORB/RIRB */ | |
a98f90fd | 283 | struct azx_rb { |
1da177e4 LT |
284 | u32 *buf; /* CORB/RIRB buffer |
285 | * Each CORB entry is 4byte, RIRB is 8byte | |
286 | */ | |
287 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | |
288 | /* for RIRB */ | |
289 | unsigned short rp, wp; /* read/write pointers */ | |
290 | int cmds; /* number of pending requests */ | |
291 | u32 res; /* last read value */ | |
292 | }; | |
293 | ||
a98f90fd TI |
294 | struct azx { |
295 | struct snd_card *card; | |
1da177e4 LT |
296 | struct pci_dev *pci; |
297 | ||
07e4ca50 TI |
298 | /* chip type specific */ |
299 | int driver_type; | |
300 | int playback_streams; | |
301 | int playback_index_offset; | |
302 | int capture_streams; | |
303 | int capture_index_offset; | |
304 | int num_streams; | |
305 | ||
1da177e4 LT |
306 | /* pci resources */ |
307 | unsigned long addr; | |
308 | void __iomem *remap_addr; | |
309 | int irq; | |
310 | ||
311 | /* locks */ | |
312 | spinlock_t reg_lock; | |
62932df8 | 313 | struct mutex open_mutex; |
1da177e4 | 314 | |
07e4ca50 | 315 | /* streams (x num_streams) */ |
a98f90fd | 316 | struct azx_dev *azx_dev; |
1da177e4 LT |
317 | |
318 | /* PCM */ | |
319 | unsigned int pcm_devs; | |
a98f90fd | 320 | struct snd_pcm *pcm[AZX_MAX_PCMS]; |
1da177e4 LT |
321 | |
322 | /* HD codec */ | |
323 | unsigned short codec_mask; | |
324 | struct hda_bus *bus; | |
325 | ||
326 | /* CORB/RIRB */ | |
a98f90fd TI |
327 | struct azx_rb corb; |
328 | struct azx_rb rirb; | |
1da177e4 LT |
329 | |
330 | /* BDL, CORB/RIRB and position buffers */ | |
331 | struct snd_dma_buffer bdl; | |
332 | struct snd_dma_buffer rb; | |
333 | struct snd_dma_buffer posbuf; | |
c74db86b TI |
334 | |
335 | /* flags */ | |
336 | int position_fix; | |
927fc866 PM |
337 | unsigned int initialized :1; |
338 | unsigned int single_cmd :1; | |
339 | unsigned int polling_mode :1; | |
68e7fffc | 340 | unsigned int msi :1; |
1da177e4 LT |
341 | }; |
342 | ||
07e4ca50 TI |
343 | /* driver types */ |
344 | enum { | |
345 | AZX_DRIVER_ICH, | |
346 | AZX_DRIVER_ATI, | |
778b6e1b | 347 | AZX_DRIVER_ATIHDMI, |
07e4ca50 TI |
348 | AZX_DRIVER_VIA, |
349 | AZX_DRIVER_SIS, | |
350 | AZX_DRIVER_ULI, | |
da3fca21 | 351 | AZX_DRIVER_NVIDIA, |
07e4ca50 TI |
352 | }; |
353 | ||
354 | static char *driver_short_names[] __devinitdata = { | |
355 | [AZX_DRIVER_ICH] = "HDA Intel", | |
356 | [AZX_DRIVER_ATI] = "HDA ATI SB", | |
778b6e1b | 357 | [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", |
07e4ca50 TI |
358 | [AZX_DRIVER_VIA] = "HDA VIA VT82xx", |
359 | [AZX_DRIVER_SIS] = "HDA SIS966", | |
da3fca21 V |
360 | [AZX_DRIVER_ULI] = "HDA ULI M5461", |
361 | [AZX_DRIVER_NVIDIA] = "HDA NVidia", | |
07e4ca50 TI |
362 | }; |
363 | ||
1da177e4 LT |
364 | /* |
365 | * macros for easy use | |
366 | */ | |
367 | #define azx_writel(chip,reg,value) \ | |
368 | writel(value, (chip)->remap_addr + ICH6_REG_##reg) | |
369 | #define azx_readl(chip,reg) \ | |
370 | readl((chip)->remap_addr + ICH6_REG_##reg) | |
371 | #define azx_writew(chip,reg,value) \ | |
372 | writew(value, (chip)->remap_addr + ICH6_REG_##reg) | |
373 | #define azx_readw(chip,reg) \ | |
374 | readw((chip)->remap_addr + ICH6_REG_##reg) | |
375 | #define azx_writeb(chip,reg,value) \ | |
376 | writeb(value, (chip)->remap_addr + ICH6_REG_##reg) | |
377 | #define azx_readb(chip,reg) \ | |
378 | readb((chip)->remap_addr + ICH6_REG_##reg) | |
379 | ||
380 | #define azx_sd_writel(dev,reg,value) \ | |
381 | writel(value, (dev)->sd_addr + ICH6_REG_##reg) | |
382 | #define azx_sd_readl(dev,reg) \ | |
383 | readl((dev)->sd_addr + ICH6_REG_##reg) | |
384 | #define azx_sd_writew(dev,reg,value) \ | |
385 | writew(value, (dev)->sd_addr + ICH6_REG_##reg) | |
386 | #define azx_sd_readw(dev,reg) \ | |
387 | readw((dev)->sd_addr + ICH6_REG_##reg) | |
388 | #define azx_sd_writeb(dev,reg,value) \ | |
389 | writeb(value, (dev)->sd_addr + ICH6_REG_##reg) | |
390 | #define azx_sd_readb(dev,reg) \ | |
391 | readb((dev)->sd_addr + ICH6_REG_##reg) | |
392 | ||
393 | /* for pcm support */ | |
a98f90fd | 394 | #define get_azx_dev(substream) (substream->runtime->private_data) |
1da177e4 LT |
395 | |
396 | /* Get the upper 32bit of the given dma_addr_t | |
397 | * Compiler should optimize and eliminate the code if dma_addr_t is 32bit | |
398 | */ | |
399 | #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0) | |
400 | ||
68e7fffc | 401 | static int azx_acquire_irq(struct azx *chip, int do_disconnect); |
1da177e4 LT |
402 | |
403 | /* | |
404 | * Interface for HD codec | |
405 | */ | |
406 | ||
1da177e4 LT |
407 | /* |
408 | * CORB / RIRB interface | |
409 | */ | |
a98f90fd | 410 | static int azx_alloc_cmd_io(struct azx *chip) |
1da177e4 LT |
411 | { |
412 | int err; | |
413 | ||
414 | /* single page (at least 4096 bytes) must suffice for both ringbuffes */ | |
415 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
416 | PAGE_SIZE, &chip->rb); | |
417 | if (err < 0) { | |
418 | snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n"); | |
419 | return err; | |
420 | } | |
421 | return 0; | |
422 | } | |
423 | ||
a98f90fd | 424 | static void azx_init_cmd_io(struct azx *chip) |
1da177e4 LT |
425 | { |
426 | /* CORB set up */ | |
427 | chip->corb.addr = chip->rb.addr; | |
428 | chip->corb.buf = (u32 *)chip->rb.area; | |
429 | azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); | |
430 | azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr)); | |
431 | ||
07e4ca50 TI |
432 | /* set the corb size to 256 entries (ULI requires explicitly) */ |
433 | azx_writeb(chip, CORBSIZE, 0x02); | |
1da177e4 LT |
434 | /* set the corb write pointer to 0 */ |
435 | azx_writew(chip, CORBWP, 0); | |
436 | /* reset the corb hw read pointer */ | |
437 | azx_writew(chip, CORBRP, ICH6_RBRWP_CLR); | |
438 | /* enable corb dma */ | |
439 | azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN); | |
440 | ||
441 | /* RIRB set up */ | |
442 | chip->rirb.addr = chip->rb.addr + 2048; | |
443 | chip->rirb.buf = (u32 *)(chip->rb.area + 2048); | |
444 | azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); | |
445 | azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr)); | |
446 | ||
07e4ca50 TI |
447 | /* set the rirb size to 256 entries (ULI requires explicitly) */ |
448 | azx_writeb(chip, RIRBSIZE, 0x02); | |
1da177e4 LT |
449 | /* reset the rirb hw write pointer */ |
450 | azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR); | |
451 | /* set N=1, get RIRB response interrupt for new entry */ | |
452 | azx_writew(chip, RINTCNT, 1); | |
453 | /* enable rirb dma and response irq */ | |
1da177e4 | 454 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); |
1da177e4 LT |
455 | chip->rirb.rp = chip->rirb.cmds = 0; |
456 | } | |
457 | ||
a98f90fd | 458 | static void azx_free_cmd_io(struct azx *chip) |
1da177e4 LT |
459 | { |
460 | /* disable ringbuffer DMAs */ | |
461 | azx_writeb(chip, RIRBCTL, 0); | |
462 | azx_writeb(chip, CORBCTL, 0); | |
463 | } | |
464 | ||
465 | /* send a command */ | |
111d3af5 TI |
466 | static int azx_corb_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct, |
467 | unsigned int verb, unsigned int para) | |
1da177e4 | 468 | { |
a98f90fd | 469 | struct azx *chip = codec->bus->private_data; |
1da177e4 LT |
470 | unsigned int wp; |
471 | u32 val; | |
472 | ||
473 | val = (u32)(codec->addr & 0x0f) << 28; | |
474 | val |= (u32)direct << 27; | |
475 | val |= (u32)nid << 20; | |
476 | val |= verb << 8; | |
477 | val |= para; | |
478 | ||
479 | /* add command to corb */ | |
480 | wp = azx_readb(chip, CORBWP); | |
481 | wp++; | |
482 | wp %= ICH6_MAX_CORB_ENTRIES; | |
483 | ||
484 | spin_lock_irq(&chip->reg_lock); | |
485 | chip->rirb.cmds++; | |
486 | chip->corb.buf[wp] = cpu_to_le32(val); | |
487 | azx_writel(chip, CORBWP, wp); | |
488 | spin_unlock_irq(&chip->reg_lock); | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
493 | #define ICH6_RIRB_EX_UNSOL_EV (1<<4) | |
494 | ||
495 | /* retrieve RIRB entry - called from interrupt handler */ | |
a98f90fd | 496 | static void azx_update_rirb(struct azx *chip) |
1da177e4 LT |
497 | { |
498 | unsigned int rp, wp; | |
499 | u32 res, res_ex; | |
500 | ||
501 | wp = azx_readb(chip, RIRBWP); | |
502 | if (wp == chip->rirb.wp) | |
503 | return; | |
504 | chip->rirb.wp = wp; | |
505 | ||
506 | while (chip->rirb.rp != wp) { | |
507 | chip->rirb.rp++; | |
508 | chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; | |
509 | ||
510 | rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ | |
511 | res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); | |
512 | res = le32_to_cpu(chip->rirb.buf[rp]); | |
513 | if (res_ex & ICH6_RIRB_EX_UNSOL_EV) | |
514 | snd_hda_queue_unsol_event(chip->bus, res, res_ex); | |
515 | else if (chip->rirb.cmds) { | |
516 | chip->rirb.cmds--; | |
517 | chip->rirb.res = res; | |
518 | } | |
519 | } | |
520 | } | |
521 | ||
522 | /* receive a response */ | |
111d3af5 | 523 | static unsigned int azx_rirb_get_response(struct hda_codec *codec) |
1da177e4 | 524 | { |
a98f90fd | 525 | struct azx *chip = codec->bus->private_data; |
5c79b1f8 | 526 | unsigned long timeout; |
1da177e4 | 527 | |
5c79b1f8 TI |
528 | again: |
529 | timeout = jiffies + msecs_to_jiffies(1000); | |
530 | do { | |
e96224ae TI |
531 | if (chip->polling_mode) { |
532 | spin_lock_irq(&chip->reg_lock); | |
533 | azx_update_rirb(chip); | |
534 | spin_unlock_irq(&chip->reg_lock); | |
535 | } | |
536 | if (! chip->rirb.cmds) | |
5c79b1f8 TI |
537 | return chip->rirb.res; /* the last value */ |
538 | schedule_timeout_interruptible(1); | |
539 | } while (time_after_eq(timeout, jiffies)); | |
540 | ||
68e7fffc TI |
541 | if (chip->msi) { |
542 | snd_printk(KERN_WARNING "hda_intel: No response from codec, " | |
543 | "disabling MSI...\n"); | |
544 | free_irq(chip->irq, chip); | |
545 | chip->irq = -1; | |
546 | pci_disable_msi(chip->pci); | |
547 | chip->msi = 0; | |
548 | if (azx_acquire_irq(chip, 1) < 0) | |
549 | return -1; | |
550 | goto again; | |
551 | } | |
552 | ||
5c79b1f8 TI |
553 | if (!chip->polling_mode) { |
554 | snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, " | |
555 | "switching to polling mode...\n"); | |
556 | chip->polling_mode = 1; | |
557 | goto again; | |
1da177e4 | 558 | } |
5c79b1f8 TI |
559 | |
560 | snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " | |
561 | "switching to single_cmd mode...\n"); | |
562 | chip->rirb.rp = azx_readb(chip, RIRBWP); | |
563 | chip->rirb.cmds = 0; | |
564 | /* switch to single_cmd mode */ | |
565 | chip->single_cmd = 1; | |
566 | azx_free_cmd_io(chip); | |
567 | return -1; | |
1da177e4 LT |
568 | } |
569 | ||
1da177e4 LT |
570 | /* |
571 | * Use the single immediate command instead of CORB/RIRB for simplicity | |
572 | * | |
573 | * Note: according to Intel, this is not preferred use. The command was | |
574 | * intended for the BIOS only, and may get confused with unsolicited | |
575 | * responses. So, we shouldn't use it for normal operation from the | |
576 | * driver. | |
577 | * I left the codes, however, for debugging/testing purposes. | |
578 | */ | |
579 | ||
1da177e4 | 580 | /* send a command */ |
27346166 TI |
581 | static int azx_single_send_cmd(struct hda_codec *codec, hda_nid_t nid, |
582 | int direct, unsigned int verb, | |
583 | unsigned int para) | |
1da177e4 | 584 | { |
a98f90fd | 585 | struct azx *chip = codec->bus->private_data; |
1da177e4 LT |
586 | u32 val; |
587 | int timeout = 50; | |
588 | ||
589 | val = (u32)(codec->addr & 0x0f) << 28; | |
590 | val |= (u32)direct << 27; | |
591 | val |= (u32)nid << 20; | |
592 | val |= verb << 8; | |
593 | val |= para; | |
594 | ||
595 | while (timeout--) { | |
596 | /* check ICB busy bit */ | |
597 | if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) { | |
598 | /* Clear IRV valid bit */ | |
599 | azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID); | |
600 | azx_writel(chip, IC, val); | |
601 | azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY); | |
602 | return 0; | |
603 | } | |
604 | udelay(1); | |
605 | } | |
606 | snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val); | |
607 | return -EIO; | |
608 | } | |
609 | ||
610 | /* receive a response */ | |
27346166 | 611 | static unsigned int azx_single_get_response(struct hda_codec *codec) |
1da177e4 | 612 | { |
a98f90fd | 613 | struct azx *chip = codec->bus->private_data; |
1da177e4 LT |
614 | int timeout = 50; |
615 | ||
616 | while (timeout--) { | |
617 | /* check IRV busy bit */ | |
618 | if (azx_readw(chip, IRS) & ICH6_IRS_VALID) | |
619 | return azx_readl(chip, IR); | |
620 | udelay(1); | |
621 | } | |
622 | snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS)); | |
623 | return (unsigned int)-1; | |
624 | } | |
625 | ||
111d3af5 TI |
626 | /* |
627 | * The below are the main callbacks from hda_codec. | |
628 | * | |
629 | * They are just the skeleton to call sub-callbacks according to the | |
630 | * current setting of chip->single_cmd. | |
631 | */ | |
632 | ||
633 | /* send a command */ | |
634 | static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, | |
635 | int direct, unsigned int verb, | |
636 | unsigned int para) | |
637 | { | |
638 | struct azx *chip = codec->bus->private_data; | |
639 | if (chip->single_cmd) | |
640 | return azx_single_send_cmd(codec, nid, direct, verb, para); | |
641 | else | |
642 | return azx_corb_send_cmd(codec, nid, direct, verb, para); | |
643 | } | |
644 | ||
645 | /* get a response */ | |
646 | static unsigned int azx_get_response(struct hda_codec *codec) | |
647 | { | |
648 | struct azx *chip = codec->bus->private_data; | |
649 | if (chip->single_cmd) | |
650 | return azx_single_get_response(codec); | |
651 | else | |
652 | return azx_rirb_get_response(codec); | |
653 | } | |
654 | ||
655 | ||
1da177e4 | 656 | /* reset codec link */ |
a98f90fd | 657 | static int azx_reset(struct azx *chip) |
1da177e4 LT |
658 | { |
659 | int count; | |
660 | ||
661 | /* reset controller */ | |
662 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); | |
663 | ||
664 | count = 50; | |
665 | while (azx_readb(chip, GCTL) && --count) | |
666 | msleep(1); | |
667 | ||
668 | /* delay for >= 100us for codec PLL to settle per spec | |
669 | * Rev 0.9 section 5.5.1 | |
670 | */ | |
671 | msleep(1); | |
672 | ||
673 | /* Bring controller out of reset */ | |
674 | azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); | |
675 | ||
676 | count = 50; | |
927fc866 | 677 | while (!azx_readb(chip, GCTL) && --count) |
1da177e4 LT |
678 | msleep(1); |
679 | ||
927fc866 | 680 | /* Brent Chartrand said to wait >= 540us for codecs to initialize */ |
1da177e4 LT |
681 | msleep(1); |
682 | ||
683 | /* check to see if controller is ready */ | |
927fc866 | 684 | if (!azx_readb(chip, GCTL)) { |
1da177e4 LT |
685 | snd_printd("azx_reset: controller not ready!\n"); |
686 | return -EBUSY; | |
687 | } | |
688 | ||
41e2fce4 M |
689 | /* Accept unsolicited responses */ |
690 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN); | |
691 | ||
1da177e4 | 692 | /* detect codecs */ |
927fc866 | 693 | if (!chip->codec_mask) { |
1da177e4 LT |
694 | chip->codec_mask = azx_readw(chip, STATESTS); |
695 | snd_printdd("codec_mask = 0x%x\n", chip->codec_mask); | |
696 | } | |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
701 | ||
702 | /* | |
703 | * Lowlevel interface | |
704 | */ | |
705 | ||
706 | /* enable interrupts */ | |
a98f90fd | 707 | static void azx_int_enable(struct azx *chip) |
1da177e4 LT |
708 | { |
709 | /* enable controller CIE and GIE */ | |
710 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | | |
711 | ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); | |
712 | } | |
713 | ||
714 | /* disable interrupts */ | |
a98f90fd | 715 | static void azx_int_disable(struct azx *chip) |
1da177e4 LT |
716 | { |
717 | int i; | |
718 | ||
719 | /* disable interrupts in stream descriptor */ | |
07e4ca50 | 720 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 721 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
722 | azx_sd_writeb(azx_dev, SD_CTL, |
723 | azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); | |
724 | } | |
725 | ||
726 | /* disable SIE for all streams */ | |
727 | azx_writeb(chip, INTCTL, 0); | |
728 | ||
729 | /* disable controller CIE and GIE */ | |
730 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & | |
731 | ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); | |
732 | } | |
733 | ||
734 | /* clear interrupts */ | |
a98f90fd | 735 | static void azx_int_clear(struct azx *chip) |
1da177e4 LT |
736 | { |
737 | int i; | |
738 | ||
739 | /* clear stream status */ | |
07e4ca50 | 740 | for (i = 0; i < chip->num_streams; i++) { |
a98f90fd | 741 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
742 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); |
743 | } | |
744 | ||
745 | /* clear STATESTS */ | |
746 | azx_writeb(chip, STATESTS, STATESTS_INT_MASK); | |
747 | ||
748 | /* clear rirb status */ | |
749 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
750 | ||
751 | /* clear int status */ | |
752 | azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); | |
753 | } | |
754 | ||
755 | /* start a stream */ | |
a98f90fd | 756 | static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) |
1da177e4 LT |
757 | { |
758 | /* enable SIE */ | |
759 | azx_writeb(chip, INTCTL, | |
760 | azx_readb(chip, INTCTL) | (1 << azx_dev->index)); | |
761 | /* set DMA start and interrupt mask */ | |
762 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | | |
763 | SD_CTL_DMA_START | SD_INT_MASK); | |
764 | } | |
765 | ||
766 | /* stop a stream */ | |
a98f90fd | 767 | static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) |
1da177e4 LT |
768 | { |
769 | /* stop DMA */ | |
770 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & | |
771 | ~(SD_CTL_DMA_START | SD_INT_MASK)); | |
772 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | |
773 | /* disable SIE */ | |
774 | azx_writeb(chip, INTCTL, | |
775 | azx_readb(chip, INTCTL) & ~(1 << azx_dev->index)); | |
776 | } | |
777 | ||
778 | ||
779 | /* | |
780 | * initialize the chip | |
781 | */ | |
a98f90fd | 782 | static void azx_init_chip(struct azx *chip) |
1da177e4 | 783 | { |
da3fca21 | 784 | unsigned char reg; |
1da177e4 LT |
785 | |
786 | /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) | |
787 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | |
788 | * Ensuring these bits are 0 clears playback static on some HD Audio codecs | |
789 | */ | |
da3fca21 V |
790 | pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, ®); |
791 | pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, reg & 0xf8); | |
1da177e4 LT |
792 | |
793 | /* reset controller */ | |
794 | azx_reset(chip); | |
795 | ||
796 | /* initialize interrupts */ | |
797 | azx_int_clear(chip); | |
798 | azx_int_enable(chip); | |
799 | ||
800 | /* initialize the codec command I/O */ | |
927fc866 | 801 | if (!chip->single_cmd) |
27346166 | 802 | azx_init_cmd_io(chip); |
1da177e4 | 803 | |
0be3b5d3 TI |
804 | /* program the position buffer */ |
805 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); | |
806 | azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr)); | |
f5d40b30 | 807 | |
da3fca21 V |
808 | switch (chip->driver_type) { |
809 | case AZX_DRIVER_ATI: | |
810 | /* For ATI SB450 azalia HD audio, we need to enable snoop */ | |
f5d40b30 | 811 | pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, |
da3fca21 | 812 | ®); |
f5d40b30 | 813 | pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, |
da3fca21 V |
814 | (reg & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP); |
815 | break; | |
816 | case AZX_DRIVER_NVIDIA: | |
817 | /* For NVIDIA HDA, enable snoop */ | |
818 | pci_read_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, ®); | |
819 | pci_write_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, | |
820 | (reg & 0xf0) | NVIDIA_HDA_ENABLE_COHBITS); | |
821 | break; | |
822 | } | |
1da177e4 LT |
823 | } |
824 | ||
825 | ||
826 | /* | |
827 | * interrupt handler | |
828 | */ | |
7d12e780 | 829 | static irqreturn_t azx_interrupt(int irq, void *dev_id) |
1da177e4 | 830 | { |
a98f90fd TI |
831 | struct azx *chip = dev_id; |
832 | struct azx_dev *azx_dev; | |
1da177e4 LT |
833 | u32 status; |
834 | int i; | |
835 | ||
836 | spin_lock(&chip->reg_lock); | |
837 | ||
838 | status = azx_readl(chip, INTSTS); | |
839 | if (status == 0) { | |
840 | spin_unlock(&chip->reg_lock); | |
841 | return IRQ_NONE; | |
842 | } | |
843 | ||
07e4ca50 | 844 | for (i = 0; i < chip->num_streams; i++) { |
1da177e4 LT |
845 | azx_dev = &chip->azx_dev[i]; |
846 | if (status & azx_dev->sd_int_sta_mask) { | |
847 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); | |
848 | if (azx_dev->substream && azx_dev->running) { | |
1a56f8d6 | 849 | azx_dev->period_intr++; |
1da177e4 LT |
850 | spin_unlock(&chip->reg_lock); |
851 | snd_pcm_period_elapsed(azx_dev->substream); | |
852 | spin_lock(&chip->reg_lock); | |
853 | } | |
854 | } | |
855 | } | |
856 | ||
857 | /* clear rirb int */ | |
858 | status = azx_readb(chip, RIRBSTS); | |
859 | if (status & RIRB_INT_MASK) { | |
27346166 | 860 | if (! chip->single_cmd && (status & RIRB_INT_RESPONSE)) |
1da177e4 LT |
861 | azx_update_rirb(chip); |
862 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
863 | } | |
864 | ||
865 | #if 0 | |
866 | /* clear state status int */ | |
867 | if (azx_readb(chip, STATESTS) & 0x04) | |
868 | azx_writeb(chip, STATESTS, 0x04); | |
869 | #endif | |
870 | spin_unlock(&chip->reg_lock); | |
871 | ||
872 | return IRQ_HANDLED; | |
873 | } | |
874 | ||
875 | ||
876 | /* | |
877 | * set up BDL entries | |
878 | */ | |
a98f90fd | 879 | static void azx_setup_periods(struct azx_dev *azx_dev) |
1da177e4 LT |
880 | { |
881 | u32 *bdl = azx_dev->bdl; | |
882 | dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr; | |
883 | int idx; | |
884 | ||
885 | /* reset BDL address */ | |
886 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
887 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
888 | ||
889 | /* program the initial BDL entries */ | |
890 | for (idx = 0; idx < azx_dev->frags; idx++) { | |
891 | unsigned int off = idx << 2; /* 4 dword step */ | |
892 | dma_addr_t addr = dma_addr + idx * azx_dev->fragsize; | |
893 | /* program the address field of the BDL entry */ | |
894 | bdl[off] = cpu_to_le32((u32)addr); | |
895 | bdl[off+1] = cpu_to_le32(upper_32bit(addr)); | |
896 | ||
897 | /* program the size field of the BDL entry */ | |
898 | bdl[off+2] = cpu_to_le32(azx_dev->fragsize); | |
899 | ||
900 | /* program the IOC to enable interrupt when buffer completes */ | |
901 | bdl[off+3] = cpu_to_le32(0x01); | |
902 | } | |
903 | } | |
904 | ||
905 | /* | |
906 | * set up the SD for streaming | |
907 | */ | |
a98f90fd | 908 | static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) |
1da177e4 LT |
909 | { |
910 | unsigned char val; | |
911 | int timeout; | |
912 | ||
913 | /* make sure the run bit is zero for SD */ | |
914 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START); | |
915 | /* reset stream */ | |
916 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET); | |
917 | udelay(3); | |
918 | timeout = 300; | |
919 | while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
920 | --timeout) | |
921 | ; | |
922 | val &= ~SD_CTL_STREAM_RESET; | |
923 | azx_sd_writeb(azx_dev, SD_CTL, val); | |
924 | udelay(3); | |
925 | ||
926 | timeout = 300; | |
927 | /* waiting for hardware to report that the stream is out of reset */ | |
928 | while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
929 | --timeout) | |
930 | ; | |
931 | ||
932 | /* program the stream_tag */ | |
933 | azx_sd_writel(azx_dev, SD_CTL, | |
934 | (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) | | |
935 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); | |
936 | ||
937 | /* program the length of samples in cyclic buffer */ | |
938 | azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); | |
939 | ||
940 | /* program the stream format */ | |
941 | /* this value needs to be the same as the one programmed */ | |
942 | azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); | |
943 | ||
944 | /* program the stream LVI (last valid index) of the BDL */ | |
945 | azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); | |
946 | ||
947 | /* program the BDL address */ | |
948 | /* lower BDL address */ | |
949 | azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr); | |
950 | /* upper BDL address */ | |
951 | azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr)); | |
952 | ||
0be3b5d3 TI |
953 | /* enable the position buffer */ |
954 | if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) | |
955 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); | |
c74db86b | 956 | |
1da177e4 LT |
957 | /* set the interrupt enable bits in the descriptor control register */ |
958 | azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); | |
959 | ||
960 | return 0; | |
961 | } | |
962 | ||
963 | ||
964 | /* | |
965 | * Codec initialization | |
966 | */ | |
967 | ||
a9995a35 TI |
968 | static unsigned int azx_max_codecs[] __devinitdata = { |
969 | [AZX_DRIVER_ICH] = 3, | |
970 | [AZX_DRIVER_ATI] = 4, | |
971 | [AZX_DRIVER_ATIHDMI] = 4, | |
972 | [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */ | |
973 | [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */ | |
974 | [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */ | |
975 | [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */ | |
976 | }; | |
977 | ||
a98f90fd | 978 | static int __devinit azx_codec_create(struct azx *chip, const char *model) |
1da177e4 LT |
979 | { |
980 | struct hda_bus_template bus_temp; | |
981 | int c, codecs, err; | |
982 | ||
983 | memset(&bus_temp, 0, sizeof(bus_temp)); | |
984 | bus_temp.private_data = chip; | |
985 | bus_temp.modelname = model; | |
986 | bus_temp.pci = chip->pci; | |
111d3af5 TI |
987 | bus_temp.ops.command = azx_send_cmd; |
988 | bus_temp.ops.get_response = azx_get_response; | |
1da177e4 LT |
989 | |
990 | if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0) | |
991 | return err; | |
992 | ||
993 | codecs = 0; | |
a9995a35 | 994 | for (c = 0; c < azx_max_codecs[chip->driver_type]; c++) { |
606ad75f | 995 | if ((chip->codec_mask & (1 << c)) & probe_mask) { |
1da177e4 LT |
996 | err = snd_hda_codec_new(chip->bus, c, NULL); |
997 | if (err < 0) | |
998 | continue; | |
999 | codecs++; | |
1000 | } | |
1001 | } | |
1002 | if (! codecs) { | |
1003 | snd_printk(KERN_ERR SFX "no codecs initialized\n"); | |
1004 | return -ENXIO; | |
1005 | } | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
1010 | ||
1011 | /* | |
1012 | * PCM support | |
1013 | */ | |
1014 | ||
1015 | /* assign a stream for the PCM */ | |
a98f90fd | 1016 | static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream) |
1da177e4 | 1017 | { |
07e4ca50 TI |
1018 | int dev, i, nums; |
1019 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
1020 | dev = chip->playback_index_offset; | |
1021 | nums = chip->playback_streams; | |
1022 | } else { | |
1023 | dev = chip->capture_index_offset; | |
1024 | nums = chip->capture_streams; | |
1025 | } | |
1026 | for (i = 0; i < nums; i++, dev++) | |
1da177e4 LT |
1027 | if (! chip->azx_dev[dev].opened) { |
1028 | chip->azx_dev[dev].opened = 1; | |
1029 | return &chip->azx_dev[dev]; | |
1030 | } | |
1031 | return NULL; | |
1032 | } | |
1033 | ||
1034 | /* release the assigned stream */ | |
a98f90fd | 1035 | static inline void azx_release_device(struct azx_dev *azx_dev) |
1da177e4 LT |
1036 | { |
1037 | azx_dev->opened = 0; | |
1038 | } | |
1039 | ||
a98f90fd | 1040 | static struct snd_pcm_hardware azx_pcm_hw = { |
1da177e4 LT |
1041 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | |
1042 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
1043 | SNDRV_PCM_INFO_MMAP_VALID | | |
927fc866 PM |
1044 | /* No full-resume yet implemented */ |
1045 | /* SNDRV_PCM_INFO_RESUME |*/ | |
1046 | SNDRV_PCM_INFO_PAUSE), | |
1da177e4 LT |
1047 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
1048 | .rates = SNDRV_PCM_RATE_48000, | |
1049 | .rate_min = 48000, | |
1050 | .rate_max = 48000, | |
1051 | .channels_min = 2, | |
1052 | .channels_max = 2, | |
1053 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, | |
1054 | .period_bytes_min = 128, | |
1055 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | |
1056 | .periods_min = 2, | |
1057 | .periods_max = AZX_MAX_FRAG, | |
1058 | .fifo_size = 0, | |
1059 | }; | |
1060 | ||
1061 | struct azx_pcm { | |
a98f90fd | 1062 | struct azx *chip; |
1da177e4 LT |
1063 | struct hda_codec *codec; |
1064 | struct hda_pcm_stream *hinfo[2]; | |
1065 | }; | |
1066 | ||
a98f90fd | 1067 | static int azx_pcm_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
1068 | { |
1069 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1070 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
a98f90fd TI |
1071 | struct azx *chip = apcm->chip; |
1072 | struct azx_dev *azx_dev; | |
1073 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1074 | unsigned long flags; |
1075 | int err; | |
1076 | ||
62932df8 | 1077 | mutex_lock(&chip->open_mutex); |
1da177e4 LT |
1078 | azx_dev = azx_assign_device(chip, substream->stream); |
1079 | if (azx_dev == NULL) { | |
62932df8 | 1080 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1081 | return -EBUSY; |
1082 | } | |
1083 | runtime->hw = azx_pcm_hw; | |
1084 | runtime->hw.channels_min = hinfo->channels_min; | |
1085 | runtime->hw.channels_max = hinfo->channels_max; | |
1086 | runtime->hw.formats = hinfo->formats; | |
1087 | runtime->hw.rates = hinfo->rates; | |
1088 | snd_pcm_limit_hw_rates(runtime); | |
1089 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | |
1090 | if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) { | |
1091 | azx_release_device(azx_dev); | |
62932df8 | 1092 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1093 | return err; |
1094 | } | |
1095 | spin_lock_irqsave(&chip->reg_lock, flags); | |
1096 | azx_dev->substream = substream; | |
1097 | azx_dev->running = 0; | |
1098 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
1099 | ||
1100 | runtime->private_data = azx_dev; | |
62932df8 | 1101 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1102 | return 0; |
1103 | } | |
1104 | ||
a98f90fd | 1105 | static int azx_pcm_close(struct snd_pcm_substream *substream) |
1da177e4 LT |
1106 | { |
1107 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1108 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
a98f90fd TI |
1109 | struct azx *chip = apcm->chip; |
1110 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 LT |
1111 | unsigned long flags; |
1112 | ||
62932df8 | 1113 | mutex_lock(&chip->open_mutex); |
1da177e4 LT |
1114 | spin_lock_irqsave(&chip->reg_lock, flags); |
1115 | azx_dev->substream = NULL; | |
1116 | azx_dev->running = 0; | |
1117 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
1118 | azx_release_device(azx_dev); | |
1119 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
62932df8 | 1120 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
1121 | return 0; |
1122 | } | |
1123 | ||
a98f90fd | 1124 | static int azx_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) |
1da177e4 LT |
1125 | { |
1126 | return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
1127 | } | |
1128 | ||
a98f90fd | 1129 | static int azx_pcm_hw_free(struct snd_pcm_substream *substream) |
1da177e4 LT |
1130 | { |
1131 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd | 1132 | struct azx_dev *azx_dev = get_azx_dev(substream); |
1da177e4 LT |
1133 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
1134 | ||
1135 | /* reset BDL address */ | |
1136 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
1137 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
1138 | azx_sd_writel(azx_dev, SD_CTL, 0); | |
1139 | ||
1140 | hinfo->ops.cleanup(hinfo, apcm->codec, substream); | |
1141 | ||
1142 | return snd_pcm_lib_free_pages(substream); | |
1143 | } | |
1144 | ||
a98f90fd | 1145 | static int azx_pcm_prepare(struct snd_pcm_substream *substream) |
1da177e4 LT |
1146 | { |
1147 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd TI |
1148 | struct azx *chip = apcm->chip; |
1149 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 | 1150 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
a98f90fd | 1151 | struct snd_pcm_runtime *runtime = substream->runtime; |
1da177e4 LT |
1152 | |
1153 | azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream); | |
1154 | azx_dev->fragsize = snd_pcm_lib_period_bytes(substream); | |
1155 | azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize; | |
1156 | azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate, | |
1157 | runtime->channels, | |
1158 | runtime->format, | |
1159 | hinfo->maxbps); | |
1160 | if (! azx_dev->format_val) { | |
1161 | snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n", | |
1162 | runtime->rate, runtime->channels, runtime->format); | |
1163 | return -EINVAL; | |
1164 | } | |
1165 | ||
1166 | snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n", | |
1167 | azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val); | |
1168 | azx_setup_periods(azx_dev); | |
1169 | azx_setup_controller(chip, azx_dev); | |
1170 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1171 | azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; | |
1172 | else | |
1173 | azx_dev->fifo_size = 0; | |
1174 | ||
1175 | return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag, | |
1176 | azx_dev->format_val, substream); | |
1177 | } | |
1178 | ||
a98f90fd | 1179 | static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 LT |
1180 | { |
1181 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
a98f90fd TI |
1182 | struct azx_dev *azx_dev = get_azx_dev(substream); |
1183 | struct azx *chip = apcm->chip; | |
1da177e4 LT |
1184 | int err = 0; |
1185 | ||
1186 | spin_lock(&chip->reg_lock); | |
1187 | switch (cmd) { | |
1188 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
1189 | case SNDRV_PCM_TRIGGER_RESUME: | |
1190 | case SNDRV_PCM_TRIGGER_START: | |
1191 | azx_stream_start(chip, azx_dev); | |
1192 | azx_dev->running = 1; | |
1193 | break; | |
1194 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
47123197 | 1195 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1da177e4 LT |
1196 | case SNDRV_PCM_TRIGGER_STOP: |
1197 | azx_stream_stop(chip, azx_dev); | |
1198 | azx_dev->running = 0; | |
1199 | break; | |
1200 | default: | |
1201 | err = -EINVAL; | |
1202 | } | |
1203 | spin_unlock(&chip->reg_lock); | |
1204 | if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH || | |
47123197 | 1205 | cmd == SNDRV_PCM_TRIGGER_SUSPEND || |
1da177e4 LT |
1206 | cmd == SNDRV_PCM_TRIGGER_STOP) { |
1207 | int timeout = 5000; | |
1208 | while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout) | |
1209 | ; | |
1210 | } | |
1211 | return err; | |
1212 | } | |
1213 | ||
a98f90fd | 1214 | static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 1215 | { |
c74db86b | 1216 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
a98f90fd TI |
1217 | struct azx *chip = apcm->chip; |
1218 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1da177e4 LT |
1219 | unsigned int pos; |
1220 | ||
1a56f8d6 TI |
1221 | if (chip->position_fix == POS_FIX_POSBUF || |
1222 | chip->position_fix == POS_FIX_AUTO) { | |
c74db86b | 1223 | /* use the position buffer */ |
929861c6 | 1224 | pos = le32_to_cpu(*azx_dev->posbuf); |
1a56f8d6 TI |
1225 | if (chip->position_fix == POS_FIX_AUTO && |
1226 | azx_dev->period_intr == 1 && ! pos) { | |
1227 | printk(KERN_WARNING | |
1228 | "hda-intel: Invalid position buffer, " | |
1229 | "using LPIB read method instead.\n"); | |
1230 | chip->position_fix = POS_FIX_NONE; | |
1231 | goto read_lpib; | |
1232 | } | |
c74db86b | 1233 | } else { |
1a56f8d6 | 1234 | read_lpib: |
c74db86b TI |
1235 | /* read LPIB */ |
1236 | pos = azx_sd_readl(azx_dev, SD_LPIB); | |
1237 | if (chip->position_fix == POS_FIX_FIFO) | |
1238 | pos += azx_dev->fifo_size; | |
1239 | } | |
1da177e4 LT |
1240 | if (pos >= azx_dev->bufsize) |
1241 | pos = 0; | |
1242 | return bytes_to_frames(substream->runtime, pos); | |
1243 | } | |
1244 | ||
a98f90fd | 1245 | static struct snd_pcm_ops azx_pcm_ops = { |
1da177e4 LT |
1246 | .open = azx_pcm_open, |
1247 | .close = azx_pcm_close, | |
1248 | .ioctl = snd_pcm_lib_ioctl, | |
1249 | .hw_params = azx_pcm_hw_params, | |
1250 | .hw_free = azx_pcm_hw_free, | |
1251 | .prepare = azx_pcm_prepare, | |
1252 | .trigger = azx_pcm_trigger, | |
1253 | .pointer = azx_pcm_pointer, | |
1254 | }; | |
1255 | ||
a98f90fd | 1256 | static void azx_pcm_free(struct snd_pcm *pcm) |
1da177e4 LT |
1257 | { |
1258 | kfree(pcm->private_data); | |
1259 | } | |
1260 | ||
a98f90fd | 1261 | static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec, |
1da177e4 LT |
1262 | struct hda_pcm *cpcm, int pcm_dev) |
1263 | { | |
1264 | int err; | |
a98f90fd | 1265 | struct snd_pcm *pcm; |
1da177e4 LT |
1266 | struct azx_pcm *apcm; |
1267 | ||
e08a007d TI |
1268 | /* if no substreams are defined for both playback and capture, |
1269 | * it's just a placeholder. ignore it. | |
1270 | */ | |
1271 | if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams) | |
1272 | return 0; | |
1273 | ||
1da177e4 LT |
1274 | snd_assert(cpcm->name, return -EINVAL); |
1275 | ||
1276 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, | |
1277 | cpcm->stream[0].substreams, cpcm->stream[1].substreams, | |
1278 | &pcm); | |
1279 | if (err < 0) | |
1280 | return err; | |
1281 | strcpy(pcm->name, cpcm->name); | |
1282 | apcm = kmalloc(sizeof(*apcm), GFP_KERNEL); | |
1283 | if (apcm == NULL) | |
1284 | return -ENOMEM; | |
1285 | apcm->chip = chip; | |
1286 | apcm->codec = codec; | |
1287 | apcm->hinfo[0] = &cpcm->stream[0]; | |
1288 | apcm->hinfo[1] = &cpcm->stream[1]; | |
1289 | pcm->private_data = apcm; | |
1290 | pcm->private_free = azx_pcm_free; | |
1291 | if (cpcm->stream[0].substreams) | |
1292 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops); | |
1293 | if (cpcm->stream[1].substreams) | |
1294 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops); | |
1295 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1296 | snd_dma_pci_data(chip->pci), | |
b66b3cfe | 1297 | 1024 * 64, 1024 * 1024); |
1da177e4 | 1298 | chip->pcm[pcm_dev] = pcm; |
e08a007d TI |
1299 | if (chip->pcm_devs < pcm_dev + 1) |
1300 | chip->pcm_devs = pcm_dev + 1; | |
1da177e4 LT |
1301 | |
1302 | return 0; | |
1303 | } | |
1304 | ||
a98f90fd | 1305 | static int __devinit azx_pcm_create(struct azx *chip) |
1da177e4 LT |
1306 | { |
1307 | struct list_head *p; | |
1308 | struct hda_codec *codec; | |
1309 | int c, err; | |
1310 | int pcm_dev; | |
1311 | ||
1312 | if ((err = snd_hda_build_pcms(chip->bus)) < 0) | |
1313 | return err; | |
1314 | ||
ec9e1c5c | 1315 | /* create audio PCMs */ |
1da177e4 LT |
1316 | pcm_dev = 0; |
1317 | list_for_each(p, &chip->bus->codec_list) { | |
1318 | codec = list_entry(p, struct hda_codec, list); | |
1319 | for (c = 0; c < codec->num_pcms; c++) { | |
ec9e1c5c TI |
1320 | if (codec->pcm_info[c].is_modem) |
1321 | continue; /* create later */ | |
1322 | if (pcm_dev >= AZX_MAX_AUDIO_PCMS) { | |
1323 | snd_printk(KERN_ERR SFX "Too many audio PCMs\n"); | |
1324 | return -EINVAL; | |
1325 | } | |
1326 | err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev); | |
1327 | if (err < 0) | |
1328 | return err; | |
1329 | pcm_dev++; | |
1330 | } | |
1331 | } | |
1332 | ||
1333 | /* create modem PCMs */ | |
1334 | pcm_dev = AZX_MAX_AUDIO_PCMS; | |
1335 | list_for_each(p, &chip->bus->codec_list) { | |
1336 | codec = list_entry(p, struct hda_codec, list); | |
1337 | for (c = 0; c < codec->num_pcms; c++) { | |
1338 | if (! codec->pcm_info[c].is_modem) | |
1339 | continue; /* already created */ | |
a28f1cda | 1340 | if (pcm_dev >= AZX_MAX_PCMS) { |
ec9e1c5c | 1341 | snd_printk(KERN_ERR SFX "Too many modem PCMs\n"); |
1da177e4 LT |
1342 | return -EINVAL; |
1343 | } | |
1344 | err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev); | |
1345 | if (err < 0) | |
1346 | return err; | |
6632d198 | 1347 | chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM; |
1da177e4 LT |
1348 | pcm_dev++; |
1349 | } | |
1350 | } | |
1351 | return 0; | |
1352 | } | |
1353 | ||
1354 | /* | |
1355 | * mixer creation - all stuff is implemented in hda module | |
1356 | */ | |
a98f90fd | 1357 | static int __devinit azx_mixer_create(struct azx *chip) |
1da177e4 LT |
1358 | { |
1359 | return snd_hda_build_controls(chip->bus); | |
1360 | } | |
1361 | ||
1362 | ||
1363 | /* | |
1364 | * initialize SD streams | |
1365 | */ | |
a98f90fd | 1366 | static int __devinit azx_init_stream(struct azx *chip) |
1da177e4 LT |
1367 | { |
1368 | int i; | |
1369 | ||
1370 | /* initialize each stream (aka device) | |
1371 | * assign the starting bdl address to each stream (device) and initialize | |
1372 | */ | |
07e4ca50 | 1373 | for (i = 0; i < chip->num_streams; i++) { |
1da177e4 | 1374 | unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4); |
a98f90fd | 1375 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1da177e4 LT |
1376 | azx_dev->bdl = (u32 *)(chip->bdl.area + off); |
1377 | azx_dev->bdl_addr = chip->bdl.addr + off; | |
929861c6 | 1378 | azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); |
1da177e4 LT |
1379 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
1380 | azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); | |
1381 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ | |
1382 | azx_dev->sd_int_sta_mask = 1 << i; | |
1383 | /* stream tag: must be non-zero and unique */ | |
1384 | azx_dev->index = i; | |
1385 | azx_dev->stream_tag = i + 1; | |
1386 | } | |
1387 | ||
1388 | return 0; | |
1389 | } | |
1390 | ||
68e7fffc TI |
1391 | static int azx_acquire_irq(struct azx *chip, int do_disconnect) |
1392 | { | |
437a5a46 TI |
1393 | if (request_irq(chip->pci->irq, azx_interrupt, |
1394 | chip->msi ? 0 : IRQF_SHARED, | |
68e7fffc TI |
1395 | "HDA Intel", chip)) { |
1396 | printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " | |
1397 | "disabling device\n", chip->pci->irq); | |
1398 | if (do_disconnect) | |
1399 | snd_card_disconnect(chip->card); | |
1400 | return -1; | |
1401 | } | |
1402 | chip->irq = chip->pci->irq; | |
69e13418 | 1403 | pci_intx(chip->pci, !chip->msi); |
68e7fffc TI |
1404 | return 0; |
1405 | } | |
1406 | ||
1da177e4 LT |
1407 | |
1408 | #ifdef CONFIG_PM | |
1409 | /* | |
1410 | * power management | |
1411 | */ | |
421a1252 | 1412 | static int azx_suspend(struct pci_dev *pci, pm_message_t state) |
1da177e4 | 1413 | { |
421a1252 TI |
1414 | struct snd_card *card = pci_get_drvdata(pci); |
1415 | struct azx *chip = card->private_data; | |
1da177e4 LT |
1416 | int i; |
1417 | ||
421a1252 | 1418 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
1da177e4 | 1419 | for (i = 0; i < chip->pcm_devs; i++) |
421a1252 | 1420 | snd_pcm_suspend_all(chip->pcm[i]); |
1da177e4 | 1421 | snd_hda_suspend(chip->bus, state); |
111d3af5 | 1422 | azx_free_cmd_io(chip); |
30b35399 TI |
1423 | if (chip->irq >= 0) { |
1424 | synchronize_irq(chip->irq); | |
43001c95 | 1425 | free_irq(chip->irq, chip); |
30b35399 TI |
1426 | chip->irq = -1; |
1427 | } | |
68e7fffc | 1428 | if (chip->msi) |
43001c95 | 1429 | pci_disable_msi(chip->pci); |
421a1252 TI |
1430 | pci_disable_device(pci); |
1431 | pci_save_state(pci); | |
30b35399 | 1432 | pci_set_power_state(pci, pci_choose_state(pci, state)); |
1da177e4 LT |
1433 | return 0; |
1434 | } | |
1435 | ||
421a1252 | 1436 | static int azx_resume(struct pci_dev *pci) |
1da177e4 | 1437 | { |
421a1252 TI |
1438 | struct snd_card *card = pci_get_drvdata(pci); |
1439 | struct azx *chip = card->private_data; | |
1da177e4 | 1440 | |
30b35399 | 1441 | pci_set_power_state(pci, PCI_D0); |
421a1252 | 1442 | pci_restore_state(pci); |
30b35399 TI |
1443 | if (pci_enable_device(pci) < 0) { |
1444 | printk(KERN_ERR "hda-intel: pci_enable_device failed, " | |
1445 | "disabling device\n"); | |
1446 | snd_card_disconnect(card); | |
1447 | return -EIO; | |
1448 | } | |
1449 | pci_set_master(pci); | |
68e7fffc TI |
1450 | if (chip->msi) |
1451 | if (pci_enable_msi(pci) < 0) | |
1452 | chip->msi = 0; | |
1453 | if (azx_acquire_irq(chip, 1) < 0) | |
30b35399 | 1454 | return -EIO; |
1da177e4 LT |
1455 | azx_init_chip(chip); |
1456 | snd_hda_resume(chip->bus); | |
421a1252 | 1457 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
1da177e4 LT |
1458 | return 0; |
1459 | } | |
1460 | #endif /* CONFIG_PM */ | |
1461 | ||
1462 | ||
1463 | /* | |
1464 | * destructor | |
1465 | */ | |
a98f90fd | 1466 | static int azx_free(struct azx *chip) |
1da177e4 | 1467 | { |
ce43fbae | 1468 | if (chip->initialized) { |
1da177e4 LT |
1469 | int i; |
1470 | ||
07e4ca50 | 1471 | for (i = 0; i < chip->num_streams; i++) |
1da177e4 LT |
1472 | azx_stream_stop(chip, &chip->azx_dev[i]); |
1473 | ||
1474 | /* disable interrupts */ | |
1475 | azx_int_disable(chip); | |
1476 | azx_int_clear(chip); | |
1477 | ||
1478 | /* disable CORB/RIRB */ | |
111d3af5 | 1479 | azx_free_cmd_io(chip); |
1da177e4 LT |
1480 | |
1481 | /* disable position buffer */ | |
1482 | azx_writel(chip, DPLBASE, 0); | |
1483 | azx_writel(chip, DPUBASE, 0); | |
1da177e4 LT |
1484 | } |
1485 | ||
7376d013 | 1486 | if (chip->irq >= 0) { |
30b35399 | 1487 | synchronize_irq(chip->irq); |
1da177e4 | 1488 | free_irq(chip->irq, (void*)chip); |
7376d013 | 1489 | } |
68e7fffc | 1490 | if (chip->msi) |
30b35399 | 1491 | pci_disable_msi(chip->pci); |
f079c25a TI |
1492 | if (chip->remap_addr) |
1493 | iounmap(chip->remap_addr); | |
1da177e4 LT |
1494 | |
1495 | if (chip->bdl.area) | |
1496 | snd_dma_free_pages(&chip->bdl); | |
1497 | if (chip->rb.area) | |
1498 | snd_dma_free_pages(&chip->rb); | |
1da177e4 LT |
1499 | if (chip->posbuf.area) |
1500 | snd_dma_free_pages(&chip->posbuf); | |
1da177e4 LT |
1501 | pci_release_regions(chip->pci); |
1502 | pci_disable_device(chip->pci); | |
07e4ca50 | 1503 | kfree(chip->azx_dev); |
1da177e4 LT |
1504 | kfree(chip); |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | ||
a98f90fd | 1509 | static int azx_dev_free(struct snd_device *device) |
1da177e4 LT |
1510 | { |
1511 | return azx_free(device->device_data); | |
1512 | } | |
1513 | ||
3372a153 TI |
1514 | /* |
1515 | * white/black-listing for position_fix | |
1516 | */ | |
1517 | static const struct snd_pci_quirk position_fix_list[] __devinitdata = { | |
1518 | SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE), | |
1519 | {} | |
1520 | }; | |
1521 | ||
1522 | static int __devinit check_position_fix(struct azx *chip, int fix) | |
1523 | { | |
1524 | const struct snd_pci_quirk *q; | |
1525 | ||
1526 | if (fix == POS_FIX_AUTO) { | |
1527 | q = snd_pci_quirk_lookup(chip->pci, position_fix_list); | |
1528 | if (q) { | |
1529 | snd_printdd(KERN_INFO | |
1530 | "hda_intel: position_fix set to %d " | |
1531 | "for device %04x:%04x\n", | |
1532 | q->value, q->subvendor, q->subdevice); | |
1533 | return q->value; | |
1534 | } | |
1535 | } | |
1536 | return fix; | |
1537 | } | |
1538 | ||
1da177e4 LT |
1539 | /* |
1540 | * constructor | |
1541 | */ | |
a98f90fd | 1542 | static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci, |
606ad75f | 1543 | int driver_type, |
a98f90fd | 1544 | struct azx **rchip) |
1da177e4 | 1545 | { |
a98f90fd | 1546 | struct azx *chip; |
927fc866 | 1547 | int err; |
a98f90fd | 1548 | static struct snd_device_ops ops = { |
1da177e4 LT |
1549 | .dev_free = azx_dev_free, |
1550 | }; | |
1551 | ||
1552 | *rchip = NULL; | |
1553 | ||
927fc866 PM |
1554 | err = pci_enable_device(pci); |
1555 | if (err < 0) | |
1da177e4 LT |
1556 | return err; |
1557 | ||
e560d8d8 | 1558 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
927fc866 | 1559 | if (!chip) { |
1da177e4 LT |
1560 | snd_printk(KERN_ERR SFX "cannot allocate chip\n"); |
1561 | pci_disable_device(pci); | |
1562 | return -ENOMEM; | |
1563 | } | |
1564 | ||
1565 | spin_lock_init(&chip->reg_lock); | |
62932df8 | 1566 | mutex_init(&chip->open_mutex); |
1da177e4 LT |
1567 | chip->card = card; |
1568 | chip->pci = pci; | |
1569 | chip->irq = -1; | |
07e4ca50 | 1570 | chip->driver_type = driver_type; |
134a11f0 | 1571 | chip->msi = enable_msi; |
1da177e4 | 1572 | |
3372a153 TI |
1573 | chip->position_fix = check_position_fix(chip, position_fix); |
1574 | ||
27346166 | 1575 | chip->single_cmd = single_cmd; |
c74db86b | 1576 | |
07e4ca50 TI |
1577 | #if BITS_PER_LONG != 64 |
1578 | /* Fix up base address on ULI M5461 */ | |
1579 | if (chip->driver_type == AZX_DRIVER_ULI) { | |
1580 | u16 tmp3; | |
1581 | pci_read_config_word(pci, 0x40, &tmp3); | |
1582 | pci_write_config_word(pci, 0x40, tmp3 | 0x10); | |
1583 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); | |
1584 | } | |
1585 | #endif | |
1586 | ||
927fc866 PM |
1587 | err = pci_request_regions(pci, "ICH HD audio"); |
1588 | if (err < 0) { | |
1da177e4 LT |
1589 | kfree(chip); |
1590 | pci_disable_device(pci); | |
1591 | return err; | |
1592 | } | |
1593 | ||
927fc866 | 1594 | chip->addr = pci_resource_start(pci, 0); |
1da177e4 LT |
1595 | chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0)); |
1596 | if (chip->remap_addr == NULL) { | |
1597 | snd_printk(KERN_ERR SFX "ioremap error\n"); | |
1598 | err = -ENXIO; | |
1599 | goto errout; | |
1600 | } | |
1601 | ||
68e7fffc TI |
1602 | if (chip->msi) |
1603 | if (pci_enable_msi(pci) < 0) | |
1604 | chip->msi = 0; | |
7376d013 | 1605 | |
68e7fffc | 1606 | if (azx_acquire_irq(chip, 0) < 0) { |
1da177e4 LT |
1607 | err = -EBUSY; |
1608 | goto errout; | |
1609 | } | |
1da177e4 LT |
1610 | |
1611 | pci_set_master(pci); | |
1612 | synchronize_irq(chip->irq); | |
1613 | ||
07e4ca50 TI |
1614 | switch (chip->driver_type) { |
1615 | case AZX_DRIVER_ULI: | |
1616 | chip->playback_streams = ULI_NUM_PLAYBACK; | |
1617 | chip->capture_streams = ULI_NUM_CAPTURE; | |
1618 | chip->playback_index_offset = ULI_PLAYBACK_INDEX; | |
1619 | chip->capture_index_offset = ULI_CAPTURE_INDEX; | |
1620 | break; | |
778b6e1b FK |
1621 | case AZX_DRIVER_ATIHDMI: |
1622 | chip->playback_streams = ATIHDMI_NUM_PLAYBACK; | |
1623 | chip->capture_streams = ATIHDMI_NUM_CAPTURE; | |
1624 | chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX; | |
1625 | chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX; | |
1626 | break; | |
07e4ca50 TI |
1627 | default: |
1628 | chip->playback_streams = ICH6_NUM_PLAYBACK; | |
1629 | chip->capture_streams = ICH6_NUM_CAPTURE; | |
1630 | chip->playback_index_offset = ICH6_PLAYBACK_INDEX; | |
1631 | chip->capture_index_offset = ICH6_CAPTURE_INDEX; | |
1632 | break; | |
1633 | } | |
1634 | chip->num_streams = chip->playback_streams + chip->capture_streams; | |
1635 | chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), GFP_KERNEL); | |
927fc866 | 1636 | if (!chip->azx_dev) { |
07e4ca50 TI |
1637 | snd_printk(KERN_ERR "cannot malloc azx_dev\n"); |
1638 | goto errout; | |
1639 | } | |
1640 | ||
1da177e4 LT |
1641 | /* allocate memory for the BDL for each stream */ |
1642 | if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
07e4ca50 | 1643 | BDL_SIZE, &chip->bdl)) < 0) { |
1da177e4 LT |
1644 | snd_printk(KERN_ERR SFX "cannot allocate BDL\n"); |
1645 | goto errout; | |
1646 | } | |
0be3b5d3 TI |
1647 | /* allocate memory for the position buffer */ |
1648 | if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
1649 | chip->num_streams * 8, &chip->posbuf)) < 0) { | |
1650 | snd_printk(KERN_ERR SFX "cannot allocate posbuf\n"); | |
1651 | goto errout; | |
1da177e4 | 1652 | } |
1da177e4 | 1653 | /* allocate CORB/RIRB */ |
27346166 TI |
1654 | if (! chip->single_cmd) |
1655 | if ((err = azx_alloc_cmd_io(chip)) < 0) | |
1656 | goto errout; | |
1da177e4 LT |
1657 | |
1658 | /* initialize streams */ | |
1659 | azx_init_stream(chip); | |
1660 | ||
1661 | /* initialize chip */ | |
1662 | azx_init_chip(chip); | |
1663 | ||
ce43fbae TI |
1664 | chip->initialized = 1; |
1665 | ||
1da177e4 | 1666 | /* codec detection */ |
927fc866 | 1667 | if (!chip->codec_mask) { |
1da177e4 LT |
1668 | snd_printk(KERN_ERR SFX "no codecs found!\n"); |
1669 | err = -ENODEV; | |
1670 | goto errout; | |
1671 | } | |
1672 | ||
1673 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) { | |
1674 | snd_printk(KERN_ERR SFX "Error creating device [card]!\n"); | |
1675 | goto errout; | |
1676 | } | |
1677 | ||
07e4ca50 TI |
1678 | strcpy(card->driver, "HDA-Intel"); |
1679 | strcpy(card->shortname, driver_short_names[chip->driver_type]); | |
1680 | sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq); | |
1681 | ||
1da177e4 LT |
1682 | *rchip = chip; |
1683 | return 0; | |
1684 | ||
1685 | errout: | |
1686 | azx_free(chip); | |
1687 | return err; | |
1688 | } | |
1689 | ||
1690 | static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) | |
1691 | { | |
a98f90fd TI |
1692 | struct snd_card *card; |
1693 | struct azx *chip; | |
927fc866 | 1694 | int err; |
1da177e4 | 1695 | |
b7fe4622 | 1696 | card = snd_card_new(index, id, THIS_MODULE, 0); |
927fc866 | 1697 | if (!card) { |
1da177e4 LT |
1698 | snd_printk(KERN_ERR SFX "Error creating card!\n"); |
1699 | return -ENOMEM; | |
1700 | } | |
1701 | ||
927fc866 PM |
1702 | err = azx_create(card, pci, pci_id->driver_data, &chip); |
1703 | if (err < 0) { | |
1da177e4 LT |
1704 | snd_card_free(card); |
1705 | return err; | |
1706 | } | |
421a1252 | 1707 | card->private_data = chip; |
1da177e4 | 1708 | |
1da177e4 | 1709 | /* create codec instances */ |
b7fe4622 | 1710 | if ((err = azx_codec_create(chip, model)) < 0) { |
1da177e4 LT |
1711 | snd_card_free(card); |
1712 | return err; | |
1713 | } | |
1714 | ||
1715 | /* create PCM streams */ | |
1716 | if ((err = azx_pcm_create(chip)) < 0) { | |
1717 | snd_card_free(card); | |
1718 | return err; | |
1719 | } | |
1720 | ||
1721 | /* create mixer controls */ | |
1722 | if ((err = azx_mixer_create(chip)) < 0) { | |
1723 | snd_card_free(card); | |
1724 | return err; | |
1725 | } | |
1726 | ||
1da177e4 LT |
1727 | snd_card_set_dev(card, &pci->dev); |
1728 | ||
1729 | if ((err = snd_card_register(card)) < 0) { | |
1730 | snd_card_free(card); | |
1731 | return err; | |
1732 | } | |
1733 | ||
1734 | pci_set_drvdata(pci, card); | |
1da177e4 LT |
1735 | |
1736 | return err; | |
1737 | } | |
1738 | ||
1739 | static void __devexit azx_remove(struct pci_dev *pci) | |
1740 | { | |
1741 | snd_card_free(pci_get_drvdata(pci)); | |
1742 | pci_set_drvdata(pci, NULL); | |
1743 | } | |
1744 | ||
1745 | /* PCI IDs */ | |
f40b6890 | 1746 | static struct pci_device_id azx_ids[] = { |
07e4ca50 TI |
1747 | { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */ |
1748 | { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */ | |
1749 | { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */ | |
d2981393 | 1750 | { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */ |
f9cc8a8b JG |
1751 | { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */ |
1752 | { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */ | |
07e4ca50 | 1753 | { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */ |
89be83f8 | 1754 | { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */ |
778b6e1b | 1755 | { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */ |
5b15c95f | 1756 | { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */ |
07e4ca50 TI |
1757 | { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */ |
1758 | { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */ | |
1759 | { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */ | |
5b005a01 PC |
1760 | { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */ |
1761 | { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */ | |
1762 | { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */ | |
1763 | { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */ | |
1764 | { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */ | |
1765 | { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */ | |
1766 | { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */ | |
1767 | { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */ | |
1da177e4 LT |
1768 | { 0, } |
1769 | }; | |
1770 | MODULE_DEVICE_TABLE(pci, azx_ids); | |
1771 | ||
1772 | /* pci_driver definition */ | |
1773 | static struct pci_driver driver = { | |
1774 | .name = "HDA Intel", | |
1775 | .id_table = azx_ids, | |
1776 | .probe = azx_probe, | |
1777 | .remove = __devexit_p(azx_remove), | |
421a1252 TI |
1778 | #ifdef CONFIG_PM |
1779 | .suspend = azx_suspend, | |
1780 | .resume = azx_resume, | |
1781 | #endif | |
1da177e4 LT |
1782 | }; |
1783 | ||
1784 | static int __init alsa_card_azx_init(void) | |
1785 | { | |
01d25d46 | 1786 | return pci_register_driver(&driver); |
1da177e4 LT |
1787 | } |
1788 | ||
1789 | static void __exit alsa_card_azx_exit(void) | |
1790 | { | |
1791 | pci_unregister_driver(&driver); | |
1792 | } | |
1793 | ||
1794 | module_init(alsa_card_azx_init) | |
1795 | module_exit(alsa_card_azx_exit) |