]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - sound/pci/hda/hda_intel.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: usb-audio: work around CH345 input SysEx corruption
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
56#include <asm/cacheflush.h>
57#endif
1da177e4
LT		 58#include <sound/core.h>
59#include <sound/initval.h>
98d8fc6c
ML		 60#include <sound/hdaudio.h>
61#include <sound/hda_i915.h>
9121947d 62#include <linux/vgaarb.h>
a82d51ed 63#include <linux/vga_switcheroo.h>
4918cdab 64#include <linux/firmware.h>
1da177e4 65#include "hda_codec.h"
05e84878 66#include "hda_controller.h"
347de1f8 67#include "hda_intel.h"
1da177e4 68
785d8c4b
LY		 69#define CREATE_TRACE_POINTS
70#include "hda_intel_trace.h"
71
b6050ef6
TI		 72/* position fix mode */
73enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79};
80
9a34af4a
TI		 81/* Defines for ATI HD Audio support in SB450 south bridge */
82#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85/* Defines for Nvidia HDA support */
86#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88#define NVIDIA_HDA_ISTRM_COH 0x4d
89#define NVIDIA_HDA_OSTRM_COH 0x4c
90#define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92/* Defines for Intel SCH HDA snoop control */
93#define INTEL_SCH_HDA_DEVC 0x78
94#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
95
96/* Define IN stream 0 FIFO size offset in VIA controller */
97#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
98/* Define VIA HD Audio Device ID*/
99#define VIA_HDAC_DEVICE_ID 0x3288
100
33124929
TI		 101/* max number of SDs */
102/* ICH, ATI and VIA have 4 playback and 4 capture */
103#define ICH6_NUM_CAPTURE 4
104#define ICH6_NUM_PLAYBACK 4
105
106/* ULI has 6 playback and 5 capture */
107#define ULI_NUM_CAPTURE 5
108#define ULI_NUM_PLAYBACK 6
109
110/* ATI HDMI may have up to 8 playbacks and 0 capture */
111#define ATIHDMI_NUM_CAPTURE 0
112#define ATIHDMI_NUM_PLAYBACK 8
113
114/* TERA has 4 playback and 3 capture */
115#define TERA_NUM_CAPTURE 3
116#define TERA_NUM_PLAYBACK 4
117
1da177e4 118
5aba4f8e
TI		 119static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
120static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 121static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 122static char *model[SNDRV_CARDS];
1dac6695 123static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 124static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 125static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 126static int probe_only[SNDRV_CARDS];
26a6cb6c 127static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 128static bool single_cmd;
71623855 129static int enable_msi = -1;
4ea6fbc8
TI		 130#ifdef CONFIG_SND_HDA_PATCH_LOADER
131static char *patch[SNDRV_CARDS];
132#endif
2dca0bba 133#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 134static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 135 CONFIG_SND_HDA_INPUT_BEEP_MODE};
136#endif
1da177e4 137
5aba4f8e 138module_param_array(index, int, NULL, 0444);
1da177e4 139MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 140module_param_array(id, charp, NULL, 0444);
1da177e4 141MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 142module_param_array(enable, bool, NULL, 0444);
143MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
144module_param_array(model, charp, NULL, 0444);
1da177e4 145MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 146module_param_array(position_fix, int, NULL, 0444);
4cb36310 147MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 148 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 149module_param_array(bdl_pos_adj, int, NULL, 0644);
150MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 151module_param_array(probe_mask, int, NULL, 0444);
606ad75f 152MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 153module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 154MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 155module_param_array(jackpoll_ms, int, NULL, 0444);
156MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 157module_param(single_cmd, bool, 0444);
d01ce99f
TI		 158MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
159 "(for debugging only).");
ac9ef6cf 160module_param(enable_msi, bint, 0444);
134a11f0 161MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 162#ifdef CONFIG_SND_HDA_PATCH_LOADER
163module_param_array(patch, charp, NULL, 0444);
164MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
165#endif
2dca0bba 166#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 167module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 168MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 169 "(0=off, 1=on) (default=1).");
2dca0bba 170#endif
606ad75f 171
83012a7c 172#ifdef CONFIG_PM
65fcd41d 173static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 174static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 175 .set = param_set_xint,
176 .get = param_get_int,
177};
178#define param_check_xint param_check_int
179
fee2fba3 180static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 181module_param(power_save, xint, 0644);
fee2fba3
TI		 182MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
183 "(in second, 0 = disable).");
1da177e4 184
dee1b66c
TI		 185/* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
8fc24426
TI		 189static bool power_save_controller = 1;
190module_param(power_save_controller, bool, 0644);
dee1b66c 191MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 192#else
bb573928 193#define power_save 0
83012a7c 194#endif /* CONFIG_PM */
dee1b66c 195
7bfe059e
TI		 196static int align_buffer_size = -1;
197module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 198MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
27fe48d9 201#ifdef CONFIG_X86
7c732015
TI		 202static int hda_snoop = -1;
203module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 204MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 205#else
206#define hda_snoop true
27fe48d9
TI		 207#endif
208
209
1da177e4
LT		 210MODULE_LICENSE("GPL");
211MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212 "{Intel, ICH6M},"
2f1b3818 213 "{Intel, ICH7},"
f5d40b30 214 "{Intel, ESB2},"
d2981393 215 "{Intel, ICH8},"
f9cc8a8b 216 "{Intel, ICH9},"
c34f5a04 217 "{Intel, ICH10},"
b29c2360 218 "{Intel, PCH},"
d2f2fcd2 219 "{Intel, CPT},"
d2edeb7c 220 "{Intel, PPT},"
8bc039a1 221 "{Intel, LPT},"
144dad99 222 "{Intel, LPT_LP},"
4eeca499 223 "{Intel, WPT_LP},"
c8b00fd2 224 "{Intel, SPT},"
b4565913 225 "{Intel, SPT_LP},"
e926f2c8 226 "{Intel, HPT},"
cea310e8 227 "{Intel, PBG},"
4979bca9 228 "{Intel, SCH},"
fc20a562 229 "{ATI, SB450},"
89be83f8 230 "{ATI, SB600},"
778b6e1b 231 "{ATI, RS600},"
5b15c95f 232 "{ATI, RS690},"
e6db1119
WL		 233 "{ATI, RS780},"
234 "{ATI, R600},"
2797f724
HRK		 235 "{ATI, RV630},"
236 "{ATI, RV610},"
27da1834
WL		 237 "{ATI, RV670},"
238 "{ATI, RV635},"
239 "{ATI, RV620},"
240 "{ATI, RV770},"
fc20a562 241 "{VIA, VT8251},"
47672310 242 "{VIA, VT8237A},"
07e4ca50
TI		 243 "{SiS, SIS966},"
244 "{ULI, M5461}}");
1da177e4
LT		 245MODULE_DESCRIPTION("Intel HDA driver");
246
a82d51ed 247#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 248#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 249#define SUPPORT_VGA_SWITCHEROO
250#endif
251#endif
252
253
1da177e4 254/*
1da177e4 255 */
1da177e4 256
07e4ca50
TI		 257/* driver types */
258enum {
259 AZX_DRIVER_ICH,
32679f95 260 AZX_DRIVER_PCH,
4979bca9 261 AZX_DRIVER_SCH,
fab1285a 262 AZX_DRIVER_HDMI,
07e4ca50 263 AZX_DRIVER_ATI,
778b6e1b 264 AZX_DRIVER_ATIHDMI,
1815b34a 265 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 266 AZX_DRIVER_VIA,
267 AZX_DRIVER_SIS,
268 AZX_DRIVER_ULI,
da3fca21 269 AZX_DRIVER_NVIDIA,
f269002e 270 AZX_DRIVER_TERA,
14d34f16 271 AZX_DRIVER_CTX,
5ae763b1 272 AZX_DRIVER_CTHDA,
c563f473 273 AZX_DRIVER_CMEDIA,
c4da29ca 274 AZX_DRIVER_GENERIC,
2f5983f2 275 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 276};
277
37e661ee
TI		 278#define azx_get_snoop_type(chip) \
279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
280#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
281
b42b4afb
TI		 282/* quirks for old Intel chipsets */
283#define AZX_DCAPS_INTEL_ICH \
103884a3 284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 285
2ea3c6a2 286/* quirks for Intel PCH */
d7dab4db 287#define AZX_DCAPS_INTEL_PCH_NOPM \
103884a3 288 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee 289 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db
TI		 290
291#define AZX_DCAPS_INTEL_PCH \
292 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 293
33499a15 294#define AZX_DCAPS_INTEL_HASWELL \
103884a3 295 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 296 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
297 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 298
54a0405d
LY		 299/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
300#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 301 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 302 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
303 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 304
40cc2392
ML		 305#define AZX_DCAPS_INTEL_BAYTRAIL \
306 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
307
2d846c74
LY		 308#define AZX_DCAPS_INTEL_BRASWELL \
309 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
310
d6795827 311#define AZX_DCAPS_INTEL_SKYLAKE \
2d846c74
LY		 312 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
313 AZX_DCAPS_I915_POWERWELL)
d6795827 314
9477c58e
TI		 315/* quirks for ATI SB / AMD Hudson */
316#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 317 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
318 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 319
320/* quirks for ATI/AMD HDMI */
321#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 322 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
323 AZX_DCAPS_NO_MSI64)
9477c58e 324
37e661ee
TI		 325/* quirks for ATI HDMI with snoop off */
326#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
327 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
328
9477c58e
TI		 329/* quirks for Nvidia */
330#define AZX_DCAPS_PRESET_NVIDIA \
103884a3 331 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
37e661ee
TI		 332 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
333 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 334
5ae763b1 335#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 336 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 337 AZX_DCAPS_NO_64BIT |\
37e661ee 338 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 339
a82d51ed
TI		 340/*
341 * VGA-switcher support
342 */
343#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 344#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
345#else
346#define use_vga_switcheroo(chip) 0
347#endif
348
03b135ce
LY		 349#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
350 ((pci)->device == 0x0c0c) || \
351 ((pci)->device == 0x0d0c) || \
352 ((pci)->device == 0x160c))
353
48c8b0eb 354static char *driver_short_names[] = {
07e4ca50 355 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 356 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 357 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 358 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 359 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 360 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 361 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 362 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
363 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 364 [AZX_DRIVER_ULI] = "HDA ULI M5461",
365 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 366 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 367 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 368 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 369 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 370 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 371};
372
27fe48d9 373#ifdef CONFIG_X86
9ddf1aeb 374static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 375{
9ddf1aeb
TI		 376 int pages;
377
27fe48d9
TI		 378 if (azx_snoop(chip))
379 return;
9ddf1aeb
TI		 380 if (!dmab || !dmab->area || !dmab->bytes)
381 return;
382
383#ifdef CONFIG_SND_DMA_SGBUF
384 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
385 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 386 if (chip->driver_type == AZX_DRIVER_CMEDIA)
387 return; /* deal with only CORB/RIRB buffers */
27fe48d9 388 if (on)
9ddf1aeb 389 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 390 else
9ddf1aeb
TI		 391 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
392 return;
27fe48d9 393 }
9ddf1aeb
TI		 394#endif
395
396 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
397 if (on)
398 set_memory_wc((unsigned long)dmab->area, pages);
399 else
400 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 401}
402
403static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
404 bool on)
405{
9ddf1aeb 406 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 407}
408static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 409 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 410{
411 if (azx_dev->wc_marked != on) {
9ddf1aeb 412 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 413 azx_dev->wc_marked = on;
414 }
415}
416#else
417/* NOP for other archs */
418static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
419 bool on)
420{
421}
422static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 423 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 424{
425}
426#endif
427
68e7fffc 428static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 429
cb53c626
TI		 430/*
431 * initialize the PCI registers
432 */
433/* update bits in a PCI register byte */
434static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
435 unsigned char mask, unsigned char val)
436{
437 unsigned char data;
438
439 pci_read_config_byte(pci, reg, &data);
440 data &= ~mask;
441 data |= (val & mask);
442 pci_write_config_byte(pci, reg, data);
443}
444
445static void azx_init_pci(struct azx *chip)
446{
37e661ee
TI		 447 int snoop_type = azx_get_snoop_type(chip);
448
cb53c626
TI		 449 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
450 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
451 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 452 * codecs.
453 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 454 */
46f2cc80 455 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 456 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 457 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 458 }
cb53c626 459
9477c58e
TI		 460 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
461 * we need to enable snoop.
462 */
37e661ee 463 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 464 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
465 azx_snoop(chip));
cb53c626 466 update_pci_byte(chip->pci,
27fe48d9
TI		 467 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
468 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 469 }
470
471 /* For NVIDIA HDA, enable snoop */
37e661ee 472 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 473 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
474 azx_snoop(chip));
cb53c626
TI		 475 update_pci_byte(chip->pci,
476 NVIDIA_HDA_TRANSREG_ADDR,
477 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 478 update_pci_byte(chip->pci,
479 NVIDIA_HDA_ISTRM_COH,
480 0x01, NVIDIA_HDA_ENABLE_COHBIT);
481 update_pci_byte(chip->pci,
482 NVIDIA_HDA_OSTRM_COH,
483 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 484 }
485
486 /* Enable SCH/PCH snoop if needed */
37e661ee 487 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 488 unsigned short snoop;
90a5ad52 489 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 490 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
491 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
492 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
493 if (!azx_snoop(chip))
494 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
495 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 496 pci_read_config_word(chip->pci,
497 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 498 }
4e76a883
TI		 499 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
500 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
501 "Disabled" : "Enabled");
da3fca21 502 }
1da177e4
LT		 503}
504
0a673521
LH		 505static void hda_intel_init_chip(struct azx *chip, bool full_reset)
506{
98d8fc6c 507 struct hdac_bus *bus = azx_bus(chip);
0a673521
LH		 508
509 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 510 snd_hdac_set_codec_wakeup(bus, true);
0a673521
LH		 511 azx_init_chip(chip, full_reset);
512 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 513 snd_hdac_set_codec_wakeup(bus, false);
0a673521
LH		 514}
515
b6050ef6
TI		 516/* calculate runtime delay from LPIB */
517static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
518 unsigned int pos)
519{
7833c3f8 520 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 521 int stream = substream->stream;
522 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
523 int delay;
524
525 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
526 delay = pos - lpib_pos;
527 else
528 delay = lpib_pos - pos;
529 if (delay < 0) {
7833c3f8 530 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 531 delay = 0;
532 else
7833c3f8 533 delay += azx_dev->core.bufsize;
b6050ef6
TI		 534 }
535
7833c3f8 536 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 537 dev_info(chip->card->dev,
538 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 539 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 540 delay = 0;
541 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
542 chip->get_delay[stream] = NULL;
543 }
544
545 return bytes_to_frames(substream->runtime, delay);
546}
547
9ad593f6
TI		 548static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
549
7ca954a8
DR		 550/* called from IRQ */
551static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
552{
9a34af4a 553 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 554 int ok;
555
556 ok = azx_position_ok(chip, azx_dev);
557 if (ok == 1) {
558 azx_dev->irq_pending = 0;
559 return ok;
2f35c630 560 } else if (ok == 0) {
7ca954a8
DR		 561 /* bogus IRQ, process it later */
562 azx_dev->irq_pending = 1;
2f35c630 563 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 564 }
565 return 0;
566}
567
17eccb27
ML		 568/* Enable/disable i915 display power for the link */
569static int azx_intel_link_power(struct azx *chip, bool enable)
570{
98d8fc6c 571 struct hdac_bus *bus = azx_bus(chip);
17eccb27 572
98d8fc6c 573 return snd_hdac_display_power(bus, enable);
17eccb27
ML		 574}
575
9ad593f6
TI		 576/*
577 * Check whether the current DMA position is acceptable for updating
578 * periods. Returns non-zero if it's OK.
579 *
580 * Many HD-audio controllers appear pretty inaccurate about
581 * the update-IRQ timing. The IRQ is issued before actually the
582 * data is processed. So, we need to process it afterwords in a
583 * workqueue.
584 */
585static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
586{
7833c3f8 587 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 588 int stream = substream->stream;
e5463720 589 u32 wallclk;
9ad593f6
TI		 590 unsigned int pos;
591
7833c3f8
TI		 592 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
593 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 594 return -1; /* bogus (too early) interrupt */
fa00e046 595
b6050ef6
TI		 596 if (chip->get_position[stream])
597 pos = chip->get_position[stream](chip, azx_dev);
598 else { /* use the position buffer as default */
599 pos = azx_get_pos_posbuf(chip, azx_dev);
600 if (!pos || pos == (u32)-1) {
601 dev_info(chip->card->dev,
602 "Invalid position buffer, using LPIB read method instead.\n");
603 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 604 if (chip->get_position[0] == azx_get_pos_lpib &&
605 chip->get_position[1] == azx_get_pos_lpib)
606 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 607 pos = azx_get_pos_lpib(chip, azx_dev);
608 chip->get_delay[stream] = NULL;
609 } else {
610 chip->get_position[stream] = azx_get_pos_posbuf;
611 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
612 chip->get_delay[stream] = azx_get_delay_from_lpib;
613 }
614 }
615
7833c3f8 616 if (pos >= azx_dev->core.bufsize)
b6050ef6 617 pos = 0;
9ad593f6 618
7833c3f8 619 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 620 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 621 return -1; /* this shouldn't happen! */
7833c3f8
TI		 622 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
623 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 624 /* NG - it's below the first next period boundary */
9cdc0115 625 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
7833c3f8 626 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 627 return 1; /* OK, it's fine */
628}
629
630/*
631 * The work for pending PCM period updates.
632 */
633static void azx_irq_pending_work(struct work_struct *work)
634{
9a34af4a
TI		 635 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
636 struct azx *chip = &hda->chip;
7833c3f8
TI		 637 struct hdac_bus *bus = azx_bus(chip);
638 struct hdac_stream *s;
639 int pending, ok;
9ad593f6 640
9a34af4a 641 if (!hda->irq_pending_warned) {
4e76a883
TI		 642 dev_info(chip->card->dev,
643 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
644 chip->card->number);
9a34af4a 645 hda->irq_pending_warned = 1;
a6a950a8
TI		 646 }
647
9ad593f6
TI		 648 for (;;) {
649 pending = 0;
a41d1224 650 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 651 list_for_each_entry(s, &bus->stream_list, list) {
652 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 653 if (!azx_dev->irq_pending ||
7833c3f8
TI		 654 !s->substream ||
655 !s->running)
9ad593f6 656 continue;
e5463720
JK		 657 ok = azx_position_ok(chip, azx_dev);
658 if (ok > 0) {
9ad593f6 659 azx_dev->irq_pending = 0;
a41d1224 660 spin_unlock(&bus->reg_lock);
7833c3f8 661 snd_pcm_period_elapsed(s->substream);
a41d1224 662 spin_lock(&bus->reg_lock);
e5463720
JK		 663 } else if (ok < 0) {
664 pending = 0; /* too early */
9ad593f6
TI		 665 } else
666 pending++;
667 }
a41d1224 668 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 669 if (!pending)
670 return;
08af495f 671 msleep(1);
9ad593f6
TI		 672 }
673}
674
675/* clear irq_pending flags and assure no on-going workq */
676static void azx_clear_irq_pending(struct azx *chip)
677{
7833c3f8
TI		 678 struct hdac_bus *bus = azx_bus(chip);
679 struct hdac_stream *s;
9ad593f6 680
a41d1224 681 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 682 list_for_each_entry(s, &bus->stream_list, list) {
683 struct azx_dev *azx_dev = stream_to_azx_dev(s);
684 azx_dev->irq_pending = 0;
685 }
a41d1224 686 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 687}
688
68e7fffc
TI		 689static int azx_acquire_irq(struct azx *chip, int do_disconnect)
690{
a41d1224
TI		 691 struct hdac_bus *bus = azx_bus(chip);
692
437a5a46
TI		 693 if (request_irq(chip->pci->irq, azx_interrupt,
694 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 695 KBUILD_MODNAME, chip)) {
4e76a883
TI		 696 dev_err(chip->card->dev,
697 "unable to grab IRQ %d, disabling device\n",
698 chip->pci->irq);
68e7fffc
TI		 699 if (do_disconnect)
700 snd_card_disconnect(chip->card);
701 return -1;
702 }
a41d1224 703 bus->irq = chip->pci->irq;
69e13418 704 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 705 return 0;
706}
707
b6050ef6
TI		 708/* get the current DMA position with correction on VIA chips */
709static unsigned int azx_via_get_position(struct azx *chip,
710 struct azx_dev *azx_dev)
711{
712 unsigned int link_pos, mini_pos, bound_pos;
713 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
714 unsigned int fifo_size;
715
1604eeee 716 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 717 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 718 /* Playback, no problem using link position */
719 return link_pos;
720 }
721
722 /* Capture */
723 /* For new chipset,
724 * use mod to get the DMA position just like old chipset
725 */
7833c3f8
TI		 726 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
727 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 728
729 /* azx_dev->fifo_size can't get FIFO size of in stream.
730 * Get from base address + offset.
731 */
a41d1224
TI		 732 fifo_size = readw(azx_bus(chip)->remap_addr +
733 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 734
735 if (azx_dev->insufficient) {
736 /* Link position never gather than FIFO size */
737 if (link_pos <= fifo_size)
738 return 0;
739
740 azx_dev->insufficient = 0;
741 }
742
743 if (link_pos <= fifo_size)
7833c3f8 744 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 745 else
746 mini_pos = link_pos - fifo_size;
747
748 /* Find nearest previous boudary */
7833c3f8
TI		 749 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
750 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 751 if (mod_link_pos >= fifo_size)
752 bound_pos = link_pos - mod_link_pos;
753 else if (mod_dma_pos >= mod_mini_pos)
754 bound_pos = mini_pos - mod_mini_pos;
755 else {
7833c3f8
TI		 756 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
757 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 758 bound_pos = 0;
759 }
760
761 /* Calculate real DMA position we want */
762 return bound_pos + mod_dma_pos;
763}
764
83012a7c 765#ifdef CONFIG_PM
65fcd41d
TI		 766static DEFINE_MUTEX(card_list_lock);
767static LIST_HEAD(card_list);
768
769static void azx_add_card_list(struct azx *chip)
770{
9a34af4a 771 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 772 mutex_lock(&card_list_lock);
9a34af4a 773 list_add(&hda->list, &card_list);
65fcd41d
TI		 774 mutex_unlock(&card_list_lock);
775}
776
777static void azx_del_card_list(struct azx *chip)
778{
9a34af4a 779 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 780 mutex_lock(&card_list_lock);
9a34af4a 781 list_del_init(&hda->list);
65fcd41d
TI		 782 mutex_unlock(&card_list_lock);
783}
784
785/* trigger power-save check at writing parameter */
786static int param_set_xint(const char *val, const struct kernel_param *kp)
787{
9a34af4a 788 struct hda_intel *hda;
65fcd41d 789 struct azx *chip;
65fcd41d
TI		 790 int prev = power_save;
791 int ret = param_set_int(val, kp);
792
793 if (ret || prev == power_save)
794 return ret;
795
796 mutex_lock(&card_list_lock);
9a34af4a
TI		 797 list_for_each_entry(hda, &card_list, list) {
798 chip = &hda->chip;
a41d1224 799 if (!hda->probe_continued || chip->disabled)
65fcd41d 800 continue;
a41d1224 801 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 802 }
803 mutex_unlock(&card_list_lock);
804 return 0;
805}
806#else
807#define azx_add_card_list(chip) /* NOP */
808#define azx_del_card_list(chip) /* NOP */
83012a7c 809#endif /* CONFIG_PM */
5c0b9bec 810
98d8fc6c
ML		 811/* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
812 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
813 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
814 * BCLK = CDCLK * M / N
815 * The values will be lost when the display power well is disabled and need to
816 * be restored to avoid abnormal playback speed.
817 */
818static void haswell_set_bclk(struct hda_intel *hda)
819{
820 struct azx *chip = &hda->chip;
821 int cdclk_freq;
822 unsigned int bclk_m, bclk_n;
823
824 if (!hda->need_i915_power)
825 return;
826
827 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
828 switch (cdclk_freq) {
829 case 337500:
830 bclk_m = 16;
831 bclk_n = 225;
832 break;
833
834 case 450000:
835 default: /* default CDCLK 450MHz */
836 bclk_m = 4;
837 bclk_n = 75;
838 break;
839
840 case 540000:
841 bclk_m = 4;
842 bclk_n = 90;
843 break;
844
845 case 675000:
846 bclk_m = 8;
847 bclk_n = 225;
848 break;
849 }
850
851 azx_writew(chip, HSW_EM4, bclk_m);
852 azx_writew(chip, HSW_EM5, bclk_n);
853}
854
7ccbde57 855#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 856/*
857 * power management
858 */
68cb2b55 859static int azx_suspend(struct device *dev)
1da177e4 860{
68cb2b55 861 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 862 struct azx *chip;
863 struct hda_intel *hda;
a41d1224 864 struct hdac_bus *bus;
1da177e4 865
2d9772ef
TI		 866 if (!card)
867 return 0;
868
869 chip = card->private_data;
870 hda = container_of(chip, struct hda_intel, chip);
342e8449 871 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 872 return 0;
873
a41d1224 874 bus = azx_bus(chip);
421a1252 875 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 876 azx_clear_irq_pending(chip);
cb53c626 877 azx_stop_chip(chip);
7295b264 878 azx_enter_link_reset(chip);
a41d1224
TI		 879 if (bus->irq >= 0) {
880 free_irq(bus->irq, chip);
881 bus->irq = -1;
30b35399 882 }
a07187c9 883
68e7fffc 884 if (chip->msi)
43001c95 885 pci_disable_msi(chip->pci);
795614dd
ML		 886 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
887 && hda->need_i915_power)
98d8fc6c 888 snd_hdac_display_power(bus, false);
785d8c4b
LY		 889
890 trace_azx_suspend(chip);
1da177e4
LT		 891 return 0;
892}
893
68cb2b55 894static int azx_resume(struct device *dev)
1da177e4 895{
68cb2b55
TI		 896 struct pci_dev *pci = to_pci_dev(dev);
897 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 898 struct azx *chip;
899 struct hda_intel *hda;
900
901 if (!card)
902 return 0;
1da177e4 903
2d9772ef
TI		 904 chip = card->private_data;
905 hda = container_of(chip, struct hda_intel, chip);
342e8449 906 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 907 return 0;
908
795614dd
ML		 909 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
910 && hda->need_i915_power) {
98d8fc6c 911 snd_hdac_display_power(azx_bus(chip), true);
926981ae 912 haswell_set_bclk(hda);
a07187c9 913 }
68e7fffc
TI		 914 if (chip->msi)
915 if (pci_enable_msi(pci) < 0)
916 chip->msi = 0;
917 if (azx_acquire_irq(chip, 1) < 0)
30b35399 918 return -EIO;
cb53c626 919 azx_init_pci(chip);
d804ad92 920
0a673521 921 hda_intel_init_chip(chip, true);
d804ad92 922
421a1252 923 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 924
925 trace_azx_resume(chip);
1da177e4
LT		 926 return 0;
927}
b8dfc462
ML		 928#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
929
641d334b 930#ifdef CONFIG_PM
b8dfc462
ML		 931static int azx_runtime_suspend(struct device *dev)
932{
933 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 934 struct azx *chip;
935 struct hda_intel *hda;
b8dfc462 936
2d9772ef
TI		 937 if (!card)
938 return 0;
939
940 chip = card->private_data;
941 hda = container_of(chip, struct hda_intel, chip);
1618e84a 942 if (chip->disabled || hda->init_failed)
246efa4a
DA		 943 return 0;
944
364aa716 945 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 946 return 0;
947
7d4f606c
WX		 948 /* enable controller wake up event */
949 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
950 STATESTS_INT_MASK);
951
b8dfc462 952 azx_stop_chip(chip);
873ce8ad 953 azx_enter_link_reset(chip);
b8dfc462 954 azx_clear_irq_pending(chip);
795614dd
ML		 955 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
956 && hda->need_i915_power)
98d8fc6c 957 snd_hdac_display_power(azx_bus(chip), false);
e4d9e513 958
785d8c4b 959 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 960 return 0;
961}
962
963static int azx_runtime_resume(struct device *dev)
964{
965 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 966 struct azx *chip;
967 struct hda_intel *hda;
98d8fc6c 968 struct hdac_bus *bus;
7d4f606c
WX		 969 struct hda_codec *codec;
970 int status;
b8dfc462 971
2d9772ef
TI		 972 if (!card)
973 return 0;
974
975 chip = card->private_data;
976 hda = container_of(chip, struct hda_intel, chip);
1618e84a 977 if (chip->disabled || hda->init_failed)
246efa4a
DA		 978 return 0;
979
364aa716 980 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 981 return 0;
982
033ea349
DH		 983 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
984 bus = azx_bus(chip);
985 if (hda->need_i915_power) {
986 snd_hdac_display_power(bus, true);
987 haswell_set_bclk(hda);
988 } else {
989 /* toggle codec wakeup bit for STATESTS read */
990 snd_hdac_set_codec_wakeup(bus, true);
991 snd_hdac_set_codec_wakeup(bus, false);
992 }
a07187c9 993 }
7d4f606c
WX		 994
995 /* Read STATESTS before controller reset */
996 status = azx_readw(chip, STATESTS);
997
b8dfc462 998 azx_init_pci(chip);
0a673521 999 hda_intel_init_chip(chip, true);
7d4f606c 1000
a41d1224
TI		 1001 if (status) {
1002 list_for_each_codec(codec, &chip->bus)
7d4f606c 1003 if (status & (1 << codec->addr))
2f35c630
TI		 1004 schedule_delayed_work(&codec->jackpoll_work,
1005 codec->jackpoll_interval);
7d4f606c
WX		 1006 }
1007
1008 /* disable controller Wake Up event*/
1009 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1010 ~STATESTS_INT_MASK);
1011
785d8c4b 1012 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1013 return 0;
1014}
6eb827d2
TI		 1015
1016static int azx_runtime_idle(struct device *dev)
1017{
1018 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1019 struct azx *chip;
1020 struct hda_intel *hda;
1021
1022 if (!card)
1023 return 0;
6eb827d2 1024
2d9772ef
TI		 1025 chip = card->private_data;
1026 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1027 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1028 return 0;
1029
55ed9cd1 1030 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1031 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1032 return -EBUSY;
1033
1034 return 0;
1035}
1036
b8dfc462
ML		 1037static const struct dev_pm_ops azx_pm = {
1038 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 1039 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1040};
1041
68cb2b55
TI		 1042#define AZX_PM_OPS &azx_pm
1043#else
68cb2b55 1044#define AZX_PM_OPS NULL
b8dfc462 1045#endif /* CONFIG_PM */
1da177e4
LT		 1046
1047
48c8b0eb 1048static int azx_probe_continue(struct azx *chip);
a82d51ed 1049
8393ec4a 1050#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1051static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1052
a82d51ed
TI		 1053static void azx_vs_set_state(struct pci_dev *pci,
1054 enum vga_switcheroo_state state)
1055{
1056 struct snd_card *card = pci_get_drvdata(pci);
1057 struct azx *chip = card->private_data;
9a34af4a 1058 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1059 bool disabled;
1060
9a34af4a
TI		 1061 wait_for_completion(&hda->probe_wait);
1062 if (hda->init_failed)
a82d51ed
TI		 1063 return;
1064
1065 disabled = (state == VGA_SWITCHEROO_OFF);
1066 if (chip->disabled == disabled)
1067 return;
1068
a41d1224 1069 if (!hda->probe_continued) {
a82d51ed
TI		 1070 chip->disabled = disabled;
1071 if (!disabled) {
4e76a883
TI		 1072 dev_info(chip->card->dev,
1073 "Start delayed initialization\n");
5c90680e 1074 if (azx_probe_continue(chip) < 0) {
4e76a883 1075 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1076 hda->init_failed = true;
a82d51ed
TI		 1077 }
1078 }
1079 } else {
4e76a883
TI		 1080 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1081 disabled ? "Disabling" : "Enabling");
a82d51ed 1082 if (disabled) {
8928756d
DR		 1083 pm_runtime_put_sync_suspend(card->dev);
1084 azx_suspend(card->dev);
246efa4a
DA		 1085 /* when we get suspended by vga switcheroo we end up in D3cold,
1086 * however we have no ACPI handle, so pci/acpi can't put us there,
1087 * put ourselves there */
1088 pci->current_state = PCI_D3cold;
a82d51ed 1089 chip->disabled = true;
a41d1224 1090 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1091 dev_warn(chip->card->dev,
1092 "Cannot lock devices!\n");
a82d51ed 1093 } else {
a41d1224 1094 snd_hda_unlock_devices(&chip->bus);
8928756d 1095 pm_runtime_get_noresume(card->dev);
a82d51ed 1096 chip->disabled = false;
8928756d 1097 azx_resume(card->dev);
a82d51ed
TI		 1098 }
1099 }
1100}
1101
1102static bool azx_vs_can_switch(struct pci_dev *pci)
1103{
1104 struct snd_card *card = pci_get_drvdata(pci);
1105 struct azx *chip = card->private_data;
9a34af4a 1106 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1107
9a34af4a
TI		 1108 wait_for_completion(&hda->probe_wait);
1109 if (hda->init_failed)
a82d51ed 1110 return false;
a41d1224 1111 if (chip->disabled || !hda->probe_continued)
a82d51ed 1112 return true;
a41d1224 1113 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1114 return false;
a41d1224 1115 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1116 return true;
1117}
1118
e23e7a14 1119static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1120{
9a34af4a 1121 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1122 struct pci_dev *p = get_bound_vga(chip->pci);
1123 if (p) {
4e76a883
TI		 1124 dev_info(chip->card->dev,
1125 "Handle VGA-switcheroo audio client\n");
9a34af4a 1126 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1127 pci_dev_put(p);
1128 }
1129}
1130
1131static const struct vga_switcheroo_client_ops azx_vs_ops = {
1132 .set_gpu_state = azx_vs_set_state,
1133 .can_switch = azx_vs_can_switch,
1134};
1135
e23e7a14 1136static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1137{
9a34af4a 1138 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1139 int err;
1140
9a34af4a 1141 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1142 return 0;
1143 /* FIXME: currently only handling DIS controller
1144 * is there any machine with two switchable HDMI audio controllers?
1145 */
128960a9 1146 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed 1147 VGA_SWITCHEROO_DIS,
a41d1224 1148 hda->probe_continued);
128960a9
TI		 1149 if (err < 0)
1150 return err;
9a34af4a 1151 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1152
1153 /* register as an optimus hdmi audio power domain */
8928756d 1154 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1155 &hda->hdmi_pm_domain);
128960a9 1156 return 0;
a82d51ed
TI		 1157}
1158#else
1159#define init_vga_switcheroo(chip) /* NOP */
1160#define register_vga_switcheroo(chip) 0
8393ec4a 1161#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1162#endif /* SUPPORT_VGA_SWITCHER */
1163
1da177e4
LT		 1164/*
1165 * destructor
1166 */
a98f90fd 1167static int azx_free(struct azx *chip)
1da177e4 1168{
c67e2228 1169 struct pci_dev *pci = chip->pci;
a07187c9 1170 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1171 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1172
364aa716 1173 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1174 pm_runtime_get_noresume(&pci->dev);
1175
65fcd41d
TI		 1176 azx_del_card_list(chip);
1177
9a34af4a
TI		 1178 hda->init_failed = 1; /* to be sure */
1179 complete_all(&hda->probe_wait);
f4c482a4 1180
9a34af4a 1181 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1182 if (chip->disabled && hda->probe_continued)
1183 snd_hda_unlock_devices(&chip->bus);
9a34af4a 1184 if (hda->vga_switcheroo_registered)
128960a9 1185 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1186 }
1187
a41d1224 1188 if (bus->chip_init) {
9ad593f6 1189 azx_clear_irq_pending(chip);
7833c3f8 1190 azx_stop_all_streams(chip);
cb53c626 1191 azx_stop_chip(chip);
1da177e4
LT		 1192 }
1193
a41d1224
TI		 1194 if (bus->irq >= 0)
1195 free_irq(bus->irq, (void*)chip);
68e7fffc 1196 if (chip->msi)
30b35399 1197 pci_disable_msi(chip->pci);
a41d1224 1198 iounmap(bus->remap_addr);
1da177e4 1199
67908994 1200 azx_free_stream_pages(chip);
a41d1224
TI		 1201 azx_free_streams(chip);
1202 snd_hdac_bus_exit(bus);
1203
a82d51ed
TI		 1204 if (chip->region_requested)
1205 pci_release_regions(chip->pci);
a41d1224 1206
1da177e4 1207 pci_disable_device(chip->pci);
4918cdab 1208#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1209 release_firmware(chip->fw);
4918cdab 1210#endif
98d8fc6c 1211
99a2008d 1212 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
795614dd 1213 if (hda->need_i915_power)
98d8fc6c
ML		 1214 snd_hdac_display_power(bus, false);
1215 snd_hdac_i915_exit(bus);
99a2008d 1216 }
a07187c9 1217 kfree(hda);
1da177e4
LT		 1218
1219 return 0;
1220}
1221
a41d1224
TI		 1222static int azx_dev_disconnect(struct snd_device *device)
1223{
1224 struct azx *chip = device->device_data;
1225
1226 chip->bus.shutdown = 1;
1227 return 0;
1228}
1229
a98f90fd 1230static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1231{
1232 return azx_free(device->device_data);
1233}
1234
8393ec4a 1235#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 1236/*
1237 * Check of disabled HDMI controller by vga-switcheroo
1238 */
e23e7a14 1239static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1240{
1241 struct pci_dev *p;
1242
1243 /* check only discrete GPU */
1244 switch (pci->vendor) {
1245 case PCI_VENDOR_ID_ATI:
1246 case PCI_VENDOR_ID_AMD:
1247 case PCI_VENDOR_ID_NVIDIA:
1248 if (pci->devfn == 1) {
1249 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1250 pci->bus->number, 0);
1251 if (p) {
1252 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1253 return p;
1254 pci_dev_put(p);
1255 }
1256 }
1257 break;
1258 }
1259 return NULL;
1260}
1261
e23e7a14 1262static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1263{
1264 bool vga_inactive = false;
1265 struct pci_dev *p = get_bound_vga(pci);
1266
1267 if (p) {
12b78a7f 1268 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1269 vga_inactive = true;
1270 pci_dev_put(p);
1271 }
1272 return vga_inactive;
1273}
8393ec4a 1274#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1275
3372a153
TI		 1276/*
1277 * white/black-listing for position_fix
1278 */
e23e7a14 1279static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1280 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1281 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1282 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1283 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1284 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1285 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1286 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1287 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1288 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1289 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1290 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1291 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1292 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1293 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1294 {}
1295};
1296
e23e7a14 1297static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1298{
1299 const struct snd_pci_quirk *q;
1300
c673ba1c 1301 switch (fix) {
1dac6695 1302 case POS_FIX_AUTO:
c673ba1c
TI		 1303 case POS_FIX_LPIB:
1304 case POS_FIX_POSBUF:
4cb36310 1305 case POS_FIX_VIACOMBO:
a6f2fd55 1306 case POS_FIX_COMBO:
c673ba1c
TI		 1307 return fix;
1308 }
1309
c673ba1c
TI		 1310 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1311 if (q) {
4e76a883
TI		 1312 dev_info(chip->card->dev,
1313 "position_fix set to %d for device %04x:%04x\n",
1314 q->value, q->subvendor, q->subdevice);
c673ba1c 1315 return q->value;
3372a153 1316 }
bdd9ef24
DH		 1317
1318 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1319 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1320 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1321 return POS_FIX_VIACOMBO;
9477c58e
TI		 1322 }
1323 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1324 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1325 return POS_FIX_LPIB;
bdd9ef24 1326 }
c673ba1c 1327 return POS_FIX_AUTO;
3372a153
TI		 1328}
1329
b6050ef6
TI		 1330static void assign_position_fix(struct azx *chip, int fix)
1331{
1332 static azx_get_pos_callback_t callbacks[] = {
1333 [POS_FIX_AUTO] = NULL,
1334 [POS_FIX_LPIB] = azx_get_pos_lpib,
1335 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1336 [POS_FIX_VIACOMBO] = azx_via_get_position,
1337 [POS_FIX_COMBO] = azx_get_pos_lpib,
1338 };
1339
1340 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1341
1342 /* combo mode uses LPIB only for playback */
1343 if (fix == POS_FIX_COMBO)
1344 chip->get_position[1] = NULL;
1345
1346 if (fix == POS_FIX_POSBUF &&
1347 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1348 chip->get_delay[0] = chip->get_delay[1] =
1349 azx_get_delay_from_lpib;
1350 }
1351
1352}
1353
669ba27a
TI		 1354/*
1355 * black-lists for probe_mask
1356 */
e23e7a14 1357static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1358 /* Thinkpad often breaks the controller communication when accessing
1359 * to the non-working (or non-existing) modem codec slot.
1360 */
1361 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1362 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1363 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1364 /* broken BIOS */
1365 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1366 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1367 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1368 /* forced codec slots */
93574844 1369 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1370 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1371 /* WinFast VP200 H (Teradici) user reported broken communication */
1372 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1373 {}
1374};
1375
f1eaaeec
TI		 1376#define AZX_FORCE_CODEC_MASK 0x100
1377
e23e7a14 1378static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1379{
1380 const struct snd_pci_quirk *q;
1381
f1eaaeec
TI		 1382 chip->codec_probe_mask = probe_mask[dev];
1383 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1384 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1385 if (q) {
4e76a883
TI		 1386 dev_info(chip->card->dev,
1387 "probe_mask set to 0x%x for device %04x:%04x\n",
1388 q->value, q->subvendor, q->subdevice);
f1eaaeec 1389 chip->codec_probe_mask = q->value;
669ba27a
TI		 1390 }
1391 }
f1eaaeec
TI		 1392
1393 /* check forced option */
1394 if (chip->codec_probe_mask != -1 &&
1395 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1396 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1397 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1398 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1399 }
669ba27a
TI		 1400}
1401
4d8e22e0 1402/*
71623855 1403 * white/black-list for enable_msi
4d8e22e0 1404 */
e23e7a14 1405static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1406 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1407 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1408 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1409 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1410 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1411 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1412 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1413 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1414 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1415 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1416 {}
1417};
1418
e23e7a14 1419static void check_msi(struct azx *chip)
4d8e22e0
TI		 1420{
1421 const struct snd_pci_quirk *q;
1422
71623855
TI		 1423 if (enable_msi >= 0) {
1424 chip->msi = !!enable_msi;
4d8e22e0 1425 return;
71623855
TI		 1426 }
1427 chip->msi = 1; /* enable MSI as default */
1428 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1429 if (q) {
4e76a883
TI		 1430 dev_info(chip->card->dev,
1431 "msi for device %04x:%04x set to %d\n",
1432 q->subvendor, q->subdevice, q->value);
4d8e22e0 1433 chip->msi = q->value;
80c43ed7
TI		 1434 return;
1435 }
1436
1437 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1438 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1439 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1440 chip->msi = 0;
4d8e22e0
TI		 1441 }
1442}
1443
a1585d76 1444/* check the snoop mode availability */
e23e7a14 1445static void azx_check_snoop_available(struct azx *chip)
a1585d76 1446{
7c732015 1447 int snoop = hda_snoop;
a1585d76 1448
7c732015
TI		 1449 if (snoop >= 0) {
1450 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1451 snoop ? "snoop" : "non-snoop");
1452 chip->snoop = snoop;
1453 return;
1454 }
1455
1456 snoop = true;
37e661ee
TI		 1457 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1458 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1459 /* force to non-snoop mode for a new VIA controller
1460 * when BIOS is set
1461 */
7c732015
TI		 1462 u8 val;
1463 pci_read_config_byte(chip->pci, 0x42, &val);
1464 if (!(val & 0x80) && chip->pci->revision == 0x30)
1465 snoop = false;
a1585d76
TI		 1466 }
1467
37e661ee
TI		 1468 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1469 snoop = false;
1470
7c732015
TI		 1471 chip->snoop = snoop;
1472 if (!snoop)
1473 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1474}
669ba27a 1475
99a2008d
WX		 1476static void azx_probe_work(struct work_struct *work)
1477{
9a34af4a
TI		 1478 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1479 azx_probe_continue(&hda->chip);
99a2008d 1480}
99a2008d 1481
1da177e4
LT		 1482/*
1483 * constructor
1484 */
a43ff5ba
TI		 1485static const struct hdac_io_ops pci_hda_io_ops;
1486static const struct hda_controller_ops pci_hda_ops;
1487
e23e7a14
BP		 1488static int azx_create(struct snd_card *card, struct pci_dev *pci,
1489 int dev, unsigned int driver_caps,
1490 struct azx **rchip)
1da177e4 1491{
a98f90fd 1492 static struct snd_device_ops ops = {
a41d1224 1493 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1494 .dev_free = azx_dev_free,
1495 };
a07187c9 1496 struct hda_intel *hda;
a82d51ed
TI		 1497 struct azx *chip;
1498 int err;
1da177e4
LT		 1499
1500 *rchip = NULL;
bcd72003 1501
927fc866
PM		 1502 err = pci_enable_device(pci);
1503 if (err < 0)
1da177e4
LT		 1504 return err;
1505
a07187c9
ML		 1506 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1507 if (!hda) {
1da177e4
LT		 1508 pci_disable_device(pci);
1509 return -ENOMEM;
1510 }
1511
a07187c9 1512 chip = &hda->chip;
62932df8 1513 mutex_init(&chip->open_mutex);
1da177e4
LT		 1514 chip->card = card;
1515 chip->pci = pci;
a43ff5ba 1516 chip->ops = &pci_hda_ops;
9477c58e
TI		 1517 chip->driver_caps = driver_caps;
1518 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1519 check_msi(chip);
555e219f 1520 chip->dev_index = dev;
749ee287 1521 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1522 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1523 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1524 INIT_LIST_HEAD(&hda->list);
a82d51ed 1525 init_vga_switcheroo(chip);
9a34af4a 1526 init_completion(&hda->probe_wait);
1da177e4 1527
b6050ef6 1528 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1529
5aba4f8e 1530 check_probe_mask(chip, dev);
3372a153 1531
27346166 1532 chip->single_cmd = single_cmd;
a1585d76 1533 azx_check_snoop_available(chip);
c74db86b 1534
5c0d7bc1
TI		 1535 if (bdl_pos_adj[dev] < 0) {
1536 switch (chip->driver_type) {
0c6341ac 1537 case AZX_DRIVER_ICH:
32679f95 1538 case AZX_DRIVER_PCH:
0c6341ac 1539 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1540 break;
1541 default:
0c6341ac 1542 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1543 break;
1544 }
1545 }
9cdc0115 1546 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1547
a41d1224
TI		 1548 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1549 if (err < 0) {
1550 kfree(hda);
1551 pci_disable_device(pci);
1552 return err;
1553 }
1554
a82d51ed
TI		 1555 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1556 if (err < 0) {
4e76a883 1557 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1558 azx_free(chip);
1559 return err;
1560 }
1561
99a2008d 1562 /* continue probing in work context as may trigger request module */
9a34af4a 1563 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1564
a82d51ed 1565 *rchip = chip;
99a2008d 1566
a82d51ed
TI		 1567 return 0;
1568}
1569
48c8b0eb 1570static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1571{
1572 int dev = chip->dev_index;
1573 struct pci_dev *pci = chip->pci;
1574 struct snd_card *card = chip->card;
a41d1224 1575 struct hdac_bus *bus = azx_bus(chip);
67908994 1576 int err;
a82d51ed 1577 unsigned short gcap;
413cbf46 1578 unsigned int dma_bits = 64;
a82d51ed 1579
07e4ca50
TI		 1580#if BITS_PER_LONG != 64
1581 /* Fix up base address on ULI M5461 */
1582 if (chip->driver_type == AZX_DRIVER_ULI) {
1583 u16 tmp3;
1584 pci_read_config_word(pci, 0x40, &tmp3);
1585 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1586 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1587 }
1588#endif
1589
927fc866 1590 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1591 if (err < 0)
1da177e4 1592 return err;
a82d51ed 1593 chip->region_requested = 1;
1da177e4 1594
a41d1224
TI		 1595 bus->addr = pci_resource_start(pci, 0);
1596 bus->remap_addr = pci_ioremap_bar(pci, 0);
1597 if (bus->remap_addr == NULL) {
4e76a883 1598 dev_err(card->dev, "ioremap error\n");
a82d51ed 1599 return -ENXIO;
1da177e4
LT		 1600 }
1601
db79afa1
BH		 1602 if (chip->msi) {
1603 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1604 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1605 pci->no_64bit_msi = true;
1606 }
68e7fffc
TI		 1607 if (pci_enable_msi(pci) < 0)
1608 chip->msi = 0;
db79afa1 1609 }
7376d013 1610
a82d51ed
TI		 1611 if (azx_acquire_irq(chip, 0) < 0)
1612 return -EBUSY;
1da177e4
LT		 1613
1614 pci_set_master(pci);
a41d1224 1615 synchronize_irq(bus->irq);
1da177e4 1616
bcd72003 1617 gcap = azx_readw(chip, GCAP);
4e76a883 1618 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1619
413cbf46
TI		 1620 /* AMD devices support 40 or 48bit DMA, take the safe one */
1621 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1622 dma_bits = 40;
1623
dc4c2e6b 1624 /* disable SB600 64bit support for safety */
9477c58e 1625 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1626 struct pci_dev *p_smbus;
413cbf46 1627 dma_bits = 40;
dc4c2e6b
AB		 1628 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1629 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1630 NULL);
1631 if (p_smbus) {
1632 if (p_smbus->revision < 0x30)
fb1d8ac2 1633 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1634 pci_dev_put(p_smbus);
1635 }
1636 }
09240cf4 1637
9477c58e
TI		 1638 /* disable 64bit DMA address on some devices */
1639 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1640 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1641 gcap &= ~AZX_GCAP_64OK;
9477c58e 1642 }
396087ea 1643
2ae66c26 1644 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1645 if (align_buffer_size >= 0)
1646 chip->align_buffer_size = !!align_buffer_size;
1647 else {
103884a3 1648 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1649 chip->align_buffer_size = 0;
7bfe059e
TI		 1650 else
1651 chip->align_buffer_size = 1;
1652 }
2ae66c26 1653
cf7aaca8 1654 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1655 if (!(gcap & AZX_GCAP_64OK))
1656 dma_bits = 32;
412b979c
QL		 1657 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1658 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1659 } else {
412b979c
QL		 1660 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1661 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1662 }
cf7aaca8 1663
8b6ed8e7
TI		 1664 /* read number of streams from GCAP register instead of using
1665 * hardcoded value
1666 */
1667 chip->capture_streams = (gcap >> 8) & 0x0f;
1668 chip->playback_streams = (gcap >> 12) & 0x0f;
1669 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1670 /* gcap didn't give any info, switching to old method */
1671
1672 switch (chip->driver_type) {
1673 case AZX_DRIVER_ULI:
1674 chip->playback_streams = ULI_NUM_PLAYBACK;
1675 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1676 break;
1677 case AZX_DRIVER_ATIHDMI:
1815b34a 1678 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1679 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1680 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1681 break;
c4da29ca 1682 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1683 default:
1684 chip->playback_streams = ICH6_NUM_PLAYBACK;
1685 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1686 break;
1687 }
07e4ca50 1688 }
8b6ed8e7
TI		 1689 chip->capture_index_offset = 0;
1690 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1691 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1692
a41d1224
TI		 1693 /* initialize streams */
1694 err = azx_init_streams(chip);
81740861 1695 if (err < 0)
a82d51ed 1696 return err;
1da177e4 1697
a41d1224
TI		 1698 err = azx_alloc_stream_pages(chip);
1699 if (err < 0)
1700 return err;
1da177e4
LT		 1701
1702 /* initialize chip */
cb53c626 1703 azx_init_pci(chip);
e4d9e513 1704
926981ae
ID		 1705 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1706 struct hda_intel *hda;
1707
1708 hda = container_of(chip, struct hda_intel, chip);
1709 haswell_set_bclk(hda);
1710 }
e4d9e513 1711
0a673521 1712 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1713
1714 /* codec detection */
a41d1224 1715 if (!azx_bus(chip)->codec_mask) {
4e76a883 1716 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1717 return -ENODEV;
1da177e4
LT		 1718 }
1719
07e4ca50 1720 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1721 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1722 sizeof(card->shortname));
1723 snprintf(card->longname, sizeof(card->longname),
1724 "%s at 0x%lx irq %i",
a41d1224 1725 card->shortname, bus->addr, bus->irq);
07e4ca50 1726
1da177e4 1727 return 0;
1da177e4
LT		 1728}
1729
97c6a3d1 1730#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1731/* callback from request_firmware_nowait() */
1732static void azx_firmware_cb(const struct firmware *fw, void *context)
1733{
1734 struct snd_card *card = context;
1735 struct azx *chip = card->private_data;
1736 struct pci_dev *pci = chip->pci;
1737
1738 if (!fw) {
4e76a883 1739 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1740 goto error;
1741 }
1742
1743 chip->fw = fw;
1744 if (!chip->disabled) {
1745 /* continue probing */
1746 if (azx_probe_continue(chip))
1747 goto error;
1748 }
1749 return; /* OK */
1750
1751 error:
1752 snd_card_free(card);
1753 pci_set_drvdata(pci, NULL);
1754}
97c6a3d1 1755#endif
5cb543db 1756
40830813
DR		 1757/*
1758 * HDA controller ops.
1759 */
1760
1761/* PCI register access. */
db291e36 1762static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1763{
1764 writel(value, addr);
1765}
1766
db291e36 1767static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1768{
1769 return readl(addr);
1770}
1771
db291e36 1772static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1773{
1774 writew(value, addr);
1775}
1776
db291e36 1777static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1778{
1779 return readw(addr);
1780}
1781
db291e36 1782static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1783{
1784 writeb(value, addr);
1785}
1786
db291e36 1787static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1788{
1789 return readb(addr);
1790}
1791
f46ea609
DR		 1792static int disable_msi_reset_irq(struct azx *chip)
1793{
a41d1224 1794 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 1795 int err;
1796
a41d1224
TI		 1797 free_irq(bus->irq, chip);
1798 bus->irq = -1;
f46ea609
DR		 1799 pci_disable_msi(chip->pci);
1800 chip->msi = 0;
1801 err = azx_acquire_irq(chip, 1);
1802 if (err < 0)
1803 return err;
1804
1805 return 0;
1806}
1807
b419b35b 1808/* DMA page allocation helpers. */
a43ff5ba 1809static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 1810 int type,
1811 size_t size,
1812 struct snd_dma_buffer *buf)
1813{
a41d1224 1814 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 1815 int err;
1816
1817 err = snd_dma_alloc_pages(type,
a43ff5ba 1818 bus->dev,
b419b35b
DR		 1819 size, buf);
1820 if (err < 0)
1821 return err;
1822 mark_pages_wc(chip, buf, true);
1823 return 0;
1824}
1825
a43ff5ba 1826static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 1827{
a41d1224 1828 struct azx *chip = bus_to_azx(bus);
a43ff5ba 1829
b419b35b
DR		 1830 mark_pages_wc(chip, buf, false);
1831 snd_dma_free_pages(buf);
1832}
1833
1834static int substream_alloc_pages(struct azx *chip,
1835 struct snd_pcm_substream *substream,
1836 size_t size)
1837{
1838 struct azx_dev *azx_dev = get_azx_dev(substream);
1839 int ret;
1840
1841 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 1842 ret = snd_pcm_lib_malloc_pages(substream, size);
1843 if (ret < 0)
1844 return ret;
1845 mark_runtime_wc(chip, azx_dev, substream, true);
1846 return 0;
1847}
1848
1849static int substream_free_pages(struct azx *chip,
1850 struct snd_pcm_substream *substream)
1851{
1852 struct azx_dev *azx_dev = get_azx_dev(substream);
1853 mark_runtime_wc(chip, azx_dev, substream, false);
1854 return snd_pcm_lib_free_pages(substream);
1855}
1856
8769b278
DR		 1857static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1858 struct vm_area_struct *area)
1859{
1860#ifdef CONFIG_X86
1861 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1862 struct azx *chip = apcm->chip;
3b70bdba 1863 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 1864 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1865#endif
1866}
1867
a43ff5ba 1868static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 1869 .reg_writel = pci_azx_writel,
1870 .reg_readl = pci_azx_readl,
1871 .reg_writew = pci_azx_writew,
1872 .reg_readw = pci_azx_readw,
1873 .reg_writeb = pci_azx_writeb,
1874 .reg_readb = pci_azx_readb,
b419b35b
DR		 1875 .dma_alloc_pages = dma_alloc_pages,
1876 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 1877};
1878
1879static const struct hda_controller_ops pci_hda_ops = {
1880 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1881 .substream_alloc_pages = substream_alloc_pages,
1882 .substream_free_pages = substream_free_pages,
8769b278 1883 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1884 .position_check = azx_position_check,
17eccb27 1885 .link_power = azx_intel_link_power,
40830813
DR		 1886};
1887
e23e7a14
BP		 1888static int azx_probe(struct pci_dev *pci,
1889 const struct pci_device_id *pci_id)
1da177e4 1890{
5aba4f8e 1891 static int dev;
a98f90fd 1892 struct snd_card *card;
9a34af4a 1893 struct hda_intel *hda;
a98f90fd 1894 struct azx *chip;
aad730d0 1895 bool schedule_probe;
927fc866 1896 int err;
1da177e4 1897
5aba4f8e
TI		 1898 if (dev >= SNDRV_CARDS)
1899 return -ENODEV;
1900 if (!enable[dev]) {
1901 dev++;
1902 return -ENOENT;
1903 }
1904
60c5772b
TI		 1905 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1906 0, &card);
e58de7ba 1907 if (err < 0) {
4e76a883 1908 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1909 return err;
1da177e4
LT		 1910 }
1911
a43ff5ba 1912 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 1913 if (err < 0)
1914 goto out_free;
421a1252 1915 card->private_data = chip;
9a34af4a 1916 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 1917
1918 pci_set_drvdata(pci, card);
1919
1920 err = register_vga_switcheroo(chip);
1921 if (err < 0) {
4e76a883 1922 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1923 goto out_free;
1924 }
1925
1926 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1927 dev_info(card->dev, "VGA controller is disabled\n");
1928 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1929 chip->disabled = true;
1930 }
1931
aad730d0 1932 schedule_probe = !chip->disabled;
1da177e4 1933
4918cdab
TI		 1934#ifdef CONFIG_SND_HDA_PATCH_LOADER
1935 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1936 dev_info(card->dev, "Applying patch firmware '%s'\n",
1937 patch[dev]);
5cb543db
TI		 1938 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1939 &pci->dev, GFP_KERNEL, card,
1940 azx_firmware_cb);
4918cdab
TI		 1941 if (err < 0)
1942 goto out_free;
aad730d0 1943 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1944 }
1945#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1946
aad730d0
TI		 1947#ifndef CONFIG_SND_HDA_I915
1948 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1949 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1950#endif
99a2008d 1951
aad730d0 1952 if (schedule_probe)
9a34af4a 1953 schedule_work(&hda->probe_work);
a82d51ed 1954
a82d51ed 1955 dev++;
88d071fc 1956 if (chip->disabled)
9a34af4a 1957 complete_all(&hda->probe_wait);
a82d51ed
TI		 1958 return 0;
1959
1960out_free:
1961 snd_card_free(card);
1962 return err;
1963}
1964
e62a42ae
DR		 1965/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1966static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1967 [AZX_DRIVER_NVIDIA] = 8,
1968 [AZX_DRIVER_TERA] = 1,
1969};
1970
48c8b0eb 1971static int azx_probe_continue(struct azx *chip)
a82d51ed 1972{
9a34af4a 1973 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 1974 struct hdac_bus *bus = azx_bus(chip);
c67e2228 1975 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1976 int dev = chip->dev_index;
1977 int err;
1978
a41d1224 1979 hda->probe_continued = 1;
795614dd
ML		 1980
1981 /* Request display power well for the HDA controller or codec. For
1982 * Haswell/Broadwell, both the display HDA controller and codec need
1983 * this power. For other platforms, like Baytrail/Braswell, only the
1984 * display codec needs the power and it can be released after probe.
1985 */
99a2008d 1986 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
03b135ce
LY		 1987 /* HSW/BDW controllers need this power */
1988 if (CONTROLLER_IN_GPU(pci))
2bd1f73f
ML		 1989 hda->need_i915_power = 1;
1990
98d8fc6c 1991 err = snd_hdac_i915_init(bus);
535115b5
TI		 1992 if (err < 0) {
1993 /* if the controller is bound only with HDMI/DP
1994 * (for HSW and BDW), we need to abort the probe;
1995 * for other chips, still continue probing as other
1996 * codecs can be on the same link.
1997 */
1998 if (CONTROLLER_IN_GPU(pci))
1999 goto out_free;
2000 else
2001 goto skip_i915;
2002 }
795614dd 2003
98d8fc6c 2004 err = snd_hdac_display_power(bus, true);
74b0c2d7
TI		 2005 if (err < 0) {
2006 dev_err(chip->card->dev,
2007 "Cannot turn on display power on i915\n");
795614dd 2008 goto i915_power_fail;
74b0c2d7 2009 }
99a2008d
WX		 2010 }
2011
bf06848b 2012 skip_i915:
5c90680e
TI		 2013 err = azx_first_init(chip);
2014 if (err < 0)
2015 goto out_free;
2016
2dca0bba
JK		 2017#ifdef CONFIG_SND_HDA_INPUT_BEEP
2018 chip->beep_mode = beep_mode[dev];
2019#endif
2020
1da177e4 2021 /* create codec instances */
96d2bd6e 2022 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2023 if (err < 0)
2024 goto out_free;
96d2bd6e 2025
4ea6fbc8 2026#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2027 if (chip->fw) {
a41d1224 2028 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2029 chip->fw->data);
4ea6fbc8
TI		 2030 if (err < 0)
2031 goto out_free;
e39ae856 2032#ifndef CONFIG_PM
4918cdab
TI		 2033 release_firmware(chip->fw); /* no longer needed */
2034 chip->fw = NULL;
e39ae856 2035#endif
4ea6fbc8
TI		 2036 }
2037#endif
10e77dda 2038 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2039 err = azx_codec_configure(chip);
2040 if (err < 0)
2041 goto out_free;
2042 }
1da177e4 2043
a82d51ed 2044 err = snd_card_register(chip->card);
41dda0fd
WF		 2045 if (err < 0)
2046 goto out_free;
1da177e4 2047
cb53c626 2048 chip->running = 1;
65fcd41d 2049 azx_add_card_list(chip);
a41d1224 2050 snd_hda_set_power_save(&chip->bus, power_save * 1000);
364aa716 2051 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
c67e2228 2052 pm_runtime_put_noidle(&pci->dev);
1da177e4 2053
41dda0fd 2054out_free:
795614dd
ML		 2055 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2056 && !hda->need_i915_power)
98d8fc6c 2057 snd_hdac_display_power(bus, false);
795614dd
ML		 2058
2059i915_power_fail:
88d071fc 2060 if (err < 0)
9a34af4a
TI		 2061 hda->init_failed = 1;
2062 complete_all(&hda->probe_wait);
41dda0fd 2063 return err;
1da177e4
LT		 2064}
2065
e23e7a14 2066static void azx_remove(struct pci_dev *pci)
1da177e4 2067{
9121947d 2068 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 2069
9121947d
TI		 2070 if (card)
2071 snd_card_free(card);
1da177e4
LT		 2072}
2073
b2a0bafa
TI		 2074static void azx_shutdown(struct pci_dev *pci)
2075{
2076 struct snd_card *card = pci_get_drvdata(pci);
2077 struct azx *chip;
2078
2079 if (!card)
2080 return;
2081 chip = card->private_data;
2082 if (chip && chip->running)
2083 azx_stop_chip(chip);
2084}
2085
1da177e4 2086/* PCI IDs */
6f51f6cf 2087static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2088 /* CPT */
9477c58e 2089 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2090 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2091 /* PBG */
9477c58e 2092 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2093 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2094 /* Panther Point */
9477c58e 2095 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2096 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2097 /* Lynx Point */
2098 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2099 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2100 /* 9 Series */
2101 { PCI_DEVICE(0x8086, 0x8ca0),
2102 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2103 /* Wellsburg */
2104 { PCI_DEVICE(0x8086, 0x8d20),
2105 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2106 { PCI_DEVICE(0x8086, 0x8d21),
2107 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2108 /* Lewisburg */
2109 { PCI_DEVICE(0x8086, 0xa1f0),
2110 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2111 { PCI_DEVICE(0x8086, 0xa270),
2112 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2113 /* Lynx Point-LP */
2114 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2115 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2116 /* Lynx Point-LP */
2117 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2118 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2119 /* Wildcat Point-LP */
2120 { PCI_DEVICE(0x8086, 0x9ca0),
2121 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2122 /* Sunrise Point */
2123 { PCI_DEVICE(0x8086, 0xa170),
db48abf4 2124 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2125 /* Sunrise Point-LP */
2126 { PCI_DEVICE(0x8086, 0x9d70),
d6795827 2127 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
e926f2c8 2128 /* Haswell */
4a7c516b 2129 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2130 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2131 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2132 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2133 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2134 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2135 /* Broadwell */
2136 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2137 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2138 /* 5 Series/3400 */
2139 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2140 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2141 /* Poulsbo */
9477c58e 2142 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 2143 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2144 /* Oaktrail */
09904b95 2145 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 2146 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 2147 /* BayTrail */
2148 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2149 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2150 /* Braswell */
2151 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2152 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2153 /* ICH6 */
8b0bd226 2154 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2155 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2156 /* ICH7 */
8b0bd226 2157 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2158 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2159 /* ESB2 */
8b0bd226 2160 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2161 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2162 /* ICH8 */
8b0bd226 2163 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2164 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2165 /* ICH9 */
8b0bd226 2166 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2167 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2168 /* ICH9 */
8b0bd226 2169 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2170 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2171 /* ICH10 */
8b0bd226 2172 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2173 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2174 /* ICH10 */
8b0bd226 2175 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2176 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2177 /* Generic Intel */
2178 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2179 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2180 .class_mask = 0xffffff,
103884a3 2181 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2182 /* ATI SB 450/600/700/800/900 */
2183 { PCI_DEVICE(0x1002, 0x437b),
2184 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2185 { PCI_DEVICE(0x1002, 0x4383),
2186 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2187 /* AMD Hudson */
2188 { PCI_DEVICE(0x1022, 0x780d),
2189 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2190 /* ATI HDMI */
650474fb
AD		 2191 { PCI_DEVICE(0x1002, 0x1308),
2192 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2193 { PCI_DEVICE(0x1002, 0x157a),
2194 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2195 { PCI_DEVICE(0x1002, 0x793b),
2196 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2197 { PCI_DEVICE(0x1002, 0x7919),
2198 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2199 { PCI_DEVICE(0x1002, 0x960f),
2200 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2201 { PCI_DEVICE(0x1002, 0x970f),
2202 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2203 { PCI_DEVICE(0x1002, 0x9840),
2204 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2205 { PCI_DEVICE(0x1002, 0xaa00),
2206 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2207 { PCI_DEVICE(0x1002, 0xaa08),
2208 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2209 { PCI_DEVICE(0x1002, 0xaa10),
2210 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2211 { PCI_DEVICE(0x1002, 0xaa18),
2212 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2213 { PCI_DEVICE(0x1002, 0xaa20),
2214 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2215 { PCI_DEVICE(0x1002, 0xaa28),
2216 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2217 { PCI_DEVICE(0x1002, 0xaa30),
2218 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2219 { PCI_DEVICE(0x1002, 0xaa38),
2220 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2221 { PCI_DEVICE(0x1002, 0xaa40),
2222 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2223 { PCI_DEVICE(0x1002, 0xaa48),
2224 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2225 { PCI_DEVICE(0x1002, 0xaa50),
2226 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2227 { PCI_DEVICE(0x1002, 0xaa58),
2228 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2229 { PCI_DEVICE(0x1002, 0xaa60),
2230 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2231 { PCI_DEVICE(0x1002, 0xaa68),
2232 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2233 { PCI_DEVICE(0x1002, 0xaa80),
2234 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2235 { PCI_DEVICE(0x1002, 0xaa88),
2236 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2237 { PCI_DEVICE(0x1002, 0xaa90),
2238 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2239 { PCI_DEVICE(0x1002, 0xaa98),
2240 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2241 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2242 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2243 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2244 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2245 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2246 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2247 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2248 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2249 { PCI_DEVICE(0x1002, 0xaac0),
2250 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2251 { PCI_DEVICE(0x1002, 0xaac8),
2252 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2253 { PCI_DEVICE(0x1002, 0xaad8),
2254 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2255 { PCI_DEVICE(0x1002, 0xaae8),
2256 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2257 /* VIA VT8251/VT8237A */
9477c58e
TI		 2258 { PCI_DEVICE(0x1106, 0x3288),
2259 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 2260 /* VIA GFX VT7122/VX900 */
2261 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2262 /* VIA GFX VT6122/VX11 */
2263 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2264 /* SIS966 */
2265 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2266 /* ULI M5461 */
2267 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2268 /* NVIDIA MCP */
0c2fd1bf
TI		 2269 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2270 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2271 .class_mask = 0xffffff,
9477c58e 2272 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2273 /* Teradici */
9477c58e
TI		 2274 { PCI_DEVICE(0x6549, 0x1200),
2275 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2276 { PCI_DEVICE(0x6549, 0x2200),
2277 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2278 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2279 /* CTHDA chips */
2280 { PCI_DEVICE(0x1102, 0x0010),
2281 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2282 { PCI_DEVICE(0x1102, 0x0012),
2283 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2284#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2285 /* the following entry conflicts with snd-ctxfi driver,
2286 * as ctxfi driver mutates from HD-audio to native mode with
2287 * a special command sequence.
2288 */
4e01f54b
TI		 2289 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2290 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2291 .class_mask = 0xffffff,
9477c58e 2292 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
cadd16ea 2293 AZX_DCAPS_NO_64BIT |
69f9ba9b 2294 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2295#else
2296 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2297 { PCI_DEVICE(0x1102, 0x0009),
2298 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
cadd16ea 2299 AZX_DCAPS_NO_64BIT |
69f9ba9b 2300 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2301#endif
c563f473
TI		 2302 /* CM8888 */
2303 { PCI_DEVICE(0x13f6, 0x5011),
2304 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2305 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2306 /* Vortex86MX */
2307 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2308 /* VMware HDAudio */
2309 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2310 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2311 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2312 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2313 .class_mask = 0xffffff,
9477c58e 2314 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2315 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2316 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2317 .class_mask = 0xffffff,
9477c58e 2318 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2319 { 0, }
2320};
2321MODULE_DEVICE_TABLE(pci, azx_ids);
2322
2323/* pci_driver definition */
e9f66d9b 2324static struct pci_driver azx_driver = {
3733e424 2325 .name = KBUILD_MODNAME,
1da177e4
LT		 2326 .id_table = azx_ids,
2327 .probe = azx_probe,
e23e7a14 2328 .remove = azx_remove,
b2a0bafa 2329 .shutdown = azx_shutdown,
68cb2b55
TI		 2330 .driver = {
2331 .pm = AZX_PM_OPS,
2332 },
1da177e4
LT		 2333};
2334
e9f66d9b 2335module_pci_driver(azx_driver);
Ubuntu Artful kernel mirror