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ALSA: hda - Split Thinkpad ACPI-related code
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4 64#include "hda_codec.h"
99a2008d 65#include "hda_i915.h"
1da177e4
LT		 66
67
5aba4f8e
TI		 68static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
69static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 70static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 71static char *model[SNDRV_CARDS];
1dac6695 72static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 73static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 74static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 75static int probe_only[SNDRV_CARDS];
26a6cb6c 76static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 77static bool single_cmd;
71623855 78static int enable_msi = -1;
4ea6fbc8
TI		 79#ifdef CONFIG_SND_HDA_PATCH_LOADER
80static char *patch[SNDRV_CARDS];
81#endif
2dca0bba 82#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 83static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 84 CONFIG_SND_HDA_INPUT_BEEP_MODE};
85#endif
1da177e4 86
5aba4f8e 87module_param_array(index, int, NULL, 0444);
1da177e4 88MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 89module_param_array(id, charp, NULL, 0444);
1da177e4 90MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 91module_param_array(enable, bool, NULL, 0444);
92MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
93module_param_array(model, charp, NULL, 0444);
1da177e4 94MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 95module_param_array(position_fix, int, NULL, 0444);
4cb36310 96MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 97 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 98module_param_array(bdl_pos_adj, int, NULL, 0644);
99MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 100module_param_array(probe_mask, int, NULL, 0444);
606ad75f 101MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 102module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 103MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 104module_param_array(jackpoll_ms, int, NULL, 0444);
105MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 106module_param(single_cmd, bool, 0444);
d01ce99f
TI		 107MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
108 "(for debugging only).");
ac9ef6cf 109module_param(enable_msi, bint, 0444);
134a11f0 110MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 111#ifdef CONFIG_SND_HDA_PATCH_LOADER
112module_param_array(patch, charp, NULL, 0444);
113MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
114#endif
2dca0bba 115#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 116module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 117MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 118 "(0=off, 1=on) (default=1).");
2dca0bba 119#endif
606ad75f 120
83012a7c 121#ifdef CONFIG_PM
65fcd41d
TI		 122static int param_set_xint(const char *val, const struct kernel_param *kp);
123static struct kernel_param_ops param_ops_xint = {
124 .set = param_set_xint,
125 .get = param_get_int,
126};
127#define param_check_xint param_check_int
128
fee2fba3 129static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 130module_param(power_save, xint, 0644);
fee2fba3
TI		 131MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
132 "(in second, 0 = disable).");
1da177e4 133
dee1b66c
TI		 134/* reset the HD-audio controller in power save mode.
135 * this may give more power-saving, but will take longer time to
136 * wake up.
137 */
8fc24426
TI		 138static bool power_save_controller = 1;
139module_param(power_save_controller, bool, 0644);
dee1b66c 140MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
83012a7c 141#endif /* CONFIG_PM */
dee1b66c 142
7bfe059e
TI		 143static int align_buffer_size = -1;
144module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 145MODULE_PARM_DESC(align_buffer_size,
146 "Force buffer and period sizes to be multiple of 128 bytes.");
147
27fe48d9
TI		 148#ifdef CONFIG_X86
149static bool hda_snoop = true;
150module_param_named(snoop, hda_snoop, bool, 0444);
151MODULE_PARM_DESC(snoop, "Enable/disable snooping");
152#define azx_snoop(chip) (chip)->snoop
153#else
154#define hda_snoop true
155#define azx_snoop(chip) true
156#endif
157
158
1da177e4
LT		 159MODULE_LICENSE("GPL");
160MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
161 "{Intel, ICH6M},"
2f1b3818 162 "{Intel, ICH7},"
f5d40b30 163 "{Intel, ESB2},"
d2981393 164 "{Intel, ICH8},"
f9cc8a8b 165 "{Intel, ICH9},"
c34f5a04 166 "{Intel, ICH10},"
b29c2360 167 "{Intel, PCH},"
d2f2fcd2 168 "{Intel, CPT},"
d2edeb7c 169 "{Intel, PPT},"
8bc039a1 170 "{Intel, LPT},"
144dad99 171 "{Intel, LPT_LP},"
4eeca499 172 "{Intel, WPT_LP},"
e926f2c8 173 "{Intel, HPT},"
cea310e8 174 "{Intel, PBG},"
4979bca9 175 "{Intel, SCH},"
fc20a562 176 "{ATI, SB450},"
89be83f8 177 "{ATI, SB600},"
778b6e1b 178 "{ATI, RS600},"
5b15c95f 179 "{ATI, RS690},"
e6db1119
WL		 180 "{ATI, RS780},"
181 "{ATI, R600},"
2797f724
HRK		 182 "{ATI, RV630},"
183 "{ATI, RV610},"
27da1834
WL		 184 "{ATI, RV670},"
185 "{ATI, RV635},"
186 "{ATI, RV620},"
187 "{ATI, RV770},"
fc20a562 188 "{VIA, VT8251},"
47672310 189 "{VIA, VT8237A},"
07e4ca50
TI		 190 "{SiS, SIS966},"
191 "{ULI, M5461}}");
1da177e4
LT		 192MODULE_DESCRIPTION("Intel HDA driver");
193
4abc1cc2
TI		 194#ifdef CONFIG_SND_VERBOSE_PRINTK
195#define SFX /* nop */
196#else
445a51b3 197#define SFX "hda-intel "
4abc1cc2 198#endif
cb53c626 199
a82d51ed
TI		 200#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
201#ifdef CONFIG_SND_HDA_CODEC_HDMI
202#define SUPPORT_VGA_SWITCHEROO
203#endif
204#endif
205
206
1da177e4
LT		 207/*
208 * registers
209 */
210#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 211#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
212#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
213#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
214#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
215#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 216#define ICH6_REG_VMIN 0x02
217#define ICH6_REG_VMAJ 0x03
218#define ICH6_REG_OUTPAY 0x04
219#define ICH6_REG_INPAY 0x06
220#define ICH6_REG_GCTL 0x08
8a933ece 221#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 222#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
223#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 224#define ICH6_REG_WAKEEN 0x0c
225#define ICH6_REG_STATESTS 0x0e
226#define ICH6_REG_GSTS 0x10
b21fadb9 227#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 228#define ICH6_REG_INTCTL 0x20
229#define ICH6_REG_INTSTS 0x24
e5463720 230#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 231#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
232#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 233#define ICH6_REG_CORBLBASE 0x40
234#define ICH6_REG_CORBUBASE 0x44
235#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 236#define ICH6_REG_CORBRP 0x4a
237#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 238#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 239#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
240#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 241#define ICH6_REG_CORBSTS 0x4d
b21fadb9 242#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 243#define ICH6_REG_CORBSIZE 0x4e
244
245#define ICH6_REG_RIRBLBASE 0x50
246#define ICH6_REG_RIRBUBASE 0x54
247#define ICH6_REG_RIRBWP 0x58
b21fadb9 248#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 249#define ICH6_REG_RINTCNT 0x5a
250#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 251#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
252#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
253#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 254#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 255#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
256#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 257#define ICH6_REG_RIRBSIZE 0x5e
258
259#define ICH6_REG_IC 0x60
260#define ICH6_REG_IR 0x64
261#define ICH6_REG_IRS 0x68
262#define ICH6_IRS_VALID (1<<1)
263#define ICH6_IRS_BUSY (1<<0)
264
265#define ICH6_REG_DPLBASE 0x70
266#define ICH6_REG_DPUBASE 0x74
267#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
268
269/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
270enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
271
272/* stream register offsets from stream base */
273#define ICH6_REG_SD_CTL 0x00
274#define ICH6_REG_SD_STS 0x03
275#define ICH6_REG_SD_LPIB 0x04
276#define ICH6_REG_SD_CBL 0x08
277#define ICH6_REG_SD_LVI 0x0c
278#define ICH6_REG_SD_FIFOW 0x0e
279#define ICH6_REG_SD_FIFOSIZE 0x10
280#define ICH6_REG_SD_FORMAT 0x12
281#define ICH6_REG_SD_BDLPL 0x18
282#define ICH6_REG_SD_BDLPU 0x1c
283
284/* PCI space */
285#define ICH6_PCIREG_TCSEL 0x44
286
287/*
288 * other constants
289 */
290
291/* max number of SDs */
07e4ca50 292/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 293#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 294#define ICH6_NUM_PLAYBACK 4
295
296/* ULI has 6 playback and 5 capture */
07e4ca50 297#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 298#define ULI_NUM_PLAYBACK 6
299
7546abfb 300/* ATI HDMI may have up to 8 playbacks and 0 capture */
778b6e1b 301#define ATIHDMI_NUM_CAPTURE 0
7546abfb 302#define ATIHDMI_NUM_PLAYBACK 8
778b6e1b 303
f269002e
KY		 304/* TERA has 4 playback and 3 capture */
305#define TERA_NUM_CAPTURE 3
306#define TERA_NUM_PLAYBACK 4
307
07e4ca50
TI		 308/* this number is statically defined for simplicity */
309#define MAX_AZX_DEV 16
310
1da177e4 311/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 312#define BDL_SIZE 4096
313#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
314#define AZX_MAX_FRAG 32
1da177e4
LT		 315/* max buffer size - no h/w limit, you can increase as you like */
316#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 317
318/* RIRB int mask: overrun[2], response[0] */
319#define RIRB_INT_RESPONSE 0x01
320#define RIRB_INT_OVERRUN 0x04
321#define RIRB_INT_MASK 0x05
322
2f5983f2 323/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 324#define AZX_MAX_CODECS 8
325#define AZX_DEFAULT_CODECS 4
deadff16 326#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 327
328/* SD_CTL bits */
329#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
330#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 331#define SD_CTL_STRIPE (3 << 16) /* stripe control */
332#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
333#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 334#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
335#define SD_CTL_STREAM_TAG_SHIFT 20
336
337/* SD_CTL and SD_STS */
338#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
339#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
340#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 341#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
342 SD_INT_COMPLETE)
1da177e4
LT		 343
344/* SD_STS */
345#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
346
347/* INTCTL and INTSTS */
d01ce99f
TI		 348#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
349#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
350#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 351
1da177e4
LT		 352/* below are so far hardcoded - should read registers in future */
353#define ICH6_MAX_CORB_ENTRIES 256
354#define ICH6_MAX_RIRB_ENTRIES 256
355
c74db86b
TI		 356/* position fix mode */
357enum {
0be3b5d3 358 POS_FIX_AUTO,
d2e1c973 359 POS_FIX_LPIB,
0be3b5d3 360 POS_FIX_POSBUF,
4cb36310 361 POS_FIX_VIACOMBO,
a6f2fd55 362 POS_FIX_COMBO,
c74db86b 363};
1da177e4 364
f5d40b30 365/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 366#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
367#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
368
da3fca21
V		 369/* Defines for Nvidia HDA support */
370#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
371#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 372#define NVIDIA_HDA_ISTRM_COH 0x4d
373#define NVIDIA_HDA_OSTRM_COH 0x4c
374#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 375
90a5ad52
TI		 376/* Defines for Intel SCH HDA snoop control */
377#define INTEL_SCH_HDA_DEVC 0x78
378#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
379
0e153474
JC		 380/* Define IN stream 0 FIFO size offset in VIA controller */
381#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
382/* Define VIA HD Audio Device ID*/
383#define VIA_HDAC_DEVICE_ID 0x3288
384
c4da29ca
YL		 385/* HD Audio class code */
386#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 387
1da177e4
LT		 388/*
389 */
390
a98f90fd 391struct azx_dev {
4ce107b9 392 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 393 u32 *posbuf; /* position buffer pointer */
1da177e4 394
d01ce99f 395 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 396 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 397 unsigned int frags; /* number for period in the play buffer */
398 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 399 unsigned long start_wallclk; /* start + minimum wallclk */
400 unsigned long period_wallclk; /* wallclk for period */
1da177e4 401
d01ce99f 402 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 403
d01ce99f 404 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 405
406 /* pcm support */
d01ce99f
TI		 407 struct snd_pcm_substream *substream; /* assigned substream,
408 * set in PCM open
409 */
410 unsigned int format_val; /* format value to be set in the
411 * controller and the codec
412 */
1da177e4
LT		 413 unsigned char stream_tag; /* assigned stream */
414 unsigned char index; /* stream index */
d5cf9911 415 int assigned_key; /* last device# key assigned to */
1da177e4 416
927fc866
PM		 417 unsigned int opened :1;
418 unsigned int running :1;
675f25d4 419 unsigned int irq_pending :1;
eb49faa6
TI		 420 unsigned int prepared:1;
421 unsigned int locked:1;
0e153474
JC		 422 /*
423 * For VIA:
424 * A flag to ensure DMA position is 0
425 * when link position is not greater than FIFO size
426 */
427 unsigned int insufficient :1;
27fe48d9 428 unsigned int wc_marked:1;
915bf29e 429 unsigned int no_period_wakeup:1;
5d890f59
PLB		 430
431 struct timecounter azx_tc;
432 struct cyclecounter azx_cc;
eb49faa6 433
e8648e5e
TI		 434 int delay_negative_threshold;
435
eb49faa6
TI		 436#ifdef CONFIG_SND_HDA_DSP_LOADER
437 struct mutex dsp_mutex;
438#endif
1da177e4
LT		 439};
440
eb49faa6
TI		 441/* DSP lock helpers */
442#ifdef CONFIG_SND_HDA_DSP_LOADER
443#define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
444#define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
445#define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
446#define dsp_is_locked(dev) ((dev)->locked)
447#else
448#define dsp_lock_init(dev) do {} while (0)
449#define dsp_lock(dev) do {} while (0)
450#define dsp_unlock(dev) do {} while (0)
451#define dsp_is_locked(dev) 0
452#endif
453
1da177e4 454/* CORB/RIRB */
a98f90fd 455struct azx_rb {
1da177e4
LT		 456 u32 *buf; /* CORB/RIRB buffer
457 * Each CORB entry is 4byte, RIRB is 8byte
458 */
459 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
460 /* for RIRB */
461 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 462 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
463 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 464};
465
01b65bfb
TI		 466struct azx_pcm {
467 struct azx *chip;
468 struct snd_pcm *pcm;
469 struct hda_codec *codec;
470 struct hda_pcm_stream *hinfo[2];
471 struct list_head list;
472};
473
a98f90fd
TI		 474struct azx {
475 struct snd_card *card;
1da177e4 476 struct pci_dev *pci;
555e219f 477 int dev_index;
1da177e4 478
07e4ca50
TI		 479 /* chip type specific */
480 int driver_type;
9477c58e 481 unsigned int driver_caps;
07e4ca50
TI		 482 int playback_streams;
483 int playback_index_offset;
484 int capture_streams;
485 int capture_index_offset;
486 int num_streams;
487
1da177e4
LT		 488 /* pci resources */
489 unsigned long addr;
490 void __iomem *remap_addr;
491 int irq;
492
493 /* locks */
494 spinlock_t reg_lock;
62932df8 495 struct mutex open_mutex;
f4c482a4 496 struct completion probe_wait;
1da177e4 497
07e4ca50 498 /* streams (x num_streams) */
a98f90fd 499 struct azx_dev *azx_dev;
1da177e4
LT		 500
501 /* PCM */
01b65bfb 502 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 503
504 /* HD codec */
505 unsigned short codec_mask;
f1eaaeec 506 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 507 struct hda_bus *bus;
2dca0bba 508 unsigned int beep_mode;
1da177e4
LT		 509
510 /* CORB/RIRB */
a98f90fd
TI		 511 struct azx_rb corb;
512 struct azx_rb rirb;
1da177e4 513
4ce107b9 514 /* CORB/RIRB and position buffers */
1da177e4
LT		 515 struct snd_dma_buffer rb;
516 struct snd_dma_buffer posbuf;
c74db86b 517
4918cdab
TI		 518#ifdef CONFIG_SND_HDA_PATCH_LOADER
519 const struct firmware *fw;
520#endif
521
c74db86b 522 /* flags */
beaffc39 523 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 524 int poll_count;
cb53c626 525 unsigned int running :1;
927fc866
PM		 526 unsigned int initialized :1;
527 unsigned int single_cmd :1;
528 unsigned int polling_mode :1;
68e7fffc 529 unsigned int msi :1;
a6a950a8 530 unsigned int irq_pending_warned :1;
6ce4a3bc 531 unsigned int probing :1; /* codec probing phase */
27fe48d9 532 unsigned int snoop:1;
52409aa6 533 unsigned int align_buffer_size:1;
a82d51ed
TI		 534 unsigned int region_requested:1;
535
536 /* VGA-switcheroo setup */
537 unsigned int use_vga_switcheroo:1;
128960a9 538 unsigned int vga_switcheroo_registered:1;
a82d51ed
TI		 539 unsigned int init_failed:1; /* delayed init failed */
540 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 541
542 /* for debugging */
feb27340 543 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 544
545 /* for pending irqs */
546 struct work_struct irq_pending_work;
0cbf0098 547
99a2008d 548 struct work_struct probe_work;
99a2008d 549
0cbf0098
TI		 550 /* reboot notifier (for mysterious hangup problem at power-down) */
551 struct notifier_block reboot_notifier;
65fcd41d
TI		 552
553 /* card list (for power_save trigger) */
554 struct list_head list;
eb49faa6
TI		 555
556#ifdef CONFIG_SND_HDA_DSP_LOADER
557 struct azx_dev saved_azx_dev;
558#endif
246efa4a
DA		 559
560 /* secondary power domain for hdmi audio under vga device */
561 struct dev_pm_domain hdmi_pm_domain;
1da177e4
LT		 562};
563
1a8506d4
TI		 564#define CREATE_TRACE_POINTS
565#include "hda_intel_trace.h"
566
07e4ca50
TI		 567/* driver types */
568enum {
569 AZX_DRIVER_ICH,
32679f95 570 AZX_DRIVER_PCH,
4979bca9 571 AZX_DRIVER_SCH,
fab1285a 572 AZX_DRIVER_HDMI,
07e4ca50 573 AZX_DRIVER_ATI,
778b6e1b 574 AZX_DRIVER_ATIHDMI,
1815b34a 575 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 576 AZX_DRIVER_VIA,
577 AZX_DRIVER_SIS,
578 AZX_DRIVER_ULI,
da3fca21 579 AZX_DRIVER_NVIDIA,
f269002e 580 AZX_DRIVER_TERA,
14d34f16 581 AZX_DRIVER_CTX,
5ae763b1 582 AZX_DRIVER_CTHDA,
c4da29ca 583 AZX_DRIVER_GENERIC,
2f5983f2 584 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 585};
586
9477c58e
TI		 587/* driver quirks (capabilities) */
588/* bits 0-7 are used for indicating driver type */
589#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
590#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
591#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
592#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
593#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
594#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
595#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
596#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
597#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
598#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
599#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
600#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 601#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 602#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 603#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 604#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
90accc58 605#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
2ea3c6a2 606#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
99a2008d 607#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 power well support */
2ea3c6a2
TI		 608
609/* quirks for Intel PCH */
d7dab4db 610#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 611 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 612 AZX_DCAPS_COUNT_LPIB_DELAY)
613
614#define AZX_DCAPS_INTEL_PCH \
615 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 616
33499a15
TI		 617#define AZX_DCAPS_INTEL_HASWELL \
618 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
619 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
620 AZX_DCAPS_I915_POWERWELL)
621
9477c58e
TI		 622/* quirks for ATI SB / AMD Hudson */
623#define AZX_DCAPS_PRESET_ATI_SB \
624 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
625 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
626
627/* quirks for ATI/AMD HDMI */
628#define AZX_DCAPS_PRESET_ATI_HDMI \
629 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
630
631/* quirks for Nvidia */
632#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 633 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
49d9e77e 634 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
9477c58e 635
5ae763b1
TI		 636#define AZX_DCAPS_PRESET_CTHDA \
637 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
638
a82d51ed
TI		 639/*
640 * VGA-switcher support
641 */
642#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 643#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
644#else
645#define use_vga_switcheroo(chip) 0
646#endif
647
48c8b0eb 648static char *driver_short_names[] = {
07e4ca50 649 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 650 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 651 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 652 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 653 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 654 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 655 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 656 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
657 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 658 [AZX_DRIVER_ULI] = "HDA ULI M5461",
659 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 660 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 661 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 662 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 663 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 664};
665
1da177e4
LT		 666/*
667 * macros for easy use
668 */
669#define azx_writel(chip,reg,value) \
670 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
671#define azx_readl(chip,reg) \
672 readl((chip)->remap_addr + ICH6_REG_##reg)
673#define azx_writew(chip,reg,value) \
674 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
675#define azx_readw(chip,reg) \
676 readw((chip)->remap_addr + ICH6_REG_##reg)
677#define azx_writeb(chip,reg,value) \
678 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
679#define azx_readb(chip,reg) \
680 readb((chip)->remap_addr + ICH6_REG_##reg)
681
682#define azx_sd_writel(dev,reg,value) \
683 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
684#define azx_sd_readl(dev,reg) \
685 readl((dev)->sd_addr + ICH6_REG_##reg)
686#define azx_sd_writew(dev,reg,value) \
687 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
688#define azx_sd_readw(dev,reg) \
689 readw((dev)->sd_addr + ICH6_REG_##reg)
690#define azx_sd_writeb(dev,reg,value) \
691 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
692#define azx_sd_readb(dev,reg) \
693 readb((dev)->sd_addr + ICH6_REG_##reg)
694
695/* for pcm support */
a98f90fd 696#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 697
27fe48d9 698#ifdef CONFIG_X86
9ddf1aeb 699static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 700{
9ddf1aeb
TI		 701 int pages;
702
27fe48d9
TI		 703 if (azx_snoop(chip))
704 return;
9ddf1aeb
TI		 705 if (!dmab || !dmab->area || !dmab->bytes)
706 return;
707
708#ifdef CONFIG_SND_DMA_SGBUF
709 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
710 struct snd_sg_buf *sgbuf = dmab->private_data;
27fe48d9 711 if (on)
9ddf1aeb 712 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 713 else
9ddf1aeb
TI		 714 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
715 return;
27fe48d9 716 }
9ddf1aeb
TI		 717#endif
718
719 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
720 if (on)
721 set_memory_wc((unsigned long)dmab->area, pages);
722 else
723 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 724}
725
726static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
727 bool on)
728{
9ddf1aeb 729 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 730}
731static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 732 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 733{
734 if (azx_dev->wc_marked != on) {
9ddf1aeb 735 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 736 azx_dev->wc_marked = on;
737 }
738}
739#else
740/* NOP for other archs */
741static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
742 bool on)
743{
744}
745static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 746 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 747{
748}
749#endif
750
68e7fffc 751static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 752static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 753/*
754 * Interface for HD codec
755 */
756
1da177e4
LT		 757/*
758 * CORB / RIRB interface
759 */
a98f90fd 760static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 761{
762 int err;
763
764 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 765 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
766 snd_dma_pci_data(chip->pci),
1da177e4
LT		 767 PAGE_SIZE, &chip->rb);
768 if (err < 0) {
445a51b3 769 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
1da177e4
LT		 770 return err;
771 }
27fe48d9 772 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 773 return 0;
774}
775
a98f90fd 776static void azx_init_cmd_io(struct azx *chip)
1da177e4 777{
cdb1fbf2 778 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 779 /* CORB set up */
780 chip->corb.addr = chip->rb.addr;
781 chip->corb.buf = (u32 *)chip->rb.area;
782 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 783 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 784
07e4ca50
TI		 785 /* set the corb size to 256 entries (ULI requires explicitly) */
786 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 787 /* set the corb write pointer to 0 */
788 azx_writew(chip, CORBWP, 0);
789 /* reset the corb hw read pointer */
b21fadb9 790 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 791 /* enable corb dma */
b21fadb9 792 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 793
794 /* RIRB set up */
795 chip->rirb.addr = chip->rb.addr + 2048;
796 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 797 chip->rirb.wp = chip->rirb.rp = 0;
798 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 799 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 800 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 801
07e4ca50
TI		 802 /* set the rirb size to 256 entries (ULI requires explicitly) */
803 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 804 /* reset the rirb hw write pointer */
b21fadb9 805 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 806 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 807 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 808 azx_writew(chip, RINTCNT, 0xc0);
809 else
810 azx_writew(chip, RINTCNT, 1);
1da177e4 811 /* enable rirb dma and response irq */
1da177e4 812 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 813 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 814}
815
a98f90fd 816static void azx_free_cmd_io(struct azx *chip)
1da177e4 817{
cdb1fbf2 818 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 819 /* disable ringbuffer DMAs */
820 azx_writeb(chip, RIRBCTL, 0);
821 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 822 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 823}
824
deadff16
WF		 825static unsigned int azx_command_addr(u32 cmd)
826{
827 unsigned int addr = cmd >> 28;
828
829 if (addr >= AZX_MAX_CODECS) {
830 snd_BUG();
831 addr = 0;
832 }
833
834 return addr;
835}
836
837static unsigned int azx_response_addr(u32 res)
838{
839 unsigned int addr = res & 0xf;
840
841 if (addr >= AZX_MAX_CODECS) {
842 snd_BUG();
843 addr = 0;
844 }
845
846 return addr;
1da177e4
LT		 847}
848
849/* send a command */
33fa35ed 850static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 851{
33fa35ed 852 struct azx *chip = bus->private_data;
deadff16 853 unsigned int addr = azx_command_addr(val);
3bcce5c0 854 unsigned int wp, rp;
1da177e4 855
c32649fe
WF		 856 spin_lock_irq(&chip->reg_lock);
857
1da177e4 858 /* add command to corb */
cc5ede3e
TI		 859 wp = azx_readw(chip, CORBWP);
860 if (wp == 0xffff) {
861 /* something wrong, controller likely turned to D3 */
862 spin_unlock_irq(&chip->reg_lock);
3bcce5c0 863 return -EIO;
cc5ede3e 864 }
1da177e4
LT		 865 wp++;
866 wp %= ICH6_MAX_CORB_ENTRIES;
867
3bcce5c0
TI		 868 rp = azx_readw(chip, CORBRP);
869 if (wp == rp) {
870 /* oops, it's full */
871 spin_unlock_irq(&chip->reg_lock);
872 return -EAGAIN;
873 }
874
deadff16 875 chip->rirb.cmds[addr]++;
1da177e4
LT		 876 chip->corb.buf[wp] = cpu_to_le32(val);
877 azx_writel(chip, CORBWP, wp);
c32649fe 878
1da177e4
LT		 879 spin_unlock_irq(&chip->reg_lock);
880
881 return 0;
882}
883
884#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
885
886/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 887static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 888{
889 unsigned int rp, wp;
deadff16 890 unsigned int addr;
1da177e4
LT		 891 u32 res, res_ex;
892
cc5ede3e
TI		 893 wp = azx_readw(chip, RIRBWP);
894 if (wp == 0xffff) {
895 /* something wrong, controller likely turned to D3 */
896 return;
897 }
898
1da177e4
LT		 899 if (wp == chip->rirb.wp)
900 return;
901 chip->rirb.wp = wp;
deadff16 902
1da177e4
LT		 903 while (chip->rirb.rp != wp) {
904 chip->rirb.rp++;
905 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
906
907 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
908 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
909 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 910 addr = azx_response_addr(res_ex);
1da177e4
LT		 911 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
912 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 913 else if (chip->rirb.cmds[addr]) {
914 chip->rirb.res[addr] = res;
2add9b92 915 smp_wmb();
deadff16 916 chip->rirb.cmds[addr]--;
3b70a67d
JP		 917 } else if (printk_ratelimit()) {
918 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, last cmd=%#08x\n",
9e3d352b 919 pci_name(chip->pci),
e310bb06
WF		 920 res, res_ex,
921 chip->last_cmd[addr]);
3b70a67d 922 }
1da177e4
LT		 923 }
924}
925
926/* receive a response */
deadff16
WF		 927static unsigned int azx_rirb_get_response(struct hda_bus *bus,
928 unsigned int addr)
1da177e4 929{
33fa35ed 930 struct azx *chip = bus->private_data;
5c79b1f8 931 unsigned long timeout;
32cf4023 932 unsigned long loopcounter;
1eb6dc7d 933 int do_poll = 0;
1da177e4 934
5c79b1f8
TI		 935 again:
936 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 937
938 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 939 if (chip->polling_mode || do_poll) {
e96224ae
TI		 940 spin_lock_irq(&chip->reg_lock);
941 azx_update_rirb(chip);
942 spin_unlock_irq(&chip->reg_lock);
943 }
deadff16 944 if (!chip->rirb.cmds[addr]) {
2add9b92 945 smp_rmb();
b613291f 946 bus->rirb_error = 0;
1eb6dc7d
ML		 947
948 if (!do_poll)
949 chip->poll_count = 0;
deadff16 950 return chip->rirb.res[addr]; /* the last value */
2add9b92 951 }
28a0d9df
TI		 952 if (time_after(jiffies, timeout))
953 break;
32cf4023 954 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 955 msleep(2); /* temporary workaround */
956 else {
957 udelay(10);
958 cond_resched();
959 }
28a0d9df 960 }
5c79b1f8 961
63e51fd7
TI		 962 if (!bus->no_response_fallback)
963 return -1;
964
1eb6dc7d 965 if (!chip->polling_mode && chip->poll_count < 2) {
445a51b3 966 snd_printdd(SFX "%s: azx_get_response timeout, "
1eb6dc7d 967 "polling the codec once: last cmd=0x%08x\n",
445a51b3 968 pci_name(chip->pci), chip->last_cmd[addr]);
1eb6dc7d
ML		 969 do_poll = 1;
970 chip->poll_count++;
971 goto again;
972 }
973
974
23c4a881 975 if (!chip->polling_mode) {
445a51b3 976 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
23c4a881 977 "switching to polling mode: last cmd=0x%08x\n",
445a51b3 978 pci_name(chip->pci), chip->last_cmd[addr]);
23c4a881
TI		 979 chip->polling_mode = 1;
980 goto again;
981 }
982
68e7fffc 983 if (chip->msi) {
445a51b3 984 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
feb27340 985 "disabling MSI: last cmd=0x%08x\n",
445a51b3 986 pci_name(chip->pci), chip->last_cmd[addr]);
68e7fffc
TI		 987 free_irq(chip->irq, chip);
988 chip->irq = -1;
989 pci_disable_msi(chip->pci);
990 chip->msi = 0;
b613291f
TI		 991 if (azx_acquire_irq(chip, 1) < 0) {
992 bus->rirb_error = 1;
68e7fffc 993 return -1;
b613291f 994 }
68e7fffc
TI		 995 goto again;
996 }
997
6ce4a3bc
TI		 998 if (chip->probing) {
999 /* If this critical timeout happens during the codec probing
1000 * phase, this is likely an access to a non-existing codec
1001 * slot. Better to return an error and reset the system.
1002 */
1003 return -1;
1004 }
1005
8dd78330
TI		 1006 /* a fatal communication error; need either to reset or to fallback
1007 * to the single_cmd mode
1008 */
b613291f 1009 bus->rirb_error = 1;
b20f3b83 1010 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 1011 bus->response_reset = 1;
1012 return -1; /* give a chance to retry */
1013 }
1014
1015 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
1016 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 1017 chip->last_cmd[addr]);
8dd78330
TI		 1018 chip->single_cmd = 1;
1019 bus->response_reset = 0;
1a696978 1020 /* release CORB/RIRB */
4fcd3920 1021 azx_free_cmd_io(chip);
1a696978
TI		 1022 /* disable unsolicited responses */
1023 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 1024 return -1;
1da177e4
LT		 1025}
1026
1da177e4
LT		 1027/*
1028 * Use the single immediate command instead of CORB/RIRB for simplicity
1029 *
1030 * Note: according to Intel, this is not preferred use. The command was
1031 * intended for the BIOS only, and may get confused with unsolicited
1032 * responses. So, we shouldn't use it for normal operation from the
1033 * driver.
1034 * I left the codes, however, for debugging/testing purposes.
1035 */
1036
b05a7d4f 1037/* receive a response */
deadff16 1038static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 1039{
1040 int timeout = 50;
1041
1042 while (timeout--) {
1043 /* check IRV busy bit */
1044 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1045 /* reuse rirb.res as the response return value */
deadff16 1046 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 1047 return 0;
1048 }
1049 udelay(1);
1050 }
1051 if (printk_ratelimit())
445a51b3
DB		 1052 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1053 pci_name(chip->pci), azx_readw(chip, IRS));
deadff16 1054 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 1055 return -EIO;
1056}
1057
1da177e4 1058/* send a command */
33fa35ed 1059static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 1060{
33fa35ed 1061 struct azx *chip = bus->private_data;
deadff16 1062 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 1063 int timeout = 50;
1064
8dd78330 1065 bus->rirb_error = 0;
1da177e4
LT		 1066 while (timeout--) {
1067 /* check ICB busy bit */
d01ce99f 1068 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 1069 /* Clear IRV valid bit */
d01ce99f
TI		 1070 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1071 ICH6_IRS_VALID);
1da177e4 1072 azx_writel(chip, IC, val);
d01ce99f
TI		 1073 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1074 ICH6_IRS_BUSY);
deadff16 1075 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 1076 }
1077 udelay(1);
1078 }
1cfd52bc 1079 if (printk_ratelimit())
445a51b3
DB		 1080 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1081 pci_name(chip->pci), azx_readw(chip, IRS), val);
1da177e4
LT		 1082 return -EIO;
1083}
1084
1085/* receive a response */
deadff16
WF		 1086static unsigned int azx_single_get_response(struct hda_bus *bus,
1087 unsigned int addr)
1da177e4 1088{
33fa35ed 1089 struct azx *chip = bus->private_data;
deadff16 1090 return chip->rirb.res[addr];
1da177e4
LT		 1091}
1092
111d3af5
TI		 1093/*
1094 * The below are the main callbacks from hda_codec.
1095 *
1096 * They are just the skeleton to call sub-callbacks according to the
1097 * current setting of chip->single_cmd.
1098 */
1099
1100/* send a command */
33fa35ed 1101static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 1102{
33fa35ed 1103 struct azx *chip = bus->private_data;
43bbb6cc 1104
a82d51ed
TI		 1105 if (chip->disabled)
1106 return 0;
feb27340 1107 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 1108 if (chip->single_cmd)
33fa35ed 1109 return azx_single_send_cmd(bus, val);
111d3af5 1110 else
33fa35ed 1111 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 1112}
1113
1114/* get a response */
deadff16
WF		 1115static unsigned int azx_get_response(struct hda_bus *bus,
1116 unsigned int addr)
111d3af5 1117{
33fa35ed 1118 struct azx *chip = bus->private_data;
a82d51ed
TI		 1119 if (chip->disabled)
1120 return 0;
111d3af5 1121 if (chip->single_cmd)
deadff16 1122 return azx_single_get_response(bus, addr);
111d3af5 1123 else
deadff16 1124 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1125}
1126
83012a7c 1127#ifdef CONFIG_PM
68467f51 1128static void azx_power_notify(struct hda_bus *bus, bool power_up);
cb53c626 1129#endif
111d3af5 1130
1d1a4564
TI		 1131#ifdef CONFIG_SND_HDA_DSP_LOADER
1132static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1133 unsigned int byte_size,
1134 struct snd_dma_buffer *bufp);
1135static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1136static void azx_load_dsp_cleanup(struct hda_bus *bus,
1137 struct snd_dma_buffer *dmab);
1138#endif
1139
3af3f356 1140/* enter link reset */
7295b264 1141static void azx_enter_link_reset(struct azx *chip)
3af3f356
ML		 1142{
1143 unsigned long timeout;
1144
1145 /* reset controller */
1146 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1147
1148 timeout = jiffies + msecs_to_jiffies(100);
1149 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
1150 time_before(jiffies, timeout))
1151 usleep_range(500, 1000);
1152}
1153
7295b264
ML		 1154/* exit link reset */
1155static void azx_exit_link_reset(struct azx *chip)
1da177e4 1156{
fa348da5 1157 unsigned long timeout;
1da177e4 1158
7295b264
ML		 1159 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1160
1161 timeout = jiffies + msecs_to_jiffies(100);
1162 while (!azx_readb(chip, GCTL) &&
1163 time_before(jiffies, timeout))
1164 usleep_range(500, 1000);
1165}
1166
1167/* reset codec link */
1168static int azx_reset(struct azx *chip, int full_reset)
1169{
cd508fe5
JK		 1170 if (!full_reset)
1171 goto __skip;
1172
e8a7f136 1173 /* clear STATESTS */
da7db6ad 1174 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
e8a7f136 1175
1da177e4 1176 /* reset controller */
7295b264 1177 azx_enter_link_reset(chip);
1da177e4
LT		 1178
1179 /* delay for >= 100us for codec PLL to settle per spec
1180 * Rev 0.9 section 5.5.1
1181 */
fa348da5 1182 usleep_range(500, 1000);
1da177e4
LT		 1183
1184 /* Bring controller out of reset */
7295b264 1185 azx_exit_link_reset(chip);
1da177e4 1186
927fc866 1187 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
fa348da5 1188 usleep_range(1000, 1200);
1da177e4 1189
cd508fe5 1190 __skip:
1da177e4 1191 /* check to see if controller is ready */
927fc866 1192 if (!azx_readb(chip, GCTL)) {
445a51b3 1193 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1da177e4
LT		 1194 return -EBUSY;
1195 }
1196
41e2fce4 1197 /* Accept unsolicited responses */
1a696978
TI		 1198 if (!chip->single_cmd)
1199 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1200 ICH6_GCTL_UNSOL);
41e2fce4 1201
1da177e4 1202 /* detect codecs */
927fc866 1203 if (!chip->codec_mask) {
1da177e4 1204 chip->codec_mask = azx_readw(chip, STATESTS);
445a51b3 1205 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1da177e4
LT		 1206 }
1207
1208 return 0;
1209}
1210
1211
1212/*
1213 * Lowlevel interface
1214 */
1215
1216/* enable interrupts */
a98f90fd 1217static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1218{
1219 /* enable controller CIE and GIE */
1220 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1221 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1222}
1223
1224/* disable interrupts */
a98f90fd 1225static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1226{
1227 int i;
1228
1229 /* disable interrupts in stream descriptor */
07e4ca50 1230 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1231 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1232 azx_sd_writeb(azx_dev, SD_CTL,
1233 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1234 }
1235
1236 /* disable SIE for all streams */
1237 azx_writeb(chip, INTCTL, 0);
1238
1239 /* disable controller CIE and GIE */
1240 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1241 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1242}
1243
1244/* clear interrupts */
a98f90fd 1245static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1246{
1247 int i;
1248
1249 /* clear stream status */
07e4ca50 1250 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1251 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1252 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1253 }
1254
1255 /* clear STATESTS */
da7db6ad 1256 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1da177e4
LT		 1257
1258 /* clear rirb status */
1259 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1260
1261 /* clear int status */
1262 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1263}
1264
1265/* start a stream */
a98f90fd 1266static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1267{
0e153474
JC		 1268 /*
1269 * Before stream start, initialize parameter
1270 */
1271 azx_dev->insufficient = 1;
1272
1da177e4 1273 /* enable SIE */
ccc5df05
WN		 1274 azx_writel(chip, INTCTL,
1275 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1276 /* set DMA start and interrupt mask */
1277 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1278 SD_CTL_DMA_START | SD_INT_MASK);
1279}
1280
1dddab40
TI		 1281/* stop DMA */
1282static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1283{
1da177e4
LT		 1284 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1285 ~(SD_CTL_DMA_START | SD_INT_MASK));
1286 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1287}
1288
1289/* stop a stream */
1290static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1291{
1292 azx_stream_clear(chip, azx_dev);
1da177e4 1293 /* disable SIE */
ccc5df05
WN		 1294 azx_writel(chip, INTCTL,
1295 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1296}
1297
1298
1299/*
cb53c626 1300 * reset and start the controller registers
1da177e4 1301 */
cd508fe5 1302static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1303{
cb53c626
TI		 1304 if (chip->initialized)
1305 return;
1da177e4
LT		 1306
1307 /* reset controller */
cd508fe5 1308 azx_reset(chip, full_reset);
1da177e4
LT		 1309
1310 /* initialize interrupts */
1311 azx_int_clear(chip);
1312 azx_int_enable(chip);
1313
1314 /* initialize the codec command I/O */
1a696978
TI		 1315 if (!chip->single_cmd)
1316 azx_init_cmd_io(chip);
1da177e4 1317
0be3b5d3
TI		 1318 /* program the position buffer */
1319 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1320 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1321
cb53c626
TI		 1322 chip->initialized = 1;
1323}
1324
1325/*
1326 * initialize the PCI registers
1327 */
1328/* update bits in a PCI register byte */
1329static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1330 unsigned char mask, unsigned char val)
1331{
1332 unsigned char data;
1333
1334 pci_read_config_byte(pci, reg, &data);
1335 data &= ~mask;
1336 data |= (val & mask);
1337 pci_write_config_byte(pci, reg, data);
1338}
1339
1340static void azx_init_pci(struct azx *chip)
1341{
1342 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1343 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1344 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1345 * codecs.
1346 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1347 */
46f2cc80 1348 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
445a51b3 1349 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
a09e89f6 1350 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1351 }
cb53c626 1352
9477c58e
TI		 1353 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1354 * we need to enable snoop.
1355 */
1356 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
445a51b3 1357 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626 1358 update_pci_byte(chip->pci,
27fe48d9
TI		 1359 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1360 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1361 }
1362
1363 /* For NVIDIA HDA, enable snoop */
1364 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
445a51b3 1365 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626
TI		 1366 update_pci_byte(chip->pci,
1367 NVIDIA_HDA_TRANSREG_ADDR,
1368 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1369 update_pci_byte(chip->pci,
1370 NVIDIA_HDA_ISTRM_COH,
1371 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1372 update_pci_byte(chip->pci,
1373 NVIDIA_HDA_OSTRM_COH,
1374 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1375 }
1376
1377 /* Enable SCH/PCH snoop if needed */
1378 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1379 unsigned short snoop;
90a5ad52 1380 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1381 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1382 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1383 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1384 if (!azx_snoop(chip))
1385 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1386 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1387 pci_read_config_word(chip->pci,
1388 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1389 }
445a51b3
DB		 1390 snd_printdd(SFX "%s: SCH snoop: %s\n",
1391 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
27fe48d9 1392 ? "Disabled" : "Enabled");
da3fca21 1393 }
1da177e4
LT		 1394}
1395
1396
9ad593f6
TI		 1397static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1398
1da177e4
LT		 1399/*
1400 * interrupt handler
1401 */
7d12e780 1402static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1403{
a98f90fd
TI		 1404 struct azx *chip = dev_id;
1405 struct azx_dev *azx_dev;
1da177e4 1406 u32 status;
9ef04066 1407 u8 sd_status;
fa00e046 1408 int i, ok;
1da177e4 1409
b8dfc462 1410#ifdef CONFIG_PM_RUNTIME
246efa4a
DA		 1411 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1412 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1413 return IRQ_NONE;
b8dfc462
ML		 1414#endif
1415
1da177e4
LT		 1416 spin_lock(&chip->reg_lock);
1417
60911062
DC		 1418 if (chip->disabled) {
1419 spin_unlock(&chip->reg_lock);
a82d51ed 1420 return IRQ_NONE;
60911062 1421 }
a82d51ed 1422
1da177e4 1423 status = azx_readl(chip, INTSTS);
246efa4a 1424 if (status == 0 || status == 0xffffffff) {
1da177e4
LT		 1425 spin_unlock(&chip->reg_lock);
1426 return IRQ_NONE;
1427 }
1428
07e4ca50 1429 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1430 azx_dev = &chip->azx_dev[i];
1431 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1432 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1433 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1434 if (!azx_dev->substream || !azx_dev->running ||
1435 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1436 continue;
1437 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1438 ok = azx_position_ok(chip, azx_dev);
1439 if (ok == 1) {
9ad593f6 1440 azx_dev->irq_pending = 0;
1da177e4
LT		 1441 spin_unlock(&chip->reg_lock);
1442 snd_pcm_period_elapsed(azx_dev->substream);
1443 spin_lock(&chip->reg_lock);
fa00e046 1444 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1445 /* bogus IRQ, process it later */
1446 azx_dev->irq_pending = 1;
6acaed38
TI		 1447 queue_work(chip->bus->workq,
1448 &chip->irq_pending_work);
1da177e4
LT		 1449 }
1450 }
1451 }
1452
1453 /* clear rirb int */
1454 status = azx_readb(chip, RIRBSTS);
1455 if (status & RIRB_INT_MASK) {
14d34f16 1456 if (status & RIRB_INT_RESPONSE) {
9477c58e 1457 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1458 udelay(80);
1da177e4 1459 azx_update_rirb(chip);
14d34f16 1460 }
1da177e4
LT		 1461 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1462 }
1463
1464#if 0
1465 /* clear state status int */
da7db6ad
WX		 1466 if (azx_readw(chip, STATESTS) & 0x04)
1467 azx_writew(chip, STATESTS, 0x04);
1da177e4
LT		 1468#endif
1469 spin_unlock(&chip->reg_lock);
1470
1471 return IRQ_HANDLED;
1472}
1473
1474
675f25d4
TI		 1475/*
1476 * set up a BDL entry
1477 */
5ae763b1 1478static int setup_bdle(struct azx *chip,
1d1a4564 1479 struct snd_dma_buffer *dmab,
675f25d4
TI		 1480 struct azx_dev *azx_dev, u32 **bdlp,
1481 int ofs, int size, int with_ioc)
1482{
675f25d4
TI		 1483 u32 *bdl = *bdlp;
1484
1485 while (size > 0) {
1486 dma_addr_t addr;
1487 int chunk;
1488
1489 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1490 return -EINVAL;
1491
1d1a4564 1492 addr = snd_sgbuf_get_addr(dmab, ofs);
675f25d4
TI		 1493 /* program the address field of the BDL entry */
1494 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1495 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1496 /* program the size field of the BDL entry */
1d1a4564 1497 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
5ae763b1
TI		 1498 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1499 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1500 u32 remain = 0x1000 - (ofs & 0xfff);
1501 if (chunk > remain)
1502 chunk = remain;
1503 }
675f25d4
TI		 1504 bdl[2] = cpu_to_le32(chunk);
1505 /* program the IOC to enable interrupt
1506 * only when the whole fragment is processed
1507 */
1508 size -= chunk;
1509 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1510 bdl += 4;
1511 azx_dev->frags++;
1512 ofs += chunk;
1513 }
1514 *bdlp = bdl;
1515 return ofs;
1516}
1517
1da177e4
LT		 1518/*
1519 * set up BDL entries
1520 */
555e219f
TI		 1521static int azx_setup_periods(struct azx *chip,
1522 struct snd_pcm_substream *substream,
4ce107b9 1523 struct azx_dev *azx_dev)
1da177e4 1524{
4ce107b9
TI		 1525 u32 *bdl;
1526 int i, ofs, periods, period_bytes;
555e219f 1527 int pos_adj;
1da177e4
LT		 1528
1529 /* reset BDL address */
1530 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1531 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1532
97b71c94 1533 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1534 periods = azx_dev->bufsize / period_bytes;
1535
1da177e4 1536 /* program the initial BDL entries */
4ce107b9
TI		 1537 bdl = (u32 *)azx_dev->bdl.area;
1538 ofs = 0;
1539 azx_dev->frags = 0;
555e219f 1540 pos_adj = bdl_pos_adj[chip->dev_index];
915bf29e 1541 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
675f25d4 1542 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1543 int pos_align = pos_adj;
555e219f 1544 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1545 if (!pos_adj)
e785d3d8
TI		 1546 pos_adj = pos_align;
1547 else
1548 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1549 pos_align;
675f25d4
TI		 1550 pos_adj = frames_to_bytes(runtime, pos_adj);
1551 if (pos_adj >= period_bytes) {
445a51b3
DB		 1552 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1553 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1554 pos_adj = 0;
1555 } else {
1d1a4564
TI		 1556 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1557 azx_dev,
915bf29e 1558 &bdl, ofs, pos_adj, true);
675f25d4
TI		 1559 if (ofs < 0)
1560 goto error;
4ce107b9 1561 }
555e219f
TI		 1562 } else
1563 pos_adj = 0;
675f25d4
TI		 1564 for (i = 0; i < periods; i++) {
1565 if (i == periods - 1 && pos_adj)
1d1a4564
TI		 1566 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1567 azx_dev, &bdl, ofs,
675f25d4
TI		 1568 period_bytes - pos_adj, 0);
1569 else
1d1a4564
TI		 1570 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1571 azx_dev, &bdl, ofs,
7bb8fb70 1572 period_bytes,
915bf29e 1573 !azx_dev->no_period_wakeup);
675f25d4
TI		 1574 if (ofs < 0)
1575 goto error;
1da177e4 1576 }
4ce107b9 1577 return 0;
675f25d4
TI		 1578
1579 error:
445a51b3
DB		 1580 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1581 pci_name(chip->pci), azx_dev->bufsize, period_bytes);
675f25d4 1582 return -EINVAL;
1da177e4
LT		 1583}
1584
1dddab40
TI		 1585/* reset stream */
1586static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1587{
1588 unsigned char val;
1589 int timeout;
1590
1dddab40
TI		 1591 azx_stream_clear(chip, azx_dev);
1592
d01ce99f
TI		 1593 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1594 SD_CTL_STREAM_RESET);
1da177e4
LT		 1595 udelay(3);
1596 timeout = 300;
1597 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1598 --timeout)
1599 ;
1600 val &= ~SD_CTL_STREAM_RESET;
1601 azx_sd_writeb(azx_dev, SD_CTL, val);
1602 udelay(3);
1603
1604 timeout = 300;
1605 /* waiting for hardware to report that the stream is out of reset */
1606 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1607 --timeout)
1608 ;
fa00e046
JK		 1609
1610 /* reset first position - may not be synced with hw at this time */
1611 *azx_dev->posbuf = 0;
1dddab40 1612}
1da177e4 1613
1dddab40
TI		 1614/*
1615 * set up the SD for streaming
1616 */
1617static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1618{
27fe48d9 1619 unsigned int val;
1dddab40
TI		 1620 /* make sure the run bit is zero for SD */
1621 azx_stream_clear(chip, azx_dev);
1da177e4 1622 /* program the stream_tag */
27fe48d9
TI		 1623 val = azx_sd_readl(azx_dev, SD_CTL);
1624 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1625 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1626 if (!azx_snoop(chip))
1627 val |= SD_CTL_TRAFFIC_PRIO;
1628 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1629
1630 /* program the length of samples in cyclic buffer */
1631 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1632
1633 /* program the stream format */
1634 /* this value needs to be the same as the one programmed */
1635 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1636
1637 /* program the stream LVI (last valid index) of the BDL */
1638 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1639
1640 /* program the BDL address */
1641 /* lower BDL address */
4ce107b9 1642 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1643 /* upper BDL address */
766979e0 1644 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1645
0be3b5d3 1646 /* enable the position buffer */
4cb36310
DH		 1647 if (chip->position_fix[0] != POS_FIX_LPIB ||
1648 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1649 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1650 azx_writel(chip, DPLBASE,
1651 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1652 }
c74db86b 1653
1da177e4 1654 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1655 azx_sd_writel(azx_dev, SD_CTL,
1656 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1657
1658 return 0;
1659}
1660
6ce4a3bc
TI		 1661/*
1662 * Probe the given codec address
1663 */
1664static int probe_codec(struct azx *chip, int addr)
1665{
1666 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1667 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1668 unsigned int res;
1669
a678cdee 1670 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1671 chip->probing = 1;
1672 azx_send_cmd(chip->bus, cmd);
deadff16 1673 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1674 chip->probing = 0;
a678cdee 1675 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1676 if (res == -1)
1677 return -EIO;
445a51b3 1678 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
6ce4a3bc
TI		 1679 return 0;
1680}
1681
33fa35ed
TI		 1682static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1683 struct hda_pcm *cpcm);
6ce4a3bc 1684static void azx_stop_chip(struct azx *chip);
1da177e4 1685
8dd78330
TI		 1686static void azx_bus_reset(struct hda_bus *bus)
1687{
1688 struct azx *chip = bus->private_data;
8dd78330
TI		 1689
1690 bus->in_reset = 1;
1691 azx_stop_chip(chip);
cd508fe5 1692 azx_init_chip(chip, 1);
65f75983 1693#ifdef CONFIG_PM
8dd78330 1694 if (chip->initialized) {
01b65bfb
TI		 1695 struct azx_pcm *p;
1696 list_for_each_entry(p, &chip->pcm_list, list)
1697 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1698 snd_hda_suspend(chip->bus);
1699 snd_hda_resume(chip->bus);
1700 }
65f75983 1701#endif
8dd78330
TI		 1702 bus->in_reset = 0;
1703}
1704
26a6cb6c
DH		 1705static int get_jackpoll_interval(struct azx *chip)
1706{
1707 int i = jackpoll_ms[chip->dev_index];
1708 unsigned int j;
1709 if (i == 0)
1710 return 0;
1711 if (i < 50 || i > 60000)
1712 j = 0;
1713 else
1714 j = msecs_to_jiffies(i);
1715 if (j == 0)
1716 snd_printk(KERN_WARNING SFX
1717 "jackpoll_ms value out of range: %d\n", i);
1718 return j;
1719}
1720
1da177e4
LT		 1721/*
1722 * Codec initialization
1723 */
1724
2f5983f2 1725/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
48c8b0eb 1726static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
7445dfc1 1727 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1728 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1729};
1730
48c8b0eb 1731static int azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1732{
1733 struct hda_bus_template bus_temp;
34c25350
TI		 1734 int c, codecs, err;
1735 int max_slots;
1da177e4
LT		 1736
1737 memset(&bus_temp, 0, sizeof(bus_temp));
1738 bus_temp.private_data = chip;
1739 bus_temp.modelname = model;
1740 bus_temp.pci = chip->pci;
111d3af5
TI		 1741 bus_temp.ops.command = azx_send_cmd;
1742 bus_temp.ops.get_response = azx_get_response;
176d5335 1743 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1744 bus_temp.ops.bus_reset = azx_bus_reset;
83012a7c 1745#ifdef CONFIG_PM
11cd41b8 1746 bus_temp.power_save = &power_save;
cb53c626
TI		 1747 bus_temp.ops.pm_notify = azx_power_notify;
1748#endif
1d1a4564
TI		 1749#ifdef CONFIG_SND_HDA_DSP_LOADER
1750 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1751 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1752 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1753#endif
1da177e4 1754
d01ce99f
TI		 1755 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1756 if (err < 0)
1da177e4
LT		 1757 return err;
1758
9477c58e 1759 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
445a51b3 1760 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
dc9c8e21 1761 chip->bus->needs_damn_long_delay = 1;
9477c58e 1762 }
dc9c8e21 1763
34c25350 1764 codecs = 0;
2f5983f2
TI		 1765 max_slots = azx_max_codecs[chip->driver_type];
1766 if (!max_slots)
7445dfc1 1767 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1768
1769 /* First try to probe all given codec slots */
1770 for (c = 0; c < max_slots; c++) {
f1eaaeec 1771 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1772 if (probe_codec(chip, c) < 0) {
1773 /* Some BIOSen give you wrong codec addresses
1774 * that don't exist
1775 */
4abc1cc2 1776 snd_printk(KERN_WARNING SFX
445a51b3
DB		 1777 "%s: Codec #%d probe error; "
1778 "disabling it...\n", pci_name(chip->pci), c);
6ce4a3bc
TI		 1779 chip->codec_mask &= ~(1 << c);
1780 /* More badly, accessing to a non-existing
1781 * codec often screws up the controller chip,
2448158e 1782 * and disturbs the further communications.
6ce4a3bc
TI		 1783 * Thus if an error occurs during probing,
1784 * better to reset the controller chip to
1785 * get back to the sanity state.
1786 */
1787 azx_stop_chip(chip);
cd508fe5 1788 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1789 }
1790 }
1791 }
1792
d507cd66
TI		 1793 /* AMD chipsets often cause the communication stalls upon certain
1794 * sequence like the pin-detection. It seems that forcing the synced
1795 * access works around the stall. Grrr...
1796 */
9477c58e 1797 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
445a51b3
DB		 1798 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1799 pci_name(chip->pci));
d507cd66
TI		 1800 chip->bus->sync_write = 1;
1801 chip->bus->allow_bus_reset = 1;
1802 }
1803
6ce4a3bc 1804 /* Then create codec instances */
34c25350 1805 for (c = 0; c < max_slots; c++) {
f1eaaeec 1806 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1807 struct hda_codec *codec;
a1e21c90 1808 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1809 if (err < 0)
1810 continue;
26a6cb6c 1811 codec->jackpoll_interval = get_jackpoll_interval(chip);
2dca0bba 1812 codec->beep_mode = chip->beep_mode;
1da177e4 1813 codecs++;
19a982b6
TI		 1814 }
1815 }
1816 if (!codecs) {
445a51b3 1817 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1da177e4
LT		 1818 return -ENXIO;
1819 }
a1e21c90
TI		 1820 return 0;
1821}
1da177e4 1822
a1e21c90 1823/* configure each codec instance */
e23e7a14 1824static int azx_codec_configure(struct azx *chip)
a1e21c90
TI		 1825{
1826 struct hda_codec *codec;
1827 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1828 snd_hda_codec_configure(codec);
1829 }
1da177e4
LT		 1830 return 0;
1831}
1832
1833
1834/*
1835 * PCM support
1836 */
1837
1838/* assign a stream for the PCM */
ef18bede
WF		 1839static inline struct azx_dev *
1840azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1841{
07e4ca50 1842 int dev, i, nums;
ef18bede 1843 struct azx_dev *res = NULL;
d5cf9911
TI		 1844 /* make a non-zero unique key for the substream */
1845 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1846 (substream->stream + 1);
ef18bede
WF		 1847
1848 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1849 dev = chip->playback_index_offset;
1850 nums = chip->playback_streams;
1851 } else {
1852 dev = chip->capture_index_offset;
1853 nums = chip->capture_streams;
1854 }
eb49faa6
TI		 1855 for (i = 0; i < nums; i++, dev++) {
1856 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1857 dsp_lock(azx_dev);
1858 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1859 res = azx_dev;
1860 if (res->assigned_key == key) {
1861 res->opened = 1;
1862 res->assigned_key = key;
1863 dsp_unlock(azx_dev);
1864 return azx_dev;
1865 }
1da177e4 1866 }
eb49faa6
TI		 1867 dsp_unlock(azx_dev);
1868 }
ef18bede 1869 if (res) {
eb49faa6 1870 dsp_lock(res);
ef18bede 1871 res->opened = 1;
d5cf9911 1872 res->assigned_key = key;
eb49faa6 1873 dsp_unlock(res);
ef18bede
WF		 1874 }
1875 return res;
1da177e4
LT		 1876}
1877
1878/* release the assigned stream */
a98f90fd 1879static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1880{
1881 azx_dev->opened = 0;
1882}
1883
5d890f59
PLB		 1884static cycle_t azx_cc_read(const struct cyclecounter *cc)
1885{
1886 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1887 struct snd_pcm_substream *substream = azx_dev->substream;
1888 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1889 struct azx *chip = apcm->chip;
1890
1891 return azx_readl(chip, WALLCLK);
1892}
1893
1894static void azx_timecounter_init(struct snd_pcm_substream *substream,
1895 bool force, cycle_t last)
1896{
1897 struct azx_dev *azx_dev = get_azx_dev(substream);
1898 struct timecounter *tc = &azx_dev->azx_tc;
1899 struct cyclecounter *cc = &azx_dev->azx_cc;
1900 u64 nsec;
1901
1902 cc->read = azx_cc_read;
1903 cc->mask = CLOCKSOURCE_MASK(32);
1904
1905 /*
1906 * Converting from 24 MHz to ns means applying a 125/3 factor.
1907 * To avoid any saturation issues in intermediate operations,
1908 * the 125 factor is applied first. The division is applied
1909 * last after reading the timecounter value.
1910 * Applying the 1/3 factor as part of the multiplication
1911 * requires at least 20 bits for a decent precision, however
1912 * overflows occur after about 4 hours or less, not a option.
1913 */
1914
1915 cc->mult = 125; /* saturation after 195 years */
1916 cc->shift = 0;
1917
1918 nsec = 0; /* audio time is elapsed time since trigger */
1919 timecounter_init(tc, cc, nsec);
1920 if (force)
1921 /*
1922 * force timecounter to use predefined value,
1923 * used for synchronized starts
1924 */
1925 tc->cycle_last = last;
1926}
1927
ae03bbb8 1928static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
78daea29
DR		 1929 u64 nsec)
1930{
1931 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1932 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1933 u64 codec_frames, codec_nsecs;
1934
1935 if (!hinfo->ops.get_delay)
1936 return nsec;
1937
1938 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1939 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1940 substream->runtime->rate);
1941
ae03bbb8
DR		 1942 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1943 return nsec + codec_nsecs;
1944
78daea29
DR		 1945 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1946}
1947
5d890f59
PLB		 1948static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1949 struct timespec *ts)
1950{
1951 struct azx_dev *azx_dev = get_azx_dev(substream);
1952 u64 nsec;
1953
1954 nsec = timecounter_read(&azx_dev->azx_tc);
1955 nsec = div_u64(nsec, 3); /* can be optimized */
ae03bbb8 1956 nsec = azx_adjust_codec_delay(substream, nsec);
5d890f59
PLB		 1957
1958 *ts = ns_to_timespec(nsec);
1959
1960 return 0;
1961}
1962
a98f90fd 1963static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1964 .info = (SNDRV_PCM_INFO_MMAP |
1965 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1966 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1967 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1968 /* No full-resume yet implemented */
1969 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1970 SNDRV_PCM_INFO_PAUSE |
7bb8fb70 1971 SNDRV_PCM_INFO_SYNC_START |
5d890f59 1972 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
7bb8fb70 1973 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1974 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1975 .rates = SNDRV_PCM_RATE_48000,
1976 .rate_min = 48000,
1977 .rate_max = 48000,
1978 .channels_min = 2,
1979 .channels_max = 2,
1980 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1981 .period_bytes_min = 128,
1982 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1983 .periods_min = 2,
1984 .periods_max = AZX_MAX_FRAG,
1985 .fifo_size = 0,
1986};
1987
a98f90fd 1988static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1989{
1990 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1991 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1992 struct azx *chip = apcm->chip;
1993 struct azx_dev *azx_dev;
1994 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1995 unsigned long flags;
1996 int err;
2ae66c26 1997 int buff_step;
1da177e4 1998
62932df8 1999 mutex_lock(&chip->open_mutex);
ef18bede 2000 azx_dev = azx_assign_device(chip, substream);
1da177e4 2001 if (azx_dev == NULL) {
62932df8 2002 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2003 return -EBUSY;
2004 }
2005 runtime->hw = azx_pcm_hw;
2006 runtime->hw.channels_min = hinfo->channels_min;
2007 runtime->hw.channels_max = hinfo->channels_max;
2008 runtime->hw.formats = hinfo->formats;
2009 runtime->hw.rates = hinfo->rates;
2010 snd_pcm_limit_hw_rates(runtime);
2011 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5d890f59
PLB		 2012
2013 /* avoid wrap-around with wall-clock */
2014 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
2015 20,
2016 178000000);
2017
52409aa6 2018 if (chip->align_buffer_size)
2ae66c26
PLB		 2019 /* constrain buffer sizes to be multiple of 128
2020 bytes. This is more efficient in terms of memory
2021 access but isn't required by the HDA spec and
2022 prevents users from specifying exact period/buffer
2023 sizes. For example for 44.1kHz, a period size set
2024 to 20ms will be rounded to 19.59ms. */
2025 buff_step = 128;
2026 else
2027 /* Don't enforce steps on buffer sizes, still need to
2028 be multiple of 4 bytes (HDA spec). Tested on Intel
2029 HDA controllers, may not work on all devices where
2030 option needs to be disabled */
2031 buff_step = 4;
2032
5f1545bc 2033 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 2034 buff_step);
5f1545bc 2035 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 2036 buff_step);
b4a91cf0 2037 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 2038 err = hinfo->ops.open(hinfo, apcm->codec, substream);
2039 if (err < 0) {
1da177e4 2040 azx_release_device(azx_dev);
cb53c626 2041 snd_hda_power_down(apcm->codec);
62932df8 2042 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2043 return err;
2044 }
70d321e6 2045 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 2046 /* sanity check */
2047 if (snd_BUG_ON(!runtime->hw.channels_min) ||
2048 snd_BUG_ON(!runtime->hw.channels_max) ||
2049 snd_BUG_ON(!runtime->hw.formats) ||
2050 snd_BUG_ON(!runtime->hw.rates)) {
2051 azx_release_device(azx_dev);
2052 hinfo->ops.close(hinfo, apcm->codec, substream);
2053 snd_hda_power_down(apcm->codec);
2054 mutex_unlock(&chip->open_mutex);
2055 return -EINVAL;
2056 }
5d890f59
PLB		 2057
2058 /* disable WALLCLOCK timestamps for capture streams
2059 until we figure out how to handle digital inputs */
2060 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2061 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2062
1da177e4
LT		 2063 spin_lock_irqsave(&chip->reg_lock, flags);
2064 azx_dev->substream = substream;
2065 azx_dev->running = 0;
2066 spin_unlock_irqrestore(&chip->reg_lock, flags);
2067
2068 runtime->private_data = azx_dev;
850f0e52 2069 snd_pcm_set_sync(substream);
62932df8 2070 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2071 return 0;
2072}
2073
a98f90fd 2074static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 2075{
2076 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2077 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 2078 struct azx *chip = apcm->chip;
2079 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 2080 unsigned long flags;
2081
62932df8 2082 mutex_lock(&chip->open_mutex);
1da177e4
LT		 2083 spin_lock_irqsave(&chip->reg_lock, flags);
2084 azx_dev->substream = NULL;
2085 azx_dev->running = 0;
2086 spin_unlock_irqrestore(&chip->reg_lock, flags);
2087 azx_release_device(azx_dev);
2088 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 2089 snd_hda_power_down(apcm->codec);
62932df8 2090 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 2091 return 0;
2092}
2093
d01ce99f
TI		 2094static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2095 struct snd_pcm_hw_params *hw_params)
1da177e4 2096{
27fe48d9
TI		 2097 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2098 struct azx *chip = apcm->chip;
97b71c94 2099 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 2100 int ret;
97b71c94 2101
eb49faa6
TI		 2102 dsp_lock(azx_dev);
2103 if (dsp_is_locked(azx_dev)) {
2104 ret = -EBUSY;
2105 goto unlock;
2106 }
2107
9ddf1aeb 2108 mark_runtime_wc(chip, azx_dev, substream, false);
97b71c94
TI		 2109 azx_dev->bufsize = 0;
2110 azx_dev->period_bytes = 0;
2111 azx_dev->format_val = 0;
27fe48d9 2112 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 2113 params_buffer_bytes(hw_params));
27fe48d9 2114 if (ret < 0)
eb49faa6 2115 goto unlock;
9ddf1aeb 2116 mark_runtime_wc(chip, azx_dev, substream, true);
eb49faa6
TI		 2117 unlock:
2118 dsp_unlock(azx_dev);
27fe48d9 2119 return ret;
1da177e4
LT		 2120}
2121
a98f90fd 2122static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 2123{
2124 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2125 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 2126 struct azx *chip = apcm->chip;
1da177e4
LT		 2127 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2128
2129 /* reset BDL address */
eb49faa6
TI		 2130 dsp_lock(azx_dev);
2131 if (!dsp_is_locked(azx_dev)) {
2132 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2133 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2134 azx_sd_writel(azx_dev, SD_CTL, 0);
2135 azx_dev->bufsize = 0;
2136 azx_dev->period_bytes = 0;
2137 azx_dev->format_val = 0;
2138 }
1da177e4 2139
eb541337 2140 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 2141
9ddf1aeb 2142 mark_runtime_wc(chip, azx_dev, substream, false);
eb49faa6
TI		 2143 azx_dev->prepared = 0;
2144 dsp_unlock(azx_dev);
1da177e4
LT		 2145 return snd_pcm_lib_free_pages(substream);
2146}
2147
a98f90fd 2148static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 2149{
2150 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 2151 struct azx *chip = apcm->chip;
2152 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 2153 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 2154 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 2155 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 2156 int err;
7c935976
SW		 2157 struct hda_spdif_out *spdif =
2158 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2159 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 2160
eb49faa6
TI		 2161 dsp_lock(azx_dev);
2162 if (dsp_is_locked(azx_dev)) {
2163 err = -EBUSY;
2164 goto unlock;
2165 }
2166
fa00e046 2167 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 2168 format_val = snd_hda_calc_stream_format(runtime->rate,
2169 runtime->channels,
2170 runtime->format,
32c168c8 2171 hinfo->maxbps,
7c935976 2172 ctls);
97b71c94 2173 if (!format_val) {
d01ce99f 2174 snd_printk(KERN_ERR SFX
445a51b3
DB		 2175 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2176 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
eb49faa6
TI		 2177 err = -EINVAL;
2178 goto unlock;
1da177e4
LT		 2179 }
2180
97b71c94
TI		 2181 bufsize = snd_pcm_lib_buffer_bytes(substream);
2182 period_bytes = snd_pcm_lib_period_bytes(substream);
2183
445a51b3
DB		 2184 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2185 pci_name(chip->pci), bufsize, format_val);
97b71c94
TI		 2186
2187 if (bufsize != azx_dev->bufsize ||
2188 period_bytes != azx_dev->period_bytes ||
915bf29e
TI		 2189 format_val != azx_dev->format_val ||
2190 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
97b71c94
TI		 2191 azx_dev->bufsize = bufsize;
2192 azx_dev->period_bytes = period_bytes;
2193 azx_dev->format_val = format_val;
915bf29e 2194 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
97b71c94
TI		 2195 err = azx_setup_periods(chip, substream, azx_dev);
2196 if (err < 0)
eb49faa6 2197 goto unlock;
97b71c94
TI		 2198 }
2199
e8648e5e
TI		 2200 /* when LPIB delay correction gives a small negative value,
2201 * we ignore it; currently set the threshold statically to
2202 * 64 frames
2203 */
2204 if (runtime->period_size > 64)
2205 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
2206 else
2207 azx_dev->delay_negative_threshold = 0;
2208
e5463720
JK		 2209 /* wallclk has 24Mhz clock source */
2210 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2211 runtime->rate) * 1000);
1da177e4
LT		 2212 azx_setup_controller(chip, azx_dev);
2213 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2214 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2215 else
2216 azx_dev->fifo_size = 0;
2217
62b7e5e0
TI		 2218 stream_tag = azx_dev->stream_tag;
2219 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 2220 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 2221 stream_tag > chip->capture_streams)
2222 stream_tag -= chip->capture_streams;
eb49faa6 2223 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 2224 azx_dev->format_val, substream);
eb49faa6
TI		 2225
2226 unlock:
2227 if (!err)
2228 azx_dev->prepared = 1;
2229 dsp_unlock(azx_dev);
2230 return err;
1da177e4
LT		 2231}
2232
a98f90fd 2233static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 2234{
2235 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2236 struct azx *chip = apcm->chip;
850f0e52
TI		 2237 struct azx_dev *azx_dev;
2238 struct snd_pcm_substream *s;
fa00e046 2239 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 2240 int nwait, timeout;
1da177e4 2241
1a8506d4
TI		 2242 azx_dev = get_azx_dev(substream);
2243 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2244
eb49faa6
TI		 2245 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2246 return -EPIPE;
2247
1da177e4 2248 switch (cmd) {
fa00e046
JK		 2249 case SNDRV_PCM_TRIGGER_START:
2250 rstart = 1;
1da177e4
LT		 2251 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2252 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 2253 start = 1;
1da177e4
LT		 2254 break;
2255 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 2256 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 2257 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 2258 start = 0;
1da177e4
LT		 2259 break;
2260 default:
850f0e52
TI		 2261 return -EINVAL;
2262 }
2263
2264 snd_pcm_group_for_each_entry(s, substream) {
2265 if (s->pcm->card != substream->pcm->card)
2266 continue;
2267 azx_dev = get_azx_dev(s);
2268 sbits |= 1 << azx_dev->index;
2269 nsync++;
2270 snd_pcm_trigger_done(s, substream);
2271 }
2272
2273 spin_lock(&chip->reg_lock);
172d3b20
PLB		 2274
2275 /* first, set SYNC bits of corresponding streams */
2276 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2277 azx_writel(chip, OLD_SSYNC,
2278 azx_readl(chip, OLD_SSYNC) | sbits);
2279 else
2280 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2281
850f0e52
TI		 2282 snd_pcm_group_for_each_entry(s, substream) {
2283 if (s->pcm->card != substream->pcm->card)
2284 continue;
2285 azx_dev = get_azx_dev(s);
e5463720
JK		 2286 if (start) {
2287 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2288 if (!rstart)
2289 azx_dev->start_wallclk -=
2290 azx_dev->period_wallclk;
850f0e52 2291 azx_stream_start(chip, azx_dev);
e5463720 2292 } else {
850f0e52 2293 azx_stream_stop(chip, azx_dev);
e5463720 2294 }
850f0e52 2295 azx_dev->running = start;
1da177e4
LT		 2296 }
2297 spin_unlock(&chip->reg_lock);
850f0e52 2298 if (start) {
850f0e52
TI		 2299 /* wait until all FIFOs get ready */
2300 for (timeout = 5000; timeout; timeout--) {
2301 nwait = 0;
2302 snd_pcm_group_for_each_entry(s, substream) {
2303 if (s->pcm->card != substream->pcm->card)
2304 continue;
2305 azx_dev = get_azx_dev(s);
2306 if (!(azx_sd_readb(azx_dev, SD_STS) &
2307 SD_STS_FIFO_READY))
2308 nwait++;
2309 }
2310 if (!nwait)
2311 break;
2312 cpu_relax();
2313 }
2314 } else {
2315 /* wait until all RUN bits are cleared */
2316 for (timeout = 5000; timeout; timeout--) {
2317 nwait = 0;
2318 snd_pcm_group_for_each_entry(s, substream) {
2319 if (s->pcm->card != substream->pcm->card)
2320 continue;
2321 azx_dev = get_azx_dev(s);
2322 if (azx_sd_readb(azx_dev, SD_CTL) &
2323 SD_CTL_DMA_START)
2324 nwait++;
2325 }
2326 if (!nwait)
2327 break;
2328 cpu_relax();
2329 }
1da177e4 2330 }
172d3b20
PLB		 2331 spin_lock(&chip->reg_lock);
2332 /* reset SYNC bits */
2333 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2334 azx_writel(chip, OLD_SSYNC,
2335 azx_readl(chip, OLD_SSYNC) & ~sbits);
2336 else
2337 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
5d890f59
PLB		 2338 if (start) {
2339 azx_timecounter_init(substream, 0, 0);
2340 if (nsync > 1) {
2341 cycle_t cycle_last;
2342
2343 /* same start cycle for master and group */
2344 azx_dev = get_azx_dev(substream);
2345 cycle_last = azx_dev->azx_tc.cycle_last;
2346
2347 snd_pcm_group_for_each_entry(s, substream) {
2348 if (s->pcm->card != substream->pcm->card)
2349 continue;
2350 azx_timecounter_init(s, 1, cycle_last);
2351 }
2352 }
2353 }
172d3b20 2354 spin_unlock(&chip->reg_lock);
850f0e52 2355 return 0;
1da177e4
LT		 2356}
2357
0e153474
JC		 2358/* get the current DMA position with correction on VIA chips */
2359static unsigned int azx_via_get_position(struct azx *chip,
2360 struct azx_dev *azx_dev)
2361{
2362 unsigned int link_pos, mini_pos, bound_pos;
2363 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2364 unsigned int fifo_size;
2365
2366 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2367 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2368 /* Playback, no problem using link position */
2369 return link_pos;
2370 }
2371
2372 /* Capture */
2373 /* For new chipset,
2374 * use mod to get the DMA position just like old chipset
2375 */
2376 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2377 mod_dma_pos %= azx_dev->period_bytes;
2378
2379 /* azx_dev->fifo_size can't get FIFO size of in stream.
2380 * Get from base address + offset.
2381 */
2382 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2383
2384 if (azx_dev->insufficient) {
2385 /* Link position never gather than FIFO size */
2386 if (link_pos <= fifo_size)
2387 return 0;
2388
2389 azx_dev->insufficient = 0;
2390 }
2391
2392 if (link_pos <= fifo_size)
2393 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2394 else
2395 mini_pos = link_pos - fifo_size;
2396
2397 /* Find nearest previous boudary */
2398 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2399 mod_link_pos = link_pos % azx_dev->period_bytes;
2400 if (mod_link_pos >= fifo_size)
2401 bound_pos = link_pos - mod_link_pos;
2402 else if (mod_dma_pos >= mod_mini_pos)
2403 bound_pos = mini_pos - mod_mini_pos;
2404 else {
2405 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2406 if (bound_pos >= azx_dev->bufsize)
2407 bound_pos = 0;
2408 }
2409
2410 /* Calculate real DMA position we want */
2411 return bound_pos + mod_dma_pos;
2412}
2413
9ad593f6 2414static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2415 struct azx_dev *azx_dev,
2416 bool with_check)
1da177e4 2417{
21229613
TI		 2418 struct snd_pcm_substream *substream = azx_dev->substream;
2419 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1da177e4 2420 unsigned int pos;
21229613
TI		 2421 int stream = substream->stream;
2422 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
1a8506d4 2423 int delay = 0;
1da177e4 2424
4cb36310
DH		 2425 switch (chip->position_fix[stream]) {
2426 case POS_FIX_LPIB:
2427 /* read LPIB */
2428 pos = azx_sd_readl(azx_dev, SD_LPIB);
2429 break;
2430 case POS_FIX_VIACOMBO:
0e153474 2431 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2432 break;
2433 default:
2434 /* use the position buffer */
2435 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2436 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2437 if (!pos || pos == (u32)-1) {
2438 printk(KERN_WARNING
2439 "hda-intel: Invalid position buffer, "
2440 "using LPIB read method instead.\n");
2441 chip->position_fix[stream] = POS_FIX_LPIB;
2442 pos = azx_sd_readl(azx_dev, SD_LPIB);
2443 } else
2444 chip->position_fix[stream] = POS_FIX_POSBUF;
2445 }
2446 break;
c74db86b 2447 }
4cb36310 2448
1da177e4
LT		 2449 if (pos >= azx_dev->bufsize)
2450 pos = 0;
90accc58
PLB		 2451
2452 /* calculate runtime delay from LPIB */
21229613 2453 if (substream->runtime &&
90accc58
PLB		 2454 chip->position_fix[stream] == POS_FIX_POSBUF &&
2455 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2456 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
90accc58
PLB		 2457 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2458 delay = pos - lpib_pos;
2459 else
2460 delay = lpib_pos - pos;
e8648e5e
TI		 2461 if (delay < 0) {
2462 if (delay >= azx_dev->delay_negative_threshold)
2463 delay = 0;
2464 else
2465 delay += azx_dev->bufsize;
2466 }
90accc58 2467 if (delay >= azx_dev->period_bytes) {
1f04661f 2468 snd_printk(KERN_WARNING SFX
445a51b3 2469 "%s: Unstable LPIB (%d >= %d); "
1f04661f 2470 "disabling LPIB delay counting\n",
445a51b3 2471 pci_name(chip->pci), delay, azx_dev->period_bytes);
1f04661f
TI		 2472 delay = 0;
2473 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
90accc58 2474 }
21229613 2475 delay = bytes_to_frames(substream->runtime, delay);
90accc58 2476 }
21229613
TI		 2477
2478 if (substream->runtime) {
2479 if (hinfo->ops.get_delay)
2480 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2481 substream);
2482 substream->runtime->delay = delay;
2483 }
2484
1a8506d4 2485 trace_azx_get_position(chip, azx_dev, pos, delay);
9ad593f6
TI		 2486 return pos;
2487}
2488
2489static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2490{
2491 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2492 struct azx *chip = apcm->chip;
2493 struct azx_dev *azx_dev = get_azx_dev(substream);
2494 return bytes_to_frames(substream->runtime,
798cb7e8 2495 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2496}
2497
2498/*
2499 * Check whether the current DMA position is acceptable for updating
2500 * periods. Returns non-zero if it's OK.
2501 *
2502 * Many HD-audio controllers appear pretty inaccurate about
2503 * the update-IRQ timing. The IRQ is issued before actually the
2504 * data is processed. So, we need to process it afterwords in a
2505 * workqueue.
2506 */
2507static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2508{
e5463720 2509 u32 wallclk;
9ad593f6
TI		 2510 unsigned int pos;
2511
f48f606d
JK		 2512 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2513 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2514 return -1; /* bogus (too early) interrupt */
fa00e046 2515
798cb7e8 2516 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2517
d6d8bf54
TI		 2518 if (WARN_ONCE(!azx_dev->period_bytes,
2519 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2520 return -1; /* this shouldn't happen! */
edb39935 2521 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2522 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2523 /* NG - it's below the first next period boundary */
2524 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2525 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2526 return 1; /* OK, it's fine */
2527}
2528
2529/*
2530 * The work for pending PCM period updates.
2531 */
2532static void azx_irq_pending_work(struct work_struct *work)
2533{
2534 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2535 int i, pending, ok;
9ad593f6 2536
a6a950a8
TI		 2537 if (!chip->irq_pending_warned) {
2538 printk(KERN_WARNING
2539 "hda-intel: IRQ timing workaround is activated "
2540 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2541 chip->card->number);
2542 chip->irq_pending_warned = 1;
2543 }
2544
9ad593f6
TI		 2545 for (;;) {
2546 pending = 0;
2547 spin_lock_irq(&chip->reg_lock);
2548 for (i = 0; i < chip->num_streams; i++) {
2549 struct azx_dev *azx_dev = &chip->azx_dev[i];
2550 if (!azx_dev->irq_pending ||
2551 !azx_dev->substream ||
2552 !azx_dev->running)
2553 continue;
e5463720
JK		 2554 ok = azx_position_ok(chip, azx_dev);
2555 if (ok > 0) {
9ad593f6
TI		 2556 azx_dev->irq_pending = 0;
2557 spin_unlock(&chip->reg_lock);
2558 snd_pcm_period_elapsed(azx_dev->substream);
2559 spin_lock(&chip->reg_lock);
e5463720
JK		 2560 } else if (ok < 0) {
2561 pending = 0; /* too early */
9ad593f6
TI		 2562 } else
2563 pending++;
2564 }
2565 spin_unlock_irq(&chip->reg_lock);
2566 if (!pending)
2567 return;
08af495f 2568 msleep(1);
9ad593f6
TI		 2569 }
2570}
2571
2572/* clear irq_pending flags and assure no on-going workq */
2573static void azx_clear_irq_pending(struct azx *chip)
2574{
2575 int i;
2576
2577 spin_lock_irq(&chip->reg_lock);
2578 for (i = 0; i < chip->num_streams; i++)
2579 chip->azx_dev[i].irq_pending = 0;
2580 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2581}
2582
27fe48d9
TI		 2583#ifdef CONFIG_X86
2584static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2585 struct vm_area_struct *area)
2586{
2587 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2588 struct azx *chip = apcm->chip;
2589 if (!azx_snoop(chip))
2590 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2591 return snd_pcm_lib_default_mmap(substream, area);
2592}
2593#else
2594#define azx_pcm_mmap NULL
2595#endif
2596
a98f90fd 2597static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2598 .open = azx_pcm_open,
2599 .close = azx_pcm_close,
2600 .ioctl = snd_pcm_lib_ioctl,
2601 .hw_params = azx_pcm_hw_params,
2602 .hw_free = azx_pcm_hw_free,
2603 .prepare = azx_pcm_prepare,
2604 .trigger = azx_pcm_trigger,
2605 .pointer = azx_pcm_pointer,
5d890f59 2606 .wall_clock = azx_get_wallclock_tstamp,
27fe48d9 2607 .mmap = azx_pcm_mmap,
4ce107b9 2608 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2609};
2610
a98f90fd 2611static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2612{
176d5335
TI		 2613 struct azx_pcm *apcm = pcm->private_data;
2614 if (apcm) {
01b65bfb 2615 list_del(&apcm->list);
176d5335
TI		 2616 kfree(apcm);
2617 }
1da177e4
LT		 2618}
2619
acfa634f
TI		 2620#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2621
176d5335 2622static int
33fa35ed
TI		 2623azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2624 struct hda_pcm *cpcm)
1da177e4 2625{
33fa35ed 2626 struct azx *chip = bus->private_data;
a98f90fd 2627 struct snd_pcm *pcm;
1da177e4 2628 struct azx_pcm *apcm;
176d5335 2629 int pcm_dev = cpcm->device;
acfa634f 2630 unsigned int size;
176d5335 2631 int s, err;
1da177e4 2632
01b65bfb
TI		 2633 list_for_each_entry(apcm, &chip->pcm_list, list) {
2634 if (apcm->pcm->device == pcm_dev) {
445a51b3
DB		 2635 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2636 pci_name(chip->pci), pcm_dev);
01b65bfb
TI		 2637 return -EBUSY;
2638 }
176d5335
TI		 2639 }
2640 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2641 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2642 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2643 &pcm);
2644 if (err < 0)
2645 return err;
18cb7109 2646 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2647 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2648 if (apcm == NULL)
2649 return -ENOMEM;
2650 apcm->chip = chip;
01b65bfb 2651 apcm->pcm = pcm;
1da177e4 2652 apcm->codec = codec;
1da177e4
LT		 2653 pcm->private_data = apcm;
2654 pcm->private_free = azx_pcm_free;
176d5335
TI		 2655 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2656 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2657 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2658 cpcm->pcm = pcm;
2659 for (s = 0; s < 2; s++) {
2660 apcm->hinfo[s] = &cpcm->stream[s];
2661 if (cpcm->stream[s].substreams)
2662 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2663 }
2664 /* buffer pre-allocation */
acfa634f
TI		 2665 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2666 if (size > MAX_PREALLOC_SIZE)
2667 size = MAX_PREALLOC_SIZE;
4ce107b9 2668 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2669 snd_dma_pci_data(chip->pci),
acfa634f 2670 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2671 return 0;
2672}
2673
2674/*
2675 * mixer creation - all stuff is implemented in hda module
2676 */
e23e7a14 2677static int azx_mixer_create(struct azx *chip)
1da177e4
LT		 2678{
2679 return snd_hda_build_controls(chip->bus);
2680}
2681
2682
2683/*
2684 * initialize SD streams
2685 */
e23e7a14 2686static int azx_init_stream(struct azx *chip)
1da177e4
LT		 2687{
2688 int i;
2689
2690 /* initialize each stream (aka device)
d01ce99f
TI		 2691 * assign the starting bdl address to each stream (device)
2692 * and initialize
1da177e4 2693 */
07e4ca50 2694 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2695 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2696 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2697 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2698 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2699 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2700 azx_dev->sd_int_sta_mask = 1 << i;
2701 /* stream tag: must be non-zero and unique */
2702 azx_dev->index = i;
2703 azx_dev->stream_tag = i + 1;
2704 }
2705
2706 return 0;
2707}
2708
68e7fffc
TI		 2709static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2710{
437a5a46
TI		 2711 if (request_irq(chip->pci->irq, azx_interrupt,
2712 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2713 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2714 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2715 "disabling device\n", chip->pci->irq);
2716 if (do_disconnect)
2717 snd_card_disconnect(chip->card);
2718 return -1;
2719 }
2720 chip->irq = chip->pci->irq;
69e13418 2721 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2722 return 0;
2723}
2724
1da177e4 2725
cb53c626
TI		 2726static void azx_stop_chip(struct azx *chip)
2727{
95e99fda 2728 if (!chip->initialized)
cb53c626
TI		 2729 return;
2730
2731 /* disable interrupts */
2732 azx_int_disable(chip);
2733 azx_int_clear(chip);
2734
2735 /* disable CORB/RIRB */
2736 azx_free_cmd_io(chip);
2737
2738 /* disable position buffer */
2739 azx_writel(chip, DPLBASE, 0);
2740 azx_writel(chip, DPUBASE, 0);
2741
2742 chip->initialized = 0;
2743}
2744
1d1a4564
TI		 2745#ifdef CONFIG_SND_HDA_DSP_LOADER
2746/*
2747 * DSP loading code (e.g. for CA0132)
2748 */
2749
2750/* use the first stream for loading DSP */
2751static struct azx_dev *
2752azx_get_dsp_loader_dev(struct azx *chip)
2753{
2754 return &chip->azx_dev[chip->playback_index_offset];
2755}
2756
2757static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2758 unsigned int byte_size,
2759 struct snd_dma_buffer *bufp)
2760{
2761 u32 *bdl;
2762 struct azx *chip = bus->private_data;
2763 struct azx_dev *azx_dev;
2764 int err;
2765
eb49faa6
TI		 2766 azx_dev = azx_get_dsp_loader_dev(chip);
2767
2768 dsp_lock(azx_dev);
2769 spin_lock_irq(&chip->reg_lock);
2770 if (azx_dev->running || azx_dev->locked) {
2771 spin_unlock_irq(&chip->reg_lock);
2772 err = -EBUSY;
2773 goto unlock;
2774 }
2775 azx_dev->prepared = 0;
2776 chip->saved_azx_dev = *azx_dev;
2777 azx_dev->locked = 1;
2778 spin_unlock_irq(&chip->reg_lock);
1d1a4564
TI		 2779
2780 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2781 snd_dma_pci_data(chip->pci),
2782 byte_size, bufp);
2783 if (err < 0)
eb49faa6 2784 goto err_alloc;
1d1a4564 2785
b3667bd7 2786 mark_pages_wc(chip, bufp, true);
1d1a4564
TI		 2787 azx_dev->bufsize = byte_size;
2788 azx_dev->period_bytes = byte_size;
2789 azx_dev->format_val = format;
2790
2791 azx_stream_reset(chip, azx_dev);
2792
2793 /* reset BDL address */
2794 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2795 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2796
2797 azx_dev->frags = 0;
2798 bdl = (u32 *)azx_dev->bdl.area;
2799 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2800 if (err < 0)
2801 goto error;
2802
2803 azx_setup_controller(chip, azx_dev);
eb49faa6 2804 dsp_unlock(azx_dev);
1d1a4564
TI		 2805 return azx_dev->stream_tag;
2806
2807 error:
b3667bd7
TI		 2808 mark_pages_wc(chip, bufp, false);
2809 snd_dma_free_pages(bufp);
eb49faa6
TI		 2810 err_alloc:
2811 spin_lock_irq(&chip->reg_lock);
2812 if (azx_dev->opened)
2813 *azx_dev = chip->saved_azx_dev;
2814 azx_dev->locked = 0;
2815 spin_unlock_irq(&chip->reg_lock);
2816 unlock:
2817 dsp_unlock(azx_dev);
1d1a4564
TI		 2818 return err;
2819}
2820
2821static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2822{
2823 struct azx *chip = bus->private_data;
2824 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2825
2826 if (start)
2827 azx_stream_start(chip, azx_dev);
2828 else
2829 azx_stream_stop(chip, azx_dev);
2830 azx_dev->running = start;
2831}
2832
2833static void azx_load_dsp_cleanup(struct hda_bus *bus,
2834 struct snd_dma_buffer *dmab)
2835{
2836 struct azx *chip = bus->private_data;
2837 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2838
eb49faa6 2839 if (!dmab->area || !azx_dev->locked)
b3667bd7
TI		 2840 return;
2841
eb49faa6 2842 dsp_lock(azx_dev);
1d1a4564
TI		 2843 /* reset BDL address */
2844 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2845 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2846 azx_sd_writel(azx_dev, SD_CTL, 0);
2847 azx_dev->bufsize = 0;
2848 azx_dev->period_bytes = 0;
2849 azx_dev->format_val = 0;
2850
b3667bd7 2851 mark_pages_wc(chip, dmab, false);
1d1a4564 2852 snd_dma_free_pages(dmab);
b3667bd7 2853 dmab->area = NULL;
1d1a4564 2854
eb49faa6
TI		 2855 spin_lock_irq(&chip->reg_lock);
2856 if (azx_dev->opened)
2857 *azx_dev = chip->saved_azx_dev;
2858 azx_dev->locked = 0;
2859 spin_unlock_irq(&chip->reg_lock);
2860 dsp_unlock(azx_dev);
1d1a4564
TI		 2861}
2862#endif /* CONFIG_SND_HDA_DSP_LOADER */
2863
83012a7c 2864#ifdef CONFIG_PM
cb53c626 2865/* power-up/down the controller */
68467f51 2866static void azx_power_notify(struct hda_bus *bus, bool power_up)
cb53c626 2867{
33fa35ed 2868 struct azx *chip = bus->private_data;
cb53c626 2869
2ea3c6a2
TI		 2870 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2871 return;
2872
68467f51 2873 if (power_up)
b8dfc462
ML		 2874 pm_runtime_get_sync(&chip->pci->dev);
2875 else
2876 pm_runtime_put_sync(&chip->pci->dev);
cb53c626 2877}
65fcd41d
TI		 2878
2879static DEFINE_MUTEX(card_list_lock);
2880static LIST_HEAD(card_list);
2881
2882static void azx_add_card_list(struct azx *chip)
2883{
2884 mutex_lock(&card_list_lock);
2885 list_add(&chip->list, &card_list);
2886 mutex_unlock(&card_list_lock);
2887}
2888
2889static void azx_del_card_list(struct azx *chip)
2890{
2891 mutex_lock(&card_list_lock);
2892 list_del_init(&chip->list);
2893 mutex_unlock(&card_list_lock);
2894}
2895
2896/* trigger power-save check at writing parameter */
2897static int param_set_xint(const char *val, const struct kernel_param *kp)
2898{
2899 struct azx *chip;
2900 struct hda_codec *c;
2901 int prev = power_save;
2902 int ret = param_set_int(val, kp);
2903
2904 if (ret || prev == power_save)
2905 return ret;
2906
2907 mutex_lock(&card_list_lock);
2908 list_for_each_entry(chip, &card_list, list) {
2909 if (!chip->bus || chip->disabled)
2910 continue;
2911 list_for_each_entry(c, &chip->bus->codec_list, list)
2912 snd_hda_power_sync(c);
2913 }
2914 mutex_unlock(&card_list_lock);
2915 return 0;
2916}
2917#else
2918#define azx_add_card_list(chip) /* NOP */
2919#define azx_del_card_list(chip) /* NOP */
83012a7c 2920#endif /* CONFIG_PM */
5c0b9bec 2921
7ccbde57 2922#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 2923/*
2924 * power management
2925 */
68cb2b55 2926static int azx_suspend(struct device *dev)
1da177e4 2927{
68cb2b55
TI		 2928 struct pci_dev *pci = to_pci_dev(dev);
2929 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2930 struct azx *chip = card->private_data;
01b65bfb 2931 struct azx_pcm *p;
1da177e4 2932
c5c21523
TI		 2933 if (chip->disabled)
2934 return 0;
2935
421a1252 2936 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2937 azx_clear_irq_pending(chip);
01b65bfb
TI		 2938 list_for_each_entry(p, &chip->pcm_list, list)
2939 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2940 if (chip->initialized)
8dd78330 2941 snd_hda_suspend(chip->bus);
cb53c626 2942 azx_stop_chip(chip);
7295b264 2943 azx_enter_link_reset(chip);
30b35399 2944 if (chip->irq >= 0) {
43001c95 2945 free_irq(chip->irq, chip);
30b35399
TI		 2946 chip->irq = -1;
2947 }
68e7fffc 2948 if (chip->msi)
43001c95 2949 pci_disable_msi(chip->pci);
421a1252
TI		 2950 pci_disable_device(pci);
2951 pci_save_state(pci);
68cb2b55 2952 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 2953 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2954 hda_display_power(false);
1da177e4
LT		 2955 return 0;
2956}
2957
68cb2b55 2958static int azx_resume(struct device *dev)
1da177e4 2959{
68cb2b55
TI		 2960 struct pci_dev *pci = to_pci_dev(dev);
2961 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2962 struct azx *chip = card->private_data;
1da177e4 2963
c5c21523
TI		 2964 if (chip->disabled)
2965 return 0;
2966
99a2008d
WX		 2967 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2968 hda_display_power(true);
d14a7e0b
TI		 2969 pci_set_power_state(pci, PCI_D0);
2970 pci_restore_state(pci);
30b35399
TI		 2971 if (pci_enable_device(pci) < 0) {
2972 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2973 "disabling device\n");
2974 snd_card_disconnect(card);
2975 return -EIO;
2976 }
2977 pci_set_master(pci);
68e7fffc
TI		 2978 if (chip->msi)
2979 if (pci_enable_msi(pci) < 0)
2980 chip->msi = 0;
2981 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2982 return -EIO;
cb53c626 2983 azx_init_pci(chip);
d804ad92 2984
7f30830b 2985 azx_init_chip(chip, 1);
d804ad92 2986
1da177e4 2987 snd_hda_resume(chip->bus);
421a1252 2988 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2989 return 0;
2990}
b8dfc462
ML		 2991#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2992
2993#ifdef CONFIG_PM_RUNTIME
2994static int azx_runtime_suspend(struct device *dev)
2995{
2996 struct snd_card *card = dev_get_drvdata(dev);
2997 struct azx *chip = card->private_data;
2998
246efa4a
DA		 2999 if (chip->disabled)
3000 return 0;
3001
3002 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3003 return 0;
3004
7d4f606c
WX		 3005 /* enable controller wake up event */
3006 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
3007 STATESTS_INT_MASK);
3008
b8dfc462 3009 azx_stop_chip(chip);
873ce8ad 3010 azx_enter_link_reset(chip);
b8dfc462 3011 azx_clear_irq_pending(chip);
99a2008d
WX		 3012 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3013 hda_display_power(false);
b8dfc462
ML		 3014 return 0;
3015}
3016
3017static int azx_runtime_resume(struct device *dev)
3018{
3019 struct snd_card *card = dev_get_drvdata(dev);
3020 struct azx *chip = card->private_data;
7d4f606c
WX		 3021 struct hda_bus *bus;
3022 struct hda_codec *codec;
3023 int status;
b8dfc462 3024
246efa4a
DA		 3025 if (chip->disabled)
3026 return 0;
3027
3028 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3029 return 0;
3030
99a2008d
WX		 3031 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3032 hda_display_power(true);
7d4f606c
WX		 3033
3034 /* Read STATESTS before controller reset */
3035 status = azx_readw(chip, STATESTS);
3036
b8dfc462
ML		 3037 azx_init_pci(chip);
3038 azx_init_chip(chip, 1);
7d4f606c
WX		 3039
3040 bus = chip->bus;
3041 if (status && bus) {
3042 list_for_each_entry(codec, &bus->codec_list, list)
3043 if (status & (1 << codec->addr))
3044 queue_delayed_work(codec->bus->workq,
3045 &codec->jackpoll_work, codec->jackpoll_interval);
3046 }
3047
3048 /* disable controller Wake Up event*/
3049 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
3050 ~STATESTS_INT_MASK);
3051
b8dfc462
ML		 3052 return 0;
3053}
6eb827d2
TI		 3054
3055static int azx_runtime_idle(struct device *dev)
3056{
3057 struct snd_card *card = dev_get_drvdata(dev);
3058 struct azx *chip = card->private_data;
3059
246efa4a
DA		 3060 if (chip->disabled)
3061 return 0;
3062
6eb827d2
TI		 3063 if (!power_save_controller ||
3064 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3065 return -EBUSY;
3066
3067 return 0;
3068}
3069
b8dfc462
ML		 3070#endif /* CONFIG_PM_RUNTIME */
3071
3072#ifdef CONFIG_PM
3073static const struct dev_pm_ops azx_pm = {
3074 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 3075 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 3076};
3077
68cb2b55
TI		 3078#define AZX_PM_OPS &azx_pm
3079#else
68cb2b55 3080#define AZX_PM_OPS NULL
b8dfc462 3081#endif /* CONFIG_PM */
1da177e4
LT		 3082
3083
0cbf0098
TI		 3084/*
3085 * reboot notifier for hang-up problem at power-down
3086 */
3087static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3088{
3089 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 3090 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 3091 azx_stop_chip(chip);
3092 return NOTIFY_OK;
3093}
3094
3095static void azx_notifier_register(struct azx *chip)
3096{
3097 chip->reboot_notifier.notifier_call = azx_halt;
3098 register_reboot_notifier(&chip->reboot_notifier);
3099}
3100
3101static void azx_notifier_unregister(struct azx *chip)
3102{
3103 if (chip->reboot_notifier.notifier_call)
3104 unregister_reboot_notifier(&chip->reboot_notifier);
3105}
3106
48c8b0eb 3107static int azx_probe_continue(struct azx *chip);
a82d51ed 3108
8393ec4a 3109#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 3110static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 3111
a82d51ed
TI		 3112static void azx_vs_set_state(struct pci_dev *pci,
3113 enum vga_switcheroo_state state)
3114{
3115 struct snd_card *card = pci_get_drvdata(pci);
3116 struct azx *chip = card->private_data;
3117 bool disabled;
3118
f4c482a4 3119 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 3120 if (chip->init_failed)
3121 return;
3122
3123 disabled = (state == VGA_SWITCHEROO_OFF);
3124 if (chip->disabled == disabled)
3125 return;
3126
3127 if (!chip->bus) {
3128 chip->disabled = disabled;
3129 if (!disabled) {
3130 snd_printk(KERN_INFO SFX
3131 "%s: Start delayed initialization\n",
3132 pci_name(chip->pci));
5c90680e 3133 if (azx_probe_continue(chip) < 0) {
a82d51ed
TI		 3134 snd_printk(KERN_ERR SFX
3135 "%s: initialization error\n",
3136 pci_name(chip->pci));
3137 chip->init_failed = true;
3138 }
3139 }
3140 } else {
3141 snd_printk(KERN_INFO SFX
445a51b3
DB		 3142 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3143 disabled ? "Disabling" : "Enabling");
a82d51ed 3144 if (disabled) {
246efa4a 3145 pm_runtime_put_sync_suspend(&pci->dev);
68cb2b55 3146 azx_suspend(&pci->dev);
246efa4a
DA		 3147 /* when we get suspended by vga switcheroo we end up in D3cold,
3148 * however we have no ACPI handle, so pci/acpi can't put us there,
3149 * put ourselves there */
3150 pci->current_state = PCI_D3cold;
a82d51ed 3151 chip->disabled = true;
128960a9 3152 if (snd_hda_lock_devices(chip->bus))
445a51b3
DB		 3153 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3154 pci_name(chip->pci));
a82d51ed
TI		 3155 } else {
3156 snd_hda_unlock_devices(chip->bus);
246efa4a 3157 pm_runtime_get_noresume(&pci->dev);
a82d51ed 3158 chip->disabled = false;
68cb2b55 3159 azx_resume(&pci->dev);
a82d51ed
TI		 3160 }
3161 }
3162}
3163
3164static bool azx_vs_can_switch(struct pci_dev *pci)
3165{
3166 struct snd_card *card = pci_get_drvdata(pci);
3167 struct azx *chip = card->private_data;
3168
f4c482a4 3169 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 3170 if (chip->init_failed)
3171 return false;
3172 if (chip->disabled || !chip->bus)
3173 return true;
3174 if (snd_hda_lock_devices(chip->bus))
3175 return false;
3176 snd_hda_unlock_devices(chip->bus);
3177 return true;
3178}
3179
e23e7a14 3180static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 3181{
3182 struct pci_dev *p = get_bound_vga(chip->pci);
3183 if (p) {
3184 snd_printk(KERN_INFO SFX
3185 "%s: Handle VGA-switcheroo audio client\n",
3186 pci_name(chip->pci));
3187 chip->use_vga_switcheroo = 1;
3188 pci_dev_put(p);
3189 }
3190}
3191
3192static const struct vga_switcheroo_client_ops azx_vs_ops = {
3193 .set_gpu_state = azx_vs_set_state,
3194 .can_switch = azx_vs_can_switch,
3195};
3196
e23e7a14 3197static int register_vga_switcheroo(struct azx *chip)
a82d51ed 3198{
128960a9
TI		 3199 int err;
3200
a82d51ed
TI		 3201 if (!chip->use_vga_switcheroo)
3202 return 0;
3203 /* FIXME: currently only handling DIS controller
3204 * is there any machine with two switchable HDMI audio controllers?
3205 */
128960a9 3206 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 3207 VGA_SWITCHEROO_DIS,
3208 chip->bus != NULL);
128960a9
TI		 3209 if (err < 0)
3210 return err;
3211 chip->vga_switcheroo_registered = 1;
246efa4a
DA		 3212
3213 /* register as an optimus hdmi audio power domain */
3214 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(&chip->pci->dev, &chip->hdmi_pm_domain);
128960a9 3215 return 0;
a82d51ed
TI		 3216}
3217#else
3218#define init_vga_switcheroo(chip) /* NOP */
3219#define register_vga_switcheroo(chip) 0
8393ec4a 3220#define check_hdmi_disabled(pci) false
a82d51ed
TI		 3221#endif /* SUPPORT_VGA_SWITCHER */
3222
1da177e4
LT		 3223/*
3224 * destructor
3225 */
a98f90fd 3226static int azx_free(struct azx *chip)
1da177e4 3227{
c67e2228 3228 struct pci_dev *pci = chip->pci;
4ce107b9
TI		 3229 int i;
3230
c67e2228
WX		 3231 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
3232 && chip->running)
3233 pm_runtime_get_noresume(&pci->dev);
3234
65fcd41d
TI		 3235 azx_del_card_list(chip);
3236
0cbf0098
TI		 3237 azx_notifier_unregister(chip);
3238
f4c482a4 3239 chip->init_failed = 1; /* to be sure */
44728e97 3240 complete_all(&chip->probe_wait);
f4c482a4 3241
a82d51ed
TI		 3242 if (use_vga_switcheroo(chip)) {
3243 if (chip->disabled && chip->bus)
3244 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 3245 if (chip->vga_switcheroo_registered)
3246 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 3247 }
3248
ce43fbae 3249 if (chip->initialized) {
9ad593f6 3250 azx_clear_irq_pending(chip);
07e4ca50 3251 for (i = 0; i < chip->num_streams; i++)
1da177e4 3252 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 3253 azx_stop_chip(chip);
1da177e4
LT		 3254 }
3255
f000fd80 3256 if (chip->irq >= 0)
1da177e4 3257 free_irq(chip->irq, (void*)chip);
68e7fffc 3258 if (chip->msi)
30b35399 3259 pci_disable_msi(chip->pci);
f079c25a
TI		 3260 if (chip->remap_addr)
3261 iounmap(chip->remap_addr);
1da177e4 3262
4ce107b9
TI		 3263 if (chip->azx_dev) {
3264 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 3265 if (chip->azx_dev[i].bdl.area) {
3266 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 3267 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 3268 }
4ce107b9 3269 }
27fe48d9
TI		 3270 if (chip->rb.area) {
3271 mark_pages_wc(chip, &chip->rb, false);
1da177e4 3272 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 3273 }
3274 if (chip->posbuf.area) {
3275 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 3276 snd_dma_free_pages(&chip->posbuf);
27fe48d9 3277 }
a82d51ed
TI		 3278 if (chip->region_requested)
3279 pci_release_regions(chip->pci);
1da177e4 3280 pci_disable_device(chip->pci);
07e4ca50 3281 kfree(chip->azx_dev);
4918cdab
TI		 3282#ifdef CONFIG_SND_HDA_PATCH_LOADER
3283 if (chip->fw)
3284 release_firmware(chip->fw);
3285#endif
99a2008d
WX		 3286 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3287 hda_display_power(false);
3288 hda_i915_exit();
3289 }
1da177e4
LT		 3290 kfree(chip);
3291
3292 return 0;
3293}
3294
a98f90fd 3295static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 3296{
3297 return azx_free(device->device_data);
3298}
3299
8393ec4a 3300#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 3301/*
3302 * Check of disabled HDMI controller by vga-switcheroo
3303 */
e23e7a14 3304static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 3305{
3306 struct pci_dev *p;
3307
3308 /* check only discrete GPU */
3309 switch (pci->vendor) {
3310 case PCI_VENDOR_ID_ATI:
3311 case PCI_VENDOR_ID_AMD:
3312 case PCI_VENDOR_ID_NVIDIA:
3313 if (pci->devfn == 1) {
3314 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3315 pci->bus->number, 0);
3316 if (p) {
3317 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3318 return p;
3319 pci_dev_put(p);
3320 }
3321 }
3322 break;
3323 }
3324 return NULL;
3325}
3326
e23e7a14 3327static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 3328{
3329 bool vga_inactive = false;
3330 struct pci_dev *p = get_bound_vga(pci);
3331
3332 if (p) {
12b78a7f 3333 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 3334 vga_inactive = true;
3335 pci_dev_put(p);
3336 }
3337 return vga_inactive;
3338}
8393ec4a 3339#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 3340
3372a153
TI		 3341/*
3342 * white/black-listing for position_fix
3343 */
e23e7a14 3344static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 3345 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3346 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 3347 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 3348 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 3349 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 3350 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 3351 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 3352 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 3353 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 3354 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 3355 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 3356 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 3357 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 3358 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 3359 {}
3360};
3361
e23e7a14 3362static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 3363{
3364 const struct snd_pci_quirk *q;
3365
c673ba1c 3366 switch (fix) {
1dac6695 3367 case POS_FIX_AUTO:
c673ba1c
TI		 3368 case POS_FIX_LPIB:
3369 case POS_FIX_POSBUF:
4cb36310 3370 case POS_FIX_VIACOMBO:
a6f2fd55 3371 case POS_FIX_COMBO:
c673ba1c
TI		 3372 return fix;
3373 }
3374
c673ba1c
TI		 3375 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3376 if (q) {
3377 printk(KERN_INFO
3378 "hda_intel: position_fix set to %d "
3379 "for device %04x:%04x\n",
3380 q->value, q->subvendor, q->subdevice);
3381 return q->value;
3372a153 3382 }
bdd9ef24
DH		 3383
3384 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 3385 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
445a51b3 3386 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
bdd9ef24 3387 return POS_FIX_VIACOMBO;
9477c58e
TI		 3388 }
3389 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
445a51b3 3390 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
50e3bbf9 3391 return POS_FIX_LPIB;
bdd9ef24 3392 }
c673ba1c 3393 return POS_FIX_AUTO;
3372a153
TI		 3394}
3395
669ba27a
TI		 3396/*
3397 * black-lists for probe_mask
3398 */
e23e7a14 3399static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 3400 /* Thinkpad often breaks the controller communication when accessing
3401 * to the non-working (or non-existing) modem codec slot.
3402 */
3403 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3404 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3405 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 3406 /* broken BIOS */
3407 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 3408 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3409 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 3410 /* forced codec slots */
93574844 3411 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 3412 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 3413 /* WinFast VP200 H (Teradici) user reported broken communication */
3414 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 3415 {}
3416};
3417
f1eaaeec
TI		 3418#define AZX_FORCE_CODEC_MASK 0x100
3419
e23e7a14 3420static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 3421{
3422 const struct snd_pci_quirk *q;
3423
f1eaaeec
TI		 3424 chip->codec_probe_mask = probe_mask[dev];
3425 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 3426 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3427 if (q) {
3428 printk(KERN_INFO
3429 "hda_intel: probe_mask set to 0x%x "
3430 "for device %04x:%04x\n",
3431 q->value, q->subvendor, q->subdevice);
f1eaaeec 3432 chip->codec_probe_mask = q->value;
669ba27a
TI		 3433 }
3434 }
f1eaaeec
TI		 3435
3436 /* check forced option */
3437 if (chip->codec_probe_mask != -1 &&
3438 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3439 chip->codec_mask = chip->codec_probe_mask & 0xff;
3440 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3441 chip->codec_mask);
3442 }
669ba27a
TI		 3443}
3444
4d8e22e0 3445/*
71623855 3446 * white/black-list for enable_msi
4d8e22e0 3447 */
e23e7a14 3448static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 3449 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
3450 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
3451 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
3452 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 3453 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 3454 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 3455 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 3456 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 3457 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 3458 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 3459 {}
3460};
3461
e23e7a14 3462static void check_msi(struct azx *chip)
4d8e22e0
TI		 3463{
3464 const struct snd_pci_quirk *q;
3465
71623855
TI		 3466 if (enable_msi >= 0) {
3467 chip->msi = !!enable_msi;
4d8e22e0 3468 return;
71623855
TI		 3469 }
3470 chip->msi = 1; /* enable MSI as default */
3471 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 3472 if (q) {
3473 printk(KERN_INFO
3474 "hda_intel: msi for device %04x:%04x set to %d\n",
3475 q->subvendor, q->subdevice, q->value);
3476 chip->msi = q->value;
80c43ed7
TI		 3477 return;
3478 }
3479
3480 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 3481 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3482 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 3483 chip->msi = 0;
4d8e22e0
TI		 3484 }
3485}
3486
a1585d76 3487/* check the snoop mode availability */
e23e7a14 3488static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 3489{
3490 bool snoop = chip->snoop;
3491
3492 switch (chip->driver_type) {
3493 case AZX_DRIVER_VIA:
3494 /* force to non-snoop mode for a new VIA controller
3495 * when BIOS is set
3496 */
3497 if (snoop) {
3498 u8 val;
3499 pci_read_config_byte(chip->pci, 0x42, &val);
3500 if (!(val & 0x80) && chip->pci->revision == 0x30)
3501 snoop = false;
3502 }
3503 break;
3504 case AZX_DRIVER_ATIHDMI_NS:
3505 /* new ATI HDMI requires non-snoop */
3506 snoop = false;
3507 break;
c1279f87
TI		 3508 case AZX_DRIVER_CTHDA:
3509 snoop = false;
3510 break;
a1585d76
TI		 3511 }
3512
3513 if (snoop != chip->snoop) {
445a51b3
DB		 3514 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3515 pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
a1585d76
TI		 3516 chip->snoop = snoop;
3517 }
3518}
669ba27a 3519
99a2008d
WX		 3520static void azx_probe_work(struct work_struct *work)
3521{
3522 azx_probe_continue(container_of(work, struct azx, probe_work));
3523}
99a2008d 3524
1da177e4
LT		 3525/*
3526 * constructor
3527 */
e23e7a14
BP		 3528static int azx_create(struct snd_card *card, struct pci_dev *pci,
3529 int dev, unsigned int driver_caps,
3530 struct azx **rchip)
1da177e4 3531{
a98f90fd 3532 static struct snd_device_ops ops = {
1da177e4
LT		 3533 .dev_free = azx_dev_free,
3534 };
a82d51ed
TI		 3535 struct azx *chip;
3536 int err;
1da177e4
LT		 3537
3538 *rchip = NULL;
bcd72003 3539
927fc866
PM		 3540 err = pci_enable_device(pci);
3541 if (err < 0)
1da177e4
LT		 3542 return err;
3543
e560d8d8 3544 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 3545 if (!chip) {
445a51b3 3546 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
1da177e4
LT		 3547 pci_disable_device(pci);
3548 return -ENOMEM;
3549 }
3550
3551 spin_lock_init(&chip->reg_lock);
62932df8 3552 mutex_init(&chip->open_mutex);
1da177e4
LT		 3553 chip->card = card;
3554 chip->pci = pci;
3555 chip->irq = -1;
9477c58e
TI		 3556 chip->driver_caps = driver_caps;
3557 chip->driver_type = driver_caps & 0xff;
4d8e22e0 3558 check_msi(chip);
555e219f 3559 chip->dev_index = dev;
9ad593f6 3560 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 3561 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 3562 INIT_LIST_HEAD(&chip->list);
a82d51ed 3563 init_vga_switcheroo(chip);
f4c482a4 3564 init_completion(&chip->probe_wait);
1da177e4 3565
beaffc39
SG		 3566 chip->position_fix[0] = chip->position_fix[1] =
3567 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 3568 /* combo mode uses LPIB for playback */
3569 if (chip->position_fix[0] == POS_FIX_COMBO) {
3570 chip->position_fix[0] = POS_FIX_LPIB;
3571 chip->position_fix[1] = POS_FIX_AUTO;
3572 }
3573
5aba4f8e 3574 check_probe_mask(chip, dev);
3372a153 3575
27346166 3576 chip->single_cmd = single_cmd;
27fe48d9 3577 chip->snoop = hda_snoop;
a1585d76 3578 azx_check_snoop_available(chip);
c74db86b 3579
5c0d7bc1
TI		 3580 if (bdl_pos_adj[dev] < 0) {
3581 switch (chip->driver_type) {
0c6341ac 3582 case AZX_DRIVER_ICH:
32679f95 3583 case AZX_DRIVER_PCH:
0c6341ac 3584 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 3585 break;
3586 default:
0c6341ac 3587 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 3588 break;
3589 }
3590 }
3591
a82d51ed
TI		 3592 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3593 if (err < 0) {
445a51b3
DB		 3594 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3595 pci_name(chip->pci));
a82d51ed
TI		 3596 azx_free(chip);
3597 return err;
3598 }
3599
99a2008d
WX		 3600 /* continue probing in work context as may trigger request module */
3601 INIT_WORK(&chip->probe_work, azx_probe_work);
99a2008d 3602
a82d51ed 3603 *rchip = chip;
99a2008d 3604
a82d51ed
TI		 3605 return 0;
3606}
3607
48c8b0eb 3608static int azx_first_init(struct azx *chip)
a82d51ed
TI		 3609{
3610 int dev = chip->dev_index;
3611 struct pci_dev *pci = chip->pci;
3612 struct snd_card *card = chip->card;
3613 int i, err;
3614 unsigned short gcap;
3615
07e4ca50
TI		 3616#if BITS_PER_LONG != 64
3617 /* Fix up base address on ULI M5461 */
3618 if (chip->driver_type == AZX_DRIVER_ULI) {
3619 u16 tmp3;
3620 pci_read_config_word(pci, 0x40, &tmp3);
3621 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3622 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3623 }
3624#endif
3625
927fc866 3626 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 3627 if (err < 0)
1da177e4 3628 return err;
a82d51ed 3629 chip->region_requested = 1;
1da177e4 3630
927fc866 3631 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 3632 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 3633 if (chip->remap_addr == NULL) {
445a51b3 3634 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
a82d51ed 3635 return -ENXIO;
1da177e4
LT		 3636 }
3637
68e7fffc
TI		 3638 if (chip->msi)
3639 if (pci_enable_msi(pci) < 0)
3640 chip->msi = 0;
7376d013 3641
a82d51ed
TI		 3642 if (azx_acquire_irq(chip, 0) < 0)
3643 return -EBUSY;
1da177e4
LT		 3644
3645 pci_set_master(pci);
3646 synchronize_irq(chip->irq);
3647
bcd72003 3648 gcap = azx_readw(chip, GCAP);
445a51b3 3649 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
bcd72003 3650
dc4c2e6b 3651 /* disable SB600 64bit support for safety */
9477c58e 3652 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3653 struct pci_dev *p_smbus;
3654 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3655 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3656 NULL);
3657 if (p_smbus) {
3658 if (p_smbus->revision < 0x30)
3659 gcap &= ~ICH6_GCAP_64OK;
3660 pci_dev_put(p_smbus);
3661 }
3662 }
09240cf4 3663
9477c58e
TI		 3664 /* disable 64bit DMA address on some devices */
3665 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
445a51b3 3666 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
396087ea 3667 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3668 }
396087ea 3669
2ae66c26 3670 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3671 if (align_buffer_size >= 0)
3672 chip->align_buffer_size = !!align_buffer_size;
3673 else {
3674 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3675 chip->align_buffer_size = 0;
3676 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3677 chip->align_buffer_size = 1;
3678 else
3679 chip->align_buffer_size = 1;
3680 }
2ae66c26 3681
cf7aaca8 3682 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3683 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3684 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3685 else {
e930438c
YH		 3686 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3687 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3688 }
cf7aaca8 3689
8b6ed8e7
TI		 3690 /* read number of streams from GCAP register instead of using
3691 * hardcoded value
3692 */
3693 chip->capture_streams = (gcap >> 8) & 0x0f;
3694 chip->playback_streams = (gcap >> 12) & 0x0f;
3695 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3696 /* gcap didn't give any info, switching to old method */
3697
3698 switch (chip->driver_type) {
3699 case AZX_DRIVER_ULI:
3700 chip->playback_streams = ULI_NUM_PLAYBACK;
3701 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3702 break;
3703 case AZX_DRIVER_ATIHDMI:
1815b34a 3704 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3705 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3706 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3707 break;
c4da29ca 3708 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3709 default:
3710 chip->playback_streams = ICH6_NUM_PLAYBACK;
3711 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3712 break;
3713 }
07e4ca50 3714 }
8b6ed8e7
TI		 3715 chip->capture_index_offset = 0;
3716 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3717 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3718 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3719 GFP_KERNEL);
927fc866 3720 if (!chip->azx_dev) {
445a51b3 3721 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
a82d51ed 3722 return -ENOMEM;
07e4ca50
TI		 3723 }
3724
4ce107b9 3725 for (i = 0; i < chip->num_streams; i++) {
eb49faa6 3726 dsp_lock_init(&chip->azx_dev[i]);
4ce107b9
TI		 3727 /* allocate memory for the BDL for each stream */
3728 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3729 snd_dma_pci_data(chip->pci),
3730 BDL_SIZE, &chip->azx_dev[i].bdl);
3731 if (err < 0) {
445a51b3 3732 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
a82d51ed 3733 return -ENOMEM;
4ce107b9 3734 }
27fe48d9 3735 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3736 }
0be3b5d3 3737 /* allocate memory for the position buffer */
d01ce99f
TI		 3738 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3739 snd_dma_pci_data(chip->pci),
3740 chip->num_streams * 8, &chip->posbuf);
3741 if (err < 0) {
445a51b3 3742 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
a82d51ed 3743 return -ENOMEM;
1da177e4 3744 }
27fe48d9 3745 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3746 /* allocate CORB/RIRB */
81740861
TI		 3747 err = azx_alloc_cmd_io(chip);
3748 if (err < 0)
a82d51ed 3749 return err;
1da177e4
LT		 3750
3751 /* initialize streams */
3752 azx_init_stream(chip);
3753
3754 /* initialize chip */
cb53c626 3755 azx_init_pci(chip);
10e77dda 3756 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3757
3758 /* codec detection */
927fc866 3759 if (!chip->codec_mask) {
445a51b3 3760 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
a82d51ed 3761 return -ENODEV;
1da177e4
LT		 3762 }
3763
07e4ca50 3764 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3765 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3766 sizeof(card->shortname));
3767 snprintf(card->longname, sizeof(card->longname),
3768 "%s at 0x%lx irq %i",
3769 card->shortname, chip->addr, chip->irq);
07e4ca50 3770
1da177e4 3771 return 0;
1da177e4
LT		 3772}
3773
cb53c626
TI		 3774static void power_down_all_codecs(struct azx *chip)
3775{
83012a7c 3776#ifdef CONFIG_PM
cb53c626
TI		 3777 /* The codecs were powered up in snd_hda_codec_new().
3778 * Now all initialization done, so turn them down if possible
3779 */
3780 struct hda_codec *codec;
3781 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3782 snd_hda_power_down(codec);
3783 }
3784#endif
3785}
3786
97c6a3d1 3787#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 3788/* callback from request_firmware_nowait() */
3789static void azx_firmware_cb(const struct firmware *fw, void *context)
3790{
3791 struct snd_card *card = context;
3792 struct azx *chip = card->private_data;
3793 struct pci_dev *pci = chip->pci;
3794
3795 if (!fw) {
445a51b3
DB		 3796 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3797 pci_name(chip->pci));
5cb543db
TI		 3798 goto error;
3799 }
3800
3801 chip->fw = fw;
3802 if (!chip->disabled) {
3803 /* continue probing */
3804 if (azx_probe_continue(chip))
3805 goto error;
3806 }
3807 return; /* OK */
3808
3809 error:
3810 snd_card_free(card);
3811 pci_set_drvdata(pci, NULL);
3812}
97c6a3d1 3813#endif
5cb543db 3814
e23e7a14
BP		 3815static int azx_probe(struct pci_dev *pci,
3816 const struct pci_device_id *pci_id)
1da177e4 3817{
5aba4f8e 3818 static int dev;
a98f90fd
TI		 3819 struct snd_card *card;
3820 struct azx *chip;
aad730d0 3821 bool schedule_probe;
927fc866 3822 int err;
1da177e4 3823
5aba4f8e
TI		 3824 if (dev >= SNDRV_CARDS)
3825 return -ENODEV;
3826 if (!enable[dev]) {
3827 dev++;
3828 return -ENOENT;
3829 }
3830
e58de7ba
TI		 3831 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3832 if (err < 0) {
445a51b3 3833 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
e58de7ba 3834 return err;
1da177e4
LT		 3835 }
3836
4ea6fbc8
TI		 3837 snd_card_set_dev(card, &pci->dev);
3838
5aba4f8e 3839 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3840 if (err < 0)
3841 goto out_free;
421a1252 3842 card->private_data = chip;
f4c482a4
TI		 3843
3844 pci_set_drvdata(pci, card);
3845
3846 err = register_vga_switcheroo(chip);
3847 if (err < 0) {
3848 snd_printk(KERN_ERR SFX
445a51b3 3849 "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
f4c482a4
TI		 3850 goto out_free;
3851 }
3852
3853 if (check_hdmi_disabled(pci)) {
445a51b3 3854 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
f4c482a4 3855 pci_name(pci));
445a51b3 3856 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
f4c482a4
TI		 3857 chip->disabled = true;
3858 }
3859
aad730d0 3860 schedule_probe = !chip->disabled;
1da177e4 3861
4918cdab
TI		 3862#ifdef CONFIG_SND_HDA_PATCH_LOADER
3863 if (patch[dev] && *patch[dev]) {
445a51b3
DB		 3864 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3865 pci_name(pci), patch[dev]);
5cb543db
TI		 3866 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3867 &pci->dev, GFP_KERNEL, card,
3868 azx_firmware_cb);
4918cdab
TI		 3869 if (err < 0)
3870 goto out_free;
aad730d0 3871 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 3872 }
3873#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3874
aad730d0
TI		 3875#ifndef CONFIG_SND_HDA_I915
3876 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
99a2008d
WX		 3877 snd_printk(KERN_ERR SFX "Haswell must build in CONFIG_SND_HDA_I915\n");
3878#endif
99a2008d 3879
aad730d0
TI		 3880 if (schedule_probe)
3881 schedule_work(&chip->probe_work);
a82d51ed 3882
a82d51ed 3883 dev++;
88d071fc
TI		 3884 if (chip->disabled)
3885 complete_all(&chip->probe_wait);
a82d51ed
TI		 3886 return 0;
3887
3888out_free:
3889 snd_card_free(card);
3890 return err;
3891}
3892
48c8b0eb 3893static int azx_probe_continue(struct azx *chip)
a82d51ed 3894{
c67e2228 3895 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 3896 int dev = chip->dev_index;
3897 int err;
3898
99a2008d
WX		 3899 /* Request power well for Haswell HDA controller and codec */
3900 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 3901#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 3902 err = hda_i915_init();
3903 if (err < 0) {
3904 snd_printk(KERN_ERR SFX "Error request power-well from i915\n");
3905 goto out_free;
3906 }
c841ad2a 3907#endif
99a2008d
WX		 3908 hda_display_power(true);
3909 }
3910
5c90680e
TI		 3911 err = azx_first_init(chip);
3912 if (err < 0)
3913 goto out_free;
3914
2dca0bba
JK		 3915#ifdef CONFIG_SND_HDA_INPUT_BEEP
3916 chip->beep_mode = beep_mode[dev];
3917#endif
3918
1da177e4 3919 /* create codec instances */
a1e21c90 3920 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3921 if (err < 0)
3922 goto out_free;
4ea6fbc8 3923#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 3924 if (chip->fw) {
3925 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3926 chip->fw->data);
4ea6fbc8
TI		 3927 if (err < 0)
3928 goto out_free;
e39ae856 3929#ifndef CONFIG_PM
4918cdab
TI		 3930 release_firmware(chip->fw); /* no longer needed */
3931 chip->fw = NULL;
e39ae856 3932#endif
4ea6fbc8
TI		 3933 }
3934#endif
10e77dda 3935 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3936 err = azx_codec_configure(chip);
3937 if (err < 0)
3938 goto out_free;
3939 }
1da177e4
LT		 3940
3941 /* create PCM streams */
176d5335 3942 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3943 if (err < 0)
3944 goto out_free;
1da177e4
LT		 3945
3946 /* create mixer controls */
d01ce99f 3947 err = azx_mixer_create(chip);
41dda0fd
WF		 3948 if (err < 0)
3949 goto out_free;
1da177e4 3950
a82d51ed 3951 err = snd_card_register(chip->card);
41dda0fd
WF		 3952 if (err < 0)
3953 goto out_free;
1da177e4 3954
cb53c626
TI		 3955 chip->running = 1;
3956 power_down_all_codecs(chip);
0cbf0098 3957 azx_notifier_register(chip);
65fcd41d 3958 azx_add_card_list(chip);
246efa4a 3959 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
c67e2228 3960 pm_runtime_put_noidle(&pci->dev);
1da177e4 3961
41dda0fd 3962out_free:
88d071fc
TI		 3963 if (err < 0)
3964 chip->init_failed = 1;
3965 complete_all(&chip->probe_wait);
41dda0fd 3966 return err;
1da177e4
LT		 3967}
3968
e23e7a14 3969static void azx_remove(struct pci_dev *pci)
1da177e4 3970{
9121947d 3971 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 3972
9121947d
TI		 3973 if (card)
3974 snd_card_free(card);
1da177e4
LT		 3975}
3976
3977/* PCI IDs */
cebe41d4 3978static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3979 /* CPT */
9477c58e 3980 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 3981 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 3982 /* PBG */
9477c58e 3983 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 3984 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 3985 /* Panther Point */
9477c58e 3986 { PCI_DEVICE(0x8086, 0x1e20),
b1920c21 3987 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 3988 /* Lynx Point */
3989 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 3990 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 3991 /* Wellsburg */
3992 { PCI_DEVICE(0x8086, 0x8d20),
3993 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3994 { PCI_DEVICE(0x8086, 0x8d21),
3995 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3996 /* Lynx Point-LP */
3997 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 3998 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3999 /* Lynx Point-LP */
4000 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 4001 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 4002 /* Wildcat Point-LP */
4003 { PCI_DEVICE(0x8086, 0x9ca0),
4004 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 4005 /* Haswell */
4a7c516b 4006 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 4007 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 4008 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 4009 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 4010 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 4011 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
99df18b3
PLB		 4012 /* 5 Series/3400 */
4013 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 4014 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 4015 /* Poulsbo */
9477c58e 4016 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 4017 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4018 /* Oaktrail */
09904b95 4019 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 4020 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 4021 /* BayTrail */
4022 { PCI_DEVICE(0x8086, 0x0f04),
4023 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
645e9035 4024 /* ICH */
8b0bd226 4025 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 4026 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4027 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 4028 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 4029 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4030 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 4031 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 4032 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4033 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 4034 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 4035 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4036 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 4037 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 4038 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4039 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 4040 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 4041 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4042 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 4043 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 4044 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4045 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 4046 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 4047 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4048 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 4049 /* Generic Intel */
4050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
4051 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4052 .class_mask = 0xffffff,
2ae66c26 4053 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 4054 /* ATI SB 450/600/700/800/900 */
4055 { PCI_DEVICE(0x1002, 0x437b),
4056 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4057 { PCI_DEVICE(0x1002, 0x4383),
4058 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4059 /* AMD Hudson */
4060 { PCI_DEVICE(0x1022, 0x780d),
4061 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 4062 /* ATI HDMI */
9477c58e
TI		 4063 { PCI_DEVICE(0x1002, 0x793b),
4064 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4065 { PCI_DEVICE(0x1002, 0x7919),
4066 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4067 { PCI_DEVICE(0x1002, 0x960f),
4068 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4069 { PCI_DEVICE(0x1002, 0x970f),
4070 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4071 { PCI_DEVICE(0x1002, 0xaa00),
4072 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4073 { PCI_DEVICE(0x1002, 0xaa08),
4074 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4075 { PCI_DEVICE(0x1002, 0xaa10),
4076 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4077 { PCI_DEVICE(0x1002, 0xaa18),
4078 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4079 { PCI_DEVICE(0x1002, 0xaa20),
4080 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4081 { PCI_DEVICE(0x1002, 0xaa28),
4082 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4083 { PCI_DEVICE(0x1002, 0xaa30),
4084 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4085 { PCI_DEVICE(0x1002, 0xaa38),
4086 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4087 { PCI_DEVICE(0x1002, 0xaa40),
4088 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4089 { PCI_DEVICE(0x1002, 0xaa48),
4090 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 4091 { PCI_DEVICE(0x1002, 0xaa50),
4092 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4093 { PCI_DEVICE(0x1002, 0xaa58),
4094 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4095 { PCI_DEVICE(0x1002, 0xaa60),
4096 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4097 { PCI_DEVICE(0x1002, 0xaa68),
4098 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4099 { PCI_DEVICE(0x1002, 0xaa80),
4100 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4101 { PCI_DEVICE(0x1002, 0xaa88),
4102 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4103 { PCI_DEVICE(0x1002, 0xaa90),
4104 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4105 { PCI_DEVICE(0x1002, 0xaa98),
4106 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 4107 { PCI_DEVICE(0x1002, 0x9902),
4108 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4109 { PCI_DEVICE(0x1002, 0xaaa0),
4110 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4111 { PCI_DEVICE(0x1002, 0xaaa8),
4112 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4113 { PCI_DEVICE(0x1002, 0xaab0),
4114 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 4115 /* VIA VT8251/VT8237A */
9477c58e
TI		 4116 { PCI_DEVICE(0x1106, 0x3288),
4117 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 4118 /* VIA GFX VT7122/VX900 */
4119 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
4120 /* VIA GFX VT6122/VX11 */
4121 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 4122 /* SIS966 */
4123 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
4124 /* ULI M5461 */
4125 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
4126 /* NVIDIA MCP */
0c2fd1bf
TI		 4127 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
4128 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4129 .class_mask = 0xffffff,
9477c58e 4130 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 4131 /* Teradici */
9477c58e
TI		 4132 { PCI_DEVICE(0x6549, 0x1200),
4133 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 4134 { PCI_DEVICE(0x6549, 0x2200),
4135 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 4136 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 4137 /* CTHDA chips */
4138 { PCI_DEVICE(0x1102, 0x0010),
4139 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4140 { PCI_DEVICE(0x1102, 0x0012),
4141 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
313f6e2d
TI		 4142#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
4143 /* the following entry conflicts with snd-ctxfi driver,
4144 * as ctxfi driver mutates from HD-audio to native mode with
4145 * a special command sequence.
4146 */
4e01f54b
TI		 4147 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4148 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4149 .class_mask = 0xffffff,
9477c58e 4150 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 4151 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 4152#else
4153 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 4154 { PCI_DEVICE(0x1102, 0x0009),
4155 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 4156 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 4157#endif
e35d4b11
OS		 4158 /* Vortex86MX */
4159 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 4160 /* VMware HDAudio */
4161 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 4162 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 4163 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4164 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4165 .class_mask = 0xffffff,
9477c58e 4166 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 4167 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4168 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4169 .class_mask = 0xffffff,
9477c58e 4170 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 4171 { 0, }
4172};
4173MODULE_DEVICE_TABLE(pci, azx_ids);
4174
4175/* pci_driver definition */
e9f66d9b 4176static struct pci_driver azx_driver = {
3733e424 4177 .name = KBUILD_MODNAME,
1da177e4
LT		 4178 .id_table = azx_ids,
4179 .probe = azx_probe,
e23e7a14 4180 .remove = azx_remove,
68cb2b55
TI		 4181 .driver = {
4182 .pm = AZX_PM_OPS,
4183 },
1da177e4
LT		 4184};
4185
e9f66d9b 4186module_pci_driver(azx_driver);
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