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ALSA: hda - Fixes distorted recording on US15W chipset
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
362775e2 40#include <linux/kernel.h>
1da177e4 41#include <linux/module.h>
24982c5f 42#include <linux/dma-mapping.h>
1da177e4
LT		 43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
62932df8 47#include <linux/mutex.h>
0cbf0098 48#include <linux/reboot.h>
1da177e4
LT		 49#include <sound/core.h>
50#include <sound/initval.h>
51#include "hda_codec.h"
52
53
5aba4f8e
TI		 54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57static char *model[SNDRV_CARDS];
58static int position_fix[SNDRV_CARDS];
5c0d7bc1 59static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 60static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 61static int probe_only[SNDRV_CARDS];
27346166 62static int single_cmd;
71623855 63static int enable_msi = -1;
4ea6fbc8
TI		 64#ifdef CONFIG_SND_HDA_PATCH_LOADER
65static char *patch[SNDRV_CARDS];
66#endif
2dca0bba
JK		 67#ifdef CONFIG_SND_HDA_INPUT_BEEP
68static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
70#endif
1da177e4 71
5aba4f8e 72module_param_array(index, int, NULL, 0444);
1da177e4 73MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 74module_param_array(id, charp, NULL, 0444);
1da177e4 75MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 76module_param_array(enable, bool, NULL, 0444);
77MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78module_param_array(model, charp, NULL, 0444);
1da177e4 79MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 80module_param_array(position_fix, int, NULL, 0444);
d01ce99f 81MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
d2e1c973 82 "(0 = auto, 1 = none, 2 = POSBUF).");
555e219f
TI		 83module_param_array(bdl_pos_adj, int, NULL, 0644);
84MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 85module_param_array(probe_mask, int, NULL, 0444);
606ad75f 86MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 87module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 88MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 89module_param(single_cmd, bool, 0444);
d01ce99f
TI		 90MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
5aba4f8e 92module_param(enable_msi, int, 0444);
134a11f0 93MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 94#ifdef CONFIG_SND_HDA_PATCH_LOADER
95module_param_array(patch, charp, NULL, 0444);
96MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97#endif
2dca0bba
JK		 98#ifdef CONFIG_SND_HDA_INPUT_BEEP
99module_param_array(beep_mode, int, NULL, 0444);
100MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102#endif
606ad75f 103
dee1b66c 104#ifdef CONFIG_SND_HDA_POWER_SAVE
fee2fba3
TI		 105static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106module_param(power_save, int, 0644);
107MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
1da177e4 109
dee1b66c
TI		 110/* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
112 * wake up.
113 */
114static int power_save_controller = 1;
115module_param(power_save_controller, bool, 0644);
116MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117#endif
118
1da177e4
LT		 119MODULE_LICENSE("GPL");
120MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121 "{Intel, ICH6M},"
2f1b3818 122 "{Intel, ICH7},"
f5d40b30 123 "{Intel, ESB2},"
d2981393 124 "{Intel, ICH8},"
f9cc8a8b 125 "{Intel, ICH9},"
c34f5a04 126 "{Intel, ICH10},"
b29c2360 127 "{Intel, PCH},"
d2f2fcd2 128 "{Intel, CPT},"
4979bca9 129 "{Intel, SCH},"
fc20a562 130 "{ATI, SB450},"
89be83f8 131 "{ATI, SB600},"
778b6e1b 132 "{ATI, RS600},"
5b15c95f 133 "{ATI, RS690},"
e6db1119
WL		 134 "{ATI, RS780},"
135 "{ATI, R600},"
2797f724
HRK		 136 "{ATI, RV630},"
137 "{ATI, RV610},"
27da1834
WL		 138 "{ATI, RV670},"
139 "{ATI, RV635},"
140 "{ATI, RV620},"
141 "{ATI, RV770},"
fc20a562 142 "{VIA, VT8251},"
47672310 143 "{VIA, VT8237A},"
07e4ca50
TI		 144 "{SiS, SIS966},"
145 "{ULI, M5461}}");
1da177e4
LT		 146MODULE_DESCRIPTION("Intel HDA driver");
147
4abc1cc2
TI		 148#ifdef CONFIG_SND_VERBOSE_PRINTK
149#define SFX /* nop */
150#else
1da177e4 151#define SFX "hda-intel: "
4abc1cc2 152#endif
cb53c626 153
1da177e4
LT		 154/*
155 * registers
156 */
157#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 158#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
159#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
160#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
161#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
162#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 163#define ICH6_REG_VMIN 0x02
164#define ICH6_REG_VMAJ 0x03
165#define ICH6_REG_OUTPAY 0x04
166#define ICH6_REG_INPAY 0x06
167#define ICH6_REG_GCTL 0x08
8a933ece 168#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 169#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
170#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 171#define ICH6_REG_WAKEEN 0x0c
172#define ICH6_REG_STATESTS 0x0e
173#define ICH6_REG_GSTS 0x10
b21fadb9 174#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 175#define ICH6_REG_INTCTL 0x20
176#define ICH6_REG_INTSTS 0x24
177#define ICH6_REG_WALCLK 0x30
178#define ICH6_REG_SYNC 0x34
179#define ICH6_REG_CORBLBASE 0x40
180#define ICH6_REG_CORBUBASE 0x44
181#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 182#define ICH6_REG_CORBRP 0x4a
183#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 184#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 185#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
186#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 187#define ICH6_REG_CORBSTS 0x4d
b21fadb9 188#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 189#define ICH6_REG_CORBSIZE 0x4e
190
191#define ICH6_REG_RIRBLBASE 0x50
192#define ICH6_REG_RIRBUBASE 0x54
193#define ICH6_REG_RIRBWP 0x58
b21fadb9 194#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 195#define ICH6_REG_RINTCNT 0x5a
196#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 197#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
198#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
199#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 200#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 201#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
202#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 203#define ICH6_REG_RIRBSIZE 0x5e
204
205#define ICH6_REG_IC 0x60
206#define ICH6_REG_IR 0x64
207#define ICH6_REG_IRS 0x68
208#define ICH6_IRS_VALID (1<<1)
209#define ICH6_IRS_BUSY (1<<0)
210
211#define ICH6_REG_DPLBASE 0x70
212#define ICH6_REG_DPUBASE 0x74
213#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
214
215/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
216enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
217
218/* stream register offsets from stream base */
219#define ICH6_REG_SD_CTL 0x00
220#define ICH6_REG_SD_STS 0x03
221#define ICH6_REG_SD_LPIB 0x04
222#define ICH6_REG_SD_CBL 0x08
223#define ICH6_REG_SD_LVI 0x0c
224#define ICH6_REG_SD_FIFOW 0x0e
225#define ICH6_REG_SD_FIFOSIZE 0x10
226#define ICH6_REG_SD_FORMAT 0x12
227#define ICH6_REG_SD_BDLPL 0x18
228#define ICH6_REG_SD_BDLPU 0x1c
229
230/* PCI space */
231#define ICH6_PCIREG_TCSEL 0x44
232
233/*
234 * other constants
235 */
236
237/* max number of SDs */
07e4ca50 238/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 239#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 240#define ICH6_NUM_PLAYBACK 4
241
242/* ULI has 6 playback and 5 capture */
07e4ca50 243#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 244#define ULI_NUM_PLAYBACK 6
245
778b6e1b 246/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 247#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 248#define ATIHDMI_NUM_PLAYBACK 1
249
f269002e
KY		 250/* TERA has 4 playback and 3 capture */
251#define TERA_NUM_CAPTURE 3
252#define TERA_NUM_PLAYBACK 4
253
07e4ca50
TI		 254/* this number is statically defined for simplicity */
255#define MAX_AZX_DEV 16
256
1da177e4 257/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 258#define BDL_SIZE 4096
259#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
260#define AZX_MAX_FRAG 32
1da177e4
LT		 261/* max buffer size - no h/w limit, you can increase as you like */
262#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 263
264/* RIRB int mask: overrun[2], response[0] */
265#define RIRB_INT_RESPONSE 0x01
266#define RIRB_INT_OVERRUN 0x04
267#define RIRB_INT_MASK 0x05
268
2f5983f2 269/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 270#define AZX_MAX_CODECS 8
271#define AZX_DEFAULT_CODECS 4
deadff16 272#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 273
274/* SD_CTL bits */
275#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
276#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 277#define SD_CTL_STRIPE (3 << 16) /* stripe control */
278#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
279#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 280#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
281#define SD_CTL_STREAM_TAG_SHIFT 20
282
283/* SD_CTL and SD_STS */
284#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
285#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
286#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 287#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
288 SD_INT_COMPLETE)
1da177e4
LT		 289
290/* SD_STS */
291#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
292
293/* INTCTL and INTSTS */
d01ce99f
TI		 294#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
295#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
296#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 297
1da177e4
LT		 298/* below are so far hardcoded - should read registers in future */
299#define ICH6_MAX_CORB_ENTRIES 256
300#define ICH6_MAX_RIRB_ENTRIES 256
301
c74db86b
TI		 302/* position fix mode */
303enum {
0be3b5d3 304 POS_FIX_AUTO,
d2e1c973 305 POS_FIX_LPIB,
0be3b5d3 306 POS_FIX_POSBUF,
c74db86b 307};
1da177e4 308
f5d40b30 309/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 310#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
311#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
312
da3fca21
V		 313/* Defines for Nvidia HDA support */
314#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
315#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 316#define NVIDIA_HDA_ISTRM_COH 0x4d
317#define NVIDIA_HDA_OSTRM_COH 0x4c
318#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 319
90a5ad52
TI		 320/* Defines for Intel SCH HDA snoop control */
321#define INTEL_SCH_HDA_DEVC 0x78
322#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
323
0e153474
JC		 324/* Define IN stream 0 FIFO size offset in VIA controller */
325#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
326/* Define VIA HD Audio Device ID*/
327#define VIA_HDAC_DEVICE_ID 0x3288
328
c4da29ca
YL		 329/* HD Audio class code */
330#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 331
1da177e4
LT		 332/*
333 */
334
a98f90fd 335struct azx_dev {
4ce107b9 336 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 337 u32 *posbuf; /* position buffer pointer */
1da177e4 338
d01ce99f 339 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 340 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 341 unsigned int frags; /* number for period in the play buffer */
342 unsigned int fifo_size; /* FIFO size */
fa00e046
JK		 343 unsigned long start_jiffies; /* start + minimum jiffies */
344 unsigned long min_jiffies; /* minimum jiffies before position is valid */
1da177e4 345
d01ce99f 346 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 347
d01ce99f 348 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 349
350 /* pcm support */
d01ce99f
TI		 351 struct snd_pcm_substream *substream; /* assigned substream,
352 * set in PCM open
353 */
354 unsigned int format_val; /* format value to be set in the
355 * controller and the codec
356 */
1da177e4
LT		 357 unsigned char stream_tag; /* assigned stream */
358 unsigned char index; /* stream index */
ef18bede 359 int device; /* last device number assigned to */
1da177e4 360
927fc866
PM		 361 unsigned int opened :1;
362 unsigned int running :1;
675f25d4 363 unsigned int irq_pending :1;
d523b0c8 364 unsigned int start_flag: 1; /* stream full start flag */
0e153474
JC		 365 /*
366 * For VIA:
367 * A flag to ensure DMA position is 0
368 * when link position is not greater than FIFO size
369 */
370 unsigned int insufficient :1;
1da177e4
LT		 371};
372
373/* CORB/RIRB */
a98f90fd 374struct azx_rb {
1da177e4
LT		 375 u32 *buf; /* CORB/RIRB buffer
376 * Each CORB entry is 4byte, RIRB is 8byte
377 */
378 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
379 /* for RIRB */
380 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 381 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
382 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 383};
384
a98f90fd
TI		 385struct azx {
386 struct snd_card *card;
1da177e4 387 struct pci_dev *pci;
555e219f 388 int dev_index;
1da177e4 389
07e4ca50
TI		 390 /* chip type specific */
391 int driver_type;
392 int playback_streams;
393 int playback_index_offset;
394 int capture_streams;
395 int capture_index_offset;
396 int num_streams;
397
1da177e4
LT		 398 /* pci resources */
399 unsigned long addr;
400 void __iomem *remap_addr;
401 int irq;
402
403 /* locks */
404 spinlock_t reg_lock;
62932df8 405 struct mutex open_mutex;
1da177e4 406
07e4ca50 407 /* streams (x num_streams) */
a98f90fd 408 struct azx_dev *azx_dev;
1da177e4
LT		 409
410 /* PCM */
c8936222 411 struct snd_pcm *pcm[HDA_MAX_PCMS];
1da177e4
LT		 412
413 /* HD codec */
414 unsigned short codec_mask;
f1eaaeec 415 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 416 struct hda_bus *bus;
2dca0bba 417 unsigned int beep_mode;
1da177e4
LT		 418
419 /* CORB/RIRB */
a98f90fd
TI		 420 struct azx_rb corb;
421 struct azx_rb rirb;
1da177e4 422
4ce107b9 423 /* CORB/RIRB and position buffers */
1da177e4
LT		 424 struct snd_dma_buffer rb;
425 struct snd_dma_buffer posbuf;
c74db86b
TI		 426
427 /* flags */
beaffc39 428 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 429 int poll_count;
cb53c626 430 unsigned int running :1;
927fc866
PM		 431 unsigned int initialized :1;
432 unsigned int single_cmd :1;
433 unsigned int polling_mode :1;
68e7fffc 434 unsigned int msi :1;
a6a950a8 435 unsigned int irq_pending_warned :1;
0e153474 436 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
6ce4a3bc 437 unsigned int probing :1; /* codec probing phase */
43bbb6cc
TI		 438
439 /* for debugging */
feb27340 440 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 441
442 /* for pending irqs */
443 struct work_struct irq_pending_work;
0cbf0098
TI		 444
445 /* reboot notifier (for mysterious hangup problem at power-down) */
446 struct notifier_block reboot_notifier;
1da177e4
LT		 447};
448
07e4ca50
TI		 449/* driver types */
450enum {
451 AZX_DRIVER_ICH,
32679f95 452 AZX_DRIVER_PCH,
4979bca9 453 AZX_DRIVER_SCH,
07e4ca50 454 AZX_DRIVER_ATI,
778b6e1b 455 AZX_DRIVER_ATIHDMI,
07e4ca50
TI		 456 AZX_DRIVER_VIA,
457 AZX_DRIVER_SIS,
458 AZX_DRIVER_ULI,
da3fca21 459 AZX_DRIVER_NVIDIA,
f269002e 460 AZX_DRIVER_TERA,
c4da29ca 461 AZX_DRIVER_GENERIC,
2f5983f2 462 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 463};
464
465static char *driver_short_names[] __devinitdata = {
466 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 467 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 468 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 469 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 470 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI		 471 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
472 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 473 [AZX_DRIVER_ULI] = "HDA ULI M5461",
474 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 475 [AZX_DRIVER_TERA] = "HDA Teradici",
c4da29ca 476 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 477};
478
1da177e4
LT		 479/*
480 * macros for easy use
481 */
482#define azx_writel(chip,reg,value) \
483 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
484#define azx_readl(chip,reg) \
485 readl((chip)->remap_addr + ICH6_REG_##reg)
486#define azx_writew(chip,reg,value) \
487 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
488#define azx_readw(chip,reg) \
489 readw((chip)->remap_addr + ICH6_REG_##reg)
490#define azx_writeb(chip,reg,value) \
491 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
492#define azx_readb(chip,reg) \
493 readb((chip)->remap_addr + ICH6_REG_##reg)
494
495#define azx_sd_writel(dev,reg,value) \
496 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
497#define azx_sd_readl(dev,reg) \
498 readl((dev)->sd_addr + ICH6_REG_##reg)
499#define azx_sd_writew(dev,reg,value) \
500 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
501#define azx_sd_readw(dev,reg) \
502 readw((dev)->sd_addr + ICH6_REG_##reg)
503#define azx_sd_writeb(dev,reg,value) \
504 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
505#define azx_sd_readb(dev,reg) \
506 readb((dev)->sd_addr + ICH6_REG_##reg)
507
508/* for pcm support */
a98f90fd 509#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 510
68e7fffc 511static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 512static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 513/*
514 * Interface for HD codec
515 */
516
1da177e4
LT		 517/*
518 * CORB / RIRB interface
519 */
a98f90fd 520static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 521{
522 int err;
523
524 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 525 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
526 snd_dma_pci_data(chip->pci),
1da177e4
LT		 527 PAGE_SIZE, &chip->rb);
528 if (err < 0) {
529 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
530 return err;
531 }
532 return 0;
533}
534
a98f90fd 535static void azx_init_cmd_io(struct azx *chip)
1da177e4 536{
cdb1fbf2 537 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 538 /* CORB set up */
539 chip->corb.addr = chip->rb.addr;
540 chip->corb.buf = (u32 *)chip->rb.area;
541 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 542 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 543
07e4ca50
TI		 544 /* set the corb size to 256 entries (ULI requires explicitly) */
545 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 546 /* set the corb write pointer to 0 */
547 azx_writew(chip, CORBWP, 0);
548 /* reset the corb hw read pointer */
b21fadb9 549 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 550 /* enable corb dma */
b21fadb9 551 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 552
553 /* RIRB set up */
554 chip->rirb.addr = chip->rb.addr + 2048;
555 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 556 chip->rirb.wp = chip->rirb.rp = 0;
557 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 558 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 559 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 560
07e4ca50
TI		 561 /* set the rirb size to 256 entries (ULI requires explicitly) */
562 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 563 /* reset the rirb hw write pointer */
b21fadb9 564 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4
LT		 565 /* set N=1, get RIRB response interrupt for new entry */
566 azx_writew(chip, RINTCNT, 1);
567 /* enable rirb dma and response irq */
1da177e4 568 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 569 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 570}
571
a98f90fd 572static void azx_free_cmd_io(struct azx *chip)
1da177e4 573{
cdb1fbf2 574 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 575 /* disable ringbuffer DMAs */
576 azx_writeb(chip, RIRBCTL, 0);
577 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 578 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 579}
580
deadff16
WF		 581static unsigned int azx_command_addr(u32 cmd)
582{
583 unsigned int addr = cmd >> 28;
584
585 if (addr >= AZX_MAX_CODECS) {
586 snd_BUG();
587 addr = 0;
588 }
589
590 return addr;
591}
592
593static unsigned int azx_response_addr(u32 res)
594{
595 unsigned int addr = res & 0xf;
596
597 if (addr >= AZX_MAX_CODECS) {
598 snd_BUG();
599 addr = 0;
600 }
601
602 return addr;
1da177e4
LT		 603}
604
605/* send a command */
33fa35ed 606static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 607{
33fa35ed 608 struct azx *chip = bus->private_data;
deadff16 609 unsigned int addr = azx_command_addr(val);
1da177e4 610 unsigned int wp;
1da177e4 611
c32649fe
WF		 612 spin_lock_irq(&chip->reg_lock);
613
1da177e4
LT		 614 /* add command to corb */
615 wp = azx_readb(chip, CORBWP);
616 wp++;
617 wp %= ICH6_MAX_CORB_ENTRIES;
618
deadff16 619 chip->rirb.cmds[addr]++;
1da177e4
LT		 620 chip->corb.buf[wp] = cpu_to_le32(val);
621 azx_writel(chip, CORBWP, wp);
c32649fe 622
1da177e4
LT		 623 spin_unlock_irq(&chip->reg_lock);
624
625 return 0;
626}
627
628#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
629
630/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 631static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 632{
633 unsigned int rp, wp;
deadff16 634 unsigned int addr;
1da177e4
LT		 635 u32 res, res_ex;
636
637 wp = azx_readb(chip, RIRBWP);
638 if (wp == chip->rirb.wp)
639 return;
640 chip->rirb.wp = wp;
deadff16 641
1da177e4
LT		 642 while (chip->rirb.rp != wp) {
643 chip->rirb.rp++;
644 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
645
646 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
647 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
648 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 649 addr = azx_response_addr(res_ex);
1da177e4
LT		 650 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
651 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 652 else if (chip->rirb.cmds[addr]) {
653 chip->rirb.res[addr] = res;
2add9b92 654 smp_wmb();
deadff16 655 chip->rirb.cmds[addr]--;
e310bb06
WF		 656 } else
657 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
658 "last cmd=%#08x\n",
659 res, res_ex,
660 chip->last_cmd[addr]);
1da177e4
LT		 661 }
662}
663
664/* receive a response */
deadff16
WF		 665static unsigned int azx_rirb_get_response(struct hda_bus *bus,
666 unsigned int addr)
1da177e4 667{
33fa35ed 668 struct azx *chip = bus->private_data;
5c79b1f8 669 unsigned long timeout;
1eb6dc7d 670 int do_poll = 0;
1da177e4 671
5c79b1f8
TI		 672 again:
673 timeout = jiffies + msecs_to_jiffies(1000);
28a0d9df 674 for (;;) {
1eb6dc7d 675 if (chip->polling_mode || do_poll) {
e96224ae
TI		 676 spin_lock_irq(&chip->reg_lock);
677 azx_update_rirb(chip);
678 spin_unlock_irq(&chip->reg_lock);
679 }
deadff16 680 if (!chip->rirb.cmds[addr]) {
2add9b92 681 smp_rmb();
b613291f 682 bus->rirb_error = 0;
1eb6dc7d
ML		 683
684 if (!do_poll)
685 chip->poll_count = 0;
deadff16 686 return chip->rirb.res[addr]; /* the last value */
2add9b92 687 }
28a0d9df
TI		 688 if (time_after(jiffies, timeout))
689 break;
33fa35ed 690 if (bus->needs_damn_long_delay)
52987656
TI		 691 msleep(2); /* temporary workaround */
692 else {
693 udelay(10);
694 cond_resched();
695 }
28a0d9df 696 }
5c79b1f8 697
1eb6dc7d
ML		 698 if (!chip->polling_mode && chip->poll_count < 2) {
699 snd_printdd(SFX "azx_get_response timeout, "
700 "polling the codec once: last cmd=0x%08x\n",
701 chip->last_cmd[addr]);
702 do_poll = 1;
703 chip->poll_count++;
704 goto again;
705 }
706
707
23c4a881
TI		 708 if (!chip->polling_mode) {
709 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
710 "switching to polling mode: last cmd=0x%08x\n",
711 chip->last_cmd[addr]);
712 chip->polling_mode = 1;
713 goto again;
714 }
715
68e7fffc 716 if (chip->msi) {
4abc1cc2 717 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 718 "disabling MSI: last cmd=0x%08x\n",
719 chip->last_cmd[addr]);
68e7fffc
TI		 720 free_irq(chip->irq, chip);
721 chip->irq = -1;
722 pci_disable_msi(chip->pci);
723 chip->msi = 0;
b613291f
TI		 724 if (azx_acquire_irq(chip, 1) < 0) {
725 bus->rirb_error = 1;
68e7fffc 726 return -1;
b613291f 727 }
68e7fffc
TI		 728 goto again;
729 }
730
6ce4a3bc
TI		 731 if (chip->probing) {
732 /* If this critical timeout happens during the codec probing
733 * phase, this is likely an access to a non-existing codec
734 * slot. Better to return an error and reset the system.
735 */
736 return -1;
737 }
738
8dd78330
TI		 739 /* a fatal communication error; need either to reset or to fallback
740 * to the single_cmd mode
741 */
b613291f 742 bus->rirb_error = 1;
b20f3b83 743 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 744 bus->response_reset = 1;
745 return -1; /* give a chance to retry */
746 }
747
748 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
749 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 750 chip->last_cmd[addr]);
8dd78330
TI		 751 chip->single_cmd = 1;
752 bus->response_reset = 0;
1a696978 753 /* release CORB/RIRB */
4fcd3920 754 azx_free_cmd_io(chip);
1a696978
TI		 755 /* disable unsolicited responses */
756 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 757 return -1;
1da177e4
LT		 758}
759
1da177e4
LT		 760/*
761 * Use the single immediate command instead of CORB/RIRB for simplicity
762 *
763 * Note: according to Intel, this is not preferred use. The command was
764 * intended for the BIOS only, and may get confused with unsolicited
765 * responses. So, we shouldn't use it for normal operation from the
766 * driver.
767 * I left the codes, however, for debugging/testing purposes.
768 */
769
b05a7d4f 770/* receive a response */
deadff16 771static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 772{
773 int timeout = 50;
774
775 while (timeout--) {
776 /* check IRV busy bit */
777 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
778 /* reuse rirb.res as the response return value */
deadff16 779 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 780 return 0;
781 }
782 udelay(1);
783 }
784 if (printk_ratelimit())
785 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
786 azx_readw(chip, IRS));
deadff16 787 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 788 return -EIO;
789}
790
1da177e4 791/* send a command */
33fa35ed 792static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 793{
33fa35ed 794 struct azx *chip = bus->private_data;
deadff16 795 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 796 int timeout = 50;
797
8dd78330 798 bus->rirb_error = 0;
1da177e4
LT		 799 while (timeout--) {
800 /* check ICB busy bit */
d01ce99f 801 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 802 /* Clear IRV valid bit */
d01ce99f
TI		 803 azx_writew(chip, IRS, azx_readw(chip, IRS) |
804 ICH6_IRS_VALID);
1da177e4 805 azx_writel(chip, IC, val);
d01ce99f
TI		 806 azx_writew(chip, IRS, azx_readw(chip, IRS) |
807 ICH6_IRS_BUSY);
deadff16 808 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 809 }
810 udelay(1);
811 }
1cfd52bc
MB		 812 if (printk_ratelimit())
813 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
814 azx_readw(chip, IRS), val);
1da177e4
LT		 815 return -EIO;
816}
817
818/* receive a response */
deadff16
WF		 819static unsigned int azx_single_get_response(struct hda_bus *bus,
820 unsigned int addr)
1da177e4 821{
33fa35ed 822 struct azx *chip = bus->private_data;
deadff16 823 return chip->rirb.res[addr];
1da177e4
LT		 824}
825
111d3af5
TI		 826/*
827 * The below are the main callbacks from hda_codec.
828 *
829 * They are just the skeleton to call sub-callbacks according to the
830 * current setting of chip->single_cmd.
831 */
832
833/* send a command */
33fa35ed 834static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 835{
33fa35ed 836 struct azx *chip = bus->private_data;
43bbb6cc 837
feb27340 838 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 839 if (chip->single_cmd)
33fa35ed 840 return azx_single_send_cmd(bus, val);
111d3af5 841 else
33fa35ed 842 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 843}
844
845/* get a response */
deadff16
WF		 846static unsigned int azx_get_response(struct hda_bus *bus,
847 unsigned int addr)
111d3af5 848{
33fa35ed 849 struct azx *chip = bus->private_data;
111d3af5 850 if (chip->single_cmd)
deadff16 851 return azx_single_get_response(bus, addr);
111d3af5 852 else
deadff16 853 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 854}
855
cb53c626 856#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 857static void azx_power_notify(struct hda_bus *bus);
cb53c626 858#endif
111d3af5 859
1da177e4 860/* reset codec link */
cd508fe5 861static int azx_reset(struct azx *chip, int full_reset)
1da177e4
LT		 862{
863 int count;
864
cd508fe5
JK		 865 if (!full_reset)
866 goto __skip;
867
e8a7f136
DT		 868 /* clear STATESTS */
869 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
870
1da177e4
LT		 871 /* reset controller */
872 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
873
874 count = 50;
875 while (azx_readb(chip, GCTL) && --count)
876 msleep(1);
877
878 /* delay for >= 100us for codec PLL to settle per spec
879 * Rev 0.9 section 5.5.1
880 */
881 msleep(1);
882
883 /* Bring controller out of reset */
884 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
885
886 count = 50;
927fc866 887 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 888 msleep(1);
889
927fc866 890 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 891 msleep(1);
892
cd508fe5 893 __skip:
1da177e4 894 /* check to see if controller is ready */
927fc866 895 if (!azx_readb(chip, GCTL)) {
4abc1cc2 896 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 897 return -EBUSY;
898 }
899
41e2fce4 900 /* Accept unsolicited responses */
1a696978
TI		 901 if (!chip->single_cmd)
902 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
903 ICH6_GCTL_UNSOL);
41e2fce4 904
1da177e4 905 /* detect codecs */
927fc866 906 if (!chip->codec_mask) {
1da177e4 907 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 908 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 909 }
910
911 return 0;
912}
913
914
915/*
916 * Lowlevel interface
917 */
918
919/* enable interrupts */
a98f90fd 920static void azx_int_enable(struct azx *chip)
1da177e4
LT		 921{
922 /* enable controller CIE and GIE */
923 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
924 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
925}
926
927/* disable interrupts */
a98f90fd 928static void azx_int_disable(struct azx *chip)
1da177e4
LT		 929{
930 int i;
931
932 /* disable interrupts in stream descriptor */
07e4ca50 933 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 934 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 935 azx_sd_writeb(azx_dev, SD_CTL,
936 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
937 }
938
939 /* disable SIE for all streams */
940 azx_writeb(chip, INTCTL, 0);
941
942 /* disable controller CIE and GIE */
943 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
944 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
945}
946
947/* clear interrupts */
a98f90fd 948static void azx_int_clear(struct azx *chip)
1da177e4
LT		 949{
950 int i;
951
952 /* clear stream status */
07e4ca50 953 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 954 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 955 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
956 }
957
958 /* clear STATESTS */
959 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
960
961 /* clear rirb status */
962 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
963
964 /* clear int status */
965 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
966}
967
968/* start a stream */
a98f90fd 969static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 970{
0e153474
JC		 971 /*
972 * Before stream start, initialize parameter
973 */
974 azx_dev->insufficient = 1;
975
1da177e4 976 /* enable SIE */
ccc5df05
WN		 977 azx_writel(chip, INTCTL,
978 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 979 /* set DMA start and interrupt mask */
980 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
981 SD_CTL_DMA_START | SD_INT_MASK);
982}
983
1dddab40
TI		 984/* stop DMA */
985static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 986{
1da177e4
LT		 987 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
988 ~(SD_CTL_DMA_START | SD_INT_MASK));
989 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 990}
991
992/* stop a stream */
993static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
994{
995 azx_stream_clear(chip, azx_dev);
1da177e4 996 /* disable SIE */
ccc5df05
WN		 997 azx_writel(chip, INTCTL,
998 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 999}
1000
1001
1002/*
cb53c626 1003 * reset and start the controller registers
1da177e4 1004 */
cd508fe5 1005static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1006{
cb53c626
TI		 1007 if (chip->initialized)
1008 return;
1da177e4
LT		 1009
1010 /* reset controller */
cd508fe5 1011 azx_reset(chip, full_reset);
1da177e4
LT		 1012
1013 /* initialize interrupts */
1014 azx_int_clear(chip);
1015 azx_int_enable(chip);
1016
1017 /* initialize the codec command I/O */
1a696978
TI		 1018 if (!chip->single_cmd)
1019 azx_init_cmd_io(chip);
1da177e4 1020
0be3b5d3
TI		 1021 /* program the position buffer */
1022 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1023 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1024
cb53c626
TI		 1025 chip->initialized = 1;
1026}
1027
1028/*
1029 * initialize the PCI registers
1030 */
1031/* update bits in a PCI register byte */
1032static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1033 unsigned char mask, unsigned char val)
1034{
1035 unsigned char data;
1036
1037 pci_read_config_byte(pci, reg, &data);
1038 data &= ~mask;
1039 data |= (val & mask);
1040 pci_write_config_byte(pci, reg, data);
1041}
1042
1043static void azx_init_pci(struct azx *chip)
1044{
90a5ad52
TI		 1045 unsigned short snoop;
1046
cb53c626
TI		 1047 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1048 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1049 * Ensuring these bits are 0 clears playback static on some HD Audio
1050 * codecs
1051 */
1052 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1053
da3fca21
V		 1054 switch (chip->driver_type) {
1055 case AZX_DRIVER_ATI:
1056 /* For ATI SB450 azalia HD audio, we need to enable snoop */
cb53c626
TI		 1057 update_pci_byte(chip->pci,
1058 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1059 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
da3fca21
V		 1060 break;
1061 case AZX_DRIVER_NVIDIA:
1062 /* For NVIDIA HDA, enable snoop */
cb53c626
TI		 1063 update_pci_byte(chip->pci,
1064 NVIDIA_HDA_TRANSREG_ADDR,
1065 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1066 update_pci_byte(chip->pci,
1067 NVIDIA_HDA_ISTRM_COH,
1068 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1069 update_pci_byte(chip->pci,
1070 NVIDIA_HDA_OSTRM_COH,
1071 0x01, NVIDIA_HDA_ENABLE_COHBIT);
da3fca21 1072 break;
90a5ad52 1073 case AZX_DRIVER_SCH:
32679f95 1074 case AZX_DRIVER_PCH:
90a5ad52
TI		 1075 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1076 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
4abc1cc2 1077 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
90a5ad52
TI		 1078 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1079 pci_read_config_word(chip->pci,
1080 INTEL_SCH_HDA_DEVC, &snoop);
4abc1cc2
TI		 1081 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1082 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
90a5ad52
TI		 1083 ? "Failed" : "OK");
1084 }
1085 break;
1086
da3fca21 1087 }
1da177e4
LT		 1088}
1089
1090
9ad593f6
TI		 1091static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1092
1da177e4
LT		 1093/*
1094 * interrupt handler
1095 */
7d12e780 1096static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1097{
a98f90fd
TI		 1098 struct azx *chip = dev_id;
1099 struct azx_dev *azx_dev;
1da177e4 1100 u32 status;
fa00e046 1101 int i, ok;
1da177e4
LT		 1102
1103 spin_lock(&chip->reg_lock);
1104
1105 status = azx_readl(chip, INTSTS);
1106 if (status == 0) {
1107 spin_unlock(&chip->reg_lock);
1108 return IRQ_NONE;
1109 }
1110
07e4ca50 1111 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1112 azx_dev = &chip->azx_dev[i];
1113 if (status & azx_dev->sd_int_sta_mask) {
1114 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ad593f6
TI		 1115 if (!azx_dev->substream || !azx_dev->running)
1116 continue;
1117 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1118 ok = azx_position_ok(chip, azx_dev);
1119 if (ok == 1) {
9ad593f6 1120 azx_dev->irq_pending = 0;
1da177e4
LT		 1121 spin_unlock(&chip->reg_lock);
1122 snd_pcm_period_elapsed(azx_dev->substream);
1123 spin_lock(&chip->reg_lock);
fa00e046 1124 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1125 /* bogus IRQ, process it later */
1126 azx_dev->irq_pending = 1;
6acaed38
TI		 1127 queue_work(chip->bus->workq,
1128 &chip->irq_pending_work);
1da177e4
LT		 1129 }
1130 }
1131 }
1132
1133 /* clear rirb int */
1134 status = azx_readb(chip, RIRBSTS);
1135 if (status & RIRB_INT_MASK) {
81740861 1136 if (status & RIRB_INT_RESPONSE)
1da177e4
LT		 1137 azx_update_rirb(chip);
1138 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1139 }
1140
1141#if 0
1142 /* clear state status int */
1143 if (azx_readb(chip, STATESTS) & 0x04)
1144 azx_writeb(chip, STATESTS, 0x04);
1145#endif
1146 spin_unlock(&chip->reg_lock);
1147
1148 return IRQ_HANDLED;
1149}
1150
1151
675f25d4
TI		 1152/*
1153 * set up a BDL entry
1154 */
1155static int setup_bdle(struct snd_pcm_substream *substream,
1156 struct azx_dev *azx_dev, u32 **bdlp,
1157 int ofs, int size, int with_ioc)
1158{
675f25d4
TI		 1159 u32 *bdl = *bdlp;
1160
1161 while (size > 0) {
1162 dma_addr_t addr;
1163 int chunk;
1164
1165 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1166 return -EINVAL;
1167
77a23f26 1168 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1169 /* program the address field of the BDL entry */
1170 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1171 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1172 /* program the size field of the BDL entry */
fc4abee8 1173 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
675f25d4
TI		 1174 bdl[2] = cpu_to_le32(chunk);
1175 /* program the IOC to enable interrupt
1176 * only when the whole fragment is processed
1177 */
1178 size -= chunk;
1179 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1180 bdl += 4;
1181 azx_dev->frags++;
1182 ofs += chunk;
1183 }
1184 *bdlp = bdl;
1185 return ofs;
1186}
1187
1da177e4
LT		 1188/*
1189 * set up BDL entries
1190 */
555e219f
TI		 1191static int azx_setup_periods(struct azx *chip,
1192 struct snd_pcm_substream *substream,
4ce107b9 1193 struct azx_dev *azx_dev)
1da177e4 1194{
4ce107b9
TI		 1195 u32 *bdl;
1196 int i, ofs, periods, period_bytes;
555e219f 1197 int pos_adj;
1da177e4
LT		 1198
1199 /* reset BDL address */
1200 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1201 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1202
97b71c94 1203 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1204 periods = azx_dev->bufsize / period_bytes;
1205
1da177e4 1206 /* program the initial BDL entries */
4ce107b9
TI		 1207 bdl = (u32 *)azx_dev->bdl.area;
1208 ofs = 0;
1209 azx_dev->frags = 0;
555e219f
TI		 1210 pos_adj = bdl_pos_adj[chip->dev_index];
1211 if (pos_adj > 0) {
675f25d4 1212 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1213 int pos_align = pos_adj;
555e219f 1214 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1215 if (!pos_adj)
e785d3d8
TI		 1216 pos_adj = pos_align;
1217 else
1218 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1219 pos_align;
675f25d4
TI		 1220 pos_adj = frames_to_bytes(runtime, pos_adj);
1221 if (pos_adj >= period_bytes) {
4abc1cc2 1222 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1223 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1224 pos_adj = 0;
1225 } else {
1226 ofs = setup_bdle(substream, azx_dev,
1227 &bdl, ofs, pos_adj, 1);
1228 if (ofs < 0)
1229 goto error;
4ce107b9 1230 }
555e219f
TI		 1231 } else
1232 pos_adj = 0;
675f25d4
TI		 1233 for (i = 0; i < periods; i++) {
1234 if (i == periods - 1 && pos_adj)
1235 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1236 period_bytes - pos_adj, 0);
1237 else
1238 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1239 period_bytes, 1);
1240 if (ofs < 0)
1241 goto error;
1da177e4 1242 }
4ce107b9 1243 return 0;
675f25d4
TI		 1244
1245 error:
4abc1cc2 1246 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1247 azx_dev->bufsize, period_bytes);
675f25d4 1248 return -EINVAL;
1da177e4
LT		 1249}
1250
1dddab40
TI		 1251/* reset stream */
1252static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1253{
1254 unsigned char val;
1255 int timeout;
1256
1dddab40
TI		 1257 azx_stream_clear(chip, azx_dev);
1258
d01ce99f
TI		 1259 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1260 SD_CTL_STREAM_RESET);
1da177e4
LT		 1261 udelay(3);
1262 timeout = 300;
1263 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1264 --timeout)
1265 ;
1266 val &= ~SD_CTL_STREAM_RESET;
1267 azx_sd_writeb(azx_dev, SD_CTL, val);
1268 udelay(3);
1269
1270 timeout = 300;
1271 /* waiting for hardware to report that the stream is out of reset */
1272 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1273 --timeout)
1274 ;
fa00e046
JK		 1275
1276 /* reset first position - may not be synced with hw at this time */
1277 *azx_dev->posbuf = 0;
1dddab40 1278}
1da177e4 1279
1dddab40
TI		 1280/*
1281 * set up the SD for streaming
1282 */
1283static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1284{
1285 /* make sure the run bit is zero for SD */
1286 azx_stream_clear(chip, azx_dev);
1da177e4
LT		 1287 /* program the stream_tag */
1288 azx_sd_writel(azx_dev, SD_CTL,
d01ce99f 1289 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1da177e4
LT		 1290 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1291
1292 /* program the length of samples in cyclic buffer */
1293 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1294
1295 /* program the stream format */
1296 /* this value needs to be the same as the one programmed */
1297 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1298
1299 /* program the stream LVI (last valid index) of the BDL */
1300 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1301
1302 /* program the BDL address */
1303 /* lower BDL address */
4ce107b9 1304 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1305 /* upper BDL address */
766979e0 1306 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1307
0be3b5d3 1308 /* enable the position buffer */
beaffc39
SG		 1309 if (chip->position_fix[0] == POS_FIX_POSBUF ||
1310 chip->position_fix[0] == POS_FIX_AUTO ||
1311 chip->position_fix[1] == POS_FIX_POSBUF ||
1312 chip->position_fix[1] == POS_FIX_AUTO ||
0e153474 1313 chip->via_dmapos_patch) {
ee9d6b9a
TI		 1314 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1315 azx_writel(chip, DPLBASE,
1316 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1317 }
c74db86b 1318
1da177e4 1319 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1320 azx_sd_writel(azx_dev, SD_CTL,
1321 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1322
1323 return 0;
1324}
1325
6ce4a3bc
TI		 1326/*
1327 * Probe the given codec address
1328 */
1329static int probe_codec(struct azx *chip, int addr)
1330{
1331 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1332 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1333 unsigned int res;
1334
a678cdee 1335 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1336 chip->probing = 1;
1337 azx_send_cmd(chip->bus, cmd);
deadff16 1338 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1339 chip->probing = 0;
a678cdee 1340 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1341 if (res == -1)
1342 return -EIO;
4abc1cc2 1343 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1344 return 0;
1345}
1346
33fa35ed
TI		 1347static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1348 struct hda_pcm *cpcm);
6ce4a3bc 1349static void azx_stop_chip(struct azx *chip);
1da177e4 1350
8dd78330
TI		 1351static void azx_bus_reset(struct hda_bus *bus)
1352{
1353 struct azx *chip = bus->private_data;
8dd78330
TI		 1354
1355 bus->in_reset = 1;
1356 azx_stop_chip(chip);
cd508fe5 1357 azx_init_chip(chip, 1);
65f75983 1358#ifdef CONFIG_PM
8dd78330 1359 if (chip->initialized) {
65f75983
AB		 1360 int i;
1361
c8936222 1362 for (i = 0; i < HDA_MAX_PCMS; i++)
8dd78330
TI		 1363 snd_pcm_suspend_all(chip->pcm[i]);
1364 snd_hda_suspend(chip->bus);
1365 snd_hda_resume(chip->bus);
1366 }
65f75983 1367#endif
8dd78330
TI		 1368 bus->in_reset = 0;
1369}
1370
1da177e4
LT		 1371/*
1372 * Codec initialization
1373 */
1374
2f5983f2
TI		 1375/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1376static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
7445dfc1 1377 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1378 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1379};
1380
a1e21c90 1381static int __devinit azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1382{
1383 struct hda_bus_template bus_temp;
34c25350
TI		 1384 int c, codecs, err;
1385 int max_slots;
1da177e4
LT		 1386
1387 memset(&bus_temp, 0, sizeof(bus_temp));
1388 bus_temp.private_data = chip;
1389 bus_temp.modelname = model;
1390 bus_temp.pci = chip->pci;
111d3af5
TI		 1391 bus_temp.ops.command = azx_send_cmd;
1392 bus_temp.ops.get_response = azx_get_response;
176d5335 1393 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1394 bus_temp.ops.bus_reset = azx_bus_reset;
cb53c626 1395#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1396 bus_temp.power_save = &power_save;
cb53c626
TI		 1397 bus_temp.ops.pm_notify = azx_power_notify;
1398#endif
1da177e4 1399
d01ce99f
TI		 1400 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1401 if (err < 0)
1da177e4
LT		 1402 return err;
1403
dc9c8e21
WN		 1404 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1405 chip->bus->needs_damn_long_delay = 1;
1406
34c25350 1407 codecs = 0;
2f5983f2
TI		 1408 max_slots = azx_max_codecs[chip->driver_type];
1409 if (!max_slots)
7445dfc1 1410 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1411
1412 /* First try to probe all given codec slots */
1413 for (c = 0; c < max_slots; c++) {
f1eaaeec 1414 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1415 if (probe_codec(chip, c) < 0) {
1416 /* Some BIOSen give you wrong codec addresses
1417 * that don't exist
1418 */
4abc1cc2
TI		 1419 snd_printk(KERN_WARNING SFX
1420 "Codec #%d probe error; "
6ce4a3bc
TI		 1421 "disabling it...\n", c);
1422 chip->codec_mask &= ~(1 << c);
1423 /* More badly, accessing to a non-existing
1424 * codec often screws up the controller chip,
2448158e 1425 * and disturbs the further communications.
6ce4a3bc
TI		 1426 * Thus if an error occurs during probing,
1427 * better to reset the controller chip to
1428 * get back to the sanity state.
1429 */
1430 azx_stop_chip(chip);
cd508fe5 1431 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1432 }
1433 }
1434 }
1435
1436 /* Then create codec instances */
34c25350 1437 for (c = 0; c < max_slots; c++) {
f1eaaeec 1438 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1439 struct hda_codec *codec;
a1e21c90 1440 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1441 if (err < 0)
1442 continue;
2dca0bba 1443 codec->beep_mode = chip->beep_mode;
1da177e4 1444 codecs++;
19a982b6
TI		 1445 }
1446 }
1447 if (!codecs) {
1da177e4
LT		 1448 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1449 return -ENXIO;
1450 }
a1e21c90
TI		 1451 return 0;
1452}
1da177e4 1453
a1e21c90
TI		 1454/* configure each codec instance */
1455static int __devinit azx_codec_configure(struct azx *chip)
1456{
1457 struct hda_codec *codec;
1458 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1459 snd_hda_codec_configure(codec);
1460 }
1da177e4
LT		 1461 return 0;
1462}
1463
1464
1465/*
1466 * PCM support
1467 */
1468
1469/* assign a stream for the PCM */
ef18bede
WF		 1470static inline struct azx_dev *
1471azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1472{
07e4ca50 1473 int dev, i, nums;
ef18bede
WF		 1474 struct azx_dev *res = NULL;
1475
1476 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1477 dev = chip->playback_index_offset;
1478 nums = chip->playback_streams;
1479 } else {
1480 dev = chip->capture_index_offset;
1481 nums = chip->capture_streams;
1482 }
1483 for (i = 0; i < nums; i++, dev++)
d01ce99f 1484 if (!chip->azx_dev[dev].opened) {
ef18bede
WF		 1485 res = &chip->azx_dev[dev];
1486 if (res->device == substream->pcm->device)
1487 break;
1da177e4 1488 }
ef18bede
WF		 1489 if (res) {
1490 res->opened = 1;
1491 res->device = substream->pcm->device;
1492 }
1493 return res;
1da177e4
LT		 1494}
1495
1496/* release the assigned stream */
a98f90fd 1497static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1498{
1499 azx_dev->opened = 0;
1500}
1501
a98f90fd 1502static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1503 .info = (SNDRV_PCM_INFO_MMAP |
1504 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1505 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1506 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1507 /* No full-resume yet implemented */
1508 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52
TI		 1509 SNDRV_PCM_INFO_PAUSE |
1510 SNDRV_PCM_INFO_SYNC_START),
1da177e4
LT		 1511 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1512 .rates = SNDRV_PCM_RATE_48000,
1513 .rate_min = 48000,
1514 .rate_max = 48000,
1515 .channels_min = 2,
1516 .channels_max = 2,
1517 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1518 .period_bytes_min = 128,
1519 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1520 .periods_min = 2,
1521 .periods_max = AZX_MAX_FRAG,
1522 .fifo_size = 0,
1523};
1524
1525struct azx_pcm {
a98f90fd 1526 struct azx *chip;
1da177e4
LT		 1527 struct hda_codec *codec;
1528 struct hda_pcm_stream *hinfo[2];
1529};
1530
a98f90fd 1531static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1532{
1533 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1534 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1535 struct azx *chip = apcm->chip;
1536 struct azx_dev *azx_dev;
1537 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1538 unsigned long flags;
1539 int err;
1540
62932df8 1541 mutex_lock(&chip->open_mutex);
ef18bede 1542 azx_dev = azx_assign_device(chip, substream);
1da177e4 1543 if (azx_dev == NULL) {
62932df8 1544 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1545 return -EBUSY;
1546 }
1547 runtime->hw = azx_pcm_hw;
1548 runtime->hw.channels_min = hinfo->channels_min;
1549 runtime->hw.channels_max = hinfo->channels_max;
1550 runtime->hw.formats = hinfo->formats;
1551 runtime->hw.rates = hinfo->rates;
1552 snd_pcm_limit_hw_rates(runtime);
1553 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5f1545bc
JD		 1554 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1555 128);
1556 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1557 128);
cb53c626 1558 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1559 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1560 if (err < 0) {
1da177e4 1561 azx_release_device(azx_dev);
cb53c626 1562 snd_hda_power_down(apcm->codec);
62932df8 1563 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1564 return err;
1565 }
70d321e6 1566 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1567 /* sanity check */
1568 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1569 snd_BUG_ON(!runtime->hw.channels_max) ||
1570 snd_BUG_ON(!runtime->hw.formats) ||
1571 snd_BUG_ON(!runtime->hw.rates)) {
1572 azx_release_device(azx_dev);
1573 hinfo->ops.close(hinfo, apcm->codec, substream);
1574 snd_hda_power_down(apcm->codec);
1575 mutex_unlock(&chip->open_mutex);
1576 return -EINVAL;
1577 }
1da177e4
LT		 1578 spin_lock_irqsave(&chip->reg_lock, flags);
1579 azx_dev->substream = substream;
1580 azx_dev->running = 0;
1581 spin_unlock_irqrestore(&chip->reg_lock, flags);
1582
1583 runtime->private_data = azx_dev;
850f0e52 1584 snd_pcm_set_sync(substream);
62932df8 1585 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1586 return 0;
1587}
1588
a98f90fd 1589static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1590{
1591 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1592 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1593 struct azx *chip = apcm->chip;
1594 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1595 unsigned long flags;
1596
62932df8 1597 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1598 spin_lock_irqsave(&chip->reg_lock, flags);
1599 azx_dev->substream = NULL;
1600 azx_dev->running = 0;
1601 spin_unlock_irqrestore(&chip->reg_lock, flags);
1602 azx_release_device(azx_dev);
1603 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1604 snd_hda_power_down(apcm->codec);
62932df8 1605 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1606 return 0;
1607}
1608
d01ce99f
TI		 1609static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1610 struct snd_pcm_hw_params *hw_params)
1da177e4 1611{
97b71c94
TI		 1612 struct azx_dev *azx_dev = get_azx_dev(substream);
1613
1614 azx_dev->bufsize = 0;
1615 azx_dev->period_bytes = 0;
1616 azx_dev->format_val = 0;
d01ce99f
TI		 1617 return snd_pcm_lib_malloc_pages(substream,
1618 params_buffer_bytes(hw_params));
1da177e4
LT		 1619}
1620
a98f90fd 1621static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1622{
1623 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1624 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1625 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1626
1627 /* reset BDL address */
1628 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1629 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1630 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1631 azx_dev->bufsize = 0;
1632 azx_dev->period_bytes = 0;
1633 azx_dev->format_val = 0;
1da177e4
LT		 1634
1635 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1636
1637 return snd_pcm_lib_free_pages(substream);
1638}
1639
a98f90fd 1640static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1641{
1642 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1643 struct azx *chip = apcm->chip;
1644 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1645 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1646 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94
TI		 1647 unsigned int bufsize, period_bytes, format_val;
1648 int err;
1da177e4 1649
fa00e046 1650 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1651 format_val = snd_hda_calc_stream_format(runtime->rate,
1652 runtime->channels,
1653 runtime->format,
1654 hinfo->maxbps);
1655 if (!format_val) {
d01ce99f
TI		 1656 snd_printk(KERN_ERR SFX
1657 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1658 runtime->rate, runtime->channels, runtime->format);
1659 return -EINVAL;
1660 }
1661
97b71c94
TI		 1662 bufsize = snd_pcm_lib_buffer_bytes(substream);
1663 period_bytes = snd_pcm_lib_period_bytes(substream);
1664
4abc1cc2 1665 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1666 bufsize, format_val);
1667
1668 if (bufsize != azx_dev->bufsize ||
1669 period_bytes != azx_dev->period_bytes ||
1670 format_val != azx_dev->format_val) {
1671 azx_dev->bufsize = bufsize;
1672 azx_dev->period_bytes = period_bytes;
1673 azx_dev->format_val = format_val;
1674 err = azx_setup_periods(chip, substream, azx_dev);
1675 if (err < 0)
1676 return err;
1677 }
1678
fa00e046
JK		 1679 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1680 (runtime->rate * 2);
1da177e4
LT		 1681 azx_setup_controller(chip, azx_dev);
1682 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1683 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1684 else
1685 azx_dev->fifo_size = 0;
1686
1687 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1688 azx_dev->format_val, substream);
1689}
1690
a98f90fd 1691static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1692{
1693 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1694 struct azx *chip = apcm->chip;
850f0e52
TI		 1695 struct azx_dev *azx_dev;
1696 struct snd_pcm_substream *s;
fa00e046 1697 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1698 int nwait, timeout;
1da177e4 1699
1da177e4 1700 switch (cmd) {
fa00e046
JK		 1701 case SNDRV_PCM_TRIGGER_START:
1702 rstart = 1;
1da177e4
LT		 1703 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1704 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1705 start = 1;
1da177e4
LT		 1706 break;
1707 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1708 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1709 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1710 start = 0;
1da177e4
LT		 1711 break;
1712 default:
850f0e52
TI		 1713 return -EINVAL;
1714 }
1715
1716 snd_pcm_group_for_each_entry(s, substream) {
1717 if (s->pcm->card != substream->pcm->card)
1718 continue;
1719 azx_dev = get_azx_dev(s);
1720 sbits |= 1 << azx_dev->index;
1721 nsync++;
1722 snd_pcm_trigger_done(s, substream);
1723 }
1724
1725 spin_lock(&chip->reg_lock);
1726 if (nsync > 1) {
1727 /* first, set SYNC bits of corresponding streams */
1728 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1729 }
1730 snd_pcm_group_for_each_entry(s, substream) {
1731 if (s->pcm->card != substream->pcm->card)
1732 continue;
1733 azx_dev = get_azx_dev(s);
fa00e046
JK		 1734 if (rstart) {
1735 azx_dev->start_flag = 1;
1736 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1737 }
850f0e52
TI		 1738 if (start)
1739 azx_stream_start(chip, azx_dev);
1740 else
1741 azx_stream_stop(chip, azx_dev);
1742 azx_dev->running = start;
1da177e4
LT		 1743 }
1744 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1745 if (start) {
1746 if (nsync == 1)
1747 return 0;
1748 /* wait until all FIFOs get ready */
1749 for (timeout = 5000; timeout; timeout--) {
1750 nwait = 0;
1751 snd_pcm_group_for_each_entry(s, substream) {
1752 if (s->pcm->card != substream->pcm->card)
1753 continue;
1754 azx_dev = get_azx_dev(s);
1755 if (!(azx_sd_readb(azx_dev, SD_STS) &
1756 SD_STS_FIFO_READY))
1757 nwait++;
1758 }
1759 if (!nwait)
1760 break;
1761 cpu_relax();
1762 }
1763 } else {
1764 /* wait until all RUN bits are cleared */
1765 for (timeout = 5000; timeout; timeout--) {
1766 nwait = 0;
1767 snd_pcm_group_for_each_entry(s, substream) {
1768 if (s->pcm->card != substream->pcm->card)
1769 continue;
1770 azx_dev = get_azx_dev(s);
1771 if (azx_sd_readb(azx_dev, SD_CTL) &
1772 SD_CTL_DMA_START)
1773 nwait++;
1774 }
1775 if (!nwait)
1776 break;
1777 cpu_relax();
1778 }
1da177e4 1779 }
850f0e52
TI		 1780 if (nsync > 1) {
1781 spin_lock(&chip->reg_lock);
1782 /* reset SYNC bits */
1783 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1784 spin_unlock(&chip->reg_lock);
1785 }
1786 return 0;
1da177e4
LT		 1787}
1788
0e153474
JC		 1789/* get the current DMA position with correction on VIA chips */
1790static unsigned int azx_via_get_position(struct azx *chip,
1791 struct azx_dev *azx_dev)
1792{
1793 unsigned int link_pos, mini_pos, bound_pos;
1794 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1795 unsigned int fifo_size;
1796
1797 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1798 if (azx_dev->index >= 4) {
1799 /* Playback, no problem using link position */
1800 return link_pos;
1801 }
1802
1803 /* Capture */
1804 /* For new chipset,
1805 * use mod to get the DMA position just like old chipset
1806 */
1807 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1808 mod_dma_pos %= azx_dev->period_bytes;
1809
1810 /* azx_dev->fifo_size can't get FIFO size of in stream.
1811 * Get from base address + offset.
1812 */
1813 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1814
1815 if (azx_dev->insufficient) {
1816 /* Link position never gather than FIFO size */
1817 if (link_pos <= fifo_size)
1818 return 0;
1819
1820 azx_dev->insufficient = 0;
1821 }
1822
1823 if (link_pos <= fifo_size)
1824 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1825 else
1826 mini_pos = link_pos - fifo_size;
1827
1828 /* Find nearest previous boudary */
1829 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1830 mod_link_pos = link_pos % azx_dev->period_bytes;
1831 if (mod_link_pos >= fifo_size)
1832 bound_pos = link_pos - mod_link_pos;
1833 else if (mod_dma_pos >= mod_mini_pos)
1834 bound_pos = mini_pos - mod_mini_pos;
1835 else {
1836 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1837 if (bound_pos >= azx_dev->bufsize)
1838 bound_pos = 0;
1839 }
1840
1841 /* Calculate real DMA position we want */
1842 return bound_pos + mod_dma_pos;
1843}
1844
9ad593f6
TI		 1845static unsigned int azx_get_position(struct azx *chip,
1846 struct azx_dev *azx_dev)
1da177e4 1847{
1da177e4
LT		 1848 unsigned int pos;
1849
0e153474
JC		 1850 if (chip->via_dmapos_patch)
1851 pos = azx_via_get_position(chip, azx_dev);
beaffc39
SG		 1852 else {
1853 int stream = azx_dev->substream->stream;
1854 if (chip->position_fix[stream] == POS_FIX_POSBUF ||
1855 chip->position_fix[stream] == POS_FIX_AUTO) {
1856 /* use the position buffer */
1857 pos = le32_to_cpu(*azx_dev->posbuf);
1858 } else {
1859 /* read LPIB */
1860 pos = azx_sd_readl(azx_dev, SD_LPIB);
1861 }
c74db86b 1862 }
1da177e4
LT		 1863 if (pos >= azx_dev->bufsize)
1864 pos = 0;
9ad593f6
TI		 1865 return pos;
1866}
1867
1868static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1869{
1870 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1871 struct azx *chip = apcm->chip;
1872 struct azx_dev *azx_dev = get_azx_dev(substream);
1873 return bytes_to_frames(substream->runtime,
1874 azx_get_position(chip, azx_dev));
1875}
1876
1877/*
1878 * Check whether the current DMA position is acceptable for updating
1879 * periods. Returns non-zero if it's OK.
1880 *
1881 * Many HD-audio controllers appear pretty inaccurate about
1882 * the update-IRQ timing. The IRQ is issued before actually the
1883 * data is processed. So, we need to process it afterwords in a
1884 * workqueue.
1885 */
1886static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1887{
1888 unsigned int pos;
beaffc39 1889 int stream;
9ad593f6 1890
fa00e046
JK		 1891 if (azx_dev->start_flag &&
1892 time_before_eq(jiffies, azx_dev->start_jiffies))
1893 return -1; /* bogus (too early) interrupt */
1894 azx_dev->start_flag = 0;
1895
beaffc39 1896 stream = azx_dev->substream->stream;
9ad593f6 1897 pos = azx_get_position(chip, azx_dev);
beaffc39 1898 if (chip->position_fix[stream] == POS_FIX_AUTO) {
9ad593f6
TI		 1899 if (!pos) {
1900 printk(KERN_WARNING
1901 "hda-intel: Invalid position buffer, "
1902 "using LPIB read method instead.\n");
beaffc39 1903 chip->position_fix[stream] = POS_FIX_LPIB;
9ad593f6
TI		 1904 pos = azx_get_position(chip, azx_dev);
1905 } else
beaffc39 1906 chip->position_fix[stream] = POS_FIX_POSBUF;
9ad593f6
TI		 1907 }
1908
a62741cf
TI		 1909 if (!bdl_pos_adj[chip->dev_index])
1910 return 1; /* no delayed ack */
d6d8bf54
TI		 1911 if (WARN_ONCE(!azx_dev->period_bytes,
1912 "hda-intel: zero azx_dev->period_bytes"))
1913 return 0; /* this shouldn't happen! */
9ad593f6
TI		 1914 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1915 return 0; /* NG - it's below the period boundary */
1916 return 1; /* OK, it's fine */
1917}
1918
1919/*
1920 * The work for pending PCM period updates.
1921 */
1922static void azx_irq_pending_work(struct work_struct *work)
1923{
1924 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1925 int i, pending;
1926
a6a950a8
TI		 1927 if (!chip->irq_pending_warned) {
1928 printk(KERN_WARNING
1929 "hda-intel: IRQ timing workaround is activated "
1930 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1931 chip->card->number);
1932 chip->irq_pending_warned = 1;
1933 }
1934
9ad593f6
TI		 1935 for (;;) {
1936 pending = 0;
1937 spin_lock_irq(&chip->reg_lock);
1938 for (i = 0; i < chip->num_streams; i++) {
1939 struct azx_dev *azx_dev = &chip->azx_dev[i];
1940 if (!azx_dev->irq_pending ||
1941 !azx_dev->substream ||
1942 !azx_dev->running)
1943 continue;
1944 if (azx_position_ok(chip, azx_dev)) {
1945 azx_dev->irq_pending = 0;
1946 spin_unlock(&chip->reg_lock);
1947 snd_pcm_period_elapsed(azx_dev->substream);
1948 spin_lock(&chip->reg_lock);
1949 } else
1950 pending++;
1951 }
1952 spin_unlock_irq(&chip->reg_lock);
1953 if (!pending)
1954 return;
1955 cond_resched();
1956 }
1957}
1958
1959/* clear irq_pending flags and assure no on-going workq */
1960static void azx_clear_irq_pending(struct azx *chip)
1961{
1962 int i;
1963
1964 spin_lock_irq(&chip->reg_lock);
1965 for (i = 0; i < chip->num_streams; i++)
1966 chip->azx_dev[i].irq_pending = 0;
1967 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1968}
1969
a98f90fd 1970static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 1971 .open = azx_pcm_open,
1972 .close = azx_pcm_close,
1973 .ioctl = snd_pcm_lib_ioctl,
1974 .hw_params = azx_pcm_hw_params,
1975 .hw_free = azx_pcm_hw_free,
1976 .prepare = azx_pcm_prepare,
1977 .trigger = azx_pcm_trigger,
1978 .pointer = azx_pcm_pointer,
4ce107b9 1979 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 1980};
1981
a98f90fd 1982static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 1983{
176d5335
TI		 1984 struct azx_pcm *apcm = pcm->private_data;
1985 if (apcm) {
1986 apcm->chip->pcm[pcm->device] = NULL;
1987 kfree(apcm);
1988 }
1da177e4
LT		 1989}
1990
176d5335 1991static int
33fa35ed
TI		 1992azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1993 struct hda_pcm *cpcm)
1da177e4 1994{
33fa35ed 1995 struct azx *chip = bus->private_data;
a98f90fd 1996 struct snd_pcm *pcm;
1da177e4 1997 struct azx_pcm *apcm;
176d5335
TI		 1998 int pcm_dev = cpcm->device;
1999 int s, err;
1da177e4 2000
c8936222 2001 if (pcm_dev >= HDA_MAX_PCMS) {
176d5335
TI		 2002 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2003 pcm_dev);
da3cec35 2004 return -EINVAL;
176d5335
TI		 2005 }
2006 if (chip->pcm[pcm_dev]) {
2007 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2008 return -EBUSY;
2009 }
2010 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2011 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2012 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2013 &pcm);
2014 if (err < 0)
2015 return err;
18cb7109 2016 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2017 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2018 if (apcm == NULL)
2019 return -ENOMEM;
2020 apcm->chip = chip;
2021 apcm->codec = codec;
1da177e4
LT		 2022 pcm->private_data = apcm;
2023 pcm->private_free = azx_pcm_free;
176d5335
TI		 2024 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2025 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2026 chip->pcm[pcm_dev] = pcm;
2027 cpcm->pcm = pcm;
2028 for (s = 0; s < 2; s++) {
2029 apcm->hinfo[s] = &cpcm->stream[s];
2030 if (cpcm->stream[s].substreams)
2031 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2032 }
2033 /* buffer pre-allocation */
4ce107b9 2034 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2035 snd_dma_pci_data(chip->pci),
fc4abee8 2036 1024 * 64, 32 * 1024 * 1024);
1da177e4
LT		 2037 return 0;
2038}
2039
2040/*
2041 * mixer creation - all stuff is implemented in hda module
2042 */
a98f90fd 2043static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2044{
2045 return snd_hda_build_controls(chip->bus);
2046}
2047
2048
2049/*
2050 * initialize SD streams
2051 */
a98f90fd 2052static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2053{
2054 int i;
2055
2056 /* initialize each stream (aka device)
d01ce99f
TI		 2057 * assign the starting bdl address to each stream (device)
2058 * and initialize
1da177e4 2059 */
07e4ca50 2060 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2061 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2062 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2063 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2064 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2065 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2066 azx_dev->sd_int_sta_mask = 1 << i;
2067 /* stream tag: must be non-zero and unique */
2068 azx_dev->index = i;
2069 azx_dev->stream_tag = i + 1;
2070 }
2071
2072 return 0;
2073}
2074
68e7fffc
TI		 2075static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2076{
437a5a46
TI		 2077 if (request_irq(chip->pci->irq, azx_interrupt,
2078 chip->msi ? 0 : IRQF_SHARED,
9492837a 2079 "hda_intel", chip)) {
68e7fffc
TI		 2080 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2081 "disabling device\n", chip->pci->irq);
2082 if (do_disconnect)
2083 snd_card_disconnect(chip->card);
2084 return -1;
2085 }
2086 chip->irq = chip->pci->irq;
69e13418 2087 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2088 return 0;
2089}
2090
1da177e4 2091
cb53c626
TI		 2092static void azx_stop_chip(struct azx *chip)
2093{
95e99fda 2094 if (!chip->initialized)
cb53c626
TI		 2095 return;
2096
2097 /* disable interrupts */
2098 azx_int_disable(chip);
2099 azx_int_clear(chip);
2100
2101 /* disable CORB/RIRB */
2102 azx_free_cmd_io(chip);
2103
2104 /* disable position buffer */
2105 azx_writel(chip, DPLBASE, 0);
2106 azx_writel(chip, DPUBASE, 0);
2107
2108 chip->initialized = 0;
2109}
2110
2111#ifdef CONFIG_SND_HDA_POWER_SAVE
2112/* power-up/down the controller */
33fa35ed 2113static void azx_power_notify(struct hda_bus *bus)
cb53c626 2114{
33fa35ed 2115 struct azx *chip = bus->private_data;
cb53c626
TI		 2116 struct hda_codec *c;
2117 int power_on = 0;
2118
33fa35ed 2119 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 2120 if (c->power_on) {
2121 power_on = 1;
2122 break;
2123 }
2124 }
2125 if (power_on)
cd508fe5 2126 azx_init_chip(chip, 1);
0287d970
WF		 2127 else if (chip->running && power_save_controller &&
2128 !bus->power_keep_link_on)
cb53c626 2129 azx_stop_chip(chip);
cb53c626 2130}
5c0b9bec
TI		 2131#endif /* CONFIG_SND_HDA_POWER_SAVE */
2132
2133#ifdef CONFIG_PM
2134/*
2135 * power management
2136 */
986862bd
TI		 2137
2138static int snd_hda_codecs_inuse(struct hda_bus *bus)
2139{
2140 struct hda_codec *codec;
2141
2142 list_for_each_entry(codec, &bus->codec_list, list) {
2143 if (snd_hda_codec_needs_resume(codec))
2144 return 1;
2145 }
2146 return 0;
2147}
cb53c626 2148
421a1252 2149static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2150{
421a1252
TI		 2151 struct snd_card *card = pci_get_drvdata(pci);
2152 struct azx *chip = card->private_data;
1da177e4
LT		 2153 int i;
2154
421a1252 2155 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2156 azx_clear_irq_pending(chip);
c8936222 2157 for (i = 0; i < HDA_MAX_PCMS; i++)
421a1252 2158 snd_pcm_suspend_all(chip->pcm[i]);
0b7a2e9c 2159 if (chip->initialized)
8dd78330 2160 snd_hda_suspend(chip->bus);
cb53c626 2161 azx_stop_chip(chip);
30b35399 2162 if (chip->irq >= 0) {
43001c95 2163 free_irq(chip->irq, chip);
30b35399
TI		 2164 chip->irq = -1;
2165 }
68e7fffc 2166 if (chip->msi)
43001c95 2167 pci_disable_msi(chip->pci);
421a1252
TI		 2168 pci_disable_device(pci);
2169 pci_save_state(pci);
30b35399 2170 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 2171 return 0;
2172}
2173
421a1252 2174static int azx_resume(struct pci_dev *pci)
1da177e4 2175{
421a1252
TI		 2176 struct snd_card *card = pci_get_drvdata(pci);
2177 struct azx *chip = card->private_data;
1da177e4 2178
d14a7e0b
TI		 2179 pci_set_power_state(pci, PCI_D0);
2180 pci_restore_state(pci);
30b35399
TI		 2181 if (pci_enable_device(pci) < 0) {
2182 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2183 "disabling device\n");
2184 snd_card_disconnect(card);
2185 return -EIO;
2186 }
2187 pci_set_master(pci);
68e7fffc
TI		 2188 if (chip->msi)
2189 if (pci_enable_msi(pci) < 0)
2190 chip->msi = 0;
2191 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2192 return -EIO;
cb53c626 2193 azx_init_pci(chip);
d804ad92
ML		 2194
2195 if (snd_hda_codecs_inuse(chip->bus))
cd508fe5 2196 azx_init_chip(chip, 1);
d804ad92 2197
1da177e4 2198 snd_hda_resume(chip->bus);
421a1252 2199 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2200 return 0;
2201}
2202#endif /* CONFIG_PM */
2203
2204
0cbf0098
TI		 2205/*
2206 * reboot notifier for hang-up problem at power-down
2207 */
2208static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2209{
2210 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2211 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2212 azx_stop_chip(chip);
2213 return NOTIFY_OK;
2214}
2215
2216static void azx_notifier_register(struct azx *chip)
2217{
2218 chip->reboot_notifier.notifier_call = azx_halt;
2219 register_reboot_notifier(&chip->reboot_notifier);
2220}
2221
2222static void azx_notifier_unregister(struct azx *chip)
2223{
2224 if (chip->reboot_notifier.notifier_call)
2225 unregister_reboot_notifier(&chip->reboot_notifier);
2226}
2227
1da177e4
LT		 2228/*
2229 * destructor
2230 */
a98f90fd 2231static int azx_free(struct azx *chip)
1da177e4 2232{
4ce107b9
TI		 2233 int i;
2234
0cbf0098
TI		 2235 azx_notifier_unregister(chip);
2236
ce43fbae 2237 if (chip->initialized) {
9ad593f6 2238 azx_clear_irq_pending(chip);
07e4ca50 2239 for (i = 0; i < chip->num_streams; i++)
1da177e4 2240 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2241 azx_stop_chip(chip);
1da177e4
LT		 2242 }
2243
f000fd80 2244 if (chip->irq >= 0)
1da177e4 2245 free_irq(chip->irq, (void*)chip);
68e7fffc 2246 if (chip->msi)
30b35399 2247 pci_disable_msi(chip->pci);
f079c25a
TI		 2248 if (chip->remap_addr)
2249 iounmap(chip->remap_addr);
1da177e4 2250
4ce107b9
TI		 2251 if (chip->azx_dev) {
2252 for (i = 0; i < chip->num_streams; i++)
2253 if (chip->azx_dev[i].bdl.area)
2254 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2255 }
1da177e4
LT		 2256 if (chip->rb.area)
2257 snd_dma_free_pages(&chip->rb);
1da177e4
LT		 2258 if (chip->posbuf.area)
2259 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT		 2260 pci_release_regions(chip->pci);
2261 pci_disable_device(chip->pci);
07e4ca50 2262 kfree(chip->azx_dev);
1da177e4
LT		 2263 kfree(chip);
2264
2265 return 0;
2266}
2267
a98f90fd 2268static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2269{
2270 return azx_free(device->device_data);
2271}
2272
3372a153
TI		 2273/*
2274 * white/black-listing for position_fix
2275 */
623ec047 2276static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2277 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2278 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
9919c761 2279 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
2f703e7a 2280 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
0708cc58 2281 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
d2e1c973 2282 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
9ec8ddad 2283 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2284 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
0321b695 2285 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
8815cd03 2286 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
0e0280dc 2287 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
572c0e3c 2288 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
3372a153
TI		 2289 {}
2290};
2291
2292static int __devinit check_position_fix(struct azx *chip, int fix)
2293{
2294 const struct snd_pci_quirk *q;
2295
c673ba1c
TI		 2296 switch (fix) {
2297 case POS_FIX_LPIB:
2298 case POS_FIX_POSBUF:
2299 return fix;
2300 }
2301
2302 /* Check VIA/ATI HD Audio Controller exist */
2303 switch (chip->driver_type) {
2304 case AZX_DRIVER_VIA:
2305 case AZX_DRIVER_ATI:
0e153474
JC		 2306 chip->via_dmapos_patch = 1;
2307 /* Use link position directly, avoid any transfer problem. */
2308 return POS_FIX_LPIB;
2309 }
2310 chip->via_dmapos_patch = 0;
2311
c673ba1c
TI		 2312 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2313 if (q) {
2314 printk(KERN_INFO
2315 "hda_intel: position_fix set to %d "
2316 "for device %04x:%04x\n",
2317 q->value, q->subvendor, q->subdevice);
2318 return q->value;
3372a153 2319 }
c673ba1c 2320 return POS_FIX_AUTO;
3372a153
TI		 2321}
2322
669ba27a
TI		 2323/*
2324 * black-lists for probe_mask
2325 */
2326static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2327 /* Thinkpad often breaks the controller communication when accessing
2328 * to the non-working (or non-existing) modem codec slot.
2329 */
2330 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2331 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2332 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2333 /* broken BIOS */
2334 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2335 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2336 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2337 /* forced codec slots */
93574844 2338 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2339 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
669ba27a
TI		 2340 {}
2341};
2342
f1eaaeec
TI		 2343#define AZX_FORCE_CODEC_MASK 0x100
2344
5aba4f8e 2345static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2346{
2347 const struct snd_pci_quirk *q;
2348
f1eaaeec
TI		 2349 chip->codec_probe_mask = probe_mask[dev];
2350 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2351 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2352 if (q) {
2353 printk(KERN_INFO
2354 "hda_intel: probe_mask set to 0x%x "
2355 "for device %04x:%04x\n",
2356 q->value, q->subvendor, q->subdevice);
f1eaaeec 2357 chip->codec_probe_mask = q->value;
669ba27a
TI		 2358 }
2359 }
f1eaaeec
TI		 2360
2361 /* check forced option */
2362 if (chip->codec_probe_mask != -1 &&
2363 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2364 chip->codec_mask = chip->codec_probe_mask & 0xff;
2365 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2366 chip->codec_mask);
2367 }
669ba27a
TI		 2368}
2369
4d8e22e0 2370/*
71623855 2371 * white/black-list for enable_msi
4d8e22e0 2372 */
71623855 2373static struct snd_pci_quirk msi_black_list[] __devinitdata = {
9dc8398b 2374 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 2375 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 2376 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 2377 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 2378 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 2379 {}
2380};
2381
2382static void __devinit check_msi(struct azx *chip)
2383{
2384 const struct snd_pci_quirk *q;
2385
71623855
TI		 2386 if (enable_msi >= 0) {
2387 chip->msi = !!enable_msi;
4d8e22e0 2388 return;
71623855
TI		 2389 }
2390 chip->msi = 1; /* enable MSI as default */
2391 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 2392 if (q) {
2393 printk(KERN_INFO
2394 "hda_intel: msi for device %04x:%04x set to %d\n",
2395 q->subvendor, q->subdevice, q->value);
2396 chip->msi = q->value;
80c43ed7
TI		 2397 return;
2398 }
2399
2400 /* NVidia chipsets seem to cause troubles with MSI */
2401 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
2402 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n");
2403 chip->msi = 0;
4d8e22e0
TI		 2404 }
2405}
2406
669ba27a 2407
1da177e4
LT		 2408/*
2409 * constructor
2410 */
a98f90fd 2411static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
5aba4f8e 2412 int dev, int driver_type,
a98f90fd 2413 struct azx **rchip)
1da177e4 2414{
a98f90fd 2415 struct azx *chip;
4ce107b9 2416 int i, err;
bcd72003 2417 unsigned short gcap;
a98f90fd 2418 static struct snd_device_ops ops = {
1da177e4
LT		 2419 .dev_free = azx_dev_free,
2420 };
2421
2422 *rchip = NULL;
bcd72003 2423
927fc866
PM		 2424 err = pci_enable_device(pci);
2425 if (err < 0)
1da177e4
LT		 2426 return err;
2427
e560d8d8 2428 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2429 if (!chip) {
1da177e4
LT		 2430 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2431 pci_disable_device(pci);
2432 return -ENOMEM;
2433 }
2434
2435 spin_lock_init(&chip->reg_lock);
62932df8 2436 mutex_init(&chip->open_mutex);
1da177e4
LT		 2437 chip->card = card;
2438 chip->pci = pci;
2439 chip->irq = -1;
07e4ca50 2440 chip->driver_type = driver_type;
4d8e22e0 2441 check_msi(chip);
555e219f 2442 chip->dev_index = dev;
9ad593f6 2443 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1da177e4 2444
beaffc39
SG		 2445 chip->position_fix[0] = chip->position_fix[1] =
2446 check_position_fix(chip, position_fix[dev]);
5aba4f8e 2447 check_probe_mask(chip, dev);
3372a153 2448
27346166 2449 chip->single_cmd = single_cmd;
c74db86b 2450
5c0d7bc1
TI		 2451 if (bdl_pos_adj[dev] < 0) {
2452 switch (chip->driver_type) {
0c6341ac 2453 case AZX_DRIVER_ICH:
32679f95 2454 case AZX_DRIVER_PCH:
0c6341ac 2455 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2456 break;
2457 default:
0c6341ac 2458 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2459 break;
2460 }
2461 }
2462
07e4ca50
TI		 2463#if BITS_PER_LONG != 64
2464 /* Fix up base address on ULI M5461 */
2465 if (chip->driver_type == AZX_DRIVER_ULI) {
2466 u16 tmp3;
2467 pci_read_config_word(pci, 0x40, &tmp3);
2468 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2469 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2470 }
2471#endif
2472
927fc866
PM		 2473 err = pci_request_regions(pci, "ICH HD audio");
2474 if (err < 0) {
1da177e4
LT		 2475 kfree(chip);
2476 pci_disable_device(pci);
2477 return err;
2478 }
2479
927fc866 2480 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 2481 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 2482 if (chip->remap_addr == NULL) {
2483 snd_printk(KERN_ERR SFX "ioremap error\n");
2484 err = -ENXIO;
2485 goto errout;
2486 }
2487
68e7fffc
TI		 2488 if (chip->msi)
2489 if (pci_enable_msi(pci) < 0)
2490 chip->msi = 0;
7376d013 2491
68e7fffc 2492 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT		 2493 err = -EBUSY;
2494 goto errout;
2495 }
1da177e4
LT		 2496
2497 pci_set_master(pci);
2498 synchronize_irq(chip->irq);
2499
bcd72003 2500 gcap = azx_readw(chip, GCAP);
4abc1cc2 2501 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 2502
dc4c2e6b
AB		 2503 /* disable SB600 64bit support for safety */
2504 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2505 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2506 struct pci_dev *p_smbus;
2507 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2508 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2509 NULL);
2510 if (p_smbus) {
2511 if (p_smbus->revision < 0x30)
2512 gcap &= ~ICH6_GCAP_64OK;
2513 pci_dev_put(p_smbus);
2514 }
2515 }
09240cf4 2516
396087ea
JK		 2517 /* disable 64bit DMA address for Teradici */
2518 /* it does not work with device 6549:1200 subsys e4a2:040b */
2519 if (chip->driver_type == AZX_DRIVER_TERA)
2520 gcap &= ~ICH6_GCAP_64OK;
2521
cf7aaca8 2522 /* allow 64bit DMA address if supported by H/W */
b21fadb9 2523 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 2524 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 2525 else {
e930438c
YH		 2526 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2527 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 2528 }
cf7aaca8 2529
8b6ed8e7
TI		 2530 /* read number of streams from GCAP register instead of using
2531 * hardcoded value
2532 */
2533 chip->capture_streams = (gcap >> 8) & 0x0f;
2534 chip->playback_streams = (gcap >> 12) & 0x0f;
2535 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 2536 /* gcap didn't give any info, switching to old method */
2537
2538 switch (chip->driver_type) {
2539 case AZX_DRIVER_ULI:
2540 chip->playback_streams = ULI_NUM_PLAYBACK;
2541 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 2542 break;
2543 case AZX_DRIVER_ATIHDMI:
2544 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2545 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 2546 break;
c4da29ca 2547 case AZX_DRIVER_GENERIC:
bcd72003
TD		 2548 default:
2549 chip->playback_streams = ICH6_NUM_PLAYBACK;
2550 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 2551 break;
2552 }
07e4ca50 2553 }
8b6ed8e7
TI		 2554 chip->capture_index_offset = 0;
2555 chip->playback_index_offset = chip->capture_streams;
07e4ca50 2556 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 2557 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2558 GFP_KERNEL);
927fc866 2559 if (!chip->azx_dev) {
4abc1cc2 2560 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
07e4ca50
TI		 2561 goto errout;
2562 }
2563
4ce107b9
TI		 2564 for (i = 0; i < chip->num_streams; i++) {
2565 /* allocate memory for the BDL for each stream */
2566 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2567 snd_dma_pci_data(chip->pci),
2568 BDL_SIZE, &chip->azx_dev[i].bdl);
2569 if (err < 0) {
2570 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2571 goto errout;
2572 }
1da177e4 2573 }
0be3b5d3 2574 /* allocate memory for the position buffer */
d01ce99f
TI		 2575 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2576 snd_dma_pci_data(chip->pci),
2577 chip->num_streams * 8, &chip->posbuf);
2578 if (err < 0) {
0be3b5d3
TI		 2579 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2580 goto errout;
1da177e4 2581 }
1da177e4 2582 /* allocate CORB/RIRB */
81740861
TI		 2583 err = azx_alloc_cmd_io(chip);
2584 if (err < 0)
2585 goto errout;
1da177e4
LT		 2586
2587 /* initialize streams */
2588 azx_init_stream(chip);
2589
2590 /* initialize chip */
cb53c626 2591 azx_init_pci(chip);
10e77dda 2592 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 2593
2594 /* codec detection */
927fc866 2595 if (!chip->codec_mask) {
1da177e4
LT		 2596 snd_printk(KERN_ERR SFX "no codecs found!\n");
2597 err = -ENODEV;
2598 goto errout;
2599 }
2600
d01ce99f
TI		 2601 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2602 if (err <0) {
1da177e4
LT		 2603 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2604 goto errout;
2605 }
2606
07e4ca50 2607 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 2608 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2609 sizeof(card->shortname));
2610 snprintf(card->longname, sizeof(card->longname),
2611 "%s at 0x%lx irq %i",
2612 card->shortname, chip->addr, chip->irq);
07e4ca50 2613
1da177e4
LT		 2614 *rchip = chip;
2615 return 0;
2616
2617 errout:
2618 azx_free(chip);
2619 return err;
2620}
2621
cb53c626
TI		 2622static void power_down_all_codecs(struct azx *chip)
2623{
2624#ifdef CONFIG_SND_HDA_POWER_SAVE
2625 /* The codecs were powered up in snd_hda_codec_new().
2626 * Now all initialization done, so turn them down if possible
2627 */
2628 struct hda_codec *codec;
2629 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2630 snd_hda_power_down(codec);
2631 }
2632#endif
2633}
2634
d01ce99f
TI		 2635static int __devinit azx_probe(struct pci_dev *pci,
2636 const struct pci_device_id *pci_id)
1da177e4 2637{
5aba4f8e 2638 static int dev;
a98f90fd
TI		 2639 struct snd_card *card;
2640 struct azx *chip;
927fc866 2641 int err;
1da177e4 2642
5aba4f8e
TI		 2643 if (dev >= SNDRV_CARDS)
2644 return -ENODEV;
2645 if (!enable[dev]) {
2646 dev++;
2647 return -ENOENT;
2648 }
2649
e58de7ba
TI		 2650 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2651 if (err < 0) {
1da177e4 2652 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 2653 return err;
1da177e4
LT		 2654 }
2655
4ea6fbc8
TI		 2656 /* set this here since it's referred in snd_hda_load_patch() */
2657 snd_card_set_dev(card, &pci->dev);
2658
5aba4f8e 2659 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2660 if (err < 0)
2661 goto out_free;
421a1252 2662 card->private_data = chip;
1da177e4 2663
2dca0bba
JK		 2664#ifdef CONFIG_SND_HDA_INPUT_BEEP
2665 chip->beep_mode = beep_mode[dev];
2666#endif
2667
1da177e4 2668 /* create codec instances */
a1e21c90 2669 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 2670 if (err < 0)
2671 goto out_free;
4ea6fbc8
TI		 2672#ifdef CONFIG_SND_HDA_PATCH_LOADER
2673 if (patch[dev]) {
2674 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2675 patch[dev]);
2676 err = snd_hda_load_patch(chip->bus, patch[dev]);
2677 if (err < 0)
2678 goto out_free;
2679 }
2680#endif
10e77dda 2681 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2682 err = azx_codec_configure(chip);
2683 if (err < 0)
2684 goto out_free;
2685 }
1da177e4
LT		 2686
2687 /* create PCM streams */
176d5335 2688 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 2689 if (err < 0)
2690 goto out_free;
1da177e4
LT		 2691
2692 /* create mixer controls */
d01ce99f 2693 err = azx_mixer_create(chip);
41dda0fd
WF		 2694 if (err < 0)
2695 goto out_free;
1da177e4 2696
d01ce99f 2697 err = snd_card_register(card);
41dda0fd
WF		 2698 if (err < 0)
2699 goto out_free;
1da177e4
LT		 2700
2701 pci_set_drvdata(pci, card);
cb53c626
TI		 2702 chip->running = 1;
2703 power_down_all_codecs(chip);
0cbf0098 2704 azx_notifier_register(chip);
1da177e4 2705
e25bcdba 2706 dev++;
1da177e4 2707 return err;
41dda0fd
WF		 2708out_free:
2709 snd_card_free(card);
2710 return err;
1da177e4
LT		 2711}
2712
2713static void __devexit azx_remove(struct pci_dev *pci)
2714{
2715 snd_card_free(pci_get_drvdata(pci));
2716 pci_set_drvdata(pci, NULL);
2717}
2718
2719/* PCI IDs */
cebe41d4 2720static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
87218e9c
TI		 2721 /* ICH 6..10 */
2722 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2723 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2724 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2725 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
abbc9d1b 2726 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2727 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2728 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2729 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2730 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
b29c2360
SH		 2731 /* PCH */
2732 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
c602c8ad 2733 { PCI_DEVICE(0x8086, 0x3b57), .driver_data = AZX_DRIVER_ICH },
d2f2fcd2 2734 /* CPT */
32679f95 2735 { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
87218e9c
TI		 2736 /* SCH */
2737 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2738 /* ATI SB 450/600 */
2739 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2740 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2741 /* ATI HDMI */
2742 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2743 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2744 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
9e6dd47b 2745 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
87218e9c
TI		 2746 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2747 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2748 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2749 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2750 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2751 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2752 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2753 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2754 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2755 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2756 /* VIA VT8251/VT8237A */
2757 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2758 /* SIS966 */
2759 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2760 /* ULI M5461 */
2761 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2762 /* NVIDIA MCP */
0c2fd1bf
TI		 2763 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2764 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2765 .class_mask = 0xffffff,
2766 .driver_data = AZX_DRIVER_NVIDIA },
f269002e
KY		 2767 /* Teradici */
2768 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
4e01f54b 2769 /* Creative X-Fi (CA0110-IBG) */
313f6e2d
TI		 2770#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2771 /* the following entry conflicts with snd-ctxfi driver,
2772 * as ctxfi driver mutates from HD-audio to native mode with
2773 * a special command sequence.
2774 */
4e01f54b
TI		 2775 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2776 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2777 .class_mask = 0xffffff,
2778 .driver_data = AZX_DRIVER_GENERIC },
313f6e2d
TI		 2779#else
2780 /* this entry seems still valid -- i.e. without emu20kx chip */
2781 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2782#endif
9176b672 2783 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2784 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2785 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2786 .class_mask = 0xffffff,
2787 .driver_data = AZX_DRIVER_GENERIC },
9176b672
AB		 2788 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2789 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2790 .class_mask = 0xffffff,
2791 .driver_data = AZX_DRIVER_GENERIC },
1da177e4
LT		 2792 { 0, }
2793};
2794MODULE_DEVICE_TABLE(pci, azx_ids);
2795
2796/* pci_driver definition */
2797static struct pci_driver driver = {
2798 .name = "HDA Intel",
2799 .id_table = azx_ids,
2800 .probe = azx_probe,
2801 .remove = __devexit_p(azx_remove),
421a1252
TI		 2802#ifdef CONFIG_PM
2803 .suspend = azx_suspend,
2804 .resume = azx_resume,
2805#endif
1da177e4
LT		 2806};
2807
2808static int __init alsa_card_azx_init(void)
2809{
01d25d46 2810 return pci_register_driver(&driver);
1da177e4
LT		 2811}
2812
2813static void __exit alsa_card_azx_exit(void)
2814{
2815 pci_unregister_driver(&driver);
2816}
2817
2818module_init(alsa_card_azx_init)
2819module_exit(alsa_card_azx_exit)
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