]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - sound/pci/hda/hda_intel.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: usb-audio: Fix Focusrite Scarlett 6i6 gen1 - input handling
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 *
d01ce99f
TI		 4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
1da177e4
LT		 6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
1da177e4
LT		 12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
1da177e4
LT		 21 */
22
1da177e4
LT		 23#include <linux/delay.h>
24#include <linux/interrupt.h>
362775e2 25#include <linux/kernel.h>
1da177e4 26#include <linux/module.h>
24982c5f 27#include <linux/dma-mapping.h>
1da177e4
LT		 28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/slab.h>
31#include <linux/pci.h>
62932df8 32#include <linux/mutex.h>
27fe48d9 33#include <linux/io.h>
b8dfc462 34#include <linux/pm_runtime.h>
5d890f59
PLB		 35#include <linux/clocksource.h>
36#include <linux/time.h>
f4c482a4 37#include <linux/completion.h>
5d890f59 38
27fe48d9
TI		 39#ifdef CONFIG_X86
40/* for snoop control */
41#include <asm/pgtable.h>
7f80f513 42#include <asm/set_memory.h>
50279d9b 43#include <asm/cpufeature.h>
27fe48d9 44#endif
1da177e4
LT		 45#include <sound/core.h>
46#include <sound/initval.h>
98d8fc6c
ML		 47#include <sound/hdaudio.h>
48#include <sound/hda_i915.h>
82d9d54a 49#include <sound/intel-dsp-config.h>
9121947d 50#include <linux/vgaarb.h>
a82d51ed 51#include <linux/vga_switcheroo.h>
4918cdab 52#include <linux/firmware.h>
be57bfff 53#include <sound/hda_codec.h>
05e84878 54#include "hda_controller.h"
347de1f8 55#include "hda_intel.h"
1da177e4 56
785d8c4b
LY		 57#define CREATE_TRACE_POINTS
58#include "hda_intel_trace.h"
59
b6050ef6
TI		 60/* position fix mode */
61enum {
62 POS_FIX_AUTO,
63 POS_FIX_LPIB,
64 POS_FIX_POSBUF,
65 POS_FIX_VIACOMBO,
66 POS_FIX_COMBO,
f87e7f25 67 POS_FIX_SKL,
c02f77d3 68 POS_FIX_FIFO,
b6050ef6
TI		 69};
70
9a34af4a
TI		 71/* Defines for ATI HD Audio support in SB450 south bridge */
72#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
73#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
74
75/* Defines for Nvidia HDA support */
76#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
77#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
78#define NVIDIA_HDA_ISTRM_COH 0x4d
79#define NVIDIA_HDA_OSTRM_COH 0x4c
80#define NVIDIA_HDA_ENABLE_COHBIT 0x01
81
82/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 83#define INTEL_HDA_CGCTL 0x48
84#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 85#define INTEL_SCH_HDA_DEVC 0x78
86#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
87
9a34af4a
TI		 88/* Define VIA HD Audio Device ID*/
89#define VIA_HDAC_DEVICE_ID 0x3288
90
33124929
TI		 91/* max number of SDs */
92/* ICH, ATI and VIA have 4 playback and 4 capture */
93#define ICH6_NUM_CAPTURE 4
94#define ICH6_NUM_PLAYBACK 4
95
96/* ULI has 6 playback and 5 capture */
97#define ULI_NUM_CAPTURE 5
98#define ULI_NUM_PLAYBACK 6
99
100/* ATI HDMI may have up to 8 playbacks and 0 capture */
101#define ATIHDMI_NUM_CAPTURE 0
102#define ATIHDMI_NUM_PLAYBACK 8
103
104/* TERA has 4 playback and 3 capture */
105#define TERA_NUM_CAPTURE 3
106#define TERA_NUM_PLAYBACK 4
107
1da177e4 108
5aba4f8e
TI		 109static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
110static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 111static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 112static char *model[SNDRV_CARDS];
1dac6695 113static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 114static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 115static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 116static int probe_only[SNDRV_CARDS];
26a6cb6c 117static int jackpoll_ms[SNDRV_CARDS];
41438f13 118static int single_cmd = -1;
71623855 119static int enable_msi = -1;
4ea6fbc8
TI		 120#ifdef CONFIG_SND_HDA_PATCH_LOADER
121static char *patch[SNDRV_CARDS];
122#endif
2dca0bba 123#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 124static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 125 CONFIG_SND_HDA_INPUT_BEEP_MODE};
126#endif
82d9d54a 127static bool dsp_driver = 1;
1da177e4 128
5aba4f8e 129module_param_array(index, int, NULL, 0444);
1da177e4 130MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 131module_param_array(id, charp, NULL, 0444);
1da177e4 132MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 133module_param_array(enable, bool, NULL, 0444);
134MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
135module_param_array(model, charp, NULL, 0444);
1da177e4 136MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 137module_param_array(position_fix, int, NULL, 0444);
4cb36310 138MODULE_PARM_DESC(position_fix, "DMA pointer read method."
c02f77d3 139 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
555e219f
TI		 140module_param_array(bdl_pos_adj, int, NULL, 0644);
141MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 142module_param_array(probe_mask, int, NULL, 0444);
606ad75f 143MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 144module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 145MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 146module_param_array(jackpoll_ms, int, NULL, 0444);
147MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 148module_param(single_cmd, bint, 0444);
d01ce99f
TI		 149MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
150 "(for debugging only).");
ac9ef6cf 151module_param(enable_msi, bint, 0444);
134a11f0 152MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 153#ifdef CONFIG_SND_HDA_PATCH_LOADER
154module_param_array(patch, charp, NULL, 0444);
155MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
156#endif
2dca0bba 157#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 158module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 159MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 160 "(0=off, 1=on) (default=1).");
2dca0bba 161#endif
82d9d54a
JK		 162module_param(dsp_driver, bool, 0444);
163MODULE_PARM_DESC(dsp_driver, "Allow DSP driver selection (bypass this driver) "
164 "(0=off, 1=on) (default=1)");
606ad75f 165
83012a7c 166#ifdef CONFIG_PM
65fcd41d 167static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 168static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 169 .set = param_set_xint,
170 .get = param_get_int,
171};
172#define param_check_xint param_check_int
173
fee2fba3 174static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 175module_param(power_save, xint, 0644);
fee2fba3
TI		 176MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
177 "(in second, 0 = disable).");
1da177e4 178
40088dc4
TI		 179static bool pm_blacklist = true;
180module_param(pm_blacklist, bool, 0644);
181MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
182
dee1b66c
TI		 183/* reset the HD-audio controller in power save mode.
184 * this may give more power-saving, but will take longer time to
185 * wake up.
186 */
8fc24426
TI		 187static bool power_save_controller = 1;
188module_param(power_save_controller, bool, 0644);
dee1b66c 189MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 190#else
bb573928 191#define power_save 0
83012a7c 192#endif /* CONFIG_PM */
dee1b66c 193
7bfe059e
TI		 194static int align_buffer_size = -1;
195module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 196MODULE_PARM_DESC(align_buffer_size,
197 "Force buffer and period sizes to be multiple of 128 bytes.");
198
27fe48d9 199#ifdef CONFIG_X86
7c732015
TI		 200static int hda_snoop = -1;
201module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 202MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 203#else
204#define hda_snoop true
27fe48d9
TI		 205#endif
206
207
1da177e4
LT		 208MODULE_LICENSE("GPL");
209MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
210 "{Intel, ICH6M},"
2f1b3818 211 "{Intel, ICH7},"
f5d40b30 212 "{Intel, ESB2},"
d2981393 213 "{Intel, ICH8},"
f9cc8a8b 214 "{Intel, ICH9},"
c34f5a04 215 "{Intel, ICH10},"
b29c2360 216 "{Intel, PCH},"
d2f2fcd2 217 "{Intel, CPT},"
d2edeb7c 218 "{Intel, PPT},"
8bc039a1 219 "{Intel, LPT},"
144dad99 220 "{Intel, LPT_LP},"
4eeca499 221 "{Intel, WPT_LP},"
c8b00fd2 222 "{Intel, SPT},"
b4565913 223 "{Intel, SPT_LP},"
e926f2c8 224 "{Intel, HPT},"
cea310e8 225 "{Intel, PBG},"
4979bca9 226 "{Intel, SCH},"
fc20a562 227 "{ATI, SB450},"
89be83f8 228 "{ATI, SB600},"
778b6e1b 229 "{ATI, RS600},"
5b15c95f 230 "{ATI, RS690},"
e6db1119
WL		 231 "{ATI, RS780},"
232 "{ATI, R600},"
2797f724
HRK		 233 "{ATI, RV630},"
234 "{ATI, RV610},"
27da1834
WL		 235 "{ATI, RV670},"
236 "{ATI, RV635},"
237 "{ATI, RV620},"
238 "{ATI, RV770},"
fc20a562 239 "{VIA, VT8251},"
47672310 240 "{VIA, VT8237A},"
07e4ca50
TI		 241 "{SiS, SIS966},"
242 "{ULI, M5461}}");
1da177e4
LT		 243MODULE_DESCRIPTION("Intel HDA driver");
244
a82d51ed 245#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 246#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 247#define SUPPORT_VGA_SWITCHEROO
248#endif
249#endif
250
251
1da177e4 252/*
1da177e4 253 */
1da177e4 254
07e4ca50
TI		 255/* driver types */
256enum {
257 AZX_DRIVER_ICH,
32679f95 258 AZX_DRIVER_PCH,
4979bca9 259 AZX_DRIVER_SCH,
a4b4793f 260 AZX_DRIVER_SKL,
fab1285a 261 AZX_DRIVER_HDMI,
07e4ca50 262 AZX_DRIVER_ATI,
778b6e1b 263 AZX_DRIVER_ATIHDMI,
1815b34a 264 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 265 AZX_DRIVER_VIA,
266 AZX_DRIVER_SIS,
267 AZX_DRIVER_ULI,
da3fca21 268 AZX_DRIVER_NVIDIA,
f269002e 269 AZX_DRIVER_TERA,
14d34f16 270 AZX_DRIVER_CTX,
5ae763b1 271 AZX_DRIVER_CTHDA,
c563f473 272 AZX_DRIVER_CMEDIA,
b6fcab14 273 AZX_DRIVER_ZHAOXIN,
c4da29ca 274 AZX_DRIVER_GENERIC,
2f5983f2 275 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 276};
277
37e661ee
TI		 278#define azx_get_snoop_type(chip) \
279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
280#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
281
b42b4afb
TI		 282/* quirks for old Intel chipsets */
283#define AZX_DCAPS_INTEL_ICH \
103884a3 284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 285
2ea3c6a2 286/* quirks for Intel PCH */
6603249d 287#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 288 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
bcb337d1 289 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 290
dba9b7b6 291/* PCH up to IVB; no runtime PM; bind with i915 gfx */
6603249d 292#define AZX_DCAPS_INTEL_PCH_NOPM \
dba9b7b6 293 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
6603249d 294
55913110 295/* PCH for HSW/BDW; with runtime PM */
dba9b7b6 296/* no i915 binding for this as HSW/BDW has another controller for HDMI */
d7dab4db 297#define AZX_DCAPS_INTEL_PCH \
6603249d 298 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 299
6603249d 300/* HSW HDMI */
33499a15 301#define AZX_DCAPS_INTEL_HASWELL \
103884a3 302 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
dba9b7b6 303 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
e454ff8e 304 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 305
54a0405d
LY		 306/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
307#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 308 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
dba9b7b6 309 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
e454ff8e 310 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 311
40cc2392 312#define AZX_DCAPS_INTEL_BAYTRAIL \
e454ff8e 313 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
40cc2392 314
2d846c74 315#define AZX_DCAPS_INTEL_BRASWELL \
dba9b7b6 316 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 317 AZX_DCAPS_I915_COMPONENT)
2d846c74 318
d6795827 319#define AZX_DCAPS_INTEL_SKYLAKE \
dba9b7b6 320 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
2756d914 321 AZX_DCAPS_SYNC_WRITE |\
e454ff8e 322 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
d6795827 323
2756d914 324#define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
c87693da 325
9477c58e
TI		 326/* quirks for ATI SB / AMD Hudson */
327#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 328 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
329 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 330
331/* quirks for ATI/AMD HDMI */
332#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 333 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
334 AZX_DCAPS_NO_MSI64)
9477c58e 335
37e661ee
TI		 336/* quirks for ATI HDMI with snoop off */
337#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
338 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
339
c02f77d3
TI		 340/* quirks for AMD SB */
341#define AZX_DCAPS_PRESET_AMD_SB \
342 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
343 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
344
9477c58e
TI		 345/* quirks for Nvidia */
346#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 347 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 348 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 349
5ae763b1 350#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 351 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 352 AZX_DCAPS_NO_64BIT |\
37e661ee 353 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 354
a82d51ed 355/*
2b760d88 356 * vga_switcheroo support
a82d51ed
TI		 357 */
358#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db 359#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
dd23e1d5 360#define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
5cb543db
TI		 361#else
362#define use_vga_switcheroo(chip) 0
37a3a98e 363#define needs_eld_notify_link(chip) false
5cb543db
TI		 364#endif
365
03b135ce
LY		 366#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
367 ((pci)->device == 0x0c0c) || \
368 ((pci)->device == 0x0d0c) || \
369 ((pci)->device == 0x160c))
370
7e31a015 371#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
7c23b7c1 372
48c8b0eb 373static char *driver_short_names[] = {
07e4ca50 374 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 375 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 376 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 377 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 378 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 379 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 380 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 381 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 382 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
383 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 384 [AZX_DRIVER_ULI] = "HDA ULI M5461",
385 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 386 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 387 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 388 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 389 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
b6fcab14 390 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
c4da29ca 391 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 392};
393
68e7fffc 394static int azx_acquire_irq(struct azx *chip, int do_disconnect);
37a3a98e 395static void set_default_power_save(struct azx *chip);
111d3af5 396
cb53c626
TI		 397/*
398 * initialize the PCI registers
399 */
400/* update bits in a PCI register byte */
401static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
402 unsigned char mask, unsigned char val)
403{
404 unsigned char data;
405
406 pci_read_config_byte(pci, reg, &data);
407 data &= ~mask;
408 data |= (val & mask);
409 pci_write_config_byte(pci, reg, data);
410}
411
412static void azx_init_pci(struct azx *chip)
413{
37e661ee
TI		 414 int snoop_type = azx_get_snoop_type(chip);
415
cb53c626
TI		 416 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
417 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
418 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 419 * codecs.
420 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 421 */
46f2cc80 422 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 423 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 424 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 425 }
cb53c626 426
9477c58e
TI		 427 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
428 * we need to enable snoop.
429 */
37e661ee 430 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 431 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
432 azx_snoop(chip));
cb53c626 433 update_pci_byte(chip->pci,
27fe48d9
TI		 434 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
435 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 436 }
437
438 /* For NVIDIA HDA, enable snoop */
37e661ee 439 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 440 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
441 azx_snoop(chip));
cb53c626
TI		 442 update_pci_byte(chip->pci,
443 NVIDIA_HDA_TRANSREG_ADDR,
444 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 445 update_pci_byte(chip->pci,
446 NVIDIA_HDA_ISTRM_COH,
447 0x01, NVIDIA_HDA_ENABLE_COHBIT);
448 update_pci_byte(chip->pci,
449 NVIDIA_HDA_OSTRM_COH,
450 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 451 }
452
453 /* Enable SCH/PCH snoop if needed */
37e661ee 454 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 455 unsigned short snoop;
90a5ad52 456 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 457 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
458 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
459 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
460 if (!azx_snoop(chip))
461 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
462 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 463 pci_read_config_word(chip->pci,
464 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 465 }
4e76a883
TI		 466 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
467 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
468 "Disabled" : "Enabled");
da3fca21 469 }
1da177e4
LT		 470}
471
7c23b7c1
LH		 472/*
473 * In BXT-P A0, HD-Audio DMA requests is later than expected,
474 * and makes an audio stream sensitive to system latencies when
475 * 24/32 bits are playing.
476 * Adjusting threshold of DMA fifo to force the DMA request
477 * sooner to improve latency tolerance at the expense of power.
478 */
479static void bxt_reduce_dma_latency(struct azx *chip)
480{
481 u32 val;
482
70eafad8 483 val = azx_readl(chip, VS_EM4L);
7c23b7c1 484 val &= (0x3 << 20);
70eafad8 485 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 486}
487
1f9d3d98
LY		 488/*
489 * ML_LCAP bits:
490 * bit 0: 6 MHz Supported
491 * bit 1: 12 MHz Supported
492 * bit 2: 24 MHz Supported
493 * bit 3: 48 MHz Supported
494 * bit 4: 96 MHz Supported
495 * bit 5: 192 MHz Supported
496 */
497static int intel_get_lctl_scf(struct azx *chip)
498{
499 struct hdac_bus *bus = azx_bus(chip);
500 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
501 u32 val, t;
502 int i;
503
504 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
505
506 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
507 t = preferred_bits[i];
508 if (val & (1 << t))
509 return t;
510 }
511
512 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
513 return 0;
514}
515
516static int intel_ml_lctl_set_power(struct azx *chip, int state)
517{
518 struct hdac_bus *bus = azx_bus(chip);
519 u32 val;
520 int timeout;
521
522 /*
523 * the codecs are sharing the first link setting by default
524 * If other links are enabled for stream, they need similar fix
525 */
526 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
527 val &= ~AZX_MLCTL_SPA;
528 val |= state << AZX_MLCTL_SPA_SHIFT;
529 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
530 /* wait for CPA */
531 timeout = 50;
532 while (timeout) {
533 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
534 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
535 return 0;
536 timeout--;
537 udelay(10);
538 }
539
540 return -1;
541}
542
543static void intel_init_lctl(struct azx *chip)
544{
545 struct hdac_bus *bus = azx_bus(chip);
546 u32 val;
547 int ret;
548
549 /* 0. check lctl register value is correct or not */
550 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
551 /* if SCF is already set, let's use it */
552 if ((val & ML_LCTL_SCF_MASK) != 0)
553 return;
554
555 /*
556 * Before operating on SPA, CPA must match SPA.
557 * Any deviation may result in undefined behavior.
558 */
559 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
560 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
561 return;
562
563 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
564 ret = intel_ml_lctl_set_power(chip, 0);
565 udelay(100);
566 if (ret)
567 goto set_spa;
568
569 /* 2. update SCF to select a properly audio clock*/
570 val &= ~ML_LCTL_SCF_MASK;
571 val |= intel_get_lctl_scf(chip);
572 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
573
574set_spa:
575 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
576 intel_ml_lctl_set_power(chip, 1);
577 udelay(100);
578}
579
0a673521
LH		 580static void hda_intel_init_chip(struct azx *chip, bool full_reset)
581{
98d8fc6c 582 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 583 struct pci_dev *pci = chip->pci;
6639484d 584 u32 val;
0a673521 585
e454ff8e 586 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 587 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 588 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
589 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
590 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
591 }
0a673521 592 azx_init_chip(chip, full_reset);
a4b4793f 593 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 594 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
595 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
596 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
597 }
e454ff8e
TI		 598
599 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 600
601 /* reduce dma latency to avoid noise */
7e31a015 602 if (IS_BXT(pci))
7c23b7c1 603 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 604
605 if (bus->mlcap != NULL)
606 intel_init_lctl(chip);
0a673521
LH		 607}
608
b6050ef6
TI		 609/* calculate runtime delay from LPIB */
610static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
611 unsigned int pos)
612{
7833c3f8 613 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 614 int stream = substream->stream;
615 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
616 int delay;
617
618 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
619 delay = pos - lpib_pos;
620 else
621 delay = lpib_pos - pos;
622 if (delay < 0) {
7833c3f8 623 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 624 delay = 0;
625 else
7833c3f8 626 delay += azx_dev->core.bufsize;
b6050ef6
TI		 627 }
628
7833c3f8 629 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 630 dev_info(chip->card->dev,
631 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 632 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 633 delay = 0;
634 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
635 chip->get_delay[stream] = NULL;
636 }
637
638 return bytes_to_frames(substream->runtime, delay);
639}
640
9ad593f6
TI		 641static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
642
7ca954a8
DR		 643/* called from IRQ */
644static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
645{
9a34af4a 646 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 647 int ok;
648
649 ok = azx_position_ok(chip, azx_dev);
650 if (ok == 1) {
651 azx_dev->irq_pending = 0;
652 return ok;
2f35c630 653 } else if (ok == 0) {
7ca954a8
DR		 654 /* bogus IRQ, process it later */
655 azx_dev->irq_pending = 1;
2f35c630 656 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 657 }
658 return 0;
659}
660
029d92c2
TI		 661#define display_power(chip, enable) \
662 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
17eccb27 663
9ad593f6
TI		 664/*
665 * Check whether the current DMA position is acceptable for updating
666 * periods. Returns non-zero if it's OK.
667 *
668 * Many HD-audio controllers appear pretty inaccurate about
669 * the update-IRQ timing. The IRQ is issued before actually the
670 * data is processed. So, we need to process it afterwords in a
671 * workqueue.
672 */
673static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
674{
7833c3f8 675 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 676 int stream = substream->stream;
e5463720 677 u32 wallclk;
9ad593f6
TI		 678 unsigned int pos;
679
7833c3f8
TI		 680 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
681 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 682 return -1; /* bogus (too early) interrupt */
fa00e046 683
b6050ef6
TI		 684 if (chip->get_position[stream])
685 pos = chip->get_position[stream](chip, azx_dev);
686 else { /* use the position buffer as default */
687 pos = azx_get_pos_posbuf(chip, azx_dev);
688 if (!pos || pos == (u32)-1) {
689 dev_info(chip->card->dev,
690 "Invalid position buffer, using LPIB read method instead.\n");
691 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 692 if (chip->get_position[0] == azx_get_pos_lpib &&
693 chip->get_position[1] == azx_get_pos_lpib)
694 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 695 pos = azx_get_pos_lpib(chip, azx_dev);
696 chip->get_delay[stream] = NULL;
697 } else {
698 chip->get_position[stream] = azx_get_pos_posbuf;
699 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
700 chip->get_delay[stream] = azx_get_delay_from_lpib;
701 }
702 }
703
7833c3f8 704 if (pos >= azx_dev->core.bufsize)
b6050ef6 705 pos = 0;
9ad593f6 706
7833c3f8 707 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 708 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 709 return -1; /* this shouldn't happen! */
7833c3f8
TI		 710 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
711 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 712 /* NG - it's below the first next period boundary */
4f0189be 713 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 714 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 715 return 1; /* OK, it's fine */
716}
717
718/*
719 * The work for pending PCM period updates.
720 */
721static void azx_irq_pending_work(struct work_struct *work)
722{
9a34af4a
TI		 723 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
724 struct azx *chip = &hda->chip;
7833c3f8
TI		 725 struct hdac_bus *bus = azx_bus(chip);
726 struct hdac_stream *s;
727 int pending, ok;
9ad593f6 728
9a34af4a 729 if (!hda->irq_pending_warned) {
4e76a883
TI		 730 dev_info(chip->card->dev,
731 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
732 chip->card->number);
9a34af4a 733 hda->irq_pending_warned = 1;
a6a950a8
TI		 734 }
735
9ad593f6
TI		 736 for (;;) {
737 pending = 0;
a41d1224 738 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 739 list_for_each_entry(s, &bus->stream_list, list) {
740 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 741 if (!azx_dev->irq_pending ||
7833c3f8
TI		 742 !s->substream ||
743 !s->running)
9ad593f6 744 continue;
e5463720
JK		 745 ok = azx_position_ok(chip, azx_dev);
746 if (ok > 0) {
9ad593f6 747 azx_dev->irq_pending = 0;
a41d1224 748 spin_unlock(&bus->reg_lock);
7833c3f8 749 snd_pcm_period_elapsed(s->substream);
a41d1224 750 spin_lock(&bus->reg_lock);
e5463720
JK		 751 } else if (ok < 0) {
752 pending = 0; /* too early */
9ad593f6
TI		 753 } else
754 pending++;
755 }
a41d1224 756 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 757 if (!pending)
758 return;
08af495f 759 msleep(1);
9ad593f6
TI		 760 }
761}
762
763/* clear irq_pending flags and assure no on-going workq */
764static void azx_clear_irq_pending(struct azx *chip)
765{
7833c3f8
TI		 766 struct hdac_bus *bus = azx_bus(chip);
767 struct hdac_stream *s;
9ad593f6 768
a41d1224 769 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 770 list_for_each_entry(s, &bus->stream_list, list) {
771 struct azx_dev *azx_dev = stream_to_azx_dev(s);
772 azx_dev->irq_pending = 0;
773 }
a41d1224 774 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 775}
776
68e7fffc
TI		 777static int azx_acquire_irq(struct azx *chip, int do_disconnect)
778{
a41d1224
TI		 779 struct hdac_bus *bus = azx_bus(chip);
780
437a5a46
TI		 781 if (request_irq(chip->pci->irq, azx_interrupt,
782 chip->msi ? 0 : IRQF_SHARED,
de65360b 783 chip->card->irq_descr, chip)) {
4e76a883
TI		 784 dev_err(chip->card->dev,
785 "unable to grab IRQ %d, disabling device\n",
786 chip->pci->irq);
68e7fffc
TI		 787 if (do_disconnect)
788 snd_card_disconnect(chip->card);
789 return -1;
790 }
a41d1224 791 bus->irq = chip->pci->irq;
69e13418 792 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 793 return 0;
794}
795
b6050ef6
TI		 796/* get the current DMA position with correction on VIA chips */
797static unsigned int azx_via_get_position(struct azx *chip,
798 struct azx_dev *azx_dev)
799{
800 unsigned int link_pos, mini_pos, bound_pos;
801 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
802 unsigned int fifo_size;
803
1604eeee 804 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 805 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 806 /* Playback, no problem using link position */
807 return link_pos;
808 }
809
810 /* Capture */
811 /* For new chipset,
812 * use mod to get the DMA position just like old chipset
813 */
7833c3f8
TI		 814 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
815 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6 816
7da20788 817 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
b6050ef6
TI		 818
819 if (azx_dev->insufficient) {
820 /* Link position never gather than FIFO size */
821 if (link_pos <= fifo_size)
822 return 0;
823
824 azx_dev->insufficient = 0;
825 }
826
827 if (link_pos <= fifo_size)
7833c3f8 828 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 829 else
830 mini_pos = link_pos - fifo_size;
831
832 /* Find nearest previous boudary */
7833c3f8
TI		 833 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
834 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 835 if (mod_link_pos >= fifo_size)
836 bound_pos = link_pos - mod_link_pos;
837 else if (mod_dma_pos >= mod_mini_pos)
838 bound_pos = mini_pos - mod_mini_pos;
839 else {
7833c3f8
TI		 840 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
841 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 842 bound_pos = 0;
843 }
844
845 /* Calculate real DMA position we want */
846 return bound_pos + mod_dma_pos;
847}
848
c02f77d3
TI		 849#define AMD_FIFO_SIZE 32
850
851/* get the current DMA position with FIFO size correction */
852static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
853{
854 struct snd_pcm_substream *substream = azx_dev->core.substream;
855 struct snd_pcm_runtime *runtime = substream->runtime;
856 unsigned int pos, delay;
857
858 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
859 if (!runtime)
860 return pos;
861
862 runtime->delay = AMD_FIFO_SIZE;
863 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
864 if (azx_dev->insufficient) {
865 if (pos < delay) {
866 delay = pos;
867 runtime->delay = bytes_to_frames(runtime, pos);
868 } else {
869 azx_dev->insufficient = 0;
870 }
871 }
872
873 /* correct the DMA position for capture stream */
874 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
875 if (pos < delay)
876 pos += azx_dev->core.bufsize;
877 pos -= delay;
878 }
879
880 return pos;
881}
882
883static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
884 unsigned int pos)
885{
886 struct snd_pcm_substream *substream = azx_dev->core.substream;
887
888 /* just read back the calculated value in the above */
889 return substream->runtime->delay;
890}
891
f87e7f25
TI		 892static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
893 struct azx_dev *azx_dev)
894{
895 return _snd_hdac_chip_readl(azx_bus(chip),
896 AZX_REG_VS_SDXDPIB_XBASE +
897 (AZX_REG_VS_SDXDPIB_XINTERVAL *
898 azx_dev->core.index));
899}
900
901/* get the current DMA position with correction on SKL+ chips */
902static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
903{
904 /* DPIB register gives a more accurate position for playback */
905 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
906 return azx_skl_get_dpib_pos(chip, azx_dev);
907
908 /* For capture, we need to read posbuf, but it requires a delay
909 * for the possible boundary overlap; the read of DPIB fetches the
910 * actual posbuf
911 */
912 udelay(20);
913 azx_skl_get_dpib_pos(chip, azx_dev);
914 return azx_get_pos_posbuf(chip, azx_dev);
915}
916
83012a7c 917#ifdef CONFIG_PM
65fcd41d
TI		 918static DEFINE_MUTEX(card_list_lock);
919static LIST_HEAD(card_list);
920
921static void azx_add_card_list(struct azx *chip)
922{
9a34af4a 923 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 924 mutex_lock(&card_list_lock);
9a34af4a 925 list_add(&hda->list, &card_list);
65fcd41d
TI		 926 mutex_unlock(&card_list_lock);
927}
928
929static void azx_del_card_list(struct azx *chip)
930{
9a34af4a 931 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 932 mutex_lock(&card_list_lock);
9a34af4a 933 list_del_init(&hda->list);
65fcd41d
TI		 934 mutex_unlock(&card_list_lock);
935}
936
937/* trigger power-save check at writing parameter */
938static int param_set_xint(const char *val, const struct kernel_param *kp)
939{
9a34af4a 940 struct hda_intel *hda;
65fcd41d 941 struct azx *chip;
65fcd41d
TI		 942 int prev = power_save;
943 int ret = param_set_int(val, kp);
944
945 if (ret || prev == power_save)
946 return ret;
947
948 mutex_lock(&card_list_lock);
9a34af4a
TI		 949 list_for_each_entry(hda, &card_list, list) {
950 chip = &hda->chip;
a41d1224 951 if (!hda->probe_continued || chip->disabled)
65fcd41d 952 continue;
a41d1224 953 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 954 }
955 mutex_unlock(&card_list_lock);
956 return 0;
957}
5c0b9bec 958
5c0b9bec
TI		 959/*
960 * power management
961 */
3baffc4a 962static bool azx_is_pm_ready(struct snd_card *card)
1da177e4 963{
2d9772ef
TI		 964 struct azx *chip;
965 struct hda_intel *hda;
1da177e4 966
2d9772ef 967 if (!card)
3baffc4a 968 return false;
2d9772ef
TI		 969 chip = card->private_data;
970 hda = container_of(chip, struct hda_intel, chip);
342e8449 971 if (chip->disabled || hda->init_failed || !chip->running)
3baffc4a
TI		 972 return false;
973 return true;
974}
975
976static void __azx_runtime_suspend(struct azx *chip)
977{
3baffc4a
TI		 978 azx_stop_chip(chip);
979 azx_enter_link_reset(chip);
980 azx_clear_irq_pending(chip);
e454ff8e 981 display_power(chip, false);
3baffc4a
TI		 982}
983
744c67ff 984static void __azx_runtime_resume(struct azx *chip, bool from_rt)
3baffc4a
TI		 985{
986 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
987 struct hdac_bus *bus = azx_bus(chip);
988 struct hda_codec *codec;
989 int status;
990
e454ff8e
TI		 991 display_power(chip, true);
992 if (hda->need_i915_power)
993 snd_hdac_i915_set_bclk(bus);
3baffc4a
TI		 994
995 /* Read STATESTS before controller reset */
996 status = azx_readw(chip, STATESTS);
997
998 azx_init_pci(chip);
999 hda_intel_init_chip(chip, true);
1000
744c67ff 1001 if (status && from_rt) {
3baffc4a
TI		 1002 list_for_each_codec(codec, &chip->bus)
1003 if (status & (1 << codec->addr))
1004 schedule_delayed_work(&codec->jackpoll_work,
1005 codec->jackpoll_interval);
1006 }
1007
1008 /* power down again for link-controlled chips */
e454ff8e 1009 if (!hda->need_i915_power)
029d92c2 1010 display_power(chip, false);
3baffc4a
TI		 1011}
1012
1013#ifdef CONFIG_PM_SLEEP
1014static int azx_suspend(struct device *dev)
1015{
1016 struct snd_card *card = dev_get_drvdata(dev);
1017 struct azx *chip;
1018 struct hdac_bus *bus;
1019
1020 if (!azx_is_pm_ready(card))
c5c21523
TI		 1021 return 0;
1022
3baffc4a 1023 chip = card->private_data;
a41d1224 1024 bus = azx_bus(chip);
421a1252 1025 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3baffc4a 1026 __azx_runtime_suspend(chip);
a41d1224
TI		 1027 if (bus->irq >= 0) {
1028 free_irq(bus->irq, chip);
1029 bus->irq = -1;
30b35399 1030 }
a07187c9 1031
68e7fffc 1032 if (chip->msi)
43001c95 1033 pci_disable_msi(chip->pci);
785d8c4b
LY		 1034
1035 trace_azx_suspend(chip);
1da177e4
LT		 1036 return 0;
1037}
1038
68cb2b55 1039static int azx_resume(struct device *dev)
1da177e4 1040{
68cb2b55 1041 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1042 struct azx *chip;
2d9772ef 1043
3baffc4a 1044 if (!azx_is_pm_ready(card))
2d9772ef 1045 return 0;
1da177e4 1046
2d9772ef 1047 chip = card->private_data;
68e7fffc 1048 if (chip->msi)
3baffc4a 1049 if (pci_enable_msi(chip->pci) < 0)
68e7fffc
TI		 1050 chip->msi = 0;
1051 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1052 return -EIO;
744c67ff 1053 __azx_runtime_resume(chip, false);
421a1252 1054 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 1055
1056 trace_azx_resume(chip);
1da177e4
LT		 1057 return 0;
1058}
b8dfc462 1059
3e6db33a
XZ		 1060/* put codec down to D3 at hibernation for Intel SKL+;
1061 * otherwise BIOS may still access the codec and screw up the driver
1062 */
3e6db33a
XZ		 1063static int azx_freeze_noirq(struct device *dev)
1064{
a4b4793f
TI		 1065 struct snd_card *card = dev_get_drvdata(dev);
1066 struct azx *chip = card->private_data;
3e6db33a
XZ		 1067 struct pci_dev *pci = to_pci_dev(dev);
1068
a4b4793f 1069 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1070 pci_set_power_state(pci, PCI_D3hot);
1071
1072 return 0;
1073}
1074
1075static int azx_thaw_noirq(struct device *dev)
1076{
a4b4793f
TI		 1077 struct snd_card *card = dev_get_drvdata(dev);
1078 struct azx *chip = card->private_data;
3e6db33a
XZ		 1079 struct pci_dev *pci = to_pci_dev(dev);
1080
a4b4793f 1081 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1082 pci_set_power_state(pci, PCI_D0);
1083
1084 return 0;
1085}
1086#endif /* CONFIG_PM_SLEEP */
1087
b8dfc462
ML		 1088static int azx_runtime_suspend(struct device *dev)
1089{
1090 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1091 struct azx *chip;
b8dfc462 1092
3baffc4a 1093 if (!azx_is_pm_ready(card))
2d9772ef 1094 return 0;
2d9772ef 1095 chip = card->private_data;
364aa716 1096 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1097 return 0;
1098
7d4f606c
WX		 1099 /* enable controller wake up event */
1100 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1101 STATESTS_INT_MASK);
1102
3baffc4a 1103 __azx_runtime_suspend(chip);
785d8c4b 1104 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1105 return 0;
1106}
1107
1108static int azx_runtime_resume(struct device *dev)
1109{
1110 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1111 struct azx *chip;
b8dfc462 1112
3baffc4a 1113 if (!azx_is_pm_ready(card))
2d9772ef 1114 return 0;
2d9772ef 1115 chip = card->private_data;
364aa716 1116 if (!azx_has_pm_runtime(chip))
246efa4a 1117 return 0;
744c67ff 1118 __azx_runtime_resume(chip, true);
7d4f606c
WX		 1119
1120 /* disable controller Wake Up event*/
1121 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1122 ~STATESTS_INT_MASK);
1123
785d8c4b 1124 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1125 return 0;
1126}
6eb827d2
TI		 1127
1128static int azx_runtime_idle(struct device *dev)
1129{
1130 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1131 struct azx *chip;
1132 struct hda_intel *hda;
1133
1134 if (!card)
1135 return 0;
6eb827d2 1136
2d9772ef
TI		 1137 chip = card->private_data;
1138 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1139 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1140 return 0;
1141
55ed9cd1 1142 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1143 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1144 return -EBUSY;
1145
37a3a98e 1146 /* ELD notification gets broken when HD-audio bus is off */
dd23e1d5 1147 if (needs_eld_notify_link(chip))
37a3a98e
TI		 1148 return -EBUSY;
1149
6eb827d2
TI		 1150 return 0;
1151}
1152
b8dfc462
ML		 1153static const struct dev_pm_ops azx_pm = {
1154 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1155#ifdef CONFIG_PM_SLEEP
1156 .freeze_noirq = azx_freeze_noirq,
1157 .thaw_noirq = azx_thaw_noirq,
1158#endif
6eb827d2 1159 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1160};
1161
68cb2b55
TI		 1162#define AZX_PM_OPS &azx_pm
1163#else
3baffc4a
TI		 1164#define azx_add_card_list(chip) /* NOP */
1165#define azx_del_card_list(chip) /* NOP */
68cb2b55 1166#define AZX_PM_OPS NULL
b8dfc462 1167#endif /* CONFIG_PM */
1da177e4
LT		 1168
1169
48c8b0eb 1170static int azx_probe_continue(struct azx *chip);
a82d51ed 1171
8393ec4a 1172#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1173static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1174
a82d51ed
TI		 1175static void azx_vs_set_state(struct pci_dev *pci,
1176 enum vga_switcheroo_state state)
1177{
1178 struct snd_card *card = pci_get_drvdata(pci);
1179 struct azx *chip = card->private_data;
9a34af4a 1180 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
07f4f97d 1181 struct hda_codec *codec;
a82d51ed
TI		 1182 bool disabled;
1183
9a34af4a
TI		 1184 wait_for_completion(&hda->probe_wait);
1185 if (hda->init_failed)
a82d51ed
TI		 1186 return;
1187
1188 disabled = (state == VGA_SWITCHEROO_OFF);
1189 if (chip->disabled == disabled)
1190 return;
1191
a41d1224 1192 if (!hda->probe_continued) {
a82d51ed
TI		 1193 chip->disabled = disabled;
1194 if (!disabled) {
4e76a883
TI		 1195 dev_info(chip->card->dev,
1196 "Start delayed initialization\n");
5c90680e 1197 if (azx_probe_continue(chip) < 0) {
4e76a883 1198 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1199 hda->init_failed = true;
a82d51ed
TI		 1200 }
1201 }
1202 } else {
2b760d88 1203 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1204 disabled ? "Disabling" : "Enabling");
a82d51ed 1205 if (disabled) {
07f4f97d
LW		 1206 list_for_each_codec(codec, &chip->bus) {
1207 pm_runtime_suspend(hda_codec_dev(codec));
1208 pm_runtime_disable(hda_codec_dev(codec));
1209 }
1210 pm_runtime_suspend(card->dev);
1211 pm_runtime_disable(card->dev);
2b760d88 1212 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1213 * however we have no ACPI handle, so pci/acpi can't put us there,
1214 * put ourselves there */
1215 pci->current_state = PCI_D3cold;
a82d51ed 1216 chip->disabled = true;
a41d1224 1217 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1218 dev_warn(chip->card->dev,
1219 "Cannot lock devices!\n");
a82d51ed 1220 } else {
a41d1224 1221 snd_hda_unlock_devices(&chip->bus);
a82d51ed 1222 chip->disabled = false;
07f4f97d
LW		 1223 pm_runtime_enable(card->dev);
1224 list_for_each_codec(codec, &chip->bus) {
1225 pm_runtime_enable(hda_codec_dev(codec));
1226 pm_runtime_resume(hda_codec_dev(codec));
1227 }
a82d51ed
TI		 1228 }
1229 }
1230}
1231
1232static bool azx_vs_can_switch(struct pci_dev *pci)
1233{
1234 struct snd_card *card = pci_get_drvdata(pci);
1235 struct azx *chip = card->private_data;
9a34af4a 1236 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1237
9a34af4a
TI		 1238 wait_for_completion(&hda->probe_wait);
1239 if (hda->init_failed)
a82d51ed 1240 return false;
a41d1224 1241 if (chip->disabled || !hda->probe_continued)
a82d51ed 1242 return true;
a41d1224 1243 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1244 return false;
a41d1224 1245 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1246 return true;
1247}
1248
37a3a98e
TI		 1249/*
1250 * The discrete GPU cannot power down unless the HDA controller runtime
1251 * suspends, so activate runtime PM on codecs even if power_save == 0.
1252 */
1253static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1254{
1255 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1256 struct hda_codec *codec;
1257
dd23e1d5 1258 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
37a3a98e
TI		 1259 list_for_each_codec(codec, &chip->bus)
1260 codec->auto_runtime_pm = 1;
1261 /* reset the power save setup */
1262 if (chip->running)
1263 set_default_power_save(chip);
1264 }
1265}
1266
1267static void azx_vs_gpu_bound(struct pci_dev *pci,
1268 enum vga_switcheroo_client_id client_id)
1269{
1270 struct snd_card *card = pci_get_drvdata(pci);
1271 struct azx *chip = card->private_data;
37a3a98e
TI		 1272
1273 if (client_id == VGA_SWITCHEROO_DIS)
dd23e1d5 1274 chip->bus.keep_power = 0;
37a3a98e
TI		 1275 setup_vga_switcheroo_runtime_pm(chip);
1276}
1277
e23e7a14 1278static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1279{
9a34af4a 1280 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1281 struct pci_dev *p = get_bound_vga(chip->pci);
bacd8614 1282 struct pci_dev *parent;
a82d51ed 1283 if (p) {
4e76a883 1284 dev_info(chip->card->dev,
2b760d88 1285 "Handle vga_switcheroo audio client\n");
9a34af4a 1286 hda->use_vga_switcheroo = 1;
bacd8614
KHF		 1287
1288 /* cleared in either gpu_bound op or codec probe, or when its
1289 * upstream port has _PR3 (i.e. dGPU).
1290 */
1291 parent = pci_upstream_bridge(p);
1292 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
07f4f97d 1293 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
a82d51ed
TI		 1294 pci_dev_put(p);
1295 }
1296}
1297
1298static const struct vga_switcheroo_client_ops azx_vs_ops = {
1299 .set_gpu_state = azx_vs_set_state,
1300 .can_switch = azx_vs_can_switch,
37a3a98e 1301 .gpu_bound = azx_vs_gpu_bound,
a82d51ed
TI		 1302};
1303
e23e7a14 1304static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1305{
9a34af4a 1306 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4aaf448f 1307 struct pci_dev *p;
128960a9
TI		 1308 int err;
1309
9a34af4a 1310 if (!hda->use_vga_switcheroo)
a82d51ed 1311 return 0;
4aaf448f
JQ		 1312
1313 p = get_bound_vga(chip->pci);
1314 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1315 pci_dev_put(p);
1316
128960a9
TI		 1317 if (err < 0)
1318 return err;
9a34af4a 1319 hda->vga_switcheroo_registered = 1;
246efa4a 1320
128960a9 1321 return 0;
a82d51ed
TI		 1322}
1323#else
1324#define init_vga_switcheroo(chip) /* NOP */
1325#define register_vga_switcheroo(chip) 0
8393ec4a 1326#define check_hdmi_disabled(pci) false
37a3a98e 1327#define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
a82d51ed
TI		 1328#endif /* SUPPORT_VGA_SWITCHER */
1329
1da177e4
LT		 1330/*
1331 * destructor
1332 */
a98f90fd 1333static int azx_free(struct azx *chip)
1da177e4 1334{
c67e2228 1335 struct pci_dev *pci = chip->pci;
a07187c9 1336 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1337 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1338
364aa716 1339 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228 1340 pm_runtime_get_noresume(&pci->dev);
37a3a98e 1341 chip->running = 0;
c67e2228 1342
65fcd41d
TI		 1343 azx_del_card_list(chip);
1344
9a34af4a
TI		 1345 hda->init_failed = 1; /* to be sure */
1346 complete_all(&hda->probe_wait);
f4c482a4 1347
9a34af4a 1348 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1349 if (chip->disabled && hda->probe_continued)
1350 snd_hda_unlock_devices(&chip->bus);
07f4f97d 1351 if (hda->vga_switcheroo_registered)
128960a9 1352 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1353 }
1354
a41d1224 1355 if (bus->chip_init) {
9ad593f6 1356 azx_clear_irq_pending(chip);
7833c3f8 1357 azx_stop_all_streams(chip);
1a7f60b9 1358 azx_stop_chip(chip);
1da177e4
LT		 1359 }
1360
a41d1224
TI		 1361 if (bus->irq >= 0)
1362 free_irq(bus->irq, (void*)chip);
68e7fffc 1363 if (chip->msi)
30b35399 1364 pci_disable_msi(chip->pci);
a41d1224 1365 iounmap(bus->remap_addr);
1da177e4 1366
67908994 1367 azx_free_stream_pages(chip);
a41d1224
TI		 1368 azx_free_streams(chip);
1369 snd_hdac_bus_exit(bus);
1370
a82d51ed
TI		 1371 if (chip->region_requested)
1372 pci_release_regions(chip->pci);
a41d1224 1373
1da177e4 1374 pci_disable_device(chip->pci);
4918cdab 1375#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1376 release_firmware(chip->fw);
4918cdab 1377#endif
e454ff8e 1378 display_power(chip, false);
98d8fc6c 1379
fc18282c 1380 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
fcc88d91 1381 snd_hdac_i915_exit(bus);
a07187c9 1382 kfree(hda);
1da177e4
LT		 1383
1384 return 0;
1385}
1386
a41d1224
TI		 1387static int azx_dev_disconnect(struct snd_device *device)
1388{
1389 struct azx *chip = device->device_data;
ca58f551 1390 struct hdac_bus *bus = azx_bus(chip);
a41d1224
TI		 1391
1392 chip->bus.shutdown = 1;
ca58f551
TI		 1393 cancel_work_sync(&bus->unsol_work);
1394
a41d1224
TI		 1395 return 0;
1396}
1397
a98f90fd 1398static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1399{
1400 return azx_free(device->device_data);
1401}
1402
8393ec4a 1403#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1404/*
2b760d88 1405 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1406 */
e23e7a14 1407static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1408{
1409 struct pci_dev *p;
1410
1411 /* check only discrete GPU */
1412 switch (pci->vendor) {
1413 case PCI_VENDOR_ID_ATI:
1414 case PCI_VENDOR_ID_AMD:
1415 case PCI_VENDOR_ID_NVIDIA:
1416 if (pci->devfn == 1) {
1417 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1418 pci->bus->number, 0);
1419 if (p) {
b6d7b362 1420 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
9121947d
TI		 1421 return p;
1422 pci_dev_put(p);
1423 }
1424 }
1425 break;
1426 }
1427 return NULL;
1428}
1429
e23e7a14 1430static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1431{
1432 bool vga_inactive = false;
1433 struct pci_dev *p = get_bound_vga(pci);
1434
1435 if (p) {
12b78a7f 1436 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1437 vga_inactive = true;
1438 pci_dev_put(p);
1439 }
1440 return vga_inactive;
1441}
8393ec4a 1442#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1443
3372a153
TI		 1444/*
1445 * white/black-listing for position_fix
1446 */
e23e7a14 1447static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1448 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1449 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1450 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1451 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1452 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1453 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1454 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1455 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1456 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1457 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1458 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1459 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1460 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1461 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1462 {}
1463};
1464
e23e7a14 1465static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1466{
1467 const struct snd_pci_quirk *q;
1468
c673ba1c 1469 switch (fix) {
1dac6695 1470 case POS_FIX_AUTO:
c673ba1c
TI		 1471 case POS_FIX_LPIB:
1472 case POS_FIX_POSBUF:
4cb36310 1473 case POS_FIX_VIACOMBO:
a6f2fd55 1474 case POS_FIX_COMBO:
f87e7f25 1475 case POS_FIX_SKL:
c02f77d3 1476 case POS_FIX_FIFO:
c673ba1c
TI		 1477 return fix;
1478 }
1479
c673ba1c
TI		 1480 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1481 if (q) {
4e76a883
TI		 1482 dev_info(chip->card->dev,
1483 "position_fix set to %d for device %04x:%04x\n",
1484 q->value, q->subvendor, q->subdevice);
c673ba1c 1485 return q->value;
3372a153 1486 }
bdd9ef24
DH		 1487
1488 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1489 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1490 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1491 return POS_FIX_VIACOMBO;
9477c58e 1492 }
c02f77d3
TI		 1493 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1494 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1495 return POS_FIX_FIFO;
1496 }
9477c58e 1497 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1498 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1499 return POS_FIX_LPIB;
bdd9ef24 1500 }
a4b4793f 1501 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1502 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1503 return POS_FIX_SKL;
1504 }
c673ba1c 1505 return POS_FIX_AUTO;
3372a153
TI		 1506}
1507
b6050ef6
TI		 1508static void assign_position_fix(struct azx *chip, int fix)
1509{
1510 static azx_get_pos_callback_t callbacks[] = {
1511 [POS_FIX_AUTO] = NULL,
1512 [POS_FIX_LPIB] = azx_get_pos_lpib,
1513 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1514 [POS_FIX_VIACOMBO] = azx_via_get_position,
1515 [POS_FIX_COMBO] = azx_get_pos_lpib,
f87e7f25 1516 [POS_FIX_SKL] = azx_get_pos_skl,
c02f77d3 1517 [POS_FIX_FIFO] = azx_get_pos_fifo,
b6050ef6
TI		 1518 };
1519
1520 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1521
1522 /* combo mode uses LPIB only for playback */
1523 if (fix == POS_FIX_COMBO)
1524 chip->get_position[1] = NULL;
1525
f87e7f25 1526 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1527 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1528 chip->get_delay[0] = chip->get_delay[1] =
1529 azx_get_delay_from_lpib;
1530 }
1531
c02f77d3
TI		 1532 if (fix == POS_FIX_FIFO)
1533 chip->get_delay[0] = chip->get_delay[1] =
1534 azx_get_delay_from_fifo;
b6050ef6
TI		 1535}
1536
669ba27a
TI		 1537/*
1538 * black-lists for probe_mask
1539 */
e23e7a14 1540static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1541 /* Thinkpad often breaks the controller communication when accessing
1542 * to the non-working (or non-existing) modem codec slot.
1543 */
1544 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1545 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1546 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1547 /* broken BIOS */
1548 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1549 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1550 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1551 /* forced codec slots */
93574844 1552 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1553 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1554 /* WinFast VP200 H (Teradici) user reported broken communication */
1555 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1556 {}
1557};
1558
f1eaaeec
TI		 1559#define AZX_FORCE_CODEC_MASK 0x100
1560
e23e7a14 1561static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1562{
1563 const struct snd_pci_quirk *q;
1564
f1eaaeec
TI		 1565 chip->codec_probe_mask = probe_mask[dev];
1566 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1567 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1568 if (q) {
4e76a883
TI		 1569 dev_info(chip->card->dev,
1570 "probe_mask set to 0x%x for device %04x:%04x\n",
1571 q->value, q->subvendor, q->subdevice);
f1eaaeec 1572 chip->codec_probe_mask = q->value;
669ba27a
TI		 1573 }
1574 }
f1eaaeec
TI		 1575
1576 /* check forced option */
1577 if (chip->codec_probe_mask != -1 &&
1578 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1579 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1580 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1581 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1582 }
669ba27a
TI		 1583}
1584
4d8e22e0 1585/*
71623855 1586 * white/black-list for enable_msi
4d8e22e0 1587 */
e23e7a14 1588static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1589 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1590 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1591 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1592 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1593 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1594 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1595 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1596 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1597 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1598 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1599 {}
1600};
1601
e23e7a14 1602static void check_msi(struct azx *chip)
4d8e22e0
TI		 1603{
1604 const struct snd_pci_quirk *q;
1605
71623855
TI		 1606 if (enable_msi >= 0) {
1607 chip->msi = !!enable_msi;
4d8e22e0 1608 return;
71623855
TI		 1609 }
1610 chip->msi = 1; /* enable MSI as default */
1611 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1612 if (q) {
4e76a883
TI		 1613 dev_info(chip->card->dev,
1614 "msi for device %04x:%04x set to %d\n",
1615 q->subvendor, q->subdevice, q->value);
4d8e22e0 1616 chip->msi = q->value;
80c43ed7
TI		 1617 return;
1618 }
1619
1620 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1621 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1622 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1623 chip->msi = 0;
4d8e22e0
TI		 1624 }
1625}
1626
a1585d76 1627/* check the snoop mode availability */
e23e7a14 1628static void azx_check_snoop_available(struct azx *chip)
a1585d76 1629{
7c732015 1630 int snoop = hda_snoop;
a1585d76 1631
7c732015
TI		 1632 if (snoop >= 0) {
1633 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1634 snoop ? "snoop" : "non-snoop");
1635 chip->snoop = snoop;
78c9be61 1636 chip->uc_buffer = !snoop;
7c732015
TI		 1637 return;
1638 }
1639
1640 snoop = true;
37e661ee
TI		 1641 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1642 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1643 /* force to non-snoop mode for a new VIA controller
1644 * when BIOS is set
1645 */
7c732015
TI		 1646 u8 val;
1647 pci_read_config_byte(chip->pci, 0x42, &val);
af52f998
DW		 1648 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1649 chip->pci->revision == 0x20))
7c732015 1650 snoop = false;
a1585d76
TI		 1651 }
1652
37e661ee
TI		 1653 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1654 snoop = false;
1655
7c732015 1656 chip->snoop = snoop;
78c9be61 1657 if (!snoop) {
7c732015 1658 dev_info(chip->card->dev, "Force to non-snoop mode\n");
78c9be61
TI		 1659 /* C-Media requires non-cached pages only for CORB/RIRB */
1660 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1661 chip->uc_buffer = true;
1662 }
a1585d76 1663}
669ba27a 1664
99a2008d
WX		 1665static void azx_probe_work(struct work_struct *work)
1666{
9a34af4a
TI		 1667 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1668 azx_probe_continue(&hda->chip);
99a2008d 1669}
99a2008d 1670
4f0189be
TI		 1671static int default_bdl_pos_adj(struct azx *chip)
1672{
2cf721db
TI		 1673 /* some exceptions: Atoms seem problematic with value 1 */
1674 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1675 switch (chip->pci->device) {
1676 case 0x0f04: /* Baytrail */
1677 case 0x2284: /* Braswell */
1678 return 32;
1679 }
1680 }
1681
4f0189be
TI		 1682 switch (chip->driver_type) {
1683 case AZX_DRIVER_ICH:
1684 case AZX_DRIVER_PCH:
1685 return 1;
1686 default:
1687 return 32;
1688 }
1689}
1690
1da177e4
LT		 1691/*
1692 * constructor
1693 */
a43ff5ba
TI		 1694static const struct hda_controller_ops pci_hda_ops;
1695
e23e7a14
BP		 1696static int azx_create(struct snd_card *card, struct pci_dev *pci,
1697 int dev, unsigned int driver_caps,
1698 struct azx **rchip)
1da177e4 1699{
a98f90fd 1700 static struct snd_device_ops ops = {
a41d1224 1701 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1702 .dev_free = azx_dev_free,
1703 };
a07187c9 1704 struct hda_intel *hda;
a82d51ed
TI		 1705 struct azx *chip;
1706 int err;
1da177e4
LT		 1707
1708 *rchip = NULL;
bcd72003 1709
927fc866
PM		 1710 err = pci_enable_device(pci);
1711 if (err < 0)
1da177e4
LT		 1712 return err;
1713
a07187c9
ML		 1714 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1715 if (!hda) {
1da177e4
LT		 1716 pci_disable_device(pci);
1717 return -ENOMEM;
1718 }
1719
a07187c9 1720 chip = &hda->chip;
62932df8 1721 mutex_init(&chip->open_mutex);
1da177e4
LT		 1722 chip->card = card;
1723 chip->pci = pci;
a43ff5ba 1724 chip->ops = &pci_hda_ops;
9477c58e
TI		 1725 chip->driver_caps = driver_caps;
1726 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1727 check_msi(chip);
555e219f 1728 chip->dev_index = dev;
3a182c84
TI		 1729 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1730 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
01b65bfb 1731 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1732 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1733 INIT_LIST_HEAD(&hda->list);
a82d51ed 1734 init_vga_switcheroo(chip);
9a34af4a 1735 init_completion(&hda->probe_wait);
1da177e4 1736
b6050ef6 1737 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1738
5aba4f8e 1739 check_probe_mask(chip, dev);
3372a153 1740
41438f13
TI		 1741 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1742 chip->fallback_to_single_cmd = 1;
1743 else /* explicitly set to single_cmd or not */
1744 chip->single_cmd = single_cmd;
1745
a1585d76 1746 azx_check_snoop_available(chip);
c74db86b 1747
4f0189be
TI		 1748 if (bdl_pos_adj[dev] < 0)
1749 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1750 else
1751 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1752
19abfefd 1753 err = azx_bus_init(chip, model[dev]);
a41d1224
TI		 1754 if (err < 0) {
1755 kfree(hda);
1756 pci_disable_device(pci);
1757 return err;
1758 }
1759
619a1f19
TI		 1760 /* use the non-cached pages in non-snoop mode */
1761 if (!azx_snoop(chip))
1762 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1763
7d9a1808
TI		 1764 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1765 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1766 chip->bus.needs_damn_long_delay = 1;
1767 }
1768
a82d51ed
TI		 1769 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1770 if (err < 0) {
4e76a883 1771 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1772 azx_free(chip);
1773 return err;
1774 }
1775
99a2008d 1776 /* continue probing in work context as may trigger request module */
9a34af4a 1777 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1778
a82d51ed 1779 *rchip = chip;
99a2008d 1780
a82d51ed
TI		 1781 return 0;
1782}
1783
48c8b0eb 1784static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1785{
1786 int dev = chip->dev_index;
1787 struct pci_dev *pci = chip->pci;
1788 struct snd_card *card = chip->card;
a41d1224 1789 struct hdac_bus *bus = azx_bus(chip);
67908994 1790 int err;
a82d51ed 1791 unsigned short gcap;
413cbf46 1792 unsigned int dma_bits = 64;
a82d51ed 1793
07e4ca50
TI		 1794#if BITS_PER_LONG != 64
1795 /* Fix up base address on ULI M5461 */
1796 if (chip->driver_type == AZX_DRIVER_ULI) {
1797 u16 tmp3;
1798 pci_read_config_word(pci, 0x40, &tmp3);
1799 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1800 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1801 }
1802#endif
1803
927fc866 1804 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1805 if (err < 0)
1da177e4 1806 return err;
a82d51ed 1807 chip->region_requested = 1;
1da177e4 1808
a41d1224
TI		 1809 bus->addr = pci_resource_start(pci, 0);
1810 bus->remap_addr = pci_ioremap_bar(pci, 0);
1811 if (bus->remap_addr == NULL) {
4e76a883 1812 dev_err(card->dev, "ioremap error\n");
a82d51ed 1813 return -ENXIO;
1da177e4
LT		 1814 }
1815
a4b4793f 1816 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1817 snd_hdac_bus_parse_capabilities(bus);
1818
1819 /*
1820 * Some Intel CPUs has always running timer (ART) feature and
1821 * controller may have Global time sync reporting capability, so
1822 * check both of these before declaring synchronized time reporting
1823 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1824 */
1825 chip->gts_present = false;
1826
1827#ifdef CONFIG_X86
1828 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1829 chip->gts_present = true;
1830#endif
1831
db79afa1
BH		 1832 if (chip->msi) {
1833 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1834 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1835 pci->no_64bit_msi = true;
1836 }
68e7fffc
TI		 1837 if (pci_enable_msi(pci) < 0)
1838 chip->msi = 0;
db79afa1 1839 }
7376d013 1840
1da177e4 1841 pci_set_master(pci);
a41d1224 1842 synchronize_irq(bus->irq);
1da177e4 1843
bcd72003 1844 gcap = azx_readw(chip, GCAP);
4e76a883 1845 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1846
413cbf46
TI		 1847 /* AMD devices support 40 or 48bit DMA, take the safe one */
1848 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1849 dma_bits = 40;
1850
dc4c2e6b 1851 /* disable SB600 64bit support for safety */
9477c58e 1852 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1853 struct pci_dev *p_smbus;
413cbf46 1854 dma_bits = 40;
dc4c2e6b
AB		 1855 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1856 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1857 NULL);
1858 if (p_smbus) {
1859 if (p_smbus->revision < 0x30)
fb1d8ac2 1860 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1861 pci_dev_put(p_smbus);
1862 }
1863 }
09240cf4 1864
3ab7511e
AB		 1865 /* NVidia hardware normally only supports up to 40 bits of DMA */
1866 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1867 dma_bits = 40;
1868
9477c58e
TI		 1869 /* disable 64bit DMA address on some devices */
1870 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1871 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1872 gcap &= ~AZX_GCAP_64OK;
9477c58e 1873 }
396087ea 1874
2ae66c26 1875 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1876 if (align_buffer_size >= 0)
1877 chip->align_buffer_size = !!align_buffer_size;
1878 else {
103884a3 1879 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1880 chip->align_buffer_size = 0;
7bfe059e
TI		 1881 else
1882 chip->align_buffer_size = 1;
1883 }
2ae66c26 1884
cf7aaca8 1885 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1886 if (!(gcap & AZX_GCAP_64OK))
1887 dma_bits = 32;
412b979c
QL		 1888 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1889 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1890 } else {
412b979c
QL		 1891 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1892 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1893 }
cf7aaca8 1894
8b6ed8e7
TI		 1895 /* read number of streams from GCAP register instead of using
1896 * hardcoded value
1897 */
1898 chip->capture_streams = (gcap >> 8) & 0x0f;
1899 chip->playback_streams = (gcap >> 12) & 0x0f;
1900 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1901 /* gcap didn't give any info, switching to old method */
1902
1903 switch (chip->driver_type) {
1904 case AZX_DRIVER_ULI:
1905 chip->playback_streams = ULI_NUM_PLAYBACK;
1906 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1907 break;
1908 case AZX_DRIVER_ATIHDMI:
1815b34a 1909 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1910 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1911 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1912 break;
c4da29ca 1913 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1914 default:
1915 chip->playback_streams = ICH6_NUM_PLAYBACK;
1916 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1917 break;
1918 }
07e4ca50 1919 }
8b6ed8e7
TI		 1920 chip->capture_index_offset = 0;
1921 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1922 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1923
df56c3db
JK		 1924 /* sanity check for the SDxCTL.STRM field overflow */
1925 if (chip->num_streams > 15 &&
1926 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1927 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1928 "forcing separate stream tags", chip->num_streams);
1929 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1930 }
1931
a41d1224
TI		 1932 /* initialize streams */
1933 err = azx_init_streams(chip);
81740861 1934 if (err < 0)
a82d51ed 1935 return err;
1da177e4 1936
a41d1224
TI		 1937 err = azx_alloc_stream_pages(chip);
1938 if (err < 0)
1939 return err;
1da177e4
LT		 1940
1941 /* initialize chip */
cb53c626 1942 azx_init_pci(chip);
e4d9e513 1943
e454ff8e 1944 snd_hdac_i915_set_bclk(bus);
e4d9e513 1945
0a673521 1946 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1947
1948 /* codec detection */
a41d1224 1949 if (!azx_bus(chip)->codec_mask) {
4e76a883 1950 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1951 return -ENODEV;
1da177e4
LT		 1952 }
1953
f495222e
TI		 1954 if (azx_acquire_irq(chip, 0) < 0)
1955 return -EBUSY;
1956
07e4ca50 1957 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1958 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1959 sizeof(card->shortname));
1960 snprintf(card->longname, sizeof(card->longname),
1961 "%s at 0x%lx irq %i",
a41d1224 1962 card->shortname, bus->addr, bus->irq);
07e4ca50 1963
1da177e4 1964 return 0;
1da177e4
LT		 1965}
1966
97c6a3d1 1967#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1968/* callback from request_firmware_nowait() */
1969static void azx_firmware_cb(const struct firmware *fw, void *context)
1970{
1971 struct snd_card *card = context;
1972 struct azx *chip = card->private_data;
1973 struct pci_dev *pci = chip->pci;
1974
1975 if (!fw) {
4e76a883 1976 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1977 goto error;
1978 }
1979
1980 chip->fw = fw;
1981 if (!chip->disabled) {
1982 /* continue probing */
1983 if (azx_probe_continue(chip))
1984 goto error;
1985 }
1986 return; /* OK */
1987
1988 error:
1989 snd_card_free(card);
1990 pci_set_drvdata(pci, NULL);
1991}
97c6a3d1 1992#endif
5cb543db 1993
f46ea609
DR		 1994static int disable_msi_reset_irq(struct azx *chip)
1995{
a41d1224 1996 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 1997 int err;
1998
a41d1224
TI		 1999 free_irq(bus->irq, chip);
2000 bus->irq = -1;
f46ea609
DR		 2001 pci_disable_msi(chip->pci);
2002 chip->msi = 0;
2003 err = azx_acquire_irq(chip, 1);
2004 if (err < 0)
2005 return err;
2006
2007 return 0;
2008}
2009
8769b278
DR		 2010static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2011 struct vm_area_struct *area)
2012{
2013#ifdef CONFIG_X86
2014 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2015 struct azx *chip = apcm->chip;
78c9be61 2016 if (chip->uc_buffer)
8769b278
DR		 2017 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2018#endif
2019}
2020
a43ff5ba
TI		 2021static const struct hda_controller_ops pci_hda_ops = {
2022 .disable_msi_reset_irq = disable_msi_reset_irq,
8769b278 2023 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 2024 .position_check = azx_position_check,
40830813
DR		 2025};
2026
e23e7a14
BP		 2027static int azx_probe(struct pci_dev *pci,
2028 const struct pci_device_id *pci_id)
1da177e4 2029{
5aba4f8e 2030 static int dev;
a98f90fd 2031 struct snd_card *card;
9a34af4a 2032 struct hda_intel *hda;
a98f90fd 2033 struct azx *chip;
aad730d0 2034 bool schedule_probe;
927fc866 2035 int err;
1da177e4 2036
5aba4f8e
TI		 2037 if (dev >= SNDRV_CARDS)
2038 return -ENODEV;
2039 if (!enable[dev]) {
2040 dev++;
2041 return -ENOENT;
2042 }
2043
82d9d54a
JK		 2044 /*
2045 * stop probe if another Intel's DSP driver should be activated
2046 */
2047 if (dsp_driver) {
2048 err = snd_intel_dsp_driver_probe(pci);
2049 if (err != SND_INTEL_DSP_DRIVER_ANY &&
2050 err != SND_INTEL_DSP_DRIVER_LEGACY)
2051 return -ENODEV;
2052 }
2053
60c5772b
TI		 2054 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2055 0, &card);
e58de7ba 2056 if (err < 0) {
4e76a883 2057 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2058 return err;
1da177e4
LT		 2059 }
2060
a43ff5ba 2061 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2062 if (err < 0)
2063 goto out_free;
421a1252 2064 card->private_data = chip;
9a34af4a 2065 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2066
2067 pci_set_drvdata(pci, card);
2068
2069 err = register_vga_switcheroo(chip);
2070 if (err < 0) {
2b760d88 2071 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2072 goto out_free;
2073 }
2074
2075 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2076 dev_info(card->dev, "VGA controller is disabled\n");
2077 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2078 chip->disabled = true;
2079 }
2080
aad730d0 2081 schedule_probe = !chip->disabled;
1da177e4 2082
4918cdab
TI		 2083#ifdef CONFIG_SND_HDA_PATCH_LOADER
2084 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2085 dev_info(card->dev, "Applying patch firmware '%s'\n",
2086 patch[dev]);
5cb543db
TI		 2087 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2088 &pci->dev, GFP_KERNEL, card,
2089 azx_firmware_cb);
4918cdab
TI		 2090 if (err < 0)
2091 goto out_free;
aad730d0 2092 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2093 }
2094#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2095
aad730d0 2096#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2097 if (CONTROLLER_IN_GPU(pci))
2098 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2099#endif
99a2008d 2100
aad730d0 2101 if (schedule_probe)
9a34af4a 2102 schedule_work(&hda->probe_work);
a82d51ed 2103
a82d51ed 2104 dev++;
88d071fc 2105 if (chip->disabled)
9a34af4a 2106 complete_all(&hda->probe_wait);
a82d51ed
TI		 2107 return 0;
2108
2109out_free:
2110 snd_card_free(card);
2111 return err;
2112}
2113
1ba8f9d3
HG		 2114#ifdef CONFIG_PM
2115/* On some boards setting power_save to a non 0 value leads to clicking /
2116 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2117 * figure out how to avoid these sounds, but that is not always feasible.
2118 * So we keep a list of devices where we disable powersaving as its known
2119 * to causes problems on these devices.
2120 */
2121static struct snd_pci_quirk power_save_blacklist[] = {
2122 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
8e82a728 2123 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
1ba8f9d3 2124 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
39070a98
HG		 2125 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2126 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
45e5fbc2
HG		 2127 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2128 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
1ba8f9d3 2129 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
b529ef24
HG		 2130 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2131 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
38d9c12c 2132 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
5cb6b5fc
HG		 2133 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2134 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
38d9c12c
HG		 2135 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2136 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
5cb6b5fc
HG		 2137 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2138 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
f91f1806
HG		 2139 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2140 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
cae30527
HW		 2141 /* https://bugs.launchpad.net/bugs/1821663 */
2142 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
dd6dd536
HG		 2143 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2144 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
1ba8f9d3
HG		 2145 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2146 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
721f1e6c
JK		 2147 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2148 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2149 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2150 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
cae30527
HW		 2151 /* https://bugs.launchpad.net/bugs/1821663 */
2152 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
1ba8f9d3
HG		 2153 {}
2154};
2155#endif /* CONFIG_PM */
2156
37a3a98e
TI		 2157static void set_default_power_save(struct azx *chip)
2158{
2159 int val = power_save;
2160
2161#ifdef CONFIG_PM
2162 if (pm_blacklist) {
2163 const struct snd_pci_quirk *q;
2164
2165 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2166 if (q && val) {
2167 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2168 q->subvendor, q->subdevice);
2169 val = 0;
2170 }
2171 }
2172#endif /* CONFIG_PM */
2173 snd_hda_set_power_save(&chip->bus, val * 1000);
2174}
2175
e62a42ae
DR		 2176/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2177static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2178 [AZX_DRIVER_NVIDIA] = 8,
2179 [AZX_DRIVER_TERA] = 1,
2180};
2181
48c8b0eb 2182static int azx_probe_continue(struct azx *chip)
a82d51ed 2183{
9a34af4a 2184 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2185 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2186 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2187 int dev = chip->dev_index;
2188 int err;
2189
305a0ade 2190 to_hda_bus(bus)->bus_probing = 1;
a41d1224 2191 hda->probe_continued = 1;
795614dd 2192
fcc88d91 2193 /* bind with i915 if needed */
dba9b7b6 2194 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
98d8fc6c 2195 err = snd_hdac_i915_init(bus);
535115b5
TI		 2196 if (err < 0) {
2197 /* if the controller is bound only with HDMI/DP
2198 * (for HSW and BDW), we need to abort the probe;
2199 * for other chips, still continue probing as other
2200 * codecs can be on the same link.
2201 */
bed2e98e
TI		 2202 if (CONTROLLER_IN_GPU(pci)) {
2203 dev_err(chip->card->dev,
2204 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2205 goto out_free;
fcc88d91
TI		 2206 } else {
2207 /* don't bother any longer */
e454ff8e 2208 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
fcc88d91 2209 }
535115b5 2210 }
e454ff8e
TI		 2211
2212 /* HSW/BDW controllers need this power */
2213 if (CONTROLLER_IN_GPU(pci))
2214 hda->need_i915_power = 1;
fcc88d91
TI		 2215 }
2216
2217 /* Request display power well for the HDA controller or codec. For
2218 * Haswell/Broadwell, both the display HDA controller and codec need
2219 * this power. For other platforms, like Baytrail/Braswell, only the
2220 * display codec needs the power and it can be released after probe.
2221 */
4f799e73 2222 display_power(chip, true);
99a2008d 2223
5c90680e
TI		 2224 err = azx_first_init(chip);
2225 if (err < 0)
2226 goto out_free;
2227
2dca0bba
JK		 2228#ifdef CONFIG_SND_HDA_INPUT_BEEP
2229 chip->beep_mode = beep_mode[dev];
2230#endif
2231
1da177e4 2232 /* create codec instances */
96d2bd6e 2233 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2234 if (err < 0)
2235 goto out_free;
96d2bd6e 2236
4ea6fbc8 2237#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2238 if (chip->fw) {
a41d1224 2239 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2240 chip->fw->data);
4ea6fbc8
TI		 2241 if (err < 0)
2242 goto out_free;
e39ae856 2243#ifndef CONFIG_PM
4918cdab
TI		 2244 release_firmware(chip->fw); /* no longer needed */
2245 chip->fw = NULL;
e39ae856 2246#endif
4ea6fbc8
TI		 2247 }
2248#endif
10e77dda 2249 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2250 err = azx_codec_configure(chip);
2251 if (err < 0)
2252 goto out_free;
2253 }
1da177e4 2254
a82d51ed 2255 err = snd_card_register(chip->card);
41dda0fd
WF		 2256 if (err < 0)
2257 goto out_free;
1da177e4 2258
37a3a98e
TI		 2259 setup_vga_switcheroo_runtime_pm(chip);
2260
cb53c626 2261 chip->running = 1;
65fcd41d 2262 azx_add_card_list(chip);
07f4f97d 2263
37a3a98e 2264 set_default_power_save(chip);
07f4f97d 2265
07f4f97d 2266 if (azx_has_pm_runtime(chip))
30ff5957 2267 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2268
41dda0fd 2269out_free:
457f3c86 2270 if (err < 0 || !hda->need_i915_power)
029d92c2 2271 display_power(chip, false);
88d071fc 2272 if (err < 0)
9a34af4a
TI		 2273 hda->init_failed = 1;
2274 complete_all(&hda->probe_wait);
305a0ade 2275 to_hda_bus(bus)->bus_probing = 0;
41dda0fd 2276 return err;
1da177e4
LT		 2277}
2278
e23e7a14 2279static void azx_remove(struct pci_dev *pci)
1da177e4 2280{
9121947d 2281 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2282 struct azx *chip;
2283 struct hda_intel *hda;
2284
2285 if (card) {
0b8c8219 2286 /* cancel the pending probing work */
991f86d7
TI		 2287 chip = card->private_data;
2288 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2289 /* FIXME: below is an ugly workaround.
2290 * Both device_release_driver() and driver_probe_device()
2291 * take *both* the device's and its parent's lock before
2292 * calling the remove() and probe() callbacks. The codec
2293 * probe takes the locks of both the codec itself and its
2294 * parent, i.e. the PCI controller dev. Meanwhile, when
2295 * the PCI controller is unbound, it takes its lock, too
2296 * ==> ouch, a deadlock!
2297 * As a workaround, we unlock temporarily here the controller
2298 * device during cancel_work_sync() call.
2299 */
2300 device_unlock(&pci->dev);
0b8c8219 2301 cancel_work_sync(&hda->probe_work);
ab949d51 2302 device_lock(&pci->dev);
b8dfc462 2303
9121947d 2304 snd_card_free(card);
991f86d7 2305 }
1da177e4
LT		 2306}
2307
b2a0bafa
TI		 2308static void azx_shutdown(struct pci_dev *pci)
2309{
2310 struct snd_card *card = pci_get_drvdata(pci);
2311 struct azx *chip;
2312
2313 if (!card)
2314 return;
2315 chip = card->private_data;
2316 if (chip && chip->running)
2317 azx_stop_chip(chip);
2318}
2319
1da177e4 2320/* PCI IDs */
6f51f6cf 2321static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2322 /* CPT */
9477c58e 2323 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2324 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2325 /* PBG */
9477c58e 2326 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2327 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2328 /* Panther Point */
9477c58e 2329 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2330 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2331 /* Lynx Point */
2332 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2333 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2334 /* 9 Series */
2335 { PCI_DEVICE(0x8086, 0x8ca0),
2336 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2337 /* Wellsburg */
2338 { PCI_DEVICE(0x8086, 0x8d20),
2339 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2340 { PCI_DEVICE(0x8086, 0x8d21),
2341 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2342 /* Lewisburg */
2343 { PCI_DEVICE(0x8086, 0xa1f0),
e7480b34 2344 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
5cf92c8b 2345 { PCI_DEVICE(0x8086, 0xa270),
e7480b34 2346 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
144dad99
JR		 2347 /* Lynx Point-LP */
2348 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2349 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2350 /* Lynx Point-LP */
2351 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2352 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2353 /* Wildcat Point-LP */
2354 { PCI_DEVICE(0x8086, 0x9ca0),
2355 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2356 /* Sunrise Point */
2357 { PCI_DEVICE(0x8086, 0xa170),
a4b4793f 2358 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2359 /* Sunrise Point-LP */
2360 { PCI_DEVICE(0x8086, 0x9d70),
3e9ad24b 2361 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2362 /* Kabylake */
2363 { PCI_DEVICE(0x8086, 0xa171),
a4b4793f 2364 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2365 /* Kabylake-LP */
2366 { PCI_DEVICE(0x8086, 0x9d71),
3e9ad24b 2367 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2368 /* Kabylake-H */
2369 { PCI_DEVICE(0x8086, 0xa2f0),
a4b4793f 2370 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
e79b0006
MD		 2371 /* Coffelake */
2372 { PCI_DEVICE(0x8086, 0xa348),
3e9ad24b 2373 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2357f6f0
GS		 2374 /* Cannonlake */
2375 { PCI_DEVICE(0x8086, 0x9dc8),
3e9ad24b 2376 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
d4c2ccdb
PLB		 2377 /* CometLake-LP */
2378 { PCI_DEVICE(0x8086, 0x02C8),
2379 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2380 /* CometLake-H */
2381 { PCI_DEVICE(0x8086, 0x06C8),
2382 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
b73a5854
CC		 2383 /* CometLake-S */
2384 { PCI_DEVICE(0x8086, 0xa3f0),
2385 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
491f8331
GS		 2386 /* Icelake */
2387 { PCI_DEVICE(0x8086, 0x34c8),
3e9ad24b 2388 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
4750c212
PX		 2389 /* Jasperlake */
2390 { PCI_DEVICE(0x8086, 0x38c8),
2391 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2392 /* Tigerlake */
2393 { PCI_DEVICE(0x8086, 0xa0c8),
2394 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
f94287b6
LPS		 2395 /* Elkhart Lake */
2396 { PCI_DEVICE(0x8086, 0x4b55),
2397 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
c87693da
LH		 2398 /* Broxton-P(Apollolake) */
2399 { PCI_DEVICE(0x8086, 0x5a98),
3e9ad24b 2400 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2401 /* Broxton-T */
2402 { PCI_DEVICE(0x8086, 0x1a98),
a4b4793f 2403 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
44b46d73
VK		 2404 /* Gemini-Lake */
2405 { PCI_DEVICE(0x8086, 0x3198),
3e9ad24b 2406 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2407 /* Haswell */
4a7c516b 2408 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2409 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2410 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2411 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2412 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2413 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2414 /* Broadwell */
2415 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2416 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2417 /* 5 Series/3400 */
2418 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2419 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2420 /* Poulsbo */
9477c58e 2421 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2422 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2423 /* Oaktrail */
09904b95 2424 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2425 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2426 /* BayTrail */
2427 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2428 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2429 /* Braswell */
2430 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2431 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2432 /* ICH6 */
8b0bd226 2433 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2434 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2435 /* ICH7 */
8b0bd226 2436 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2437 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2438 /* ESB2 */
8b0bd226 2439 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2440 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2441 /* ICH8 */
8b0bd226 2442 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2443 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2444 /* ICH9 */
8b0bd226 2445 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2446 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2447 /* ICH9 */
8b0bd226 2448 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2449 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2450 /* ICH10 */
8b0bd226 2451 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2452 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2453 /* ICH10 */
8b0bd226 2454 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2455 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2456 /* Generic Intel */
2457 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2458 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2459 .class_mask = 0xffffff,
103884a3 2460 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2461 /* ATI SB 450/600/700/800/900 */
2462 { PCI_DEVICE(0x1002, 0x437b),
2463 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2464 { PCI_DEVICE(0x1002, 0x4383),
2465 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2466 /* AMD Hudson */
2467 { PCI_DEVICE(0x1022, 0x780d),
2468 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
c02f77d3
TI		 2469 /* AMD, X370 & co */
2470 { PCI_DEVICE(0x1022, 0x1457),
2471 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
de768ce4
TI		 2472 /* AMD, X570 & co */
2473 { PCI_DEVICE(0x1022, 0x1487),
2474 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
3deef52c
KHF		 2475 /* AMD Stoney */
2476 { PCI_DEVICE(0x1022, 0x157a),
2477 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2478 AZX_DCAPS_PM_RUNTIME },
9ceace3c
VM		 2479 /* AMD Raven */
2480 { PCI_DEVICE(0x1022, 0x15e3),
d2c63b7d 2481 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
87218e9c 2482 /* ATI HDMI */
fd48331f
MSB		 2483 { PCI_DEVICE(0x1002, 0x0002),
2484 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
650474fb
AD		 2485 { PCI_DEVICE(0x1002, 0x1308),
2486 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2487 { PCI_DEVICE(0x1002, 0x157a),
2488 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
d716fb03
AB		 2489 { PCI_DEVICE(0x1002, 0x15b3),
2490 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2491 { PCI_DEVICE(0x1002, 0x793b),
2492 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2493 { PCI_DEVICE(0x1002, 0x7919),
2494 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2495 { PCI_DEVICE(0x1002, 0x960f),
2496 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2497 { PCI_DEVICE(0x1002, 0x970f),
2498 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2499 { PCI_DEVICE(0x1002, 0x9840),
2500 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2501 { PCI_DEVICE(0x1002, 0xaa00),
2502 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2503 { PCI_DEVICE(0x1002, 0xaa08),
2504 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2505 { PCI_DEVICE(0x1002, 0xaa10),
2506 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2507 { PCI_DEVICE(0x1002, 0xaa18),
2508 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2509 { PCI_DEVICE(0x1002, 0xaa20),
2510 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2511 { PCI_DEVICE(0x1002, 0xaa28),
2512 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2513 { PCI_DEVICE(0x1002, 0xaa30),
2514 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2515 { PCI_DEVICE(0x1002, 0xaa38),
2516 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2517 { PCI_DEVICE(0x1002, 0xaa40),
2518 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2519 { PCI_DEVICE(0x1002, 0xaa48),
2520 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2521 { PCI_DEVICE(0x1002, 0xaa50),
2522 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2523 { PCI_DEVICE(0x1002, 0xaa58),
2524 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2525 { PCI_DEVICE(0x1002, 0xaa60),
2526 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2527 { PCI_DEVICE(0x1002, 0xaa68),
2528 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2529 { PCI_DEVICE(0x1002, 0xaa80),
2530 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2531 { PCI_DEVICE(0x1002, 0xaa88),
2532 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2533 { PCI_DEVICE(0x1002, 0xaa90),
2534 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2535 { PCI_DEVICE(0x1002, 0xaa98),
2536 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2537 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2538 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2539 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2540 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2541 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2542 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2543 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2544 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2545 { PCI_DEVICE(0x1002, 0xaac0),
2546 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2547 { PCI_DEVICE(0x1002, 0xaac8),
2548 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2549 { PCI_DEVICE(0x1002, 0xaad8),
2550 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2551 { PCI_DEVICE(0x1002, 0xaae8),
2552 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
8eb22214
MSB		 2553 { PCI_DEVICE(0x1002, 0xaae0),
2554 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2555 { PCI_DEVICE(0x1002, 0xaaf0),
2556 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2557 /* VIA VT8251/VT8237A */
26f05717 2558 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2559 /* VIA GFX VT7122/VX900 */
2560 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2561 /* VIA GFX VT6122/VX11 */
2562 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2563 /* SIS966 */
2564 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2565 /* ULI M5461 */
2566 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2567 /* NVIDIA MCP */
0c2fd1bf
TI		 2568 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2569 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2570 .class_mask = 0xffffff,
9477c58e 2571 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2572 /* Teradici */
9477c58e
TI		 2573 { PCI_DEVICE(0x6549, 0x1200),
2574 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2575 { PCI_DEVICE(0x6549, 0x2200),
2576 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2577 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2578 /* CTHDA chips */
2579 { PCI_DEVICE(0x1102, 0x0010),
2580 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2581 { PCI_DEVICE(0x1102, 0x0012),
2582 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2583#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2584 /* the following entry conflicts with snd-ctxfi driver,
2585 * as ctxfi driver mutates from HD-audio to native mode with
2586 * a special command sequence.
2587 */
4e01f54b
TI		 2588 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2589 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2590 .class_mask = 0xffffff,
9477c58e 2591 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2592 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2593#else
2594 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2595 { PCI_DEVICE(0x1102, 0x0009),
2596 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2597 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2598#endif
c563f473
TI		 2599 /* CM8888 */
2600 { PCI_DEVICE(0x13f6, 0x5011),
2601 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2602 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2603 /* Vortex86MX */
2604 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2605 /* VMware HDAudio */
2606 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2607 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2608 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2609 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2610 .class_mask = 0xffffff,
9477c58e 2611 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2612 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2613 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2614 .class_mask = 0xffffff,
9477c58e 2615 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
b6fcab14
TW		 2616 /* Zhaoxin */
2617 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
1da177e4
LT		 2618 { 0, }
2619};
2620MODULE_DEVICE_TABLE(pci, azx_ids);
2621
2622/* pci_driver definition */
e9f66d9b 2623static struct pci_driver azx_driver = {
3733e424 2624 .name = KBUILD_MODNAME,
1da177e4
LT		 2625 .id_table = azx_ids,
2626 .probe = azx_probe,
e23e7a14 2627 .remove = azx_remove,
b2a0bafa 2628 .shutdown = azx_shutdown,
68cb2b55
TI		 2629 .driver = {
2630 .pm = AZX_PM_OPS,
2631 },
1da177e4
LT		 2632};
2633
e9f66d9b 2634module_pci_driver(azx_driver);
Ubuntu Jammy Linux kernel mirror