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ALSA: hda: intel: Allow repeatedly probing on codec configuration errors
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 *
d01ce99f
TI		 4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
1da177e4
LT		 6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
1da177e4
LT		 12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
1da177e4
LT		 21 */
22
1da177e4
LT		 23#include <linux/delay.h>
24#include <linux/interrupt.h>
362775e2 25#include <linux/kernel.h>
1da177e4 26#include <linux/module.h>
24982c5f 27#include <linux/dma-mapping.h>
1da177e4
LT		 28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/slab.h>
31#include <linux/pci.h>
62932df8 32#include <linux/mutex.h>
27fe48d9 33#include <linux/io.h>
b8dfc462 34#include <linux/pm_runtime.h>
5d890f59
PLB		 35#include <linux/clocksource.h>
36#include <linux/time.h>
f4c482a4 37#include <linux/completion.h>
586bc4aa 38#include <linux/acpi.h>
65fddcfc 39#include <linux/pgtable.h>
5d890f59 40
27fe48d9
TI		 41#ifdef CONFIG_X86
42/* for snoop control */
7f80f513 43#include <asm/set_memory.h>
50279d9b 44#include <asm/cpufeature.h>
27fe48d9 45#endif
1da177e4
LT		 46#include <sound/core.h>
47#include <sound/initval.h>
98d8fc6c
ML		 48#include <sound/hdaudio.h>
49#include <sound/hda_i915.h>
82d9d54a 50#include <sound/intel-dsp-config.h>
9121947d 51#include <linux/vgaarb.h>
a82d51ed 52#include <linux/vga_switcheroo.h>
4918cdab 53#include <linux/firmware.h>
be57bfff 54#include <sound/hda_codec.h>
05e84878 55#include "hda_controller.h"
347de1f8 56#include "hda_intel.h"
1da177e4 57
785d8c4b
LY		 58#define CREATE_TRACE_POINTS
59#include "hda_intel_trace.h"
60
b6050ef6
TI		 61/* position fix mode */
62enum {
63 POS_FIX_AUTO,
64 POS_FIX_LPIB,
65 POS_FIX_POSBUF,
66 POS_FIX_VIACOMBO,
67 POS_FIX_COMBO,
f87e7f25 68 POS_FIX_SKL,
c02f77d3 69 POS_FIX_FIFO,
b6050ef6
TI		 70};
71
9a34af4a
TI		 72/* Defines for ATI HD Audio support in SB450 south bridge */
73#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
74#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
75
76/* Defines for Nvidia HDA support */
77#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
78#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
79#define NVIDIA_HDA_ISTRM_COH 0x4d
80#define NVIDIA_HDA_OSTRM_COH 0x4c
81#define NVIDIA_HDA_ENABLE_COHBIT 0x01
82
83/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 84#define INTEL_HDA_CGCTL 0x48
85#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 86#define INTEL_SCH_HDA_DEVC 0x78
87#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
88
9a34af4a
TI		 89/* Define VIA HD Audio Device ID*/
90#define VIA_HDAC_DEVICE_ID 0x3288
91
33124929
TI		 92/* max number of SDs */
93/* ICH, ATI and VIA have 4 playback and 4 capture */
94#define ICH6_NUM_CAPTURE 4
95#define ICH6_NUM_PLAYBACK 4
96
97/* ULI has 6 playback and 5 capture */
98#define ULI_NUM_CAPTURE 5
99#define ULI_NUM_PLAYBACK 6
100
101/* ATI HDMI may have up to 8 playbacks and 0 capture */
102#define ATIHDMI_NUM_CAPTURE 0
103#define ATIHDMI_NUM_PLAYBACK 8
104
105/* TERA has 4 playback and 3 capture */
106#define TERA_NUM_CAPTURE 3
107#define TERA_NUM_PLAYBACK 4
108
1da177e4 109
5aba4f8e
TI		 110static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
111static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 112static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 113static char *model[SNDRV_CARDS];
1dac6695 114static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 115static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 116static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 117static int probe_only[SNDRV_CARDS];
26a6cb6c 118static int jackpoll_ms[SNDRV_CARDS];
41438f13 119static int single_cmd = -1;
71623855 120static int enable_msi = -1;
4ea6fbc8
TI		 121#ifdef CONFIG_SND_HDA_PATCH_LOADER
122static char *patch[SNDRV_CARDS];
123#endif
2dca0bba 124#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 125static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 126 CONFIG_SND_HDA_INPUT_BEEP_MODE};
127#endif
7fba6aea 128static bool dmic_detect = 1;
1da177e4 129
5aba4f8e 130module_param_array(index, int, NULL, 0444);
1da177e4 131MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 132module_param_array(id, charp, NULL, 0444);
1da177e4 133MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 134module_param_array(enable, bool, NULL, 0444);
135MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
136module_param_array(model, charp, NULL, 0444);
1da177e4 137MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 138module_param_array(position_fix, int, NULL, 0444);
4cb36310 139MODULE_PARM_DESC(position_fix, "DMA pointer read method."
c02f77d3 140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
555e219f
TI		 141module_param_array(bdl_pos_adj, int, NULL, 0644);
142MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 143module_param_array(probe_mask, int, NULL, 0444);
606ad75f 144MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 145module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 146MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 147module_param_array(jackpoll_ms, int, NULL, 0444);
148MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 149module_param(single_cmd, bint, 0444);
d01ce99f
TI		 150MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
151 "(for debugging only).");
ac9ef6cf 152module_param(enable_msi, bint, 0444);
134a11f0 153MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 154#ifdef CONFIG_SND_HDA_PATCH_LOADER
155module_param_array(patch, charp, NULL, 0444);
156MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
157#endif
2dca0bba 158#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 159module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 160MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 161 "(0=off, 1=on) (default=1).");
2dca0bba 162#endif
7fba6aea
TI		 163module_param(dmic_detect, bool, 0444);
164MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
165 "(0=off, 1=on) (default=1); "
166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
606ad75f 167
83012a7c 168#ifdef CONFIG_PM
65fcd41d 169static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 170static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 171 .set = param_set_xint,
172 .get = param_get_int,
173};
174#define param_check_xint param_check_int
175
fee2fba3 176static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 177module_param(power_save, xint, 0644);
fee2fba3
TI		 178MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
179 "(in second, 0 = disable).");
1da177e4 180
40088dc4
TI		 181static bool pm_blacklist = true;
182module_param(pm_blacklist, bool, 0644);
6317e5eb 183MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
40088dc4 184
dee1b66c
TI		 185/* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
8fc24426
TI		 189static bool power_save_controller = 1;
190module_param(power_save_controller, bool, 0644);
dee1b66c 191MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 192#else
bb573928 193#define power_save 0
83012a7c 194#endif /* CONFIG_PM */
dee1b66c 195
7bfe059e
TI		 196static int align_buffer_size = -1;
197module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 198MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
27fe48d9 201#ifdef CONFIG_X86
7c732015
TI		 202static int hda_snoop = -1;
203module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 204MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 205#else
206#define hda_snoop true
27fe48d9
TI		 207#endif
208
209
1da177e4 210MODULE_LICENSE("GPL");
1da177e4
LT		 211MODULE_DESCRIPTION("Intel HDA driver");
212
a82d51ed 213#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 214#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 215#define SUPPORT_VGA_SWITCHEROO
216#endif
217#endif
218
219
1da177e4 220/*
1da177e4 221 */
1da177e4 222
07e4ca50
TI		 223/* driver types */
224enum {
225 AZX_DRIVER_ICH,
32679f95 226 AZX_DRIVER_PCH,
4979bca9 227 AZX_DRIVER_SCH,
a4b4793f 228 AZX_DRIVER_SKL,
fab1285a 229 AZX_DRIVER_HDMI,
07e4ca50 230 AZX_DRIVER_ATI,
778b6e1b 231 AZX_DRIVER_ATIHDMI,
1815b34a 232 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 233 AZX_DRIVER_VIA,
234 AZX_DRIVER_SIS,
235 AZX_DRIVER_ULI,
da3fca21 236 AZX_DRIVER_NVIDIA,
f269002e 237 AZX_DRIVER_TERA,
14d34f16 238 AZX_DRIVER_CTX,
5ae763b1 239 AZX_DRIVER_CTHDA,
c563f473 240 AZX_DRIVER_CMEDIA,
b6fcab14 241 AZX_DRIVER_ZHAOXIN,
c4da29ca 242 AZX_DRIVER_GENERIC,
2f5983f2 243 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 244};
245
37e661ee
TI		 246#define azx_get_snoop_type(chip) \
247 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
248#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
249
b42b4afb
TI		 250/* quirks for old Intel chipsets */
251#define AZX_DCAPS_INTEL_ICH \
f34a4c9d 252 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 253
2ea3c6a2 254/* quirks for Intel PCH */
6603249d 255#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 256 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
f34a4c9d 257 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 258
dba9b7b6 259/* PCH up to IVB; no runtime PM; bind with i915 gfx */
6603249d 260#define AZX_DCAPS_INTEL_PCH_NOPM \
dba9b7b6 261 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
6603249d 262
55913110 263/* PCH for HSW/BDW; with runtime PM */
dba9b7b6 264/* no i915 binding for this as HSW/BDW has another controller for HDMI */
d7dab4db 265#define AZX_DCAPS_INTEL_PCH \
f5dac54d 266 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 267
6603249d 268/* HSW HDMI */
33499a15 269#define AZX_DCAPS_INTEL_HASWELL \
103884a3 270 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
dba9b7b6 271 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
f34a4c9d 272 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 273
54a0405d
LY		 274/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
275#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 276 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
dba9b7b6 277 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
f34a4c9d 278 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 279
40cc2392 280#define AZX_DCAPS_INTEL_BAYTRAIL \
e454ff8e 281 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
40cc2392 282
2d846c74 283#define AZX_DCAPS_INTEL_BRASWELL \
dba9b7b6 284 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 285 AZX_DCAPS_I915_COMPONENT)
2d846c74 286
d6795827 287#define AZX_DCAPS_INTEL_SKYLAKE \
dba9b7b6 288 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 289 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
d6795827 290
2756d914 291#define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
c87693da 292
9477c58e
TI		 293/* quirks for ATI SB / AMD Hudson */
294#define AZX_DCAPS_PRESET_ATI_SB \
f34a4c9d 295 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
37e661ee 296 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 297
298/* quirks for ATI/AMD HDMI */
299#define AZX_DCAPS_PRESET_ATI_HDMI \
f34a4c9d 300 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
db79afa1 301 AZX_DCAPS_NO_MSI64)
9477c58e 302
37e661ee
TI		 303/* quirks for ATI HDMI with snoop off */
304#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
305 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
306
c02f77d3
TI		 307/* quirks for AMD SB */
308#define AZX_DCAPS_PRESET_AMD_SB \
f34a4c9d 309 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
c0f1886d
TI		 310 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
311 AZX_DCAPS_RETRY_PROBE)
c02f77d3 312
9477c58e
TI		 313/* quirks for Nvidia */
314#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 315 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 316 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 317
5ae763b1 318#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 319 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 320 AZX_DCAPS_NO_64BIT |\
37e661ee 321 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 322
a82d51ed 323/*
2b760d88 324 * vga_switcheroo support
a82d51ed
TI		 325 */
326#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db 327#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
dd23e1d5 328#define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
5cb543db
TI		 329#else
330#define use_vga_switcheroo(chip) 0
37a3a98e 331#define needs_eld_notify_link(chip) false
5cb543db
TI		 332#endif
333
03b135ce
LY		 334#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
335 ((pci)->device == 0x0c0c) || \
336 ((pci)->device == 0x0d0c) || \
1bee263d
KV		 337 ((pci)->device == 0x160c) || \
338 ((pci)->device == 0x490d))
03b135ce 339
7e31a015 340#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
7c23b7c1 341
bf82326f 342static const char * const driver_short_names[] = {
07e4ca50 343 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 344 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 345 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 346 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 347 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 348 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 349 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 350 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 351 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
352 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 353 [AZX_DRIVER_ULI] = "HDA ULI M5461",
354 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 355 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 356 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 357 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 358 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
b6fcab14 359 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
c4da29ca 360 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 361};
362
68e7fffc 363static int azx_acquire_irq(struct azx *chip, int do_disconnect);
37a3a98e 364static void set_default_power_save(struct azx *chip);
111d3af5 365
cb53c626
TI		 366/*
367 * initialize the PCI registers
368 */
369/* update bits in a PCI register byte */
370static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
371 unsigned char mask, unsigned char val)
372{
373 unsigned char data;
374
375 pci_read_config_byte(pci, reg, &data);
376 data &= ~mask;
377 data |= (val & mask);
378 pci_write_config_byte(pci, reg, data);
379}
380
381static void azx_init_pci(struct azx *chip)
382{
37e661ee
TI		 383 int snoop_type = azx_get_snoop_type(chip);
384
cb53c626
TI		 385 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
386 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
387 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 388 * codecs.
389 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 390 */
46f2cc80 391 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 392 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 393 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 394 }
cb53c626 395
9477c58e
TI		 396 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
397 * we need to enable snoop.
398 */
37e661ee 399 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 400 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
401 azx_snoop(chip));
cb53c626 402 update_pci_byte(chip->pci,
27fe48d9
TI		 403 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
404 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 405 }
406
407 /* For NVIDIA HDA, enable snoop */
37e661ee 408 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 409 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
410 azx_snoop(chip));
cb53c626
TI		 411 update_pci_byte(chip->pci,
412 NVIDIA_HDA_TRANSREG_ADDR,
413 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 414 update_pci_byte(chip->pci,
415 NVIDIA_HDA_ISTRM_COH,
416 0x01, NVIDIA_HDA_ENABLE_COHBIT);
417 update_pci_byte(chip->pci,
418 NVIDIA_HDA_OSTRM_COH,
419 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 420 }
421
422 /* Enable SCH/PCH snoop if needed */
37e661ee 423 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 424 unsigned short snoop;
90a5ad52 425 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 426 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
427 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
428 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
429 if (!azx_snoop(chip))
430 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
431 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 432 pci_read_config_word(chip->pci,
433 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 434 }
4e76a883
TI		 435 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
436 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
437 "Disabled" : "Enabled");
da3fca21 438 }
1da177e4
LT		 439}
440
7c23b7c1
LH		 441/*
442 * In BXT-P A0, HD-Audio DMA requests is later than expected,
443 * and makes an audio stream sensitive to system latencies when
444 * 24/32 bits are playing.
445 * Adjusting threshold of DMA fifo to force the DMA request
446 * sooner to improve latency tolerance at the expense of power.
447 */
448static void bxt_reduce_dma_latency(struct azx *chip)
449{
450 u32 val;
451
70eafad8 452 val = azx_readl(chip, VS_EM4L);
7c23b7c1 453 val &= (0x3 << 20);
70eafad8 454 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 455}
456
1f9d3d98
LY		 457/*
458 * ML_LCAP bits:
459 * bit 0: 6 MHz Supported
460 * bit 1: 12 MHz Supported
461 * bit 2: 24 MHz Supported
462 * bit 3: 48 MHz Supported
463 * bit 4: 96 MHz Supported
464 * bit 5: 192 MHz Supported
465 */
466static int intel_get_lctl_scf(struct azx *chip)
467{
468 struct hdac_bus *bus = azx_bus(chip);
bf82326f 469 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
1f9d3d98
LY		 470 u32 val, t;
471 int i;
472
473 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
474
475 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
476 t = preferred_bits[i];
477 if (val & (1 << t))
478 return t;
479 }
480
481 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
482 return 0;
483}
484
485static int intel_ml_lctl_set_power(struct azx *chip, int state)
486{
487 struct hdac_bus *bus = azx_bus(chip);
488 u32 val;
489 int timeout;
490
491 /*
492 * the codecs are sharing the first link setting by default
493 * If other links are enabled for stream, they need similar fix
494 */
495 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
496 val &= ~AZX_MLCTL_SPA;
497 val |= state << AZX_MLCTL_SPA_SHIFT;
498 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
499 /* wait for CPA */
500 timeout = 50;
501 while (timeout) {
502 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
503 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
504 return 0;
505 timeout--;
506 udelay(10);
507 }
508
509 return -1;
510}
511
512static void intel_init_lctl(struct azx *chip)
513{
514 struct hdac_bus *bus = azx_bus(chip);
515 u32 val;
516 int ret;
517
518 /* 0. check lctl register value is correct or not */
519 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
520 /* if SCF is already set, let's use it */
521 if ((val & ML_LCTL_SCF_MASK) != 0)
522 return;
523
524 /*
525 * Before operating on SPA, CPA must match SPA.
526 * Any deviation may result in undefined behavior.
527 */
528 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
529 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
530 return;
531
532 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
533 ret = intel_ml_lctl_set_power(chip, 0);
534 udelay(100);
535 if (ret)
536 goto set_spa;
537
538 /* 2. update SCF to select a properly audio clock*/
539 val &= ~ML_LCTL_SCF_MASK;
540 val |= intel_get_lctl_scf(chip);
541 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
542
543set_spa:
544 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
545 intel_ml_lctl_set_power(chip, 1);
546 udelay(100);
547}
548
0a673521
LH		 549static void hda_intel_init_chip(struct azx *chip, bool full_reset)
550{
98d8fc6c 551 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 552 struct pci_dev *pci = chip->pci;
6639484d 553 u32 val;
0a673521 554
e454ff8e 555 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 556 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 557 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
558 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
559 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
560 }
0a673521 561 azx_init_chip(chip, full_reset);
a4b4793f 562 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 563 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
564 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
565 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
566 }
e454ff8e
TI		 567
568 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 569
570 /* reduce dma latency to avoid noise */
7e31a015 571 if (IS_BXT(pci))
7c23b7c1 572 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 573
574 if (bus->mlcap != NULL)
575 intel_init_lctl(chip);
0a673521
LH		 576}
577
b6050ef6
TI		 578/* calculate runtime delay from LPIB */
579static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
580 unsigned int pos)
581{
7833c3f8 582 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 583 int stream = substream->stream;
584 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
585 int delay;
586
587 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
588 delay = pos - lpib_pos;
589 else
590 delay = lpib_pos - pos;
591 if (delay < 0) {
7833c3f8 592 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 593 delay = 0;
594 else
7833c3f8 595 delay += azx_dev->core.bufsize;
b6050ef6
TI		 596 }
597
7833c3f8 598 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 599 dev_info(chip->card->dev,
600 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 601 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 602 delay = 0;
603 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
604 chip->get_delay[stream] = NULL;
605 }
606
607 return bytes_to_frames(substream->runtime, delay);
608}
609
9ad593f6
TI		 610static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
611
7ca954a8
DR		 612/* called from IRQ */
613static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
614{
9a34af4a 615 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 616 int ok;
617
618 ok = azx_position_ok(chip, azx_dev);
619 if (ok == 1) {
620 azx_dev->irq_pending = 0;
621 return ok;
2f35c630 622 } else if (ok == 0) {
7ca954a8
DR		 623 /* bogus IRQ, process it later */
624 azx_dev->irq_pending = 1;
2f35c630 625 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 626 }
627 return 0;
628}
629
029d92c2
TI		 630#define display_power(chip, enable) \
631 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
17eccb27 632
9ad593f6
TI		 633/*
634 * Check whether the current DMA position is acceptable for updating
635 * periods. Returns non-zero if it's OK.
636 *
637 * Many HD-audio controllers appear pretty inaccurate about
638 * the update-IRQ timing. The IRQ is issued before actually the
639 * data is processed. So, we need to process it afterwords in a
640 * workqueue.
641 */
642static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
643{
7833c3f8 644 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 645 int stream = substream->stream;
e5463720 646 u32 wallclk;
9ad593f6
TI		 647 unsigned int pos;
648
7833c3f8
TI		 649 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
650 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 651 return -1; /* bogus (too early) interrupt */
fa00e046 652
b6050ef6
TI		 653 if (chip->get_position[stream])
654 pos = chip->get_position[stream](chip, azx_dev);
655 else { /* use the position buffer as default */
656 pos = azx_get_pos_posbuf(chip, azx_dev);
657 if (!pos || pos == (u32)-1) {
658 dev_info(chip->card->dev,
659 "Invalid position buffer, using LPIB read method instead.\n");
660 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 661 if (chip->get_position[0] == azx_get_pos_lpib &&
662 chip->get_position[1] == azx_get_pos_lpib)
663 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 664 pos = azx_get_pos_lpib(chip, azx_dev);
665 chip->get_delay[stream] = NULL;
666 } else {
667 chip->get_position[stream] = azx_get_pos_posbuf;
668 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
669 chip->get_delay[stream] = azx_get_delay_from_lpib;
670 }
671 }
672
7833c3f8 673 if (pos >= azx_dev->core.bufsize)
b6050ef6 674 pos = 0;
9ad593f6 675
7833c3f8 676 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 677 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 678 return -1; /* this shouldn't happen! */
7833c3f8
TI		 679 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
680 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 681 /* NG - it's below the first next period boundary */
4f0189be 682 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 683 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 684 return 1; /* OK, it's fine */
685}
686
687/*
688 * The work for pending PCM period updates.
689 */
690static void azx_irq_pending_work(struct work_struct *work)
691{
9a34af4a
TI		 692 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
693 struct azx *chip = &hda->chip;
7833c3f8
TI		 694 struct hdac_bus *bus = azx_bus(chip);
695 struct hdac_stream *s;
696 int pending, ok;
9ad593f6 697
9a34af4a 698 if (!hda->irq_pending_warned) {
4e76a883
TI		 699 dev_info(chip->card->dev,
700 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
701 chip->card->number);
9a34af4a 702 hda->irq_pending_warned = 1;
a6a950a8
TI		 703 }
704
9ad593f6
TI		 705 for (;;) {
706 pending = 0;
a41d1224 707 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 708 list_for_each_entry(s, &bus->stream_list, list) {
709 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 710 if (!azx_dev->irq_pending ||
7833c3f8
TI		 711 !s->substream ||
712 !s->running)
9ad593f6 713 continue;
e5463720
JK		 714 ok = azx_position_ok(chip, azx_dev);
715 if (ok > 0) {
9ad593f6 716 azx_dev->irq_pending = 0;
a41d1224 717 spin_unlock(&bus->reg_lock);
7833c3f8 718 snd_pcm_period_elapsed(s->substream);
a41d1224 719 spin_lock(&bus->reg_lock);
e5463720
JK		 720 } else if (ok < 0) {
721 pending = 0; /* too early */
9ad593f6
TI		 722 } else
723 pending++;
724 }
a41d1224 725 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 726 if (!pending)
727 return;
08af495f 728 msleep(1);
9ad593f6
TI		 729 }
730}
731
732/* clear irq_pending flags and assure no on-going workq */
733static void azx_clear_irq_pending(struct azx *chip)
734{
7833c3f8
TI		 735 struct hdac_bus *bus = azx_bus(chip);
736 struct hdac_stream *s;
9ad593f6 737
a41d1224 738 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 739 list_for_each_entry(s, &bus->stream_list, list) {
740 struct azx_dev *azx_dev = stream_to_azx_dev(s);
741 azx_dev->irq_pending = 0;
742 }
a41d1224 743 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 744}
745
68e7fffc
TI		 746static int azx_acquire_irq(struct azx *chip, int do_disconnect)
747{
a41d1224
TI		 748 struct hdac_bus *bus = azx_bus(chip);
749
437a5a46
TI		 750 if (request_irq(chip->pci->irq, azx_interrupt,
751 chip->msi ? 0 : IRQF_SHARED,
de65360b 752 chip->card->irq_descr, chip)) {
4e76a883
TI		 753 dev_err(chip->card->dev,
754 "unable to grab IRQ %d, disabling device\n",
755 chip->pci->irq);
68e7fffc
TI		 756 if (do_disconnect)
757 snd_card_disconnect(chip->card);
758 return -1;
759 }
a41d1224 760 bus->irq = chip->pci->irq;
f36da940 761 chip->card->sync_irq = bus->irq;
69e13418 762 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 763 return 0;
764}
765
b6050ef6
TI		 766/* get the current DMA position with correction on VIA chips */
767static unsigned int azx_via_get_position(struct azx *chip,
768 struct azx_dev *azx_dev)
769{
770 unsigned int link_pos, mini_pos, bound_pos;
771 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
772 unsigned int fifo_size;
773
1604eeee 774 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 775 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 776 /* Playback, no problem using link position */
777 return link_pos;
778 }
779
780 /* Capture */
781 /* For new chipset,
782 * use mod to get the DMA position just like old chipset
783 */
7833c3f8
TI		 784 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
785 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6 786
7da20788 787 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
b6050ef6
TI		 788
789 if (azx_dev->insufficient) {
790 /* Link position never gather than FIFO size */
791 if (link_pos <= fifo_size)
792 return 0;
793
794 azx_dev->insufficient = 0;
795 }
796
797 if (link_pos <= fifo_size)
7833c3f8 798 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 799 else
800 mini_pos = link_pos - fifo_size;
801
802 /* Find nearest previous boudary */
7833c3f8
TI		 803 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
804 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 805 if (mod_link_pos >= fifo_size)
806 bound_pos = link_pos - mod_link_pos;
807 else if (mod_dma_pos >= mod_mini_pos)
808 bound_pos = mini_pos - mod_mini_pos;
809 else {
7833c3f8
TI		 810 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
811 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 812 bound_pos = 0;
813 }
814
815 /* Calculate real DMA position we want */
816 return bound_pos + mod_dma_pos;
817}
818
c02f77d3
TI		 819#define AMD_FIFO_SIZE 32
820
821/* get the current DMA position with FIFO size correction */
822static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
823{
824 struct snd_pcm_substream *substream = azx_dev->core.substream;
825 struct snd_pcm_runtime *runtime = substream->runtime;
826 unsigned int pos, delay;
827
828 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
829 if (!runtime)
830 return pos;
831
832 runtime->delay = AMD_FIFO_SIZE;
833 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
834 if (azx_dev->insufficient) {
835 if (pos < delay) {
836 delay = pos;
837 runtime->delay = bytes_to_frames(runtime, pos);
838 } else {
839 azx_dev->insufficient = 0;
840 }
841 }
842
843 /* correct the DMA position for capture stream */
844 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
845 if (pos < delay)
846 pos += azx_dev->core.bufsize;
847 pos -= delay;
848 }
849
850 return pos;
851}
852
853static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
854 unsigned int pos)
855{
856 struct snd_pcm_substream *substream = azx_dev->core.substream;
857
858 /* just read back the calculated value in the above */
859 return substream->runtime->delay;
860}
861
f87e7f25
TI		 862static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
863 struct azx_dev *azx_dev)
864{
865 return _snd_hdac_chip_readl(azx_bus(chip),
866 AZX_REG_VS_SDXDPIB_XBASE +
867 (AZX_REG_VS_SDXDPIB_XINTERVAL *
868 azx_dev->core.index));
869}
870
871/* get the current DMA position with correction on SKL+ chips */
872static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
873{
874 /* DPIB register gives a more accurate position for playback */
875 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
876 return azx_skl_get_dpib_pos(chip, azx_dev);
877
878 /* For capture, we need to read posbuf, but it requires a delay
879 * for the possible boundary overlap; the read of DPIB fetches the
880 * actual posbuf
881 */
882 udelay(20);
883 azx_skl_get_dpib_pos(chip, azx_dev);
884 return azx_get_pos_posbuf(chip, azx_dev);
885}
886
6f445784 887static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
472e18f6
ID		 888{
889 azx_stop_chip(chip);
6f445784
TI		 890 if (!skip_link_reset)
891 azx_enter_link_reset(chip);
472e18f6
ID		 892 azx_clear_irq_pending(chip);
893 display_power(chip, false);
894}
895
83012a7c 896#ifdef CONFIG_PM
65fcd41d
TI		 897static DEFINE_MUTEX(card_list_lock);
898static LIST_HEAD(card_list);
899
6f445784
TI		 900static void azx_shutdown_chip(struct azx *chip)
901{
902 __azx_shutdown_chip(chip, false);
903}
904
65fcd41d
TI		 905static void azx_add_card_list(struct azx *chip)
906{
9a34af4a 907 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 908 mutex_lock(&card_list_lock);
9a34af4a 909 list_add(&hda->list, &card_list);
65fcd41d
TI		 910 mutex_unlock(&card_list_lock);
911}
912
913static void azx_del_card_list(struct azx *chip)
914{
9a34af4a 915 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 916 mutex_lock(&card_list_lock);
9a34af4a 917 list_del_init(&hda->list);
65fcd41d
TI		 918 mutex_unlock(&card_list_lock);
919}
920
921/* trigger power-save check at writing parameter */
922static int param_set_xint(const char *val, const struct kernel_param *kp)
923{
9a34af4a 924 struct hda_intel *hda;
65fcd41d 925 struct azx *chip;
65fcd41d
TI		 926 int prev = power_save;
927 int ret = param_set_int(val, kp);
928
929 if (ret || prev == power_save)
930 return ret;
931
932 mutex_lock(&card_list_lock);
9a34af4a
TI		 933 list_for_each_entry(hda, &card_list, list) {
934 chip = &hda->chip;
a41d1224 935 if (!hda->probe_continued || chip->disabled)
65fcd41d 936 continue;
a41d1224 937 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 938 }
939 mutex_unlock(&card_list_lock);
940 return 0;
941}
5c0b9bec 942
5c0b9bec
TI		 943/*
944 * power management
945 */
3baffc4a 946static bool azx_is_pm_ready(struct snd_card *card)
1da177e4 947{
2d9772ef
TI		 948 struct azx *chip;
949 struct hda_intel *hda;
1da177e4 950
2d9772ef 951 if (!card)
3baffc4a 952 return false;
2d9772ef
TI		 953 chip = card->private_data;
954 hda = container_of(chip, struct hda_intel, chip);
342e8449 955 if (chip->disabled || hda->init_failed || !chip->running)
3baffc4a
TI		 956 return false;
957 return true;
958}
959
f5dac54d 960static void __azx_runtime_resume(struct azx *chip)
3baffc4a
TI		 961{
962 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
963 struct hdac_bus *bus = azx_bus(chip);
964 struct hda_codec *codec;
965 int status;
966
e454ff8e
TI		 967 display_power(chip, true);
968 if (hda->need_i915_power)
969 snd_hdac_i915_set_bclk(bus);
3baffc4a
TI		 970
971 /* Read STATESTS before controller reset */
972 status = azx_readw(chip, STATESTS);
973
974 azx_init_pci(chip);
975 hda_intel_init_chip(chip, true);
976
f5dac54d
KHF		 977 /* Avoid codec resume if runtime resume is for system suspend */
978 if (!chip->pm_prepared) {
a6e7d0a4
KV		 979 list_for_each_codec(codec, &chip->bus) {
980 if (codec->relaxed_resume)
981 continue;
982
983 if (codec->forced_resume || (status & (1 << codec->addr)))
984 pm_request_resume(hda_codec_dev(codec));
985 }
3baffc4a
TI		 986 }
987
988 /* power down again for link-controlled chips */
e454ff8e 989 if (!hda->need_i915_power)
029d92c2 990 display_power(chip, false);
3baffc4a
TI		 991}
992
993#ifdef CONFIG_PM_SLEEP
f5dac54d
KHF		 994static int azx_prepare(struct device *dev)
995{
996 struct snd_card *card = dev_get_drvdata(dev);
997 struct azx *chip;
998
66affb7b
TI		 999 if (!azx_is_pm_ready(card))
1000 return 0;
1001
f5dac54d
KHF		 1002 chip = card->private_data;
1003 chip->pm_prepared = 1;
c8f79808 1004 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
f5dac54d 1005
13661fc4
TI		 1006 flush_work(&azx_bus(chip)->unsol_work);
1007
f5dac54d
KHF		 1008 /* HDA controller always requires different WAKEEN for runtime suspend
1009 * and system suspend, so don't use direct-complete here.
1010 */
1011 return 0;
1012}
1013
1014static void azx_complete(struct device *dev)
1015{
1016 struct snd_card *card = dev_get_drvdata(dev);
1017 struct azx *chip;
1018
66affb7b
TI		 1019 if (!azx_is_pm_ready(card))
1020 return;
1021
f5dac54d 1022 chip = card->private_data;
c8f79808 1023 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
f5dac54d
KHF		 1024 chip->pm_prepared = 0;
1025}
1026
3baffc4a
TI		 1027static int azx_suspend(struct device *dev)
1028{
1029 struct snd_card *card = dev_get_drvdata(dev);
1030 struct azx *chip;
1031 struct hdac_bus *bus;
1032
1033 if (!azx_is_pm_ready(card))
c5c21523
TI		 1034 return 0;
1035
3baffc4a 1036 chip = card->private_data;
a41d1224 1037 bus = azx_bus(chip);
472e18f6 1038 azx_shutdown_chip(chip);
a41d1224
TI		 1039 if (bus->irq >= 0) {
1040 free_irq(bus->irq, chip);
1041 bus->irq = -1;
f36da940 1042 chip->card->sync_irq = -1;
30b35399 1043 }
a07187c9 1044
68e7fffc 1045 if (chip->msi)
43001c95 1046 pci_disable_msi(chip->pci);
785d8c4b
LY		 1047
1048 trace_azx_suspend(chip);
1da177e4
LT		 1049 return 0;
1050}
1051
68cb2b55 1052static int azx_resume(struct device *dev)
1da177e4 1053{
68cb2b55 1054 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1055 struct azx *chip;
2d9772ef 1056
3baffc4a 1057 if (!azx_is_pm_ready(card))
2d9772ef 1058 return 0;
1da177e4 1059
2d9772ef 1060 chip = card->private_data;
68e7fffc 1061 if (chip->msi)
3baffc4a 1062 if (pci_enable_msi(chip->pci) < 0)
68e7fffc
TI		 1063 chip->msi = 0;
1064 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1065 return -EIO;
c4c8dd6e 1066
f5dac54d 1067 __azx_runtime_resume(chip);
785d8c4b
LY		 1068
1069 trace_azx_resume(chip);
1da177e4
LT		 1070 return 0;
1071}
b8dfc462 1072
3e6db33a
XZ		 1073/* put codec down to D3 at hibernation for Intel SKL+;
1074 * otherwise BIOS may still access the codec and screw up the driver
1075 */
3e6db33a
XZ		 1076static int azx_freeze_noirq(struct device *dev)
1077{
a4b4793f
TI		 1078 struct snd_card *card = dev_get_drvdata(dev);
1079 struct azx *chip = card->private_data;
3e6db33a
XZ		 1080 struct pci_dev *pci = to_pci_dev(dev);
1081
10db5bcc
TI		 1082 if (!azx_is_pm_ready(card))
1083 return 0;
a4b4793f 1084 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1085 pci_set_power_state(pci, PCI_D3hot);
1086
1087 return 0;
1088}
1089
1090static int azx_thaw_noirq(struct device *dev)
1091{
a4b4793f
TI		 1092 struct snd_card *card = dev_get_drvdata(dev);
1093 struct azx *chip = card->private_data;
3e6db33a
XZ		 1094 struct pci_dev *pci = to_pci_dev(dev);
1095
10db5bcc
TI		 1096 if (!azx_is_pm_ready(card))
1097 return 0;
a4b4793f 1098 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1099 pci_set_power_state(pci, PCI_D0);
1100
1101 return 0;
1102}
1103#endif /* CONFIG_PM_SLEEP */
1104
b8dfc462
ML		 1105static int azx_runtime_suspend(struct device *dev)
1106{
1107 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1108 struct azx *chip;
b8dfc462 1109
3baffc4a 1110 if (!azx_is_pm_ready(card))
2d9772ef 1111 return 0;
2d9772ef 1112 chip = card->private_data;
246efa4a 1113
7d4f606c 1114 /* enable controller wake up event */
f5dac54d 1115 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
7d4f606c 1116
472e18f6 1117 azx_shutdown_chip(chip);
785d8c4b 1118 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1119 return 0;
1120}
1121
1122static int azx_runtime_resume(struct device *dev)
1123{
1124 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1125 struct azx *chip;
b8dfc462 1126
3baffc4a 1127 if (!azx_is_pm_ready(card))
2d9772ef 1128 return 0;
2d9772ef 1129 chip = card->private_data;
f5dac54d 1130 __azx_runtime_resume(chip);
7d4f606c
WX		 1131
1132 /* disable controller Wake Up event*/
f5dac54d 1133 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
7d4f606c 1134
785d8c4b 1135 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1136 return 0;
1137}
6eb827d2
TI		 1138
1139static int azx_runtime_idle(struct device *dev)
1140{
1141 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1142 struct azx *chip;
1143 struct hda_intel *hda;
1144
1145 if (!card)
1146 return 0;
6eb827d2 1147
2d9772ef
TI		 1148 chip = card->private_data;
1149 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1150 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1151 return 0;
1152
55ed9cd1 1153 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1154 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1155 return -EBUSY;
1156
37a3a98e 1157 /* ELD notification gets broken when HD-audio bus is off */
dd23e1d5 1158 if (needs_eld_notify_link(chip))
37a3a98e
TI		 1159 return -EBUSY;
1160
6eb827d2
TI		 1161 return 0;
1162}
1163
b8dfc462
ML		 1164static const struct dev_pm_ops azx_pm = {
1165 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a 1166#ifdef CONFIG_PM_SLEEP
f5dac54d
KHF		 1167 .prepare = azx_prepare,
1168 .complete = azx_complete,
3e6db33a
XZ		 1169 .freeze_noirq = azx_freeze_noirq,
1170 .thaw_noirq = azx_thaw_noirq,
1171#endif
6eb827d2 1172 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1173};
1174
68cb2b55
TI		 1175#define AZX_PM_OPS &azx_pm
1176#else
3baffc4a
TI		 1177#define azx_add_card_list(chip) /* NOP */
1178#define azx_del_card_list(chip) /* NOP */
68cb2b55 1179#define AZX_PM_OPS NULL
b8dfc462 1180#endif /* CONFIG_PM */
1da177e4
LT		 1181
1182
48c8b0eb 1183static int azx_probe_continue(struct azx *chip);
a82d51ed 1184
8393ec4a 1185#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1186static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1187
a82d51ed
TI		 1188static void azx_vs_set_state(struct pci_dev *pci,
1189 enum vga_switcheroo_state state)
1190{
1191 struct snd_card *card = pci_get_drvdata(pci);
1192 struct azx *chip = card->private_data;
9a34af4a 1193 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
07f4f97d 1194 struct hda_codec *codec;
a82d51ed
TI		 1195 bool disabled;
1196
9a34af4a
TI		 1197 wait_for_completion(&hda->probe_wait);
1198 if (hda->init_failed)
a82d51ed
TI		 1199 return;
1200
1201 disabled = (state == VGA_SWITCHEROO_OFF);
1202 if (chip->disabled == disabled)
1203 return;
1204
a41d1224 1205 if (!hda->probe_continued) {
a82d51ed
TI		 1206 chip->disabled = disabled;
1207 if (!disabled) {
4e76a883
TI		 1208 dev_info(chip->card->dev,
1209 "Start delayed initialization\n");
2393e755 1210 if (azx_probe_continue(chip) < 0)
4e76a883 1211 dev_err(chip->card->dev, "initialization error\n");
a82d51ed
TI		 1212 }
1213 } else {
2b760d88 1214 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1215 disabled ? "Disabling" : "Enabling");
a82d51ed 1216 if (disabled) {
07f4f97d
LW		 1217 list_for_each_codec(codec, &chip->bus) {
1218 pm_runtime_suspend(hda_codec_dev(codec));
1219 pm_runtime_disable(hda_codec_dev(codec));
1220 }
1221 pm_runtime_suspend(card->dev);
1222 pm_runtime_disable(card->dev);
2b760d88 1223 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1224 * however we have no ACPI handle, so pci/acpi can't put us there,
1225 * put ourselves there */
1226 pci->current_state = PCI_D3cold;
a82d51ed 1227 chip->disabled = true;
a41d1224 1228 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1229 dev_warn(chip->card->dev,
1230 "Cannot lock devices!\n");
a82d51ed 1231 } else {
a41d1224 1232 snd_hda_unlock_devices(&chip->bus);
a82d51ed 1233 chip->disabled = false;
07f4f97d
LW		 1234 pm_runtime_enable(card->dev);
1235 list_for_each_codec(codec, &chip->bus) {
1236 pm_runtime_enable(hda_codec_dev(codec));
1237 pm_runtime_resume(hda_codec_dev(codec));
1238 }
a82d51ed
TI		 1239 }
1240 }
1241}
1242
1243static bool azx_vs_can_switch(struct pci_dev *pci)
1244{
1245 struct snd_card *card = pci_get_drvdata(pci);
1246 struct azx *chip = card->private_data;
9a34af4a 1247 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1248
9a34af4a
TI		 1249 wait_for_completion(&hda->probe_wait);
1250 if (hda->init_failed)
a82d51ed 1251 return false;
a41d1224 1252 if (chip->disabled || !hda->probe_continued)
a82d51ed 1253 return true;
a41d1224 1254 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1255 return false;
a41d1224 1256 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1257 return true;
1258}
1259
37a3a98e
TI		 1260/*
1261 * The discrete GPU cannot power down unless the HDA controller runtime
1262 * suspends, so activate runtime PM on codecs even if power_save == 0.
1263 */
1264static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1265{
1266 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1267 struct hda_codec *codec;
1268
dd23e1d5 1269 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
37a3a98e
TI		 1270 list_for_each_codec(codec, &chip->bus)
1271 codec->auto_runtime_pm = 1;
1272 /* reset the power save setup */
1273 if (chip->running)
1274 set_default_power_save(chip);
1275 }
1276}
1277
1278static void azx_vs_gpu_bound(struct pci_dev *pci,
1279 enum vga_switcheroo_client_id client_id)
1280{
1281 struct snd_card *card = pci_get_drvdata(pci);
1282 struct azx *chip = card->private_data;
37a3a98e
TI		 1283
1284 if (client_id == VGA_SWITCHEROO_DIS)
dd23e1d5 1285 chip->bus.keep_power = 0;
37a3a98e
TI		 1286 setup_vga_switcheroo_runtime_pm(chip);
1287}
1288
e23e7a14 1289static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1290{
9a34af4a 1291 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1292 struct pci_dev *p = get_bound_vga(chip->pci);
bacd8614 1293 struct pci_dev *parent;
a82d51ed 1294 if (p) {
4e76a883 1295 dev_info(chip->card->dev,
2b760d88 1296 "Handle vga_switcheroo audio client\n");
9a34af4a 1297 hda->use_vga_switcheroo = 1;
bacd8614
KHF		 1298
1299 /* cleared in either gpu_bound op or codec probe, or when its
1300 * upstream port has _PR3 (i.e. dGPU).
1301 */
1302 parent = pci_upstream_bridge(p);
1303 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
07f4f97d 1304 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
a82d51ed
TI		 1305 pci_dev_put(p);
1306 }
1307}
1308
1309static const struct vga_switcheroo_client_ops azx_vs_ops = {
1310 .set_gpu_state = azx_vs_set_state,
1311 .can_switch = azx_vs_can_switch,
37a3a98e 1312 .gpu_bound = azx_vs_gpu_bound,
a82d51ed
TI		 1313};
1314
e23e7a14 1315static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1316{
9a34af4a 1317 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4aaf448f 1318 struct pci_dev *p;
128960a9
TI		 1319 int err;
1320
9a34af4a 1321 if (!hda->use_vga_switcheroo)
a82d51ed 1322 return 0;
4aaf448f
JQ		 1323
1324 p = get_bound_vga(chip->pci);
1325 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1326 pci_dev_put(p);
1327
128960a9
TI		 1328 if (err < 0)
1329 return err;
9a34af4a 1330 hda->vga_switcheroo_registered = 1;
246efa4a 1331
128960a9 1332 return 0;
a82d51ed
TI		 1333}
1334#else
1335#define init_vga_switcheroo(chip) /* NOP */
1336#define register_vga_switcheroo(chip) 0
8393ec4a 1337#define check_hdmi_disabled(pci) false
37a3a98e 1338#define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
a82d51ed
TI		 1339#endif /* SUPPORT_VGA_SWITCHER */
1340
1da177e4
LT		 1341/*
1342 * destructor
1343 */
2393e755 1344static void azx_free(struct azx *chip)
1da177e4 1345{
c67e2228 1346 struct pci_dev *pci = chip->pci;
a07187c9 1347 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1348 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1349
2393e755
TI		 1350 if (hda->freed)
1351 return;
1352
364aa716 1353 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228 1354 pm_runtime_get_noresume(&pci->dev);
37a3a98e 1355 chip->running = 0;
c67e2228 1356
65fcd41d
TI		 1357 azx_del_card_list(chip);
1358
9a34af4a
TI		 1359 hda->init_failed = 1; /* to be sure */
1360 complete_all(&hda->probe_wait);
f4c482a4 1361
9a34af4a 1362 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1363 if (chip->disabled && hda->probe_continued)
1364 snd_hda_unlock_devices(&chip->bus);
07f4f97d 1365 if (hda->vga_switcheroo_registered)
128960a9 1366 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1367 }
1368
a41d1224 1369 if (bus->chip_init) {
9ad593f6 1370 azx_clear_irq_pending(chip);
7833c3f8 1371 azx_stop_all_streams(chip);
1a7f60b9 1372 azx_stop_chip(chip);
1da177e4
LT		 1373 }
1374
a41d1224
TI		 1375 if (bus->irq >= 0)
1376 free_irq(bus->irq, (void*)chip);
1da177e4 1377
67908994 1378 azx_free_stream_pages(chip);
a41d1224
TI		 1379 azx_free_streams(chip);
1380 snd_hdac_bus_exit(bus);
1381
4918cdab 1382#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1383 release_firmware(chip->fw);
4918cdab 1384#endif
e454ff8e 1385 display_power(chip, false);
98d8fc6c 1386
fc18282c 1387 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
fcc88d91 1388 snd_hdac_i915_exit(bus);
1da177e4 1389
2393e755 1390 hda->freed = 1;
1da177e4
LT		 1391}
1392
a41d1224
TI		 1393static int azx_dev_disconnect(struct snd_device *device)
1394{
1395 struct azx *chip = device->device_data;
ca58f551 1396 struct hdac_bus *bus = azx_bus(chip);
a41d1224
TI		 1397
1398 chip->bus.shutdown = 1;
ca58f551
TI		 1399 cancel_work_sync(&bus->unsol_work);
1400
a41d1224
TI		 1401 return 0;
1402}
1403
a98f90fd 1404static int azx_dev_free(struct snd_device *device)
1da177e4 1405{
2393e755
TI		 1406 azx_free(device->device_data);
1407 return 0;
1da177e4
LT		 1408}
1409
8393ec4a 1410#ifdef SUPPORT_VGA_SWITCHEROO
586bc4aa
AD		 1411#ifdef CONFIG_ACPI
1412/* ATPX is in the integrated GPU's namespace */
1413static bool atpx_present(void)
1414{
1415 struct pci_dev *pdev = NULL;
1416 acpi_handle dhandle, atpx_handle;
1417 acpi_status status;
1418
8cc0991c
AD		 1419 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1420 dhandle = ACPI_HANDLE(&pdev->dev);
1421 if (dhandle) {
1422 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
10e92724 1423 if (ACPI_SUCCESS(status)) {
8cc0991c
AD		 1424 pci_dev_put(pdev);
1425 return true;
1426 }
1427 }
1428 }
1429 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
586bc4aa
AD		 1430 dhandle = ACPI_HANDLE(&pdev->dev);
1431 if (dhandle) {
1432 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
10e92724 1433 if (ACPI_SUCCESS(status)) {
586bc4aa
AD		 1434 pci_dev_put(pdev);
1435 return true;
1436 }
1437 }
586bc4aa
AD		 1438 }
1439 return false;
1440}
1441#else
1442static bool atpx_present(void)
1443{
1444 return false;
1445}
1446#endif
1447
9121947d 1448/*
2b760d88 1449 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1450 */
e23e7a14 1451static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1452{
1453 struct pci_dev *p;
1454
1455 /* check only discrete GPU */
1456 switch (pci->vendor) {
1457 case PCI_VENDOR_ID_ATI:
1458 case PCI_VENDOR_ID_AMD:
586bc4aa
AD		 1459 if (pci->devfn == 1) {
1460 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1461 pci->bus->number, 0);
1462 if (p) {
1463 /* ATPX is in the integrated GPU's ACPI namespace
1464 * rather than the dGPU's namespace. However,
1465 * the dGPU is the one who is involved in
1466 * vgaswitcheroo.
1467 */
1468 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1469 atpx_present())
1470 return p;
1471 pci_dev_put(p);
1472 }
1473 }
1474 break;
9121947d
TI		 1475 case PCI_VENDOR_ID_NVIDIA:
1476 if (pci->devfn == 1) {
1477 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1478 pci->bus->number, 0);
1479 if (p) {
b6d7b362 1480 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
9121947d
TI		 1481 return p;
1482 pci_dev_put(p);
1483 }
1484 }
1485 break;
1486 }
1487 return NULL;
1488}
1489
e23e7a14 1490static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1491{
1492 bool vga_inactive = false;
1493 struct pci_dev *p = get_bound_vga(pci);
1494
1495 if (p) {
12b78a7f 1496 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1497 vga_inactive = true;
1498 pci_dev_put(p);
1499 }
1500 return vga_inactive;
1501}
8393ec4a 1502#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1503
3372a153 1504/*
6317e5eb 1505 * allow/deny-listing for position_fix
3372a153 1506 */
a5dc05e4 1507static const struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1508 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1509 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1510 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1511 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1512 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1513 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1514 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1515 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1516 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1517 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1518 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1519 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1520 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1521 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1522 {}
1523};
1524
e23e7a14 1525static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1526{
1527 const struct snd_pci_quirk *q;
1528
c673ba1c 1529 switch (fix) {
1dac6695 1530 case POS_FIX_AUTO:
c673ba1c
TI		 1531 case POS_FIX_LPIB:
1532 case POS_FIX_POSBUF:
4cb36310 1533 case POS_FIX_VIACOMBO:
a6f2fd55 1534 case POS_FIX_COMBO:
f87e7f25 1535 case POS_FIX_SKL:
c02f77d3 1536 case POS_FIX_FIFO:
c673ba1c
TI		 1537 return fix;
1538 }
1539
c673ba1c
TI		 1540 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1541 if (q) {
4e76a883
TI		 1542 dev_info(chip->card->dev,
1543 "position_fix set to %d for device %04x:%04x\n",
1544 q->value, q->subvendor, q->subdevice);
c673ba1c 1545 return q->value;
3372a153 1546 }
bdd9ef24
DH		 1547
1548 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1549 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1550 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1551 return POS_FIX_VIACOMBO;
9477c58e 1552 }
c02f77d3
TI		 1553 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1554 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1555 return POS_FIX_FIFO;
1556 }
9477c58e 1557 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1558 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1559 return POS_FIX_LPIB;
bdd9ef24 1560 }
a4b4793f 1561 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1562 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1563 return POS_FIX_SKL;
1564 }
c673ba1c 1565 return POS_FIX_AUTO;
3372a153
TI		 1566}
1567
b6050ef6
TI		 1568static void assign_position_fix(struct azx *chip, int fix)
1569{
bf82326f 1570 static const azx_get_pos_callback_t callbacks[] = {
b6050ef6
TI		 1571 [POS_FIX_AUTO] = NULL,
1572 [POS_FIX_LPIB] = azx_get_pos_lpib,
1573 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1574 [POS_FIX_VIACOMBO] = azx_via_get_position,
1575 [POS_FIX_COMBO] = azx_get_pos_lpib,
f87e7f25 1576 [POS_FIX_SKL] = azx_get_pos_skl,
c02f77d3 1577 [POS_FIX_FIFO] = azx_get_pos_fifo,
b6050ef6
TI		 1578 };
1579
1580 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1581
1582 /* combo mode uses LPIB only for playback */
1583 if (fix == POS_FIX_COMBO)
1584 chip->get_position[1] = NULL;
1585
f87e7f25 1586 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1587 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1588 chip->get_delay[0] = chip->get_delay[1] =
1589 azx_get_delay_from_lpib;
1590 }
1591
c02f77d3
TI		 1592 if (fix == POS_FIX_FIFO)
1593 chip->get_delay[0] = chip->get_delay[1] =
1594 azx_get_delay_from_fifo;
b6050ef6
TI		 1595}
1596
669ba27a 1597/*
6317e5eb 1598 * deny-lists for probe_mask
669ba27a 1599 */
a5dc05e4 1600static const struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1601 /* Thinkpad often breaks the controller communication when accessing
1602 * to the non-working (or non-existing) modem codec slot.
1603 */
1604 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1605 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1606 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1607 /* broken BIOS */
1608 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1609 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1610 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1611 /* forced codec slots */
93574844 1612 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1613 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1614 /* WinFast VP200 H (Teradici) user reported broken communication */
1615 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1616 {}
1617};
1618
f1eaaeec
TI		 1619#define AZX_FORCE_CODEC_MASK 0x100
1620
e23e7a14 1621static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1622{
1623 const struct snd_pci_quirk *q;
1624
f1eaaeec
TI		 1625 chip->codec_probe_mask = probe_mask[dev];
1626 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1627 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1628 if (q) {
4e76a883
TI		 1629 dev_info(chip->card->dev,
1630 "probe_mask set to 0x%x for device %04x:%04x\n",
1631 q->value, q->subvendor, q->subdevice);
f1eaaeec 1632 chip->codec_probe_mask = q->value;
669ba27a
TI		 1633 }
1634 }
f1eaaeec
TI		 1635
1636 /* check forced option */
1637 if (chip->codec_probe_mask != -1 &&
1638 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1639 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1640 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1641 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1642 }
669ba27a
TI		 1643}
1644
4d8e22e0 1645/*
6317e5eb 1646 * allow/deny-list for enable_msi
4d8e22e0 1647 */
6317e5eb 1648static const struct snd_pci_quirk msi_deny_list[] = {
693e0cb0
DH		 1649 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1650 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1651 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1652 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1653 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1654 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1655 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1656 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1657 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1658 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1659 {}
1660};
1661
e23e7a14 1662static void check_msi(struct azx *chip)
4d8e22e0
TI		 1663{
1664 const struct snd_pci_quirk *q;
1665
71623855
TI		 1666 if (enable_msi >= 0) {
1667 chip->msi = !!enable_msi;
4d8e22e0 1668 return;
71623855
TI		 1669 }
1670 chip->msi = 1; /* enable MSI as default */
6317e5eb 1671 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
4d8e22e0 1672 if (q) {
4e76a883
TI		 1673 dev_info(chip->card->dev,
1674 "msi for device %04x:%04x set to %d\n",
1675 q->subvendor, q->subdevice, q->value);
4d8e22e0 1676 chip->msi = q->value;
80c43ed7
TI		 1677 return;
1678 }
1679
1680 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1681 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1682 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1683 chip->msi = 0;
4d8e22e0
TI		 1684 }
1685}
1686
a1585d76 1687/* check the snoop mode availability */
e23e7a14 1688static void azx_check_snoop_available(struct azx *chip)
a1585d76 1689{
7c732015 1690 int snoop = hda_snoop;
a1585d76 1691
7c732015
TI		 1692 if (snoop >= 0) {
1693 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1694 snoop ? "snoop" : "non-snoop");
1695 chip->snoop = snoop;
78c9be61 1696 chip->uc_buffer = !snoop;
7c732015
TI		 1697 return;
1698 }
1699
1700 snoop = true;
37e661ee
TI		 1701 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1702 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1703 /* force to non-snoop mode for a new VIA controller
1704 * when BIOS is set
1705 */
7c732015
TI		 1706 u8 val;
1707 pci_read_config_byte(chip->pci, 0x42, &val);
af52f998
DW		 1708 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1709 chip->pci->revision == 0x20))
7c732015 1710 snoop = false;
a1585d76
TI		 1711 }
1712
37e661ee
TI		 1713 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1714 snoop = false;
1715
7c732015 1716 chip->snoop = snoop;
78c9be61 1717 if (!snoop) {
7c732015 1718 dev_info(chip->card->dev, "Force to non-snoop mode\n");
78c9be61
TI		 1719 /* C-Media requires non-cached pages only for CORB/RIRB */
1720 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1721 chip->uc_buffer = true;
1722 }
a1585d76 1723}
669ba27a 1724
99a2008d
WX		 1725static void azx_probe_work(struct work_struct *work)
1726{
c0f1886d 1727 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
9a34af4a 1728 azx_probe_continue(&hda->chip);
99a2008d 1729}
99a2008d 1730
4f0189be
TI		 1731static int default_bdl_pos_adj(struct azx *chip)
1732{
2cf721db
TI		 1733 /* some exceptions: Atoms seem problematic with value 1 */
1734 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1735 switch (chip->pci->device) {
1736 case 0x0f04: /* Baytrail */
1737 case 0x2284: /* Braswell */
1738 return 32;
1739 }
1740 }
1741
4f0189be
TI		 1742 switch (chip->driver_type) {
1743 case AZX_DRIVER_ICH:
1744 case AZX_DRIVER_PCH:
1745 return 1;
1746 default:
1747 return 32;
1748 }
1749}
1750
1da177e4
LT		 1751/*
1752 * constructor
1753 */
a43ff5ba
TI		 1754static const struct hda_controller_ops pci_hda_ops;
1755
e23e7a14
BP		 1756static int azx_create(struct snd_card *card, struct pci_dev *pci,
1757 int dev, unsigned int driver_caps,
1758 struct azx **rchip)
1da177e4 1759{
41f394a8 1760 static const struct snd_device_ops ops = {
a41d1224 1761 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1762 .dev_free = azx_dev_free,
1763 };
a07187c9 1764 struct hda_intel *hda;
a82d51ed
TI		 1765 struct azx *chip;
1766 int err;
1da177e4
LT		 1767
1768 *rchip = NULL;
bcd72003 1769
3fcaf24e 1770 err = pcim_enable_device(pci);
927fc866 1771 if (err < 0)
1da177e4
LT		 1772 return err;
1773
2393e755 1774 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
3fcaf24e 1775 if (!hda)
1da177e4 1776 return -ENOMEM;
1da177e4 1777
a07187c9 1778 chip = &hda->chip;
62932df8 1779 mutex_init(&chip->open_mutex);
1da177e4
LT		 1780 chip->card = card;
1781 chip->pci = pci;
a43ff5ba 1782 chip->ops = &pci_hda_ops;
9477c58e
TI		 1783 chip->driver_caps = driver_caps;
1784 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1785 check_msi(chip);
555e219f 1786 chip->dev_index = dev;
3a182c84
TI		 1787 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1788 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
01b65bfb 1789 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1790 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1791 INIT_LIST_HEAD(&hda->list);
a82d51ed 1792 init_vga_switcheroo(chip);
9a34af4a 1793 init_completion(&hda->probe_wait);
1da177e4 1794
b6050ef6 1795 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1796
5aba4f8e 1797 check_probe_mask(chip, dev);
3372a153 1798
41438f13
TI		 1799 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1800 chip->fallback_to_single_cmd = 1;
1801 else /* explicitly set to single_cmd or not */
1802 chip->single_cmd = single_cmd;
1803
a1585d76 1804 azx_check_snoop_available(chip);
c74db86b 1805
4f0189be
TI		 1806 if (bdl_pos_adj[dev] < 0)
1807 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1808 else
1809 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1810
19abfefd 1811 err = azx_bus_init(chip, model[dev]);
3fcaf24e 1812 if (err < 0)
a41d1224 1813 return err;
a41d1224 1814
619a1f19
TI		 1815 /* use the non-cached pages in non-snoop mode */
1816 if (!azx_snoop(chip))
58a95dfa 1817 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC;
619a1f19 1818
7d9a1808
TI		 1819 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1820 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
5f2cb361 1821 chip->bus.core.needs_damn_long_delay = 1;
7d9a1808
TI		 1822 }
1823
a82d51ed
TI		 1824 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1825 if (err < 0) {
4e76a883 1826 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1827 azx_free(chip);
1828 return err;
1829 }
1830
99a2008d 1831 /* continue probing in work context as may trigger request module */
c0f1886d 1832 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1833
a82d51ed 1834 *rchip = chip;
99a2008d 1835
a82d51ed
TI		 1836 return 0;
1837}
1838
48c8b0eb 1839static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1840{
1841 int dev = chip->dev_index;
1842 struct pci_dev *pci = chip->pci;
1843 struct snd_card *card = chip->card;
a41d1224 1844 struct hdac_bus *bus = azx_bus(chip);
67908994 1845 int err;
a82d51ed 1846 unsigned short gcap;
413cbf46 1847 unsigned int dma_bits = 64;
a82d51ed 1848
07e4ca50
TI		 1849#if BITS_PER_LONG != 64
1850 /* Fix up base address on ULI M5461 */
1851 if (chip->driver_type == AZX_DRIVER_ULI) {
1852 u16 tmp3;
1853 pci_read_config_word(pci, 0x40, &tmp3);
1854 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1855 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1856 }
1857#endif
1858
3fcaf24e 1859 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");
a82d51ed 1860 if (err < 0)
1da177e4 1861 return err;
1da177e4 1862
a41d1224 1863 bus->addr = pci_resource_start(pci, 0);
3fcaf24e 1864 bus->remap_addr = pcim_iomap_table(pci)[0];
1da177e4 1865
a4b4793f 1866 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1867 snd_hdac_bus_parse_capabilities(bus);
1868
1869 /*
1870 * Some Intel CPUs has always running timer (ART) feature and
1871 * controller may have Global time sync reporting capability, so
1872 * check both of these before declaring synchronized time reporting
1873 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1874 */
1875 chip->gts_present = false;
1876
1877#ifdef CONFIG_X86
1878 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1879 chip->gts_present = true;
1880#endif
1881
db79afa1
BH		 1882 if (chip->msi) {
1883 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1884 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1885 pci->no_64bit_msi = true;
1886 }
68e7fffc
TI		 1887 if (pci_enable_msi(pci) < 0)
1888 chip->msi = 0;
db79afa1 1889 }
7376d013 1890
1da177e4 1891 pci_set_master(pci);
1da177e4 1892
bcd72003 1893 gcap = azx_readw(chip, GCAP);
4e76a883 1894 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1895
413cbf46
TI		 1896 /* AMD devices support 40 or 48bit DMA, take the safe one */
1897 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1898 dma_bits = 40;
1899
dc4c2e6b 1900 /* disable SB600 64bit support for safety */
9477c58e 1901 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1902 struct pci_dev *p_smbus;
413cbf46 1903 dma_bits = 40;
dc4c2e6b
AB		 1904 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1905 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1906 NULL);
1907 if (p_smbus) {
1908 if (p_smbus->revision < 0x30)
fb1d8ac2 1909 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1910 pci_dev_put(p_smbus);
1911 }
1912 }
09240cf4 1913
3ab7511e
AB		 1914 /* NVidia hardware normally only supports up to 40 bits of DMA */
1915 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1916 dma_bits = 40;
1917
9477c58e
TI		 1918 /* disable 64bit DMA address on some devices */
1919 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1920 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1921 gcap &= ~AZX_GCAP_64OK;
9477c58e 1922 }
396087ea 1923
2ae66c26 1924 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1925 if (align_buffer_size >= 0)
1926 chip->align_buffer_size = !!align_buffer_size;
1927 else {
103884a3 1928 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1929 chip->align_buffer_size = 0;
7bfe059e
TI		 1930 else
1931 chip->align_buffer_size = 1;
1932 }
2ae66c26 1933
cf7aaca8 1934 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1935 if (!(gcap & AZX_GCAP_64OK))
1936 dma_bits = 32;
669f65ea
TI		 1937 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1938 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
cf7aaca8 1939
8b6ed8e7
TI		 1940 /* read number of streams from GCAP register instead of using
1941 * hardcoded value
1942 */
1943 chip->capture_streams = (gcap >> 8) & 0x0f;
1944 chip->playback_streams = (gcap >> 12) & 0x0f;
1945 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1946 /* gcap didn't give any info, switching to old method */
1947
1948 switch (chip->driver_type) {
1949 case AZX_DRIVER_ULI:
1950 chip->playback_streams = ULI_NUM_PLAYBACK;
1951 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1952 break;
1953 case AZX_DRIVER_ATIHDMI:
1815b34a 1954 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1955 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1956 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1957 break;
c4da29ca 1958 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1959 default:
1960 chip->playback_streams = ICH6_NUM_PLAYBACK;
1961 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1962 break;
1963 }
07e4ca50 1964 }
8b6ed8e7
TI		 1965 chip->capture_index_offset = 0;
1966 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1967 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1968
df56c3db
JK		 1969 /* sanity check for the SDxCTL.STRM field overflow */
1970 if (chip->num_streams > 15 &&
1971 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1972 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1973 "forcing separate stream tags", chip->num_streams);
1974 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1975 }
1976
a41d1224
TI		 1977 /* initialize streams */
1978 err = azx_init_streams(chip);
81740861 1979 if (err < 0)
a82d51ed 1980 return err;
1da177e4 1981
a41d1224
TI		 1982 err = azx_alloc_stream_pages(chip);
1983 if (err < 0)
1984 return err;
1da177e4
LT		 1985
1986 /* initialize chip */
cb53c626 1987 azx_init_pci(chip);
e4d9e513 1988
e454ff8e 1989 snd_hdac_i915_set_bclk(bus);
e4d9e513 1990
0a673521 1991 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1992
1993 /* codec detection */
a41d1224 1994 if (!azx_bus(chip)->codec_mask) {
4e76a883 1995 dev_err(card->dev, "no codecs found!\n");
9479e75f 1996 /* keep running the rest for the runtime PM */
1da177e4
LT		 1997 }
1998
f495222e
TI		 1999 if (azx_acquire_irq(chip, 0) < 0)
2000 return -EBUSY;
2001
07e4ca50 2002 strcpy(card->driver, "HDA-Intel");
75b1a8f9 2003 strscpy(card->shortname, driver_short_names[chip->driver_type],
18cb7109
TI		 2004 sizeof(card->shortname));
2005 snprintf(card->longname, sizeof(card->longname),
2006 "%s at 0x%lx irq %i",
a41d1224 2007 card->shortname, bus->addr, bus->irq);
07e4ca50 2008
1da177e4 2009 return 0;
1da177e4
LT		 2010}
2011
97c6a3d1 2012#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 2013/* callback from request_firmware_nowait() */
2014static void azx_firmware_cb(const struct firmware *fw, void *context)
2015{
2016 struct snd_card *card = context;
2017 struct azx *chip = card->private_data;
5cb543db 2018
25faa4bd
TI		 2019 if (fw)
2020 chip->fw = fw;
2021 else
2022 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
5cb543db
TI		 2023 if (!chip->disabled) {
2024 /* continue probing */
25faa4bd 2025 azx_probe_continue(chip);
5cb543db 2026 }
5cb543db 2027}
97c6a3d1 2028#endif
5cb543db 2029
f46ea609
DR		 2030static int disable_msi_reset_irq(struct azx *chip)
2031{
a41d1224 2032 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 2033 int err;
2034
a41d1224
TI		 2035 free_irq(bus->irq, chip);
2036 bus->irq = -1;
f36da940 2037 chip->card->sync_irq = -1;
f46ea609
DR		 2038 pci_disable_msi(chip->pci);
2039 chip->msi = 0;
2040 err = azx_acquire_irq(chip, 1);
2041 if (err < 0)
2042 return err;
2043
2044 return 0;
2045}
2046
6317e5eb 2047/* Denylist for skipping the whole probe:
3c6fd1f0
TI		 2048 * some HD-audio PCI entries are exposed without any codecs, and such devices
2049 * should be ignored from the beginning.
2050 */
6317e5eb 2051static const struct pci_device_id driver_denylist[] = {
977dfef4
TI		 2052 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2053 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2054 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
3c6fd1f0
TI		 2055 {}
2056};
2057
a43ff5ba
TI		 2058static const struct hda_controller_ops pci_hda_ops = {
2059 .disable_msi_reset_irq = disable_msi_reset_irq,
7ca954a8 2060 .position_check = azx_position_check,
40830813
DR		 2061};
2062
e23e7a14
BP		 2063static int azx_probe(struct pci_dev *pci,
2064 const struct pci_device_id *pci_id)
1da177e4 2065{
5aba4f8e 2066 static int dev;
a98f90fd 2067 struct snd_card *card;
9a34af4a 2068 struct hda_intel *hda;
a98f90fd 2069 struct azx *chip;
aad730d0 2070 bool schedule_probe;
927fc866 2071 int err;
1da177e4 2072
6317e5eb
TI		 2073 if (pci_match_id(driver_denylist, pci)) {
2074 dev_info(&pci->dev, "Skipping the device on the denylist\n");
3c6fd1f0
TI		 2075 return -ENODEV;
2076 }
2077
5aba4f8e
TI		 2078 if (dev >= SNDRV_CARDS)
2079 return -ENODEV;
2080 if (!enable[dev]) {
2081 dev++;
2082 return -ENOENT;
2083 }
2084
82d9d54a
JK		 2085 /*
2086 * stop probe if another Intel's DSP driver should be activated
2087 */
7fba6aea 2088 if (dmic_detect) {
82d9d54a 2089 err = snd_intel_dsp_driver_probe(pci);
ae035947
PLB		 2090 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2091 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
82d9d54a 2092 return -ENODEV;
ae035947 2093 }
7fba6aea
TI		 2094 } else {
2095 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
82d9d54a
JK		 2096 }
2097
60c5772b
TI		 2098 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2099 0, &card);
e58de7ba 2100 if (err < 0) {
4e76a883 2101 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2102 return err;
1da177e4
LT		 2103 }
2104
a43ff5ba 2105 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2106 if (err < 0)
2107 goto out_free;
421a1252 2108 card->private_data = chip;
9a34af4a 2109 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2110
2111 pci_set_drvdata(pci, card);
2112
2113 err = register_vga_switcheroo(chip);
2114 if (err < 0) {
2b760d88 2115 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2116 goto out_free;
2117 }
2118
2119 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2120 dev_info(card->dev, "VGA controller is disabled\n");
2121 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2122 chip->disabled = true;
2123 }
2124
aad730d0 2125 schedule_probe = !chip->disabled;
1da177e4 2126
4918cdab
TI		 2127#ifdef CONFIG_SND_HDA_PATCH_LOADER
2128 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2129 dev_info(card->dev, "Applying patch firmware '%s'\n",
2130 patch[dev]);
5cb543db
TI		 2131 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2132 &pci->dev, GFP_KERNEL, card,
2133 azx_firmware_cb);
4918cdab
TI		 2134 if (err < 0)
2135 goto out_free;
aad730d0 2136 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2137 }
2138#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2139
aad730d0 2140#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2141 if (CONTROLLER_IN_GPU(pci))
2142 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2143#endif
99a2008d 2144
aad730d0 2145 if (schedule_probe)
c0f1886d 2146 schedule_delayed_work(&hda->probe_work, 0);
a82d51ed 2147
a82d51ed 2148 dev++;
88d071fc 2149 if (chip->disabled)
9a34af4a 2150 complete_all(&hda->probe_wait);
a82d51ed
TI		 2151 return 0;
2152
2153out_free:
2154 snd_card_free(card);
2155 return err;
2156}
2157
1ba8f9d3
HG		 2158#ifdef CONFIG_PM
2159/* On some boards setting power_save to a non 0 value leads to clicking /
2160 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2161 * figure out how to avoid these sounds, but that is not always feasible.
2162 * So we keep a list of devices where we disable powersaving as its known
2163 * to causes problems on these devices.
2164 */
6317e5eb 2165static const struct snd_pci_quirk power_save_denylist[] = {
1ba8f9d3 2166 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
8e82a728 2167 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
1ba8f9d3 2168 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
39070a98
HG		 2169 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2170 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
45e5fbc2
HG		 2171 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2172 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
1ba8f9d3 2173 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
38d9c12c 2174 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
5cb6b5fc
HG		 2175 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2176 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
38d9c12c
HG		 2177 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2178 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
5cb6b5fc
HG		 2179 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2180 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
f91f1806
HG		 2181 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2182 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
cae30527
HW		 2183 /* https://bugs.launchpad.net/bugs/1821663 */
2184 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
dd6dd536
HG		 2185 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2186 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
1ba8f9d3
HG		 2187 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2188 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
721f1e6c
JK		 2189 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2190 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2191 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2192 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
cae30527
HW		 2193 /* https://bugs.launchpad.net/bugs/1821663 */
2194 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
1ba8f9d3
HG		 2195 {}
2196};
2197#endif /* CONFIG_PM */
2198
37a3a98e
TI		 2199static void set_default_power_save(struct azx *chip)
2200{
2201 int val = power_save;
2202
2203#ifdef CONFIG_PM
2204 if (pm_blacklist) {
2205 const struct snd_pci_quirk *q;
2206
6317e5eb 2207 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
37a3a98e 2208 if (q && val) {
6317e5eb 2209 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
37a3a98e
TI		 2210 q->subvendor, q->subdevice);
2211 val = 0;
2212 }
2213 }
2214#endif /* CONFIG_PM */
2215 snd_hda_set_power_save(&chip->bus, val * 1000);
2216}
2217
e62a42ae 2218/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
bf82326f 2219static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
e62a42ae
DR		 2220 [AZX_DRIVER_NVIDIA] = 8,
2221 [AZX_DRIVER_TERA] = 1,
2222};
2223
48c8b0eb 2224static int azx_probe_continue(struct azx *chip)
a82d51ed 2225{
9a34af4a 2226 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2227 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2228 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2229 int dev = chip->dev_index;
2230 int err;
2231
c0f1886d
TI		 2232 if (chip->disabled || hda->init_failed)
2233 return -EIO;
2234 if (hda->probe_retry)
2235 goto probe_retry;
2236
305a0ade 2237 to_hda_bus(bus)->bus_probing = 1;
a41d1224 2238 hda->probe_continued = 1;
795614dd 2239
fcc88d91 2240 /* bind with i915 if needed */
dba9b7b6 2241 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
98d8fc6c 2242 err = snd_hdac_i915_init(bus);
535115b5
TI		 2243 if (err < 0) {
2244 /* if the controller is bound only with HDMI/DP
2245 * (for HSW and BDW), we need to abort the probe;
2246 * for other chips, still continue probing as other
2247 * codecs can be on the same link.
2248 */
bed2e98e
TI		 2249 if (CONTROLLER_IN_GPU(pci)) {
2250 dev_err(chip->card->dev,
2251 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2252 goto out_free;
fcc88d91
TI		 2253 } else {
2254 /* don't bother any longer */
e454ff8e 2255 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
fcc88d91 2256 }
535115b5 2257 }
e454ff8e
TI		 2258
2259 /* HSW/BDW controllers need this power */
2260 if (CONTROLLER_IN_GPU(pci))
62c2b4be 2261 hda->need_i915_power = true;
fcc88d91
TI		 2262 }
2263
2264 /* Request display power well for the HDA controller or codec. For
2265 * Haswell/Broadwell, both the display HDA controller and codec need
2266 * this power. For other platforms, like Baytrail/Braswell, only the
2267 * display codec needs the power and it can be released after probe.
2268 */
4f799e73 2269 display_power(chip, true);
99a2008d 2270
5c90680e
TI		 2271 err = azx_first_init(chip);
2272 if (err < 0)
2273 goto out_free;
2274
2dca0bba
JK		 2275#ifdef CONFIG_SND_HDA_INPUT_BEEP
2276 chip->beep_mode = beep_mode[dev];
2277#endif
2278
1da177e4 2279 /* create codec instances */
9479e75f
TI		 2280 if (bus->codec_mask) {
2281 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2282 if (err < 0)
2283 goto out_free;
2284 }
96d2bd6e 2285
4ea6fbc8 2286#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2287 if (chip->fw) {
a41d1224 2288 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2289 chip->fw->data);
4ea6fbc8
TI		 2290 if (err < 0)
2291 goto out_free;
e39ae856 2292#ifndef CONFIG_PM
4918cdab
TI		 2293 release_firmware(chip->fw); /* no longer needed */
2294 chip->fw = NULL;
e39ae856 2295#endif
4ea6fbc8
TI		 2296 }
2297#endif
c0f1886d
TI		 2298
2299 probe_retry:
9479e75f 2300 if (bus->codec_mask && !(probe_only[dev] & 1)) {
a1e21c90 2301 err = azx_codec_configure(chip);
c0f1886d
TI		 2302 if (err) {
2303 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2304 ++hda->probe_retry < 60) {
2305 schedule_delayed_work(&hda->probe_work,
2306 msecs_to_jiffies(1000));
2307 return 0; /* keep things up */
2308 }
2309 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
a1e21c90 2310 goto out_free;
c0f1886d 2311 }
a1e21c90 2312 }
1da177e4 2313
a82d51ed 2314 err = snd_card_register(chip->card);
41dda0fd
WF		 2315 if (err < 0)
2316 goto out_free;
1da177e4 2317
37a3a98e
TI		 2318 setup_vga_switcheroo_runtime_pm(chip);
2319
cb53c626 2320 chip->running = 1;
65fcd41d 2321 azx_add_card_list(chip);
07f4f97d 2322
37a3a98e 2323 set_default_power_save(chip);
07f4f97d 2324
3ba21113
RS		 2325 if (azx_has_pm_runtime(chip)) {
2326 pm_runtime_use_autosuspend(&pci->dev);
9fc149c3 2327 pm_runtime_allow(&pci->dev);
30ff5957 2328 pm_runtime_put_autosuspend(&pci->dev);
3ba21113 2329 }
1da177e4 2330
41dda0fd 2331out_free:
2393e755
TI		 2332 if (err < 0) {
2333 azx_free(chip);
2334 return err;
2335 }
2336
2337 if (!hda->need_i915_power)
029d92c2 2338 display_power(chip, false);
9a34af4a 2339 complete_all(&hda->probe_wait);
305a0ade 2340 to_hda_bus(bus)->bus_probing = 0;
c0f1886d 2341 hda->probe_retry = 0;
2393e755 2342 return 0;
1da177e4
LT		 2343}
2344
e23e7a14 2345static void azx_remove(struct pci_dev *pci)
1da177e4 2346{
9121947d 2347 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2348 struct azx *chip;
2349 struct hda_intel *hda;
2350
2351 if (card) {
0b8c8219 2352 /* cancel the pending probing work */
991f86d7
TI		 2353 chip = card->private_data;
2354 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2355 /* FIXME: below is an ugly workaround.
2356 * Both device_release_driver() and driver_probe_device()
2357 * take *both* the device's and its parent's lock before
2358 * calling the remove() and probe() callbacks. The codec
2359 * probe takes the locks of both the codec itself and its
2360 * parent, i.e. the PCI controller dev. Meanwhile, when
2361 * the PCI controller is unbound, it takes its lock, too
2362 * ==> ouch, a deadlock!
2363 * As a workaround, we unlock temporarily here the controller
2364 * device during cancel_work_sync() call.
2365 */
2366 device_unlock(&pci->dev);
c0f1886d 2367 cancel_delayed_work_sync(&hda->probe_work);
ab949d51 2368 device_lock(&pci->dev);
b8dfc462 2369
9121947d 2370 snd_card_free(card);
991f86d7 2371 }
1da177e4
LT		 2372}
2373
b2a0bafa
TI		 2374static void azx_shutdown(struct pci_dev *pci)
2375{
2376 struct snd_card *card = pci_get_drvdata(pci);
2377 struct azx *chip;
2378
2379 if (!card)
2380 return;
2381 chip = card->private_data;
2382 if (chip && chip->running)
6f445784 2383 __azx_shutdown_chip(chip, true);
b2a0bafa
TI		 2384}
2385
1da177e4 2386/* PCI IDs */
6f51f6cf 2387static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2388 /* CPT */
9477c58e 2389 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2390 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2391 /* PBG */
9477c58e 2392 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2393 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2394 /* Panther Point */
9477c58e 2395 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2396 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2397 /* Lynx Point */
2398 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2399 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2400 /* 9 Series */
2401 { PCI_DEVICE(0x8086, 0x8ca0),
2402 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2403 /* Wellsburg */
2404 { PCI_DEVICE(0x8086, 0x8d20),
2405 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2406 { PCI_DEVICE(0x8086, 0x8d21),
2407 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2408 /* Lewisburg */
2409 { PCI_DEVICE(0x8086, 0xa1f0),
e7480b34 2410 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
5cf92c8b 2411 { PCI_DEVICE(0x8086, 0xa270),
e7480b34 2412 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
144dad99
JR		 2413 /* Lynx Point-LP */
2414 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2415 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2416 /* Lynx Point-LP */
2417 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2418 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2419 /* Wildcat Point-LP */
2420 { PCI_DEVICE(0x8086, 0x9ca0),
2421 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2422 /* Sunrise Point */
2423 { PCI_DEVICE(0x8086, 0xa170),
a4b4793f 2424 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2425 /* Sunrise Point-LP */
2426 { PCI_DEVICE(0x8086, 0x9d70),
3e9ad24b 2427 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2428 /* Kabylake */
2429 { PCI_DEVICE(0x8086, 0xa171),
a4b4793f 2430 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2431 /* Kabylake-LP */
2432 { PCI_DEVICE(0x8086, 0x9d71),
3e9ad24b 2433 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2434 /* Kabylake-H */
2435 { PCI_DEVICE(0x8086, 0xa2f0),
a4b4793f 2436 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
e79b0006
MD		 2437 /* Coffelake */
2438 { PCI_DEVICE(0x8086, 0xa348),
3e9ad24b 2439 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2357f6f0
GS		 2440 /* Cannonlake */
2441 { PCI_DEVICE(0x8086, 0x9dc8),
3e9ad24b 2442 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
d4c2ccdb
PLB		 2443 /* CometLake-LP */
2444 { PCI_DEVICE(0x8086, 0x02C8),
2445 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2446 /* CometLake-H */
2447 { PCI_DEVICE(0x8086, 0x06C8),
2448 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
0d3070f5
KV		 2449 { PCI_DEVICE(0x8086, 0xf1c8),
2450 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
b73a5854
CC		 2451 /* CometLake-S */
2452 { PCI_DEVICE(0x8086, 0xa3f0),
2453 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
f84d3a1e
KCH		 2454 /* CometLake-R */
2455 { PCI_DEVICE(0x8086, 0xf0c8),
2456 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
491f8331
GS		 2457 /* Icelake */
2458 { PCI_DEVICE(0x8086, 0x34c8),
3e9ad24b 2459 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
d50313a5
PLB		 2460 /* Icelake-H */
2461 { PCI_DEVICE(0x8086, 0x3dc8),
2462 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
4750c212
PX		 2463 /* Jasperlake */
2464 { PCI_DEVICE(0x8086, 0x38c8),
2465 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
78be2228
YZ		 2466 { PCI_DEVICE(0x8086, 0x4dc8),
2467 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
4750c212
PX		 2468 /* Tigerlake */
2469 { PCI_DEVICE(0x8086, 0xa0c8),
2470 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
d50313a5
PLB		 2471 /* Tigerlake-H */
2472 { PCI_DEVICE(0x8086, 0x43c8),
2473 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
69b08bdf
KV		 2474 /* DG1 */
2475 { PCI_DEVICE(0x8086, 0x490d),
2476 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
d78359b2
KV		 2477 /* Alderlake-S */
2478 { PCI_DEVICE(0x8086, 0x7ad0),
2479 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
5e941fc0
KV		 2480 /* Alderlake-P */
2481 { PCI_DEVICE(0x8086, 0x51c8),
2482 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
4ad7935d
KV		 2483 /* Alderlake-M */
2484 { PCI_DEVICE(0x8086, 0x51cc),
2485 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
f94287b6
LPS		 2486 /* Elkhart Lake */
2487 { PCI_DEVICE(0x8086, 0x4b55),
2488 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
d50313a5
PLB		 2489 { PCI_DEVICE(0x8086, 0x4b58),
2490 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
c87693da
LH		 2491 /* Broxton-P(Apollolake) */
2492 { PCI_DEVICE(0x8086, 0x5a98),
3e9ad24b 2493 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2494 /* Broxton-T */
2495 { PCI_DEVICE(0x8086, 0x1a98),
a4b4793f 2496 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
44b46d73
VK		 2497 /* Gemini-Lake */
2498 { PCI_DEVICE(0x8086, 0x3198),
3e9ad24b 2499 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2500 /* Haswell */
4a7c516b 2501 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2502 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2503 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2504 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2505 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2506 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2507 /* Broadwell */
2508 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2509 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2510 /* 5 Series/3400 */
2511 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2512 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2513 /* Poulsbo */
9477c58e 2514 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2515 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2516 /* Oaktrail */
09904b95 2517 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2518 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2519 /* BayTrail */
2520 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2521 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2522 /* Braswell */
2523 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2524 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2525 /* ICH6 */
8b0bd226 2526 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2527 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2528 /* ICH7 */
8b0bd226 2529 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2530 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2531 /* ESB2 */
8b0bd226 2532 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2533 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2534 /* ICH8 */
8b0bd226 2535 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2536 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2537 /* ICH9 */
8b0bd226 2538 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2539 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2540 /* ICH9 */
8b0bd226 2541 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2542 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2543 /* ICH10 */
8b0bd226 2544 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2545 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2546 /* ICH10 */
8b0bd226 2547 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2548 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2549 /* Generic Intel */
2550 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2551 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2552 .class_mask = 0xffffff,
103884a3 2553 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2554 /* ATI SB 450/600/700/800/900 */
2555 { PCI_DEVICE(0x1002, 0x437b),
2556 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2557 { PCI_DEVICE(0x1002, 0x4383),
2558 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2559 /* AMD Hudson */
2560 { PCI_DEVICE(0x1022, 0x780d),
2561 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
c02f77d3
TI		 2562 /* AMD, X370 & co */
2563 { PCI_DEVICE(0x1022, 0x1457),
2564 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
de768ce4
TI		 2565 /* AMD, X570 & co */
2566 { PCI_DEVICE(0x1022, 0x1487),
2567 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
3deef52c
KHF		 2568 /* AMD Stoney */
2569 { PCI_DEVICE(0x1022, 0x157a),
2570 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2571 AZX_DCAPS_PM_RUNTIME },
9ceace3c
VM		 2572 /* AMD Raven */
2573 { PCI_DEVICE(0x1022, 0x15e3),
d2c63b7d 2574 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
87218e9c 2575 /* ATI HDMI */
fd48331f 2576 { PCI_DEVICE(0x1002, 0x0002),
20c7842e
AD		 2577 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2578 AZX_DCAPS_PM_RUNTIME },
650474fb
AD		 2579 { PCI_DEVICE(0x1002, 0x1308),
2580 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2581 { PCI_DEVICE(0x1002, 0x157a),
2582 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
d716fb03
AB		 2583 { PCI_DEVICE(0x1002, 0x15b3),
2584 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2585 { PCI_DEVICE(0x1002, 0x793b),
2586 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2587 { PCI_DEVICE(0x1002, 0x7919),
2588 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2589 { PCI_DEVICE(0x1002, 0x960f),
2590 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2591 { PCI_DEVICE(0x1002, 0x970f),
2592 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2593 { PCI_DEVICE(0x1002, 0x9840),
2594 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2595 { PCI_DEVICE(0x1002, 0xaa00),
2596 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2597 { PCI_DEVICE(0x1002, 0xaa08),
2598 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2599 { PCI_DEVICE(0x1002, 0xaa10),
2600 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2601 { PCI_DEVICE(0x1002, 0xaa18),
2602 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2603 { PCI_DEVICE(0x1002, 0xaa20),
2604 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2605 { PCI_DEVICE(0x1002, 0xaa28),
2606 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2607 { PCI_DEVICE(0x1002, 0xaa30),
2608 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2609 { PCI_DEVICE(0x1002, 0xaa38),
2610 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2611 { PCI_DEVICE(0x1002, 0xaa40),
2612 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2613 { PCI_DEVICE(0x1002, 0xaa48),
2614 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2615 { PCI_DEVICE(0x1002, 0xaa50),
2616 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2617 { PCI_DEVICE(0x1002, 0xaa58),
2618 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2619 { PCI_DEVICE(0x1002, 0xaa60),
2620 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2621 { PCI_DEVICE(0x1002, 0xaa68),
2622 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2623 { PCI_DEVICE(0x1002, 0xaa80),
2624 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2625 { PCI_DEVICE(0x1002, 0xaa88),
2626 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2627 { PCI_DEVICE(0x1002, 0xaa90),
2628 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2629 { PCI_DEVICE(0x1002, 0xaa98),
2630 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2631 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2632 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2633 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2634 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2635 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2636 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2637 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2638 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d 2639 { PCI_DEVICE(0x1002, 0xaac0),
20c7842e
AD		 2640 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2641 AZX_DCAPS_PM_RUNTIME },
0fa372b6 2642 { PCI_DEVICE(0x1002, 0xaac8),
20c7842e
AD		 2643 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2644 AZX_DCAPS_PM_RUNTIME },
5022813d 2645 { PCI_DEVICE(0x1002, 0xaad8),
73b1422b
AD		 2646 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2647 AZX_DCAPS_PM_RUNTIME },
8eb22214 2648 { PCI_DEVICE(0x1002, 0xaae0),
73b1422b
AD		 2649 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2650 AZX_DCAPS_PM_RUNTIME },
2651 { PCI_DEVICE(0x1002, 0xaae8),
2652 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2653 AZX_DCAPS_PM_RUNTIME },
8eb22214 2654 { PCI_DEVICE(0x1002, 0xaaf0),
73b1422b
AD		 2655 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2656 AZX_DCAPS_PM_RUNTIME },
8d68a872 2657 { PCI_DEVICE(0x1002, 0xaaf8),
73b1422b
AD		 2658 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2659 AZX_DCAPS_PM_RUNTIME },
8d68a872 2660 { PCI_DEVICE(0x1002, 0xab00),
73b1422b
AD		 2661 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2662 AZX_DCAPS_PM_RUNTIME },
8d68a872 2663 { PCI_DEVICE(0x1002, 0xab08),
73b1422b
AD		 2664 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2665 AZX_DCAPS_PM_RUNTIME },
8d68a872 2666 { PCI_DEVICE(0x1002, 0xab10),
73b1422b
AD		 2667 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2668 AZX_DCAPS_PM_RUNTIME },
8d68a872 2669 { PCI_DEVICE(0x1002, 0xab18),
73b1422b
AD		 2670 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2671 AZX_DCAPS_PM_RUNTIME },
8d68a872 2672 { PCI_DEVICE(0x1002, 0xab20),
73b1422b 2673 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
27a7c670
HW		 2674 AZX_DCAPS_PM_RUNTIME },
2675 { PCI_DEVICE(0x1002, 0xab28),
2676 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
73b1422b 2677 AZX_DCAPS_PM_RUNTIME },
8d68a872 2678 { PCI_DEVICE(0x1002, 0xab38),
73b1422b
AD		 2679 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2680 AZX_DCAPS_PM_RUNTIME },
87218e9c 2681 /* VIA VT8251/VT8237A */
26f05717 2682 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2683 /* VIA GFX VT7122/VX900 */
2684 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2685 /* VIA GFX VT6122/VX11 */
2686 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2687 /* SIS966 */
2688 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2689 /* ULI M5461 */
2690 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2691 /* NVIDIA MCP */
0c2fd1bf
TI		 2692 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2693 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2694 .class_mask = 0xffffff,
9477c58e 2695 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2696 /* Teradici */
9477c58e
TI		 2697 { PCI_DEVICE(0x6549, 0x1200),
2698 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2699 { PCI_DEVICE(0x6549, 0x2200),
2700 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2701 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2702 /* CTHDA chips */
2703 { PCI_DEVICE(0x1102, 0x0010),
2704 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2705 { PCI_DEVICE(0x1102, 0x0012),
2706 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2707#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2708 /* the following entry conflicts with snd-ctxfi driver,
2709 * as ctxfi driver mutates from HD-audio to native mode with
2710 * a special command sequence.
2711 */
4e01f54b
TI		 2712 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2713 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2714 .class_mask = 0xffffff,
9477c58e 2715 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2716 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2717#else
2718 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2719 { PCI_DEVICE(0x1102, 0x0009),
2720 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2721 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2722#endif
c563f473
TI		 2723 /* CM8888 */
2724 { PCI_DEVICE(0x13f6, 0x5011),
2725 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2726 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2727 /* Vortex86MX */
2728 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2729 /* VMware HDAudio */
2730 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2731 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2732 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2733 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2734 .class_mask = 0xffffff,
9477c58e 2735 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2736 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2737 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2738 .class_mask = 0xffffff,
9477c58e 2739 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
b6fcab14
TW		 2740 /* Zhaoxin */
2741 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
1da177e4
LT		 2742 { 0, }
2743};
2744MODULE_DEVICE_TABLE(pci, azx_ids);
2745
2746/* pci_driver definition */
e9f66d9b 2747static struct pci_driver azx_driver = {
3733e424 2748 .name = KBUILD_MODNAME,
1da177e4
LT		 2749 .id_table = azx_ids,
2750 .probe = azx_probe,
e23e7a14 2751 .remove = azx_remove,
b2a0bafa 2752 .shutdown = azx_shutdown,
68cb2b55
TI		 2753 .driver = {
2754 .pm = AZX_PM_OPS,
2755 },
1da177e4
LT		 2756};
2757
e9f66d9b 2758module_pci_driver(azx_driver);
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