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CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
362775e2 40#include <linux/kernel.h>
1da177e4 41#include <linux/module.h>
24982c5f 42#include <linux/dma-mapping.h>
1da177e4
LT		 43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
62932df8 47#include <linux/mutex.h>
0cbf0098 48#include <linux/reboot.h>
1da177e4
LT		 49#include <sound/core.h>
50#include <sound/initval.h>
51#include "hda_codec.h"
52
53
5aba4f8e
TI		 54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57static char *model[SNDRV_CARDS];
58static int position_fix[SNDRV_CARDS];
5c0d7bc1 59static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 60static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 61static int probe_only[SNDRV_CARDS];
27346166 62static int single_cmd;
71623855 63static int enable_msi = -1;
4ea6fbc8
TI		 64#ifdef CONFIG_SND_HDA_PATCH_LOADER
65static char *patch[SNDRV_CARDS];
66#endif
2dca0bba
JK		 67#ifdef CONFIG_SND_HDA_INPUT_BEEP
68static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
70#endif
1da177e4 71
5aba4f8e 72module_param_array(index, int, NULL, 0444);
1da177e4 73MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 74module_param_array(id, charp, NULL, 0444);
1da177e4 75MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 76module_param_array(enable, bool, NULL, 0444);
77MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78module_param_array(model, charp, NULL, 0444);
1da177e4 79MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 80module_param_array(position_fix, int, NULL, 0444);
d01ce99f 81MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
d2e1c973 82 "(0 = auto, 1 = none, 2 = POSBUF).");
555e219f
TI		 83module_param_array(bdl_pos_adj, int, NULL, 0644);
84MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 85module_param_array(probe_mask, int, NULL, 0444);
606ad75f 86MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
d4d9cd03
TI		 87module_param_array(probe_only, bool, NULL, 0444);
88MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 89module_param(single_cmd, bool, 0444);
d01ce99f
TI		 90MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
5aba4f8e 92module_param(enable_msi, int, 0444);
134a11f0 93MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 94#ifdef CONFIG_SND_HDA_PATCH_LOADER
95module_param_array(patch, charp, NULL, 0444);
96MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97#endif
2dca0bba
JK		 98#ifdef CONFIG_SND_HDA_INPUT_BEEP
99module_param_array(beep_mode, int, NULL, 0444);
100MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102#endif
606ad75f 103
dee1b66c 104#ifdef CONFIG_SND_HDA_POWER_SAVE
fee2fba3
TI		 105static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106module_param(power_save, int, 0644);
107MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
1da177e4 109
dee1b66c
TI		 110/* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
112 * wake up.
113 */
114static int power_save_controller = 1;
115module_param(power_save_controller, bool, 0644);
116MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117#endif
118
1da177e4
LT		 119MODULE_LICENSE("GPL");
120MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121 "{Intel, ICH6M},"
2f1b3818 122 "{Intel, ICH7},"
f5d40b30 123 "{Intel, ESB2},"
d2981393 124 "{Intel, ICH8},"
f9cc8a8b 125 "{Intel, ICH9},"
c34f5a04 126 "{Intel, ICH10},"
b29c2360 127 "{Intel, PCH},"
4979bca9 128 "{Intel, SCH},"
fc20a562 129 "{ATI, SB450},"
89be83f8 130 "{ATI, SB600},"
778b6e1b 131 "{ATI, RS600},"
5b15c95f 132 "{ATI, RS690},"
e6db1119
WL		 133 "{ATI, RS780},"
134 "{ATI, R600},"
2797f724
HRK		 135 "{ATI, RV630},"
136 "{ATI, RV610},"
27da1834
WL		 137 "{ATI, RV670},"
138 "{ATI, RV635},"
139 "{ATI, RV620},"
140 "{ATI, RV770},"
fc20a562 141 "{VIA, VT8251},"
47672310 142 "{VIA, VT8237A},"
07e4ca50
TI		 143 "{SiS, SIS966},"
144 "{ULI, M5461}}");
1da177e4
LT		 145MODULE_DESCRIPTION("Intel HDA driver");
146
4abc1cc2
TI		 147#ifdef CONFIG_SND_VERBOSE_PRINTK
148#define SFX /* nop */
149#else
1da177e4 150#define SFX "hda-intel: "
4abc1cc2 151#endif
cb53c626 152
1da177e4
LT		 153/*
154 * registers
155 */
156#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 157#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
158#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
159#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
160#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
161#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 162#define ICH6_REG_VMIN 0x02
163#define ICH6_REG_VMAJ 0x03
164#define ICH6_REG_OUTPAY 0x04
165#define ICH6_REG_INPAY 0x06
166#define ICH6_REG_GCTL 0x08
8a933ece 167#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 168#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
169#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 170#define ICH6_REG_WAKEEN 0x0c
171#define ICH6_REG_STATESTS 0x0e
172#define ICH6_REG_GSTS 0x10
b21fadb9 173#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 174#define ICH6_REG_INTCTL 0x20
175#define ICH6_REG_INTSTS 0x24
176#define ICH6_REG_WALCLK 0x30
177#define ICH6_REG_SYNC 0x34
178#define ICH6_REG_CORBLBASE 0x40
179#define ICH6_REG_CORBUBASE 0x44
180#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 181#define ICH6_REG_CORBRP 0x4a
182#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 183#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 184#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
185#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 186#define ICH6_REG_CORBSTS 0x4d
b21fadb9 187#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 188#define ICH6_REG_CORBSIZE 0x4e
189
190#define ICH6_REG_RIRBLBASE 0x50
191#define ICH6_REG_RIRBUBASE 0x54
192#define ICH6_REG_RIRBWP 0x58
b21fadb9 193#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 194#define ICH6_REG_RINTCNT 0x5a
195#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 196#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
197#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
198#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 199#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 200#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
201#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 202#define ICH6_REG_RIRBSIZE 0x5e
203
204#define ICH6_REG_IC 0x60
205#define ICH6_REG_IR 0x64
206#define ICH6_REG_IRS 0x68
207#define ICH6_IRS_VALID (1<<1)
208#define ICH6_IRS_BUSY (1<<0)
209
210#define ICH6_REG_DPLBASE 0x70
211#define ICH6_REG_DPUBASE 0x74
212#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
213
214/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
215enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
216
217/* stream register offsets from stream base */
218#define ICH6_REG_SD_CTL 0x00
219#define ICH6_REG_SD_STS 0x03
220#define ICH6_REG_SD_LPIB 0x04
221#define ICH6_REG_SD_CBL 0x08
222#define ICH6_REG_SD_LVI 0x0c
223#define ICH6_REG_SD_FIFOW 0x0e
224#define ICH6_REG_SD_FIFOSIZE 0x10
225#define ICH6_REG_SD_FORMAT 0x12
226#define ICH6_REG_SD_BDLPL 0x18
227#define ICH6_REG_SD_BDLPU 0x1c
228
229/* PCI space */
230#define ICH6_PCIREG_TCSEL 0x44
231
232/*
233 * other constants
234 */
235
236/* max number of SDs */
07e4ca50 237/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 238#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 239#define ICH6_NUM_PLAYBACK 4
240
241/* ULI has 6 playback and 5 capture */
07e4ca50 242#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 243#define ULI_NUM_PLAYBACK 6
244
778b6e1b 245/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 246#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 247#define ATIHDMI_NUM_PLAYBACK 1
248
f269002e
KY		 249/* TERA has 4 playback and 3 capture */
250#define TERA_NUM_CAPTURE 3
251#define TERA_NUM_PLAYBACK 4
252
07e4ca50
TI		 253/* this number is statically defined for simplicity */
254#define MAX_AZX_DEV 16
255
1da177e4 256/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 257#define BDL_SIZE 4096
258#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
259#define AZX_MAX_FRAG 32
1da177e4
LT		 260/* max buffer size - no h/w limit, you can increase as you like */
261#define AZX_MAX_BUF_SIZE (1024*1024*1024)
262/* max number of PCM devics per card */
7ba72ba1 263#define AZX_MAX_PCMS 8
1da177e4
LT		 264
265/* RIRB int mask: overrun[2], response[0] */
266#define RIRB_INT_RESPONSE 0x01
267#define RIRB_INT_OVERRUN 0x04
268#define RIRB_INT_MASK 0x05
269
2f5983f2
TI		 270/* STATESTS int mask: S3,SD2,SD1,SD0 */
271#define AZX_MAX_CODECS 4
deadff16 272#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 273
274/* SD_CTL bits */
275#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
276#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 277#define SD_CTL_STRIPE (3 << 16) /* stripe control */
278#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
279#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 280#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
281#define SD_CTL_STREAM_TAG_SHIFT 20
282
283/* SD_CTL and SD_STS */
284#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
285#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
286#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 287#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
288 SD_INT_COMPLETE)
1da177e4
LT		 289
290/* SD_STS */
291#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
292
293/* INTCTL and INTSTS */
d01ce99f
TI		 294#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
295#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
296#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 297
1da177e4
LT		 298/* below are so far hardcoded - should read registers in future */
299#define ICH6_MAX_CORB_ENTRIES 256
300#define ICH6_MAX_RIRB_ENTRIES 256
301
c74db86b
TI		 302/* position fix mode */
303enum {
0be3b5d3 304 POS_FIX_AUTO,
d2e1c973 305 POS_FIX_LPIB,
0be3b5d3 306 POS_FIX_POSBUF,
c74db86b 307};
1da177e4 308
f5d40b30 309/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 310#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
311#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
312
da3fca21
V		 313/* Defines for Nvidia HDA support */
314#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
315#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 316#define NVIDIA_HDA_ISTRM_COH 0x4d
317#define NVIDIA_HDA_OSTRM_COH 0x4c
318#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 319
90a5ad52
TI		 320/* Defines for Intel SCH HDA snoop control */
321#define INTEL_SCH_HDA_DEVC 0x78
322#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
323
0e153474
JC		 324/* Define IN stream 0 FIFO size offset in VIA controller */
325#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
326/* Define VIA HD Audio Device ID*/
327#define VIA_HDAC_DEVICE_ID 0x3288
328
c4da29ca
YL		 329/* HD Audio class code */
330#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 331
1da177e4
LT		 332/*
333 */
334
a98f90fd 335struct azx_dev {
4ce107b9 336 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 337 u32 *posbuf; /* position buffer pointer */
1da177e4 338
d01ce99f 339 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 340 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 341 unsigned int frags; /* number for period in the play buffer */
342 unsigned int fifo_size; /* FIFO size */
fa00e046
JK		 343 unsigned long start_jiffies; /* start + minimum jiffies */
344 unsigned long min_jiffies; /* minimum jiffies before position is valid */
1da177e4 345
d01ce99f 346 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 347
d01ce99f 348 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 349
350 /* pcm support */
d01ce99f
TI		 351 struct snd_pcm_substream *substream; /* assigned substream,
352 * set in PCM open
353 */
354 unsigned int format_val; /* format value to be set in the
355 * controller and the codec
356 */
1da177e4
LT		 357 unsigned char stream_tag; /* assigned stream */
358 unsigned char index; /* stream index */
ef18bede 359 int device; /* last device number assigned to */
1da177e4 360
927fc866
PM		 361 unsigned int opened :1;
362 unsigned int running :1;
675f25d4 363 unsigned int irq_pending :1;
d523b0c8 364 unsigned int start_flag: 1; /* stream full start flag */
0e153474
JC		 365 /*
366 * For VIA:
367 * A flag to ensure DMA position is 0
368 * when link position is not greater than FIFO size
369 */
370 unsigned int insufficient :1;
1da177e4
LT		 371};
372
373/* CORB/RIRB */
a98f90fd 374struct azx_rb {
1da177e4
LT		 375 u32 *buf; /* CORB/RIRB buffer
376 * Each CORB entry is 4byte, RIRB is 8byte
377 */
378 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
379 /* for RIRB */
380 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 381 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
382 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 383};
384
a98f90fd
TI		 385struct azx {
386 struct snd_card *card;
1da177e4 387 struct pci_dev *pci;
555e219f 388 int dev_index;
1da177e4 389
07e4ca50
TI		 390 /* chip type specific */
391 int driver_type;
392 int playback_streams;
393 int playback_index_offset;
394 int capture_streams;
395 int capture_index_offset;
396 int num_streams;
397
1da177e4
LT		 398 /* pci resources */
399 unsigned long addr;
400 void __iomem *remap_addr;
401 int irq;
402
403 /* locks */
404 spinlock_t reg_lock;
62932df8 405 struct mutex open_mutex;
1da177e4 406
07e4ca50 407 /* streams (x num_streams) */
a98f90fd 408 struct azx_dev *azx_dev;
1da177e4
LT		 409
410 /* PCM */
a98f90fd 411 struct snd_pcm *pcm[AZX_MAX_PCMS];
1da177e4
LT		 412
413 /* HD codec */
414 unsigned short codec_mask;
f1eaaeec 415 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 416 struct hda_bus *bus;
2dca0bba 417 unsigned int beep_mode;
1da177e4
LT		 418
419 /* CORB/RIRB */
a98f90fd
TI		 420 struct azx_rb corb;
421 struct azx_rb rirb;
1da177e4 422
4ce107b9 423 /* CORB/RIRB and position buffers */
1da177e4
LT		 424 struct snd_dma_buffer rb;
425 struct snd_dma_buffer posbuf;
c74db86b
TI		 426
427 /* flags */
428 int position_fix;
cb53c626 429 unsigned int running :1;
927fc866
PM		 430 unsigned int initialized :1;
431 unsigned int single_cmd :1;
432 unsigned int polling_mode :1;
68e7fffc 433 unsigned int msi :1;
a6a950a8 434 unsigned int irq_pending_warned :1;
0e153474 435 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
6ce4a3bc 436 unsigned int probing :1; /* codec probing phase */
43bbb6cc
TI		 437
438 /* for debugging */
feb27340 439 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 440
441 /* for pending irqs */
442 struct work_struct irq_pending_work;
0cbf0098
TI		 443
444 /* reboot notifier (for mysterious hangup problem at power-down) */
445 struct notifier_block reboot_notifier;
1da177e4
LT		 446};
447
07e4ca50
TI		 448/* driver types */
449enum {
450 AZX_DRIVER_ICH,
4979bca9 451 AZX_DRIVER_SCH,
07e4ca50 452 AZX_DRIVER_ATI,
778b6e1b 453 AZX_DRIVER_ATIHDMI,
07e4ca50
TI		 454 AZX_DRIVER_VIA,
455 AZX_DRIVER_SIS,
456 AZX_DRIVER_ULI,
da3fca21 457 AZX_DRIVER_NVIDIA,
f269002e 458 AZX_DRIVER_TERA,
c4da29ca 459 AZX_DRIVER_GENERIC,
2f5983f2 460 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 461};
462
463static char *driver_short_names[] __devinitdata = {
464 [AZX_DRIVER_ICH] = "HDA Intel",
4979bca9 465 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 466 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 467 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI		 468 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
469 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 470 [AZX_DRIVER_ULI] = "HDA ULI M5461",
471 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 472 [AZX_DRIVER_TERA] = "HDA Teradici",
c4da29ca 473 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 474};
475
1da177e4
LT		 476/*
477 * macros for easy use
478 */
479#define azx_writel(chip,reg,value) \
480 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
481#define azx_readl(chip,reg) \
482 readl((chip)->remap_addr + ICH6_REG_##reg)
483#define azx_writew(chip,reg,value) \
484 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
485#define azx_readw(chip,reg) \
486 readw((chip)->remap_addr + ICH6_REG_##reg)
487#define azx_writeb(chip,reg,value) \
488 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
489#define azx_readb(chip,reg) \
490 readb((chip)->remap_addr + ICH6_REG_##reg)
491
492#define azx_sd_writel(dev,reg,value) \
493 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
494#define azx_sd_readl(dev,reg) \
495 readl((dev)->sd_addr + ICH6_REG_##reg)
496#define azx_sd_writew(dev,reg,value) \
497 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
498#define azx_sd_readw(dev,reg) \
499 readw((dev)->sd_addr + ICH6_REG_##reg)
500#define azx_sd_writeb(dev,reg,value) \
501 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
502#define azx_sd_readb(dev,reg) \
503 readb((dev)->sd_addr + ICH6_REG_##reg)
504
505/* for pcm support */
a98f90fd 506#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 507
68e7fffc 508static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1da177e4
LT		 509
510/*
511 * Interface for HD codec
512 */
513
1da177e4
LT		 514/*
515 * CORB / RIRB interface
516 */
a98f90fd 517static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 518{
519 int err;
520
521 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 522 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
523 snd_dma_pci_data(chip->pci),
1da177e4
LT		 524 PAGE_SIZE, &chip->rb);
525 if (err < 0) {
526 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
527 return err;
528 }
529 return 0;
530}
531
a98f90fd 532static void azx_init_cmd_io(struct azx *chip)
1da177e4 533{
cdb1fbf2 534 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 535 /* CORB set up */
536 chip->corb.addr = chip->rb.addr;
537 chip->corb.buf = (u32 *)chip->rb.area;
538 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 539 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 540
07e4ca50
TI		 541 /* set the corb size to 256 entries (ULI requires explicitly) */
542 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 543 /* set the corb write pointer to 0 */
544 azx_writew(chip, CORBWP, 0);
545 /* reset the corb hw read pointer */
b21fadb9 546 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 547 /* enable corb dma */
b21fadb9 548 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 549
550 /* RIRB set up */
551 chip->rirb.addr = chip->rb.addr + 2048;
552 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 553 chip->rirb.wp = chip->rirb.rp = 0;
554 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 555 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 556 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 557
07e4ca50
TI		 558 /* set the rirb size to 256 entries (ULI requires explicitly) */
559 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 560 /* reset the rirb hw write pointer */
b21fadb9 561 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4
LT		 562 /* set N=1, get RIRB response interrupt for new entry */
563 azx_writew(chip, RINTCNT, 1);
564 /* enable rirb dma and response irq */
1da177e4 565 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 566 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 567}
568
a98f90fd 569static void azx_free_cmd_io(struct azx *chip)
1da177e4 570{
cdb1fbf2 571 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 572 /* disable ringbuffer DMAs */
573 azx_writeb(chip, RIRBCTL, 0);
574 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 575 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 576}
577
deadff16
WF		 578static unsigned int azx_command_addr(u32 cmd)
579{
580 unsigned int addr = cmd >> 28;
581
582 if (addr >= AZX_MAX_CODECS) {
583 snd_BUG();
584 addr = 0;
585 }
586
587 return addr;
588}
589
590static unsigned int azx_response_addr(u32 res)
591{
592 unsigned int addr = res & 0xf;
593
594 if (addr >= AZX_MAX_CODECS) {
595 snd_BUG();
596 addr = 0;
597 }
598
599 return addr;
1da177e4
LT		 600}
601
602/* send a command */
33fa35ed 603static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 604{
33fa35ed 605 struct azx *chip = bus->private_data;
deadff16 606 unsigned int addr = azx_command_addr(val);
1da177e4 607 unsigned int wp;
1da177e4 608
c32649fe
WF		 609 spin_lock_irq(&chip->reg_lock);
610
1da177e4
LT		 611 /* add command to corb */
612 wp = azx_readb(chip, CORBWP);
613 wp++;
614 wp %= ICH6_MAX_CORB_ENTRIES;
615
deadff16 616 chip->rirb.cmds[addr]++;
1da177e4
LT		 617 chip->corb.buf[wp] = cpu_to_le32(val);
618 azx_writel(chip, CORBWP, wp);
c32649fe 619
1da177e4
LT		 620 spin_unlock_irq(&chip->reg_lock);
621
622 return 0;
623}
624
625#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
626
627/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 628static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 629{
630 unsigned int rp, wp;
deadff16 631 unsigned int addr;
1da177e4
LT		 632 u32 res, res_ex;
633
634 wp = azx_readb(chip, RIRBWP);
635 if (wp == chip->rirb.wp)
636 return;
637 chip->rirb.wp = wp;
deadff16 638
1da177e4
LT		 639 while (chip->rirb.rp != wp) {
640 chip->rirb.rp++;
641 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
642
643 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
644 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
645 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 646 addr = azx_response_addr(res_ex);
1da177e4
LT		 647 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
648 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 649 else if (chip->rirb.cmds[addr]) {
650 chip->rirb.res[addr] = res;
2add9b92 651 smp_wmb();
deadff16 652 chip->rirb.cmds[addr]--;
e310bb06
WF		 653 } else
654 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
655 "last cmd=%#08x\n",
656 res, res_ex,
657 chip->last_cmd[addr]);
1da177e4
LT		 658 }
659}
660
661/* receive a response */
deadff16
WF		 662static unsigned int azx_rirb_get_response(struct hda_bus *bus,
663 unsigned int addr)
1da177e4 664{
33fa35ed 665 struct azx *chip = bus->private_data;
5c79b1f8 666 unsigned long timeout;
1da177e4 667
5c79b1f8
TI		 668 again:
669 timeout = jiffies + msecs_to_jiffies(1000);
28a0d9df 670 for (;;) {
e96224ae
TI		 671 if (chip->polling_mode) {
672 spin_lock_irq(&chip->reg_lock);
673 azx_update_rirb(chip);
674 spin_unlock_irq(&chip->reg_lock);
675 }
deadff16 676 if (!chip->rirb.cmds[addr]) {
2add9b92 677 smp_rmb();
b613291f 678 bus->rirb_error = 0;
deadff16 679 return chip->rirb.res[addr]; /* the last value */
2add9b92 680 }
28a0d9df
TI		 681 if (time_after(jiffies, timeout))
682 break;
33fa35ed 683 if (bus->needs_damn_long_delay)
52987656
TI		 684 msleep(2); /* temporary workaround */
685 else {
686 udelay(10);
687 cond_resched();
688 }
28a0d9df 689 }
5c79b1f8 690
23c4a881
TI		 691 if (!chip->polling_mode) {
692 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
693 "switching to polling mode: last cmd=0x%08x\n",
694 chip->last_cmd[addr]);
695 chip->polling_mode = 1;
696 goto again;
697 }
698
68e7fffc 699 if (chip->msi) {
4abc1cc2 700 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 701 "disabling MSI: last cmd=0x%08x\n",
702 chip->last_cmd[addr]);
68e7fffc
TI		 703 free_irq(chip->irq, chip);
704 chip->irq = -1;
705 pci_disable_msi(chip->pci);
706 chip->msi = 0;
b613291f
TI		 707 if (azx_acquire_irq(chip, 1) < 0) {
708 bus->rirb_error = 1;
68e7fffc 709 return -1;
b613291f 710 }
68e7fffc
TI		 711 goto again;
712 }
713
6ce4a3bc
TI		 714 if (chip->probing) {
715 /* If this critical timeout happens during the codec probing
716 * phase, this is likely an access to a non-existing codec
717 * slot. Better to return an error and reset the system.
718 */
719 return -1;
720 }
721
8dd78330
TI		 722 /* a fatal communication error; need either to reset or to fallback
723 * to the single_cmd mode
724 */
b613291f 725 bus->rirb_error = 1;
b20f3b83 726 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 727 bus->response_reset = 1;
728 return -1; /* give a chance to retry */
729 }
730
731 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
732 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 733 chip->last_cmd[addr]);
8dd78330
TI		 734 chip->single_cmd = 1;
735 bus->response_reset = 0;
1a696978 736 /* release CORB/RIRB */
4fcd3920 737 azx_free_cmd_io(chip);
1a696978
TI		 738 /* disable unsolicited responses */
739 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 740 return -1;
1da177e4
LT		 741}
742
1da177e4
LT		 743/*
744 * Use the single immediate command instead of CORB/RIRB for simplicity
745 *
746 * Note: according to Intel, this is not preferred use. The command was
747 * intended for the BIOS only, and may get confused with unsolicited
748 * responses. So, we shouldn't use it for normal operation from the
749 * driver.
750 * I left the codes, however, for debugging/testing purposes.
751 */
752
b05a7d4f 753/* receive a response */
deadff16 754static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 755{
756 int timeout = 50;
757
758 while (timeout--) {
759 /* check IRV busy bit */
760 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
761 /* reuse rirb.res as the response return value */
deadff16 762 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 763 return 0;
764 }
765 udelay(1);
766 }
767 if (printk_ratelimit())
768 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
769 azx_readw(chip, IRS));
deadff16 770 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 771 return -EIO;
772}
773
1da177e4 774/* send a command */
33fa35ed 775static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 776{
33fa35ed 777 struct azx *chip = bus->private_data;
deadff16 778 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 779 int timeout = 50;
780
8dd78330 781 bus->rirb_error = 0;
1da177e4
LT		 782 while (timeout--) {
783 /* check ICB busy bit */
d01ce99f 784 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 785 /* Clear IRV valid bit */
d01ce99f
TI		 786 azx_writew(chip, IRS, azx_readw(chip, IRS) |
787 ICH6_IRS_VALID);
1da177e4 788 azx_writel(chip, IC, val);
d01ce99f
TI		 789 azx_writew(chip, IRS, azx_readw(chip, IRS) |
790 ICH6_IRS_BUSY);
deadff16 791 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 792 }
793 udelay(1);
794 }
1cfd52bc
MB		 795 if (printk_ratelimit())
796 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
797 azx_readw(chip, IRS), val);
1da177e4
LT		 798 return -EIO;
799}
800
801/* receive a response */
deadff16
WF		 802static unsigned int azx_single_get_response(struct hda_bus *bus,
803 unsigned int addr)
1da177e4 804{
33fa35ed 805 struct azx *chip = bus->private_data;
deadff16 806 return chip->rirb.res[addr];
1da177e4
LT		 807}
808
111d3af5
TI		 809/*
810 * The below are the main callbacks from hda_codec.
811 *
812 * They are just the skeleton to call sub-callbacks according to the
813 * current setting of chip->single_cmd.
814 */
815
816/* send a command */
33fa35ed 817static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 818{
33fa35ed 819 struct azx *chip = bus->private_data;
43bbb6cc 820
feb27340 821 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 822 if (chip->single_cmd)
33fa35ed 823 return azx_single_send_cmd(bus, val);
111d3af5 824 else
33fa35ed 825 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 826}
827
828/* get a response */
deadff16
WF		 829static unsigned int azx_get_response(struct hda_bus *bus,
830 unsigned int addr)
111d3af5 831{
33fa35ed 832 struct azx *chip = bus->private_data;
111d3af5 833 if (chip->single_cmd)
deadff16 834 return azx_single_get_response(bus, addr);
111d3af5 835 else
deadff16 836 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 837}
838
cb53c626 839#ifdef CONFIG_SND_HDA_POWER_SAVE
33fa35ed 840static void azx_power_notify(struct hda_bus *bus);
cb53c626 841#endif
111d3af5 842
1da177e4 843/* reset codec link */
a98f90fd 844static int azx_reset(struct azx *chip)
1da177e4
LT		 845{
846 int count;
847
e8a7f136
DT		 848 /* clear STATESTS */
849 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
850
1da177e4
LT		 851 /* reset controller */
852 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
853
854 count = 50;
855 while (azx_readb(chip, GCTL) && --count)
856 msleep(1);
857
858 /* delay for >= 100us for codec PLL to settle per spec
859 * Rev 0.9 section 5.5.1
860 */
861 msleep(1);
862
863 /* Bring controller out of reset */
864 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
865
866 count = 50;
927fc866 867 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 868 msleep(1);
869
927fc866 870 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 871 msleep(1);
872
873 /* check to see if controller is ready */
927fc866 874 if (!azx_readb(chip, GCTL)) {
4abc1cc2 875 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 876 return -EBUSY;
877 }
878
41e2fce4 879 /* Accept unsolicited responses */
1a696978
TI		 880 if (!chip->single_cmd)
881 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
882 ICH6_GCTL_UNSOL);
41e2fce4 883
1da177e4 884 /* detect codecs */
927fc866 885 if (!chip->codec_mask) {
1da177e4 886 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 887 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 888 }
889
890 return 0;
891}
892
893
894/*
895 * Lowlevel interface
896 */
897
898/* enable interrupts */
a98f90fd 899static void azx_int_enable(struct azx *chip)
1da177e4
LT		 900{
901 /* enable controller CIE and GIE */
902 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
903 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
904}
905
906/* disable interrupts */
a98f90fd 907static void azx_int_disable(struct azx *chip)
1da177e4
LT		 908{
909 int i;
910
911 /* disable interrupts in stream descriptor */
07e4ca50 912 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 913 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 914 azx_sd_writeb(azx_dev, SD_CTL,
915 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
916 }
917
918 /* disable SIE for all streams */
919 azx_writeb(chip, INTCTL, 0);
920
921 /* disable controller CIE and GIE */
922 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
923 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
924}
925
926/* clear interrupts */
a98f90fd 927static void azx_int_clear(struct azx *chip)
1da177e4
LT		 928{
929 int i;
930
931 /* clear stream status */
07e4ca50 932 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 933 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 934 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
935 }
936
937 /* clear STATESTS */
938 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
939
940 /* clear rirb status */
941 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
942
943 /* clear int status */
944 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
945}
946
947/* start a stream */
a98f90fd 948static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 949{
0e153474
JC		 950 /*
951 * Before stream start, initialize parameter
952 */
953 azx_dev->insufficient = 1;
954
1da177e4
LT		 955 /* enable SIE */
956 azx_writeb(chip, INTCTL,
957 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
958 /* set DMA start and interrupt mask */
959 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
960 SD_CTL_DMA_START | SD_INT_MASK);
961}
962
1dddab40
TI		 963/* stop DMA */
964static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 965{
1da177e4
LT		 966 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
967 ~(SD_CTL_DMA_START | SD_INT_MASK));
968 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 969}
970
971/* stop a stream */
972static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
973{
974 azx_stream_clear(chip, azx_dev);
1da177e4
LT		 975 /* disable SIE */
976 azx_writeb(chip, INTCTL,
977 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
978}
979
980
981/*
cb53c626 982 * reset and start the controller registers
1da177e4 983 */
a98f90fd 984static void azx_init_chip(struct azx *chip)
1da177e4 985{
cb53c626
TI		 986 if (chip->initialized)
987 return;
1da177e4
LT		 988
989 /* reset controller */
990 azx_reset(chip);
991
992 /* initialize interrupts */
993 azx_int_clear(chip);
994 azx_int_enable(chip);
995
996 /* initialize the codec command I/O */
1a696978
TI		 997 if (!chip->single_cmd)
998 azx_init_cmd_io(chip);
1da177e4 999
0be3b5d3
TI		 1000 /* program the position buffer */
1001 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1002 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1003
cb53c626
TI		 1004 chip->initialized = 1;
1005}
1006
1007/*
1008 * initialize the PCI registers
1009 */
1010/* update bits in a PCI register byte */
1011static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1012 unsigned char mask, unsigned char val)
1013{
1014 unsigned char data;
1015
1016 pci_read_config_byte(pci, reg, &data);
1017 data &= ~mask;
1018 data |= (val & mask);
1019 pci_write_config_byte(pci, reg, data);
1020}
1021
1022static void azx_init_pci(struct azx *chip)
1023{
90a5ad52
TI		 1024 unsigned short snoop;
1025
cb53c626
TI		 1026 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1027 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1028 * Ensuring these bits are 0 clears playback static on some HD Audio
1029 * codecs
1030 */
1031 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1032
da3fca21
V		 1033 switch (chip->driver_type) {
1034 case AZX_DRIVER_ATI:
1035 /* For ATI SB450 azalia HD audio, we need to enable snoop */
cb53c626
TI		 1036 update_pci_byte(chip->pci,
1037 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1038 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
da3fca21
V		 1039 break;
1040 case AZX_DRIVER_NVIDIA:
1041 /* For NVIDIA HDA, enable snoop */
cb53c626
TI		 1042 update_pci_byte(chip->pci,
1043 NVIDIA_HDA_TRANSREG_ADDR,
1044 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1045 update_pci_byte(chip->pci,
1046 NVIDIA_HDA_ISTRM_COH,
1047 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1048 update_pci_byte(chip->pci,
1049 NVIDIA_HDA_OSTRM_COH,
1050 0x01, NVIDIA_HDA_ENABLE_COHBIT);
da3fca21 1051 break;
90a5ad52
TI		 1052 case AZX_DRIVER_SCH:
1053 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1054 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
4abc1cc2 1055 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
90a5ad52
TI		 1056 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1057 pci_read_config_word(chip->pci,
1058 INTEL_SCH_HDA_DEVC, &snoop);
4abc1cc2
TI		 1059 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1060 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
90a5ad52
TI		 1061 ? "Failed" : "OK");
1062 }
1063 break;
1064
da3fca21 1065 }
1da177e4
LT		 1066}
1067
1068
9ad593f6
TI		 1069static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1070
1da177e4
LT		 1071/*
1072 * interrupt handler
1073 */
7d12e780 1074static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1075{
a98f90fd
TI		 1076 struct azx *chip = dev_id;
1077 struct azx_dev *azx_dev;
1da177e4 1078 u32 status;
fa00e046 1079 int i, ok;
1da177e4
LT		 1080
1081 spin_lock(&chip->reg_lock);
1082
1083 status = azx_readl(chip, INTSTS);
1084 if (status == 0) {
1085 spin_unlock(&chip->reg_lock);
1086 return IRQ_NONE;
1087 }
1088
07e4ca50 1089 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1090 azx_dev = &chip->azx_dev[i];
1091 if (status & azx_dev->sd_int_sta_mask) {
1092 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ad593f6
TI		 1093 if (!azx_dev->substream || !azx_dev->running)
1094 continue;
1095 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1096 ok = azx_position_ok(chip, azx_dev);
1097 if (ok == 1) {
9ad593f6 1098 azx_dev->irq_pending = 0;
1da177e4
LT		 1099 spin_unlock(&chip->reg_lock);
1100 snd_pcm_period_elapsed(azx_dev->substream);
1101 spin_lock(&chip->reg_lock);
fa00e046 1102 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1103 /* bogus IRQ, process it later */
1104 azx_dev->irq_pending = 1;
6acaed38
TI		 1105 queue_work(chip->bus->workq,
1106 &chip->irq_pending_work);
1da177e4
LT		 1107 }
1108 }
1109 }
1110
1111 /* clear rirb int */
1112 status = azx_readb(chip, RIRBSTS);
1113 if (status & RIRB_INT_MASK) {
81740861 1114 if (status & RIRB_INT_RESPONSE)
1da177e4
LT		 1115 azx_update_rirb(chip);
1116 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1117 }
1118
1119#if 0
1120 /* clear state status int */
1121 if (azx_readb(chip, STATESTS) & 0x04)
1122 azx_writeb(chip, STATESTS, 0x04);
1123#endif
1124 spin_unlock(&chip->reg_lock);
1125
1126 return IRQ_HANDLED;
1127}
1128
1129
675f25d4
TI		 1130/*
1131 * set up a BDL entry
1132 */
1133static int setup_bdle(struct snd_pcm_substream *substream,
1134 struct azx_dev *azx_dev, u32 **bdlp,
1135 int ofs, int size, int with_ioc)
1136{
675f25d4
TI		 1137 u32 *bdl = *bdlp;
1138
1139 while (size > 0) {
1140 dma_addr_t addr;
1141 int chunk;
1142
1143 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1144 return -EINVAL;
1145
77a23f26 1146 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1147 /* program the address field of the BDL entry */
1148 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1149 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1150 /* program the size field of the BDL entry */
fc4abee8 1151 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
675f25d4
TI		 1152 bdl[2] = cpu_to_le32(chunk);
1153 /* program the IOC to enable interrupt
1154 * only when the whole fragment is processed
1155 */
1156 size -= chunk;
1157 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1158 bdl += 4;
1159 azx_dev->frags++;
1160 ofs += chunk;
1161 }
1162 *bdlp = bdl;
1163 return ofs;
1164}
1165
1da177e4
LT		 1166/*
1167 * set up BDL entries
1168 */
555e219f
TI		 1169static int azx_setup_periods(struct azx *chip,
1170 struct snd_pcm_substream *substream,
4ce107b9 1171 struct azx_dev *azx_dev)
1da177e4 1172{
4ce107b9
TI		 1173 u32 *bdl;
1174 int i, ofs, periods, period_bytes;
555e219f 1175 int pos_adj;
1da177e4
LT		 1176
1177 /* reset BDL address */
1178 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1179 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1180
97b71c94 1181 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1182 periods = azx_dev->bufsize / period_bytes;
1183
1da177e4 1184 /* program the initial BDL entries */
4ce107b9
TI		 1185 bdl = (u32 *)azx_dev->bdl.area;
1186 ofs = 0;
1187 azx_dev->frags = 0;
555e219f
TI		 1188 pos_adj = bdl_pos_adj[chip->dev_index];
1189 if (pos_adj > 0) {
675f25d4 1190 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1191 int pos_align = pos_adj;
555e219f 1192 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1193 if (!pos_adj)
e785d3d8
TI		 1194 pos_adj = pos_align;
1195 else
1196 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1197 pos_align;
675f25d4
TI		 1198 pos_adj = frames_to_bytes(runtime, pos_adj);
1199 if (pos_adj >= period_bytes) {
4abc1cc2 1200 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1201 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1202 pos_adj = 0;
1203 } else {
1204 ofs = setup_bdle(substream, azx_dev,
1205 &bdl, ofs, pos_adj, 1);
1206 if (ofs < 0)
1207 goto error;
4ce107b9 1208 }
555e219f
TI		 1209 } else
1210 pos_adj = 0;
675f25d4
TI		 1211 for (i = 0; i < periods; i++) {
1212 if (i == periods - 1 && pos_adj)
1213 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1214 period_bytes - pos_adj, 0);
1215 else
1216 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1217 period_bytes, 1);
1218 if (ofs < 0)
1219 goto error;
1da177e4 1220 }
4ce107b9 1221 return 0;
675f25d4
TI		 1222
1223 error:
4abc1cc2 1224 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1225 azx_dev->bufsize, period_bytes);
675f25d4 1226 return -EINVAL;
1da177e4
LT		 1227}
1228
1dddab40
TI		 1229/* reset stream */
1230static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1231{
1232 unsigned char val;
1233 int timeout;
1234
1dddab40
TI		 1235 azx_stream_clear(chip, azx_dev);
1236
d01ce99f
TI		 1237 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1238 SD_CTL_STREAM_RESET);
1da177e4
LT		 1239 udelay(3);
1240 timeout = 300;
1241 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1242 --timeout)
1243 ;
1244 val &= ~SD_CTL_STREAM_RESET;
1245 azx_sd_writeb(azx_dev, SD_CTL, val);
1246 udelay(3);
1247
1248 timeout = 300;
1249 /* waiting for hardware to report that the stream is out of reset */
1250 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1251 --timeout)
1252 ;
fa00e046
JK		 1253
1254 /* reset first position - may not be synced with hw at this time */
1255 *azx_dev->posbuf = 0;
1dddab40 1256}
1da177e4 1257
1dddab40
TI		 1258/*
1259 * set up the SD for streaming
1260 */
1261static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1262{
1263 /* make sure the run bit is zero for SD */
1264 azx_stream_clear(chip, azx_dev);
1da177e4
LT		 1265 /* program the stream_tag */
1266 azx_sd_writel(azx_dev, SD_CTL,
d01ce99f 1267 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1da177e4
LT		 1268 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1269
1270 /* program the length of samples in cyclic buffer */
1271 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1272
1273 /* program the stream format */
1274 /* this value needs to be the same as the one programmed */
1275 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1276
1277 /* program the stream LVI (last valid index) of the BDL */
1278 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1279
1280 /* program the BDL address */
1281 /* lower BDL address */
4ce107b9 1282 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1283 /* upper BDL address */
766979e0 1284 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1285
0be3b5d3 1286 /* enable the position buffer */
ee9d6b9a 1287 if (chip->position_fix == POS_FIX_POSBUF ||
0e153474
JC		 1288 chip->position_fix == POS_FIX_AUTO ||
1289 chip->via_dmapos_patch) {
ee9d6b9a
TI		 1290 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1291 azx_writel(chip, DPLBASE,
1292 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1293 }
c74db86b 1294
1da177e4 1295 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1296 azx_sd_writel(azx_dev, SD_CTL,
1297 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1298
1299 return 0;
1300}
1301
6ce4a3bc
TI		 1302/*
1303 * Probe the given codec address
1304 */
1305static int probe_codec(struct azx *chip, int addr)
1306{
1307 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1308 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1309 unsigned int res;
1310
a678cdee 1311 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1312 chip->probing = 1;
1313 azx_send_cmd(chip->bus, cmd);
deadff16 1314 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1315 chip->probing = 0;
a678cdee 1316 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1317 if (res == -1)
1318 return -EIO;
4abc1cc2 1319 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1320 return 0;
1321}
1322
33fa35ed
TI		 1323static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1324 struct hda_pcm *cpcm);
6ce4a3bc 1325static void azx_stop_chip(struct azx *chip);
1da177e4 1326
8dd78330
TI		 1327static void azx_bus_reset(struct hda_bus *bus)
1328{
1329 struct azx *chip = bus->private_data;
8dd78330
TI		 1330
1331 bus->in_reset = 1;
1332 azx_stop_chip(chip);
1333 azx_init_chip(chip);
65f75983 1334#ifdef CONFIG_PM
8dd78330 1335 if (chip->initialized) {
65f75983
AB		 1336 int i;
1337
8dd78330
TI		 1338 for (i = 0; i < AZX_MAX_PCMS; i++)
1339 snd_pcm_suspend_all(chip->pcm[i]);
1340 snd_hda_suspend(chip->bus);
1341 snd_hda_resume(chip->bus);
1342 }
65f75983 1343#endif
8dd78330
TI		 1344 bus->in_reset = 0;
1345}
1346
1da177e4
LT		 1347/*
1348 * Codec initialization
1349 */
1350
2f5983f2
TI		 1351/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1352static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
f269002e 1353 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1354};
1355
a1e21c90 1356static int __devinit azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1357{
1358 struct hda_bus_template bus_temp;
34c25350
TI		 1359 int c, codecs, err;
1360 int max_slots;
1da177e4
LT		 1361
1362 memset(&bus_temp, 0, sizeof(bus_temp));
1363 bus_temp.private_data = chip;
1364 bus_temp.modelname = model;
1365 bus_temp.pci = chip->pci;
111d3af5
TI		 1366 bus_temp.ops.command = azx_send_cmd;
1367 bus_temp.ops.get_response = azx_get_response;
176d5335 1368 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1369 bus_temp.ops.bus_reset = azx_bus_reset;
cb53c626 1370#ifdef CONFIG_SND_HDA_POWER_SAVE
11cd41b8 1371 bus_temp.power_save = &power_save;
cb53c626
TI		 1372 bus_temp.ops.pm_notify = azx_power_notify;
1373#endif
1da177e4 1374
d01ce99f
TI		 1375 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1376 if (err < 0)
1da177e4
LT		 1377 return err;
1378
dc9c8e21
WN		 1379 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1380 chip->bus->needs_damn_long_delay = 1;
1381
34c25350 1382 codecs = 0;
2f5983f2
TI		 1383 max_slots = azx_max_codecs[chip->driver_type];
1384 if (!max_slots)
1385 max_slots = AZX_MAX_CODECS;
6ce4a3bc
TI		 1386
1387 /* First try to probe all given codec slots */
1388 for (c = 0; c < max_slots; c++) {
f1eaaeec 1389 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1390 if (probe_codec(chip, c) < 0) {
1391 /* Some BIOSen give you wrong codec addresses
1392 * that don't exist
1393 */
4abc1cc2
TI		 1394 snd_printk(KERN_WARNING SFX
1395 "Codec #%d probe error; "
6ce4a3bc
TI		 1396 "disabling it...\n", c);
1397 chip->codec_mask &= ~(1 << c);
1398 /* More badly, accessing to a non-existing
1399 * codec often screws up the controller chip,
1400 * and distrubs the further communications.
1401 * Thus if an error occurs during probing,
1402 * better to reset the controller chip to
1403 * get back to the sanity state.
1404 */
1405 azx_stop_chip(chip);
1406 azx_init_chip(chip);
1407 }
1408 }
1409 }
1410
1411 /* Then create codec instances */
34c25350 1412 for (c = 0; c < max_slots; c++) {
f1eaaeec 1413 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1414 struct hda_codec *codec;
a1e21c90 1415 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1416 if (err < 0)
1417 continue;
2dca0bba 1418 codec->beep_mode = chip->beep_mode;
1da177e4 1419 codecs++;
19a982b6
TI		 1420 }
1421 }
1422 if (!codecs) {
1da177e4
LT		 1423 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1424 return -ENXIO;
1425 }
a1e21c90
TI		 1426 return 0;
1427}
1da177e4 1428
a1e21c90
TI		 1429/* configure each codec instance */
1430static int __devinit azx_codec_configure(struct azx *chip)
1431{
1432 struct hda_codec *codec;
1433 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1434 snd_hda_codec_configure(codec);
1435 }
1da177e4
LT		 1436 return 0;
1437}
1438
1439
1440/*
1441 * PCM support
1442 */
1443
1444/* assign a stream for the PCM */
ef18bede
WF		 1445static inline struct azx_dev *
1446azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1447{
07e4ca50 1448 int dev, i, nums;
ef18bede
WF		 1449 struct azx_dev *res = NULL;
1450
1451 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1452 dev = chip->playback_index_offset;
1453 nums = chip->playback_streams;
1454 } else {
1455 dev = chip->capture_index_offset;
1456 nums = chip->capture_streams;
1457 }
1458 for (i = 0; i < nums; i++, dev++)
d01ce99f 1459 if (!chip->azx_dev[dev].opened) {
ef18bede
WF		 1460 res = &chip->azx_dev[dev];
1461 if (res->device == substream->pcm->device)
1462 break;
1da177e4 1463 }
ef18bede
WF		 1464 if (res) {
1465 res->opened = 1;
1466 res->device = substream->pcm->device;
1467 }
1468 return res;
1da177e4
LT		 1469}
1470
1471/* release the assigned stream */
a98f90fd 1472static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1473{
1474 azx_dev->opened = 0;
1475}
1476
a98f90fd 1477static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1478 .info = (SNDRV_PCM_INFO_MMAP |
1479 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1480 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1481 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1482 /* No full-resume yet implemented */
1483 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52
TI		 1484 SNDRV_PCM_INFO_PAUSE |
1485 SNDRV_PCM_INFO_SYNC_START),
1da177e4
LT		 1486 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1487 .rates = SNDRV_PCM_RATE_48000,
1488 .rate_min = 48000,
1489 .rate_max = 48000,
1490 .channels_min = 2,
1491 .channels_max = 2,
1492 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1493 .period_bytes_min = 128,
1494 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1495 .periods_min = 2,
1496 .periods_max = AZX_MAX_FRAG,
1497 .fifo_size = 0,
1498};
1499
1500struct azx_pcm {
a98f90fd 1501 struct azx *chip;
1da177e4
LT		 1502 struct hda_codec *codec;
1503 struct hda_pcm_stream *hinfo[2];
1504};
1505
a98f90fd 1506static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1507{
1508 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1509 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1510 struct azx *chip = apcm->chip;
1511 struct azx_dev *azx_dev;
1512 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1513 unsigned long flags;
1514 int err;
1515
62932df8 1516 mutex_lock(&chip->open_mutex);
ef18bede 1517 azx_dev = azx_assign_device(chip, substream);
1da177e4 1518 if (azx_dev == NULL) {
62932df8 1519 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1520 return -EBUSY;
1521 }
1522 runtime->hw = azx_pcm_hw;
1523 runtime->hw.channels_min = hinfo->channels_min;
1524 runtime->hw.channels_max = hinfo->channels_max;
1525 runtime->hw.formats = hinfo->formats;
1526 runtime->hw.rates = hinfo->rates;
1527 snd_pcm_limit_hw_rates(runtime);
1528 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5f1545bc
JD		 1529 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1530 128);
1531 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1532 128);
cb53c626 1533 snd_hda_power_up(apcm->codec);
d01ce99f
TI		 1534 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1535 if (err < 0) {
1da177e4 1536 azx_release_device(azx_dev);
cb53c626 1537 snd_hda_power_down(apcm->codec);
62932df8 1538 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1539 return err;
1540 }
70d321e6 1541 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1542 /* sanity check */
1543 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1544 snd_BUG_ON(!runtime->hw.channels_max) ||
1545 snd_BUG_ON(!runtime->hw.formats) ||
1546 snd_BUG_ON(!runtime->hw.rates)) {
1547 azx_release_device(azx_dev);
1548 hinfo->ops.close(hinfo, apcm->codec, substream);
1549 snd_hda_power_down(apcm->codec);
1550 mutex_unlock(&chip->open_mutex);
1551 return -EINVAL;
1552 }
1da177e4
LT		 1553 spin_lock_irqsave(&chip->reg_lock, flags);
1554 azx_dev->substream = substream;
1555 azx_dev->running = 0;
1556 spin_unlock_irqrestore(&chip->reg_lock, flags);
1557
1558 runtime->private_data = azx_dev;
850f0e52 1559 snd_pcm_set_sync(substream);
62932df8 1560 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1561 return 0;
1562}
1563
a98f90fd 1564static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1565{
1566 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1567 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1568 struct azx *chip = apcm->chip;
1569 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1570 unsigned long flags;
1571
62932df8 1572 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1573 spin_lock_irqsave(&chip->reg_lock, flags);
1574 azx_dev->substream = NULL;
1575 azx_dev->running = 0;
1576 spin_unlock_irqrestore(&chip->reg_lock, flags);
1577 azx_release_device(azx_dev);
1578 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1579 snd_hda_power_down(apcm->codec);
62932df8 1580 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1581 return 0;
1582}
1583
d01ce99f
TI		 1584static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1585 struct snd_pcm_hw_params *hw_params)
1da177e4 1586{
97b71c94
TI		 1587 struct azx_dev *azx_dev = get_azx_dev(substream);
1588
1589 azx_dev->bufsize = 0;
1590 azx_dev->period_bytes = 0;
1591 azx_dev->format_val = 0;
d01ce99f
TI		 1592 return snd_pcm_lib_malloc_pages(substream,
1593 params_buffer_bytes(hw_params));
1da177e4
LT		 1594}
1595
a98f90fd 1596static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1597{
1598 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1599 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1600 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1601
1602 /* reset BDL address */
1603 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1604 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1605 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1606 azx_dev->bufsize = 0;
1607 azx_dev->period_bytes = 0;
1608 azx_dev->format_val = 0;
1da177e4
LT		 1609
1610 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1611
1612 return snd_pcm_lib_free_pages(substream);
1613}
1614
a98f90fd 1615static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1616{
1617 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1618 struct azx *chip = apcm->chip;
1619 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1620 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1621 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94
TI		 1622 unsigned int bufsize, period_bytes, format_val;
1623 int err;
1da177e4 1624
fa00e046 1625 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1626 format_val = snd_hda_calc_stream_format(runtime->rate,
1627 runtime->channels,
1628 runtime->format,
1629 hinfo->maxbps);
1630 if (!format_val) {
d01ce99f
TI		 1631 snd_printk(KERN_ERR SFX
1632 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1633 runtime->rate, runtime->channels, runtime->format);
1634 return -EINVAL;
1635 }
1636
97b71c94
TI		 1637 bufsize = snd_pcm_lib_buffer_bytes(substream);
1638 period_bytes = snd_pcm_lib_period_bytes(substream);
1639
4abc1cc2 1640 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1641 bufsize, format_val);
1642
1643 if (bufsize != azx_dev->bufsize ||
1644 period_bytes != azx_dev->period_bytes ||
1645 format_val != azx_dev->format_val) {
1646 azx_dev->bufsize = bufsize;
1647 azx_dev->period_bytes = period_bytes;
1648 azx_dev->format_val = format_val;
1649 err = azx_setup_periods(chip, substream, azx_dev);
1650 if (err < 0)
1651 return err;
1652 }
1653
fa00e046
JK		 1654 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1655 (runtime->rate * 2);
1da177e4
LT		 1656 azx_setup_controller(chip, azx_dev);
1657 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1658 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1659 else
1660 azx_dev->fifo_size = 0;
1661
1662 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1663 azx_dev->format_val, substream);
1664}
1665
a98f90fd 1666static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1667{
1668 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1669 struct azx *chip = apcm->chip;
850f0e52
TI		 1670 struct azx_dev *azx_dev;
1671 struct snd_pcm_substream *s;
fa00e046 1672 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1673 int nwait, timeout;
1da177e4 1674
1da177e4 1675 switch (cmd) {
fa00e046
JK		 1676 case SNDRV_PCM_TRIGGER_START:
1677 rstart = 1;
1da177e4
LT		 1678 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1679 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1680 start = 1;
1da177e4
LT		 1681 break;
1682 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1683 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1684 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1685 start = 0;
1da177e4
LT		 1686 break;
1687 default:
850f0e52
TI		 1688 return -EINVAL;
1689 }
1690
1691 snd_pcm_group_for_each_entry(s, substream) {
1692 if (s->pcm->card != substream->pcm->card)
1693 continue;
1694 azx_dev = get_azx_dev(s);
1695 sbits |= 1 << azx_dev->index;
1696 nsync++;
1697 snd_pcm_trigger_done(s, substream);
1698 }
1699
1700 spin_lock(&chip->reg_lock);
1701 if (nsync > 1) {
1702 /* first, set SYNC bits of corresponding streams */
1703 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1704 }
1705 snd_pcm_group_for_each_entry(s, substream) {
1706 if (s->pcm->card != substream->pcm->card)
1707 continue;
1708 azx_dev = get_azx_dev(s);
fa00e046
JK		 1709 if (rstart) {
1710 azx_dev->start_flag = 1;
1711 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1712 }
850f0e52
TI		 1713 if (start)
1714 azx_stream_start(chip, azx_dev);
1715 else
1716 azx_stream_stop(chip, azx_dev);
1717 azx_dev->running = start;
1da177e4
LT		 1718 }
1719 spin_unlock(&chip->reg_lock);
850f0e52
TI		 1720 if (start) {
1721 if (nsync == 1)
1722 return 0;
1723 /* wait until all FIFOs get ready */
1724 for (timeout = 5000; timeout; timeout--) {
1725 nwait = 0;
1726 snd_pcm_group_for_each_entry(s, substream) {
1727 if (s->pcm->card != substream->pcm->card)
1728 continue;
1729 azx_dev = get_azx_dev(s);
1730 if (!(azx_sd_readb(azx_dev, SD_STS) &
1731 SD_STS_FIFO_READY))
1732 nwait++;
1733 }
1734 if (!nwait)
1735 break;
1736 cpu_relax();
1737 }
1738 } else {
1739 /* wait until all RUN bits are cleared */
1740 for (timeout = 5000; timeout; timeout--) {
1741 nwait = 0;
1742 snd_pcm_group_for_each_entry(s, substream) {
1743 if (s->pcm->card != substream->pcm->card)
1744 continue;
1745 azx_dev = get_azx_dev(s);
1746 if (azx_sd_readb(azx_dev, SD_CTL) &
1747 SD_CTL_DMA_START)
1748 nwait++;
1749 }
1750 if (!nwait)
1751 break;
1752 cpu_relax();
1753 }
1da177e4 1754 }
850f0e52
TI		 1755 if (nsync > 1) {
1756 spin_lock(&chip->reg_lock);
1757 /* reset SYNC bits */
1758 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1759 spin_unlock(&chip->reg_lock);
1760 }
1761 return 0;
1da177e4
LT		 1762}
1763
0e153474
JC		 1764/* get the current DMA position with correction on VIA chips */
1765static unsigned int azx_via_get_position(struct azx *chip,
1766 struct azx_dev *azx_dev)
1767{
1768 unsigned int link_pos, mini_pos, bound_pos;
1769 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1770 unsigned int fifo_size;
1771
1772 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1773 if (azx_dev->index >= 4) {
1774 /* Playback, no problem using link position */
1775 return link_pos;
1776 }
1777
1778 /* Capture */
1779 /* For new chipset,
1780 * use mod to get the DMA position just like old chipset
1781 */
1782 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1783 mod_dma_pos %= azx_dev->period_bytes;
1784
1785 /* azx_dev->fifo_size can't get FIFO size of in stream.
1786 * Get from base address + offset.
1787 */
1788 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1789
1790 if (azx_dev->insufficient) {
1791 /* Link position never gather than FIFO size */
1792 if (link_pos <= fifo_size)
1793 return 0;
1794
1795 azx_dev->insufficient = 0;
1796 }
1797
1798 if (link_pos <= fifo_size)
1799 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1800 else
1801 mini_pos = link_pos - fifo_size;
1802
1803 /* Find nearest previous boudary */
1804 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1805 mod_link_pos = link_pos % azx_dev->period_bytes;
1806 if (mod_link_pos >= fifo_size)
1807 bound_pos = link_pos - mod_link_pos;
1808 else if (mod_dma_pos >= mod_mini_pos)
1809 bound_pos = mini_pos - mod_mini_pos;
1810 else {
1811 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1812 if (bound_pos >= azx_dev->bufsize)
1813 bound_pos = 0;
1814 }
1815
1816 /* Calculate real DMA position we want */
1817 return bound_pos + mod_dma_pos;
1818}
1819
9ad593f6
TI		 1820static unsigned int azx_get_position(struct azx *chip,
1821 struct azx_dev *azx_dev)
1da177e4 1822{
1da177e4
LT		 1823 unsigned int pos;
1824
0e153474
JC		 1825 if (chip->via_dmapos_patch)
1826 pos = azx_via_get_position(chip, azx_dev);
1827 else if (chip->position_fix == POS_FIX_POSBUF ||
1828 chip->position_fix == POS_FIX_AUTO) {
c74db86b 1829 /* use the position buffer */
929861c6 1830 pos = le32_to_cpu(*azx_dev->posbuf);
c74db86b
TI		 1831 } else {
1832 /* read LPIB */
1833 pos = azx_sd_readl(azx_dev, SD_LPIB);
c74db86b 1834 }
1da177e4
LT		 1835 if (pos >= azx_dev->bufsize)
1836 pos = 0;
9ad593f6
TI		 1837 return pos;
1838}
1839
1840static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1841{
1842 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1843 struct azx *chip = apcm->chip;
1844 struct azx_dev *azx_dev = get_azx_dev(substream);
1845 return bytes_to_frames(substream->runtime,
1846 azx_get_position(chip, azx_dev));
1847}
1848
1849/*
1850 * Check whether the current DMA position is acceptable for updating
1851 * periods. Returns non-zero if it's OK.
1852 *
1853 * Many HD-audio controllers appear pretty inaccurate about
1854 * the update-IRQ timing. The IRQ is issued before actually the
1855 * data is processed. So, we need to process it afterwords in a
1856 * workqueue.
1857 */
1858static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1859{
1860 unsigned int pos;
1861
fa00e046
JK		 1862 if (azx_dev->start_flag &&
1863 time_before_eq(jiffies, azx_dev->start_jiffies))
1864 return -1; /* bogus (too early) interrupt */
1865 azx_dev->start_flag = 0;
1866
9ad593f6
TI		 1867 pos = azx_get_position(chip, azx_dev);
1868 if (chip->position_fix == POS_FIX_AUTO) {
1869 if (!pos) {
1870 printk(KERN_WARNING
1871 "hda-intel: Invalid position buffer, "
1872 "using LPIB read method instead.\n");
d2e1c973 1873 chip->position_fix = POS_FIX_LPIB;
9ad593f6
TI		 1874 pos = azx_get_position(chip, azx_dev);
1875 } else
1876 chip->position_fix = POS_FIX_POSBUF;
1877 }
1878
a62741cf
TI		 1879 if (!bdl_pos_adj[chip->dev_index])
1880 return 1; /* no delayed ack */
9ad593f6
TI		 1881 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1882 return 0; /* NG - it's below the period boundary */
1883 return 1; /* OK, it's fine */
1884}
1885
1886/*
1887 * The work for pending PCM period updates.
1888 */
1889static void azx_irq_pending_work(struct work_struct *work)
1890{
1891 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1892 int i, pending;
1893
a6a950a8
TI		 1894 if (!chip->irq_pending_warned) {
1895 printk(KERN_WARNING
1896 "hda-intel: IRQ timing workaround is activated "
1897 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1898 chip->card->number);
1899 chip->irq_pending_warned = 1;
1900 }
1901
9ad593f6
TI		 1902 for (;;) {
1903 pending = 0;
1904 spin_lock_irq(&chip->reg_lock);
1905 for (i = 0; i < chip->num_streams; i++) {
1906 struct azx_dev *azx_dev = &chip->azx_dev[i];
1907 if (!azx_dev->irq_pending ||
1908 !azx_dev->substream ||
1909 !azx_dev->running)
1910 continue;
1911 if (azx_position_ok(chip, azx_dev)) {
1912 azx_dev->irq_pending = 0;
1913 spin_unlock(&chip->reg_lock);
1914 snd_pcm_period_elapsed(azx_dev->substream);
1915 spin_lock(&chip->reg_lock);
1916 } else
1917 pending++;
1918 }
1919 spin_unlock_irq(&chip->reg_lock);
1920 if (!pending)
1921 return;
1922 cond_resched();
1923 }
1924}
1925
1926/* clear irq_pending flags and assure no on-going workq */
1927static void azx_clear_irq_pending(struct azx *chip)
1928{
1929 int i;
1930
1931 spin_lock_irq(&chip->reg_lock);
1932 for (i = 0; i < chip->num_streams; i++)
1933 chip->azx_dev[i].irq_pending = 0;
1934 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1935}
1936
a98f90fd 1937static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 1938 .open = azx_pcm_open,
1939 .close = azx_pcm_close,
1940 .ioctl = snd_pcm_lib_ioctl,
1941 .hw_params = azx_pcm_hw_params,
1942 .hw_free = azx_pcm_hw_free,
1943 .prepare = azx_pcm_prepare,
1944 .trigger = azx_pcm_trigger,
1945 .pointer = azx_pcm_pointer,
4ce107b9 1946 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 1947};
1948
a98f90fd 1949static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 1950{
176d5335
TI		 1951 struct azx_pcm *apcm = pcm->private_data;
1952 if (apcm) {
1953 apcm->chip->pcm[pcm->device] = NULL;
1954 kfree(apcm);
1955 }
1da177e4
LT		 1956}
1957
176d5335 1958static int
33fa35ed
TI		 1959azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1960 struct hda_pcm *cpcm)
1da177e4 1961{
33fa35ed 1962 struct azx *chip = bus->private_data;
a98f90fd 1963 struct snd_pcm *pcm;
1da177e4 1964 struct azx_pcm *apcm;
176d5335
TI		 1965 int pcm_dev = cpcm->device;
1966 int s, err;
1da177e4 1967
176d5335
TI		 1968 if (pcm_dev >= AZX_MAX_PCMS) {
1969 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1970 pcm_dev);
da3cec35 1971 return -EINVAL;
176d5335
TI		 1972 }
1973 if (chip->pcm[pcm_dev]) {
1974 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1975 return -EBUSY;
1976 }
1977 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1978 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1979 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 1980 &pcm);
1981 if (err < 0)
1982 return err;
18cb7109 1983 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 1984 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 1985 if (apcm == NULL)
1986 return -ENOMEM;
1987 apcm->chip = chip;
1988 apcm->codec = codec;
1da177e4
LT		 1989 pcm->private_data = apcm;
1990 pcm->private_free = azx_pcm_free;
176d5335
TI		 1991 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1992 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1993 chip->pcm[pcm_dev] = pcm;
1994 cpcm->pcm = pcm;
1995 for (s = 0; s < 2; s++) {
1996 apcm->hinfo[s] = &cpcm->stream[s];
1997 if (cpcm->stream[s].substreams)
1998 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1999 }
2000 /* buffer pre-allocation */
4ce107b9 2001 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2002 snd_dma_pci_data(chip->pci),
fc4abee8 2003 1024 * 64, 32 * 1024 * 1024);
1da177e4
LT		 2004 return 0;
2005}
2006
2007/*
2008 * mixer creation - all stuff is implemented in hda module
2009 */
a98f90fd 2010static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2011{
2012 return snd_hda_build_controls(chip->bus);
2013}
2014
2015
2016/*
2017 * initialize SD streams
2018 */
a98f90fd 2019static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2020{
2021 int i;
2022
2023 /* initialize each stream (aka device)
d01ce99f
TI		 2024 * assign the starting bdl address to each stream (device)
2025 * and initialize
1da177e4 2026 */
07e4ca50 2027 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2028 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2029 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2030 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2031 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2032 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2033 azx_dev->sd_int_sta_mask = 1 << i;
2034 /* stream tag: must be non-zero and unique */
2035 azx_dev->index = i;
2036 azx_dev->stream_tag = i + 1;
2037 }
2038
2039 return 0;
2040}
2041
68e7fffc
TI		 2042static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2043{
437a5a46
TI		 2044 if (request_irq(chip->pci->irq, azx_interrupt,
2045 chip->msi ? 0 : IRQF_SHARED,
68e7fffc
TI		 2046 "HDA Intel", chip)) {
2047 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2048 "disabling device\n", chip->pci->irq);
2049 if (do_disconnect)
2050 snd_card_disconnect(chip->card);
2051 return -1;
2052 }
2053 chip->irq = chip->pci->irq;
69e13418 2054 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2055 return 0;
2056}
2057
1da177e4 2058
cb53c626
TI		 2059static void azx_stop_chip(struct azx *chip)
2060{
95e99fda 2061 if (!chip->initialized)
cb53c626
TI		 2062 return;
2063
2064 /* disable interrupts */
2065 azx_int_disable(chip);
2066 azx_int_clear(chip);
2067
2068 /* disable CORB/RIRB */
2069 azx_free_cmd_io(chip);
2070
2071 /* disable position buffer */
2072 azx_writel(chip, DPLBASE, 0);
2073 azx_writel(chip, DPUBASE, 0);
2074
2075 chip->initialized = 0;
2076}
2077
2078#ifdef CONFIG_SND_HDA_POWER_SAVE
2079/* power-up/down the controller */
33fa35ed 2080static void azx_power_notify(struct hda_bus *bus)
cb53c626 2081{
33fa35ed 2082 struct azx *chip = bus->private_data;
cb53c626
TI		 2083 struct hda_codec *c;
2084 int power_on = 0;
2085
33fa35ed 2086 list_for_each_entry(c, &bus->codec_list, list) {
cb53c626
TI		 2087 if (c->power_on) {
2088 power_on = 1;
2089 break;
2090 }
2091 }
2092 if (power_on)
2093 azx_init_chip(chip);
0287d970
WF		 2094 else if (chip->running && power_save_controller &&
2095 !bus->power_keep_link_on)
cb53c626 2096 azx_stop_chip(chip);
cb53c626 2097}
5c0b9bec
TI		 2098#endif /* CONFIG_SND_HDA_POWER_SAVE */
2099
2100#ifdef CONFIG_PM
2101/*
2102 * power management
2103 */
986862bd
TI		 2104
2105static int snd_hda_codecs_inuse(struct hda_bus *bus)
2106{
2107 struct hda_codec *codec;
2108
2109 list_for_each_entry(codec, &bus->codec_list, list) {
2110 if (snd_hda_codec_needs_resume(codec))
2111 return 1;
2112 }
2113 return 0;
2114}
cb53c626 2115
421a1252 2116static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2117{
421a1252
TI		 2118 struct snd_card *card = pci_get_drvdata(pci);
2119 struct azx *chip = card->private_data;
1da177e4
LT		 2120 int i;
2121
421a1252 2122 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2123 azx_clear_irq_pending(chip);
7ba72ba1 2124 for (i = 0; i < AZX_MAX_PCMS; i++)
421a1252 2125 snd_pcm_suspend_all(chip->pcm[i]);
0b7a2e9c 2126 if (chip->initialized)
8dd78330 2127 snd_hda_suspend(chip->bus);
cb53c626 2128 azx_stop_chip(chip);
30b35399 2129 if (chip->irq >= 0) {
43001c95 2130 free_irq(chip->irq, chip);
30b35399
TI		 2131 chip->irq = -1;
2132 }
68e7fffc 2133 if (chip->msi)
43001c95 2134 pci_disable_msi(chip->pci);
421a1252
TI		 2135 pci_disable_device(pci);
2136 pci_save_state(pci);
30b35399 2137 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 2138 return 0;
2139}
2140
421a1252 2141static int azx_resume(struct pci_dev *pci)
1da177e4 2142{
421a1252
TI		 2143 struct snd_card *card = pci_get_drvdata(pci);
2144 struct azx *chip = card->private_data;
1da177e4 2145
d14a7e0b
TI		 2146 pci_set_power_state(pci, PCI_D0);
2147 pci_restore_state(pci);
30b35399
TI		 2148 if (pci_enable_device(pci) < 0) {
2149 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2150 "disabling device\n");
2151 snd_card_disconnect(card);
2152 return -EIO;
2153 }
2154 pci_set_master(pci);
68e7fffc
TI		 2155 if (chip->msi)
2156 if (pci_enable_msi(pci) < 0)
2157 chip->msi = 0;
2158 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2159 return -EIO;
cb53c626 2160 azx_init_pci(chip);
d804ad92
ML		 2161
2162 if (snd_hda_codecs_inuse(chip->bus))
2163 azx_init_chip(chip);
2164
1da177e4 2165 snd_hda_resume(chip->bus);
421a1252 2166 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2167 return 0;
2168}
2169#endif /* CONFIG_PM */
2170
2171
0cbf0098
TI		 2172/*
2173 * reboot notifier for hang-up problem at power-down
2174 */
2175static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2176{
2177 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2178 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2179 azx_stop_chip(chip);
2180 return NOTIFY_OK;
2181}
2182
2183static void azx_notifier_register(struct azx *chip)
2184{
2185 chip->reboot_notifier.notifier_call = azx_halt;
2186 register_reboot_notifier(&chip->reboot_notifier);
2187}
2188
2189static void azx_notifier_unregister(struct azx *chip)
2190{
2191 if (chip->reboot_notifier.notifier_call)
2192 unregister_reboot_notifier(&chip->reboot_notifier);
2193}
2194
1da177e4
LT		 2195/*
2196 * destructor
2197 */
a98f90fd 2198static int azx_free(struct azx *chip)
1da177e4 2199{
4ce107b9
TI		 2200 int i;
2201
0cbf0098
TI		 2202 azx_notifier_unregister(chip);
2203
ce43fbae 2204 if (chip->initialized) {
9ad593f6 2205 azx_clear_irq_pending(chip);
07e4ca50 2206 for (i = 0; i < chip->num_streams; i++)
1da177e4 2207 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2208 azx_stop_chip(chip);
1da177e4
LT		 2209 }
2210
f000fd80 2211 if (chip->irq >= 0)
1da177e4 2212 free_irq(chip->irq, (void*)chip);
68e7fffc 2213 if (chip->msi)
30b35399 2214 pci_disable_msi(chip->pci);
f079c25a
TI		 2215 if (chip->remap_addr)
2216 iounmap(chip->remap_addr);
1da177e4 2217
4ce107b9
TI		 2218 if (chip->azx_dev) {
2219 for (i = 0; i < chip->num_streams; i++)
2220 if (chip->azx_dev[i].bdl.area)
2221 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2222 }
1da177e4
LT		 2223 if (chip->rb.area)
2224 snd_dma_free_pages(&chip->rb);
1da177e4
LT		 2225 if (chip->posbuf.area)
2226 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT		 2227 pci_release_regions(chip->pci);
2228 pci_disable_device(chip->pci);
07e4ca50 2229 kfree(chip->azx_dev);
1da177e4
LT		 2230 kfree(chip);
2231
2232 return 0;
2233}
2234
a98f90fd 2235static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2236{
2237 return azx_free(device->device_data);
2238}
2239
3372a153
TI		 2240/*
2241 * white/black-listing for position_fix
2242 */
623ec047 2243static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2244 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2245 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2246 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2247 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
45d4ebf1 2248 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3372a153
TI		 2249 {}
2250};
2251
2252static int __devinit check_position_fix(struct azx *chip, int fix)
2253{
2254 const struct snd_pci_quirk *q;
2255
c673ba1c
TI		 2256 switch (fix) {
2257 case POS_FIX_LPIB:
2258 case POS_FIX_POSBUF:
2259 return fix;
2260 }
2261
2262 /* Check VIA/ATI HD Audio Controller exist */
2263 switch (chip->driver_type) {
2264 case AZX_DRIVER_VIA:
2265 case AZX_DRIVER_ATI:
0e153474
JC		 2266 chip->via_dmapos_patch = 1;
2267 /* Use link position directly, avoid any transfer problem. */
2268 return POS_FIX_LPIB;
2269 }
2270 chip->via_dmapos_patch = 0;
2271
c673ba1c
TI		 2272 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2273 if (q) {
2274 printk(KERN_INFO
2275 "hda_intel: position_fix set to %d "
2276 "for device %04x:%04x\n",
2277 q->value, q->subvendor, q->subdevice);
2278 return q->value;
3372a153 2279 }
c673ba1c 2280 return POS_FIX_AUTO;
3372a153
TI		 2281}
2282
669ba27a
TI		 2283/*
2284 * black-lists for probe_mask
2285 */
2286static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2287 /* Thinkpad often breaks the controller communication when accessing
2288 * to the non-working (or non-existing) modem codec slot.
2289 */
2290 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2291 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2292 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2293 /* broken BIOS */
2294 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2295 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2296 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2297 /* forced codec slots */
93574844 2298 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2299 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
669ba27a
TI		 2300 {}
2301};
2302
f1eaaeec
TI		 2303#define AZX_FORCE_CODEC_MASK 0x100
2304
5aba4f8e 2305static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2306{
2307 const struct snd_pci_quirk *q;
2308
f1eaaeec
TI		 2309 chip->codec_probe_mask = probe_mask[dev];
2310 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2311 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2312 if (q) {
2313 printk(KERN_INFO
2314 "hda_intel: probe_mask set to 0x%x "
2315 "for device %04x:%04x\n",
2316 q->value, q->subvendor, q->subdevice);
f1eaaeec 2317 chip->codec_probe_mask = q->value;
669ba27a
TI		 2318 }
2319 }
f1eaaeec
TI		 2320
2321 /* check forced option */
2322 if (chip->codec_probe_mask != -1 &&
2323 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2324 chip->codec_mask = chip->codec_probe_mask & 0xff;
2325 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2326 chip->codec_mask);
2327 }
669ba27a
TI		 2328}
2329
4d8e22e0 2330/*
71623855 2331 * white/black-list for enable_msi
4d8e22e0 2332 */
71623855 2333static struct snd_pci_quirk msi_black_list[] __devinitdata = {
9dc8398b 2334 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
4d8e22e0
TI		 2335 {}
2336};
2337
2338static void __devinit check_msi(struct azx *chip)
2339{
2340 const struct snd_pci_quirk *q;
2341
71623855
TI		 2342 if (enable_msi >= 0) {
2343 chip->msi = !!enable_msi;
4d8e22e0 2344 return;
71623855
TI		 2345 }
2346 chip->msi = 1; /* enable MSI as default */
2347 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 2348 if (q) {
2349 printk(KERN_INFO
2350 "hda_intel: msi for device %04x:%04x set to %d\n",
2351 q->subvendor, q->subdevice, q->value);
2352 chip->msi = q->value;
2353 }
2354}
2355
669ba27a 2356
1da177e4
LT		 2357/*
2358 * constructor
2359 */
a98f90fd 2360static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
5aba4f8e 2361 int dev, int driver_type,
a98f90fd 2362 struct azx **rchip)
1da177e4 2363{
a98f90fd 2364 struct azx *chip;
4ce107b9 2365 int i, err;
bcd72003 2366 unsigned short gcap;
a98f90fd 2367 static struct snd_device_ops ops = {
1da177e4
LT		 2368 .dev_free = azx_dev_free,
2369 };
2370
2371 *rchip = NULL;
bcd72003 2372
927fc866
PM		 2373 err = pci_enable_device(pci);
2374 if (err < 0)
1da177e4
LT		 2375 return err;
2376
e560d8d8 2377 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2378 if (!chip) {
1da177e4
LT		 2379 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2380 pci_disable_device(pci);
2381 return -ENOMEM;
2382 }
2383
2384 spin_lock_init(&chip->reg_lock);
62932df8 2385 mutex_init(&chip->open_mutex);
1da177e4
LT		 2386 chip->card = card;
2387 chip->pci = pci;
2388 chip->irq = -1;
07e4ca50 2389 chip->driver_type = driver_type;
4d8e22e0 2390 check_msi(chip);
555e219f 2391 chip->dev_index = dev;
9ad593f6 2392 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1da177e4 2393
5aba4f8e
TI		 2394 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2395 check_probe_mask(chip, dev);
3372a153 2396
27346166 2397 chip->single_cmd = single_cmd;
c74db86b 2398
5c0d7bc1
TI		 2399 if (bdl_pos_adj[dev] < 0) {
2400 switch (chip->driver_type) {
0c6341ac
TI		 2401 case AZX_DRIVER_ICH:
2402 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 2403 break;
2404 default:
0c6341ac 2405 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 2406 break;
2407 }
2408 }
2409
07e4ca50
TI		 2410#if BITS_PER_LONG != 64
2411 /* Fix up base address on ULI M5461 */
2412 if (chip->driver_type == AZX_DRIVER_ULI) {
2413 u16 tmp3;
2414 pci_read_config_word(pci, 0x40, &tmp3);
2415 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2416 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2417 }
2418#endif
2419
927fc866
PM		 2420 err = pci_request_regions(pci, "ICH HD audio");
2421 if (err < 0) {
1da177e4
LT		 2422 kfree(chip);
2423 pci_disable_device(pci);
2424 return err;
2425 }
2426
927fc866 2427 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 2428 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 2429 if (chip->remap_addr == NULL) {
2430 snd_printk(KERN_ERR SFX "ioremap error\n");
2431 err = -ENXIO;
2432 goto errout;
2433 }
2434
68e7fffc
TI		 2435 if (chip->msi)
2436 if (pci_enable_msi(pci) < 0)
2437 chip->msi = 0;
7376d013 2438
68e7fffc 2439 if (azx_acquire_irq(chip, 0) < 0) {
1da177e4
LT		 2440 err = -EBUSY;
2441 goto errout;
2442 }
1da177e4
LT		 2443
2444 pci_set_master(pci);
2445 synchronize_irq(chip->irq);
2446
bcd72003 2447 gcap = azx_readw(chip, GCAP);
4abc1cc2 2448 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 2449
dc4c2e6b
AB		 2450 /* disable SB600 64bit support for safety */
2451 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2452 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2453 struct pci_dev *p_smbus;
2454 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2455 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2456 NULL);
2457 if (p_smbus) {
2458 if (p_smbus->revision < 0x30)
2459 gcap &= ~ICH6_GCAP_64OK;
2460 pci_dev_put(p_smbus);
2461 }
2462 }
09240cf4 2463
396087ea
JK		 2464 /* disable 64bit DMA address for Teradici */
2465 /* it does not work with device 6549:1200 subsys e4a2:040b */
2466 if (chip->driver_type == AZX_DRIVER_TERA)
2467 gcap &= ~ICH6_GCAP_64OK;
2468
cf7aaca8 2469 /* allow 64bit DMA address if supported by H/W */
b21fadb9 2470 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 2471 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 2472 else {
e930438c
YH		 2473 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2474 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 2475 }
cf7aaca8 2476
8b6ed8e7
TI		 2477 /* read number of streams from GCAP register instead of using
2478 * hardcoded value
2479 */
2480 chip->capture_streams = (gcap >> 8) & 0x0f;
2481 chip->playback_streams = (gcap >> 12) & 0x0f;
2482 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 2483 /* gcap didn't give any info, switching to old method */
2484
2485 switch (chip->driver_type) {
2486 case AZX_DRIVER_ULI:
2487 chip->playback_streams = ULI_NUM_PLAYBACK;
2488 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 2489 break;
2490 case AZX_DRIVER_ATIHDMI:
2491 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2492 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 2493 break;
c4da29ca 2494 case AZX_DRIVER_GENERIC:
bcd72003
TD		 2495 default:
2496 chip->playback_streams = ICH6_NUM_PLAYBACK;
2497 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 2498 break;
2499 }
07e4ca50 2500 }
8b6ed8e7
TI		 2501 chip->capture_index_offset = 0;
2502 chip->playback_index_offset = chip->capture_streams;
07e4ca50 2503 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 2504 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2505 GFP_KERNEL);
927fc866 2506 if (!chip->azx_dev) {
4abc1cc2 2507 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
07e4ca50
TI		 2508 goto errout;
2509 }
2510
4ce107b9
TI		 2511 for (i = 0; i < chip->num_streams; i++) {
2512 /* allocate memory for the BDL for each stream */
2513 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2514 snd_dma_pci_data(chip->pci),
2515 BDL_SIZE, &chip->azx_dev[i].bdl);
2516 if (err < 0) {
2517 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2518 goto errout;
2519 }
1da177e4 2520 }
0be3b5d3 2521 /* allocate memory for the position buffer */
d01ce99f
TI		 2522 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2523 snd_dma_pci_data(chip->pci),
2524 chip->num_streams * 8, &chip->posbuf);
2525 if (err < 0) {
0be3b5d3
TI		 2526 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2527 goto errout;
1da177e4 2528 }
1da177e4 2529 /* allocate CORB/RIRB */
81740861
TI		 2530 err = azx_alloc_cmd_io(chip);
2531 if (err < 0)
2532 goto errout;
1da177e4
LT		 2533
2534 /* initialize streams */
2535 azx_init_stream(chip);
2536
2537 /* initialize chip */
cb53c626 2538 azx_init_pci(chip);
1da177e4
LT		 2539 azx_init_chip(chip);
2540
2541 /* codec detection */
927fc866 2542 if (!chip->codec_mask) {
1da177e4
LT		 2543 snd_printk(KERN_ERR SFX "no codecs found!\n");
2544 err = -ENODEV;
2545 goto errout;
2546 }
2547
d01ce99f
TI		 2548 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2549 if (err <0) {
1da177e4
LT		 2550 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2551 goto errout;
2552 }
2553
07e4ca50 2554 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 2555 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2556 sizeof(card->shortname));
2557 snprintf(card->longname, sizeof(card->longname),
2558 "%s at 0x%lx irq %i",
2559 card->shortname, chip->addr, chip->irq);
07e4ca50 2560
1da177e4
LT		 2561 *rchip = chip;
2562 return 0;
2563
2564 errout:
2565 azx_free(chip);
2566 return err;
2567}
2568
cb53c626
TI		 2569static void power_down_all_codecs(struct azx *chip)
2570{
2571#ifdef CONFIG_SND_HDA_POWER_SAVE
2572 /* The codecs were powered up in snd_hda_codec_new().
2573 * Now all initialization done, so turn them down if possible
2574 */
2575 struct hda_codec *codec;
2576 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2577 snd_hda_power_down(codec);
2578 }
2579#endif
2580}
2581
d01ce99f
TI		 2582static int __devinit azx_probe(struct pci_dev *pci,
2583 const struct pci_device_id *pci_id)
1da177e4 2584{
5aba4f8e 2585 static int dev;
a98f90fd
TI		 2586 struct snd_card *card;
2587 struct azx *chip;
927fc866 2588 int err;
1da177e4 2589
5aba4f8e
TI		 2590 if (dev >= SNDRV_CARDS)
2591 return -ENODEV;
2592 if (!enable[dev]) {
2593 dev++;
2594 return -ENOENT;
2595 }
2596
e58de7ba
TI		 2597 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2598 if (err < 0) {
1da177e4 2599 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 2600 return err;
1da177e4
LT		 2601 }
2602
4ea6fbc8
TI		 2603 /* set this here since it's referred in snd_hda_load_patch() */
2604 snd_card_set_dev(card, &pci->dev);
2605
5aba4f8e 2606 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2607 if (err < 0)
2608 goto out_free;
421a1252 2609 card->private_data = chip;
1da177e4 2610
2dca0bba
JK		 2611#ifdef CONFIG_SND_HDA_INPUT_BEEP
2612 chip->beep_mode = beep_mode[dev];
2613#endif
2614
1da177e4 2615 /* create codec instances */
a1e21c90 2616 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 2617 if (err < 0)
2618 goto out_free;
4ea6fbc8
TI		 2619#ifdef CONFIG_SND_HDA_PATCH_LOADER
2620 if (patch[dev]) {
2621 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2622 patch[dev]);
2623 err = snd_hda_load_patch(chip->bus, patch[dev]);
2624 if (err < 0)
2625 goto out_free;
2626 }
2627#endif
a1e21c90
TI		 2628 if (!probe_only[dev]) {
2629 err = azx_codec_configure(chip);
2630 if (err < 0)
2631 goto out_free;
2632 }
1da177e4
LT		 2633
2634 /* create PCM streams */
176d5335 2635 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 2636 if (err < 0)
2637 goto out_free;
1da177e4
LT		 2638
2639 /* create mixer controls */
d01ce99f 2640 err = azx_mixer_create(chip);
41dda0fd
WF		 2641 if (err < 0)
2642 goto out_free;
1da177e4 2643
d01ce99f 2644 err = snd_card_register(card);
41dda0fd
WF		 2645 if (err < 0)
2646 goto out_free;
1da177e4
LT		 2647
2648 pci_set_drvdata(pci, card);
cb53c626
TI		 2649 chip->running = 1;
2650 power_down_all_codecs(chip);
0cbf0098 2651 azx_notifier_register(chip);
1da177e4 2652
e25bcdba 2653 dev++;
1da177e4 2654 return err;
41dda0fd
WF		 2655out_free:
2656 snd_card_free(card);
2657 return err;
1da177e4
LT		 2658}
2659
2660static void __devexit azx_remove(struct pci_dev *pci)
2661{
2662 snd_card_free(pci_get_drvdata(pci));
2663 pci_set_drvdata(pci, NULL);
2664}
2665
2666/* PCI IDs */
cebe41d4 2667static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
87218e9c
TI		 2668 /* ICH 6..10 */
2669 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2670 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2671 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2672 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
abbc9d1b 2673 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2674 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2675 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2676 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2677 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
b29c2360
SH		 2678 /* PCH */
2679 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
87218e9c
TI		 2680 /* SCH */
2681 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2682 /* ATI SB 450/600 */
2683 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2684 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2685 /* ATI HDMI */
2686 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2687 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2688 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
9e6dd47b 2689 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
87218e9c
TI		 2690 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2691 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2692 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2693 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2694 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2695 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2696 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2697 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2698 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2699 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2700 /* VIA VT8251/VT8237A */
2701 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2702 /* SIS966 */
2703 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2704 /* ULI M5461 */
2705 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2706 /* NVIDIA MCP */
0c2fd1bf
TI		 2707 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2708 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2709 .class_mask = 0xffffff,
2710 .driver_data = AZX_DRIVER_NVIDIA },
f269002e
KY		 2711 /* Teradici */
2712 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
4e01f54b 2713 /* Creative X-Fi (CA0110-IBG) */
313f6e2d
TI		 2714#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2715 /* the following entry conflicts with snd-ctxfi driver,
2716 * as ctxfi driver mutates from HD-audio to native mode with
2717 * a special command sequence.
2718 */
4e01f54b
TI		 2719 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2720 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2721 .class_mask = 0xffffff,
2722 .driver_data = AZX_DRIVER_GENERIC },
313f6e2d
TI		 2723#else
2724 /* this entry seems still valid -- i.e. without emu20kx chip */
2725 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2726#endif
9176b672 2727 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2728 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2729 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2730 .class_mask = 0xffffff,
2731 .driver_data = AZX_DRIVER_GENERIC },
9176b672
AB		 2732 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2733 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2734 .class_mask = 0xffffff,
2735 .driver_data = AZX_DRIVER_GENERIC },
1da177e4
LT		 2736 { 0, }
2737};
2738MODULE_DEVICE_TABLE(pci, azx_ids);
2739
2740/* pci_driver definition */
2741static struct pci_driver driver = {
2742 .name = "HDA Intel",
2743 .id_table = azx_ids,
2744 .probe = azx_probe,
2745 .remove = __devexit_p(azx_remove),
421a1252
TI		 2746#ifdef CONFIG_PM
2747 .suspend = azx_suspend,
2748 .resume = azx_resume,
2749#endif
1da177e4
LT		 2750};
2751
2752static int __init alsa_card_azx_init(void)
2753{
01d25d46 2754 return pci_register_driver(&driver);
1da177e4
LT		 2755}
2756
2757static void __exit alsa_card_azx_exit(void)
2758{
2759 pci_unregister_driver(&driver);
2760}
2761
2762module_init(alsa_card_azx_init)
2763module_exit(alsa_card_azx_exit)
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