]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - sound/pci/hda/hda_intel.c
[ALSA] hda-codec - Allocate amp hash array dynamically
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT
1/*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
4 *
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
6 *
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 *
24 * CONTACTS:
25 *
26 * Matt Jared matt.jared@intel.com
27 * Andy Kopp andy.kopp@intel.com
28 * Dan Kogan dan.d.kogan@intel.com
29 *
30 * CHANGES:
31 *
32 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
33 *
34 */
35
36#include <sound/driver.h>
37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
40#include <linux/module.h>
41#include <linux/moduleparam.h>
42#include <linux/init.h>
43#include <linux/slab.h>
44#include <linux/pci.h>
45#include <sound/core.h>
46#include <sound/initval.h>
47#include "hda_codec.h"
48
49
b7fe4622
CL
50static int index = SNDRV_DEFAULT_IDX1;
51static char *id = SNDRV_DEFAULT_STR1;
52static char *model;
53static int position_fix;
1da177e4 54
b7fe4622 55module_param(index, int, 0444);
1da177e4 56MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
b7fe4622 57module_param(id, charp, 0444);
1da177e4 58MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
b7fe4622 59module_param(model, charp, 0444);
1da177e4 60MODULE_PARM_DESC(model, "Use the given board model.");
b7fe4622 61module_param(position_fix, int, 0444);
0be3b5d3 62MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
1da177e4 63
2b3e584b
TI
64/* just for backward compatibility */
65static int enable;
698444f3 66module_param(enable, bool, 0444);
2b3e584b 67
1da177e4
LT
68MODULE_LICENSE("GPL");
69MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
70 "{Intel, ICH6M},"
2f1b3818 71 "{Intel, ICH7},"
f5d40b30 72 "{Intel, ESB2},"
fc20a562
TI
73 "{ATI, SB450},"
74 "{VIA, VT8251},"
47672310 75 "{VIA, VT8237A},"
07e4ca50
TI
76 "{SiS, SIS966},"
77 "{ULI, M5461}}");
1da177e4
LT
78MODULE_DESCRIPTION("Intel HDA driver");
79
80#define SFX "hda-intel: "
81
82/*
83 * registers
84 */
85#define ICH6_REG_GCAP 0x00
86#define ICH6_REG_VMIN 0x02
87#define ICH6_REG_VMAJ 0x03
88#define ICH6_REG_OUTPAY 0x04
89#define ICH6_REG_INPAY 0x06
90#define ICH6_REG_GCTL 0x08
91#define ICH6_REG_WAKEEN 0x0c
92#define ICH6_REG_STATESTS 0x0e
93#define ICH6_REG_GSTS 0x10
94#define ICH6_REG_INTCTL 0x20
95#define ICH6_REG_INTSTS 0x24
96#define ICH6_REG_WALCLK 0x30
97#define ICH6_REG_SYNC 0x34
98#define ICH6_REG_CORBLBASE 0x40
99#define ICH6_REG_CORBUBASE 0x44
100#define ICH6_REG_CORBWP 0x48
101#define ICH6_REG_CORBRP 0x4A
102#define ICH6_REG_CORBCTL 0x4c
103#define ICH6_REG_CORBSTS 0x4d
104#define ICH6_REG_CORBSIZE 0x4e
105
106#define ICH6_REG_RIRBLBASE 0x50
107#define ICH6_REG_RIRBUBASE 0x54
108#define ICH6_REG_RIRBWP 0x58
109#define ICH6_REG_RINTCNT 0x5a
110#define ICH6_REG_RIRBCTL 0x5c
111#define ICH6_REG_RIRBSTS 0x5d
112#define ICH6_REG_RIRBSIZE 0x5e
113
114#define ICH6_REG_IC 0x60
115#define ICH6_REG_IR 0x64
116#define ICH6_REG_IRS 0x68
117#define ICH6_IRS_VALID (1<<1)
118#define ICH6_IRS_BUSY (1<<0)
119
120#define ICH6_REG_DPLBASE 0x70
121#define ICH6_REG_DPUBASE 0x74
122#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
123
124/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
125enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
126
127/* stream register offsets from stream base */
128#define ICH6_REG_SD_CTL 0x00
129#define ICH6_REG_SD_STS 0x03
130#define ICH6_REG_SD_LPIB 0x04
131#define ICH6_REG_SD_CBL 0x08
132#define ICH6_REG_SD_LVI 0x0c
133#define ICH6_REG_SD_FIFOW 0x0e
134#define ICH6_REG_SD_FIFOSIZE 0x10
135#define ICH6_REG_SD_FORMAT 0x12
136#define ICH6_REG_SD_BDLPL 0x18
137#define ICH6_REG_SD_BDLPU 0x1c
138
139/* PCI space */
140#define ICH6_PCIREG_TCSEL 0x44
141
142/*
143 * other constants
144 */
145
146/* max number of SDs */
07e4ca50
TI
147/* ICH, ATI and VIA have 4 playback and 4 capture */
148#define ICH6_CAPTURE_INDEX 0
149#define ICH6_NUM_CAPTURE 4
150#define ICH6_PLAYBACK_INDEX 4
151#define ICH6_NUM_PLAYBACK 4
152
153/* ULI has 6 playback and 5 capture */
154#define ULI_CAPTURE_INDEX 0
155#define ULI_NUM_CAPTURE 5
156#define ULI_PLAYBACK_INDEX 5
157#define ULI_NUM_PLAYBACK 6
158
159/* this number is statically defined for simplicity */
160#define MAX_AZX_DEV 16
161
1da177e4 162/* max number of fragments - we may use more if allocating more pages for BDL */
07e4ca50
TI
163#define BDL_SIZE PAGE_ALIGN(8192)
164#define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
1da177e4
LT
165/* max buffer size - no h/w limit, you can increase as you like */
166#define AZX_MAX_BUF_SIZE (1024*1024*1024)
167/* max number of PCM devics per card */
ec9e1c5c
TI
168#define AZX_MAX_AUDIO_PCMS 6
169#define AZX_MAX_MODEM_PCMS 2
170#define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
1da177e4
LT
171
172/* RIRB int mask: overrun[2], response[0] */
173#define RIRB_INT_RESPONSE 0x01
174#define RIRB_INT_OVERRUN 0x04
175#define RIRB_INT_MASK 0x05
176
177/* STATESTS int mask: SD2,SD1,SD0 */
178#define STATESTS_INT_MASK 0x07
f5d40b30 179#define AZX_MAX_CODECS 4
1da177e4
LT
180
181/* SD_CTL bits */
182#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
183#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
184#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
185#define SD_CTL_STREAM_TAG_SHIFT 20
186
187/* SD_CTL and SD_STS */
188#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
189#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
190#define SD_INT_COMPLETE 0x04 /* completion interrupt */
191#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
192
193/* SD_STS */
194#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
195
196/* INTCTL and INTSTS */
197#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
198#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
199#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
200
41e2fce4
M
201/* GCTL unsolicited response enable bit */
202#define ICH6_GCTL_UREN (1<<8)
203
1da177e4
LT
204/* GCTL reset bit */
205#define ICH6_GCTL_RESET (1<<0)
206
207/* CORB/RIRB control, read/write pointer */
208#define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
209#define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
210#define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
211/* below are so far hardcoded - should read registers in future */
212#define ICH6_MAX_CORB_ENTRIES 256
213#define ICH6_MAX_RIRB_ENTRIES 256
214
c74db86b
TI
215/* position fix mode */
216enum {
0be3b5d3 217 POS_FIX_AUTO,
c74db86b 218 POS_FIX_NONE,
0be3b5d3
TI
219 POS_FIX_POSBUF,
220 POS_FIX_FIFO,
c74db86b 221};
1da177e4 222
f5d40b30 223/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL
224#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
225#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
226
da3fca21
V
227/* Defines for Nvidia HDA support */
228#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
229#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
f5d40b30 230
1da177e4
LT
231/*
232 * Use CORB/RIRB for communication from/to codecs.
233 * This is the way recommended by Intel (see below).
234 */
235#define USE_CORB_RIRB
236
1da177e4
LT
237/*
238 */
239
240typedef struct snd_azx azx_t;
241typedef struct snd_azx_rb azx_rb_t;
242typedef struct snd_azx_dev azx_dev_t;
243
244struct snd_azx_dev {
245 u32 *bdl; /* virtual address of the BDL */
246 dma_addr_t bdl_addr; /* physical address of the BDL */
247 volatile u32 *posbuf; /* position buffer pointer */
248
249 unsigned int bufsize; /* size of the play buffer in bytes */
250 unsigned int fragsize; /* size of each period in bytes */
251 unsigned int frags; /* number for period in the play buffer */
252 unsigned int fifo_size; /* FIFO size */
0be3b5d3 253 unsigned int last_pos; /* last updated period position */
1da177e4
LT
254
255 void __iomem *sd_addr; /* stream descriptor pointer */
256
257 u32 sd_int_sta_mask; /* stream int status mask */
258
259 /* pcm support */
260 snd_pcm_substream_t *substream; /* assigned substream, set in PCM open */
261 unsigned int format_val; /* format value to be set in the controller and the codec */
262 unsigned char stream_tag; /* assigned stream */
263 unsigned char index; /* stream index */
264
265 unsigned int opened: 1;
266 unsigned int running: 1;
0be3b5d3 267 unsigned int period_updating: 1;
1da177e4
LT
268};
269
270/* CORB/RIRB */
271struct snd_azx_rb {
272 u32 *buf; /* CORB/RIRB buffer
273 * Each CORB entry is 4byte, RIRB is 8byte
274 */
275 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
276 /* for RIRB */
277 unsigned short rp, wp; /* read/write pointers */
278 int cmds; /* number of pending requests */
279 u32 res; /* last read value */
280};
281
282struct snd_azx {
283 snd_card_t *card;
284 struct pci_dev *pci;
285
07e4ca50
TI
286 /* chip type specific */
287 int driver_type;
288 int playback_streams;
289 int playback_index_offset;
290 int capture_streams;
291 int capture_index_offset;
292 int num_streams;
293
1da177e4
LT
294 /* pci resources */
295 unsigned long addr;
296 void __iomem *remap_addr;
297 int irq;
298
299 /* locks */
300 spinlock_t reg_lock;
301 struct semaphore open_mutex;
302
07e4ca50
TI
303 /* streams (x num_streams) */
304 azx_dev_t *azx_dev;
1da177e4
LT
305
306 /* PCM */
307 unsigned int pcm_devs;
308 snd_pcm_t *pcm[AZX_MAX_PCMS];
309
310 /* HD codec */
311 unsigned short codec_mask;
312 struct hda_bus *bus;
313
314 /* CORB/RIRB */
315 azx_rb_t corb;
316 azx_rb_t rirb;
317
318 /* BDL, CORB/RIRB and position buffers */
319 struct snd_dma_buffer bdl;
320 struct snd_dma_buffer rb;
321 struct snd_dma_buffer posbuf;
c74db86b
TI
322
323 /* flags */
324 int position_fix;
ce43fbae 325 unsigned int initialized: 1;
1da177e4
LT
326};
327
07e4ca50
TI
328/* driver types */
329enum {
330 AZX_DRIVER_ICH,
331 AZX_DRIVER_ATI,
332 AZX_DRIVER_VIA,
333 AZX_DRIVER_SIS,
334 AZX_DRIVER_ULI,
da3fca21 335 AZX_DRIVER_NVIDIA,
07e4ca50
TI
336};
337
338static char *driver_short_names[] __devinitdata = {
339 [AZX_DRIVER_ICH] = "HDA Intel",
340 [AZX_DRIVER_ATI] = "HDA ATI SB",
341 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
342 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V
343 [AZX_DRIVER_ULI] = "HDA ULI M5461",
344 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
07e4ca50
TI
345};
346
1da177e4
LT
347/*
348 * macros for easy use
349 */
350#define azx_writel(chip,reg,value) \
351 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
352#define azx_readl(chip,reg) \
353 readl((chip)->remap_addr + ICH6_REG_##reg)
354#define azx_writew(chip,reg,value) \
355 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
356#define azx_readw(chip,reg) \
357 readw((chip)->remap_addr + ICH6_REG_##reg)
358#define azx_writeb(chip,reg,value) \
359 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
360#define azx_readb(chip,reg) \
361 readb((chip)->remap_addr + ICH6_REG_##reg)
362
363#define azx_sd_writel(dev,reg,value) \
364 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
365#define azx_sd_readl(dev,reg) \
366 readl((dev)->sd_addr + ICH6_REG_##reg)
367#define azx_sd_writew(dev,reg,value) \
368 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
369#define azx_sd_readw(dev,reg) \
370 readw((dev)->sd_addr + ICH6_REG_##reg)
371#define azx_sd_writeb(dev,reg,value) \
372 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
373#define azx_sd_readb(dev,reg) \
374 readb((dev)->sd_addr + ICH6_REG_##reg)
375
376/* for pcm support */
377#define get_azx_dev(substream) (azx_dev_t*)(substream->runtime->private_data)
378
379/* Get the upper 32bit of the given dma_addr_t
380 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
381 */
382#define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
383
384
385/*
386 * Interface for HD codec
387 */
388
389#ifdef USE_CORB_RIRB
390/*
391 * CORB / RIRB interface
392 */
393static int azx_alloc_cmd_io(azx_t *chip)
394{
395 int err;
396
397 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
398 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
399 PAGE_SIZE, &chip->rb);
400 if (err < 0) {
401 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
402 return err;
403 }
404 return 0;
405}
406
407static void azx_init_cmd_io(azx_t *chip)
408{
409 /* CORB set up */
410 chip->corb.addr = chip->rb.addr;
411 chip->corb.buf = (u32 *)chip->rb.area;
412 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
413 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
414
07e4ca50
TI
415 /* set the corb size to 256 entries (ULI requires explicitly) */
416 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT
417 /* set the corb write pointer to 0 */
418 azx_writew(chip, CORBWP, 0);
419 /* reset the corb hw read pointer */
420 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
421 /* enable corb dma */
422 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
423
424 /* RIRB set up */
425 chip->rirb.addr = chip->rb.addr + 2048;
426 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
427 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
428 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
429
07e4ca50
TI
430 /* set the rirb size to 256 entries (ULI requires explicitly) */
431 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4
LT
432 /* reset the rirb hw write pointer */
433 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
434 /* set N=1, get RIRB response interrupt for new entry */
435 azx_writew(chip, RINTCNT, 1);
436 /* enable rirb dma and response irq */
437#ifdef USE_CORB_RIRB
438 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
439#else
440 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN);
441#endif
442 chip->rirb.rp = chip->rirb.cmds = 0;
443}
444
445static void azx_free_cmd_io(azx_t *chip)
446{
447 /* disable ringbuffer DMAs */
448 azx_writeb(chip, RIRBCTL, 0);
449 azx_writeb(chip, CORBCTL, 0);
450}
451
452/* send a command */
453static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
454 unsigned int verb, unsigned int para)
455{
456 azx_t *chip = codec->bus->private_data;
457 unsigned int wp;
458 u32 val;
459
460 val = (u32)(codec->addr & 0x0f) << 28;
461 val |= (u32)direct << 27;
462 val |= (u32)nid << 20;
463 val |= verb << 8;
464 val |= para;
465
466 /* add command to corb */
467 wp = azx_readb(chip, CORBWP);
468 wp++;
469 wp %= ICH6_MAX_CORB_ENTRIES;
470
471 spin_lock_irq(&chip->reg_lock);
472 chip->rirb.cmds++;
473 chip->corb.buf[wp] = cpu_to_le32(val);
474 azx_writel(chip, CORBWP, wp);
475 spin_unlock_irq(&chip->reg_lock);
476
477 return 0;
478}
479
480#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
481
482/* retrieve RIRB entry - called from interrupt handler */
483static void azx_update_rirb(azx_t *chip)
484{
485 unsigned int rp, wp;
486 u32 res, res_ex;
487
488 wp = azx_readb(chip, RIRBWP);
489 if (wp == chip->rirb.wp)
490 return;
491 chip->rirb.wp = wp;
492
493 while (chip->rirb.rp != wp) {
494 chip->rirb.rp++;
495 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
496
497 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
498 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
499 res = le32_to_cpu(chip->rirb.buf[rp]);
500 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
501 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
502 else if (chip->rirb.cmds) {
503 chip->rirb.cmds--;
504 chip->rirb.res = res;
505 }
506 }
507}
508
509/* receive a response */
510static unsigned int azx_get_response(struct hda_codec *codec)
511{
512 azx_t *chip = codec->bus->private_data;
513 int timeout = 50;
514
515 while (chip->rirb.cmds) {
516 if (! --timeout) {
517 snd_printk(KERN_ERR "azx_get_response timeout\n");
518 chip->rirb.rp = azx_readb(chip, RIRBWP);
519 chip->rirb.cmds = 0;
520 return -1;
521 }
522 msleep(1);
523 }
524 return chip->rirb.res; /* the last value */
525}
526
527#else
528/*
529 * Use the single immediate command instead of CORB/RIRB for simplicity
530 *
531 * Note: according to Intel, this is not preferred use. The command was
532 * intended for the BIOS only, and may get confused with unsolicited
533 * responses. So, we shouldn't use it for normal operation from the
534 * driver.
535 * I left the codes, however, for debugging/testing purposes.
536 */
537
538#define azx_alloc_cmd_io(chip) 0
539#define azx_init_cmd_io(chip)
540#define azx_free_cmd_io(chip)
541
542/* send a command */
543static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
544 unsigned int verb, unsigned int para)
545{
546 azx_t *chip = codec->bus->private_data;
547 u32 val;
548 int timeout = 50;
549
550 val = (u32)(codec->addr & 0x0f) << 28;
551 val |= (u32)direct << 27;
552 val |= (u32)nid << 20;
553 val |= verb << 8;
554 val |= para;
555
556 while (timeout--) {
557 /* check ICB busy bit */
558 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
559 /* Clear IRV valid bit */
560 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
561 azx_writel(chip, IC, val);
562 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
563 return 0;
564 }
565 udelay(1);
566 }
567 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
568 return -EIO;
569}
570
571/* receive a response */
572static unsigned int azx_get_response(struct hda_codec *codec)
573{
574 azx_t *chip = codec->bus->private_data;
575 int timeout = 50;
576
577 while (timeout--) {
578 /* check IRV busy bit */
579 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
580 return azx_readl(chip, IR);
581 udelay(1);
582 }
583 snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
584 return (unsigned int)-1;
585}
586
587#define azx_update_rirb(chip)
588
589#endif /* USE_CORB_RIRB */
590
591/* reset codec link */
592static int azx_reset(azx_t *chip)
593{
594 int count;
595
596 /* reset controller */
597 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
598
599 count = 50;
600 while (azx_readb(chip, GCTL) && --count)
601 msleep(1);
602
603 /* delay for >= 100us for codec PLL to settle per spec
604 * Rev 0.9 section 5.5.1
605 */
606 msleep(1);
607
608 /* Bring controller out of reset */
609 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
610
611 count = 50;
612 while (! azx_readb(chip, GCTL) && --count)
613 msleep(1);
614
615 /* Brent Chartrand said to wait >= 540us for codecs to intialize */
616 msleep(1);
617
618 /* check to see if controller is ready */
619 if (! azx_readb(chip, GCTL)) {
620 snd_printd("azx_reset: controller not ready!\n");
621 return -EBUSY;
622 }
623
41e2fce4
M
624 /* Accept unsolicited responses */
625 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
626
1da177e4
LT
627 /* detect codecs */
628 if (! chip->codec_mask) {
629 chip->codec_mask = azx_readw(chip, STATESTS);
630 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
631 }
632
633 return 0;
634}
635
636
637/*
638 * Lowlevel interface
639 */
640
641/* enable interrupts */
642static void azx_int_enable(azx_t *chip)
643{
644 /* enable controller CIE and GIE */
645 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
646 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
647}
648
649/* disable interrupts */
650static void azx_int_disable(azx_t *chip)
651{
652 int i;
653
654 /* disable interrupts in stream descriptor */
07e4ca50 655 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT
656 azx_dev_t *azx_dev = &chip->azx_dev[i];
657 azx_sd_writeb(azx_dev, SD_CTL,
658 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
659 }
660
661 /* disable SIE for all streams */
662 azx_writeb(chip, INTCTL, 0);
663
664 /* disable controller CIE and GIE */
665 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
666 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
667}
668
669/* clear interrupts */
670static void azx_int_clear(azx_t *chip)
671{
672 int i;
673
674 /* clear stream status */
07e4ca50 675 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT
676 azx_dev_t *azx_dev = &chip->azx_dev[i];
677 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
678 }
679
680 /* clear STATESTS */
681 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
682
683 /* clear rirb status */
684 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
685
686 /* clear int status */
687 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
688}
689
690/* start a stream */
691static void azx_stream_start(azx_t *chip, azx_dev_t *azx_dev)
692{
693 /* enable SIE */
694 azx_writeb(chip, INTCTL,
695 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
696 /* set DMA start and interrupt mask */
697 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
698 SD_CTL_DMA_START | SD_INT_MASK);
699}
700
701/* stop a stream */
702static void azx_stream_stop(azx_t *chip, azx_dev_t *azx_dev)
703{
704 /* stop DMA */
705 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
706 ~(SD_CTL_DMA_START | SD_INT_MASK));
707 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
708 /* disable SIE */
709 azx_writeb(chip, INTCTL,
710 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
711}
712
713
714/*
715 * initialize the chip
716 */
717static void azx_init_chip(azx_t *chip)
718{
da3fca21 719 unsigned char reg;
1da177e4
LT
720
721 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
722 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
723 * Ensuring these bits are 0 clears playback static on some HD Audio codecs
724 */
da3fca21
V
725 pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &reg);
726 pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, reg & 0xf8);
1da177e4
LT
727
728 /* reset controller */
729 azx_reset(chip);
730
731 /* initialize interrupts */
732 azx_int_clear(chip);
733 azx_int_enable(chip);
734
735 /* initialize the codec command I/O */
736 azx_init_cmd_io(chip);
737
0be3b5d3
TI
738 /* program the position buffer */
739 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
740 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
f5d40b30 741
da3fca21
V
742 switch (chip->driver_type) {
743 case AZX_DRIVER_ATI:
744 /* For ATI SB450 azalia HD audio, we need to enable snoop */
f5d40b30 745 pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
da3fca21 746 &reg);
f5d40b30 747 pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
da3fca21
V
748 (reg & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP);
749 break;
750 case AZX_DRIVER_NVIDIA:
751 /* For NVIDIA HDA, enable snoop */
752 pci_read_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, &reg);
753 pci_write_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR,
754 (reg & 0xf0) | NVIDIA_HDA_ENABLE_COHBITS);
755 break;
756 }
1da177e4
LT
757}
758
759
760/*
761 * interrupt handler
762 */
763static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs)
764{
765 azx_t *chip = dev_id;
766 azx_dev_t *azx_dev;
767 u32 status;
768 int i;
769
770 spin_lock(&chip->reg_lock);
771
772 status = azx_readl(chip, INTSTS);
773 if (status == 0) {
774 spin_unlock(&chip->reg_lock);
775 return IRQ_NONE;
776 }
777
07e4ca50 778 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT
779 azx_dev = &chip->azx_dev[i];
780 if (status & azx_dev->sd_int_sta_mask) {
781 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
782 if (azx_dev->substream && azx_dev->running) {
0be3b5d3 783 azx_dev->period_updating = 1;
1da177e4
LT
784 spin_unlock(&chip->reg_lock);
785 snd_pcm_period_elapsed(azx_dev->substream);
786 spin_lock(&chip->reg_lock);
0be3b5d3 787 azx_dev->period_updating = 0;
1da177e4
LT
788 }
789 }
790 }
791
792 /* clear rirb int */
793 status = azx_readb(chip, RIRBSTS);
794 if (status & RIRB_INT_MASK) {
795 if (status & RIRB_INT_RESPONSE)
796 azx_update_rirb(chip);
797 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
798 }
799
800#if 0
801 /* clear state status int */
802 if (azx_readb(chip, STATESTS) & 0x04)
803 azx_writeb(chip, STATESTS, 0x04);
804#endif
805 spin_unlock(&chip->reg_lock);
806
807 return IRQ_HANDLED;
808}
809
810
811/*
812 * set up BDL entries
813 */
814static void azx_setup_periods(azx_dev_t *azx_dev)
815{
816 u32 *bdl = azx_dev->bdl;
817 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
818 int idx;
819
820 /* reset BDL address */
821 azx_sd_writel(azx_dev, SD_BDLPL, 0);
822 azx_sd_writel(azx_dev, SD_BDLPU, 0);
823
824 /* program the initial BDL entries */
825 for (idx = 0; idx < azx_dev->frags; idx++) {
826 unsigned int off = idx << 2; /* 4 dword step */
827 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
828 /* program the address field of the BDL entry */
829 bdl[off] = cpu_to_le32((u32)addr);
830 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
831
832 /* program the size field of the BDL entry */
833 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
834
835 /* program the IOC to enable interrupt when buffer completes */
836 bdl[off+3] = cpu_to_le32(0x01);
837 }
838}
839
840/*
841 * set up the SD for streaming
842 */
843static int azx_setup_controller(azx_t *chip, azx_dev_t *azx_dev)
844{
845 unsigned char val;
846 int timeout;
847
848 /* make sure the run bit is zero for SD */
849 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
850 /* reset stream */
851 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
852 udelay(3);
853 timeout = 300;
854 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
855 --timeout)
856 ;
857 val &= ~SD_CTL_STREAM_RESET;
858 azx_sd_writeb(azx_dev, SD_CTL, val);
859 udelay(3);
860
861 timeout = 300;
862 /* waiting for hardware to report that the stream is out of reset */
863 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
864 --timeout)
865 ;
866
867 /* program the stream_tag */
868 azx_sd_writel(azx_dev, SD_CTL,
869 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
870 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
871
872 /* program the length of samples in cyclic buffer */
873 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
874
875 /* program the stream format */
876 /* this value needs to be the same as the one programmed */
877 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
878
879 /* program the stream LVI (last valid index) of the BDL */
880 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
881
882 /* program the BDL address */
883 /* lower BDL address */
884 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
885 /* upper BDL address */
886 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
887
0be3b5d3
TI
888 /* enable the position buffer */
889 if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
890 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
c74db86b 891
1da177e4
LT
892 /* set the interrupt enable bits in the descriptor control register */
893 azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
894
895 return 0;
896}
897
898
899/*
900 * Codec initialization
901 */
902
903static int __devinit azx_codec_create(azx_t *chip, const char *model)
904{
905 struct hda_bus_template bus_temp;
906 int c, codecs, err;
907
908 memset(&bus_temp, 0, sizeof(bus_temp));
909 bus_temp.private_data = chip;
910 bus_temp.modelname = model;
911 bus_temp.pci = chip->pci;
912 bus_temp.ops.command = azx_send_cmd;
913 bus_temp.ops.get_response = azx_get_response;
914
915 if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
916 return err;
917
918 codecs = 0;
919 for (c = 0; c < AZX_MAX_CODECS; c++) {
920 if (chip->codec_mask & (1 << c)) {
921 err = snd_hda_codec_new(chip->bus, c, NULL);
922 if (err < 0)
923 continue;
924 codecs++;
925 }
926 }
927 if (! codecs) {
928 snd_printk(KERN_ERR SFX "no codecs initialized\n");
929 return -ENXIO;
930 }
931
932 return 0;
933}
934
935
936/*
937 * PCM support
938 */
939
940/* assign a stream for the PCM */
941static inline azx_dev_t *azx_assign_device(azx_t *chip, int stream)
942{
07e4ca50
TI
943 int dev, i, nums;
944 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
945 dev = chip->playback_index_offset;
946 nums = chip->playback_streams;
947 } else {
948 dev = chip->capture_index_offset;
949 nums = chip->capture_streams;
950 }
951 for (i = 0; i < nums; i++, dev++)
1da177e4
LT
952 if (! chip->azx_dev[dev].opened) {
953 chip->azx_dev[dev].opened = 1;
954 return &chip->azx_dev[dev];
955 }
956 return NULL;
957}
958
959/* release the assigned stream */
960static inline void azx_release_device(azx_dev_t *azx_dev)
961{
962 azx_dev->opened = 0;
963}
964
965static snd_pcm_hardware_t azx_pcm_hw = {
966 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
967 SNDRV_PCM_INFO_BLOCK_TRANSFER |
968 SNDRV_PCM_INFO_MMAP_VALID |
47123197
JK
969 SNDRV_PCM_INFO_PAUSE /*|*/
970 /*SNDRV_PCM_INFO_RESUME*/),
1da177e4
LT
971 .formats = SNDRV_PCM_FMTBIT_S16_LE,
972 .rates = SNDRV_PCM_RATE_48000,
973 .rate_min = 48000,
974 .rate_max = 48000,
975 .channels_min = 2,
976 .channels_max = 2,
977 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
978 .period_bytes_min = 128,
979 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
980 .periods_min = 2,
981 .periods_max = AZX_MAX_FRAG,
982 .fifo_size = 0,
983};
984
985struct azx_pcm {
986 azx_t *chip;
987 struct hda_codec *codec;
988 struct hda_pcm_stream *hinfo[2];
989};
990
991static int azx_pcm_open(snd_pcm_substream_t *substream)
992{
993 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
994 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
995 azx_t *chip = apcm->chip;
996 azx_dev_t *azx_dev;
997 snd_pcm_runtime_t *runtime = substream->runtime;
998 unsigned long flags;
999 int err;
1000
1001 down(&chip->open_mutex);
1002 azx_dev = azx_assign_device(chip, substream->stream);
1003 if (azx_dev == NULL) {
1004 up(&chip->open_mutex);
1005 return -EBUSY;
1006 }
1007 runtime->hw = azx_pcm_hw;
1008 runtime->hw.channels_min = hinfo->channels_min;
1009 runtime->hw.channels_max = hinfo->channels_max;
1010 runtime->hw.formats = hinfo->formats;
1011 runtime->hw.rates = hinfo->rates;
1012 snd_pcm_limit_hw_rates(runtime);
1013 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1014 if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
1015 azx_release_device(azx_dev);
1016 up(&chip->open_mutex);
1017 return err;
1018 }
1019 spin_lock_irqsave(&chip->reg_lock, flags);
1020 azx_dev->substream = substream;
1021 azx_dev->running = 0;
1022 spin_unlock_irqrestore(&chip->reg_lock, flags);
1023
1024 runtime->private_data = azx_dev;
1025 up(&chip->open_mutex);
1026 return 0;
1027}
1028
1029static int azx_pcm_close(snd_pcm_substream_t *substream)
1030{
1031 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1032 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1033 azx_t *chip = apcm->chip;
1034 azx_dev_t *azx_dev = get_azx_dev(substream);
1035 unsigned long flags;
1036
1037 down(&chip->open_mutex);
1038 spin_lock_irqsave(&chip->reg_lock, flags);
1039 azx_dev->substream = NULL;
1040 azx_dev->running = 0;
1041 spin_unlock_irqrestore(&chip->reg_lock, flags);
1042 azx_release_device(azx_dev);
1043 hinfo->ops.close(hinfo, apcm->codec, substream);
1044 up(&chip->open_mutex);
1045 return 0;
1046}
1047
1048static int azx_pcm_hw_params(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *hw_params)
1049{
1050 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1051}
1052
1053static int azx_pcm_hw_free(snd_pcm_substream_t *substream)
1054{
1055 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1056 azx_dev_t *azx_dev = get_azx_dev(substream);
1057 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1058
1059 /* reset BDL address */
1060 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1061 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1062 azx_sd_writel(azx_dev, SD_CTL, 0);
1063
1064 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1065
1066 return snd_pcm_lib_free_pages(substream);
1067}
1068
1069static int azx_pcm_prepare(snd_pcm_substream_t *substream)
1070{
1071 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1072 azx_t *chip = apcm->chip;
1073 azx_dev_t *azx_dev = get_azx_dev(substream);
1074 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1075 snd_pcm_runtime_t *runtime = substream->runtime;
1076
1077 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1078 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1079 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1080 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1081 runtime->channels,
1082 runtime->format,
1083 hinfo->maxbps);
1084 if (! azx_dev->format_val) {
1085 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
1086 runtime->rate, runtime->channels, runtime->format);
1087 return -EINVAL;
1088 }
1089
1090 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1091 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1092 azx_setup_periods(azx_dev);
1093 azx_setup_controller(chip, azx_dev);
1094 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1095 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1096 else
1097 azx_dev->fifo_size = 0;
0be3b5d3 1098 azx_dev->last_pos = 0;
1da177e4
LT
1099
1100 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1101 azx_dev->format_val, substream);
1102}
1103
1104static int azx_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
1105{
1106 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1107 azx_dev_t *azx_dev = get_azx_dev(substream);
1108 azx_t *chip = apcm->chip;
1109 int err = 0;
1110
1111 spin_lock(&chip->reg_lock);
1112 switch (cmd) {
1113 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1114 case SNDRV_PCM_TRIGGER_RESUME:
1115 case SNDRV_PCM_TRIGGER_START:
1116 azx_stream_start(chip, azx_dev);
1117 azx_dev->running = 1;
1118 break;
1119 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1120 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT
1121 case SNDRV_PCM_TRIGGER_STOP:
1122 azx_stream_stop(chip, azx_dev);
1123 azx_dev->running = 0;
1124 break;
1125 default:
1126 err = -EINVAL;
1127 }
1128 spin_unlock(&chip->reg_lock);
1129 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
47123197 1130 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1da177e4
LT
1131 cmd == SNDRV_PCM_TRIGGER_STOP) {
1132 int timeout = 5000;
1133 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1134 ;
1135 }
1136 return err;
1137}
1138
1139static snd_pcm_uframes_t azx_pcm_pointer(snd_pcm_substream_t *substream)
1140{
c74db86b
TI
1141 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1142 azx_t *chip = apcm->chip;
1da177e4
LT
1143 azx_dev_t *azx_dev = get_azx_dev(substream);
1144 unsigned int pos;
1145
c74db86b
TI
1146 if (chip->position_fix == POS_FIX_POSBUF) {
1147 /* use the position buffer */
1148 pos = *azx_dev->posbuf;
1149 } else {
1150 /* read LPIB */
1151 pos = azx_sd_readl(azx_dev, SD_LPIB);
1152 if (chip->position_fix == POS_FIX_FIFO)
1153 pos += azx_dev->fifo_size;
e8dede5a 1154#if 0 /* disabled temprarily, auto-correction doesn't work well... */
0be3b5d3
TI
1155 else if (chip->position_fix == POS_FIX_AUTO && azx_dev->period_updating) {
1156 /* check the validity of DMA position */
1157 unsigned int diff = 0;
1158 azx_dev->last_pos += azx_dev->fragsize;
1159 if (azx_dev->last_pos > pos)
1160 diff = azx_dev->last_pos - pos;
1161 if (azx_dev->last_pos >= azx_dev->bufsize) {
1162 if (pos < azx_dev->fragsize)
1163 diff = 0;
1164 azx_dev->last_pos = 0;
1165 }
1166 if (diff > 0 && diff <= azx_dev->fifo_size)
1167 pos += azx_dev->fifo_size;
1168 else {
1169 snd_printdd(KERN_INFO "hda_intel: DMA position fix %d, switching to posbuf\n", diff);
1170 chip->position_fix = POS_FIX_POSBUF;
1171 pos = *azx_dev->posbuf;
1172 }
1173 azx_dev->period_updating = 0;
1174 }
e8dede5a
TI
1175#else
1176 else if (chip->position_fix == POS_FIX_AUTO)
1177 pos += azx_dev->fifo_size;
1178#endif
c74db86b 1179 }
1da177e4
LT
1180 if (pos >= azx_dev->bufsize)
1181 pos = 0;
1182 return bytes_to_frames(substream->runtime, pos);
1183}
1184
1185static snd_pcm_ops_t azx_pcm_ops = {
1186 .open = azx_pcm_open,
1187 .close = azx_pcm_close,
1188 .ioctl = snd_pcm_lib_ioctl,
1189 .hw_params = azx_pcm_hw_params,
1190 .hw_free = azx_pcm_hw_free,
1191 .prepare = azx_pcm_prepare,
1192 .trigger = azx_pcm_trigger,
1193 .pointer = azx_pcm_pointer,
1194};
1195
1196static void azx_pcm_free(snd_pcm_t *pcm)
1197{
1198 kfree(pcm->private_data);
1199}
1200
1201static int __devinit create_codec_pcm(azx_t *chip, struct hda_codec *codec,
1202 struct hda_pcm *cpcm, int pcm_dev)
1203{
1204 int err;
1205 snd_pcm_t *pcm;
1206 struct azx_pcm *apcm;
1207
1208 snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL);
1209 snd_assert(cpcm->name, return -EINVAL);
1210
1211 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1212 cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1213 &pcm);
1214 if (err < 0)
1215 return err;
1216 strcpy(pcm->name, cpcm->name);
1217 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1218 if (apcm == NULL)
1219 return -ENOMEM;
1220 apcm->chip = chip;
1221 apcm->codec = codec;
1222 apcm->hinfo[0] = &cpcm->stream[0];
1223 apcm->hinfo[1] = &cpcm->stream[1];
1224 pcm->private_data = apcm;
1225 pcm->private_free = azx_pcm_free;
1226 if (cpcm->stream[0].substreams)
1227 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1228 if (cpcm->stream[1].substreams)
1229 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1230 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1231 snd_dma_pci_data(chip->pci),
1232 1024 * 64, 1024 * 128);
1233 chip->pcm[pcm_dev] = pcm;
47123197 1234 chip->pcm_devs = pcm_dev + 1;
1da177e4
LT
1235
1236 return 0;
1237}
1238
1239static int __devinit azx_pcm_create(azx_t *chip)
1240{
1241 struct list_head *p;
1242 struct hda_codec *codec;
1243 int c, err;
1244 int pcm_dev;
1245
1246 if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1247 return err;
1248
ec9e1c5c 1249 /* create audio PCMs */
1da177e4
LT
1250 pcm_dev = 0;
1251 list_for_each(p, &chip->bus->codec_list) {
1252 codec = list_entry(p, struct hda_codec, list);
1253 for (c = 0; c < codec->num_pcms; c++) {
ec9e1c5c
TI
1254 if (codec->pcm_info[c].is_modem)
1255 continue; /* create later */
1256 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1257 snd_printk(KERN_ERR SFX "Too many audio PCMs\n");
1258 return -EINVAL;
1259 }
1260 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1261 if (err < 0)
1262 return err;
1263 pcm_dev++;
1264 }
1265 }
1266
1267 /* create modem PCMs */
1268 pcm_dev = AZX_MAX_AUDIO_PCMS;
1269 list_for_each(p, &chip->bus->codec_list) {
1270 codec = list_entry(p, struct hda_codec, list);
1271 for (c = 0; c < codec->num_pcms; c++) {
1272 if (! codec->pcm_info[c].is_modem)
1273 continue; /* already created */
a28f1cda 1274 if (pcm_dev >= AZX_MAX_PCMS) {
ec9e1c5c 1275 snd_printk(KERN_ERR SFX "Too many modem PCMs\n");
1da177e4
LT
1276 return -EINVAL;
1277 }
1278 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1279 if (err < 0)
1280 return err;
6632d198 1281 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1da177e4
LT
1282 pcm_dev++;
1283 }
1284 }
1285 return 0;
1286}
1287
1288/*
1289 * mixer creation - all stuff is implemented in hda module
1290 */
1291static int __devinit azx_mixer_create(azx_t *chip)
1292{
1293 return snd_hda_build_controls(chip->bus);
1294}
1295
1296
1297/*
1298 * initialize SD streams
1299 */
1300static int __devinit azx_init_stream(azx_t *chip)
1301{
1302 int i;
1303
1304 /* initialize each stream (aka device)
1305 * assign the starting bdl address to each stream (device) and initialize
1306 */
07e4ca50 1307 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT
1308 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1309 azx_dev_t *azx_dev = &chip->azx_dev[i];
1310 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1311 azx_dev->bdl_addr = chip->bdl.addr + off;
0be3b5d3 1312 azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8);
1da177e4
LT
1313 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1314 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1315 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1316 azx_dev->sd_int_sta_mask = 1 << i;
1317 /* stream tag: must be non-zero and unique */
1318 azx_dev->index = i;
1319 azx_dev->stream_tag = i + 1;
1320 }
1321
1322 return 0;
1323}
1324
1325
1326#ifdef CONFIG_PM
1327/*
1328 * power management
1329 */
1330static int azx_suspend(snd_card_t *card, pm_message_t state)
1331{
1332 azx_t *chip = card->pm_private_data;
1333 int i;
1334
1335 for (i = 0; i < chip->pcm_devs; i++)
1336 if (chip->pcm[i])
1337 snd_pcm_suspend_all(chip->pcm[i]);
1338 snd_hda_suspend(chip->bus, state);
1339 azx_free_cmd_io(chip);
1340 pci_disable_device(chip->pci);
1341 return 0;
1342}
1343
1344static int azx_resume(snd_card_t *card)
1345{
1346 azx_t *chip = card->pm_private_data;
1347
1348 pci_enable_device(chip->pci);
1349 pci_set_master(chip->pci);
1350 azx_init_chip(chip);
1351 snd_hda_resume(chip->bus);
1352 return 0;
1353}
1354#endif /* CONFIG_PM */
1355
1356
1357/*
1358 * destructor
1359 */
1360static int azx_free(azx_t *chip)
1361{
ce43fbae 1362 if (chip->initialized) {
1da177e4
LT
1363 int i;
1364
07e4ca50 1365 for (i = 0; i < chip->num_streams; i++)
1da177e4
LT
1366 azx_stream_stop(chip, &chip->azx_dev[i]);
1367
1368 /* disable interrupts */
1369 azx_int_disable(chip);
1370 azx_int_clear(chip);
1371
1372 /* disable CORB/RIRB */
1373 azx_free_cmd_io(chip);
1374
1375 /* disable position buffer */
1376 azx_writel(chip, DPLBASE, 0);
1377 azx_writel(chip, DPUBASE, 0);
1378
1379 /* wait a little for interrupts to finish */
1380 msleep(1);
1da177e4
LT
1381 }
1382
07e4ca50
TI
1383 if (chip->remap_addr)
1384 iounmap(chip->remap_addr);
1da177e4
LT
1385 if (chip->irq >= 0)
1386 free_irq(chip->irq, (void*)chip);
1387
1388 if (chip->bdl.area)
1389 snd_dma_free_pages(&chip->bdl);
1390 if (chip->rb.area)
1391 snd_dma_free_pages(&chip->rb);
1da177e4
LT
1392 if (chip->posbuf.area)
1393 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT
1394 pci_release_regions(chip->pci);
1395 pci_disable_device(chip->pci);
07e4ca50 1396 kfree(chip->azx_dev);
1da177e4
LT
1397 kfree(chip);
1398
1399 return 0;
1400}
1401
1402static int azx_dev_free(snd_device_t *device)
1403{
1404 return azx_free(device->device_data);
1405}
1406
1407/*
1408 * constructor
1409 */
c74db86b 1410static int __devinit azx_create(snd_card_t *card, struct pci_dev *pci,
07e4ca50
TI
1411 int posfix, int driver_type,
1412 azx_t **rchip)
1da177e4
LT
1413{
1414 azx_t *chip;
1415 int err = 0;
1416 static snd_device_ops_t ops = {
1417 .dev_free = azx_dev_free,
1418 };
1419
1420 *rchip = NULL;
1421
1422 if ((err = pci_enable_device(pci)) < 0)
1423 return err;
1424
e560d8d8 1425 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT
1426
1427 if (NULL == chip) {
1428 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1429 pci_disable_device(pci);
1430 return -ENOMEM;
1431 }
1432
1433 spin_lock_init(&chip->reg_lock);
1434 init_MUTEX(&chip->open_mutex);
1435 chip->card = card;
1436 chip->pci = pci;
1437 chip->irq = -1;
07e4ca50 1438 chip->driver_type = driver_type;
1da177e4 1439
c74db86b
TI
1440 chip->position_fix = posfix;
1441
07e4ca50
TI
1442#if BITS_PER_LONG != 64
1443 /* Fix up base address on ULI M5461 */
1444 if (chip->driver_type == AZX_DRIVER_ULI) {
1445 u16 tmp3;
1446 pci_read_config_word(pci, 0x40, &tmp3);
1447 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1448 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1449 }
1450#endif
1451
1da177e4
LT
1452 if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) {
1453 kfree(chip);
1454 pci_disable_device(pci);
1455 return err;
1456 }
1457
1458 chip->addr = pci_resource_start(pci,0);
1459 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1460 if (chip->remap_addr == NULL) {
1461 snd_printk(KERN_ERR SFX "ioremap error\n");
1462 err = -ENXIO;
1463 goto errout;
1464 }
1465
1466 if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ,
1467 "HDA Intel", (void*)chip)) {
1468 snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq);
1469 err = -EBUSY;
1470 goto errout;
1471 }
1472 chip->irq = pci->irq;
1473
1474 pci_set_master(pci);
1475 synchronize_irq(chip->irq);
1476
07e4ca50
TI
1477 switch (chip->driver_type) {
1478 case AZX_DRIVER_ULI:
1479 chip->playback_streams = ULI_NUM_PLAYBACK;
1480 chip->capture_streams = ULI_NUM_CAPTURE;
1481 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1482 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1483 break;
1484 default:
1485 chip->playback_streams = ICH6_NUM_PLAYBACK;
1486 chip->capture_streams = ICH6_NUM_CAPTURE;
1487 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1488 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1489 break;
1490 }
1491 chip->num_streams = chip->playback_streams + chip->capture_streams;
1492 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), GFP_KERNEL);
1493 if (! chip->azx_dev) {
1494 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1495 goto errout;
1496 }
1497
1da177e4
LT
1498 /* allocate memory for the BDL for each stream */
1499 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
07e4ca50 1500 BDL_SIZE, &chip->bdl)) < 0) {
1da177e4
LT
1501 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1502 goto errout;
1503 }
0be3b5d3
TI
1504 /* allocate memory for the position buffer */
1505 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1506 chip->num_streams * 8, &chip->posbuf)) < 0) {
1507 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1508 goto errout;
1da177e4 1509 }
1da177e4
LT
1510 /* allocate CORB/RIRB */
1511 if ((err = azx_alloc_cmd_io(chip)) < 0)
1512 goto errout;
1513
1514 /* initialize streams */
1515 azx_init_stream(chip);
1516
1517 /* initialize chip */
1518 azx_init_chip(chip);
1519
ce43fbae
TI
1520 chip->initialized = 1;
1521
1da177e4
LT
1522 /* codec detection */
1523 if (! chip->codec_mask) {
1524 snd_printk(KERN_ERR SFX "no codecs found!\n");
1525 err = -ENODEV;
1526 goto errout;
1527 }
1528
1529 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1530 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1531 goto errout;
1532 }
1533
07e4ca50
TI
1534 strcpy(card->driver, "HDA-Intel");
1535 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1536 sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1537
1da177e4
LT
1538 *rchip = chip;
1539 return 0;
1540
1541 errout:
1542 azx_free(chip);
1543 return err;
1544}
1545
1546static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1547{
1da177e4
LT
1548 snd_card_t *card;
1549 azx_t *chip;
1550 int err = 0;
1551
b7fe4622 1552 card = snd_card_new(index, id, THIS_MODULE, 0);
1da177e4
LT
1553 if (NULL == card) {
1554 snd_printk(KERN_ERR SFX "Error creating card!\n");
1555 return -ENOMEM;
1556 }
1557
b7fe4622 1558 if ((err = azx_create(card, pci, position_fix, pci_id->driver_data,
07e4ca50 1559 &chip)) < 0) {
1da177e4
LT
1560 snd_card_free(card);
1561 return err;
1562 }
1563
1da177e4 1564 /* create codec instances */
b7fe4622 1565 if ((err = azx_codec_create(chip, model)) < 0) {
1da177e4
LT
1566 snd_card_free(card);
1567 return err;
1568 }
1569
1570 /* create PCM streams */
1571 if ((err = azx_pcm_create(chip)) < 0) {
1572 snd_card_free(card);
1573 return err;
1574 }
1575
1576 /* create mixer controls */
1577 if ((err = azx_mixer_create(chip)) < 0) {
1578 snd_card_free(card);
1579 return err;
1580 }
1581
1582 snd_card_set_pm_callback(card, azx_suspend, azx_resume, chip);
1583 snd_card_set_dev(card, &pci->dev);
1584
1585 if ((err = snd_card_register(card)) < 0) {
1586 snd_card_free(card);
1587 return err;
1588 }
1589
1590 pci_set_drvdata(pci, card);
1da177e4
LT
1591
1592 return err;
1593}
1594
1595static void __devexit azx_remove(struct pci_dev *pci)
1596{
1597 snd_card_free(pci_get_drvdata(pci));
1598 pci_set_drvdata(pci, NULL);
1599}
1600
1601/* PCI IDs */
1602static struct pci_device_id azx_ids[] = {
07e4ca50
TI
1603 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1604 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1605 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
1606 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
1607 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1608 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1609 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
da3fca21
V
1610 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA 026c */
1611 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA 0371 */
1da177e4
LT
1612 { 0, }
1613};
1614MODULE_DEVICE_TABLE(pci, azx_ids);
1615
1616/* pci_driver definition */
1617static struct pci_driver driver = {
1618 .name = "HDA Intel",
1619 .id_table = azx_ids,
1620 .probe = azx_probe,
1621 .remove = __devexit_p(azx_remove),
1622 SND_PCI_PM_CALLBACKS
1623};
1624
1625static int __init alsa_card_azx_init(void)
1626{
01d25d46 1627 return pci_register_driver(&driver);
1da177e4
LT
1628}
1629
1630static void __exit alsa_card_azx_exit(void)
1631{
1632 pci_unregister_driver(&driver);
1633}
1634
1635module_init(alsa_card_azx_init)
1636module_exit(alsa_card_azx_exit)