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CommitLineData
1da177e4
LT
1/*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
4 *
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
6 *
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 *
24 * CONTACTS:
25 *
26 * Matt Jared matt.jared@intel.com
27 * Andy Kopp andy.kopp@intel.com
28 * Dan Kogan dan.d.kogan@intel.com
29 *
30 * CHANGES:
31 *
32 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
33 *
34 */
35
36#include <sound/driver.h>
37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
362775e2 40#include <linux/kernel.h>
1da177e4
LT
41#include <linux/module.h>
42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
1da177e4
LT
47#include <sound/core.h>
48#include <sound/initval.h>
49#include "hda_codec.h"
50
51
b7fe4622
CL
52static int index = SNDRV_DEFAULT_IDX1;
53static char *id = SNDRV_DEFAULT_STR1;
54static char *model;
55static int position_fix;
954fa19a 56static int probe_mask = -1;
27346166 57static int single_cmd;
7376d013 58static int disable_msi;
1da177e4 59
b7fe4622 60module_param(index, int, 0444);
1da177e4 61MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
b7fe4622 62module_param(id, charp, 0444);
1da177e4 63MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
b7fe4622 64module_param(model, charp, 0444);
1da177e4 65MODULE_PARM_DESC(model, "Use the given board model.");
b7fe4622 66module_param(position_fix, int, 0444);
0be3b5d3 67MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
606ad75f
TI
68module_param(probe_mask, int, 0444);
69MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
27346166
TI
70module_param(single_cmd, bool, 0444);
71MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs (for debugging only).");
7376d013
SH
72module_param(disable_msi, int, 0);
73MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
606ad75f 74
1da177e4 75
2b3e584b
TI
76/* just for backward compatibility */
77static int enable;
698444f3 78module_param(enable, bool, 0444);
2b3e584b 79
1da177e4
LT
80MODULE_LICENSE("GPL");
81MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
82 "{Intel, ICH6M},"
2f1b3818 83 "{Intel, ICH7},"
f5d40b30 84 "{Intel, ESB2},"
d2981393 85 "{Intel, ICH8},"
fc20a562 86 "{ATI, SB450},"
89be83f8 87 "{ATI, SB600},"
778b6e1b 88 "{ATI, RS600},"
fc20a562 89 "{VIA, VT8251},"
47672310 90 "{VIA, VT8237A},"
07e4ca50
TI
91 "{SiS, SIS966},"
92 "{ULI, M5461}}");
1da177e4
LT
93MODULE_DESCRIPTION("Intel HDA driver");
94
95#define SFX "hda-intel: "
96
97/*
98 * registers
99 */
100#define ICH6_REG_GCAP 0x00
101#define ICH6_REG_VMIN 0x02
102#define ICH6_REG_VMAJ 0x03
103#define ICH6_REG_OUTPAY 0x04
104#define ICH6_REG_INPAY 0x06
105#define ICH6_REG_GCTL 0x08
106#define ICH6_REG_WAKEEN 0x0c
107#define ICH6_REG_STATESTS 0x0e
108#define ICH6_REG_GSTS 0x10
109#define ICH6_REG_INTCTL 0x20
110#define ICH6_REG_INTSTS 0x24
111#define ICH6_REG_WALCLK 0x30
112#define ICH6_REG_SYNC 0x34
113#define ICH6_REG_CORBLBASE 0x40
114#define ICH6_REG_CORBUBASE 0x44
115#define ICH6_REG_CORBWP 0x48
116#define ICH6_REG_CORBRP 0x4A
117#define ICH6_REG_CORBCTL 0x4c
118#define ICH6_REG_CORBSTS 0x4d
119#define ICH6_REG_CORBSIZE 0x4e
120
121#define ICH6_REG_RIRBLBASE 0x50
122#define ICH6_REG_RIRBUBASE 0x54
123#define ICH6_REG_RIRBWP 0x58
124#define ICH6_REG_RINTCNT 0x5a
125#define ICH6_REG_RIRBCTL 0x5c
126#define ICH6_REG_RIRBSTS 0x5d
127#define ICH6_REG_RIRBSIZE 0x5e
128
129#define ICH6_REG_IC 0x60
130#define ICH6_REG_IR 0x64
131#define ICH6_REG_IRS 0x68
132#define ICH6_IRS_VALID (1<<1)
133#define ICH6_IRS_BUSY (1<<0)
134
135#define ICH6_REG_DPLBASE 0x70
136#define ICH6_REG_DPUBASE 0x74
137#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
138
139/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
140enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
141
142/* stream register offsets from stream base */
143#define ICH6_REG_SD_CTL 0x00
144#define ICH6_REG_SD_STS 0x03
145#define ICH6_REG_SD_LPIB 0x04
146#define ICH6_REG_SD_CBL 0x08
147#define ICH6_REG_SD_LVI 0x0c
148#define ICH6_REG_SD_FIFOW 0x0e
149#define ICH6_REG_SD_FIFOSIZE 0x10
150#define ICH6_REG_SD_FORMAT 0x12
151#define ICH6_REG_SD_BDLPL 0x18
152#define ICH6_REG_SD_BDLPU 0x1c
153
154/* PCI space */
155#define ICH6_PCIREG_TCSEL 0x44
156
157/*
158 * other constants
159 */
160
161/* max number of SDs */
07e4ca50
TI
162/* ICH, ATI and VIA have 4 playback and 4 capture */
163#define ICH6_CAPTURE_INDEX 0
164#define ICH6_NUM_CAPTURE 4
165#define ICH6_PLAYBACK_INDEX 4
166#define ICH6_NUM_PLAYBACK 4
167
168/* ULI has 6 playback and 5 capture */
169#define ULI_CAPTURE_INDEX 0
170#define ULI_NUM_CAPTURE 5
171#define ULI_PLAYBACK_INDEX 5
172#define ULI_NUM_PLAYBACK 6
173
778b6e1b
FK
174/* ATI HDMI has 1 playback and 0 capture */
175#define ATIHDMI_CAPTURE_INDEX 0
176#define ATIHDMI_NUM_CAPTURE 0
177#define ATIHDMI_PLAYBACK_INDEX 0
178#define ATIHDMI_NUM_PLAYBACK 1
179
07e4ca50
TI
180/* this number is statically defined for simplicity */
181#define MAX_AZX_DEV 16
182
1da177e4 183/* max number of fragments - we may use more if allocating more pages for BDL */
07e4ca50
TI
184#define BDL_SIZE PAGE_ALIGN(8192)
185#define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
1da177e4
LT
186/* max buffer size - no h/w limit, you can increase as you like */
187#define AZX_MAX_BUF_SIZE (1024*1024*1024)
188/* max number of PCM devics per card */
ec9e1c5c
TI
189#define AZX_MAX_AUDIO_PCMS 6
190#define AZX_MAX_MODEM_PCMS 2
191#define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
1da177e4
LT
192
193/* RIRB int mask: overrun[2], response[0] */
194#define RIRB_INT_RESPONSE 0x01
195#define RIRB_INT_OVERRUN 0x04
196#define RIRB_INT_MASK 0x05
197
198/* STATESTS int mask: SD2,SD1,SD0 */
199#define STATESTS_INT_MASK 0x07
f5d40b30 200#define AZX_MAX_CODECS 4
1da177e4
LT
201
202/* SD_CTL bits */
203#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
204#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
205#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
206#define SD_CTL_STREAM_TAG_SHIFT 20
207
208/* SD_CTL and SD_STS */
209#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
210#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
211#define SD_INT_COMPLETE 0x04 /* completion interrupt */
212#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
213
214/* SD_STS */
215#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
216
217/* INTCTL and INTSTS */
218#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
219#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
220#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
221
41e2fce4
M
222/* GCTL unsolicited response enable bit */
223#define ICH6_GCTL_UREN (1<<8)
224
1da177e4
LT
225/* GCTL reset bit */
226#define ICH6_GCTL_RESET (1<<0)
227
228/* CORB/RIRB control, read/write pointer */
229#define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
230#define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
231#define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
232/* below are so far hardcoded - should read registers in future */
233#define ICH6_MAX_CORB_ENTRIES 256
234#define ICH6_MAX_RIRB_ENTRIES 256
235
c74db86b
TI
236/* position fix mode */
237enum {
0be3b5d3 238 POS_FIX_AUTO,
c74db86b 239 POS_FIX_NONE,
0be3b5d3
TI
240 POS_FIX_POSBUF,
241 POS_FIX_FIFO,
c74db86b 242};
1da177e4 243
f5d40b30 244/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL
245#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
246#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
247
da3fca21
V
248/* Defines for Nvidia HDA support */
249#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
250#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
f5d40b30 251
1da177e4
LT
252/*
253 */
254
a98f90fd 255struct azx_dev {
1da177e4
LT
256 u32 *bdl; /* virtual address of the BDL */
257 dma_addr_t bdl_addr; /* physical address of the BDL */
929861c6 258 u32 *posbuf; /* position buffer pointer */
1da177e4
LT
259
260 unsigned int bufsize; /* size of the play buffer in bytes */
261 unsigned int fragsize; /* size of each period in bytes */
262 unsigned int frags; /* number for period in the play buffer */
263 unsigned int fifo_size; /* FIFO size */
264
265 void __iomem *sd_addr; /* stream descriptor pointer */
266
267 u32 sd_int_sta_mask; /* stream int status mask */
268
269 /* pcm support */
a98f90fd 270 struct snd_pcm_substream *substream; /* assigned substream, set in PCM open */
1da177e4
LT
271 unsigned int format_val; /* format value to be set in the controller and the codec */
272 unsigned char stream_tag; /* assigned stream */
273 unsigned char index; /* stream index */
1a56f8d6
TI
274 /* for sanity check of position buffer */
275 unsigned int period_intr;
1da177e4 276
927fc866
PM
277 unsigned int opened :1;
278 unsigned int running :1;
1da177e4
LT
279};
280
281/* CORB/RIRB */
a98f90fd 282struct azx_rb {
1da177e4
LT
283 u32 *buf; /* CORB/RIRB buffer
284 * Each CORB entry is 4byte, RIRB is 8byte
285 */
286 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
287 /* for RIRB */
288 unsigned short rp, wp; /* read/write pointers */
289 int cmds; /* number of pending requests */
290 u32 res; /* last read value */
291};
292
a98f90fd
TI
293struct azx {
294 struct snd_card *card;
1da177e4
LT
295 struct pci_dev *pci;
296
07e4ca50
TI
297 /* chip type specific */
298 int driver_type;
299 int playback_streams;
300 int playback_index_offset;
301 int capture_streams;
302 int capture_index_offset;
303 int num_streams;
304
1da177e4
LT
305 /* pci resources */
306 unsigned long addr;
307 void __iomem *remap_addr;
308 int irq;
309
310 /* locks */
311 spinlock_t reg_lock;
62932df8 312 struct mutex open_mutex;
1da177e4 313
07e4ca50 314 /* streams (x num_streams) */
a98f90fd 315 struct azx_dev *azx_dev;
1da177e4
LT
316
317 /* PCM */
318 unsigned int pcm_devs;
a98f90fd 319 struct snd_pcm *pcm[AZX_MAX_PCMS];
1da177e4
LT
320
321 /* HD codec */
322 unsigned short codec_mask;
323 struct hda_bus *bus;
324
325 /* CORB/RIRB */
a98f90fd
TI
326 struct azx_rb corb;
327 struct azx_rb rirb;
1da177e4
LT
328
329 /* BDL, CORB/RIRB and position buffers */
330 struct snd_dma_buffer bdl;
331 struct snd_dma_buffer rb;
332 struct snd_dma_buffer posbuf;
c74db86b
TI
333
334 /* flags */
335 int position_fix;
927fc866
PM
336 unsigned int initialized :1;
337 unsigned int single_cmd :1;
338 unsigned int polling_mode :1;
1da177e4
LT
339};
340
07e4ca50
TI
341/* driver types */
342enum {
343 AZX_DRIVER_ICH,
344 AZX_DRIVER_ATI,
778b6e1b 345 AZX_DRIVER_ATIHDMI,
07e4ca50
TI
346 AZX_DRIVER_VIA,
347 AZX_DRIVER_SIS,
348 AZX_DRIVER_ULI,
da3fca21 349 AZX_DRIVER_NVIDIA,
07e4ca50
TI
350};
351
352static char *driver_short_names[] __devinitdata = {
353 [AZX_DRIVER_ICH] = "HDA Intel",
354 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 355 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
07e4ca50
TI
356 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
357 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V
358 [AZX_DRIVER_ULI] = "HDA ULI M5461",
359 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
07e4ca50
TI
360};
361
1da177e4
LT
362/*
363 * macros for easy use
364 */
365#define azx_writel(chip,reg,value) \
366 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
367#define azx_readl(chip,reg) \
368 readl((chip)->remap_addr + ICH6_REG_##reg)
369#define azx_writew(chip,reg,value) \
370 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
371#define azx_readw(chip,reg) \
372 readw((chip)->remap_addr + ICH6_REG_##reg)
373#define azx_writeb(chip,reg,value) \
374 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
375#define azx_readb(chip,reg) \
376 readb((chip)->remap_addr + ICH6_REG_##reg)
377
378#define azx_sd_writel(dev,reg,value) \
379 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
380#define azx_sd_readl(dev,reg) \
381 readl((dev)->sd_addr + ICH6_REG_##reg)
382#define azx_sd_writew(dev,reg,value) \
383 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
384#define azx_sd_readw(dev,reg) \
385 readw((dev)->sd_addr + ICH6_REG_##reg)
386#define azx_sd_writeb(dev,reg,value) \
387 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
388#define azx_sd_readb(dev,reg) \
389 readb((dev)->sd_addr + ICH6_REG_##reg)
390
391/* for pcm support */
a98f90fd 392#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4
LT
393
394/* Get the upper 32bit of the given dma_addr_t
395 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
396 */
397#define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
398
399
400/*
401 * Interface for HD codec
402 */
403
1da177e4
LT
404/*
405 * CORB / RIRB interface
406 */
a98f90fd 407static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT
408{
409 int err;
410
411 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
412 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
413 PAGE_SIZE, &chip->rb);
414 if (err < 0) {
415 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
416 return err;
417 }
418 return 0;
419}
420
a98f90fd 421static void azx_init_cmd_io(struct azx *chip)
1da177e4
LT
422{
423 /* CORB set up */
424 chip->corb.addr = chip->rb.addr;
425 chip->corb.buf = (u32 *)chip->rb.area;
426 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
427 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
428
07e4ca50
TI
429 /* set the corb size to 256 entries (ULI requires explicitly) */
430 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT
431 /* set the corb write pointer to 0 */
432 azx_writew(chip, CORBWP, 0);
433 /* reset the corb hw read pointer */
434 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
435 /* enable corb dma */
436 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
437
438 /* RIRB set up */
439 chip->rirb.addr = chip->rb.addr + 2048;
440 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
441 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
442 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
443
07e4ca50
TI
444 /* set the rirb size to 256 entries (ULI requires explicitly) */
445 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4
LT
446 /* reset the rirb hw write pointer */
447 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
448 /* set N=1, get RIRB response interrupt for new entry */
449 azx_writew(chip, RINTCNT, 1);
450 /* enable rirb dma and response irq */
1da177e4 451 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
1da177e4
LT
452 chip->rirb.rp = chip->rirb.cmds = 0;
453}
454
a98f90fd 455static void azx_free_cmd_io(struct azx *chip)
1da177e4
LT
456{
457 /* disable ringbuffer DMAs */
458 azx_writeb(chip, RIRBCTL, 0);
459 azx_writeb(chip, CORBCTL, 0);
460}
461
462/* send a command */
111d3af5
TI
463static int azx_corb_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
464 unsigned int verb, unsigned int para)
1da177e4 465{
a98f90fd 466 struct azx *chip = codec->bus->private_data;
1da177e4
LT
467 unsigned int wp;
468 u32 val;
469
470 val = (u32)(codec->addr & 0x0f) << 28;
471 val |= (u32)direct << 27;
472 val |= (u32)nid << 20;
473 val |= verb << 8;
474 val |= para;
475
476 /* add command to corb */
477 wp = azx_readb(chip, CORBWP);
478 wp++;
479 wp %= ICH6_MAX_CORB_ENTRIES;
480
481 spin_lock_irq(&chip->reg_lock);
482 chip->rirb.cmds++;
483 chip->corb.buf[wp] = cpu_to_le32(val);
484 azx_writel(chip, CORBWP, wp);
485 spin_unlock_irq(&chip->reg_lock);
486
487 return 0;
488}
489
490#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
491
492/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 493static void azx_update_rirb(struct azx *chip)
1da177e4
LT
494{
495 unsigned int rp, wp;
496 u32 res, res_ex;
497
498 wp = azx_readb(chip, RIRBWP);
499 if (wp == chip->rirb.wp)
500 return;
501 chip->rirb.wp = wp;
502
503 while (chip->rirb.rp != wp) {
504 chip->rirb.rp++;
505 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
506
507 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
508 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
509 res = le32_to_cpu(chip->rirb.buf[rp]);
510 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
511 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
512 else if (chip->rirb.cmds) {
513 chip->rirb.cmds--;
514 chip->rirb.res = res;
515 }
516 }
517}
518
519/* receive a response */
111d3af5 520static unsigned int azx_rirb_get_response(struct hda_codec *codec)
1da177e4 521{
a98f90fd 522 struct azx *chip = codec->bus->private_data;
5c79b1f8 523 unsigned long timeout;
1da177e4 524
5c79b1f8
TI
525 again:
526 timeout = jiffies + msecs_to_jiffies(1000);
527 do {
e96224ae
TI
528 if (chip->polling_mode) {
529 spin_lock_irq(&chip->reg_lock);
530 azx_update_rirb(chip);
531 spin_unlock_irq(&chip->reg_lock);
532 }
533 if (! chip->rirb.cmds)
5c79b1f8
TI
534 return chip->rirb.res; /* the last value */
535 schedule_timeout_interruptible(1);
536 } while (time_after_eq(timeout, jiffies));
537
538 if (!chip->polling_mode) {
539 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
540 "switching to polling mode...\n");
541 chip->polling_mode = 1;
542 goto again;
1da177e4 543 }
5c79b1f8
TI
544
545 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
546 "switching to single_cmd mode...\n");
547 chip->rirb.rp = azx_readb(chip, RIRBWP);
548 chip->rirb.cmds = 0;
549 /* switch to single_cmd mode */
550 chip->single_cmd = 1;
551 azx_free_cmd_io(chip);
552 return -1;
1da177e4
LT
553}
554
1da177e4
LT
555/*
556 * Use the single immediate command instead of CORB/RIRB for simplicity
557 *
558 * Note: according to Intel, this is not preferred use. The command was
559 * intended for the BIOS only, and may get confused with unsolicited
560 * responses. So, we shouldn't use it for normal operation from the
561 * driver.
562 * I left the codes, however, for debugging/testing purposes.
563 */
564
1da177e4 565/* send a command */
27346166
TI
566static int azx_single_send_cmd(struct hda_codec *codec, hda_nid_t nid,
567 int direct, unsigned int verb,
568 unsigned int para)
1da177e4 569{
a98f90fd 570 struct azx *chip = codec->bus->private_data;
1da177e4
LT
571 u32 val;
572 int timeout = 50;
573
574 val = (u32)(codec->addr & 0x0f) << 28;
575 val |= (u32)direct << 27;
576 val |= (u32)nid << 20;
577 val |= verb << 8;
578 val |= para;
579
580 while (timeout--) {
581 /* check ICB busy bit */
582 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
583 /* Clear IRV valid bit */
584 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
585 azx_writel(chip, IC, val);
586 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
587 return 0;
588 }
589 udelay(1);
590 }
591 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
592 return -EIO;
593}
594
595/* receive a response */
27346166 596static unsigned int azx_single_get_response(struct hda_codec *codec)
1da177e4 597{
a98f90fd 598 struct azx *chip = codec->bus->private_data;
1da177e4
LT
599 int timeout = 50;
600
601 while (timeout--) {
602 /* check IRV busy bit */
603 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
604 return azx_readl(chip, IR);
605 udelay(1);
606 }
607 snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
608 return (unsigned int)-1;
609}
610
111d3af5
TI
611/*
612 * The below are the main callbacks from hda_codec.
613 *
614 * They are just the skeleton to call sub-callbacks according to the
615 * current setting of chip->single_cmd.
616 */
617
618/* send a command */
619static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
620 int direct, unsigned int verb,
621 unsigned int para)
622{
623 struct azx *chip = codec->bus->private_data;
624 if (chip->single_cmd)
625 return azx_single_send_cmd(codec, nid, direct, verb, para);
626 else
627 return azx_corb_send_cmd(codec, nid, direct, verb, para);
628}
629
630/* get a response */
631static unsigned int azx_get_response(struct hda_codec *codec)
632{
633 struct azx *chip = codec->bus->private_data;
634 if (chip->single_cmd)
635 return azx_single_get_response(codec);
636 else
637 return azx_rirb_get_response(codec);
638}
639
640
1da177e4 641/* reset codec link */
a98f90fd 642static int azx_reset(struct azx *chip)
1da177e4
LT
643{
644 int count;
645
646 /* reset controller */
647 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
648
649 count = 50;
650 while (azx_readb(chip, GCTL) && --count)
651 msleep(1);
652
653 /* delay for >= 100us for codec PLL to settle per spec
654 * Rev 0.9 section 5.5.1
655 */
656 msleep(1);
657
658 /* Bring controller out of reset */
659 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
660
661 count = 50;
927fc866 662 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT
663 msleep(1);
664
927fc866 665 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT
666 msleep(1);
667
668 /* check to see if controller is ready */
927fc866 669 if (!azx_readb(chip, GCTL)) {
1da177e4
LT
670 snd_printd("azx_reset: controller not ready!\n");
671 return -EBUSY;
672 }
673
41e2fce4
M
674 /* Accept unsolicited responses */
675 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
676
1da177e4 677 /* detect codecs */
927fc866 678 if (!chip->codec_mask) {
1da177e4
LT
679 chip->codec_mask = azx_readw(chip, STATESTS);
680 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
681 }
682
683 return 0;
684}
685
686
687/*
688 * Lowlevel interface
689 */
690
691/* enable interrupts */
a98f90fd 692static void azx_int_enable(struct azx *chip)
1da177e4
LT
693{
694 /* enable controller CIE and GIE */
695 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
696 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
697}
698
699/* disable interrupts */
a98f90fd 700static void azx_int_disable(struct azx *chip)
1da177e4
LT
701{
702 int i;
703
704 /* disable interrupts in stream descriptor */
07e4ca50 705 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 706 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT
707 azx_sd_writeb(azx_dev, SD_CTL,
708 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
709 }
710
711 /* disable SIE for all streams */
712 azx_writeb(chip, INTCTL, 0);
713
714 /* disable controller CIE and GIE */
715 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
716 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
717}
718
719/* clear interrupts */
a98f90fd 720static void azx_int_clear(struct azx *chip)
1da177e4
LT
721{
722 int i;
723
724 /* clear stream status */
07e4ca50 725 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 726 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT
727 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
728 }
729
730 /* clear STATESTS */
731 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
732
733 /* clear rirb status */
734 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
735
736 /* clear int status */
737 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
738}
739
740/* start a stream */
a98f90fd 741static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT
742{
743 /* enable SIE */
744 azx_writeb(chip, INTCTL,
745 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
746 /* set DMA start and interrupt mask */
747 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
748 SD_CTL_DMA_START | SD_INT_MASK);
749}
750
751/* stop a stream */
a98f90fd 752static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT
753{
754 /* stop DMA */
755 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
756 ~(SD_CTL_DMA_START | SD_INT_MASK));
757 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
758 /* disable SIE */
759 azx_writeb(chip, INTCTL,
760 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
761}
762
763
764/*
765 * initialize the chip
766 */
a98f90fd 767static void azx_init_chip(struct azx *chip)
1da177e4 768{
da3fca21 769 unsigned char reg;
1da177e4
LT
770
771 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
772 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
773 * Ensuring these bits are 0 clears playback static on some HD Audio codecs
774 */
da3fca21
V
775 pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &reg);
776 pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, reg & 0xf8);
1da177e4
LT
777
778 /* reset controller */
779 azx_reset(chip);
780
781 /* initialize interrupts */
782 azx_int_clear(chip);
783 azx_int_enable(chip);
784
785 /* initialize the codec command I/O */
927fc866 786 if (!chip->single_cmd)
27346166 787 azx_init_cmd_io(chip);
1da177e4 788
0be3b5d3
TI
789 /* program the position buffer */
790 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
791 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
f5d40b30 792
da3fca21
V
793 switch (chip->driver_type) {
794 case AZX_DRIVER_ATI:
795 /* For ATI SB450 azalia HD audio, we need to enable snoop */
f5d40b30 796 pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
da3fca21 797 &reg);
f5d40b30 798 pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
da3fca21
V
799 (reg & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP);
800 break;
801 case AZX_DRIVER_NVIDIA:
802 /* For NVIDIA HDA, enable snoop */
803 pci_read_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, &reg);
804 pci_write_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR,
805 (reg & 0xf0) | NVIDIA_HDA_ENABLE_COHBITS);
806 break;
807 }
1da177e4
LT
808}
809
810
811/*
812 * interrupt handler
813 */
927fc866 814static irqreturn_t azx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1da177e4 815{
a98f90fd
TI
816 struct azx *chip = dev_id;
817 struct azx_dev *azx_dev;
1da177e4
LT
818 u32 status;
819 int i;
820
821 spin_lock(&chip->reg_lock);
822
823 status = azx_readl(chip, INTSTS);
824 if (status == 0) {
825 spin_unlock(&chip->reg_lock);
826 return IRQ_NONE;
827 }
828
07e4ca50 829 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT
830 azx_dev = &chip->azx_dev[i];
831 if (status & azx_dev->sd_int_sta_mask) {
832 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
833 if (azx_dev->substream && azx_dev->running) {
1a56f8d6 834 azx_dev->period_intr++;
1da177e4
LT
835 spin_unlock(&chip->reg_lock);
836 snd_pcm_period_elapsed(azx_dev->substream);
837 spin_lock(&chip->reg_lock);
838 }
839 }
840 }
841
842 /* clear rirb int */
843 status = azx_readb(chip, RIRBSTS);
844 if (status & RIRB_INT_MASK) {
27346166 845 if (! chip->single_cmd && (status & RIRB_INT_RESPONSE))
1da177e4
LT
846 azx_update_rirb(chip);
847 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
848 }
849
850#if 0
851 /* clear state status int */
852 if (azx_readb(chip, STATESTS) & 0x04)
853 azx_writeb(chip, STATESTS, 0x04);
854#endif
855 spin_unlock(&chip->reg_lock);
856
857 return IRQ_HANDLED;
858}
859
860
861/*
862 * set up BDL entries
863 */
a98f90fd 864static void azx_setup_periods(struct azx_dev *azx_dev)
1da177e4
LT
865{
866 u32 *bdl = azx_dev->bdl;
867 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
868 int idx;
869
870 /* reset BDL address */
871 azx_sd_writel(azx_dev, SD_BDLPL, 0);
872 azx_sd_writel(azx_dev, SD_BDLPU, 0);
873
874 /* program the initial BDL entries */
875 for (idx = 0; idx < azx_dev->frags; idx++) {
876 unsigned int off = idx << 2; /* 4 dword step */
877 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
878 /* program the address field of the BDL entry */
879 bdl[off] = cpu_to_le32((u32)addr);
880 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
881
882 /* program the size field of the BDL entry */
883 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
884
885 /* program the IOC to enable interrupt when buffer completes */
886 bdl[off+3] = cpu_to_le32(0x01);
887 }
888}
889
890/*
891 * set up the SD for streaming
892 */
a98f90fd 893static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT
894{
895 unsigned char val;
896 int timeout;
897
898 /* make sure the run bit is zero for SD */
899 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
900 /* reset stream */
901 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
902 udelay(3);
903 timeout = 300;
904 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
905 --timeout)
906 ;
907 val &= ~SD_CTL_STREAM_RESET;
908 azx_sd_writeb(azx_dev, SD_CTL, val);
909 udelay(3);
910
911 timeout = 300;
912 /* waiting for hardware to report that the stream is out of reset */
913 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
914 --timeout)
915 ;
916
917 /* program the stream_tag */
918 azx_sd_writel(azx_dev, SD_CTL,
919 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
920 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
921
922 /* program the length of samples in cyclic buffer */
923 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
924
925 /* program the stream format */
926 /* this value needs to be the same as the one programmed */
927 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
928
929 /* program the stream LVI (last valid index) of the BDL */
930 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
931
932 /* program the BDL address */
933 /* lower BDL address */
934 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
935 /* upper BDL address */
936 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
937
0be3b5d3
TI
938 /* enable the position buffer */
939 if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
940 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
c74db86b 941
1da177e4
LT
942 /* set the interrupt enable bits in the descriptor control register */
943 azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
944
945 return 0;
946}
947
948
949/*
950 * Codec initialization
951 */
952
a98f90fd 953static int __devinit azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT
954{
955 struct hda_bus_template bus_temp;
956 int c, codecs, err;
957
958 memset(&bus_temp, 0, sizeof(bus_temp));
959 bus_temp.private_data = chip;
960 bus_temp.modelname = model;
961 bus_temp.pci = chip->pci;
111d3af5
TI
962 bus_temp.ops.command = azx_send_cmd;
963 bus_temp.ops.get_response = azx_get_response;
1da177e4
LT
964
965 if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
966 return err;
967
968 codecs = 0;
969 for (c = 0; c < AZX_MAX_CODECS; c++) {
606ad75f 970 if ((chip->codec_mask & (1 << c)) & probe_mask) {
1da177e4
LT
971 err = snd_hda_codec_new(chip->bus, c, NULL);
972 if (err < 0)
973 continue;
974 codecs++;
975 }
976 }
977 if (! codecs) {
978 snd_printk(KERN_ERR SFX "no codecs initialized\n");
979 return -ENXIO;
980 }
981
982 return 0;
983}
984
985
986/*
987 * PCM support
988 */
989
990/* assign a stream for the PCM */
a98f90fd 991static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1da177e4 992{
07e4ca50
TI
993 int dev, i, nums;
994 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
995 dev = chip->playback_index_offset;
996 nums = chip->playback_streams;
997 } else {
998 dev = chip->capture_index_offset;
999 nums = chip->capture_streams;
1000 }
1001 for (i = 0; i < nums; i++, dev++)
1da177e4
LT
1002 if (! chip->azx_dev[dev].opened) {
1003 chip->azx_dev[dev].opened = 1;
1004 return &chip->azx_dev[dev];
1005 }
1006 return NULL;
1007}
1008
1009/* release the assigned stream */
a98f90fd 1010static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT
1011{
1012 azx_dev->opened = 0;
1013}
1014
a98f90fd 1015static struct snd_pcm_hardware azx_pcm_hw = {
1da177e4
LT
1016 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1017 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1018 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM
1019 /* No full-resume yet implemented */
1020 /* SNDRV_PCM_INFO_RESUME |*/
1021 SNDRV_PCM_INFO_PAUSE),
1da177e4
LT
1022 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1023 .rates = SNDRV_PCM_RATE_48000,
1024 .rate_min = 48000,
1025 .rate_max = 48000,
1026 .channels_min = 2,
1027 .channels_max = 2,
1028 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1029 .period_bytes_min = 128,
1030 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1031 .periods_min = 2,
1032 .periods_max = AZX_MAX_FRAG,
1033 .fifo_size = 0,
1034};
1035
1036struct azx_pcm {
a98f90fd 1037 struct azx *chip;
1da177e4
LT
1038 struct hda_codec *codec;
1039 struct hda_pcm_stream *hinfo[2];
1040};
1041
a98f90fd 1042static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT
1043{
1044 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1045 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI
1046 struct azx *chip = apcm->chip;
1047 struct azx_dev *azx_dev;
1048 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT
1049 unsigned long flags;
1050 int err;
1051
62932df8 1052 mutex_lock(&chip->open_mutex);
1da177e4
LT
1053 azx_dev = azx_assign_device(chip, substream->stream);
1054 if (azx_dev == NULL) {
62932df8 1055 mutex_unlock(&chip->open_mutex);
1da177e4
LT
1056 return -EBUSY;
1057 }
1058 runtime->hw = azx_pcm_hw;
1059 runtime->hw.channels_min = hinfo->channels_min;
1060 runtime->hw.channels_max = hinfo->channels_max;
1061 runtime->hw.formats = hinfo->formats;
1062 runtime->hw.rates = hinfo->rates;
1063 snd_pcm_limit_hw_rates(runtime);
1064 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1065 if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
1066 azx_release_device(azx_dev);
62932df8 1067 mutex_unlock(&chip->open_mutex);
1da177e4
LT
1068 return err;
1069 }
1070 spin_lock_irqsave(&chip->reg_lock, flags);
1071 azx_dev->substream = substream;
1072 azx_dev->running = 0;
1073 spin_unlock_irqrestore(&chip->reg_lock, flags);
1074
1075 runtime->private_data = azx_dev;
62932df8 1076 mutex_unlock(&chip->open_mutex);
1da177e4
LT
1077 return 0;
1078}
1079
a98f90fd 1080static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT
1081{
1082 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1083 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI
1084 struct azx *chip = apcm->chip;
1085 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT
1086 unsigned long flags;
1087
62932df8 1088 mutex_lock(&chip->open_mutex);
1da177e4
LT
1089 spin_lock_irqsave(&chip->reg_lock, flags);
1090 azx_dev->substream = NULL;
1091 azx_dev->running = 0;
1092 spin_unlock_irqrestore(&chip->reg_lock, flags);
1093 azx_release_device(azx_dev);
1094 hinfo->ops.close(hinfo, apcm->codec, substream);
62932df8 1095 mutex_unlock(&chip->open_mutex);
1da177e4
LT
1096 return 0;
1097}
1098
a98f90fd 1099static int azx_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params)
1da177e4
LT
1100{
1101 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1102}
1103
a98f90fd 1104static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT
1105{
1106 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1107 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT
1108 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1109
1110 /* reset BDL address */
1111 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1112 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1113 azx_sd_writel(azx_dev, SD_CTL, 0);
1114
1115 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1116
1117 return snd_pcm_lib_free_pages(substream);
1118}
1119
a98f90fd 1120static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT
1121{
1122 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI
1123 struct azx *chip = apcm->chip;
1124 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1125 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1126 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT
1127
1128 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1129 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1130 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1131 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1132 runtime->channels,
1133 runtime->format,
1134 hinfo->maxbps);
1135 if (! azx_dev->format_val) {
1136 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
1137 runtime->rate, runtime->channels, runtime->format);
1138 return -EINVAL;
1139 }
1140
1141 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1142 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1143 azx_setup_periods(azx_dev);
1144 azx_setup_controller(chip, azx_dev);
1145 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1146 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1147 else
1148 azx_dev->fifo_size = 0;
1149
1150 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1151 azx_dev->format_val, substream);
1152}
1153
a98f90fd 1154static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT
1155{
1156 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI
1157 struct azx_dev *azx_dev = get_azx_dev(substream);
1158 struct azx *chip = apcm->chip;
1da177e4
LT
1159 int err = 0;
1160
1161 spin_lock(&chip->reg_lock);
1162 switch (cmd) {
1163 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1164 case SNDRV_PCM_TRIGGER_RESUME:
1165 case SNDRV_PCM_TRIGGER_START:
1166 azx_stream_start(chip, azx_dev);
1167 azx_dev->running = 1;
1168 break;
1169 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1170 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT
1171 case SNDRV_PCM_TRIGGER_STOP:
1172 azx_stream_stop(chip, azx_dev);
1173 azx_dev->running = 0;
1174 break;
1175 default:
1176 err = -EINVAL;
1177 }
1178 spin_unlock(&chip->reg_lock);
1179 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
47123197 1180 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1da177e4
LT
1181 cmd == SNDRV_PCM_TRIGGER_STOP) {
1182 int timeout = 5000;
1183 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1184 ;
1185 }
1186 return err;
1187}
1188
a98f90fd 1189static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 1190{
c74db86b 1191 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI
1192 struct azx *chip = apcm->chip;
1193 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT
1194 unsigned int pos;
1195
1a56f8d6
TI
1196 if (chip->position_fix == POS_FIX_POSBUF ||
1197 chip->position_fix == POS_FIX_AUTO) {
c74db86b 1198 /* use the position buffer */
929861c6 1199 pos = le32_to_cpu(*azx_dev->posbuf);
1a56f8d6
TI
1200 if (chip->position_fix == POS_FIX_AUTO &&
1201 azx_dev->period_intr == 1 && ! pos) {
1202 printk(KERN_WARNING
1203 "hda-intel: Invalid position buffer, "
1204 "using LPIB read method instead.\n");
1205 chip->position_fix = POS_FIX_NONE;
1206 goto read_lpib;
1207 }
c74db86b 1208 } else {
1a56f8d6 1209 read_lpib:
c74db86b
TI
1210 /* read LPIB */
1211 pos = azx_sd_readl(azx_dev, SD_LPIB);
1212 if (chip->position_fix == POS_FIX_FIFO)
1213 pos += azx_dev->fifo_size;
1214 }
1da177e4
LT
1215 if (pos >= azx_dev->bufsize)
1216 pos = 0;
1217 return bytes_to_frames(substream->runtime, pos);
1218}
1219
a98f90fd 1220static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT
1221 .open = azx_pcm_open,
1222 .close = azx_pcm_close,
1223 .ioctl = snd_pcm_lib_ioctl,
1224 .hw_params = azx_pcm_hw_params,
1225 .hw_free = azx_pcm_hw_free,
1226 .prepare = azx_pcm_prepare,
1227 .trigger = azx_pcm_trigger,
1228 .pointer = azx_pcm_pointer,
1229};
1230
a98f90fd 1231static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4
LT
1232{
1233 kfree(pcm->private_data);
1234}
1235
a98f90fd 1236static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1da177e4
LT
1237 struct hda_pcm *cpcm, int pcm_dev)
1238{
1239 int err;
a98f90fd 1240 struct snd_pcm *pcm;
1da177e4
LT
1241 struct azx_pcm *apcm;
1242
e08a007d
TI
1243 /* if no substreams are defined for both playback and capture,
1244 * it's just a placeholder. ignore it.
1245 */
1246 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1247 return 0;
1248
1da177e4
LT
1249 snd_assert(cpcm->name, return -EINVAL);
1250
1251 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1252 cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1253 &pcm);
1254 if (err < 0)
1255 return err;
1256 strcpy(pcm->name, cpcm->name);
1257 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1258 if (apcm == NULL)
1259 return -ENOMEM;
1260 apcm->chip = chip;
1261 apcm->codec = codec;
1262 apcm->hinfo[0] = &cpcm->stream[0];
1263 apcm->hinfo[1] = &cpcm->stream[1];
1264 pcm->private_data = apcm;
1265 pcm->private_free = azx_pcm_free;
1266 if (cpcm->stream[0].substreams)
1267 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1268 if (cpcm->stream[1].substreams)
1269 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1270 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1271 snd_dma_pci_data(chip->pci),
1272 1024 * 64, 1024 * 128);
1273 chip->pcm[pcm_dev] = pcm;
e08a007d
TI
1274 if (chip->pcm_devs < pcm_dev + 1)
1275 chip->pcm_devs = pcm_dev + 1;
1da177e4
LT
1276
1277 return 0;
1278}
1279
a98f90fd 1280static int __devinit azx_pcm_create(struct azx *chip)
1da177e4
LT
1281{
1282 struct list_head *p;
1283 struct hda_codec *codec;
1284 int c, err;
1285 int pcm_dev;
1286
1287 if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1288 return err;
1289
ec9e1c5c 1290 /* create audio PCMs */
1da177e4
LT
1291 pcm_dev = 0;
1292 list_for_each(p, &chip->bus->codec_list) {
1293 codec = list_entry(p, struct hda_codec, list);
1294 for (c = 0; c < codec->num_pcms; c++) {
ec9e1c5c
TI
1295 if (codec->pcm_info[c].is_modem)
1296 continue; /* create later */
1297 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1298 snd_printk(KERN_ERR SFX "Too many audio PCMs\n");
1299 return -EINVAL;
1300 }
1301 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1302 if (err < 0)
1303 return err;
1304 pcm_dev++;
1305 }
1306 }
1307
1308 /* create modem PCMs */
1309 pcm_dev = AZX_MAX_AUDIO_PCMS;
1310 list_for_each(p, &chip->bus->codec_list) {
1311 codec = list_entry(p, struct hda_codec, list);
1312 for (c = 0; c < codec->num_pcms; c++) {
1313 if (! codec->pcm_info[c].is_modem)
1314 continue; /* already created */
a28f1cda 1315 if (pcm_dev >= AZX_MAX_PCMS) {
ec9e1c5c 1316 snd_printk(KERN_ERR SFX "Too many modem PCMs\n");
1da177e4
LT
1317 return -EINVAL;
1318 }
1319 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1320 if (err < 0)
1321 return err;
6632d198 1322 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1da177e4
LT
1323 pcm_dev++;
1324 }
1325 }
1326 return 0;
1327}
1328
1329/*
1330 * mixer creation - all stuff is implemented in hda module
1331 */
a98f90fd 1332static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT
1333{
1334 return snd_hda_build_controls(chip->bus);
1335}
1336
1337
1338/*
1339 * initialize SD streams
1340 */
a98f90fd 1341static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT
1342{
1343 int i;
1344
1345 /* initialize each stream (aka device)
1346 * assign the starting bdl address to each stream (device) and initialize
1347 */
07e4ca50 1348 for (i = 0; i < chip->num_streams; i++) {
1da177e4 1349 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
a98f90fd 1350 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT
1351 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1352 azx_dev->bdl_addr = chip->bdl.addr + off;
929861c6 1353 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT
1354 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1355 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1356 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1357 azx_dev->sd_int_sta_mask = 1 << i;
1358 /* stream tag: must be non-zero and unique */
1359 azx_dev->index = i;
1360 azx_dev->stream_tag = i + 1;
1361 }
1362
1363 return 0;
1364}
1365
1366
1367#ifdef CONFIG_PM
1368/*
1369 * power management
1370 */
421a1252 1371static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 1372{
421a1252
TI
1373 struct snd_card *card = pci_get_drvdata(pci);
1374 struct azx *chip = card->private_data;
1da177e4
LT
1375 int i;
1376
421a1252 1377 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1da177e4 1378 for (i = 0; i < chip->pcm_devs; i++)
421a1252 1379 snd_pcm_suspend_all(chip->pcm[i]);
1da177e4 1380 snd_hda_suspend(chip->bus, state);
111d3af5 1381 azx_free_cmd_io(chip);
43001c95
TI
1382 if (chip->irq >= 0)
1383 free_irq(chip->irq, chip);
1384 if (!disable_msi)
1385 pci_disable_msi(chip->pci);
421a1252
TI
1386 pci_disable_device(pci);
1387 pci_save_state(pci);
1da177e4
LT
1388 return 0;
1389}
1390
421a1252 1391static int azx_resume(struct pci_dev *pci)
1da177e4 1392{
421a1252
TI
1393 struct snd_card *card = pci_get_drvdata(pci);
1394 struct azx *chip = card->private_data;
1da177e4 1395
421a1252
TI
1396 pci_restore_state(pci);
1397 pci_enable_device(pci);
43001c95
TI
1398 if (!disable_msi)
1399 pci_enable_msi(pci);
1400 /* FIXME: need proper error handling */
1401 request_irq(pci->irq, azx_interrupt, IRQF_DISABLED|IRQF_SHARED,
1402 "HDA Intel", chip);
1403 chip->irq = pci->irq;
421a1252 1404 pci_set_master(pci);
1da177e4
LT
1405 azx_init_chip(chip);
1406 snd_hda_resume(chip->bus);
421a1252 1407 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT
1408 return 0;
1409}
1410#endif /* CONFIG_PM */
1411
1412
1413/*
1414 * destructor
1415 */
a98f90fd 1416static int azx_free(struct azx *chip)
1da177e4 1417{
ce43fbae 1418 if (chip->initialized) {
1da177e4
LT
1419 int i;
1420
07e4ca50 1421 for (i = 0; i < chip->num_streams; i++)
1da177e4
LT
1422 azx_stream_stop(chip, &chip->azx_dev[i]);
1423
1424 /* disable interrupts */
1425 azx_int_disable(chip);
1426 azx_int_clear(chip);
1427
1428 /* disable CORB/RIRB */
111d3af5 1429 azx_free_cmd_io(chip);
1da177e4
LT
1430
1431 /* disable position buffer */
1432 azx_writel(chip, DPLBASE, 0);
1433 azx_writel(chip, DPUBASE, 0);
1434
929861c6 1435 synchronize_irq(chip->irq);
1da177e4
LT
1436 }
1437
7376d013 1438 if (chip->irq >= 0) {
1da177e4 1439 free_irq(chip->irq, (void*)chip);
dafbbb1f
TI
1440 if (!disable_msi)
1441 pci_disable_msi(chip->pci);
7376d013 1442 }
f079c25a
TI
1443 if (chip->remap_addr)
1444 iounmap(chip->remap_addr);
1da177e4
LT
1445
1446 if (chip->bdl.area)
1447 snd_dma_free_pages(&chip->bdl);
1448 if (chip->rb.area)
1449 snd_dma_free_pages(&chip->rb);
1da177e4
LT
1450 if (chip->posbuf.area)
1451 snd_dma_free_pages(&chip->posbuf);
1da177e4
LT
1452 pci_release_regions(chip->pci);
1453 pci_disable_device(chip->pci);
07e4ca50 1454 kfree(chip->azx_dev);
1da177e4
LT
1455 kfree(chip);
1456
1457 return 0;
1458}
1459
a98f90fd 1460static int azx_dev_free(struct snd_device *device)
1da177e4
LT
1461{
1462 return azx_free(device->device_data);
1463}
1464
1465/*
1466 * constructor
1467 */
a98f90fd 1468static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
606ad75f 1469 int driver_type,
a98f90fd 1470 struct azx **rchip)
1da177e4 1471{
a98f90fd 1472 struct azx *chip;
927fc866 1473 int err;
a98f90fd 1474 static struct snd_device_ops ops = {
1da177e4
LT
1475 .dev_free = azx_dev_free,
1476 };
1477
1478 *rchip = NULL;
1479
927fc866
PM
1480 err = pci_enable_device(pci);
1481 if (err < 0)
1da177e4
LT
1482 return err;
1483
e560d8d8 1484 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 1485 if (!chip) {
1da177e4
LT
1486 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1487 pci_disable_device(pci);
1488 return -ENOMEM;
1489 }
1490
1491 spin_lock_init(&chip->reg_lock);
62932df8 1492 mutex_init(&chip->open_mutex);
1da177e4
LT
1493 chip->card = card;
1494 chip->pci = pci;
1495 chip->irq = -1;
07e4ca50 1496 chip->driver_type = driver_type;
1da177e4 1497
1a56f8d6 1498 chip->position_fix = position_fix;
27346166 1499 chip->single_cmd = single_cmd;
c74db86b 1500
07e4ca50
TI
1501#if BITS_PER_LONG != 64
1502 /* Fix up base address on ULI M5461 */
1503 if (chip->driver_type == AZX_DRIVER_ULI) {
1504 u16 tmp3;
1505 pci_read_config_word(pci, 0x40, &tmp3);
1506 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1507 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1508 }
1509#endif
1510
927fc866
PM
1511 err = pci_request_regions(pci, "ICH HD audio");
1512 if (err < 0) {
1da177e4
LT
1513 kfree(chip);
1514 pci_disable_device(pci);
1515 return err;
1516 }
1517
927fc866 1518 chip->addr = pci_resource_start(pci, 0);
1da177e4
LT
1519 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1520 if (chip->remap_addr == NULL) {
1521 snd_printk(KERN_ERR SFX "ioremap error\n");
1522 err = -ENXIO;
1523 goto errout;
1524 }
1525
7376d013
SH
1526 if (!disable_msi)
1527 pci_enable_msi(pci);
1528
65ca68b3 1529 if (request_irq(pci->irq, azx_interrupt, IRQF_DISABLED|IRQF_SHARED,
1da177e4
LT
1530 "HDA Intel", (void*)chip)) {
1531 snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq);
1532 err = -EBUSY;
1533 goto errout;
1534 }
1535 chip->irq = pci->irq;
1536
1537 pci_set_master(pci);
1538 synchronize_irq(chip->irq);
1539
07e4ca50
TI
1540 switch (chip->driver_type) {
1541 case AZX_DRIVER_ULI:
1542 chip->playback_streams = ULI_NUM_PLAYBACK;
1543 chip->capture_streams = ULI_NUM_CAPTURE;
1544 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1545 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1546 break;
778b6e1b
FK
1547 case AZX_DRIVER_ATIHDMI:
1548 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1549 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1550 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1551 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1552 break;
07e4ca50
TI
1553 default:
1554 chip->playback_streams = ICH6_NUM_PLAYBACK;
1555 chip->capture_streams = ICH6_NUM_CAPTURE;
1556 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1557 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1558 break;
1559 }
1560 chip->num_streams = chip->playback_streams + chip->capture_streams;
1561 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), GFP_KERNEL);
927fc866 1562 if (!chip->azx_dev) {
07e4ca50
TI
1563 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1564 goto errout;
1565 }
1566
1da177e4
LT
1567 /* allocate memory for the BDL for each stream */
1568 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
07e4ca50 1569 BDL_SIZE, &chip->bdl)) < 0) {
1da177e4
LT
1570 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1571 goto errout;
1572 }
0be3b5d3
TI
1573 /* allocate memory for the position buffer */
1574 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1575 chip->num_streams * 8, &chip->posbuf)) < 0) {
1576 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1577 goto errout;
1da177e4 1578 }
1da177e4 1579 /* allocate CORB/RIRB */
27346166
TI
1580 if (! chip->single_cmd)
1581 if ((err = azx_alloc_cmd_io(chip)) < 0)
1582 goto errout;
1da177e4
LT
1583
1584 /* initialize streams */
1585 azx_init_stream(chip);
1586
1587 /* initialize chip */
1588 azx_init_chip(chip);
1589
ce43fbae
TI
1590 chip->initialized = 1;
1591
1da177e4 1592 /* codec detection */
927fc866 1593 if (!chip->codec_mask) {
1da177e4
LT
1594 snd_printk(KERN_ERR SFX "no codecs found!\n");
1595 err = -ENODEV;
1596 goto errout;
1597 }
1598
1599 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1600 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1601 goto errout;
1602 }
1603
07e4ca50
TI
1604 strcpy(card->driver, "HDA-Intel");
1605 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1606 sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1607
1da177e4
LT
1608 *rchip = chip;
1609 return 0;
1610
1611 errout:
1612 azx_free(chip);
1613 return err;
1614}
1615
1616static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1617{
a98f90fd
TI
1618 struct snd_card *card;
1619 struct azx *chip;
927fc866 1620 int err;
1da177e4 1621
b7fe4622 1622 card = snd_card_new(index, id, THIS_MODULE, 0);
927fc866 1623 if (!card) {
1da177e4
LT
1624 snd_printk(KERN_ERR SFX "Error creating card!\n");
1625 return -ENOMEM;
1626 }
1627
927fc866
PM
1628 err = azx_create(card, pci, pci_id->driver_data, &chip);
1629 if (err < 0) {
1da177e4
LT
1630 snd_card_free(card);
1631 return err;
1632 }
421a1252 1633 card->private_data = chip;
1da177e4 1634
1da177e4 1635 /* create codec instances */
b7fe4622 1636 if ((err = azx_codec_create(chip, model)) < 0) {
1da177e4
LT
1637 snd_card_free(card);
1638 return err;
1639 }
1640
1641 /* create PCM streams */
1642 if ((err = azx_pcm_create(chip)) < 0) {
1643 snd_card_free(card);
1644 return err;
1645 }
1646
1647 /* create mixer controls */
1648 if ((err = azx_mixer_create(chip)) < 0) {
1649 snd_card_free(card);
1650 return err;
1651 }
1652
1da177e4
LT
1653 snd_card_set_dev(card, &pci->dev);
1654
1655 if ((err = snd_card_register(card)) < 0) {
1656 snd_card_free(card);
1657 return err;
1658 }
1659
1660 pci_set_drvdata(pci, card);
1da177e4
LT
1661
1662 return err;
1663}
1664
1665static void __devexit azx_remove(struct pci_dev *pci)
1666{
1667 snd_card_free(pci_get_drvdata(pci));
1668 pci_set_drvdata(pci, NULL);
1669}
1670
1671/* PCI IDs */
f40b6890 1672static struct pci_device_id azx_ids[] = {
07e4ca50
TI
1673 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1674 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1675 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
d2981393 1676 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
07e4ca50 1677 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
89be83f8 1678 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
778b6e1b 1679 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
07e4ca50
TI
1680 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1681 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1682 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
da3fca21
V
1683 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA 026c */
1684 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA 0371 */
1da177e4
LT
1685 { 0, }
1686};
1687MODULE_DEVICE_TABLE(pci, azx_ids);
1688
1689/* pci_driver definition */
1690static struct pci_driver driver = {
1691 .name = "HDA Intel",
1692 .id_table = azx_ids,
1693 .probe = azx_probe,
1694 .remove = __devexit_p(azx_remove),
421a1252
TI
1695#ifdef CONFIG_PM
1696 .suspend = azx_suspend,
1697 .resume = azx_resume,
1698#endif
1da177e4
LT
1699};
1700
1701static int __init alsa_card_azx_init(void)
1702{
01d25d46 1703 return pci_register_driver(&driver);
1da177e4
LT
1704}
1705
1706static void __exit alsa_card_azx_exit(void)
1707{
1708 pci_unregister_driver(&driver);
1709}
1710
1711module_init(alsa_card_azx_init)
1712module_exit(alsa_card_azx_exit)