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ALSA: hda - add headset mic detect quirk for a Dell laptop
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4 64#include "hda_codec.h"
99a2008d 65#include "hda_i915.h"
05e84878 66#include "hda_controller.h"
2538a4f5 67#include "hda_priv.h"
1da177e4
LT		 68
69
5aba4f8e
TI		 70static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
71static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 72static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 73static char *model[SNDRV_CARDS];
1dac6695 74static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 75static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 76static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 77static int probe_only[SNDRV_CARDS];
26a6cb6c 78static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 79static bool single_cmd;
71623855 80static int enable_msi = -1;
4ea6fbc8
TI		 81#ifdef CONFIG_SND_HDA_PATCH_LOADER
82static char *patch[SNDRV_CARDS];
83#endif
2dca0bba 84#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 85static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 86 CONFIG_SND_HDA_INPUT_BEEP_MODE};
87#endif
1da177e4 88
5aba4f8e 89module_param_array(index, int, NULL, 0444);
1da177e4 90MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 91module_param_array(id, charp, NULL, 0444);
1da177e4 92MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 93module_param_array(enable, bool, NULL, 0444);
94MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
95module_param_array(model, charp, NULL, 0444);
1da177e4 96MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 97module_param_array(position_fix, int, NULL, 0444);
4cb36310 98MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 99 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 100module_param_array(bdl_pos_adj, int, NULL, 0644);
101MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 102module_param_array(probe_mask, int, NULL, 0444);
606ad75f 103MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 104module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 105MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 106module_param_array(jackpoll_ms, int, NULL, 0444);
107MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 108module_param(single_cmd, bool, 0444);
d01ce99f
TI		 109MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
110 "(for debugging only).");
ac9ef6cf 111module_param(enable_msi, bint, 0444);
134a11f0 112MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 113#ifdef CONFIG_SND_HDA_PATCH_LOADER
114module_param_array(patch, charp, NULL, 0444);
115MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
116#endif
2dca0bba 117#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 118module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 119MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 120 "(0=off, 1=on) (default=1).");
2dca0bba 121#endif
606ad75f 122
83012a7c 123#ifdef CONFIG_PM
65fcd41d
TI		 124static int param_set_xint(const char *val, const struct kernel_param *kp);
125static struct kernel_param_ops param_ops_xint = {
126 .set = param_set_xint,
127 .get = param_get_int,
128};
129#define param_check_xint param_check_int
130
fee2fba3 131static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
e62a42ae 132static int *power_save_addr = &power_save;
65fcd41d 133module_param(power_save, xint, 0644);
fee2fba3
TI		 134MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
135 "(in second, 0 = disable).");
1da177e4 136
dee1b66c
TI		 137/* reset the HD-audio controller in power save mode.
138 * this may give more power-saving, but will take longer time to
139 * wake up.
140 */
8fc24426
TI		 141static bool power_save_controller = 1;
142module_param(power_save_controller, bool, 0644);
dee1b66c 143MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae
DR		 144#else
145static int *power_save_addr;
83012a7c 146#endif /* CONFIG_PM */
dee1b66c 147
7bfe059e
TI		 148static int align_buffer_size = -1;
149module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 150MODULE_PARM_DESC(align_buffer_size,
151 "Force buffer and period sizes to be multiple of 128 bytes.");
152
27fe48d9
TI		 153#ifdef CONFIG_X86
154static bool hda_snoop = true;
155module_param_named(snoop, hda_snoop, bool, 0444);
156MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 157#else
158#define hda_snoop true
27fe48d9
TI		 159#endif
160
161
1da177e4
LT		 162MODULE_LICENSE("GPL");
163MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
164 "{Intel, ICH6M},"
2f1b3818 165 "{Intel, ICH7},"
f5d40b30 166 "{Intel, ESB2},"
d2981393 167 "{Intel, ICH8},"
f9cc8a8b 168 "{Intel, ICH9},"
c34f5a04 169 "{Intel, ICH10},"
b29c2360 170 "{Intel, PCH},"
d2f2fcd2 171 "{Intel, CPT},"
d2edeb7c 172 "{Intel, PPT},"
8bc039a1 173 "{Intel, LPT},"
144dad99 174 "{Intel, LPT_LP},"
4eeca499 175 "{Intel, WPT_LP},"
e926f2c8 176 "{Intel, HPT},"
cea310e8 177 "{Intel, PBG},"
4979bca9 178 "{Intel, SCH},"
fc20a562 179 "{ATI, SB450},"
89be83f8 180 "{ATI, SB600},"
778b6e1b 181 "{ATI, RS600},"
5b15c95f 182 "{ATI, RS690},"
e6db1119
WL		 183 "{ATI, RS780},"
184 "{ATI, R600},"
2797f724
HRK		 185 "{ATI, RV630},"
186 "{ATI, RV610},"
27da1834
WL		 187 "{ATI, RV670},"
188 "{ATI, RV635},"
189 "{ATI, RV620},"
190 "{ATI, RV770},"
fc20a562 191 "{VIA, VT8251},"
47672310 192 "{VIA, VT8237A},"
07e4ca50
TI		 193 "{SiS, SIS966},"
194 "{ULI, M5461}}");
1da177e4
LT		 195MODULE_DESCRIPTION("Intel HDA driver");
196
a82d51ed 197#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 198#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 199#define SUPPORT_VGA_SWITCHEROO
200#endif
201#endif
202
203
1da177e4 204/*
1da177e4 205 */
1da177e4 206
07e4ca50
TI		 207/* driver types */
208enum {
209 AZX_DRIVER_ICH,
32679f95 210 AZX_DRIVER_PCH,
4979bca9 211 AZX_DRIVER_SCH,
fab1285a 212 AZX_DRIVER_HDMI,
07e4ca50 213 AZX_DRIVER_ATI,
778b6e1b 214 AZX_DRIVER_ATIHDMI,
1815b34a 215 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 216 AZX_DRIVER_VIA,
217 AZX_DRIVER_SIS,
218 AZX_DRIVER_ULI,
da3fca21 219 AZX_DRIVER_NVIDIA,
f269002e 220 AZX_DRIVER_TERA,
14d34f16 221 AZX_DRIVER_CTX,
5ae763b1 222 AZX_DRIVER_CTHDA,
c4da29ca 223 AZX_DRIVER_GENERIC,
2f5983f2 224 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 225};
226
2ea3c6a2 227/* quirks for Intel PCH */
d7dab4db 228#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 229 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 230 AZX_DCAPS_COUNT_LPIB_DELAY)
231
232#define AZX_DCAPS_INTEL_PCH \
233 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e 234
33499a15
TI		 235#define AZX_DCAPS_INTEL_HASWELL \
236 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
237 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
238 AZX_DCAPS_I915_POWERWELL)
239
9477c58e
TI		 240/* quirks for ATI SB / AMD Hudson */
241#define AZX_DCAPS_PRESET_ATI_SB \
242 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
243 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
244
245/* quirks for ATI/AMD HDMI */
246#define AZX_DCAPS_PRESET_ATI_HDMI \
247 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
248
249/* quirks for Nvidia */
250#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e 251 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
49d9e77e 252 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
9477c58e 253
5ae763b1
TI		 254#define AZX_DCAPS_PRESET_CTHDA \
255 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
256
a82d51ed
TI		 257/*
258 * VGA-switcher support
259 */
260#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 261#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
262#else
263#define use_vga_switcheroo(chip) 0
264#endif
265
48c8b0eb 266static char *driver_short_names[] = {
07e4ca50 267 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 268 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 269 [AZX_DRIVER_SCH] = "HDA Intel MID",
fab1285a 270 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 271 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 272 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 273 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 274 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
275 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 276 [AZX_DRIVER_ULI] = "HDA ULI M5461",
277 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 278 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 279 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 280 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 281 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 282};
283
27fe48d9 284#ifdef CONFIG_X86
9ddf1aeb 285static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 286{
9ddf1aeb
TI		 287 int pages;
288
27fe48d9
TI		 289 if (azx_snoop(chip))
290 return;
9ddf1aeb
TI		 291 if (!dmab || !dmab->area || !dmab->bytes)
292 return;
293
294#ifdef CONFIG_SND_DMA_SGBUF
295 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
296 struct snd_sg_buf *sgbuf = dmab->private_data;
27fe48d9 297 if (on)
9ddf1aeb 298 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 299 else
9ddf1aeb
TI		 300 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
301 return;
27fe48d9 302 }
9ddf1aeb
TI		 303#endif
304
305 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
306 if (on)
307 set_memory_wc((unsigned long)dmab->area, pages);
308 else
309 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 310}
311
312static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
313 bool on)
314{
9ddf1aeb 315 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 316}
317static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 318 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 319{
320 if (azx_dev->wc_marked != on) {
9ddf1aeb 321 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 322 azx_dev->wc_marked = on;
323 }
324}
325#else
326/* NOP for other archs */
327static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
328 bool on)
329{
330}
331static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 332 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 333{
334}
335#endif
336
68e7fffc 337static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 338
cb53c626
TI		 339/*
340 * initialize the PCI registers
341 */
342/* update bits in a PCI register byte */
343static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
344 unsigned char mask, unsigned char val)
345{
346 unsigned char data;
347
348 pci_read_config_byte(pci, reg, &data);
349 data &= ~mask;
350 data |= (val & mask);
351 pci_write_config_byte(pci, reg, data);
352}
353
354static void azx_init_pci(struct azx *chip)
355{
356 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
357 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
358 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 359 * codecs.
360 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 361 */
46f2cc80 362 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 363 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
a09e89f6 364 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 365 }
cb53c626 366
9477c58e
TI		 367 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
368 * we need to enable snoop.
369 */
370 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
4e76a883
TI		 371 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
372 azx_snoop(chip));
cb53c626 373 update_pci_byte(chip->pci,
27fe48d9
TI		 374 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
375 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 376 }
377
378 /* For NVIDIA HDA, enable snoop */
379 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
4e76a883
TI		 380 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
381 azx_snoop(chip));
cb53c626
TI		 382 update_pci_byte(chip->pci,
383 NVIDIA_HDA_TRANSREG_ADDR,
384 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 385 update_pci_byte(chip->pci,
386 NVIDIA_HDA_ISTRM_COH,
387 0x01, NVIDIA_HDA_ENABLE_COHBIT);
388 update_pci_byte(chip->pci,
389 NVIDIA_HDA_OSTRM_COH,
390 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 391 }
392
393 /* Enable SCH/PCH snoop if needed */
394 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 395 unsigned short snoop;
90a5ad52 396 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 397 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
398 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
399 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
400 if (!azx_snoop(chip))
401 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
402 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 403 pci_read_config_word(chip->pci,
404 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 405 }
4e76a883
TI		 406 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
407 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
408 "Disabled" : "Enabled");
da3fca21 409 }
1da177e4
LT		 410}
411
9ad593f6
TI		 412static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
413
7ca954a8
DR		 414/* called from IRQ */
415static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
416{
417 int ok;
418
419 ok = azx_position_ok(chip, azx_dev);
420 if (ok == 1) {
421 azx_dev->irq_pending = 0;
422 return ok;
423 } else if (ok == 0 && chip->bus && chip->bus->workq) {
424 /* bogus IRQ, process it later */
425 azx_dev->irq_pending = 1;
426 queue_work(chip->bus->workq, &chip->irq_pending_work);
427 }
428 return 0;
429}
430
9ad593f6
TI		 431/*
432 * Check whether the current DMA position is acceptable for updating
433 * periods. Returns non-zero if it's OK.
434 *
435 * Many HD-audio controllers appear pretty inaccurate about
436 * the update-IRQ timing. The IRQ is issued before actually the
437 * data is processed. So, we need to process it afterwords in a
438 * workqueue.
439 */
440static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
441{
e5463720 442 u32 wallclk;
9ad593f6
TI		 443 unsigned int pos;
444
f48f606d
JK		 445 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
446 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 447 return -1; /* bogus (too early) interrupt */
fa00e046 448
798cb7e8 449 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 450
d6d8bf54
TI		 451 if (WARN_ONCE(!azx_dev->period_bytes,
452 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 453 return -1; /* this shouldn't happen! */
edb39935 454 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 455 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
456 /* NG - it's below the first next period boundary */
9cdc0115 457 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 458 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 459 return 1; /* OK, it's fine */
460}
461
462/*
463 * The work for pending PCM period updates.
464 */
465static void azx_irq_pending_work(struct work_struct *work)
466{
467 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 468 int i, pending, ok;
9ad593f6 469
a6a950a8 470 if (!chip->irq_pending_warned) {
4e76a883
TI		 471 dev_info(chip->card->dev,
472 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
473 chip->card->number);
a6a950a8
TI		 474 chip->irq_pending_warned = 1;
475 }
476
9ad593f6
TI		 477 for (;;) {
478 pending = 0;
479 spin_lock_irq(&chip->reg_lock);
480 for (i = 0; i < chip->num_streams; i++) {
481 struct azx_dev *azx_dev = &chip->azx_dev[i];
482 if (!azx_dev->irq_pending ||
483 !azx_dev->substream ||
484 !azx_dev->running)
485 continue;
e5463720
JK		 486 ok = azx_position_ok(chip, azx_dev);
487 if (ok > 0) {
9ad593f6
TI		 488 azx_dev->irq_pending = 0;
489 spin_unlock(&chip->reg_lock);
490 snd_pcm_period_elapsed(azx_dev->substream);
491 spin_lock(&chip->reg_lock);
e5463720
JK		 492 } else if (ok < 0) {
493 pending = 0; /* too early */
9ad593f6
TI		 494 } else
495 pending++;
496 }
497 spin_unlock_irq(&chip->reg_lock);
498 if (!pending)
499 return;
08af495f 500 msleep(1);
9ad593f6
TI		 501 }
502}
503
504/* clear irq_pending flags and assure no on-going workq */
505static void azx_clear_irq_pending(struct azx *chip)
506{
507 int i;
508
509 spin_lock_irq(&chip->reg_lock);
510 for (i = 0; i < chip->num_streams; i++)
511 chip->azx_dev[i].irq_pending = 0;
512 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 513}
514
68e7fffc
TI		 515static int azx_acquire_irq(struct azx *chip, int do_disconnect)
516{
437a5a46
TI		 517 if (request_irq(chip->pci->irq, azx_interrupt,
518 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 519 KBUILD_MODNAME, chip)) {
4e76a883
TI		 520 dev_err(chip->card->dev,
521 "unable to grab IRQ %d, disabling device\n",
522 chip->pci->irq);
68e7fffc
TI		 523 if (do_disconnect)
524 snd_card_disconnect(chip->card);
525 return -1;
526 }
527 chip->irq = chip->pci->irq;
69e13418 528 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 529 return 0;
530}
531
83012a7c 532#ifdef CONFIG_PM
65fcd41d
TI		 533static DEFINE_MUTEX(card_list_lock);
534static LIST_HEAD(card_list);
535
536static void azx_add_card_list(struct azx *chip)
537{
538 mutex_lock(&card_list_lock);
539 list_add(&chip->list, &card_list);
540 mutex_unlock(&card_list_lock);
541}
542
543static void azx_del_card_list(struct azx *chip)
544{
545 mutex_lock(&card_list_lock);
546 list_del_init(&chip->list);
547 mutex_unlock(&card_list_lock);
548}
549
550/* trigger power-save check at writing parameter */
551static int param_set_xint(const char *val, const struct kernel_param *kp)
552{
553 struct azx *chip;
554 struct hda_codec *c;
555 int prev = power_save;
556 int ret = param_set_int(val, kp);
557
558 if (ret || prev == power_save)
559 return ret;
560
561 mutex_lock(&card_list_lock);
562 list_for_each_entry(chip, &card_list, list) {
563 if (!chip->bus || chip->disabled)
564 continue;
565 list_for_each_entry(c, &chip->bus->codec_list, list)
566 snd_hda_power_sync(c);
567 }
568 mutex_unlock(&card_list_lock);
569 return 0;
570}
571#else
572#define azx_add_card_list(chip) /* NOP */
573#define azx_del_card_list(chip) /* NOP */
83012a7c 574#endif /* CONFIG_PM */
5c0b9bec 575
7ccbde57 576#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 577/*
578 * power management
579 */
68cb2b55 580static int azx_suspend(struct device *dev)
1da177e4 581{
68cb2b55
TI		 582 struct pci_dev *pci = to_pci_dev(dev);
583 struct snd_card *card = dev_get_drvdata(dev);
421a1252 584 struct azx *chip = card->private_data;
01b65bfb 585 struct azx_pcm *p;
1da177e4 586
c5c21523
TI		 587 if (chip->disabled)
588 return 0;
589
421a1252 590 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 591 azx_clear_irq_pending(chip);
01b65bfb
TI		 592 list_for_each_entry(p, &chip->pcm_list, list)
593 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 594 if (chip->initialized)
8dd78330 595 snd_hda_suspend(chip->bus);
cb53c626 596 azx_stop_chip(chip);
7295b264 597 azx_enter_link_reset(chip);
30b35399 598 if (chip->irq >= 0) {
43001c95 599 free_irq(chip->irq, chip);
30b35399
TI		 600 chip->irq = -1;
601 }
68e7fffc 602 if (chip->msi)
43001c95 603 pci_disable_msi(chip->pci);
421a1252
TI		 604 pci_disable_device(pci);
605 pci_save_state(pci);
68cb2b55 606 pci_set_power_state(pci, PCI_D3hot);
99a2008d
WX		 607 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
608 hda_display_power(false);
1da177e4
LT		 609 return 0;
610}
611
68cb2b55 612static int azx_resume(struct device *dev)
1da177e4 613{
68cb2b55
TI		 614 struct pci_dev *pci = to_pci_dev(dev);
615 struct snd_card *card = dev_get_drvdata(dev);
421a1252 616 struct azx *chip = card->private_data;
1da177e4 617
c5c21523
TI		 618 if (chip->disabled)
619 return 0;
620
99a2008d
WX		 621 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
622 hda_display_power(true);
d14a7e0b
TI		 623 pci_set_power_state(pci, PCI_D0);
624 pci_restore_state(pci);
30b35399 625 if (pci_enable_device(pci) < 0) {
4e76a883
TI		 626 dev_err(chip->card->dev,
627 "pci_enable_device failed, disabling device\n");
30b35399
TI		 628 snd_card_disconnect(card);
629 return -EIO;
630 }
631 pci_set_master(pci);
68e7fffc
TI		 632 if (chip->msi)
633 if (pci_enable_msi(pci) < 0)
634 chip->msi = 0;
635 if (azx_acquire_irq(chip, 1) < 0)
30b35399 636 return -EIO;
cb53c626 637 azx_init_pci(chip);
d804ad92 638
17c3ad03 639 azx_init_chip(chip, true);
d804ad92 640
1da177e4 641 snd_hda_resume(chip->bus);
421a1252 642 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 643 return 0;
644}
b8dfc462
ML		 645#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
646
647#ifdef CONFIG_PM_RUNTIME
648static int azx_runtime_suspend(struct device *dev)
649{
650 struct snd_card *card = dev_get_drvdata(dev);
651 struct azx *chip = card->private_data;
652
246efa4a
DA		 653 if (chip->disabled)
654 return 0;
655
656 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
657 return 0;
658
7d4f606c
WX		 659 /* enable controller wake up event */
660 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
661 STATESTS_INT_MASK);
662
b8dfc462 663 azx_stop_chip(chip);
873ce8ad 664 azx_enter_link_reset(chip);
b8dfc462 665 azx_clear_irq_pending(chip);
99a2008d
WX		 666 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
667 hda_display_power(false);
b8dfc462
ML		 668 return 0;
669}
670
671static int azx_runtime_resume(struct device *dev)
672{
673 struct snd_card *card = dev_get_drvdata(dev);
674 struct azx *chip = card->private_data;
7d4f606c
WX		 675 struct hda_bus *bus;
676 struct hda_codec *codec;
677 int status;
b8dfc462 678
246efa4a
DA		 679 if (chip->disabled)
680 return 0;
681
682 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
683 return 0;
684
99a2008d
WX		 685 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
686 hda_display_power(true);
7d4f606c
WX		 687
688 /* Read STATESTS before controller reset */
689 status = azx_readw(chip, STATESTS);
690
b8dfc462 691 azx_init_pci(chip);
17c3ad03 692 azx_init_chip(chip, true);
7d4f606c
WX		 693
694 bus = chip->bus;
695 if (status && bus) {
696 list_for_each_entry(codec, &bus->codec_list, list)
697 if (status & (1 << codec->addr))
698 queue_delayed_work(codec->bus->workq,
699 &codec->jackpoll_work, codec->jackpoll_interval);
700 }
701
702 /* disable controller Wake Up event*/
703 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
704 ~STATESTS_INT_MASK);
705
b8dfc462
ML		 706 return 0;
707}
6eb827d2
TI		 708
709static int azx_runtime_idle(struct device *dev)
710{
711 struct snd_card *card = dev_get_drvdata(dev);
712 struct azx *chip = card->private_data;
713
246efa4a
DA		 714 if (chip->disabled)
715 return 0;
716
6eb827d2
TI		 717 if (!power_save_controller ||
718 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
719 return -EBUSY;
720
721 return 0;
722}
723
b8dfc462
ML		 724#endif /* CONFIG_PM_RUNTIME */
725
726#ifdef CONFIG_PM
727static const struct dev_pm_ops azx_pm = {
728 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 729 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 730};
731
68cb2b55
TI		 732#define AZX_PM_OPS &azx_pm
733#else
68cb2b55 734#define AZX_PM_OPS NULL
b8dfc462 735#endif /* CONFIG_PM */
1da177e4
LT		 736
737
0cbf0098
TI		 738/*
739 * reboot notifier for hang-up problem at power-down
740 */
741static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
742{
743 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 744 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 745 azx_stop_chip(chip);
746 return NOTIFY_OK;
747}
748
749static void azx_notifier_register(struct azx *chip)
750{
751 chip->reboot_notifier.notifier_call = azx_halt;
752 register_reboot_notifier(&chip->reboot_notifier);
753}
754
755static void azx_notifier_unregister(struct azx *chip)
756{
757 if (chip->reboot_notifier.notifier_call)
758 unregister_reboot_notifier(&chip->reboot_notifier);
759}
760
48c8b0eb 761static int azx_probe_continue(struct azx *chip);
a82d51ed 762
8393ec4a 763#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 764static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 765
a82d51ed
TI		 766static void azx_vs_set_state(struct pci_dev *pci,
767 enum vga_switcheroo_state state)
768{
769 struct snd_card *card = pci_get_drvdata(pci);
770 struct azx *chip = card->private_data;
771 bool disabled;
772
f4c482a4 773 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 774 if (chip->init_failed)
775 return;
776
777 disabled = (state == VGA_SWITCHEROO_OFF);
778 if (chip->disabled == disabled)
779 return;
780
781 if (!chip->bus) {
782 chip->disabled = disabled;
783 if (!disabled) {
4e76a883
TI		 784 dev_info(chip->card->dev,
785 "Start delayed initialization\n");
5c90680e 786 if (azx_probe_continue(chip) < 0) {
4e76a883 787 dev_err(chip->card->dev, "initialization error\n");
a82d51ed
TI		 788 chip->init_failed = true;
789 }
790 }
791 } else {
4e76a883
TI		 792 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
793 disabled ? "Disabling" : "Enabling");
a82d51ed 794 if (disabled) {
8928756d
DR		 795 pm_runtime_put_sync_suspend(card->dev);
796 azx_suspend(card->dev);
246efa4a
DA		 797 /* when we get suspended by vga switcheroo we end up in D3cold,
798 * however we have no ACPI handle, so pci/acpi can't put us there,
799 * put ourselves there */
800 pci->current_state = PCI_D3cold;
a82d51ed 801 chip->disabled = true;
128960a9 802 if (snd_hda_lock_devices(chip->bus))
4e76a883
TI		 803 dev_warn(chip->card->dev,
804 "Cannot lock devices!\n");
a82d51ed
TI		 805 } else {
806 snd_hda_unlock_devices(chip->bus);
8928756d 807 pm_runtime_get_noresume(card->dev);
a82d51ed 808 chip->disabled = false;
8928756d 809 azx_resume(card->dev);
a82d51ed
TI		 810 }
811 }
812}
813
814static bool azx_vs_can_switch(struct pci_dev *pci)
815{
816 struct snd_card *card = pci_get_drvdata(pci);
817 struct azx *chip = card->private_data;
818
f4c482a4 819 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 820 if (chip->init_failed)
821 return false;
822 if (chip->disabled || !chip->bus)
823 return true;
824 if (snd_hda_lock_devices(chip->bus))
825 return false;
826 snd_hda_unlock_devices(chip->bus);
827 return true;
828}
829
e23e7a14 830static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 831{
832 struct pci_dev *p = get_bound_vga(chip->pci);
833 if (p) {
4e76a883
TI		 834 dev_info(chip->card->dev,
835 "Handle VGA-switcheroo audio client\n");
a82d51ed
TI		 836 chip->use_vga_switcheroo = 1;
837 pci_dev_put(p);
838 }
839}
840
841static const struct vga_switcheroo_client_ops azx_vs_ops = {
842 .set_gpu_state = azx_vs_set_state,
843 .can_switch = azx_vs_can_switch,
844};
845
e23e7a14 846static int register_vga_switcheroo(struct azx *chip)
a82d51ed 847{
128960a9
TI		 848 int err;
849
a82d51ed
TI		 850 if (!chip->use_vga_switcheroo)
851 return 0;
852 /* FIXME: currently only handling DIS controller
853 * is there any machine with two switchable HDMI audio controllers?
854 */
128960a9 855 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 856 VGA_SWITCHEROO_DIS,
857 chip->bus != NULL);
128960a9
TI		 858 if (err < 0)
859 return err;
860 chip->vga_switcheroo_registered = 1;
246efa4a
DA		 861
862 /* register as an optimus hdmi audio power domain */
8928756d
DR		 863 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
864 &chip->hdmi_pm_domain);
128960a9 865 return 0;
a82d51ed
TI		 866}
867#else
868#define init_vga_switcheroo(chip) /* NOP */
869#define register_vga_switcheroo(chip) 0
8393ec4a 870#define check_hdmi_disabled(pci) false
a82d51ed
TI		 871#endif /* SUPPORT_VGA_SWITCHER */
872
1da177e4
LT		 873/*
874 * destructor
875 */
a98f90fd 876static int azx_free(struct azx *chip)
1da177e4 877{
c67e2228 878 struct pci_dev *pci = chip->pci;
4ce107b9
TI		 879 int i;
880
c67e2228
WX		 881 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
882 && chip->running)
883 pm_runtime_get_noresume(&pci->dev);
884
65fcd41d
TI		 885 azx_del_card_list(chip);
886
0cbf0098
TI		 887 azx_notifier_unregister(chip);
888
f4c482a4 889 chip->init_failed = 1; /* to be sure */
44728e97 890 complete_all(&chip->probe_wait);
f4c482a4 891
a82d51ed
TI		 892 if (use_vga_switcheroo(chip)) {
893 if (chip->disabled && chip->bus)
894 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 895 if (chip->vga_switcheroo_registered)
896 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 897 }
898
ce43fbae 899 if (chip->initialized) {
9ad593f6 900 azx_clear_irq_pending(chip);
07e4ca50 901 for (i = 0; i < chip->num_streams; i++)
1da177e4 902 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 903 azx_stop_chip(chip);
1da177e4
LT		 904 }
905
f000fd80 906 if (chip->irq >= 0)
1da177e4 907 free_irq(chip->irq, (void*)chip);
68e7fffc 908 if (chip->msi)
30b35399 909 pci_disable_msi(chip->pci);
f079c25a
TI		 910 if (chip->remap_addr)
911 iounmap(chip->remap_addr);
1da177e4 912
67908994 913 azx_free_stream_pages(chip);
a82d51ed
TI		 914 if (chip->region_requested)
915 pci_release_regions(chip->pci);
1da177e4 916 pci_disable_device(chip->pci);
07e4ca50 917 kfree(chip->azx_dev);
4918cdab
TI		 918#ifdef CONFIG_SND_HDA_PATCH_LOADER
919 if (chip->fw)
920 release_firmware(chip->fw);
921#endif
99a2008d
WX		 922 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
923 hda_display_power(false);
924 hda_i915_exit();
925 }
1da177e4
LT		 926 kfree(chip);
927
928 return 0;
929}
930
a98f90fd 931static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 932{
933 return azx_free(device->device_data);
934}
935
8393ec4a 936#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 937/*
938 * Check of disabled HDMI controller by vga-switcheroo
939 */
e23e7a14 940static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 941{
942 struct pci_dev *p;
943
944 /* check only discrete GPU */
945 switch (pci->vendor) {
946 case PCI_VENDOR_ID_ATI:
947 case PCI_VENDOR_ID_AMD:
948 case PCI_VENDOR_ID_NVIDIA:
949 if (pci->devfn == 1) {
950 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
951 pci->bus->number, 0);
952 if (p) {
953 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
954 return p;
955 pci_dev_put(p);
956 }
957 }
958 break;
959 }
960 return NULL;
961}
962
e23e7a14 963static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 964{
965 bool vga_inactive = false;
966 struct pci_dev *p = get_bound_vga(pci);
967
968 if (p) {
12b78a7f 969 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 970 vga_inactive = true;
971 pci_dev_put(p);
972 }
973 return vga_inactive;
974}
8393ec4a 975#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 976
3372a153
TI		 977/*
978 * white/black-listing for position_fix
979 */
e23e7a14 980static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 981 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
982 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 983 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 984 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 985 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 986 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 987 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 988 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 989 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 990 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 991 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 992 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 993 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 994 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 995 {}
996};
997
e23e7a14 998static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 999{
1000 const struct snd_pci_quirk *q;
1001
c673ba1c 1002 switch (fix) {
1dac6695 1003 case POS_FIX_AUTO:
c673ba1c
TI		 1004 case POS_FIX_LPIB:
1005 case POS_FIX_POSBUF:
4cb36310 1006 case POS_FIX_VIACOMBO:
a6f2fd55 1007 case POS_FIX_COMBO:
c673ba1c
TI		 1008 return fix;
1009 }
1010
c673ba1c
TI		 1011 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1012 if (q) {
4e76a883
TI		 1013 dev_info(chip->card->dev,
1014 "position_fix set to %d for device %04x:%04x\n",
1015 q->value, q->subvendor, q->subdevice);
c673ba1c 1016 return q->value;
3372a153 1017 }
bdd9ef24
DH		 1018
1019 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 1020 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
4e76a883 1021 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1022 return POS_FIX_VIACOMBO;
9477c58e
TI		 1023 }
1024 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1025 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1026 return POS_FIX_LPIB;
bdd9ef24 1027 }
c673ba1c 1028 return POS_FIX_AUTO;
3372a153
TI		 1029}
1030
669ba27a
TI		 1031/*
1032 * black-lists for probe_mask
1033 */
e23e7a14 1034static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1035 /* Thinkpad often breaks the controller communication when accessing
1036 * to the non-working (or non-existing) modem codec slot.
1037 */
1038 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1039 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1040 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1041 /* broken BIOS */
1042 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1043 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1044 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1045 /* forced codec slots */
93574844 1046 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1047 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1048 /* WinFast VP200 H (Teradici) user reported broken communication */
1049 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1050 {}
1051};
1052
f1eaaeec
TI		 1053#define AZX_FORCE_CODEC_MASK 0x100
1054
e23e7a14 1055static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1056{
1057 const struct snd_pci_quirk *q;
1058
f1eaaeec
TI		 1059 chip->codec_probe_mask = probe_mask[dev];
1060 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1061 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1062 if (q) {
4e76a883
TI		 1063 dev_info(chip->card->dev,
1064 "probe_mask set to 0x%x for device %04x:%04x\n",
1065 q->value, q->subvendor, q->subdevice);
f1eaaeec 1066 chip->codec_probe_mask = q->value;
669ba27a
TI		 1067 }
1068 }
f1eaaeec
TI		 1069
1070 /* check forced option */
1071 if (chip->codec_probe_mask != -1 &&
1072 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1073 chip->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883
TI		 1074 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1075 chip->codec_mask);
f1eaaeec 1076 }
669ba27a
TI		 1077}
1078
4d8e22e0 1079/*
71623855 1080 * white/black-list for enable_msi
4d8e22e0 1081 */
e23e7a14 1082static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1083 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1084 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1085 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1086 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1087 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1088 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1089 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1090 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1091 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1092 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1093 {}
1094};
1095
e23e7a14 1096static void check_msi(struct azx *chip)
4d8e22e0
TI		 1097{
1098 const struct snd_pci_quirk *q;
1099
71623855
TI		 1100 if (enable_msi >= 0) {
1101 chip->msi = !!enable_msi;
4d8e22e0 1102 return;
71623855
TI		 1103 }
1104 chip->msi = 1; /* enable MSI as default */
1105 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1106 if (q) {
4e76a883
TI		 1107 dev_info(chip->card->dev,
1108 "msi for device %04x:%04x set to %d\n",
1109 q->subvendor, q->subdevice, q->value);
4d8e22e0 1110 chip->msi = q->value;
80c43ed7
TI		 1111 return;
1112 }
1113
1114 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1115 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1116 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1117 chip->msi = 0;
4d8e22e0
TI		 1118 }
1119}
1120
a1585d76 1121/* check the snoop mode availability */
e23e7a14 1122static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 1123{
1124 bool snoop = chip->snoop;
1125
1126 switch (chip->driver_type) {
1127 case AZX_DRIVER_VIA:
1128 /* force to non-snoop mode for a new VIA controller
1129 * when BIOS is set
1130 */
1131 if (snoop) {
1132 u8 val;
1133 pci_read_config_byte(chip->pci, 0x42, &val);
1134 if (!(val & 0x80) && chip->pci->revision == 0x30)
1135 snoop = false;
1136 }
1137 break;
1138 case AZX_DRIVER_ATIHDMI_NS:
1139 /* new ATI HDMI requires non-snoop */
1140 snoop = false;
1141 break;
c1279f87
TI		 1142 case AZX_DRIVER_CTHDA:
1143 snoop = false;
1144 break;
a1585d76
TI		 1145 }
1146
1147 if (snoop != chip->snoop) {
4e76a883
TI		 1148 dev_info(chip->card->dev, "Force to %s mode\n",
1149 snoop ? "snoop" : "non-snoop");
a1585d76
TI		 1150 chip->snoop = snoop;
1151 }
1152}
669ba27a 1153
99a2008d
WX		 1154static void azx_probe_work(struct work_struct *work)
1155{
1156 azx_probe_continue(container_of(work, struct azx, probe_work));
1157}
99a2008d 1158
1da177e4
LT		 1159/*
1160 * constructor
1161 */
e23e7a14
BP		 1162static int azx_create(struct snd_card *card, struct pci_dev *pci,
1163 int dev, unsigned int driver_caps,
40830813 1164 const struct hda_controller_ops *hda_ops,
e23e7a14 1165 struct azx **rchip)
1da177e4 1166{
a98f90fd 1167 static struct snd_device_ops ops = {
1da177e4
LT		 1168 .dev_free = azx_dev_free,
1169 };
a82d51ed
TI		 1170 struct azx *chip;
1171 int err;
1da177e4
LT		 1172
1173 *rchip = NULL;
bcd72003 1174
927fc866
PM		 1175 err = pci_enable_device(pci);
1176 if (err < 0)
1da177e4
LT		 1177 return err;
1178
e560d8d8 1179 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 1180 if (!chip) {
4e76a883 1181 dev_err(card->dev, "Cannot allocate chip\n");
1da177e4
LT		 1182 pci_disable_device(pci);
1183 return -ENOMEM;
1184 }
1185
1186 spin_lock_init(&chip->reg_lock);
62932df8 1187 mutex_init(&chip->open_mutex);
1da177e4
LT		 1188 chip->card = card;
1189 chip->pci = pci;
40830813 1190 chip->ops = hda_ops;
1da177e4 1191 chip->irq = -1;
9477c58e
TI		 1192 chip->driver_caps = driver_caps;
1193 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1194 check_msi(chip);
555e219f 1195 chip->dev_index = dev;
749ee287 1196 chip->jackpoll_ms = jackpoll_ms;
9ad593f6 1197 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 1198 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 1199 INIT_LIST_HEAD(&chip->list);
a82d51ed 1200 init_vga_switcheroo(chip);
f4c482a4 1201 init_completion(&chip->probe_wait);
1da177e4 1202
beaffc39
SG		 1203 chip->position_fix[0] = chip->position_fix[1] =
1204 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 1205 /* combo mode uses LPIB for playback */
1206 if (chip->position_fix[0] == POS_FIX_COMBO) {
1207 chip->position_fix[0] = POS_FIX_LPIB;
1208 chip->position_fix[1] = POS_FIX_AUTO;
1209 }
1210
5aba4f8e 1211 check_probe_mask(chip, dev);
3372a153 1212
27346166 1213 chip->single_cmd = single_cmd;
27fe48d9 1214 chip->snoop = hda_snoop;
a1585d76 1215 azx_check_snoop_available(chip);
c74db86b 1216
5c0d7bc1
TI		 1217 if (bdl_pos_adj[dev] < 0) {
1218 switch (chip->driver_type) {
0c6341ac 1219 case AZX_DRIVER_ICH:
32679f95 1220 case AZX_DRIVER_PCH:
0c6341ac 1221 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 1222 break;
1223 default:
0c6341ac 1224 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 1225 break;
1226 }
1227 }
9cdc0115 1228 chip->bdl_pos_adj = bdl_pos_adj;
5c0d7bc1 1229
a82d51ed
TI		 1230 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1231 if (err < 0) {
4e76a883 1232 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1233 azx_free(chip);
1234 return err;
1235 }
1236
99a2008d
WX		 1237 /* continue probing in work context as may trigger request module */
1238 INIT_WORK(&chip->probe_work, azx_probe_work);
99a2008d 1239
a82d51ed 1240 *rchip = chip;
99a2008d 1241
a82d51ed
TI		 1242 return 0;
1243}
1244
48c8b0eb 1245static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1246{
1247 int dev = chip->dev_index;
1248 struct pci_dev *pci = chip->pci;
1249 struct snd_card *card = chip->card;
67908994 1250 int err;
a82d51ed
TI		 1251 unsigned short gcap;
1252
07e4ca50
TI		 1253#if BITS_PER_LONG != 64
1254 /* Fix up base address on ULI M5461 */
1255 if (chip->driver_type == AZX_DRIVER_ULI) {
1256 u16 tmp3;
1257 pci_read_config_word(pci, 0x40, &tmp3);
1258 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1259 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1260 }
1261#endif
1262
927fc866 1263 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1264 if (err < 0)
1da177e4 1265 return err;
a82d51ed 1266 chip->region_requested = 1;
1da177e4 1267
927fc866 1268 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 1269 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 1270 if (chip->remap_addr == NULL) {
4e76a883 1271 dev_err(card->dev, "ioremap error\n");
a82d51ed 1272 return -ENXIO;
1da177e4
LT		 1273 }
1274
68e7fffc
TI		 1275 if (chip->msi)
1276 if (pci_enable_msi(pci) < 0)
1277 chip->msi = 0;
7376d013 1278
a82d51ed
TI		 1279 if (azx_acquire_irq(chip, 0) < 0)
1280 return -EBUSY;
1da177e4
LT		 1281
1282 pci_set_master(pci);
1283 synchronize_irq(chip->irq);
1284
bcd72003 1285 gcap = azx_readw(chip, GCAP);
4e76a883 1286 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1287
dc4c2e6b 1288 /* disable SB600 64bit support for safety */
9477c58e 1289 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 1290 struct pci_dev *p_smbus;
1291 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1292 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1293 NULL);
1294 if (p_smbus) {
1295 if (p_smbus->revision < 0x30)
1296 gcap &= ~ICH6_GCAP_64OK;
1297 pci_dev_put(p_smbus);
1298 }
1299 }
09240cf4 1300
9477c58e
TI		 1301 /* disable 64bit DMA address on some devices */
1302 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1303 dev_dbg(card->dev, "Disabling 64bit DMA\n");
396087ea 1304 gcap &= ~ICH6_GCAP_64OK;
9477c58e 1305 }
396087ea 1306
2ae66c26 1307 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1308 if (align_buffer_size >= 0)
1309 chip->align_buffer_size = !!align_buffer_size;
1310 else {
1311 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
1312 chip->align_buffer_size = 0;
1313 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
1314 chip->align_buffer_size = 1;
1315 else
1316 chip->align_buffer_size = 1;
1317 }
2ae66c26 1318
cf7aaca8 1319 /* allow 64bit DMA address if supported by H/W */
b21fadb9 1320 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 1321 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 1322 else {
e930438c
YH		 1323 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1324 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 1325 }
cf7aaca8 1326
8b6ed8e7
TI		 1327 /* read number of streams from GCAP register instead of using
1328 * hardcoded value
1329 */
1330 chip->capture_streams = (gcap >> 8) & 0x0f;
1331 chip->playback_streams = (gcap >> 12) & 0x0f;
1332 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1333 /* gcap didn't give any info, switching to old method */
1334
1335 switch (chip->driver_type) {
1336 case AZX_DRIVER_ULI:
1337 chip->playback_streams = ULI_NUM_PLAYBACK;
1338 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1339 break;
1340 case AZX_DRIVER_ATIHDMI:
1815b34a 1341 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1342 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1343 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1344 break;
c4da29ca 1345 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1346 default:
1347 chip->playback_streams = ICH6_NUM_PLAYBACK;
1348 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1349 break;
1350 }
07e4ca50 1351 }
8b6ed8e7
TI		 1352 chip->capture_index_offset = 0;
1353 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1354 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 1355 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1356 GFP_KERNEL);
927fc866 1357 if (!chip->azx_dev) {
4e76a883 1358 dev_err(card->dev, "cannot malloc azx_dev\n");
a82d51ed 1359 return -ENOMEM;
07e4ca50
TI		 1360 }
1361
67908994 1362 err = azx_alloc_stream_pages(chip);
81740861 1363 if (err < 0)
a82d51ed 1364 return err;
1da177e4
LT		 1365
1366 /* initialize streams */
1367 azx_init_stream(chip);
1368
1369 /* initialize chip */
cb53c626 1370 azx_init_pci(chip);
10e77dda 1371 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1372
1373 /* codec detection */
927fc866 1374 if (!chip->codec_mask) {
4e76a883 1375 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1376 return -ENODEV;
1da177e4
LT		 1377 }
1378
07e4ca50 1379 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1380 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1381 sizeof(card->shortname));
1382 snprintf(card->longname, sizeof(card->longname),
1383 "%s at 0x%lx irq %i",
1384 card->shortname, chip->addr, chip->irq);
07e4ca50 1385
1da177e4 1386 return 0;
1da177e4
LT		 1387}
1388
cb53c626
TI		 1389static void power_down_all_codecs(struct azx *chip)
1390{
83012a7c 1391#ifdef CONFIG_PM
cb53c626
TI		 1392 /* The codecs were powered up in snd_hda_codec_new().
1393 * Now all initialization done, so turn them down if possible
1394 */
1395 struct hda_codec *codec;
1396 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1397 snd_hda_power_down(codec);
1398 }
1399#endif
1400}
1401
97c6a3d1 1402#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1403/* callback from request_firmware_nowait() */
1404static void azx_firmware_cb(const struct firmware *fw, void *context)
1405{
1406 struct snd_card *card = context;
1407 struct azx *chip = card->private_data;
1408 struct pci_dev *pci = chip->pci;
1409
1410 if (!fw) {
4e76a883 1411 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1412 goto error;
1413 }
1414
1415 chip->fw = fw;
1416 if (!chip->disabled) {
1417 /* continue probing */
1418 if (azx_probe_continue(chip))
1419 goto error;
1420 }
1421 return; /* OK */
1422
1423 error:
1424 snd_card_free(card);
1425 pci_set_drvdata(pci, NULL);
1426}
97c6a3d1 1427#endif
5cb543db 1428
40830813
DR		 1429/*
1430 * HDA controller ops.
1431 */
1432
1433/* PCI register access. */
db291e36 1434static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1435{
1436 writel(value, addr);
1437}
1438
db291e36 1439static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1440{
1441 return readl(addr);
1442}
1443
db291e36 1444static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1445{
1446 writew(value, addr);
1447}
1448
db291e36 1449static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1450{
1451 return readw(addr);
1452}
1453
db291e36 1454static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1455{
1456 writeb(value, addr);
1457}
1458
db291e36 1459static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1460{
1461 return readb(addr);
1462}
1463
f46ea609
DR		 1464static int disable_msi_reset_irq(struct azx *chip)
1465{
1466 int err;
1467
1468 free_irq(chip->irq, chip);
1469 chip->irq = -1;
1470 pci_disable_msi(chip->pci);
1471 chip->msi = 0;
1472 err = azx_acquire_irq(chip, 1);
1473 if (err < 0)
1474 return err;
1475
1476 return 0;
1477}
1478
b419b35b
DR		 1479/* DMA page allocation helpers. */
1480static int dma_alloc_pages(struct azx *chip,
1481 int type,
1482 size_t size,
1483 struct snd_dma_buffer *buf)
1484{
1485 int err;
1486
1487 err = snd_dma_alloc_pages(type,
1488 chip->card->dev,
1489 size, buf);
1490 if (err < 0)
1491 return err;
1492 mark_pages_wc(chip, buf, true);
1493 return 0;
1494}
1495
1496static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1497{
1498 mark_pages_wc(chip, buf, false);
1499 snd_dma_free_pages(buf);
1500}
1501
1502static int substream_alloc_pages(struct azx *chip,
1503 struct snd_pcm_substream *substream,
1504 size_t size)
1505{
1506 struct azx_dev *azx_dev = get_azx_dev(substream);
1507 int ret;
1508
1509 mark_runtime_wc(chip, azx_dev, substream, false);
1510 azx_dev->bufsize = 0;
1511 azx_dev->period_bytes = 0;
1512 azx_dev->format_val = 0;
1513 ret = snd_pcm_lib_malloc_pages(substream, size);
1514 if (ret < 0)
1515 return ret;
1516 mark_runtime_wc(chip, azx_dev, substream, true);
1517 return 0;
1518}
1519
1520static int substream_free_pages(struct azx *chip,
1521 struct snd_pcm_substream *substream)
1522{
1523 struct azx_dev *azx_dev = get_azx_dev(substream);
1524 mark_runtime_wc(chip, azx_dev, substream, false);
1525 return snd_pcm_lib_free_pages(substream);
1526}
1527
8769b278
DR		 1528static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1529 struct vm_area_struct *area)
1530{
1531#ifdef CONFIG_X86
1532 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1533 struct azx *chip = apcm->chip;
1534 if (!azx_snoop(chip))
1535 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1536#endif
1537}
1538
40830813 1539static const struct hda_controller_ops pci_hda_ops = {
778bde6f
DR		 1540 .reg_writel = pci_azx_writel,
1541 .reg_readl = pci_azx_readl,
1542 .reg_writew = pci_azx_writew,
1543 .reg_readw = pci_azx_readw,
1544 .reg_writeb = pci_azx_writeb,
1545 .reg_readb = pci_azx_readb,
f46ea609 1546 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 1547 .dma_alloc_pages = dma_alloc_pages,
1548 .dma_free_pages = dma_free_pages,
1549 .substream_alloc_pages = substream_alloc_pages,
1550 .substream_free_pages = substream_free_pages,
8769b278 1551 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 1552 .position_check = azx_position_check,
40830813
DR		 1553};
1554
e23e7a14
BP		 1555static int azx_probe(struct pci_dev *pci,
1556 const struct pci_device_id *pci_id)
1da177e4 1557{
5aba4f8e 1558 static int dev;
a98f90fd
TI		 1559 struct snd_card *card;
1560 struct azx *chip;
aad730d0 1561 bool schedule_probe;
927fc866 1562 int err;
1da177e4 1563
5aba4f8e
TI		 1564 if (dev >= SNDRV_CARDS)
1565 return -ENODEV;
1566 if (!enable[dev]) {
1567 dev++;
1568 return -ENOENT;
1569 }
1570
60c5772b
TI		 1571 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1572 0, &card);
e58de7ba 1573 if (err < 0) {
4e76a883 1574 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 1575 return err;
1da177e4
LT		 1576 }
1577
40830813
DR		 1578 err = azx_create(card, pci, dev, pci_id->driver_data,
1579 &pci_hda_ops, &chip);
41dda0fd
WF		 1580 if (err < 0)
1581 goto out_free;
421a1252 1582 card->private_data = chip;
f4c482a4
TI		 1583
1584 pci_set_drvdata(pci, card);
1585
1586 err = register_vga_switcheroo(chip);
1587 if (err < 0) {
4e76a883 1588 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
f4c482a4
TI		 1589 goto out_free;
1590 }
1591
1592 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 1593 dev_info(card->dev, "VGA controller is disabled\n");
1594 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 1595 chip->disabled = true;
1596 }
1597
aad730d0 1598 schedule_probe = !chip->disabled;
1da177e4 1599
4918cdab
TI		 1600#ifdef CONFIG_SND_HDA_PATCH_LOADER
1601 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 1602 dev_info(card->dev, "Applying patch firmware '%s'\n",
1603 patch[dev]);
5cb543db
TI		 1604 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1605 &pci->dev, GFP_KERNEL, card,
1606 azx_firmware_cb);
4918cdab
TI		 1607 if (err < 0)
1608 goto out_free;
aad730d0 1609 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 1610 }
1611#endif /* CONFIG_SND_HDA_PATCH_LOADER */
1612
aad730d0
TI		 1613#ifndef CONFIG_SND_HDA_I915
1614 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
4e76a883 1615 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
99a2008d 1616#endif
99a2008d 1617
aad730d0
TI		 1618 if (schedule_probe)
1619 schedule_work(&chip->probe_work);
a82d51ed 1620
a82d51ed 1621 dev++;
88d071fc
TI		 1622 if (chip->disabled)
1623 complete_all(&chip->probe_wait);
a82d51ed
TI		 1624 return 0;
1625
1626out_free:
1627 snd_card_free(card);
1628 return err;
1629}
1630
e62a42ae
DR		 1631/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1632static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1633 [AZX_DRIVER_NVIDIA] = 8,
1634 [AZX_DRIVER_TERA] = 1,
1635};
1636
48c8b0eb 1637static int azx_probe_continue(struct azx *chip)
a82d51ed 1638{
c67e2228 1639 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 1640 int dev = chip->dev_index;
1641 int err;
1642
99a2008d
WX		 1643 /* Request power well for Haswell HDA controller and codec */
1644 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
c841ad2a 1645#ifdef CONFIG_SND_HDA_I915
99a2008d
WX		 1646 err = hda_i915_init();
1647 if (err < 0) {
4e76a883
TI		 1648 dev_err(chip->card->dev,
1649 "Error request power-well from i915\n");
99a2008d
WX		 1650 goto out_free;
1651 }
c841ad2a 1652#endif
99a2008d
WX		 1653 hda_display_power(true);
1654 }
1655
5c90680e
TI		 1656 err = azx_first_init(chip);
1657 if (err < 0)
1658 goto out_free;
1659
2dca0bba
JK		 1660#ifdef CONFIG_SND_HDA_INPUT_BEEP
1661 chip->beep_mode = beep_mode[dev];
1662#endif
1663
1da177e4 1664 /* create codec instances */
e62a42ae
DR		 1665 err = azx_codec_create(chip, model[dev],
1666 azx_max_codecs[chip->driver_type],
1667 power_save_addr);
1668
41dda0fd
WF		 1669 if (err < 0)
1670 goto out_free;
4ea6fbc8 1671#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 1672 if (chip->fw) {
1673 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1674 chip->fw->data);
4ea6fbc8
TI		 1675 if (err < 0)
1676 goto out_free;
e39ae856 1677#ifndef CONFIG_PM
4918cdab
TI		 1678 release_firmware(chip->fw); /* no longer needed */
1679 chip->fw = NULL;
e39ae856 1680#endif
4ea6fbc8
TI		 1681 }
1682#endif
10e77dda 1683 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 1684 err = azx_codec_configure(chip);
1685 if (err < 0)
1686 goto out_free;
1687 }
1da177e4
LT		 1688
1689 /* create PCM streams */
176d5335 1690 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 1691 if (err < 0)
1692 goto out_free;
1da177e4
LT		 1693
1694 /* create mixer controls */
d01ce99f 1695 err = azx_mixer_create(chip);
41dda0fd
WF		 1696 if (err < 0)
1697 goto out_free;
1da177e4 1698
a82d51ed 1699 err = snd_card_register(chip->card);
41dda0fd
WF		 1700 if (err < 0)
1701 goto out_free;
1da177e4 1702
cb53c626
TI		 1703 chip->running = 1;
1704 power_down_all_codecs(chip);
0cbf0098 1705 azx_notifier_register(chip);
65fcd41d 1706 azx_add_card_list(chip);
246efa4a 1707 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
c67e2228 1708 pm_runtime_put_noidle(&pci->dev);
1da177e4 1709
41dda0fd 1710out_free:
88d071fc
TI		 1711 if (err < 0)
1712 chip->init_failed = 1;
1713 complete_all(&chip->probe_wait);
41dda0fd 1714 return err;
1da177e4
LT		 1715}
1716
e23e7a14 1717static void azx_remove(struct pci_dev *pci)
1da177e4 1718{
9121947d 1719 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462 1720
9121947d
TI		 1721 if (card)
1722 snd_card_free(card);
1da177e4
LT		 1723}
1724
1725/* PCI IDs */
cebe41d4 1726static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 1727 /* CPT */
9477c58e 1728 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 1729 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 1730 /* PBG */
9477c58e 1731 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 1732 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 1733 /* Panther Point */
9477c58e 1734 { PCI_DEVICE(0x8086, 0x1e20),
b1920c21 1735 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 1736 /* Lynx Point */
1737 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 1738 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 1739 /* Wellsburg */
1740 { PCI_DEVICE(0x8086, 0x8d20),
1741 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1742 { PCI_DEVICE(0x8086, 0x8d21),
1743 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1744 /* Lynx Point-LP */
1745 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 1746 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 1747 /* Lynx Point-LP */
1748 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 1749 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 1750 /* Wildcat Point-LP */
1751 { PCI_DEVICE(0x8086, 0x9ca0),
1752 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8 1753 /* Haswell */
4a7c516b 1754 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 1755 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 1756 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 1757 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 1758 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 1759 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 1760 /* Broadwell */
1761 { PCI_DEVICE(0x8086, 0x160c),
1762 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
99df18b3
PLB		 1763 /* 5 Series/3400 */
1764 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 1765 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 1766 /* Poulsbo */
9477c58e 1767 { PCI_DEVICE(0x8086, 0x811b),
f748abcc
TI		 1768 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
1769 /* Oaktrail */
09904b95 1770 { PCI_DEVICE(0x8086, 0x080a),
f748abcc 1771 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
e44007e0
CCE		 1772 /* BayTrail */
1773 { PCI_DEVICE(0x8086, 0x0f04),
1774 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
645e9035 1775 /* ICH */
8b0bd226 1776 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 1777 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1778 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 1779 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 1780 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1781 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 1782 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 1783 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1784 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 1785 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 1786 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1787 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 1788 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 1789 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1790 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 1791 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 1792 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1793 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 1794 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 1795 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1796 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 1797 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 1798 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
1799 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 1800 /* Generic Intel */
1801 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
1802 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1803 .class_mask = 0xffffff,
2ae66c26 1804 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 1805 /* ATI SB 450/600/700/800/900 */
1806 { PCI_DEVICE(0x1002, 0x437b),
1807 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
1808 { PCI_DEVICE(0x1002, 0x4383),
1809 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
1810 /* AMD Hudson */
1811 { PCI_DEVICE(0x1022, 0x780d),
1812 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 1813 /* ATI HDMI */
9477c58e
TI		 1814 { PCI_DEVICE(0x1002, 0x793b),
1815 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1816 { PCI_DEVICE(0x1002, 0x7919),
1817 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1818 { PCI_DEVICE(0x1002, 0x960f),
1819 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1820 { PCI_DEVICE(0x1002, 0x970f),
1821 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1822 { PCI_DEVICE(0x1002, 0xaa00),
1823 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1824 { PCI_DEVICE(0x1002, 0xaa08),
1825 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1826 { PCI_DEVICE(0x1002, 0xaa10),
1827 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1828 { PCI_DEVICE(0x1002, 0xaa18),
1829 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1830 { PCI_DEVICE(0x1002, 0xaa20),
1831 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1832 { PCI_DEVICE(0x1002, 0xaa28),
1833 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1834 { PCI_DEVICE(0x1002, 0xaa30),
1835 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1836 { PCI_DEVICE(0x1002, 0xaa38),
1837 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1838 { PCI_DEVICE(0x1002, 0xaa40),
1839 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1840 { PCI_DEVICE(0x1002, 0xaa48),
1841 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 1842 { PCI_DEVICE(0x1002, 0xaa50),
1843 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1844 { PCI_DEVICE(0x1002, 0xaa58),
1845 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1846 { PCI_DEVICE(0x1002, 0xaa60),
1847 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1848 { PCI_DEVICE(0x1002, 0xaa68),
1849 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1850 { PCI_DEVICE(0x1002, 0xaa80),
1851 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1852 { PCI_DEVICE(0x1002, 0xaa88),
1853 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1854 { PCI_DEVICE(0x1002, 0xaa90),
1855 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1856 { PCI_DEVICE(0x1002, 0xaa98),
1857 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 1858 { PCI_DEVICE(0x1002, 0x9902),
1859 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1860 { PCI_DEVICE(0x1002, 0xaaa0),
1861 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1862 { PCI_DEVICE(0x1002, 0xaaa8),
1863 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
1864 { PCI_DEVICE(0x1002, 0xaab0),
1865 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 1866 /* VIA VT8251/VT8237A */
9477c58e
TI		 1867 { PCI_DEVICE(0x1106, 0x3288),
1868 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 1869 /* VIA GFX VT7122/VX900 */
1870 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
1871 /* VIA GFX VT6122/VX11 */
1872 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 1873 /* SIS966 */
1874 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
1875 /* ULI M5461 */
1876 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
1877 /* NVIDIA MCP */
0c2fd1bf
TI		 1878 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1879 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1880 .class_mask = 0xffffff,
9477c58e 1881 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 1882 /* Teradici */
9477c58e
TI		 1883 { PCI_DEVICE(0x6549, 0x1200),
1884 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 1885 { PCI_DEVICE(0x6549, 0x2200),
1886 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 1887 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 1888 /* CTHDA chips */
1889 { PCI_DEVICE(0x1102, 0x0010),
1890 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
1891 { PCI_DEVICE(0x1102, 0x0012),
1892 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 1893#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 1894 /* the following entry conflicts with snd-ctxfi driver,
1895 * as ctxfi driver mutates from HD-audio to native mode with
1896 * a special command sequence.
1897 */
4e01f54b
TI		 1898 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
1899 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1900 .class_mask = 0xffffff,
9477c58e 1901 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 1902 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 1903#else
1904 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 1905 { PCI_DEVICE(0x1102, 0x0009),
1906 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 1907 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 1908#endif
e35d4b11
OS		 1909 /* Vortex86MX */
1910 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 1911 /* VMware HDAudio */
1912 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 1913 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 1914 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
1915 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1916 .class_mask = 0xffffff,
9477c58e 1917 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 1918 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
1919 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
1920 .class_mask = 0xffffff,
9477c58e 1921 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 1922 { 0, }
1923};
1924MODULE_DEVICE_TABLE(pci, azx_ids);
1925
1926/* pci_driver definition */
e9f66d9b 1927static struct pci_driver azx_driver = {
3733e424 1928 .name = KBUILD_MODNAME,
1da177e4
LT		 1929 .id_table = azx_ids,
1930 .probe = azx_probe,
e23e7a14 1931 .remove = azx_remove,
68cb2b55
TI		 1932 .driver = {
1933 .pm = AZX_PM_OPS,
1934 },
1da177e4
LT		 1935};
1936
e9f66d9b 1937module_pci_driver(azx_driver);
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