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ALSA: hda/intel: Drop superfluous AZX_DCAPS_I915_POWERWELL checks
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
7f80f513 56#include <asm/set_memory.h>
50279d9b 57#include <asm/cpufeature.h>
27fe48d9 58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
98d8fc6c
ML		 61#include <sound/hdaudio.h>
62#include <sound/hda_i915.h>
9121947d 63#include <linux/vgaarb.h>
a82d51ed 64#include <linux/vga_switcheroo.h>
4918cdab 65#include <linux/firmware.h>
be57bfff 66#include <sound/hda_codec.h>
05e84878 67#include "hda_controller.h"
347de1f8 68#include "hda_intel.h"
1da177e4 69
785d8c4b
LY		 70#define CREATE_TRACE_POINTS
71#include "hda_intel_trace.h"
72
b6050ef6
TI		 73/* position fix mode */
74enum {
75 POS_FIX_AUTO,
76 POS_FIX_LPIB,
77 POS_FIX_POSBUF,
78 POS_FIX_VIACOMBO,
79 POS_FIX_COMBO,
f87e7f25 80 POS_FIX_SKL,
b6050ef6
TI		 81};
82
9a34af4a
TI		 83/* Defines for ATI HD Audio support in SB450 south bridge */
84#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
85#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
86
87/* Defines for Nvidia HDA support */
88#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
89#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
90#define NVIDIA_HDA_ISTRM_COH 0x4d
91#define NVIDIA_HDA_OSTRM_COH 0x4c
92#define NVIDIA_HDA_ENABLE_COHBIT 0x01
93
94/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 95#define INTEL_HDA_CGCTL 0x48
96#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 97#define INTEL_SCH_HDA_DEVC 0x78
98#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
99
100/* Define IN stream 0 FIFO size offset in VIA controller */
101#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
102/* Define VIA HD Audio Device ID*/
103#define VIA_HDAC_DEVICE_ID 0x3288
104
33124929
TI		 105/* max number of SDs */
106/* ICH, ATI and VIA have 4 playback and 4 capture */
107#define ICH6_NUM_CAPTURE 4
108#define ICH6_NUM_PLAYBACK 4
109
110/* ULI has 6 playback and 5 capture */
111#define ULI_NUM_CAPTURE 5
112#define ULI_NUM_PLAYBACK 6
113
114/* ATI HDMI may have up to 8 playbacks and 0 capture */
115#define ATIHDMI_NUM_CAPTURE 0
116#define ATIHDMI_NUM_PLAYBACK 8
117
118/* TERA has 4 playback and 3 capture */
119#define TERA_NUM_CAPTURE 3
120#define TERA_NUM_PLAYBACK 4
121
1da177e4 122
5aba4f8e
TI		 123static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
124static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 125static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 126static char *model[SNDRV_CARDS];
1dac6695 127static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 128static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 129static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 130static int probe_only[SNDRV_CARDS];
26a6cb6c 131static int jackpoll_ms[SNDRV_CARDS];
41438f13 132static int single_cmd = -1;
71623855 133static int enable_msi = -1;
4ea6fbc8
TI		 134#ifdef CONFIG_SND_HDA_PATCH_LOADER
135static char *patch[SNDRV_CARDS];
136#endif
2dca0bba 137#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 138static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 139 CONFIG_SND_HDA_INPUT_BEEP_MODE};
140#endif
1da177e4 141
5aba4f8e 142module_param_array(index, int, NULL, 0444);
1da177e4 143MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 144module_param_array(id, charp, NULL, 0444);
1da177e4 145MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 146module_param_array(enable, bool, NULL, 0444);
147MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
148module_param_array(model, charp, NULL, 0444);
1da177e4 149MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 150module_param_array(position_fix, int, NULL, 0444);
4cb36310 151MODULE_PARM_DESC(position_fix, "DMA pointer read method."
f87e7f25 152 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
555e219f
TI		 153module_param_array(bdl_pos_adj, int, NULL, 0644);
154MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 155module_param_array(probe_mask, int, NULL, 0444);
606ad75f 156MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 157module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 158MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 159module_param_array(jackpoll_ms, int, NULL, 0444);
160MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 161module_param(single_cmd, bint, 0444);
d01ce99f
TI		 162MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
163 "(for debugging only).");
ac9ef6cf 164module_param(enable_msi, bint, 0444);
134a11f0 165MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 166#ifdef CONFIG_SND_HDA_PATCH_LOADER
167module_param_array(patch, charp, NULL, 0444);
168MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
169#endif
2dca0bba 170#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 171module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 172MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 173 "(0=off, 1=on) (default=1).");
2dca0bba 174#endif
606ad75f 175
83012a7c 176#ifdef CONFIG_PM
65fcd41d 177static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 178static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 179 .set = param_set_xint,
180 .get = param_get_int,
181};
182#define param_check_xint param_check_int
183
fee2fba3 184static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 185module_param(power_save, xint, 0644);
fee2fba3
TI		 186MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
187 "(in second, 0 = disable).");
1da177e4 188
40088dc4
TI		 189static bool pm_blacklist = true;
190module_param(pm_blacklist, bool, 0644);
191MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
192
dee1b66c
TI		 193/* reset the HD-audio controller in power save mode.
194 * this may give more power-saving, but will take longer time to
195 * wake up.
196 */
8fc24426
TI		 197static bool power_save_controller = 1;
198module_param(power_save_controller, bool, 0644);
dee1b66c 199MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 200#else
bb573928 201#define power_save 0
83012a7c 202#endif /* CONFIG_PM */
dee1b66c 203
7bfe059e
TI		 204static int align_buffer_size = -1;
205module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 206MODULE_PARM_DESC(align_buffer_size,
207 "Force buffer and period sizes to be multiple of 128 bytes.");
208
27fe48d9 209#ifdef CONFIG_X86
7c732015
TI		 210static int hda_snoop = -1;
211module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 212MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 213#else
214#define hda_snoop true
27fe48d9
TI		 215#endif
216
217
1da177e4
LT		 218MODULE_LICENSE("GPL");
219MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
220 "{Intel, ICH6M},"
2f1b3818 221 "{Intel, ICH7},"
f5d40b30 222 "{Intel, ESB2},"
d2981393 223 "{Intel, ICH8},"
f9cc8a8b 224 "{Intel, ICH9},"
c34f5a04 225 "{Intel, ICH10},"
b29c2360 226 "{Intel, PCH},"
d2f2fcd2 227 "{Intel, CPT},"
d2edeb7c 228 "{Intel, PPT},"
8bc039a1 229 "{Intel, LPT},"
144dad99 230 "{Intel, LPT_LP},"
4eeca499 231 "{Intel, WPT_LP},"
c8b00fd2 232 "{Intel, SPT},"
b4565913 233 "{Intel, SPT_LP},"
e926f2c8 234 "{Intel, HPT},"
cea310e8 235 "{Intel, PBG},"
4979bca9 236 "{Intel, SCH},"
fc20a562 237 "{ATI, SB450},"
89be83f8 238 "{ATI, SB600},"
778b6e1b 239 "{ATI, RS600},"
5b15c95f 240 "{ATI, RS690},"
e6db1119
WL		 241 "{ATI, RS780},"
242 "{ATI, R600},"
2797f724
HRK		 243 "{ATI, RV630},"
244 "{ATI, RV610},"
27da1834
WL		 245 "{ATI, RV670},"
246 "{ATI, RV635},"
247 "{ATI, RV620},"
248 "{ATI, RV770},"
fc20a562 249 "{VIA, VT8251},"
47672310 250 "{VIA, VT8237A},"
07e4ca50
TI		 251 "{SiS, SIS966},"
252 "{ULI, M5461}}");
1da177e4
LT		 253MODULE_DESCRIPTION("Intel HDA driver");
254
a82d51ed 255#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 256#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 257#define SUPPORT_VGA_SWITCHEROO
258#endif
259#endif
260
261
1da177e4 262/*
1da177e4 263 */
1da177e4 264
07e4ca50
TI		 265/* driver types */
266enum {
267 AZX_DRIVER_ICH,
32679f95 268 AZX_DRIVER_PCH,
4979bca9 269 AZX_DRIVER_SCH,
a4b4793f 270 AZX_DRIVER_SKL,
fab1285a 271 AZX_DRIVER_HDMI,
07e4ca50 272 AZX_DRIVER_ATI,
778b6e1b 273 AZX_DRIVER_ATIHDMI,
1815b34a 274 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 275 AZX_DRIVER_VIA,
276 AZX_DRIVER_SIS,
277 AZX_DRIVER_ULI,
da3fca21 278 AZX_DRIVER_NVIDIA,
f269002e 279 AZX_DRIVER_TERA,
14d34f16 280 AZX_DRIVER_CTX,
5ae763b1 281 AZX_DRIVER_CTHDA,
c563f473 282 AZX_DRIVER_CMEDIA,
c4da29ca 283 AZX_DRIVER_GENERIC,
2f5983f2 284 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 285};
286
37e661ee
TI		 287#define azx_get_snoop_type(chip) \
288 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
289#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
290
b42b4afb
TI		 291/* quirks for old Intel chipsets */
292#define AZX_DCAPS_INTEL_ICH \
103884a3 293 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 294
2ea3c6a2 295/* quirks for Intel PCH */
6603249d 296#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 297 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
bcb337d1 298 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 299
dba9b7b6 300/* PCH up to IVB; no runtime PM; bind with i915 gfx */
6603249d 301#define AZX_DCAPS_INTEL_PCH_NOPM \
dba9b7b6 302 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
6603249d 303
55913110 304/* PCH for HSW/BDW; with runtime PM */
dba9b7b6 305/* no i915 binding for this as HSW/BDW has another controller for HDMI */
d7dab4db 306#define AZX_DCAPS_INTEL_PCH \
6603249d 307 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 308
6603249d 309/* HSW HDMI */
33499a15 310#define AZX_DCAPS_INTEL_HASWELL \
103884a3 311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
dba9b7b6 312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
e454ff8e 313 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 314
54a0405d
LY		 315/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
316#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 317 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
dba9b7b6 318 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
e454ff8e 319 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 320
40cc2392 321#define AZX_DCAPS_INTEL_BAYTRAIL \
e454ff8e 322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
40cc2392 323
2d846c74 324#define AZX_DCAPS_INTEL_BRASWELL \
dba9b7b6 325 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 326 AZX_DCAPS_I915_COMPONENT)
2d846c74 327
d6795827 328#define AZX_DCAPS_INTEL_SKYLAKE \
dba9b7b6 329 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 330 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
d6795827 331
c87693da 332#define AZX_DCAPS_INTEL_BROXTON \
dba9b7b6 333 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 334 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
c87693da 335
9477c58e
TI		 336/* quirks for ATI SB / AMD Hudson */
337#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 338 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
339 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 340
341/* quirks for ATI/AMD HDMI */
342#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 343 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
344 AZX_DCAPS_NO_MSI64)
9477c58e 345
37e661ee
TI		 346/* quirks for ATI HDMI with snoop off */
347#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
348 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
349
9477c58e
TI		 350/* quirks for Nvidia */
351#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 352 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 353 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 354
5ae763b1 355#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 356 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 357 AZX_DCAPS_NO_64BIT |\
37e661ee 358 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 359
a82d51ed 360/*
2b760d88 361 * vga_switcheroo support
a82d51ed
TI		 362 */
363#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db 364#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
37a3a98e 365#define needs_eld_notify_link(chip) ((chip)->need_eld_notify_link)
5cb543db
TI		 366#else
367#define use_vga_switcheroo(chip) 0
37a3a98e 368#define needs_eld_notify_link(chip) false
5cb543db
TI		 369#endif
370
03b135ce
LY		 371#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
372 ((pci)->device == 0x0c0c) || \
373 ((pci)->device == 0x0d0c) || \
374 ((pci)->device == 0x160c))
375
7e31a015 376#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
a8d7bde2 377#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
7c23b7c1 378
48c8b0eb 379static char *driver_short_names[] = {
07e4ca50 380 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 381 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 382 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 383 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 384 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 385 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 386 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 387 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 388 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
389 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 390 [AZX_DRIVER_ULI] = "HDA ULI M5461",
391 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 392 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 393 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 394 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 395 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 396 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 397};
398
68e7fffc 399static int azx_acquire_irq(struct azx *chip, int do_disconnect);
37a3a98e 400static void set_default_power_save(struct azx *chip);
111d3af5 401
cb53c626
TI		 402/*
403 * initialize the PCI registers
404 */
405/* update bits in a PCI register byte */
406static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
407 unsigned char mask, unsigned char val)
408{
409 unsigned char data;
410
411 pci_read_config_byte(pci, reg, &data);
412 data &= ~mask;
413 data |= (val & mask);
414 pci_write_config_byte(pci, reg, data);
415}
416
417static void azx_init_pci(struct azx *chip)
418{
37e661ee
TI		 419 int snoop_type = azx_get_snoop_type(chip);
420
cb53c626
TI		 421 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
422 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
423 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 424 * codecs.
425 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 426 */
46f2cc80 427 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 428 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 429 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 430 }
cb53c626 431
9477c58e
TI		 432 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
433 * we need to enable snoop.
434 */
37e661ee 435 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 436 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
437 azx_snoop(chip));
cb53c626 438 update_pci_byte(chip->pci,
27fe48d9
TI		 439 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
440 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 441 }
442
443 /* For NVIDIA HDA, enable snoop */
37e661ee 444 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 445 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
446 azx_snoop(chip));
cb53c626
TI		 447 update_pci_byte(chip->pci,
448 NVIDIA_HDA_TRANSREG_ADDR,
449 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 450 update_pci_byte(chip->pci,
451 NVIDIA_HDA_ISTRM_COH,
452 0x01, NVIDIA_HDA_ENABLE_COHBIT);
453 update_pci_byte(chip->pci,
454 NVIDIA_HDA_OSTRM_COH,
455 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 456 }
457
458 /* Enable SCH/PCH snoop if needed */
37e661ee 459 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 460 unsigned short snoop;
90a5ad52 461 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 462 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
463 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
464 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
465 if (!azx_snoop(chip))
466 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
467 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 468 pci_read_config_word(chip->pci,
469 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 470 }
4e76a883
TI		 471 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
472 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
473 "Disabled" : "Enabled");
da3fca21 474 }
1da177e4
LT		 475}
476
7c23b7c1
LH		 477/*
478 * In BXT-P A0, HD-Audio DMA requests is later than expected,
479 * and makes an audio stream sensitive to system latencies when
480 * 24/32 bits are playing.
481 * Adjusting threshold of DMA fifo to force the DMA request
482 * sooner to improve latency tolerance at the expense of power.
483 */
484static void bxt_reduce_dma_latency(struct azx *chip)
485{
486 u32 val;
487
70eafad8 488 val = azx_readl(chip, VS_EM4L);
7c23b7c1 489 val &= (0x3 << 20);
70eafad8 490 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 491}
492
1f9d3d98
LY		 493/*
494 * ML_LCAP bits:
495 * bit 0: 6 MHz Supported
496 * bit 1: 12 MHz Supported
497 * bit 2: 24 MHz Supported
498 * bit 3: 48 MHz Supported
499 * bit 4: 96 MHz Supported
500 * bit 5: 192 MHz Supported
501 */
502static int intel_get_lctl_scf(struct azx *chip)
503{
504 struct hdac_bus *bus = azx_bus(chip);
505 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
506 u32 val, t;
507 int i;
508
509 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
510
511 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
512 t = preferred_bits[i];
513 if (val & (1 << t))
514 return t;
515 }
516
517 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
518 return 0;
519}
520
521static int intel_ml_lctl_set_power(struct azx *chip, int state)
522{
523 struct hdac_bus *bus = azx_bus(chip);
524 u32 val;
525 int timeout;
526
527 /*
528 * the codecs are sharing the first link setting by default
529 * If other links are enabled for stream, they need similar fix
530 */
531 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
532 val &= ~AZX_MLCTL_SPA;
533 val |= state << AZX_MLCTL_SPA_SHIFT;
534 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
535 /* wait for CPA */
536 timeout = 50;
537 while (timeout) {
538 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
539 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
540 return 0;
541 timeout--;
542 udelay(10);
543 }
544
545 return -1;
546}
547
548static void intel_init_lctl(struct azx *chip)
549{
550 struct hdac_bus *bus = azx_bus(chip);
551 u32 val;
552 int ret;
553
554 /* 0. check lctl register value is correct or not */
555 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
556 /* if SCF is already set, let's use it */
557 if ((val & ML_LCTL_SCF_MASK) != 0)
558 return;
559
560 /*
561 * Before operating on SPA, CPA must match SPA.
562 * Any deviation may result in undefined behavior.
563 */
564 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
565 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
566 return;
567
568 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
569 ret = intel_ml_lctl_set_power(chip, 0);
570 udelay(100);
571 if (ret)
572 goto set_spa;
573
574 /* 2. update SCF to select a properly audio clock*/
575 val &= ~ML_LCTL_SCF_MASK;
576 val |= intel_get_lctl_scf(chip);
577 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
578
579set_spa:
580 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
581 intel_ml_lctl_set_power(chip, 1);
582 udelay(100);
583}
584
0a673521
LH		 585static void hda_intel_init_chip(struct azx *chip, bool full_reset)
586{
98d8fc6c 587 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 588 struct pci_dev *pci = chip->pci;
6639484d 589 u32 val;
0a673521 590
e454ff8e 591 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 592 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 593 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
594 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
595 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
596 }
0a673521 597 azx_init_chip(chip, full_reset);
a4b4793f 598 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 599 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
600 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
601 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
602 }
e454ff8e
TI		 603
604 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 605
606 /* reduce dma latency to avoid noise */
7e31a015 607 if (IS_BXT(pci))
7c23b7c1 608 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 609
610 if (bus->mlcap != NULL)
611 intel_init_lctl(chip);
0a673521
LH		 612}
613
b6050ef6
TI		 614/* calculate runtime delay from LPIB */
615static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
616 unsigned int pos)
617{
7833c3f8 618 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 619 int stream = substream->stream;
620 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
621 int delay;
622
623 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
624 delay = pos - lpib_pos;
625 else
626 delay = lpib_pos - pos;
627 if (delay < 0) {
7833c3f8 628 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 629 delay = 0;
630 else
7833c3f8 631 delay += azx_dev->core.bufsize;
b6050ef6
TI		 632 }
633
7833c3f8 634 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 635 dev_info(chip->card->dev,
636 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 637 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 638 delay = 0;
639 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
640 chip->get_delay[stream] = NULL;
641 }
642
643 return bytes_to_frames(substream->runtime, delay);
644}
645
9ad593f6
TI		 646static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
647
7ca954a8
DR		 648/* called from IRQ */
649static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
650{
9a34af4a 651 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 652 int ok;
653
654 ok = azx_position_ok(chip, azx_dev);
655 if (ok == 1) {
656 azx_dev->irq_pending = 0;
657 return ok;
2f35c630 658 } else if (ok == 0) {
7ca954a8
DR		 659 /* bogus IRQ, process it later */
660 azx_dev->irq_pending = 1;
2f35c630 661 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 662 }
663 return 0;
664}
665
029d92c2
TI		 666#define display_power(chip, enable) \
667 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
17eccb27 668
9ad593f6
TI		 669/*
670 * Check whether the current DMA position is acceptable for updating
671 * periods. Returns non-zero if it's OK.
672 *
673 * Many HD-audio controllers appear pretty inaccurate about
674 * the update-IRQ timing. The IRQ is issued before actually the
675 * data is processed. So, we need to process it afterwords in a
676 * workqueue.
677 */
678static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
679{
7833c3f8 680 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 681 int stream = substream->stream;
e5463720 682 u32 wallclk;
9ad593f6
TI		 683 unsigned int pos;
684
7833c3f8
TI		 685 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
686 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 687 return -1; /* bogus (too early) interrupt */
fa00e046 688
b6050ef6
TI		 689 if (chip->get_position[stream])
690 pos = chip->get_position[stream](chip, azx_dev);
691 else { /* use the position buffer as default */
692 pos = azx_get_pos_posbuf(chip, azx_dev);
693 if (!pos || pos == (u32)-1) {
694 dev_info(chip->card->dev,
695 "Invalid position buffer, using LPIB read method instead.\n");
696 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 697 if (chip->get_position[0] == azx_get_pos_lpib &&
698 chip->get_position[1] == azx_get_pos_lpib)
699 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 700 pos = azx_get_pos_lpib(chip, azx_dev);
701 chip->get_delay[stream] = NULL;
702 } else {
703 chip->get_position[stream] = azx_get_pos_posbuf;
704 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
705 chip->get_delay[stream] = azx_get_delay_from_lpib;
706 }
707 }
708
7833c3f8 709 if (pos >= azx_dev->core.bufsize)
b6050ef6 710 pos = 0;
9ad593f6 711
7833c3f8 712 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 713 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 714 return -1; /* this shouldn't happen! */
7833c3f8
TI		 715 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
716 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 717 /* NG - it's below the first next period boundary */
4f0189be 718 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 719 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 720 return 1; /* OK, it's fine */
721}
722
723/*
724 * The work for pending PCM period updates.
725 */
726static void azx_irq_pending_work(struct work_struct *work)
727{
9a34af4a
TI		 728 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
729 struct azx *chip = &hda->chip;
7833c3f8
TI		 730 struct hdac_bus *bus = azx_bus(chip);
731 struct hdac_stream *s;
732 int pending, ok;
9ad593f6 733
9a34af4a 734 if (!hda->irq_pending_warned) {
4e76a883
TI		 735 dev_info(chip->card->dev,
736 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
737 chip->card->number);
9a34af4a 738 hda->irq_pending_warned = 1;
a6a950a8
TI		 739 }
740
9ad593f6
TI		 741 for (;;) {
742 pending = 0;
a41d1224 743 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 744 list_for_each_entry(s, &bus->stream_list, list) {
745 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 746 if (!azx_dev->irq_pending ||
7833c3f8
TI		 747 !s->substream ||
748 !s->running)
9ad593f6 749 continue;
e5463720
JK		 750 ok = azx_position_ok(chip, azx_dev);
751 if (ok > 0) {
9ad593f6 752 azx_dev->irq_pending = 0;
a41d1224 753 spin_unlock(&bus->reg_lock);
7833c3f8 754 snd_pcm_period_elapsed(s->substream);
a41d1224 755 spin_lock(&bus->reg_lock);
e5463720
JK		 756 } else if (ok < 0) {
757 pending = 0; /* too early */
9ad593f6
TI		 758 } else
759 pending++;
760 }
a41d1224 761 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 762 if (!pending)
763 return;
08af495f 764 msleep(1);
9ad593f6
TI		 765 }
766}
767
768/* clear irq_pending flags and assure no on-going workq */
769static void azx_clear_irq_pending(struct azx *chip)
770{
7833c3f8
TI		 771 struct hdac_bus *bus = azx_bus(chip);
772 struct hdac_stream *s;
9ad593f6 773
a41d1224 774 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 775 list_for_each_entry(s, &bus->stream_list, list) {
776 struct azx_dev *azx_dev = stream_to_azx_dev(s);
777 azx_dev->irq_pending = 0;
778 }
a41d1224 779 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 780}
781
68e7fffc
TI		 782static int azx_acquire_irq(struct azx *chip, int do_disconnect)
783{
a41d1224
TI		 784 struct hdac_bus *bus = azx_bus(chip);
785
437a5a46
TI		 786 if (request_irq(chip->pci->irq, azx_interrupt,
787 chip->msi ? 0 : IRQF_SHARED,
de65360b 788 chip->card->irq_descr, chip)) {
4e76a883
TI		 789 dev_err(chip->card->dev,
790 "unable to grab IRQ %d, disabling device\n",
791 chip->pci->irq);
68e7fffc
TI		 792 if (do_disconnect)
793 snd_card_disconnect(chip->card);
794 return -1;
795 }
a41d1224 796 bus->irq = chip->pci->irq;
69e13418 797 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 798 return 0;
799}
800
b6050ef6
TI		 801/* get the current DMA position with correction on VIA chips */
802static unsigned int azx_via_get_position(struct azx *chip,
803 struct azx_dev *azx_dev)
804{
805 unsigned int link_pos, mini_pos, bound_pos;
806 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
807 unsigned int fifo_size;
808
1604eeee 809 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 810 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 811 /* Playback, no problem using link position */
812 return link_pos;
813 }
814
815 /* Capture */
816 /* For new chipset,
817 * use mod to get the DMA position just like old chipset
818 */
7833c3f8
TI		 819 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
820 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 821
822 /* azx_dev->fifo_size can't get FIFO size of in stream.
823 * Get from base address + offset.
824 */
a41d1224
TI		 825 fifo_size = readw(azx_bus(chip)->remap_addr +
826 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 827
828 if (azx_dev->insufficient) {
829 /* Link position never gather than FIFO size */
830 if (link_pos <= fifo_size)
831 return 0;
832
833 azx_dev->insufficient = 0;
834 }
835
836 if (link_pos <= fifo_size)
7833c3f8 837 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 838 else
839 mini_pos = link_pos - fifo_size;
840
841 /* Find nearest previous boudary */
7833c3f8
TI		 842 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
843 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 844 if (mod_link_pos >= fifo_size)
845 bound_pos = link_pos - mod_link_pos;
846 else if (mod_dma_pos >= mod_mini_pos)
847 bound_pos = mini_pos - mod_mini_pos;
848 else {
7833c3f8
TI		 849 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
850 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 851 bound_pos = 0;
852 }
853
854 /* Calculate real DMA position we want */
855 return bound_pos + mod_dma_pos;
856}
857
f87e7f25
TI		 858static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
859 struct azx_dev *azx_dev)
860{
861 return _snd_hdac_chip_readl(azx_bus(chip),
862 AZX_REG_VS_SDXDPIB_XBASE +
863 (AZX_REG_VS_SDXDPIB_XINTERVAL *
864 azx_dev->core.index));
865}
866
867/* get the current DMA position with correction on SKL+ chips */
868static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
869{
870 /* DPIB register gives a more accurate position for playback */
871 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
872 return azx_skl_get_dpib_pos(chip, azx_dev);
873
874 /* For capture, we need to read posbuf, but it requires a delay
875 * for the possible boundary overlap; the read of DPIB fetches the
876 * actual posbuf
877 */
878 udelay(20);
879 azx_skl_get_dpib_pos(chip, azx_dev);
880 return azx_get_pos_posbuf(chip, azx_dev);
881}
882
83012a7c 883#ifdef CONFIG_PM
65fcd41d
TI		 884static DEFINE_MUTEX(card_list_lock);
885static LIST_HEAD(card_list);
886
887static void azx_add_card_list(struct azx *chip)
888{
9a34af4a 889 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 890 mutex_lock(&card_list_lock);
9a34af4a 891 list_add(&hda->list, &card_list);
65fcd41d
TI		 892 mutex_unlock(&card_list_lock);
893}
894
895static void azx_del_card_list(struct azx *chip)
896{
9a34af4a 897 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 898 mutex_lock(&card_list_lock);
9a34af4a 899 list_del_init(&hda->list);
65fcd41d
TI		 900 mutex_unlock(&card_list_lock);
901}
902
903/* trigger power-save check at writing parameter */
904static int param_set_xint(const char *val, const struct kernel_param *kp)
905{
9a34af4a 906 struct hda_intel *hda;
65fcd41d 907 struct azx *chip;
65fcd41d
TI		 908 int prev = power_save;
909 int ret = param_set_int(val, kp);
910
911 if (ret || prev == power_save)
912 return ret;
913
914 mutex_lock(&card_list_lock);
9a34af4a
TI		 915 list_for_each_entry(hda, &card_list, list) {
916 chip = &hda->chip;
a41d1224 917 if (!hda->probe_continued || chip->disabled)
65fcd41d 918 continue;
a41d1224 919 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 920 }
921 mutex_unlock(&card_list_lock);
922 return 0;
923}
5c0b9bec 924
5c0b9bec
TI		 925/*
926 * power management
927 */
3baffc4a 928static bool azx_is_pm_ready(struct snd_card *card)
1da177e4 929{
2d9772ef
TI		 930 struct azx *chip;
931 struct hda_intel *hda;
1da177e4 932
2d9772ef 933 if (!card)
3baffc4a 934 return false;
2d9772ef
TI		 935 chip = card->private_data;
936 hda = container_of(chip, struct hda_intel, chip);
342e8449 937 if (chip->disabled || hda->init_failed || !chip->running)
3baffc4a
TI		 938 return false;
939 return true;
940}
941
942static void __azx_runtime_suspend(struct azx *chip)
943{
3baffc4a
TI		 944 azx_stop_chip(chip);
945 azx_enter_link_reset(chip);
946 azx_clear_irq_pending(chip);
e454ff8e 947 display_power(chip, false);
3baffc4a
TI		 948}
949
950static void __azx_runtime_resume(struct azx *chip)
951{
952 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
953 struct hdac_bus *bus = azx_bus(chip);
954 struct hda_codec *codec;
955 int status;
956
e454ff8e
TI		 957 display_power(chip, true);
958 if (hda->need_i915_power)
959 snd_hdac_i915_set_bclk(bus);
3baffc4a
TI		 960
961 /* Read STATESTS before controller reset */
962 status = azx_readw(chip, STATESTS);
963
964 azx_init_pci(chip);
965 hda_intel_init_chip(chip, true);
966
967 if (status) {
968 list_for_each_codec(codec, &chip->bus)
969 if (status & (1 << codec->addr))
970 schedule_delayed_work(&codec->jackpoll_work,
971 codec->jackpoll_interval);
972 }
973
974 /* power down again for link-controlled chips */
e454ff8e 975 if (!hda->need_i915_power)
029d92c2 976 display_power(chip, false);
3baffc4a
TI		 977}
978
979#ifdef CONFIG_PM_SLEEP
980static int azx_suspend(struct device *dev)
981{
982 struct snd_card *card = dev_get_drvdata(dev);
983 struct azx *chip;
984 struct hdac_bus *bus;
985
986 if (!azx_is_pm_ready(card))
c5c21523
TI		 987 return 0;
988
3baffc4a 989 chip = card->private_data;
a41d1224 990 bus = azx_bus(chip);
421a1252 991 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3baffc4a 992 __azx_runtime_suspend(chip);
a41d1224
TI		 993 if (bus->irq >= 0) {
994 free_irq(bus->irq, chip);
995 bus->irq = -1;
30b35399 996 }
a07187c9 997
68e7fffc 998 if (chip->msi)
43001c95 999 pci_disable_msi(chip->pci);
785d8c4b
LY		 1000
1001 trace_azx_suspend(chip);
1da177e4
LT		 1002 return 0;
1003}
1004
68cb2b55 1005static int azx_resume(struct device *dev)
1da177e4 1006{
68cb2b55 1007 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1008 struct azx *chip;
2d9772ef 1009
3baffc4a 1010 if (!azx_is_pm_ready(card))
2d9772ef 1011 return 0;
1da177e4 1012
2d9772ef 1013 chip = card->private_data;
68e7fffc 1014 if (chip->msi)
3baffc4a 1015 if (pci_enable_msi(chip->pci) < 0)
68e7fffc
TI		 1016 chip->msi = 0;
1017 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1018 return -EIO;
3baffc4a 1019 __azx_runtime_resume(chip);
421a1252 1020 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 1021
1022 trace_azx_resume(chip);
1da177e4
LT		 1023 return 0;
1024}
b8dfc462 1025
3e6db33a
XZ		 1026/* put codec down to D3 at hibernation for Intel SKL+;
1027 * otherwise BIOS may still access the codec and screw up the driver
1028 */
3e6db33a
XZ		 1029static int azx_freeze_noirq(struct device *dev)
1030{
a4b4793f
TI		 1031 struct snd_card *card = dev_get_drvdata(dev);
1032 struct azx *chip = card->private_data;
3e6db33a
XZ		 1033 struct pci_dev *pci = to_pci_dev(dev);
1034
a4b4793f 1035 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1036 pci_set_power_state(pci, PCI_D3hot);
1037
1038 return 0;
1039}
1040
1041static int azx_thaw_noirq(struct device *dev)
1042{
a4b4793f
TI		 1043 struct snd_card *card = dev_get_drvdata(dev);
1044 struct azx *chip = card->private_data;
3e6db33a
XZ		 1045 struct pci_dev *pci = to_pci_dev(dev);
1046
a4b4793f 1047 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1048 pci_set_power_state(pci, PCI_D0);
1049
1050 return 0;
1051}
1052#endif /* CONFIG_PM_SLEEP */
1053
b8dfc462
ML		 1054static int azx_runtime_suspend(struct device *dev)
1055{
1056 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1057 struct azx *chip;
b8dfc462 1058
3baffc4a 1059 if (!azx_is_pm_ready(card))
2d9772ef 1060 return 0;
2d9772ef 1061 chip = card->private_data;
364aa716 1062 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1063 return 0;
1064
7d4f606c
WX		 1065 /* enable controller wake up event */
1066 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1067 STATESTS_INT_MASK);
1068
3baffc4a 1069 __azx_runtime_suspend(chip);
785d8c4b 1070 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1071 return 0;
1072}
1073
1074static int azx_runtime_resume(struct device *dev)
1075{
1076 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1077 struct azx *chip;
b8dfc462 1078
3baffc4a 1079 if (!azx_is_pm_ready(card))
2d9772ef 1080 return 0;
2d9772ef 1081 chip = card->private_data;
364aa716 1082 if (!azx_has_pm_runtime(chip))
246efa4a 1083 return 0;
3baffc4a 1084 __azx_runtime_resume(chip);
7d4f606c
WX		 1085
1086 /* disable controller Wake Up event*/
1087 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1088 ~STATESTS_INT_MASK);
1089
785d8c4b 1090 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1091 return 0;
1092}
6eb827d2
TI		 1093
1094static int azx_runtime_idle(struct device *dev)
1095{
1096 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1097 struct azx *chip;
1098 struct hda_intel *hda;
1099
1100 if (!card)
1101 return 0;
6eb827d2 1102
2d9772ef
TI		 1103 chip = card->private_data;
1104 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1105 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1106 return 0;
1107
55ed9cd1 1108 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1109 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1110 return -EBUSY;
1111
37a3a98e
TI		 1112 /* ELD notification gets broken when HD-audio bus is off */
1113 if (needs_eld_notify_link(hda))
1114 return -EBUSY;
1115
6eb827d2
TI		 1116 return 0;
1117}
1118
b8dfc462
ML		 1119static const struct dev_pm_ops azx_pm = {
1120 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1121#ifdef CONFIG_PM_SLEEP
1122 .freeze_noirq = azx_freeze_noirq,
1123 .thaw_noirq = azx_thaw_noirq,
1124#endif
6eb827d2 1125 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1126};
1127
68cb2b55
TI		 1128#define AZX_PM_OPS &azx_pm
1129#else
3baffc4a
TI		 1130#define azx_add_card_list(chip) /* NOP */
1131#define azx_del_card_list(chip) /* NOP */
68cb2b55 1132#define AZX_PM_OPS NULL
b8dfc462 1133#endif /* CONFIG_PM */
1da177e4
LT		 1134
1135
48c8b0eb 1136static int azx_probe_continue(struct azx *chip);
a82d51ed 1137
8393ec4a 1138#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1139static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1140
a82d51ed
TI		 1141static void azx_vs_set_state(struct pci_dev *pci,
1142 enum vga_switcheroo_state state)
1143{
1144 struct snd_card *card = pci_get_drvdata(pci);
1145 struct azx *chip = card->private_data;
9a34af4a 1146 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
07f4f97d 1147 struct hda_codec *codec;
a82d51ed
TI		 1148 bool disabled;
1149
9a34af4a
TI		 1150 wait_for_completion(&hda->probe_wait);
1151 if (hda->init_failed)
a82d51ed
TI		 1152 return;
1153
1154 disabled = (state == VGA_SWITCHEROO_OFF);
1155 if (chip->disabled == disabled)
1156 return;
1157
a41d1224 1158 if (!hda->probe_continued) {
a82d51ed
TI		 1159 chip->disabled = disabled;
1160 if (!disabled) {
4e76a883
TI		 1161 dev_info(chip->card->dev,
1162 "Start delayed initialization\n");
5c90680e 1163 if (azx_probe_continue(chip) < 0) {
4e76a883 1164 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1165 hda->init_failed = true;
a82d51ed
TI		 1166 }
1167 }
1168 } else {
2b760d88 1169 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1170 disabled ? "Disabling" : "Enabling");
a82d51ed 1171 if (disabled) {
07f4f97d
LW		 1172 list_for_each_codec(codec, &chip->bus) {
1173 pm_runtime_suspend(hda_codec_dev(codec));
1174 pm_runtime_disable(hda_codec_dev(codec));
1175 }
1176 pm_runtime_suspend(card->dev);
1177 pm_runtime_disable(card->dev);
2b760d88 1178 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1179 * however we have no ACPI handle, so pci/acpi can't put us there,
1180 * put ourselves there */
1181 pci->current_state = PCI_D3cold;
a82d51ed 1182 chip->disabled = true;
a41d1224 1183 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1184 dev_warn(chip->card->dev,
1185 "Cannot lock devices!\n");
a82d51ed 1186 } else {
a41d1224 1187 snd_hda_unlock_devices(&chip->bus);
a82d51ed 1188 chip->disabled = false;
07f4f97d
LW		 1189 pm_runtime_enable(card->dev);
1190 list_for_each_codec(codec, &chip->bus) {
1191 pm_runtime_enable(hda_codec_dev(codec));
1192 pm_runtime_resume(hda_codec_dev(codec));
1193 }
a82d51ed
TI		 1194 }
1195 }
1196}
1197
1198static bool azx_vs_can_switch(struct pci_dev *pci)
1199{
1200 struct snd_card *card = pci_get_drvdata(pci);
1201 struct azx *chip = card->private_data;
9a34af4a 1202 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1203
9a34af4a
TI		 1204 wait_for_completion(&hda->probe_wait);
1205 if (hda->init_failed)
a82d51ed 1206 return false;
a41d1224 1207 if (chip->disabled || !hda->probe_continued)
a82d51ed 1208 return true;
a41d1224 1209 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1210 return false;
a41d1224 1211 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1212 return true;
1213}
1214
37a3a98e
TI		 1215/*
1216 * The discrete GPU cannot power down unless the HDA controller runtime
1217 * suspends, so activate runtime PM on codecs even if power_save == 0.
1218 */
1219static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1220{
1221 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1222 struct hda_codec *codec;
1223
1224 if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1225 list_for_each_codec(codec, &chip->bus)
1226 codec->auto_runtime_pm = 1;
1227 /* reset the power save setup */
1228 if (chip->running)
1229 set_default_power_save(chip);
1230 }
1231}
1232
1233static void azx_vs_gpu_bound(struct pci_dev *pci,
1234 enum vga_switcheroo_client_id client_id)
1235{
1236 struct snd_card *card = pci_get_drvdata(pci);
1237 struct azx *chip = card->private_data;
1238 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1239
1240 if (client_id == VGA_SWITCHEROO_DIS)
1241 hda->need_eld_notify_link = 0;
1242 setup_vga_switcheroo_runtime_pm(chip);
1243}
1244
e23e7a14 1245static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1246{
9a34af4a 1247 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1248 struct pci_dev *p = get_bound_vga(chip->pci);
1249 if (p) {
4e76a883 1250 dev_info(chip->card->dev,
2b760d88 1251 "Handle vga_switcheroo audio client\n");
9a34af4a 1252 hda->use_vga_switcheroo = 1;
37a3a98e 1253 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
07f4f97d 1254 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
a82d51ed
TI		 1255 pci_dev_put(p);
1256 }
1257}
1258
1259static const struct vga_switcheroo_client_ops azx_vs_ops = {
1260 .set_gpu_state = azx_vs_set_state,
1261 .can_switch = azx_vs_can_switch,
37a3a98e 1262 .gpu_bound = azx_vs_gpu_bound,
a82d51ed
TI		 1263};
1264
e23e7a14 1265static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1266{
9a34af4a 1267 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4aaf448f 1268 struct pci_dev *p;
128960a9
TI		 1269 int err;
1270
9a34af4a 1271 if (!hda->use_vga_switcheroo)
a82d51ed 1272 return 0;
4aaf448f
JQ		 1273
1274 p = get_bound_vga(chip->pci);
1275 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1276 pci_dev_put(p);
1277
128960a9
TI		 1278 if (err < 0)
1279 return err;
9a34af4a 1280 hda->vga_switcheroo_registered = 1;
246efa4a 1281
128960a9 1282 return 0;
a82d51ed
TI		 1283}
1284#else
1285#define init_vga_switcheroo(chip) /* NOP */
1286#define register_vga_switcheroo(chip) 0
8393ec4a 1287#define check_hdmi_disabled(pci) false
37a3a98e 1288#define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
a82d51ed
TI		 1289#endif /* SUPPORT_VGA_SWITCHER */
1290
1da177e4
LT		 1291/*
1292 * destructor
1293 */
a98f90fd 1294static int azx_free(struct azx *chip)
1da177e4 1295{
c67e2228 1296 struct pci_dev *pci = chip->pci;
a07187c9 1297 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1298 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1299
364aa716 1300 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228 1301 pm_runtime_get_noresume(&pci->dev);
37a3a98e 1302 chip->running = 0;
c67e2228 1303
65fcd41d
TI		 1304 azx_del_card_list(chip);
1305
9a34af4a
TI		 1306 hda->init_failed = 1; /* to be sure */
1307 complete_all(&hda->probe_wait);
f4c482a4 1308
9a34af4a 1309 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1310 if (chip->disabled && hda->probe_continued)
1311 snd_hda_unlock_devices(&chip->bus);
07f4f97d 1312 if (hda->vga_switcheroo_registered)
128960a9 1313 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1314 }
1315
a41d1224 1316 if (bus->chip_init) {
9ad593f6 1317 azx_clear_irq_pending(chip);
7833c3f8 1318 azx_stop_all_streams(chip);
cb53c626 1319 azx_stop_chip(chip);
1da177e4
LT		 1320 }
1321
a41d1224
TI		 1322 if (bus->irq >= 0)
1323 free_irq(bus->irq, (void*)chip);
68e7fffc 1324 if (chip->msi)
30b35399 1325 pci_disable_msi(chip->pci);
a41d1224 1326 iounmap(bus->remap_addr);
1da177e4 1327
67908994 1328 azx_free_stream_pages(chip);
a41d1224
TI		 1329 azx_free_streams(chip);
1330 snd_hdac_bus_exit(bus);
1331
a82d51ed
TI		 1332 if (chip->region_requested)
1333 pci_release_regions(chip->pci);
a41d1224 1334
1da177e4 1335 pci_disable_device(chip->pci);
4918cdab 1336#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1337 release_firmware(chip->fw);
4918cdab 1338#endif
e454ff8e 1339 display_power(chip, false);
98d8fc6c 1340
fc18282c 1341 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
fcc88d91 1342 snd_hdac_i915_exit(bus);
a07187c9 1343 kfree(hda);
1da177e4
LT		 1344
1345 return 0;
1346}
1347
a41d1224
TI		 1348static int azx_dev_disconnect(struct snd_device *device)
1349{
1350 struct azx *chip = device->device_data;
1351
1352 chip->bus.shutdown = 1;
1353 return 0;
1354}
1355
a98f90fd 1356static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1357{
1358 return azx_free(device->device_data);
1359}
1360
8393ec4a 1361#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1362/*
2b760d88 1363 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1364 */
e23e7a14 1365static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1366{
1367 struct pci_dev *p;
1368
1369 /* check only discrete GPU */
1370 switch (pci->vendor) {
1371 case PCI_VENDOR_ID_ATI:
1372 case PCI_VENDOR_ID_AMD:
1373 case PCI_VENDOR_ID_NVIDIA:
1374 if (pci->devfn == 1) {
1375 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1376 pci->bus->number, 0);
1377 if (p) {
b6d7b362 1378 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
9121947d
TI		 1379 return p;
1380 pci_dev_put(p);
1381 }
1382 }
1383 break;
1384 }
1385 return NULL;
1386}
1387
e23e7a14 1388static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1389{
1390 bool vga_inactive = false;
1391 struct pci_dev *p = get_bound_vga(pci);
1392
1393 if (p) {
12b78a7f 1394 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1395 vga_inactive = true;
1396 pci_dev_put(p);
1397 }
1398 return vga_inactive;
1399}
8393ec4a 1400#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1401
3372a153
TI		 1402/*
1403 * white/black-listing for position_fix
1404 */
e23e7a14 1405static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1406 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1407 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1408 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1409 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1410 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1411 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1412 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1413 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1414 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1415 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1416 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1417 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1418 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1419 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1420 {}
1421};
1422
e23e7a14 1423static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1424{
1425 const struct snd_pci_quirk *q;
1426
c673ba1c 1427 switch (fix) {
1dac6695 1428 case POS_FIX_AUTO:
c673ba1c
TI		 1429 case POS_FIX_LPIB:
1430 case POS_FIX_POSBUF:
4cb36310 1431 case POS_FIX_VIACOMBO:
a6f2fd55 1432 case POS_FIX_COMBO:
f87e7f25 1433 case POS_FIX_SKL:
c673ba1c
TI		 1434 return fix;
1435 }
1436
c673ba1c
TI		 1437 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1438 if (q) {
4e76a883
TI		 1439 dev_info(chip->card->dev,
1440 "position_fix set to %d for device %04x:%04x\n",
1441 q->value, q->subvendor, q->subdevice);
c673ba1c 1442 return q->value;
3372a153 1443 }
bdd9ef24
DH		 1444
1445 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1446 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1447 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1448 return POS_FIX_VIACOMBO;
9477c58e
TI		 1449 }
1450 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1451 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1452 return POS_FIX_LPIB;
bdd9ef24 1453 }
a4b4793f 1454 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1455 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1456 return POS_FIX_SKL;
1457 }
c673ba1c 1458 return POS_FIX_AUTO;
3372a153
TI		 1459}
1460
b6050ef6
TI		 1461static void assign_position_fix(struct azx *chip, int fix)
1462{
1463 static azx_get_pos_callback_t callbacks[] = {
1464 [POS_FIX_AUTO] = NULL,
1465 [POS_FIX_LPIB] = azx_get_pos_lpib,
1466 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1467 [POS_FIX_VIACOMBO] = azx_via_get_position,
1468 [POS_FIX_COMBO] = azx_get_pos_lpib,
f87e7f25 1469 [POS_FIX_SKL] = azx_get_pos_skl,
b6050ef6
TI		 1470 };
1471
1472 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1473
1474 /* combo mode uses LPIB only for playback */
1475 if (fix == POS_FIX_COMBO)
1476 chip->get_position[1] = NULL;
1477
f87e7f25 1478 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1479 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1480 chip->get_delay[0] = chip->get_delay[1] =
1481 azx_get_delay_from_lpib;
1482 }
1483
1484}
1485
669ba27a
TI		 1486/*
1487 * black-lists for probe_mask
1488 */
e23e7a14 1489static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1490 /* Thinkpad often breaks the controller communication when accessing
1491 * to the non-working (or non-existing) modem codec slot.
1492 */
1493 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1494 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1495 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1496 /* broken BIOS */
1497 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1498 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1499 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1500 /* forced codec slots */
93574844 1501 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1502 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1503 /* WinFast VP200 H (Teradici) user reported broken communication */
1504 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1505 {}
1506};
1507
f1eaaeec
TI		 1508#define AZX_FORCE_CODEC_MASK 0x100
1509
e23e7a14 1510static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1511{
1512 const struct snd_pci_quirk *q;
1513
f1eaaeec
TI		 1514 chip->codec_probe_mask = probe_mask[dev];
1515 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1516 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1517 if (q) {
4e76a883
TI		 1518 dev_info(chip->card->dev,
1519 "probe_mask set to 0x%x for device %04x:%04x\n",
1520 q->value, q->subvendor, q->subdevice);
f1eaaeec 1521 chip->codec_probe_mask = q->value;
669ba27a
TI		 1522 }
1523 }
f1eaaeec
TI		 1524
1525 /* check forced option */
1526 if (chip->codec_probe_mask != -1 &&
1527 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1528 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1529 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1530 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1531 }
669ba27a
TI		 1532}
1533
4d8e22e0 1534/*
71623855 1535 * white/black-list for enable_msi
4d8e22e0 1536 */
e23e7a14 1537static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1538 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1539 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1540 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1541 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1542 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1543 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1544 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1545 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1546 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1547 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1548 {}
1549};
1550
e23e7a14 1551static void check_msi(struct azx *chip)
4d8e22e0
TI		 1552{
1553 const struct snd_pci_quirk *q;
1554
71623855
TI		 1555 if (enable_msi >= 0) {
1556 chip->msi = !!enable_msi;
4d8e22e0 1557 return;
71623855
TI		 1558 }
1559 chip->msi = 1; /* enable MSI as default */
1560 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1561 if (q) {
4e76a883
TI		 1562 dev_info(chip->card->dev,
1563 "msi for device %04x:%04x set to %d\n",
1564 q->subvendor, q->subdevice, q->value);
4d8e22e0 1565 chip->msi = q->value;
80c43ed7
TI		 1566 return;
1567 }
1568
1569 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1570 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1571 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1572 chip->msi = 0;
4d8e22e0
TI		 1573 }
1574}
1575
a1585d76 1576/* check the snoop mode availability */
e23e7a14 1577static void azx_check_snoop_available(struct azx *chip)
a1585d76 1578{
7c732015 1579 int snoop = hda_snoop;
a1585d76 1580
7c732015
TI		 1581 if (snoop >= 0) {
1582 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1583 snoop ? "snoop" : "non-snoop");
1584 chip->snoop = snoop;
78c9be61 1585 chip->uc_buffer = !snoop;
7c732015
TI		 1586 return;
1587 }
1588
1589 snoop = true;
37e661ee
TI		 1590 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1591 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1592 /* force to non-snoop mode for a new VIA controller
1593 * when BIOS is set
1594 */
7c732015
TI		 1595 u8 val;
1596 pci_read_config_byte(chip->pci, 0x42, &val);
af52f998
DW		 1597 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1598 chip->pci->revision == 0x20))
7c732015 1599 snoop = false;
a1585d76
TI		 1600 }
1601
37e661ee
TI		 1602 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1603 snoop = false;
1604
7c732015 1605 chip->snoop = snoop;
78c9be61 1606 if (!snoop) {
7c732015 1607 dev_info(chip->card->dev, "Force to non-snoop mode\n");
78c9be61
TI		 1608 /* C-Media requires non-cached pages only for CORB/RIRB */
1609 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1610 chip->uc_buffer = true;
1611 }
a1585d76 1612}
669ba27a 1613
99a2008d
WX		 1614static void azx_probe_work(struct work_struct *work)
1615{
9a34af4a
TI		 1616 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1617 azx_probe_continue(&hda->chip);
99a2008d 1618}
99a2008d 1619
4f0189be
TI		 1620static int default_bdl_pos_adj(struct azx *chip)
1621{
2cf721db
TI		 1622 /* some exceptions: Atoms seem problematic with value 1 */
1623 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1624 switch (chip->pci->device) {
1625 case 0x0f04: /* Baytrail */
1626 case 0x2284: /* Braswell */
1627 return 32;
1628 }
1629 }
1630
4f0189be
TI		 1631 switch (chip->driver_type) {
1632 case AZX_DRIVER_ICH:
1633 case AZX_DRIVER_PCH:
1634 return 1;
1635 default:
1636 return 32;
1637 }
1638}
1639
1da177e4
LT		 1640/*
1641 * constructor
1642 */
a43ff5ba
TI		 1643static const struct hdac_io_ops pci_hda_io_ops;
1644static const struct hda_controller_ops pci_hda_ops;
1645
e23e7a14
BP		 1646static int azx_create(struct snd_card *card, struct pci_dev *pci,
1647 int dev, unsigned int driver_caps,
1648 struct azx **rchip)
1da177e4 1649{
a98f90fd 1650 static struct snd_device_ops ops = {
a41d1224 1651 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1652 .dev_free = azx_dev_free,
1653 };
a07187c9 1654 struct hda_intel *hda;
a82d51ed
TI		 1655 struct azx *chip;
1656 int err;
1da177e4
LT		 1657
1658 *rchip = NULL;
bcd72003 1659
927fc866
PM		 1660 err = pci_enable_device(pci);
1661 if (err < 0)
1da177e4
LT		 1662 return err;
1663
a07187c9
ML		 1664 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1665 if (!hda) {
1da177e4
LT		 1666 pci_disable_device(pci);
1667 return -ENOMEM;
1668 }
1669
a07187c9 1670 chip = &hda->chip;
62932df8 1671 mutex_init(&chip->open_mutex);
1da177e4
LT		 1672 chip->card = card;
1673 chip->pci = pci;
a43ff5ba 1674 chip->ops = &pci_hda_ops;
9477c58e
TI		 1675 chip->driver_caps = driver_caps;
1676 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1677 check_msi(chip);
555e219f 1678 chip->dev_index = dev;
3a182c84
TI		 1679 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1680 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
01b65bfb 1681 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1682 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1683 INIT_LIST_HEAD(&hda->list);
a82d51ed 1684 init_vga_switcheroo(chip);
9a34af4a 1685 init_completion(&hda->probe_wait);
1da177e4 1686
b6050ef6 1687 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1688
5aba4f8e 1689 check_probe_mask(chip, dev);
3372a153 1690
41438f13
TI		 1691 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1692 chip->fallback_to_single_cmd = 1;
1693 else /* explicitly set to single_cmd or not */
1694 chip->single_cmd = single_cmd;
1695
a1585d76 1696 azx_check_snoop_available(chip);
c74db86b 1697
4f0189be
TI		 1698 if (bdl_pos_adj[dev] < 0)
1699 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1700 else
1701 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1702
a8d7bde2
TI		 1703 /* Workaround for a communication error on CFL (bko#199007) */
1704 if (IS_CFL(pci))
1705 chip->polling_mode = 1;
1706
a41d1224
TI		 1707 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1708 if (err < 0) {
1709 kfree(hda);
1710 pci_disable_device(pci);
1711 return err;
1712 }
1713
7d9a1808
TI		 1714 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1715 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1716 chip->bus.needs_damn_long_delay = 1;
1717 }
1718
a82d51ed
TI		 1719 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1720 if (err < 0) {
4e76a883 1721 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1722 azx_free(chip);
1723 return err;
1724 }
1725
99a2008d 1726 /* continue probing in work context as may trigger request module */
9a34af4a 1727 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1728
a82d51ed 1729 *rchip = chip;
99a2008d 1730
a82d51ed
TI		 1731 return 0;
1732}
1733
48c8b0eb 1734static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1735{
1736 int dev = chip->dev_index;
1737 struct pci_dev *pci = chip->pci;
1738 struct snd_card *card = chip->card;
a41d1224 1739 struct hdac_bus *bus = azx_bus(chip);
67908994 1740 int err;
a82d51ed 1741 unsigned short gcap;
413cbf46 1742 unsigned int dma_bits = 64;
a82d51ed 1743
07e4ca50
TI		 1744#if BITS_PER_LONG != 64
1745 /* Fix up base address on ULI M5461 */
1746 if (chip->driver_type == AZX_DRIVER_ULI) {
1747 u16 tmp3;
1748 pci_read_config_word(pci, 0x40, &tmp3);
1749 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1750 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1751 }
1752#endif
1753
927fc866 1754 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1755 if (err < 0)
1da177e4 1756 return err;
a82d51ed 1757 chip->region_requested = 1;
1da177e4 1758
a41d1224
TI		 1759 bus->addr = pci_resource_start(pci, 0);
1760 bus->remap_addr = pci_ioremap_bar(pci, 0);
1761 if (bus->remap_addr == NULL) {
4e76a883 1762 dev_err(card->dev, "ioremap error\n");
a82d51ed 1763 return -ENXIO;
1da177e4
LT		 1764 }
1765
a4b4793f 1766 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1767 snd_hdac_bus_parse_capabilities(bus);
1768
1769 /*
1770 * Some Intel CPUs has always running timer (ART) feature and
1771 * controller may have Global time sync reporting capability, so
1772 * check both of these before declaring synchronized time reporting
1773 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1774 */
1775 chip->gts_present = false;
1776
1777#ifdef CONFIG_X86
1778 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1779 chip->gts_present = true;
1780#endif
1781
db79afa1
BH		 1782 if (chip->msi) {
1783 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1784 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1785 pci->no_64bit_msi = true;
1786 }
68e7fffc
TI		 1787 if (pci_enable_msi(pci) < 0)
1788 chip->msi = 0;
db79afa1 1789 }
7376d013 1790
a82d51ed
TI		 1791 if (azx_acquire_irq(chip, 0) < 0)
1792 return -EBUSY;
1da177e4
LT		 1793
1794 pci_set_master(pci);
a41d1224 1795 synchronize_irq(bus->irq);
1da177e4 1796
bcd72003 1797 gcap = azx_readw(chip, GCAP);
4e76a883 1798 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1799
413cbf46
TI		 1800 /* AMD devices support 40 or 48bit DMA, take the safe one */
1801 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1802 dma_bits = 40;
1803
dc4c2e6b 1804 /* disable SB600 64bit support for safety */
9477c58e 1805 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1806 struct pci_dev *p_smbus;
413cbf46 1807 dma_bits = 40;
dc4c2e6b
AB		 1808 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1809 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1810 NULL);
1811 if (p_smbus) {
1812 if (p_smbus->revision < 0x30)
fb1d8ac2 1813 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1814 pci_dev_put(p_smbus);
1815 }
1816 }
09240cf4 1817
3ab7511e
AB		 1818 /* NVidia hardware normally only supports up to 40 bits of DMA */
1819 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1820 dma_bits = 40;
1821
9477c58e
TI		 1822 /* disable 64bit DMA address on some devices */
1823 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1824 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1825 gcap &= ~AZX_GCAP_64OK;
9477c58e 1826 }
396087ea 1827
2ae66c26 1828 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1829 if (align_buffer_size >= 0)
1830 chip->align_buffer_size = !!align_buffer_size;
1831 else {
103884a3 1832 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1833 chip->align_buffer_size = 0;
7bfe059e
TI		 1834 else
1835 chip->align_buffer_size = 1;
1836 }
2ae66c26 1837
cf7aaca8 1838 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1839 if (!(gcap & AZX_GCAP_64OK))
1840 dma_bits = 32;
412b979c
QL		 1841 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1842 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1843 } else {
412b979c
QL		 1844 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1845 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1846 }
cf7aaca8 1847
8b6ed8e7
TI		 1848 /* read number of streams from GCAP register instead of using
1849 * hardcoded value
1850 */
1851 chip->capture_streams = (gcap >> 8) & 0x0f;
1852 chip->playback_streams = (gcap >> 12) & 0x0f;
1853 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1854 /* gcap didn't give any info, switching to old method */
1855
1856 switch (chip->driver_type) {
1857 case AZX_DRIVER_ULI:
1858 chip->playback_streams = ULI_NUM_PLAYBACK;
1859 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1860 break;
1861 case AZX_DRIVER_ATIHDMI:
1815b34a 1862 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1863 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1864 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1865 break;
c4da29ca 1866 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1867 default:
1868 chip->playback_streams = ICH6_NUM_PLAYBACK;
1869 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1870 break;
1871 }
07e4ca50 1872 }
8b6ed8e7
TI		 1873 chip->capture_index_offset = 0;
1874 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1875 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1876
df56c3db
JK		 1877 /* sanity check for the SDxCTL.STRM field overflow */
1878 if (chip->num_streams > 15 &&
1879 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1880 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1881 "forcing separate stream tags", chip->num_streams);
1882 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1883 }
1884
a41d1224
TI		 1885 /* initialize streams */
1886 err = azx_init_streams(chip);
81740861 1887 if (err < 0)
a82d51ed 1888 return err;
1da177e4 1889
a41d1224
TI		 1890 err = azx_alloc_stream_pages(chip);
1891 if (err < 0)
1892 return err;
1da177e4
LT		 1893
1894 /* initialize chip */
cb53c626 1895 azx_init_pci(chip);
e4d9e513 1896
e454ff8e 1897 snd_hdac_i915_set_bclk(bus);
e4d9e513 1898
0a673521 1899 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1900
1901 /* codec detection */
a41d1224 1902 if (!azx_bus(chip)->codec_mask) {
4e76a883 1903 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1904 return -ENODEV;
1da177e4
LT		 1905 }
1906
07e4ca50 1907 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1908 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1909 sizeof(card->shortname));
1910 snprintf(card->longname, sizeof(card->longname),
1911 "%s at 0x%lx irq %i",
a41d1224 1912 card->shortname, bus->addr, bus->irq);
07e4ca50 1913
1da177e4 1914 return 0;
1da177e4
LT		 1915}
1916
97c6a3d1 1917#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1918/* callback from request_firmware_nowait() */
1919static void azx_firmware_cb(const struct firmware *fw, void *context)
1920{
1921 struct snd_card *card = context;
1922 struct azx *chip = card->private_data;
1923 struct pci_dev *pci = chip->pci;
1924
1925 if (!fw) {
4e76a883 1926 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1927 goto error;
1928 }
1929
1930 chip->fw = fw;
1931 if (!chip->disabled) {
1932 /* continue probing */
1933 if (azx_probe_continue(chip))
1934 goto error;
1935 }
1936 return; /* OK */
1937
1938 error:
1939 snd_card_free(card);
1940 pci_set_drvdata(pci, NULL);
1941}
97c6a3d1 1942#endif
5cb543db 1943
40830813
DR		 1944/*
1945 * HDA controller ops.
1946 */
1947
1948/* PCI register access. */
db291e36 1949static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1950{
1951 writel(value, addr);
1952}
1953
db291e36 1954static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1955{
1956 return readl(addr);
1957}
1958
db291e36 1959static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1960{
1961 writew(value, addr);
1962}
1963
db291e36 1964static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1965{
1966 return readw(addr);
1967}
1968
db291e36 1969static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 1970{
1971 writeb(value, addr);
1972}
1973
db291e36 1974static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 1975{
1976 return readb(addr);
1977}
1978
f46ea609
DR		 1979static int disable_msi_reset_irq(struct azx *chip)
1980{
a41d1224 1981 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 1982 int err;
1983
a41d1224
TI		 1984 free_irq(bus->irq, chip);
1985 bus->irq = -1;
f46ea609
DR		 1986 pci_disable_msi(chip->pci);
1987 chip->msi = 0;
1988 err = azx_acquire_irq(chip, 1);
1989 if (err < 0)
1990 return err;
1991
1992 return 0;
1993}
1994
b419b35b 1995/* DMA page allocation helpers. */
a43ff5ba 1996static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 1997 int type,
1998 size_t size,
1999 struct snd_dma_buffer *buf)
2000{
a41d1224 2001 struct azx *chip = bus_to_azx(bus);
b419b35b 2002
fc478143
TI		 2003 if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV)
2004 type = SNDRV_DMA_TYPE_DEV_UC;
2005 return snd_dma_alloc_pages(type, bus->dev, size, buf);
b419b35b
DR		 2006}
2007
a43ff5ba 2008static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 2009{
b419b35b
DR		 2010 snd_dma_free_pages(buf);
2011}
2012
8769b278
DR		 2013static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2014 struct vm_area_struct *area)
2015{
2016#ifdef CONFIG_X86
2017 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2018 struct azx *chip = apcm->chip;
78c9be61 2019 if (chip->uc_buffer)
8769b278
DR		 2020 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2021#endif
2022}
2023
a43ff5ba 2024static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 2025 .reg_writel = pci_azx_writel,
2026 .reg_readl = pci_azx_readl,
2027 .reg_writew = pci_azx_writew,
2028 .reg_readw = pci_azx_readw,
2029 .reg_writeb = pci_azx_writeb,
2030 .reg_readb = pci_azx_readb,
b419b35b
DR		 2031 .dma_alloc_pages = dma_alloc_pages,
2032 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 2033};
2034
2035static const struct hda_controller_ops pci_hda_ops = {
2036 .disable_msi_reset_irq = disable_msi_reset_irq,
8769b278 2037 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 2038 .position_check = azx_position_check,
40830813
DR		 2039};
2040
e23e7a14
BP		 2041static int azx_probe(struct pci_dev *pci,
2042 const struct pci_device_id *pci_id)
1da177e4 2043{
5aba4f8e 2044 static int dev;
a98f90fd 2045 struct snd_card *card;
9a34af4a 2046 struct hda_intel *hda;
a98f90fd 2047 struct azx *chip;
aad730d0 2048 bool schedule_probe;
927fc866 2049 int err;
1da177e4 2050
5aba4f8e
TI		 2051 if (dev >= SNDRV_CARDS)
2052 return -ENODEV;
2053 if (!enable[dev]) {
2054 dev++;
2055 return -ENOENT;
2056 }
2057
60c5772b
TI		 2058 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2059 0, &card);
e58de7ba 2060 if (err < 0) {
4e76a883 2061 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2062 return err;
1da177e4
LT		 2063 }
2064
a43ff5ba 2065 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2066 if (err < 0)
2067 goto out_free;
421a1252 2068 card->private_data = chip;
9a34af4a 2069 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2070
2071 pci_set_drvdata(pci, card);
2072
2073 err = register_vga_switcheroo(chip);
2074 if (err < 0) {
2b760d88 2075 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2076 goto out_free;
2077 }
2078
2079 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2080 dev_info(card->dev, "VGA controller is disabled\n");
2081 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2082 chip->disabled = true;
2083 }
2084
aad730d0 2085 schedule_probe = !chip->disabled;
1da177e4 2086
4918cdab
TI		 2087#ifdef CONFIG_SND_HDA_PATCH_LOADER
2088 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2089 dev_info(card->dev, "Applying patch firmware '%s'\n",
2090 patch[dev]);
5cb543db
TI		 2091 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2092 &pci->dev, GFP_KERNEL, card,
2093 azx_firmware_cb);
4918cdab
TI		 2094 if (err < 0)
2095 goto out_free;
aad730d0 2096 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2097 }
2098#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2099
aad730d0 2100#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2101 if (CONTROLLER_IN_GPU(pci))
2102 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2103#endif
99a2008d 2104
aad730d0 2105 if (schedule_probe)
9a34af4a 2106 schedule_work(&hda->probe_work);
a82d51ed 2107
a82d51ed 2108 dev++;
88d071fc 2109 if (chip->disabled)
9a34af4a 2110 complete_all(&hda->probe_wait);
a82d51ed
TI		 2111 return 0;
2112
2113out_free:
2114 snd_card_free(card);
2115 return err;
2116}
2117
1ba8f9d3
HG		 2118#ifdef CONFIG_PM
2119/* On some boards setting power_save to a non 0 value leads to clicking /
2120 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2121 * figure out how to avoid these sounds, but that is not always feasible.
2122 * So we keep a list of devices where we disable powersaving as its known
2123 * to causes problems on these devices.
2124 */
2125static struct snd_pci_quirk power_save_blacklist[] = {
2126 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
8e82a728 2127 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
1ba8f9d3 2128 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
39070a98
HG		 2129 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2130 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
45e5fbc2
HG		 2131 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2132 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
1ba8f9d3 2133 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
b529ef24
HG		 2134 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2135 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
38d9c12c 2136 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
5cb6b5fc
HG		 2137 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2138 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
38d9c12c
HG		 2139 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2140 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
5cb6b5fc
HG		 2141 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2142 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
f91f1806
HG		 2143 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2144 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
dd6dd536
HG		 2145 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2146 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
c8beccc1
HG		 2147 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2148 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
1ba8f9d3
HG		 2149 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2150 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2151 {}
2152};
2153#endif /* CONFIG_PM */
2154
37a3a98e
TI		 2155static void set_default_power_save(struct azx *chip)
2156{
2157 int val = power_save;
2158
2159#ifdef CONFIG_PM
2160 if (pm_blacklist) {
2161 const struct snd_pci_quirk *q;
2162
2163 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2164 if (q && val) {
2165 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2166 q->subvendor, q->subdevice);
2167 val = 0;
2168 }
2169 }
2170#endif /* CONFIG_PM */
2171 snd_hda_set_power_save(&chip->bus, val * 1000);
2172}
2173
e62a42ae
DR		 2174/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2175static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2176 [AZX_DRIVER_NVIDIA] = 8,
2177 [AZX_DRIVER_TERA] = 1,
2178};
2179
48c8b0eb 2180static int azx_probe_continue(struct azx *chip)
a82d51ed 2181{
9a34af4a 2182 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2183 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2184 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2185 int dev = chip->dev_index;
2186 int err;
2187
a41d1224 2188 hda->probe_continued = 1;
795614dd 2189
fcc88d91 2190 /* bind with i915 if needed */
dba9b7b6 2191 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
98d8fc6c 2192 err = snd_hdac_i915_init(bus);
535115b5
TI		 2193 if (err < 0) {
2194 /* if the controller is bound only with HDMI/DP
2195 * (for HSW and BDW), we need to abort the probe;
2196 * for other chips, still continue probing as other
2197 * codecs can be on the same link.
2198 */
bed2e98e
TI		 2199 if (CONTROLLER_IN_GPU(pci)) {
2200 dev_err(chip->card->dev,
2201 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2202 goto out_free;
fcc88d91
TI		 2203 } else {
2204 /* don't bother any longer */
e454ff8e 2205 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
fcc88d91 2206 }
535115b5 2207 }
e454ff8e
TI		 2208
2209 /* HSW/BDW controllers need this power */
2210 if (CONTROLLER_IN_GPU(pci))
2211 hda->need_i915_power = 1;
fcc88d91
TI		 2212 }
2213
2214 /* Request display power well for the HDA controller or codec. For
2215 * Haswell/Broadwell, both the display HDA controller and codec need
2216 * this power. For other platforms, like Baytrail/Braswell, only the
2217 * display codec needs the power and it can be released after probe.
2218 */
e454ff8e
TI		 2219 err = display_power(chip, true);
2220 if (err < 0) {
2221 dev_err(chip->card->dev,
2222 "Cannot turn on display power on i915\n");
2223 goto i915_power_fail;
99a2008d
WX		 2224 }
2225
5c90680e
TI		 2226 err = azx_first_init(chip);
2227 if (err < 0)
2228 goto out_free;
2229
2dca0bba
JK		 2230#ifdef CONFIG_SND_HDA_INPUT_BEEP
2231 chip->beep_mode = beep_mode[dev];
2232#endif
2233
1da177e4 2234 /* create codec instances */
96d2bd6e 2235 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2236 if (err < 0)
2237 goto out_free;
96d2bd6e 2238
4ea6fbc8 2239#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2240 if (chip->fw) {
a41d1224 2241 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2242 chip->fw->data);
4ea6fbc8
TI		 2243 if (err < 0)
2244 goto out_free;
e39ae856 2245#ifndef CONFIG_PM
4918cdab
TI		 2246 release_firmware(chip->fw); /* no longer needed */
2247 chip->fw = NULL;
e39ae856 2248#endif
4ea6fbc8
TI		 2249 }
2250#endif
10e77dda 2251 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2252 err = azx_codec_configure(chip);
2253 if (err < 0)
2254 goto out_free;
2255 }
1da177e4 2256
a82d51ed 2257 err = snd_card_register(chip->card);
41dda0fd
WF		 2258 if (err < 0)
2259 goto out_free;
1da177e4 2260
37a3a98e
TI		 2261 setup_vga_switcheroo_runtime_pm(chip);
2262
cb53c626 2263 chip->running = 1;
65fcd41d 2264 azx_add_card_list(chip);
07f4f97d 2265
37a3a98e 2266 set_default_power_save(chip);
07f4f97d 2267
07f4f97d 2268 if (azx_has_pm_runtime(chip))
30ff5957 2269 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2270
41dda0fd 2271out_free:
e454ff8e 2272 if (!hda->need_i915_power)
029d92c2 2273 display_power(chip, false);
795614dd
ML		 2274
2275i915_power_fail:
88d071fc 2276 if (err < 0)
9a34af4a
TI		 2277 hda->init_failed = 1;
2278 complete_all(&hda->probe_wait);
41dda0fd 2279 return err;
1da177e4
LT		 2280}
2281
e23e7a14 2282static void azx_remove(struct pci_dev *pci)
1da177e4 2283{
9121947d 2284 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2285 struct azx *chip;
2286 struct hda_intel *hda;
2287
2288 if (card) {
0b8c8219 2289 /* cancel the pending probing work */
991f86d7
TI		 2290 chip = card->private_data;
2291 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2292 /* FIXME: below is an ugly workaround.
2293 * Both device_release_driver() and driver_probe_device()
2294 * take *both* the device's and its parent's lock before
2295 * calling the remove() and probe() callbacks. The codec
2296 * probe takes the locks of both the codec itself and its
2297 * parent, i.e. the PCI controller dev. Meanwhile, when
2298 * the PCI controller is unbound, it takes its lock, too
2299 * ==> ouch, a deadlock!
2300 * As a workaround, we unlock temporarily here the controller
2301 * device during cancel_work_sync() call.
2302 */
2303 device_unlock(&pci->dev);
0b8c8219 2304 cancel_work_sync(&hda->probe_work);
ab949d51 2305 device_lock(&pci->dev);
b8dfc462 2306
9121947d 2307 snd_card_free(card);
991f86d7 2308 }
1da177e4
LT		 2309}
2310
b2a0bafa
TI		 2311static void azx_shutdown(struct pci_dev *pci)
2312{
2313 struct snd_card *card = pci_get_drvdata(pci);
2314 struct azx *chip;
2315
2316 if (!card)
2317 return;
2318 chip = card->private_data;
2319 if (chip && chip->running)
2320 azx_stop_chip(chip);
2321}
2322
1da177e4 2323/* PCI IDs */
6f51f6cf 2324static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2325 /* CPT */
9477c58e 2326 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2327 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2328 /* PBG */
9477c58e 2329 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2330 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2331 /* Panther Point */
9477c58e 2332 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2333 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2334 /* Lynx Point */
2335 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2336 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2337 /* 9 Series */
2338 { PCI_DEVICE(0x8086, 0x8ca0),
2339 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2340 /* Wellsburg */
2341 { PCI_DEVICE(0x8086, 0x8d20),
2342 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2343 { PCI_DEVICE(0x8086, 0x8d21),
2344 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2345 /* Lewisburg */
2346 { PCI_DEVICE(0x8086, 0xa1f0),
e7480b34 2347 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
5cf92c8b 2348 { PCI_DEVICE(0x8086, 0xa270),
e7480b34 2349 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
144dad99
JR		 2350 /* Lynx Point-LP */
2351 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2352 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2353 /* Lynx Point-LP */
2354 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2355 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2356 /* Wildcat Point-LP */
2357 { PCI_DEVICE(0x8086, 0x9ca0),
2358 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2359 /* Sunrise Point */
2360 { PCI_DEVICE(0x8086, 0xa170),
a4b4793f 2361 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2362 /* Sunrise Point-LP */
2363 { PCI_DEVICE(0x8086, 0x9d70),
a4b4793f 2364 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2365 /* Kabylake */
2366 { PCI_DEVICE(0x8086, 0xa171),
a4b4793f 2367 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2368 /* Kabylake-LP */
2369 { PCI_DEVICE(0x8086, 0x9d71),
a4b4793f 2370 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2371 /* Kabylake-H */
2372 { PCI_DEVICE(0x8086, 0xa2f0),
a4b4793f 2373 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
e79b0006
MD		 2374 /* Coffelake */
2375 { PCI_DEVICE(0x8086, 0xa348),
a4b4793f 2376 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2357f6f0
GS		 2377 /* Cannonlake */
2378 { PCI_DEVICE(0x8086, 0x9dc8),
2379 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
491f8331
GS		 2380 /* Icelake */
2381 { PCI_DEVICE(0x8086, 0x34c8),
2382 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
c87693da
LH		 2383 /* Broxton-P(Apollolake) */
2384 { PCI_DEVICE(0x8086, 0x5a98),
a4b4793f 2385 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2386 /* Broxton-T */
2387 { PCI_DEVICE(0x8086, 0x1a98),
a4b4793f 2388 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
44b46d73
VK		 2389 /* Gemini-Lake */
2390 { PCI_DEVICE(0x8086, 0x3198),
a4b4793f 2391 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2392 /* Haswell */
4a7c516b 2393 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2394 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2395 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2396 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2397 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2398 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2399 /* Broadwell */
2400 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2401 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2402 /* 5 Series/3400 */
2403 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2404 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2405 /* Poulsbo */
9477c58e 2406 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2407 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2408 /* Oaktrail */
09904b95 2409 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2410 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2411 /* BayTrail */
2412 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2413 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2414 /* Braswell */
2415 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2416 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2417 /* ICH6 */
8b0bd226 2418 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2419 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2420 /* ICH7 */
8b0bd226 2421 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2422 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2423 /* ESB2 */
8b0bd226 2424 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2425 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2426 /* ICH8 */
8b0bd226 2427 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2428 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2429 /* ICH9 */
8b0bd226 2430 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2431 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2432 /* ICH9 */
8b0bd226 2433 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2434 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2435 /* ICH10 */
8b0bd226 2436 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2437 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2438 /* ICH10 */
8b0bd226 2439 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2440 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2441 /* Generic Intel */
2442 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2443 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2444 .class_mask = 0xffffff,
103884a3 2445 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2446 /* ATI SB 450/600/700/800/900 */
2447 { PCI_DEVICE(0x1002, 0x437b),
2448 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2449 { PCI_DEVICE(0x1002, 0x4383),
2450 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2451 /* AMD Hudson */
2452 { PCI_DEVICE(0x1022, 0x780d),
2453 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3deef52c
KHF		 2454 /* AMD Stoney */
2455 { PCI_DEVICE(0x1022, 0x157a),
2456 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2457 AZX_DCAPS_PM_RUNTIME },
9ceace3c
VM		 2458 /* AMD Raven */
2459 { PCI_DEVICE(0x1022, 0x15e3),
1adca4b0
KHF		 2460 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2461 AZX_DCAPS_PM_RUNTIME },
87218e9c 2462 /* ATI HDMI */
fd48331f
MSB		 2463 { PCI_DEVICE(0x1002, 0x0002),
2464 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
650474fb
AD		 2465 { PCI_DEVICE(0x1002, 0x1308),
2466 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2467 { PCI_DEVICE(0x1002, 0x157a),
2468 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
d716fb03
AB		 2469 { PCI_DEVICE(0x1002, 0x15b3),
2470 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2471 { PCI_DEVICE(0x1002, 0x793b),
2472 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2473 { PCI_DEVICE(0x1002, 0x7919),
2474 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2475 { PCI_DEVICE(0x1002, 0x960f),
2476 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2477 { PCI_DEVICE(0x1002, 0x970f),
2478 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2479 { PCI_DEVICE(0x1002, 0x9840),
2480 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2481 { PCI_DEVICE(0x1002, 0xaa00),
2482 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2483 { PCI_DEVICE(0x1002, 0xaa08),
2484 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2485 { PCI_DEVICE(0x1002, 0xaa10),
2486 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2487 { PCI_DEVICE(0x1002, 0xaa18),
2488 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2489 { PCI_DEVICE(0x1002, 0xaa20),
2490 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2491 { PCI_DEVICE(0x1002, 0xaa28),
2492 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2493 { PCI_DEVICE(0x1002, 0xaa30),
2494 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2495 { PCI_DEVICE(0x1002, 0xaa38),
2496 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2497 { PCI_DEVICE(0x1002, 0xaa40),
2498 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2499 { PCI_DEVICE(0x1002, 0xaa48),
2500 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2501 { PCI_DEVICE(0x1002, 0xaa50),
2502 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2503 { PCI_DEVICE(0x1002, 0xaa58),
2504 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2505 { PCI_DEVICE(0x1002, 0xaa60),
2506 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2507 { PCI_DEVICE(0x1002, 0xaa68),
2508 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2509 { PCI_DEVICE(0x1002, 0xaa80),
2510 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2511 { PCI_DEVICE(0x1002, 0xaa88),
2512 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2513 { PCI_DEVICE(0x1002, 0xaa90),
2514 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2515 { PCI_DEVICE(0x1002, 0xaa98),
2516 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2517 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2518 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2519 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2520 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2521 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2522 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2523 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2524 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2525 { PCI_DEVICE(0x1002, 0xaac0),
2526 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2527 { PCI_DEVICE(0x1002, 0xaac8),
2528 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2529 { PCI_DEVICE(0x1002, 0xaad8),
2530 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2531 { PCI_DEVICE(0x1002, 0xaae8),
2532 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
8eb22214
MSB		 2533 { PCI_DEVICE(0x1002, 0xaae0),
2534 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2535 { PCI_DEVICE(0x1002, 0xaaf0),
2536 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2537 /* VIA VT8251/VT8237A */
26f05717 2538 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2539 /* VIA GFX VT7122/VX900 */
2540 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2541 /* VIA GFX VT6122/VX11 */
2542 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2543 /* SIS966 */
2544 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2545 /* ULI M5461 */
2546 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2547 /* NVIDIA MCP */
0c2fd1bf
TI		 2548 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2549 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2550 .class_mask = 0xffffff,
9477c58e 2551 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2552 /* Teradici */
9477c58e
TI		 2553 { PCI_DEVICE(0x6549, 0x1200),
2554 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2555 { PCI_DEVICE(0x6549, 0x2200),
2556 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2557 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2558 /* CTHDA chips */
2559 { PCI_DEVICE(0x1102, 0x0010),
2560 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2561 { PCI_DEVICE(0x1102, 0x0012),
2562 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2563#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2564 /* the following entry conflicts with snd-ctxfi driver,
2565 * as ctxfi driver mutates from HD-audio to native mode with
2566 * a special command sequence.
2567 */
4e01f54b
TI		 2568 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2569 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2570 .class_mask = 0xffffff,
9477c58e 2571 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2572 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2573#else
2574 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2575 { PCI_DEVICE(0x1102, 0x0009),
2576 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2577 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2578#endif
c563f473
TI		 2579 /* CM8888 */
2580 { PCI_DEVICE(0x13f6, 0x5011),
2581 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2582 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2583 /* Vortex86MX */
2584 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2585 /* VMware HDAudio */
2586 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2587 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2588 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2589 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2590 .class_mask = 0xffffff,
9477c58e 2591 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2592 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2593 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2594 .class_mask = 0xffffff,
9477c58e 2595 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2596 { 0, }
2597};
2598MODULE_DEVICE_TABLE(pci, azx_ids);
2599
2600/* pci_driver definition */
e9f66d9b 2601static struct pci_driver azx_driver = {
3733e424 2602 .name = KBUILD_MODNAME,
1da177e4
LT		 2603 .id_table = azx_ids,
2604 .probe = azx_probe,
e23e7a14 2605 .remove = azx_remove,
b2a0bafa 2606 .shutdown = azx_shutdown,
68cb2b55
TI		 2607 .driver = {
2608 .pm = AZX_PM_OPS,
2609 },
1da177e4
LT		 2610};
2611
e9f66d9b 2612module_pci_driver(azx_driver);
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