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ALSA: hda - Clean up superfluous position_fix list entries
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
27fe48d9
TI		 50#ifdef CONFIG_X86
51/* for snoop control */
52#include <asm/pgtable.h>
53#include <asm/cacheflush.h>
54#endif
1da177e4
LT		 55#include <sound/core.h>
56#include <sound/initval.h>
9121947d 57#include <linux/vgaarb.h>
a82d51ed 58#include <linux/vga_switcheroo.h>
4918cdab 59#include <linux/firmware.h>
1da177e4
LT		 60#include "hda_codec.h"
61
62
5aba4f8e
TI		 63static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
64static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 65static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 66static char *model[SNDRV_CARDS];
1dac6695 67static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 68static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 69static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 70static int probe_only[SNDRV_CARDS];
a67ff6a5 71static bool single_cmd;
71623855 72static int enable_msi = -1;
4ea6fbc8
TI		 73#ifdef CONFIG_SND_HDA_PATCH_LOADER
74static char *patch[SNDRV_CARDS];
75#endif
2dca0bba 76#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 77static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 78 CONFIG_SND_HDA_INPUT_BEEP_MODE};
79#endif
1da177e4 80
5aba4f8e 81module_param_array(index, int, NULL, 0444);
1da177e4 82MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 83module_param_array(id, charp, NULL, 0444);
1da177e4 84MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 85module_param_array(enable, bool, NULL, 0444);
86MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
87module_param_array(model, charp, NULL, 0444);
1da177e4 88MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 89module_param_array(position_fix, int, NULL, 0444);
4cb36310 90MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 91 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 92module_param_array(bdl_pos_adj, int, NULL, 0644);
93MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 94module_param_array(probe_mask, int, NULL, 0444);
606ad75f 95MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 96module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 97MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
27346166 98module_param(single_cmd, bool, 0444);
d01ce99f
TI		 99MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
100 "(for debugging only).");
ac9ef6cf 101module_param(enable_msi, bint, 0444);
134a11f0 102MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 103#ifdef CONFIG_SND_HDA_PATCH_LOADER
104module_param_array(patch, charp, NULL, 0444);
105MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
106#endif
2dca0bba 107#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 108module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 109MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 110 "(0=off, 1=on) (default=1).");
2dca0bba 111#endif
606ad75f 112
83012a7c 113#ifdef CONFIG_PM
65fcd41d
TI		 114static int param_set_xint(const char *val, const struct kernel_param *kp);
115static struct kernel_param_ops param_ops_xint = {
116 .set = param_set_xint,
117 .get = param_get_int,
118};
119#define param_check_xint param_check_int
120
fee2fba3 121static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 122module_param(power_save, xint, 0644);
fee2fba3
TI		 123MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
124 "(in second, 0 = disable).");
1da177e4 125
dee1b66c
TI		 126/* reset the HD-audio controller in power save mode.
127 * this may give more power-saving, but will take longer time to
128 * wake up.
129 */
a67ff6a5 130static bool power_save_controller = 1;
dee1b66c
TI		 131module_param(power_save_controller, bool, 0644);
132MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
83012a7c 133#endif /* CONFIG_PM */
dee1b66c 134
7bfe059e
TI		 135static int align_buffer_size = -1;
136module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 137MODULE_PARM_DESC(align_buffer_size,
138 "Force buffer and period sizes to be multiple of 128 bytes.");
139
27fe48d9
TI		 140#ifdef CONFIG_X86
141static bool hda_snoop = true;
142module_param_named(snoop, hda_snoop, bool, 0444);
143MODULE_PARM_DESC(snoop, "Enable/disable snooping");
144#define azx_snoop(chip) (chip)->snoop
145#else
146#define hda_snoop true
147#define azx_snoop(chip) true
148#endif
149
150
1da177e4
LT		 151MODULE_LICENSE("GPL");
152MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
153 "{Intel, ICH6M},"
2f1b3818 154 "{Intel, ICH7},"
f5d40b30 155 "{Intel, ESB2},"
d2981393 156 "{Intel, ICH8},"
f9cc8a8b 157 "{Intel, ICH9},"
c34f5a04 158 "{Intel, ICH10},"
b29c2360 159 "{Intel, PCH},"
d2f2fcd2 160 "{Intel, CPT},"
d2edeb7c 161 "{Intel, PPT},"
8bc039a1 162 "{Intel, LPT},"
144dad99 163 "{Intel, LPT_LP},"
e926f2c8 164 "{Intel, HPT},"
cea310e8 165 "{Intel, PBG},"
4979bca9 166 "{Intel, SCH},"
fc20a562 167 "{ATI, SB450},"
89be83f8 168 "{ATI, SB600},"
778b6e1b 169 "{ATI, RS600},"
5b15c95f 170 "{ATI, RS690},"
e6db1119
WL		 171 "{ATI, RS780},"
172 "{ATI, R600},"
2797f724
HRK		 173 "{ATI, RV630},"
174 "{ATI, RV610},"
27da1834
WL		 175 "{ATI, RV670},"
176 "{ATI, RV635},"
177 "{ATI, RV620},"
178 "{ATI, RV770},"
fc20a562 179 "{VIA, VT8251},"
47672310 180 "{VIA, VT8237A},"
07e4ca50
TI		 181 "{SiS, SIS966},"
182 "{ULI, M5461}}");
1da177e4
LT		 183MODULE_DESCRIPTION("Intel HDA driver");
184
4abc1cc2
TI		 185#ifdef CONFIG_SND_VERBOSE_PRINTK
186#define SFX /* nop */
187#else
1da177e4 188#define SFX "hda-intel: "
4abc1cc2 189#endif
cb53c626 190
a82d51ed
TI		 191#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
192#ifdef CONFIG_SND_HDA_CODEC_HDMI
193#define SUPPORT_VGA_SWITCHEROO
194#endif
195#endif
196
197
1da177e4
LT		 198/*
199 * registers
200 */
201#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 202#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
203#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
204#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
205#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
206#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 207#define ICH6_REG_VMIN 0x02
208#define ICH6_REG_VMAJ 0x03
209#define ICH6_REG_OUTPAY 0x04
210#define ICH6_REG_INPAY 0x06
211#define ICH6_REG_GCTL 0x08
8a933ece 212#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 213#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
214#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 215#define ICH6_REG_WAKEEN 0x0c
216#define ICH6_REG_STATESTS 0x0e
217#define ICH6_REG_GSTS 0x10
b21fadb9 218#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 219#define ICH6_REG_INTCTL 0x20
220#define ICH6_REG_INTSTS 0x24
e5463720 221#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 222#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
223#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 224#define ICH6_REG_CORBLBASE 0x40
225#define ICH6_REG_CORBUBASE 0x44
226#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 227#define ICH6_REG_CORBRP 0x4a
228#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 229#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 230#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
231#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 232#define ICH6_REG_CORBSTS 0x4d
b21fadb9 233#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 234#define ICH6_REG_CORBSIZE 0x4e
235
236#define ICH6_REG_RIRBLBASE 0x50
237#define ICH6_REG_RIRBUBASE 0x54
238#define ICH6_REG_RIRBWP 0x58
b21fadb9 239#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 240#define ICH6_REG_RINTCNT 0x5a
241#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 242#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
243#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
244#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 245#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 246#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
247#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 248#define ICH6_REG_RIRBSIZE 0x5e
249
250#define ICH6_REG_IC 0x60
251#define ICH6_REG_IR 0x64
252#define ICH6_REG_IRS 0x68
253#define ICH6_IRS_VALID (1<<1)
254#define ICH6_IRS_BUSY (1<<0)
255
256#define ICH6_REG_DPLBASE 0x70
257#define ICH6_REG_DPUBASE 0x74
258#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
259
260/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
261enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
262
263/* stream register offsets from stream base */
264#define ICH6_REG_SD_CTL 0x00
265#define ICH6_REG_SD_STS 0x03
266#define ICH6_REG_SD_LPIB 0x04
267#define ICH6_REG_SD_CBL 0x08
268#define ICH6_REG_SD_LVI 0x0c
269#define ICH6_REG_SD_FIFOW 0x0e
270#define ICH6_REG_SD_FIFOSIZE 0x10
271#define ICH6_REG_SD_FORMAT 0x12
272#define ICH6_REG_SD_BDLPL 0x18
273#define ICH6_REG_SD_BDLPU 0x1c
274
275/* PCI space */
276#define ICH6_PCIREG_TCSEL 0x44
277
278/*
279 * other constants
280 */
281
282/* max number of SDs */
07e4ca50 283/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 284#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 285#define ICH6_NUM_PLAYBACK 4
286
287/* ULI has 6 playback and 5 capture */
07e4ca50 288#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 289#define ULI_NUM_PLAYBACK 6
290
778b6e1b 291/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 292#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 293#define ATIHDMI_NUM_PLAYBACK 1
294
f269002e
KY		 295/* TERA has 4 playback and 3 capture */
296#define TERA_NUM_CAPTURE 3
297#define TERA_NUM_PLAYBACK 4
298
07e4ca50
TI		 299/* this number is statically defined for simplicity */
300#define MAX_AZX_DEV 16
301
1da177e4 302/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 303#define BDL_SIZE 4096
304#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
305#define AZX_MAX_FRAG 32
1da177e4
LT		 306/* max buffer size - no h/w limit, you can increase as you like */
307#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 308
309/* RIRB int mask: overrun[2], response[0] */
310#define RIRB_INT_RESPONSE 0x01
311#define RIRB_INT_OVERRUN 0x04
312#define RIRB_INT_MASK 0x05
313
2f5983f2 314/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 315#define AZX_MAX_CODECS 8
316#define AZX_DEFAULT_CODECS 4
deadff16 317#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 318
319/* SD_CTL bits */
320#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
321#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 322#define SD_CTL_STRIPE (3 << 16) /* stripe control */
323#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
324#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 325#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
326#define SD_CTL_STREAM_TAG_SHIFT 20
327
328/* SD_CTL and SD_STS */
329#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
330#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
331#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 332#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
333 SD_INT_COMPLETE)
1da177e4
LT		 334
335/* SD_STS */
336#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
337
338/* INTCTL and INTSTS */
d01ce99f
TI		 339#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
340#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
341#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 342
1da177e4
LT		 343/* below are so far hardcoded - should read registers in future */
344#define ICH6_MAX_CORB_ENTRIES 256
345#define ICH6_MAX_RIRB_ENTRIES 256
346
c74db86b
TI		 347/* position fix mode */
348enum {
0be3b5d3 349 POS_FIX_AUTO,
d2e1c973 350 POS_FIX_LPIB,
0be3b5d3 351 POS_FIX_POSBUF,
4cb36310 352 POS_FIX_VIACOMBO,
a6f2fd55 353 POS_FIX_COMBO,
c74db86b 354};
1da177e4 355
f5d40b30 356/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 357#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
358#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
359
da3fca21
V		 360/* Defines for Nvidia HDA support */
361#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
362#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 363#define NVIDIA_HDA_ISTRM_COH 0x4d
364#define NVIDIA_HDA_OSTRM_COH 0x4c
365#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 366
90a5ad52
TI		 367/* Defines for Intel SCH HDA snoop control */
368#define INTEL_SCH_HDA_DEVC 0x78
369#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
370
0e153474
JC		 371/* Define IN stream 0 FIFO size offset in VIA controller */
372#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
373/* Define VIA HD Audio Device ID*/
374#define VIA_HDAC_DEVICE_ID 0x3288
375
c4da29ca
YL		 376/* HD Audio class code */
377#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 378
1da177e4
LT		 379/*
380 */
381
a98f90fd 382struct azx_dev {
4ce107b9 383 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 384 u32 *posbuf; /* position buffer pointer */
1da177e4 385
d01ce99f 386 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 387 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 388 unsigned int frags; /* number for period in the play buffer */
389 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 390 unsigned long start_wallclk; /* start + minimum wallclk */
391 unsigned long period_wallclk; /* wallclk for period */
1da177e4 392
d01ce99f 393 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 394
d01ce99f 395 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 396
397 /* pcm support */
d01ce99f
TI		 398 struct snd_pcm_substream *substream; /* assigned substream,
399 * set in PCM open
400 */
401 unsigned int format_val; /* format value to be set in the
402 * controller and the codec
403 */
1da177e4
LT		 404 unsigned char stream_tag; /* assigned stream */
405 unsigned char index; /* stream index */
d5cf9911 406 int assigned_key; /* last device# key assigned to */
1da177e4 407
927fc866
PM		 408 unsigned int opened :1;
409 unsigned int running :1;
675f25d4 410 unsigned int irq_pending :1;
0e153474
JC		 411 /*
412 * For VIA:
413 * A flag to ensure DMA position is 0
414 * when link position is not greater than FIFO size
415 */
416 unsigned int insufficient :1;
27fe48d9 417 unsigned int wc_marked:1;
915bf29e 418 unsigned int no_period_wakeup:1;
1da177e4
LT		 419};
420
421/* CORB/RIRB */
a98f90fd 422struct azx_rb {
1da177e4
LT		 423 u32 *buf; /* CORB/RIRB buffer
424 * Each CORB entry is 4byte, RIRB is 8byte
425 */
426 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
427 /* for RIRB */
428 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 429 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
430 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 431};
432
01b65bfb
TI		 433struct azx_pcm {
434 struct azx *chip;
435 struct snd_pcm *pcm;
436 struct hda_codec *codec;
437 struct hda_pcm_stream *hinfo[2];
438 struct list_head list;
439};
440
a98f90fd
TI		 441struct azx {
442 struct snd_card *card;
1da177e4 443 struct pci_dev *pci;
555e219f 444 int dev_index;
1da177e4 445
07e4ca50
TI		 446 /* chip type specific */
447 int driver_type;
9477c58e 448 unsigned int driver_caps;
07e4ca50
TI		 449 int playback_streams;
450 int playback_index_offset;
451 int capture_streams;
452 int capture_index_offset;
453 int num_streams;
454
1da177e4
LT		 455 /* pci resources */
456 unsigned long addr;
457 void __iomem *remap_addr;
458 int irq;
459
460 /* locks */
461 spinlock_t reg_lock;
62932df8 462 struct mutex open_mutex;
1da177e4 463
07e4ca50 464 /* streams (x num_streams) */
a98f90fd 465 struct azx_dev *azx_dev;
1da177e4
LT		 466
467 /* PCM */
01b65bfb 468 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 469
470 /* HD codec */
471 unsigned short codec_mask;
f1eaaeec 472 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 473 struct hda_bus *bus;
2dca0bba 474 unsigned int beep_mode;
1da177e4
LT		 475
476 /* CORB/RIRB */
a98f90fd
TI		 477 struct azx_rb corb;
478 struct azx_rb rirb;
1da177e4 479
4ce107b9 480 /* CORB/RIRB and position buffers */
1da177e4
LT		 481 struct snd_dma_buffer rb;
482 struct snd_dma_buffer posbuf;
c74db86b 483
4918cdab
TI		 484#ifdef CONFIG_SND_HDA_PATCH_LOADER
485 const struct firmware *fw;
486#endif
487
c74db86b 488 /* flags */
beaffc39 489 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 490 int poll_count;
cb53c626 491 unsigned int running :1;
927fc866
PM		 492 unsigned int initialized :1;
493 unsigned int single_cmd :1;
494 unsigned int polling_mode :1;
68e7fffc 495 unsigned int msi :1;
a6a950a8 496 unsigned int irq_pending_warned :1;
6ce4a3bc 497 unsigned int probing :1; /* codec probing phase */
27fe48d9 498 unsigned int snoop:1;
52409aa6 499 unsigned int align_buffer_size:1;
a82d51ed
TI		 500 unsigned int region_requested:1;
501
502 /* VGA-switcheroo setup */
503 unsigned int use_vga_switcheroo:1;
504 unsigned int init_failed:1; /* delayed init failed */
505 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 506
507 /* for debugging */
feb27340 508 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 509
510 /* for pending irqs */
511 struct work_struct irq_pending_work;
0cbf0098
TI		 512
513 /* reboot notifier (for mysterious hangup problem at power-down) */
514 struct notifier_block reboot_notifier;
65fcd41d
TI		 515
516 /* card list (for power_save trigger) */
517 struct list_head list;
1da177e4
LT		 518};
519
07e4ca50
TI		 520/* driver types */
521enum {
522 AZX_DRIVER_ICH,
32679f95 523 AZX_DRIVER_PCH,
4979bca9 524 AZX_DRIVER_SCH,
07e4ca50 525 AZX_DRIVER_ATI,
778b6e1b 526 AZX_DRIVER_ATIHDMI,
1815b34a 527 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 528 AZX_DRIVER_VIA,
529 AZX_DRIVER_SIS,
530 AZX_DRIVER_ULI,
da3fca21 531 AZX_DRIVER_NVIDIA,
f269002e 532 AZX_DRIVER_TERA,
14d34f16 533 AZX_DRIVER_CTX,
5ae763b1 534 AZX_DRIVER_CTHDA,
c4da29ca 535 AZX_DRIVER_GENERIC,
2f5983f2 536 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 537};
538
9477c58e
TI		 539/* driver quirks (capabilities) */
540/* bits 0-7 are used for indicating driver type */
541#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
542#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
543#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
544#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
545#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
546#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
547#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
548#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
549#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
550#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
551#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
552#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 553#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 554#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 555#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 556#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
90accc58 557#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
9477c58e
TI		 558
559/* quirks for ATI SB / AMD Hudson */
560#define AZX_DCAPS_PRESET_ATI_SB \
561 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
562 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
563
564/* quirks for ATI/AMD HDMI */
565#define AZX_DCAPS_PRESET_ATI_HDMI \
566 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
567
568/* quirks for Nvidia */
569#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e
TI		 570 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
571 AZX_DCAPS_ALIGN_BUFSIZE)
9477c58e 572
5ae763b1
TI		 573#define AZX_DCAPS_PRESET_CTHDA \
574 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
575
a82d51ed
TI		 576/*
577 * VGA-switcher support
578 */
579#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 580#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
581#else
582#define use_vga_switcheroo(chip) 0
583#endif
584
585#if defined(SUPPORT_VGA_SWITCHEROO) || defined(CONFIG_SND_HDA_PATCH_LOADER)
a82d51ed
TI		 586#define DELAYED_INIT_MARK
587#define DELAYED_INITDATA_MARK
a82d51ed
TI		 588#else
589#define DELAYED_INIT_MARK __devinit
590#define DELAYED_INITDATA_MARK __devinitdata
a82d51ed
TI		 591#endif
592
593static char *driver_short_names[] DELAYED_INITDATA_MARK = {
07e4ca50 594 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 595 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 596 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 597 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 598 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 599 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 600 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
601 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 602 [AZX_DRIVER_ULI] = "HDA ULI M5461",
603 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 604 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 605 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 606 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 607 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 608};
609
1da177e4
LT		 610/*
611 * macros for easy use
612 */
613#define azx_writel(chip,reg,value) \
614 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
615#define azx_readl(chip,reg) \
616 readl((chip)->remap_addr + ICH6_REG_##reg)
617#define azx_writew(chip,reg,value) \
618 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
619#define azx_readw(chip,reg) \
620 readw((chip)->remap_addr + ICH6_REG_##reg)
621#define azx_writeb(chip,reg,value) \
622 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
623#define azx_readb(chip,reg) \
624 readb((chip)->remap_addr + ICH6_REG_##reg)
625
626#define azx_sd_writel(dev,reg,value) \
627 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
628#define azx_sd_readl(dev,reg) \
629 readl((dev)->sd_addr + ICH6_REG_##reg)
630#define azx_sd_writew(dev,reg,value) \
631 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
632#define azx_sd_readw(dev,reg) \
633 readw((dev)->sd_addr + ICH6_REG_##reg)
634#define azx_sd_writeb(dev,reg,value) \
635 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
636#define azx_sd_readb(dev,reg) \
637 readb((dev)->sd_addr + ICH6_REG_##reg)
638
639/* for pcm support */
a98f90fd 640#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 641
27fe48d9
TI		 642#ifdef CONFIG_X86
643static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
644{
645 if (azx_snoop(chip))
646 return;
647 if (addr && size) {
648 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
649 if (on)
650 set_memory_wc((unsigned long)addr, pages);
651 else
652 set_memory_wb((unsigned long)addr, pages);
653 }
654}
655
656static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
657 bool on)
658{
659 __mark_pages_wc(chip, buf->area, buf->bytes, on);
660}
661static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
662 struct snd_pcm_runtime *runtime, bool on)
663{
664 if (azx_dev->wc_marked != on) {
665 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
666 azx_dev->wc_marked = on;
667 }
668}
669#else
670/* NOP for other archs */
671static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
672 bool on)
673{
674}
675static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
676 struct snd_pcm_runtime *runtime, bool on)
677{
678}
679#endif
680
68e7fffc 681static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 682static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 683/*
684 * Interface for HD codec
685 */
686
1da177e4
LT		 687/*
688 * CORB / RIRB interface
689 */
a98f90fd 690static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 691{
692 int err;
693
694 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 695 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
696 snd_dma_pci_data(chip->pci),
1da177e4
LT		 697 PAGE_SIZE, &chip->rb);
698 if (err < 0) {
699 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
700 return err;
701 }
27fe48d9 702 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 703 return 0;
704}
705
a98f90fd 706static void azx_init_cmd_io(struct azx *chip)
1da177e4 707{
cdb1fbf2 708 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 709 /* CORB set up */
710 chip->corb.addr = chip->rb.addr;
711 chip->corb.buf = (u32 *)chip->rb.area;
712 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 713 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 714
07e4ca50
TI		 715 /* set the corb size to 256 entries (ULI requires explicitly) */
716 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 717 /* set the corb write pointer to 0 */
718 azx_writew(chip, CORBWP, 0);
719 /* reset the corb hw read pointer */
b21fadb9 720 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 721 /* enable corb dma */
b21fadb9 722 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 723
724 /* RIRB set up */
725 chip->rirb.addr = chip->rb.addr + 2048;
726 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 727 chip->rirb.wp = chip->rirb.rp = 0;
728 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 729 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 730 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 731
07e4ca50
TI		 732 /* set the rirb size to 256 entries (ULI requires explicitly) */
733 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 734 /* reset the rirb hw write pointer */
b21fadb9 735 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 736 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 737 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 738 azx_writew(chip, RINTCNT, 0xc0);
739 else
740 azx_writew(chip, RINTCNT, 1);
1da177e4 741 /* enable rirb dma and response irq */
1da177e4 742 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 743 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 744}
745
a98f90fd 746static void azx_free_cmd_io(struct azx *chip)
1da177e4 747{
cdb1fbf2 748 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 749 /* disable ringbuffer DMAs */
750 azx_writeb(chip, RIRBCTL, 0);
751 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 752 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 753}
754
deadff16
WF		 755static unsigned int azx_command_addr(u32 cmd)
756{
757 unsigned int addr = cmd >> 28;
758
759 if (addr >= AZX_MAX_CODECS) {
760 snd_BUG();
761 addr = 0;
762 }
763
764 return addr;
765}
766
767static unsigned int azx_response_addr(u32 res)
768{
769 unsigned int addr = res & 0xf;
770
771 if (addr >= AZX_MAX_CODECS) {
772 snd_BUG();
773 addr = 0;
774 }
775
776 return addr;
1da177e4
LT		 777}
778
779/* send a command */
33fa35ed 780static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 781{
33fa35ed 782 struct azx *chip = bus->private_data;
deadff16 783 unsigned int addr = azx_command_addr(val);
1da177e4 784 unsigned int wp;
1da177e4 785
c32649fe
WF		 786 spin_lock_irq(&chip->reg_lock);
787
1da177e4
LT		 788 /* add command to corb */
789 wp = azx_readb(chip, CORBWP);
790 wp++;
791 wp %= ICH6_MAX_CORB_ENTRIES;
792
deadff16 793 chip->rirb.cmds[addr]++;
1da177e4
LT		 794 chip->corb.buf[wp] = cpu_to_le32(val);
795 azx_writel(chip, CORBWP, wp);
c32649fe 796
1da177e4
LT		 797 spin_unlock_irq(&chip->reg_lock);
798
799 return 0;
800}
801
802#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
803
804/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 805static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 806{
807 unsigned int rp, wp;
deadff16 808 unsigned int addr;
1da177e4
LT		 809 u32 res, res_ex;
810
811 wp = azx_readb(chip, RIRBWP);
812 if (wp == chip->rirb.wp)
813 return;
814 chip->rirb.wp = wp;
deadff16 815
1da177e4
LT		 816 while (chip->rirb.rp != wp) {
817 chip->rirb.rp++;
818 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
819
820 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
821 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
822 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 823 addr = azx_response_addr(res_ex);
1da177e4
LT		 824 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
825 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 826 else if (chip->rirb.cmds[addr]) {
827 chip->rirb.res[addr] = res;
2add9b92 828 smp_wmb();
deadff16 829 chip->rirb.cmds[addr]--;
e310bb06
WF		 830 } else
831 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
832 "last cmd=%#08x\n",
833 res, res_ex,
834 chip->last_cmd[addr]);
1da177e4
LT		 835 }
836}
837
838/* receive a response */
deadff16
WF		 839static unsigned int azx_rirb_get_response(struct hda_bus *bus,
840 unsigned int addr)
1da177e4 841{
33fa35ed 842 struct azx *chip = bus->private_data;
5c79b1f8 843 unsigned long timeout;
32cf4023 844 unsigned long loopcounter;
1eb6dc7d 845 int do_poll = 0;
1da177e4 846
5c79b1f8
TI		 847 again:
848 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 849
850 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 851 if (chip->polling_mode || do_poll) {
e96224ae
TI		 852 spin_lock_irq(&chip->reg_lock);
853 azx_update_rirb(chip);
854 spin_unlock_irq(&chip->reg_lock);
855 }
deadff16 856 if (!chip->rirb.cmds[addr]) {
2add9b92 857 smp_rmb();
b613291f 858 bus->rirb_error = 0;
1eb6dc7d
ML		 859
860 if (!do_poll)
861 chip->poll_count = 0;
deadff16 862 return chip->rirb.res[addr]; /* the last value */
2add9b92 863 }
28a0d9df
TI		 864 if (time_after(jiffies, timeout))
865 break;
32cf4023 866 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 867 msleep(2); /* temporary workaround */
868 else {
869 udelay(10);
870 cond_resched();
871 }
28a0d9df 872 }
5c79b1f8 873
1eb6dc7d
ML		 874 if (!chip->polling_mode && chip->poll_count < 2) {
875 snd_printdd(SFX "azx_get_response timeout, "
876 "polling the codec once: last cmd=0x%08x\n",
877 chip->last_cmd[addr]);
878 do_poll = 1;
879 chip->poll_count++;
880 goto again;
881 }
882
883
23c4a881
TI		 884 if (!chip->polling_mode) {
885 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
886 "switching to polling mode: last cmd=0x%08x\n",
887 chip->last_cmd[addr]);
888 chip->polling_mode = 1;
889 goto again;
890 }
891
68e7fffc 892 if (chip->msi) {
4abc1cc2 893 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 894 "disabling MSI: last cmd=0x%08x\n",
895 chip->last_cmd[addr]);
68e7fffc
TI		 896 free_irq(chip->irq, chip);
897 chip->irq = -1;
898 pci_disable_msi(chip->pci);
899 chip->msi = 0;
b613291f
TI		 900 if (azx_acquire_irq(chip, 1) < 0) {
901 bus->rirb_error = 1;
68e7fffc 902 return -1;
b613291f 903 }
68e7fffc
TI		 904 goto again;
905 }
906
6ce4a3bc
TI		 907 if (chip->probing) {
908 /* If this critical timeout happens during the codec probing
909 * phase, this is likely an access to a non-existing codec
910 * slot. Better to return an error and reset the system.
911 */
912 return -1;
913 }
914
8dd78330
TI		 915 /* a fatal communication error; need either to reset or to fallback
916 * to the single_cmd mode
917 */
b613291f 918 bus->rirb_error = 1;
b20f3b83 919 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 920 bus->response_reset = 1;
921 return -1; /* give a chance to retry */
922 }
923
924 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
925 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 926 chip->last_cmd[addr]);
8dd78330
TI		 927 chip->single_cmd = 1;
928 bus->response_reset = 0;
1a696978 929 /* release CORB/RIRB */
4fcd3920 930 azx_free_cmd_io(chip);
1a696978
TI		 931 /* disable unsolicited responses */
932 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 933 return -1;
1da177e4
LT		 934}
935
1da177e4
LT		 936/*
937 * Use the single immediate command instead of CORB/RIRB for simplicity
938 *
939 * Note: according to Intel, this is not preferred use. The command was
940 * intended for the BIOS only, and may get confused with unsolicited
941 * responses. So, we shouldn't use it for normal operation from the
942 * driver.
943 * I left the codes, however, for debugging/testing purposes.
944 */
945
b05a7d4f 946/* receive a response */
deadff16 947static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 948{
949 int timeout = 50;
950
951 while (timeout--) {
952 /* check IRV busy bit */
953 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
954 /* reuse rirb.res as the response return value */
deadff16 955 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 956 return 0;
957 }
958 udelay(1);
959 }
960 if (printk_ratelimit())
961 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
962 azx_readw(chip, IRS));
deadff16 963 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 964 return -EIO;
965}
966
1da177e4 967/* send a command */
33fa35ed 968static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 969{
33fa35ed 970 struct azx *chip = bus->private_data;
deadff16 971 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 972 int timeout = 50;
973
8dd78330 974 bus->rirb_error = 0;
1da177e4
LT		 975 while (timeout--) {
976 /* check ICB busy bit */
d01ce99f 977 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 978 /* Clear IRV valid bit */
d01ce99f
TI		 979 azx_writew(chip, IRS, azx_readw(chip, IRS) |
980 ICH6_IRS_VALID);
1da177e4 981 azx_writel(chip, IC, val);
d01ce99f
TI		 982 azx_writew(chip, IRS, azx_readw(chip, IRS) |
983 ICH6_IRS_BUSY);
deadff16 984 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 985 }
986 udelay(1);
987 }
1cfd52bc
MB		 988 if (printk_ratelimit())
989 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
990 azx_readw(chip, IRS), val);
1da177e4
LT		 991 return -EIO;
992}
993
994/* receive a response */
deadff16
WF		 995static unsigned int azx_single_get_response(struct hda_bus *bus,
996 unsigned int addr)
1da177e4 997{
33fa35ed 998 struct azx *chip = bus->private_data;
deadff16 999 return chip->rirb.res[addr];
1da177e4
LT		 1000}
1001
111d3af5
TI		 1002/*
1003 * The below are the main callbacks from hda_codec.
1004 *
1005 * They are just the skeleton to call sub-callbacks according to the
1006 * current setting of chip->single_cmd.
1007 */
1008
1009/* send a command */
33fa35ed 1010static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 1011{
33fa35ed 1012 struct azx *chip = bus->private_data;
43bbb6cc 1013
a82d51ed
TI		 1014 if (chip->disabled)
1015 return 0;
feb27340 1016 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 1017 if (chip->single_cmd)
33fa35ed 1018 return azx_single_send_cmd(bus, val);
111d3af5 1019 else
33fa35ed 1020 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 1021}
1022
1023/* get a response */
deadff16
WF		 1024static unsigned int azx_get_response(struct hda_bus *bus,
1025 unsigned int addr)
111d3af5 1026{
33fa35ed 1027 struct azx *chip = bus->private_data;
a82d51ed
TI		 1028 if (chip->disabled)
1029 return 0;
111d3af5 1030 if (chip->single_cmd)
deadff16 1031 return azx_single_get_response(bus, addr);
111d3af5 1032 else
deadff16 1033 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1034}
1035
83012a7c 1036#ifdef CONFIG_PM
68467f51 1037static void azx_power_notify(struct hda_bus *bus, bool power_up);
cb53c626 1038#endif
111d3af5 1039
1da177e4 1040/* reset codec link */
cd508fe5 1041static int azx_reset(struct azx *chip, int full_reset)
1da177e4
LT		 1042{
1043 int count;
1044
cd508fe5
JK		 1045 if (!full_reset)
1046 goto __skip;
1047
e8a7f136
DT		 1048 /* clear STATESTS */
1049 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1050
1da177e4
LT		 1051 /* reset controller */
1052 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1053
1054 count = 50;
1055 while (azx_readb(chip, GCTL) && --count)
1056 msleep(1);
1057
1058 /* delay for >= 100us for codec PLL to settle per spec
1059 * Rev 0.9 section 5.5.1
1060 */
1061 msleep(1);
1062
1063 /* Bring controller out of reset */
1064 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1065
1066 count = 50;
927fc866 1067 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 1068 msleep(1);
1069
927fc866 1070 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 1071 msleep(1);
1072
cd508fe5 1073 __skip:
1da177e4 1074 /* check to see if controller is ready */
927fc866 1075 if (!azx_readb(chip, GCTL)) {
4abc1cc2 1076 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 1077 return -EBUSY;
1078 }
1079
41e2fce4 1080 /* Accept unsolicited responses */
1a696978
TI		 1081 if (!chip->single_cmd)
1082 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1083 ICH6_GCTL_UNSOL);
41e2fce4 1084
1da177e4 1085 /* detect codecs */
927fc866 1086 if (!chip->codec_mask) {
1da177e4 1087 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 1088 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 1089 }
1090
1091 return 0;
1092}
1093
1094
1095/*
1096 * Lowlevel interface
1097 */
1098
1099/* enable interrupts */
a98f90fd 1100static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1101{
1102 /* enable controller CIE and GIE */
1103 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1104 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1105}
1106
1107/* disable interrupts */
a98f90fd 1108static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1109{
1110 int i;
1111
1112 /* disable interrupts in stream descriptor */
07e4ca50 1113 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1114 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1115 azx_sd_writeb(azx_dev, SD_CTL,
1116 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1117 }
1118
1119 /* disable SIE for all streams */
1120 azx_writeb(chip, INTCTL, 0);
1121
1122 /* disable controller CIE and GIE */
1123 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1124 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1125}
1126
1127/* clear interrupts */
a98f90fd 1128static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1129{
1130 int i;
1131
1132 /* clear stream status */
07e4ca50 1133 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1134 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1135 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1136 }
1137
1138 /* clear STATESTS */
1139 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1140
1141 /* clear rirb status */
1142 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1143
1144 /* clear int status */
1145 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1146}
1147
1148/* start a stream */
a98f90fd 1149static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1150{
0e153474
JC		 1151 /*
1152 * Before stream start, initialize parameter
1153 */
1154 azx_dev->insufficient = 1;
1155
1da177e4 1156 /* enable SIE */
ccc5df05
WN		 1157 azx_writel(chip, INTCTL,
1158 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1159 /* set DMA start and interrupt mask */
1160 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1161 SD_CTL_DMA_START | SD_INT_MASK);
1162}
1163
1dddab40
TI		 1164/* stop DMA */
1165static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1166{
1da177e4
LT		 1167 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1168 ~(SD_CTL_DMA_START | SD_INT_MASK));
1169 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1170}
1171
1172/* stop a stream */
1173static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1174{
1175 azx_stream_clear(chip, azx_dev);
1da177e4 1176 /* disable SIE */
ccc5df05
WN		 1177 azx_writel(chip, INTCTL,
1178 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1179}
1180
1181
1182/*
cb53c626 1183 * reset and start the controller registers
1da177e4 1184 */
cd508fe5 1185static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1186{
cb53c626
TI		 1187 if (chip->initialized)
1188 return;
1da177e4
LT		 1189
1190 /* reset controller */
cd508fe5 1191 azx_reset(chip, full_reset);
1da177e4
LT		 1192
1193 /* initialize interrupts */
1194 azx_int_clear(chip);
1195 azx_int_enable(chip);
1196
1197 /* initialize the codec command I/O */
1a696978
TI		 1198 if (!chip->single_cmd)
1199 azx_init_cmd_io(chip);
1da177e4 1200
0be3b5d3
TI		 1201 /* program the position buffer */
1202 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1203 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1204
cb53c626
TI		 1205 chip->initialized = 1;
1206}
1207
1208/*
1209 * initialize the PCI registers
1210 */
1211/* update bits in a PCI register byte */
1212static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1213 unsigned char mask, unsigned char val)
1214{
1215 unsigned char data;
1216
1217 pci_read_config_byte(pci, reg, &data);
1218 data &= ~mask;
1219 data |= (val & mask);
1220 pci_write_config_byte(pci, reg, data);
1221}
1222
1223static void azx_init_pci(struct azx *chip)
1224{
1225 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1226 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1227 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1228 * codecs.
1229 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1230 */
46f2cc80 1231 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
9477c58e 1232 snd_printdd(SFX "Clearing TCSEL\n");
a09e89f6 1233 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1234 }
cb53c626 1235
9477c58e
TI		 1236 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1237 * we need to enable snoop.
1238 */
1239 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
27fe48d9 1240 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
cb53c626 1241 update_pci_byte(chip->pci,
27fe48d9
TI		 1242 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1243 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1244 }
1245
1246 /* For NVIDIA HDA, enable snoop */
1247 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
27fe48d9 1248 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
cb53c626
TI		 1249 update_pci_byte(chip->pci,
1250 NVIDIA_HDA_TRANSREG_ADDR,
1251 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1252 update_pci_byte(chip->pci,
1253 NVIDIA_HDA_ISTRM_COH,
1254 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1255 update_pci_byte(chip->pci,
1256 NVIDIA_HDA_OSTRM_COH,
1257 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1258 }
1259
1260 /* Enable SCH/PCH snoop if needed */
1261 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1262 unsigned short snoop;
90a5ad52 1263 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1264 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1265 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1266 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1267 if (!azx_snoop(chip))
1268 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1269 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1270 pci_read_config_word(chip->pci,
1271 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1272 }
27fe48d9
TI		 1273 snd_printdd(SFX "SCH snoop: %s\n",
1274 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1275 ? "Disabled" : "Enabled");
da3fca21 1276 }
1da177e4
LT		 1277}
1278
1279
9ad593f6
TI		 1280static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1281
1da177e4
LT		 1282/*
1283 * interrupt handler
1284 */
7d12e780 1285static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1286{
a98f90fd
TI		 1287 struct azx *chip = dev_id;
1288 struct azx_dev *azx_dev;
1da177e4 1289 u32 status;
9ef04066 1290 u8 sd_status;
fa00e046 1291 int i, ok;
1da177e4 1292
b8dfc462
ML		 1293#ifdef CONFIG_PM_RUNTIME
1294 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1295 return IRQ_NONE;
1296#endif
1297
1da177e4
LT		 1298 spin_lock(&chip->reg_lock);
1299
60911062
DC		 1300 if (chip->disabled) {
1301 spin_unlock(&chip->reg_lock);
a82d51ed 1302 return IRQ_NONE;
60911062 1303 }
a82d51ed 1304
1da177e4
LT		 1305 status = azx_readl(chip, INTSTS);
1306 if (status == 0) {
1307 spin_unlock(&chip->reg_lock);
1308 return IRQ_NONE;
1309 }
1310
07e4ca50 1311 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1312 azx_dev = &chip->azx_dev[i];
1313 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1314 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1315 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1316 if (!azx_dev->substream || !azx_dev->running ||
1317 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1318 continue;
1319 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1320 ok = azx_position_ok(chip, azx_dev);
1321 if (ok == 1) {
9ad593f6 1322 azx_dev->irq_pending = 0;
1da177e4
LT		 1323 spin_unlock(&chip->reg_lock);
1324 snd_pcm_period_elapsed(azx_dev->substream);
1325 spin_lock(&chip->reg_lock);
fa00e046 1326 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1327 /* bogus IRQ, process it later */
1328 azx_dev->irq_pending = 1;
6acaed38
TI		 1329 queue_work(chip->bus->workq,
1330 &chip->irq_pending_work);
1da177e4
LT		 1331 }
1332 }
1333 }
1334
1335 /* clear rirb int */
1336 status = azx_readb(chip, RIRBSTS);
1337 if (status & RIRB_INT_MASK) {
14d34f16 1338 if (status & RIRB_INT_RESPONSE) {
9477c58e 1339 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1340 udelay(80);
1da177e4 1341 azx_update_rirb(chip);
14d34f16 1342 }
1da177e4
LT		 1343 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1344 }
1345
1346#if 0
1347 /* clear state status int */
1348 if (azx_readb(chip, STATESTS) & 0x04)
1349 azx_writeb(chip, STATESTS, 0x04);
1350#endif
1351 spin_unlock(&chip->reg_lock);
1352
1353 return IRQ_HANDLED;
1354}
1355
1356
675f25d4
TI		 1357/*
1358 * set up a BDL entry
1359 */
5ae763b1
TI		 1360static int setup_bdle(struct azx *chip,
1361 struct snd_pcm_substream *substream,
675f25d4
TI		 1362 struct azx_dev *azx_dev, u32 **bdlp,
1363 int ofs, int size, int with_ioc)
1364{
675f25d4
TI		 1365 u32 *bdl = *bdlp;
1366
1367 while (size > 0) {
1368 dma_addr_t addr;
1369 int chunk;
1370
1371 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1372 return -EINVAL;
1373
77a23f26 1374 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1375 /* program the address field of the BDL entry */
1376 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1377 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1378 /* program the size field of the BDL entry */
fc4abee8 1379 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
5ae763b1
TI		 1380 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1381 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1382 u32 remain = 0x1000 - (ofs & 0xfff);
1383 if (chunk > remain)
1384 chunk = remain;
1385 }
675f25d4
TI		 1386 bdl[2] = cpu_to_le32(chunk);
1387 /* program the IOC to enable interrupt
1388 * only when the whole fragment is processed
1389 */
1390 size -= chunk;
1391 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1392 bdl += 4;
1393 azx_dev->frags++;
1394 ofs += chunk;
1395 }
1396 *bdlp = bdl;
1397 return ofs;
1398}
1399
1da177e4
LT		 1400/*
1401 * set up BDL entries
1402 */
555e219f
TI		 1403static int azx_setup_periods(struct azx *chip,
1404 struct snd_pcm_substream *substream,
4ce107b9 1405 struct azx_dev *azx_dev)
1da177e4 1406{
4ce107b9
TI		 1407 u32 *bdl;
1408 int i, ofs, periods, period_bytes;
555e219f 1409 int pos_adj;
1da177e4
LT		 1410
1411 /* reset BDL address */
1412 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1413 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1414
97b71c94 1415 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1416 periods = azx_dev->bufsize / period_bytes;
1417
1da177e4 1418 /* program the initial BDL entries */
4ce107b9
TI		 1419 bdl = (u32 *)azx_dev->bdl.area;
1420 ofs = 0;
1421 azx_dev->frags = 0;
555e219f 1422 pos_adj = bdl_pos_adj[chip->dev_index];
915bf29e 1423 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
675f25d4 1424 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1425 int pos_align = pos_adj;
555e219f 1426 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1427 if (!pos_adj)
e785d3d8
TI		 1428 pos_adj = pos_align;
1429 else
1430 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1431 pos_align;
675f25d4
TI		 1432 pos_adj = frames_to_bytes(runtime, pos_adj);
1433 if (pos_adj >= period_bytes) {
4abc1cc2 1434 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1435 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1436 pos_adj = 0;
1437 } else {
5ae763b1 1438 ofs = setup_bdle(chip, substream, azx_dev,
915bf29e 1439 &bdl, ofs, pos_adj, true);
675f25d4
TI		 1440 if (ofs < 0)
1441 goto error;
4ce107b9 1442 }
555e219f
TI		 1443 } else
1444 pos_adj = 0;
675f25d4
TI		 1445 for (i = 0; i < periods; i++) {
1446 if (i == periods - 1 && pos_adj)
5ae763b1 1447 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
675f25d4
TI		 1448 period_bytes - pos_adj, 0);
1449 else
5ae763b1 1450 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
7bb8fb70 1451 period_bytes,
915bf29e 1452 !azx_dev->no_period_wakeup);
675f25d4
TI		 1453 if (ofs < 0)
1454 goto error;
1da177e4 1455 }
4ce107b9 1456 return 0;
675f25d4
TI		 1457
1458 error:
4abc1cc2 1459 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1460 azx_dev->bufsize, period_bytes);
675f25d4 1461 return -EINVAL;
1da177e4
LT		 1462}
1463
1dddab40
TI		 1464/* reset stream */
1465static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1466{
1467 unsigned char val;
1468 int timeout;
1469
1dddab40
TI		 1470 azx_stream_clear(chip, azx_dev);
1471
d01ce99f
TI		 1472 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1473 SD_CTL_STREAM_RESET);
1da177e4
LT		 1474 udelay(3);
1475 timeout = 300;
1476 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1477 --timeout)
1478 ;
1479 val &= ~SD_CTL_STREAM_RESET;
1480 azx_sd_writeb(azx_dev, SD_CTL, val);
1481 udelay(3);
1482
1483 timeout = 300;
1484 /* waiting for hardware to report that the stream is out of reset */
1485 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1486 --timeout)
1487 ;
fa00e046
JK		 1488
1489 /* reset first position - may not be synced with hw at this time */
1490 *azx_dev->posbuf = 0;
1dddab40 1491}
1da177e4 1492
1dddab40
TI		 1493/*
1494 * set up the SD for streaming
1495 */
1496static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1497{
27fe48d9 1498 unsigned int val;
1dddab40
TI		 1499 /* make sure the run bit is zero for SD */
1500 azx_stream_clear(chip, azx_dev);
1da177e4 1501 /* program the stream_tag */
27fe48d9
TI		 1502 val = azx_sd_readl(azx_dev, SD_CTL);
1503 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1504 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1505 if (!azx_snoop(chip))
1506 val |= SD_CTL_TRAFFIC_PRIO;
1507 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1508
1509 /* program the length of samples in cyclic buffer */
1510 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1511
1512 /* program the stream format */
1513 /* this value needs to be the same as the one programmed */
1514 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1515
1516 /* program the stream LVI (last valid index) of the BDL */
1517 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1518
1519 /* program the BDL address */
1520 /* lower BDL address */
4ce107b9 1521 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1522 /* upper BDL address */
766979e0 1523 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1524
0be3b5d3 1525 /* enable the position buffer */
4cb36310
DH		 1526 if (chip->position_fix[0] != POS_FIX_LPIB ||
1527 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1528 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1529 azx_writel(chip, DPLBASE,
1530 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1531 }
c74db86b 1532
1da177e4 1533 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1534 azx_sd_writel(azx_dev, SD_CTL,
1535 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1536
1537 return 0;
1538}
1539
6ce4a3bc
TI		 1540/*
1541 * Probe the given codec address
1542 */
1543static int probe_codec(struct azx *chip, int addr)
1544{
1545 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1546 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1547 unsigned int res;
1548
a678cdee 1549 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1550 chip->probing = 1;
1551 azx_send_cmd(chip->bus, cmd);
deadff16 1552 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1553 chip->probing = 0;
a678cdee 1554 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1555 if (res == -1)
1556 return -EIO;
4abc1cc2 1557 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1558 return 0;
1559}
1560
33fa35ed
TI		 1561static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1562 struct hda_pcm *cpcm);
6ce4a3bc 1563static void azx_stop_chip(struct azx *chip);
1da177e4 1564
8dd78330
TI		 1565static void azx_bus_reset(struct hda_bus *bus)
1566{
1567 struct azx *chip = bus->private_data;
8dd78330
TI		 1568
1569 bus->in_reset = 1;
1570 azx_stop_chip(chip);
cd508fe5 1571 azx_init_chip(chip, 1);
65f75983 1572#ifdef CONFIG_PM
8dd78330 1573 if (chip->initialized) {
01b65bfb
TI		 1574 struct azx_pcm *p;
1575 list_for_each_entry(p, &chip->pcm_list, list)
1576 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1577 snd_hda_suspend(chip->bus);
1578 snd_hda_resume(chip->bus);
1579 }
65f75983 1580#endif
8dd78330
TI		 1581 bus->in_reset = 0;
1582}
1583
1da177e4
LT		 1584/*
1585 * Codec initialization
1586 */
1587
2f5983f2 1588/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
a82d51ed 1589static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
7445dfc1 1590 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1591 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1592};
1593
a82d51ed 1594static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1595{
1596 struct hda_bus_template bus_temp;
34c25350
TI		 1597 int c, codecs, err;
1598 int max_slots;
1da177e4
LT		 1599
1600 memset(&bus_temp, 0, sizeof(bus_temp));
1601 bus_temp.private_data = chip;
1602 bus_temp.modelname = model;
1603 bus_temp.pci = chip->pci;
111d3af5
TI		 1604 bus_temp.ops.command = azx_send_cmd;
1605 bus_temp.ops.get_response = azx_get_response;
176d5335 1606 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1607 bus_temp.ops.bus_reset = azx_bus_reset;
83012a7c 1608#ifdef CONFIG_PM
11cd41b8 1609 bus_temp.power_save = &power_save;
cb53c626
TI		 1610 bus_temp.ops.pm_notify = azx_power_notify;
1611#endif
1da177e4 1612
d01ce99f
TI		 1613 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1614 if (err < 0)
1da177e4
LT		 1615 return err;
1616
9477c58e
TI		 1617 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1618 snd_printd(SFX "Enable delay in RIRB handling\n");
dc9c8e21 1619 chip->bus->needs_damn_long_delay = 1;
9477c58e 1620 }
dc9c8e21 1621
34c25350 1622 codecs = 0;
2f5983f2
TI		 1623 max_slots = azx_max_codecs[chip->driver_type];
1624 if (!max_slots)
7445dfc1 1625 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1626
1627 /* First try to probe all given codec slots */
1628 for (c = 0; c < max_slots; c++) {
f1eaaeec 1629 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1630 if (probe_codec(chip, c) < 0) {
1631 /* Some BIOSen give you wrong codec addresses
1632 * that don't exist
1633 */
4abc1cc2
TI		 1634 snd_printk(KERN_WARNING SFX
1635 "Codec #%d probe error; "
6ce4a3bc
TI		 1636 "disabling it...\n", c);
1637 chip->codec_mask &= ~(1 << c);
1638 /* More badly, accessing to a non-existing
1639 * codec often screws up the controller chip,
2448158e 1640 * and disturbs the further communications.
6ce4a3bc
TI		 1641 * Thus if an error occurs during probing,
1642 * better to reset the controller chip to
1643 * get back to the sanity state.
1644 */
1645 azx_stop_chip(chip);
cd508fe5 1646 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1647 }
1648 }
1649 }
1650
d507cd66
TI		 1651 /* AMD chipsets often cause the communication stalls upon certain
1652 * sequence like the pin-detection. It seems that forcing the synced
1653 * access works around the stall. Grrr...
1654 */
9477c58e
TI		 1655 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1656 snd_printd(SFX "Enable sync_write for stable communication\n");
d507cd66
TI		 1657 chip->bus->sync_write = 1;
1658 chip->bus->allow_bus_reset = 1;
1659 }
1660
6ce4a3bc 1661 /* Then create codec instances */
34c25350 1662 for (c = 0; c < max_slots; c++) {
f1eaaeec 1663 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1664 struct hda_codec *codec;
a1e21c90 1665 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1666 if (err < 0)
1667 continue;
2dca0bba 1668 codec->beep_mode = chip->beep_mode;
1da177e4 1669 codecs++;
19a982b6
TI		 1670 }
1671 }
1672 if (!codecs) {
1da177e4
LT		 1673 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1674 return -ENXIO;
1675 }
a1e21c90
TI		 1676 return 0;
1677}
1da177e4 1678
a1e21c90
TI		 1679/* configure each codec instance */
1680static int __devinit azx_codec_configure(struct azx *chip)
1681{
1682 struct hda_codec *codec;
1683 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1684 snd_hda_codec_configure(codec);
1685 }
1da177e4
LT		 1686 return 0;
1687}
1688
1689
1690/*
1691 * PCM support
1692 */
1693
1694/* assign a stream for the PCM */
ef18bede
WF		 1695static inline struct azx_dev *
1696azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1697{
07e4ca50 1698 int dev, i, nums;
ef18bede 1699 struct azx_dev *res = NULL;
d5cf9911
TI		 1700 /* make a non-zero unique key for the substream */
1701 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1702 (substream->stream + 1);
ef18bede
WF		 1703
1704 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1705 dev = chip->playback_index_offset;
1706 nums = chip->playback_streams;
1707 } else {
1708 dev = chip->capture_index_offset;
1709 nums = chip->capture_streams;
1710 }
1711 for (i = 0; i < nums; i++, dev++)
d01ce99f 1712 if (!chip->azx_dev[dev].opened) {
ef18bede 1713 res = &chip->azx_dev[dev];
d5cf9911 1714 if (res->assigned_key == key)
ef18bede 1715 break;
1da177e4 1716 }
ef18bede
WF		 1717 if (res) {
1718 res->opened = 1;
d5cf9911 1719 res->assigned_key = key;
ef18bede
WF		 1720 }
1721 return res;
1da177e4
LT		 1722}
1723
1724/* release the assigned stream */
a98f90fd 1725static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1726{
1727 azx_dev->opened = 0;
1728}
1729
a98f90fd 1730static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1731 .info = (SNDRV_PCM_INFO_MMAP |
1732 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1733 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1734 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1735 /* No full-resume yet implemented */
1736 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1737 SNDRV_PCM_INFO_PAUSE |
7bb8fb70
CL		 1738 SNDRV_PCM_INFO_SYNC_START |
1739 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1740 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1741 .rates = SNDRV_PCM_RATE_48000,
1742 .rate_min = 48000,
1743 .rate_max = 48000,
1744 .channels_min = 2,
1745 .channels_max = 2,
1746 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1747 .period_bytes_min = 128,
1748 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1749 .periods_min = 2,
1750 .periods_max = AZX_MAX_FRAG,
1751 .fifo_size = 0,
1752};
1753
a98f90fd 1754static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1755{
1756 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1757 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1758 struct azx *chip = apcm->chip;
1759 struct azx_dev *azx_dev;
1760 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1761 unsigned long flags;
1762 int err;
2ae66c26 1763 int buff_step;
1da177e4 1764
62932df8 1765 mutex_lock(&chip->open_mutex);
ef18bede 1766 azx_dev = azx_assign_device(chip, substream);
1da177e4 1767 if (azx_dev == NULL) {
62932df8 1768 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1769 return -EBUSY;
1770 }
1771 runtime->hw = azx_pcm_hw;
1772 runtime->hw.channels_min = hinfo->channels_min;
1773 runtime->hw.channels_max = hinfo->channels_max;
1774 runtime->hw.formats = hinfo->formats;
1775 runtime->hw.rates = hinfo->rates;
1776 snd_pcm_limit_hw_rates(runtime);
1777 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
52409aa6 1778 if (chip->align_buffer_size)
2ae66c26
PLB		 1779 /* constrain buffer sizes to be multiple of 128
1780 bytes. This is more efficient in terms of memory
1781 access but isn't required by the HDA spec and
1782 prevents users from specifying exact period/buffer
1783 sizes. For example for 44.1kHz, a period size set
1784 to 20ms will be rounded to 19.59ms. */
1785 buff_step = 128;
1786 else
1787 /* Don't enforce steps on buffer sizes, still need to
1788 be multiple of 4 bytes (HDA spec). Tested on Intel
1789 HDA controllers, may not work on all devices where
1790 option needs to be disabled */
1791 buff_step = 4;
1792
5f1545bc 1793 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 1794 buff_step);
5f1545bc 1795 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 1796 buff_step);
b4a91cf0 1797 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 1798 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1799 if (err < 0) {
1da177e4 1800 azx_release_device(azx_dev);
cb53c626 1801 snd_hda_power_down(apcm->codec);
62932df8 1802 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1803 return err;
1804 }
70d321e6 1805 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1806 /* sanity check */
1807 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1808 snd_BUG_ON(!runtime->hw.channels_max) ||
1809 snd_BUG_ON(!runtime->hw.formats) ||
1810 snd_BUG_ON(!runtime->hw.rates)) {
1811 azx_release_device(azx_dev);
1812 hinfo->ops.close(hinfo, apcm->codec, substream);
1813 snd_hda_power_down(apcm->codec);
1814 mutex_unlock(&chip->open_mutex);
1815 return -EINVAL;
1816 }
1da177e4
LT		 1817 spin_lock_irqsave(&chip->reg_lock, flags);
1818 azx_dev->substream = substream;
1819 azx_dev->running = 0;
1820 spin_unlock_irqrestore(&chip->reg_lock, flags);
1821
1822 runtime->private_data = azx_dev;
850f0e52 1823 snd_pcm_set_sync(substream);
62932df8 1824 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1825 return 0;
1826}
1827
a98f90fd 1828static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1829{
1830 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1831 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1832 struct azx *chip = apcm->chip;
1833 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1834 unsigned long flags;
1835
62932df8 1836 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1837 spin_lock_irqsave(&chip->reg_lock, flags);
1838 azx_dev->substream = NULL;
1839 azx_dev->running = 0;
1840 spin_unlock_irqrestore(&chip->reg_lock, flags);
1841 azx_release_device(azx_dev);
1842 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1843 snd_hda_power_down(apcm->codec);
62932df8 1844 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1845 return 0;
1846}
1847
d01ce99f
TI		 1848static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1849 struct snd_pcm_hw_params *hw_params)
1da177e4 1850{
27fe48d9
TI		 1851 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1852 struct azx *chip = apcm->chip;
1853 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94 1854 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 1855 int ret;
97b71c94 1856
27fe48d9 1857 mark_runtime_wc(chip, azx_dev, runtime, false);
97b71c94
TI		 1858 azx_dev->bufsize = 0;
1859 azx_dev->period_bytes = 0;
1860 azx_dev->format_val = 0;
27fe48d9 1861 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 1862 params_buffer_bytes(hw_params));
27fe48d9
TI		 1863 if (ret < 0)
1864 return ret;
1865 mark_runtime_wc(chip, azx_dev, runtime, true);
1866 return ret;
1da177e4
LT		 1867}
1868
a98f90fd 1869static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1870{
1871 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1872 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9
TI		 1873 struct azx *chip = apcm->chip;
1874 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1875 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1876
1877 /* reset BDL address */
1878 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1879 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1880 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1881 azx_dev->bufsize = 0;
1882 azx_dev->period_bytes = 0;
1883 azx_dev->format_val = 0;
1da177e4 1884
eb541337 1885 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 1886
27fe48d9 1887 mark_runtime_wc(chip, azx_dev, runtime, false);
1da177e4
LT		 1888 return snd_pcm_lib_free_pages(substream);
1889}
1890
a98f90fd 1891static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1892{
1893 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1894 struct azx *chip = apcm->chip;
1895 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 1896 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 1897 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 1898 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 1899 int err;
7c935976
SW		 1900 struct hda_spdif_out *spdif =
1901 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1902 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 1903
fa00e046 1904 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 1905 format_val = snd_hda_calc_stream_format(runtime->rate,
1906 runtime->channels,
1907 runtime->format,
32c168c8 1908 hinfo->maxbps,
7c935976 1909 ctls);
97b71c94 1910 if (!format_val) {
d01ce99f
TI		 1911 snd_printk(KERN_ERR SFX
1912 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 1913 runtime->rate, runtime->channels, runtime->format);
1914 return -EINVAL;
1915 }
1916
97b71c94
TI		 1917 bufsize = snd_pcm_lib_buffer_bytes(substream);
1918 period_bytes = snd_pcm_lib_period_bytes(substream);
1919
4abc1cc2 1920 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 1921 bufsize, format_val);
1922
1923 if (bufsize != azx_dev->bufsize ||
1924 period_bytes != azx_dev->period_bytes ||
915bf29e
TI		 1925 format_val != azx_dev->format_val ||
1926 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
97b71c94
TI		 1927 azx_dev->bufsize = bufsize;
1928 azx_dev->period_bytes = period_bytes;
1929 azx_dev->format_val = format_val;
915bf29e 1930 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
97b71c94
TI		 1931 err = azx_setup_periods(chip, substream, azx_dev);
1932 if (err < 0)
1933 return err;
1934 }
1935
e5463720
JK		 1936 /* wallclk has 24Mhz clock source */
1937 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1938 runtime->rate) * 1000);
1da177e4
LT		 1939 azx_setup_controller(chip, azx_dev);
1940 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1941 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1942 else
1943 azx_dev->fifo_size = 0;
1944
62b7e5e0
TI		 1945 stream_tag = azx_dev->stream_tag;
1946 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 1947 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 1948 stream_tag > chip->capture_streams)
1949 stream_tag -= chip->capture_streams;
1950 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 1951 azx_dev->format_val, substream);
1da177e4
LT		 1952}
1953
a98f90fd 1954static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 1955{
1956 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1957 struct azx *chip = apcm->chip;
850f0e52
TI		 1958 struct azx_dev *azx_dev;
1959 struct snd_pcm_substream *s;
fa00e046 1960 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 1961 int nwait, timeout;
1da177e4 1962
1da177e4 1963 switch (cmd) {
fa00e046
JK		 1964 case SNDRV_PCM_TRIGGER_START:
1965 rstart = 1;
1da177e4
LT		 1966 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1967 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 1968 start = 1;
1da177e4
LT		 1969 break;
1970 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 1971 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 1972 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 1973 start = 0;
1da177e4
LT		 1974 break;
1975 default:
850f0e52
TI		 1976 return -EINVAL;
1977 }
1978
1979 snd_pcm_group_for_each_entry(s, substream) {
1980 if (s->pcm->card != substream->pcm->card)
1981 continue;
1982 azx_dev = get_azx_dev(s);
1983 sbits |= 1 << azx_dev->index;
1984 nsync++;
1985 snd_pcm_trigger_done(s, substream);
1986 }
1987
1988 spin_lock(&chip->reg_lock);
172d3b20
PLB		 1989
1990 /* first, set SYNC bits of corresponding streams */
1991 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1992 azx_writel(chip, OLD_SSYNC,
1993 azx_readl(chip, OLD_SSYNC) | sbits);
1994 else
1995 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1996
850f0e52
TI		 1997 snd_pcm_group_for_each_entry(s, substream) {
1998 if (s->pcm->card != substream->pcm->card)
1999 continue;
2000 azx_dev = get_azx_dev(s);
e5463720
JK		 2001 if (start) {
2002 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2003 if (!rstart)
2004 azx_dev->start_wallclk -=
2005 azx_dev->period_wallclk;
850f0e52 2006 azx_stream_start(chip, azx_dev);
e5463720 2007 } else {
850f0e52 2008 azx_stream_stop(chip, azx_dev);
e5463720 2009 }
850f0e52 2010 azx_dev->running = start;
1da177e4
LT		 2011 }
2012 spin_unlock(&chip->reg_lock);
850f0e52 2013 if (start) {
850f0e52
TI		 2014 /* wait until all FIFOs get ready */
2015 for (timeout = 5000; timeout; timeout--) {
2016 nwait = 0;
2017 snd_pcm_group_for_each_entry(s, substream) {
2018 if (s->pcm->card != substream->pcm->card)
2019 continue;
2020 azx_dev = get_azx_dev(s);
2021 if (!(azx_sd_readb(azx_dev, SD_STS) &
2022 SD_STS_FIFO_READY))
2023 nwait++;
2024 }
2025 if (!nwait)
2026 break;
2027 cpu_relax();
2028 }
2029 } else {
2030 /* wait until all RUN bits are cleared */
2031 for (timeout = 5000; timeout; timeout--) {
2032 nwait = 0;
2033 snd_pcm_group_for_each_entry(s, substream) {
2034 if (s->pcm->card != substream->pcm->card)
2035 continue;
2036 azx_dev = get_azx_dev(s);
2037 if (azx_sd_readb(azx_dev, SD_CTL) &
2038 SD_CTL_DMA_START)
2039 nwait++;
2040 }
2041 if (!nwait)
2042 break;
2043 cpu_relax();
2044 }
1da177e4 2045 }
172d3b20
PLB		 2046 spin_lock(&chip->reg_lock);
2047 /* reset SYNC bits */
2048 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2049 azx_writel(chip, OLD_SSYNC,
2050 azx_readl(chip, OLD_SSYNC) & ~sbits);
2051 else
2052 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2053 spin_unlock(&chip->reg_lock);
850f0e52 2054 return 0;
1da177e4
LT		 2055}
2056
0e153474
JC		 2057/* get the current DMA position with correction on VIA chips */
2058static unsigned int azx_via_get_position(struct azx *chip,
2059 struct azx_dev *azx_dev)
2060{
2061 unsigned int link_pos, mini_pos, bound_pos;
2062 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2063 unsigned int fifo_size;
2064
2065 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2066 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2067 /* Playback, no problem using link position */
2068 return link_pos;
2069 }
2070
2071 /* Capture */
2072 /* For new chipset,
2073 * use mod to get the DMA position just like old chipset
2074 */
2075 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2076 mod_dma_pos %= azx_dev->period_bytes;
2077
2078 /* azx_dev->fifo_size can't get FIFO size of in stream.
2079 * Get from base address + offset.
2080 */
2081 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2082
2083 if (azx_dev->insufficient) {
2084 /* Link position never gather than FIFO size */
2085 if (link_pos <= fifo_size)
2086 return 0;
2087
2088 azx_dev->insufficient = 0;
2089 }
2090
2091 if (link_pos <= fifo_size)
2092 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2093 else
2094 mini_pos = link_pos - fifo_size;
2095
2096 /* Find nearest previous boudary */
2097 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2098 mod_link_pos = link_pos % azx_dev->period_bytes;
2099 if (mod_link_pos >= fifo_size)
2100 bound_pos = link_pos - mod_link_pos;
2101 else if (mod_dma_pos >= mod_mini_pos)
2102 bound_pos = mini_pos - mod_mini_pos;
2103 else {
2104 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2105 if (bound_pos >= azx_dev->bufsize)
2106 bound_pos = 0;
2107 }
2108
2109 /* Calculate real DMA position we want */
2110 return bound_pos + mod_dma_pos;
2111}
2112
9ad593f6 2113static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2114 struct azx_dev *azx_dev,
2115 bool with_check)
1da177e4 2116{
1da177e4 2117 unsigned int pos;
4cb36310 2118 int stream = azx_dev->substream->stream;
1da177e4 2119
4cb36310
DH		 2120 switch (chip->position_fix[stream]) {
2121 case POS_FIX_LPIB:
2122 /* read LPIB */
2123 pos = azx_sd_readl(azx_dev, SD_LPIB);
2124 break;
2125 case POS_FIX_VIACOMBO:
0e153474 2126 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2127 break;
2128 default:
2129 /* use the position buffer */
2130 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2131 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2132 if (!pos || pos == (u32)-1) {
2133 printk(KERN_WARNING
2134 "hda-intel: Invalid position buffer, "
2135 "using LPIB read method instead.\n");
2136 chip->position_fix[stream] = POS_FIX_LPIB;
2137 pos = azx_sd_readl(azx_dev, SD_LPIB);
2138 } else
2139 chip->position_fix[stream] = POS_FIX_POSBUF;
2140 }
2141 break;
c74db86b 2142 }
4cb36310 2143
1da177e4
LT		 2144 if (pos >= azx_dev->bufsize)
2145 pos = 0;
90accc58
PLB		 2146
2147 /* calculate runtime delay from LPIB */
2148 if (azx_dev->substream->runtime &&
2149 chip->position_fix[stream] == POS_FIX_POSBUF &&
2150 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2151 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2152 int delay;
2153 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2154 delay = pos - lpib_pos;
2155 else
2156 delay = lpib_pos - pos;
2157 if (delay < 0)
2158 delay += azx_dev->bufsize;
2159 if (delay >= azx_dev->period_bytes) {
2160 snd_printdd("delay %d > period_bytes %d\n",
2161 delay, azx_dev->period_bytes);
2162 delay = 0; /* something is wrong */
2163 }
2164 azx_dev->substream->runtime->delay =
2165 bytes_to_frames(azx_dev->substream->runtime, delay);
2166 }
9ad593f6
TI		 2167 return pos;
2168}
2169
2170static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2171{
2172 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2173 struct azx *chip = apcm->chip;
2174 struct azx_dev *azx_dev = get_azx_dev(substream);
2175 return bytes_to_frames(substream->runtime,
798cb7e8 2176 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2177}
2178
2179/*
2180 * Check whether the current DMA position is acceptable for updating
2181 * periods. Returns non-zero if it's OK.
2182 *
2183 * Many HD-audio controllers appear pretty inaccurate about
2184 * the update-IRQ timing. The IRQ is issued before actually the
2185 * data is processed. So, we need to process it afterwords in a
2186 * workqueue.
2187 */
2188static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2189{
e5463720 2190 u32 wallclk;
9ad593f6 2191 unsigned int pos;
beaffc39 2192 int stream;
9ad593f6 2193
f48f606d
JK		 2194 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2195 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2196 return -1; /* bogus (too early) interrupt */
fa00e046 2197
beaffc39 2198 stream = azx_dev->substream->stream;
798cb7e8 2199 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2200
d6d8bf54
TI		 2201 if (WARN_ONCE(!azx_dev->period_bytes,
2202 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2203 return -1; /* this shouldn't happen! */
edb39935 2204 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2205 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2206 /* NG - it's below the first next period boundary */
2207 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2208 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2209 return 1; /* OK, it's fine */
2210}
2211
2212/*
2213 * The work for pending PCM period updates.
2214 */
2215static void azx_irq_pending_work(struct work_struct *work)
2216{
2217 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2218 int i, pending, ok;
9ad593f6 2219
a6a950a8
TI		 2220 if (!chip->irq_pending_warned) {
2221 printk(KERN_WARNING
2222 "hda-intel: IRQ timing workaround is activated "
2223 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2224 chip->card->number);
2225 chip->irq_pending_warned = 1;
2226 }
2227
9ad593f6
TI		 2228 for (;;) {
2229 pending = 0;
2230 spin_lock_irq(&chip->reg_lock);
2231 for (i = 0; i < chip->num_streams; i++) {
2232 struct azx_dev *azx_dev = &chip->azx_dev[i];
2233 if (!azx_dev->irq_pending ||
2234 !azx_dev->substream ||
2235 !azx_dev->running)
2236 continue;
e5463720
JK		 2237 ok = azx_position_ok(chip, azx_dev);
2238 if (ok > 0) {
9ad593f6
TI		 2239 azx_dev->irq_pending = 0;
2240 spin_unlock(&chip->reg_lock);
2241 snd_pcm_period_elapsed(azx_dev->substream);
2242 spin_lock(&chip->reg_lock);
e5463720
JK		 2243 } else if (ok < 0) {
2244 pending = 0; /* too early */
9ad593f6
TI		 2245 } else
2246 pending++;
2247 }
2248 spin_unlock_irq(&chip->reg_lock);
2249 if (!pending)
2250 return;
08af495f 2251 msleep(1);
9ad593f6
TI		 2252 }
2253}
2254
2255/* clear irq_pending flags and assure no on-going workq */
2256static void azx_clear_irq_pending(struct azx *chip)
2257{
2258 int i;
2259
2260 spin_lock_irq(&chip->reg_lock);
2261 for (i = 0; i < chip->num_streams; i++)
2262 chip->azx_dev[i].irq_pending = 0;
2263 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2264}
2265
27fe48d9
TI		 2266#ifdef CONFIG_X86
2267static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2268 struct vm_area_struct *area)
2269{
2270 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2271 struct azx *chip = apcm->chip;
2272 if (!azx_snoop(chip))
2273 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2274 return snd_pcm_lib_default_mmap(substream, area);
2275}
2276#else
2277#define azx_pcm_mmap NULL
2278#endif
2279
a98f90fd 2280static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2281 .open = azx_pcm_open,
2282 .close = azx_pcm_close,
2283 .ioctl = snd_pcm_lib_ioctl,
2284 .hw_params = azx_pcm_hw_params,
2285 .hw_free = azx_pcm_hw_free,
2286 .prepare = azx_pcm_prepare,
2287 .trigger = azx_pcm_trigger,
2288 .pointer = azx_pcm_pointer,
27fe48d9 2289 .mmap = azx_pcm_mmap,
4ce107b9 2290 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2291};
2292
a98f90fd 2293static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2294{
176d5335
TI		 2295 struct azx_pcm *apcm = pcm->private_data;
2296 if (apcm) {
01b65bfb 2297 list_del(&apcm->list);
176d5335
TI		 2298 kfree(apcm);
2299 }
1da177e4
LT		 2300}
2301
acfa634f
TI		 2302#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2303
176d5335 2304static int
33fa35ed
TI		 2305azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2306 struct hda_pcm *cpcm)
1da177e4 2307{
33fa35ed 2308 struct azx *chip = bus->private_data;
a98f90fd 2309 struct snd_pcm *pcm;
1da177e4 2310 struct azx_pcm *apcm;
176d5335 2311 int pcm_dev = cpcm->device;
acfa634f 2312 unsigned int size;
176d5335 2313 int s, err;
1da177e4 2314
01b65bfb
TI		 2315 list_for_each_entry(apcm, &chip->pcm_list, list) {
2316 if (apcm->pcm->device == pcm_dev) {
2317 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2318 return -EBUSY;
2319 }
176d5335
TI		 2320 }
2321 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2322 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2323 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2324 &pcm);
2325 if (err < 0)
2326 return err;
18cb7109 2327 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2328 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2329 if (apcm == NULL)
2330 return -ENOMEM;
2331 apcm->chip = chip;
01b65bfb 2332 apcm->pcm = pcm;
1da177e4 2333 apcm->codec = codec;
1da177e4
LT		 2334 pcm->private_data = apcm;
2335 pcm->private_free = azx_pcm_free;
176d5335
TI		 2336 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2337 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2338 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2339 cpcm->pcm = pcm;
2340 for (s = 0; s < 2; s++) {
2341 apcm->hinfo[s] = &cpcm->stream[s];
2342 if (cpcm->stream[s].substreams)
2343 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2344 }
2345 /* buffer pre-allocation */
acfa634f
TI		 2346 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2347 if (size > MAX_PREALLOC_SIZE)
2348 size = MAX_PREALLOC_SIZE;
4ce107b9 2349 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2350 snd_dma_pci_data(chip->pci),
acfa634f 2351 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2352 return 0;
2353}
2354
2355/*
2356 * mixer creation - all stuff is implemented in hda module
2357 */
a98f90fd 2358static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2359{
2360 return snd_hda_build_controls(chip->bus);
2361}
2362
2363
2364/*
2365 * initialize SD streams
2366 */
a98f90fd 2367static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2368{
2369 int i;
2370
2371 /* initialize each stream (aka device)
d01ce99f
TI		 2372 * assign the starting bdl address to each stream (device)
2373 * and initialize
1da177e4 2374 */
07e4ca50 2375 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2376 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2377 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2378 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2379 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2380 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2381 azx_dev->sd_int_sta_mask = 1 << i;
2382 /* stream tag: must be non-zero and unique */
2383 azx_dev->index = i;
2384 azx_dev->stream_tag = i + 1;
2385 }
2386
2387 return 0;
2388}
2389
68e7fffc
TI		 2390static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2391{
437a5a46
TI		 2392 if (request_irq(chip->pci->irq, azx_interrupt,
2393 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2394 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2395 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2396 "disabling device\n", chip->pci->irq);
2397 if (do_disconnect)
2398 snd_card_disconnect(chip->card);
2399 return -1;
2400 }
2401 chip->irq = chip->pci->irq;
69e13418 2402 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2403 return 0;
2404}
2405
1da177e4 2406
cb53c626
TI		 2407static void azx_stop_chip(struct azx *chip)
2408{
95e99fda 2409 if (!chip->initialized)
cb53c626
TI		 2410 return;
2411
2412 /* disable interrupts */
2413 azx_int_disable(chip);
2414 azx_int_clear(chip);
2415
2416 /* disable CORB/RIRB */
2417 azx_free_cmd_io(chip);
2418
2419 /* disable position buffer */
2420 azx_writel(chip, DPLBASE, 0);
2421 azx_writel(chip, DPUBASE, 0);
2422
2423 chip->initialized = 0;
2424}
2425
83012a7c 2426#ifdef CONFIG_PM
cb53c626 2427/* power-up/down the controller */
68467f51 2428static void azx_power_notify(struct hda_bus *bus, bool power_up)
cb53c626 2429{
33fa35ed 2430 struct azx *chip = bus->private_data;
cb53c626 2431
68467f51 2432 if (power_up)
b8dfc462
ML		 2433 pm_runtime_get_sync(&chip->pci->dev);
2434 else
2435 pm_runtime_put_sync(&chip->pci->dev);
cb53c626 2436}
65fcd41d
TI		 2437
2438static DEFINE_MUTEX(card_list_lock);
2439static LIST_HEAD(card_list);
2440
2441static void azx_add_card_list(struct azx *chip)
2442{
2443 mutex_lock(&card_list_lock);
2444 list_add(&chip->list, &card_list);
2445 mutex_unlock(&card_list_lock);
2446}
2447
2448static void azx_del_card_list(struct azx *chip)
2449{
2450 mutex_lock(&card_list_lock);
2451 list_del_init(&chip->list);
2452 mutex_unlock(&card_list_lock);
2453}
2454
2455/* trigger power-save check at writing parameter */
2456static int param_set_xint(const char *val, const struct kernel_param *kp)
2457{
2458 struct azx *chip;
2459 struct hda_codec *c;
2460 int prev = power_save;
2461 int ret = param_set_int(val, kp);
2462
2463 if (ret || prev == power_save)
2464 return ret;
2465
2466 mutex_lock(&card_list_lock);
2467 list_for_each_entry(chip, &card_list, list) {
2468 if (!chip->bus || chip->disabled)
2469 continue;
2470 list_for_each_entry(c, &chip->bus->codec_list, list)
2471 snd_hda_power_sync(c);
2472 }
2473 mutex_unlock(&card_list_lock);
2474 return 0;
2475}
2476#else
2477#define azx_add_card_list(chip) /* NOP */
2478#define azx_del_card_list(chip) /* NOP */
83012a7c 2479#endif /* CONFIG_PM */
5c0b9bec 2480
7ccbde57 2481#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 2482/*
2483 * power management
2484 */
68cb2b55 2485static int azx_suspend(struct device *dev)
1da177e4 2486{
68cb2b55
TI		 2487 struct pci_dev *pci = to_pci_dev(dev);
2488 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2489 struct azx *chip = card->private_data;
01b65bfb 2490 struct azx_pcm *p;
1da177e4 2491
421a1252 2492 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2493 azx_clear_irq_pending(chip);
01b65bfb
TI		 2494 list_for_each_entry(p, &chip->pcm_list, list)
2495 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2496 if (chip->initialized)
8dd78330 2497 snd_hda_suspend(chip->bus);
cb53c626 2498 azx_stop_chip(chip);
30b35399 2499 if (chip->irq >= 0) {
43001c95 2500 free_irq(chip->irq, chip);
30b35399
TI		 2501 chip->irq = -1;
2502 }
68e7fffc 2503 if (chip->msi)
43001c95 2504 pci_disable_msi(chip->pci);
421a1252
TI		 2505 pci_disable_device(pci);
2506 pci_save_state(pci);
68cb2b55 2507 pci_set_power_state(pci, PCI_D3hot);
1da177e4
LT		 2508 return 0;
2509}
2510
68cb2b55 2511static int azx_resume(struct device *dev)
1da177e4 2512{
68cb2b55
TI		 2513 struct pci_dev *pci = to_pci_dev(dev);
2514 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2515 struct azx *chip = card->private_data;
1da177e4 2516
d14a7e0b
TI		 2517 pci_set_power_state(pci, PCI_D0);
2518 pci_restore_state(pci);
30b35399
TI		 2519 if (pci_enable_device(pci) < 0) {
2520 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2521 "disabling device\n");
2522 snd_card_disconnect(card);
2523 return -EIO;
2524 }
2525 pci_set_master(pci);
68e7fffc
TI		 2526 if (chip->msi)
2527 if (pci_enable_msi(pci) < 0)
2528 chip->msi = 0;
2529 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2530 return -EIO;
cb53c626 2531 azx_init_pci(chip);
d804ad92 2532
7f30830b 2533 azx_init_chip(chip, 1);
d804ad92 2534
1da177e4 2535 snd_hda_resume(chip->bus);
421a1252 2536 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2537 return 0;
2538}
b8dfc462
ML		 2539#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2540
2541#ifdef CONFIG_PM_RUNTIME
2542static int azx_runtime_suspend(struct device *dev)
2543{
2544 struct snd_card *card = dev_get_drvdata(dev);
2545 struct azx *chip = card->private_data;
2546
2547 if (!power_save_controller)
2548 return -EAGAIN;
2549
2550 azx_stop_chip(chip);
2551 azx_clear_irq_pending(chip);
2552 return 0;
2553}
2554
2555static int azx_runtime_resume(struct device *dev)
2556{
2557 struct snd_card *card = dev_get_drvdata(dev);
2558 struct azx *chip = card->private_data;
2559
2560 azx_init_pci(chip);
2561 azx_init_chip(chip, 1);
2562 return 0;
2563}
2564#endif /* CONFIG_PM_RUNTIME */
2565
2566#ifdef CONFIG_PM
2567static const struct dev_pm_ops azx_pm = {
2568 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2569 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, NULL)
2570};
2571
68cb2b55
TI		 2572#define AZX_PM_OPS &azx_pm
2573#else
68cb2b55 2574#define AZX_PM_OPS NULL
b8dfc462 2575#endif /* CONFIG_PM */
1da177e4
LT		 2576
2577
0cbf0098
TI		 2578/*
2579 * reboot notifier for hang-up problem at power-down
2580 */
2581static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2582{
2583 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2584 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2585 azx_stop_chip(chip);
2586 return NOTIFY_OK;
2587}
2588
2589static void azx_notifier_register(struct azx *chip)
2590{
2591 chip->reboot_notifier.notifier_call = azx_halt;
2592 register_reboot_notifier(&chip->reboot_notifier);
2593}
2594
2595static void azx_notifier_unregister(struct azx *chip)
2596{
2597 if (chip->reboot_notifier.notifier_call)
2598 unregister_reboot_notifier(&chip->reboot_notifier);
2599}
2600
a82d51ed
TI		 2601static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2602static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2603
8393ec4a 2604#ifdef SUPPORT_VGA_SWITCHEROO
a82d51ed
TI		 2605static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2606
a82d51ed
TI		 2607static void azx_vs_set_state(struct pci_dev *pci,
2608 enum vga_switcheroo_state state)
2609{
2610 struct snd_card *card = pci_get_drvdata(pci);
2611 struct azx *chip = card->private_data;
2612 bool disabled;
2613
2614 if (chip->init_failed)
2615 return;
2616
2617 disabled = (state == VGA_SWITCHEROO_OFF);
2618 if (chip->disabled == disabled)
2619 return;
2620
2621 if (!chip->bus) {
2622 chip->disabled = disabled;
2623 if (!disabled) {
2624 snd_printk(KERN_INFO SFX
2625 "%s: Start delayed initialization\n",
2626 pci_name(chip->pci));
2627 if (azx_first_init(chip) < 0 ||
2628 azx_probe_continue(chip) < 0) {
2629 snd_printk(KERN_ERR SFX
2630 "%s: initialization error\n",
2631 pci_name(chip->pci));
2632 chip->init_failed = true;
2633 }
2634 }
2635 } else {
2636 snd_printk(KERN_INFO SFX
2637 "%s %s via VGA-switcheroo\n",
2638 disabled ? "Disabling" : "Enabling",
2639 pci_name(chip->pci));
2640 if (disabled) {
68cb2b55 2641 azx_suspend(&pci->dev);
a82d51ed
TI		 2642 chip->disabled = true;
2643 snd_hda_lock_devices(chip->bus);
2644 } else {
2645 snd_hda_unlock_devices(chip->bus);
2646 chip->disabled = false;
68cb2b55 2647 azx_resume(&pci->dev);
a82d51ed
TI		 2648 }
2649 }
2650}
2651
2652static bool azx_vs_can_switch(struct pci_dev *pci)
2653{
2654 struct snd_card *card = pci_get_drvdata(pci);
2655 struct azx *chip = card->private_data;
2656
2657 if (chip->init_failed)
2658 return false;
2659 if (chip->disabled || !chip->bus)
2660 return true;
2661 if (snd_hda_lock_devices(chip->bus))
2662 return false;
2663 snd_hda_unlock_devices(chip->bus);
2664 return true;
2665}
2666
2667static void __devinit init_vga_switcheroo(struct azx *chip)
2668{
2669 struct pci_dev *p = get_bound_vga(chip->pci);
2670 if (p) {
2671 snd_printk(KERN_INFO SFX
2672 "%s: Handle VGA-switcheroo audio client\n",
2673 pci_name(chip->pci));
2674 chip->use_vga_switcheroo = 1;
2675 pci_dev_put(p);
2676 }
2677}
2678
2679static const struct vga_switcheroo_client_ops azx_vs_ops = {
2680 .set_gpu_state = azx_vs_set_state,
2681 .can_switch = azx_vs_can_switch,
2682};
2683
2684static int __devinit register_vga_switcheroo(struct azx *chip)
2685{
2686 if (!chip->use_vga_switcheroo)
2687 return 0;
2688 /* FIXME: currently only handling DIS controller
2689 * is there any machine with two switchable HDMI audio controllers?
2690 */
2691 return vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2692 VGA_SWITCHEROO_DIS,
2693 chip->bus != NULL);
2694}
2695#else
2696#define init_vga_switcheroo(chip) /* NOP */
2697#define register_vga_switcheroo(chip) 0
8393ec4a 2698#define check_hdmi_disabled(pci) false
a82d51ed
TI		 2699#endif /* SUPPORT_VGA_SWITCHER */
2700
1da177e4
LT		 2701/*
2702 * destructor
2703 */
a98f90fd 2704static int azx_free(struct azx *chip)
1da177e4 2705{
4ce107b9
TI		 2706 int i;
2707
65fcd41d
TI		 2708 azx_del_card_list(chip);
2709
0cbf0098
TI		 2710 azx_notifier_unregister(chip);
2711
a82d51ed
TI		 2712 if (use_vga_switcheroo(chip)) {
2713 if (chip->disabled && chip->bus)
2714 snd_hda_unlock_devices(chip->bus);
2715 vga_switcheroo_unregister_client(chip->pci);
2716 }
2717
ce43fbae 2718 if (chip->initialized) {
9ad593f6 2719 azx_clear_irq_pending(chip);
07e4ca50 2720 for (i = 0; i < chip->num_streams; i++)
1da177e4 2721 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2722 azx_stop_chip(chip);
1da177e4
LT		 2723 }
2724
f000fd80 2725 if (chip->irq >= 0)
1da177e4 2726 free_irq(chip->irq, (void*)chip);
68e7fffc 2727 if (chip->msi)
30b35399 2728 pci_disable_msi(chip->pci);
f079c25a
TI		 2729 if (chip->remap_addr)
2730 iounmap(chip->remap_addr);
1da177e4 2731
4ce107b9
TI		 2732 if (chip->azx_dev) {
2733 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 2734 if (chip->azx_dev[i].bdl.area) {
2735 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 2736 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 2737 }
4ce107b9 2738 }
27fe48d9
TI		 2739 if (chip->rb.area) {
2740 mark_pages_wc(chip, &chip->rb, false);
1da177e4 2741 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 2742 }
2743 if (chip->posbuf.area) {
2744 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 2745 snd_dma_free_pages(&chip->posbuf);
27fe48d9 2746 }
a82d51ed
TI		 2747 if (chip->region_requested)
2748 pci_release_regions(chip->pci);
1da177e4 2749 pci_disable_device(chip->pci);
07e4ca50 2750 kfree(chip->azx_dev);
4918cdab
TI		 2751#ifdef CONFIG_SND_HDA_PATCH_LOADER
2752 if (chip->fw)
2753 release_firmware(chip->fw);
2754#endif
1da177e4
LT		 2755 kfree(chip);
2756
2757 return 0;
2758}
2759
a98f90fd 2760static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2761{
2762 return azx_free(device->device_data);
2763}
2764
8393ec4a 2765#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 2766/*
2767 * Check of disabled HDMI controller by vga-switcheroo
2768 */
2769static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2770{
2771 struct pci_dev *p;
2772
2773 /* check only discrete GPU */
2774 switch (pci->vendor) {
2775 case PCI_VENDOR_ID_ATI:
2776 case PCI_VENDOR_ID_AMD:
2777 case PCI_VENDOR_ID_NVIDIA:
2778 if (pci->devfn == 1) {
2779 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2780 pci->bus->number, 0);
2781 if (p) {
2782 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2783 return p;
2784 pci_dev_put(p);
2785 }
2786 }
2787 break;
2788 }
2789 return NULL;
2790}
2791
2792static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2793{
2794 bool vga_inactive = false;
2795 struct pci_dev *p = get_bound_vga(pci);
2796
2797 if (p) {
12b78a7f 2798 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 2799 vga_inactive = true;
2800 pci_dev_put(p);
2801 }
2802 return vga_inactive;
2803}
8393ec4a 2804#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 2805
3372a153
TI		 2806/*
2807 * white/black-listing for position_fix
2808 */
623ec047 2809static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2810 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2811 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2812 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2813 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 2814 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 2815 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 2816 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 2817 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 2818 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 2819 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2820 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 2821 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 2822 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 2823 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 2824 {}
2825};
2826
2827static int __devinit check_position_fix(struct azx *chip, int fix)
2828{
2829 const struct snd_pci_quirk *q;
2830
c673ba1c 2831 switch (fix) {
1dac6695 2832 case POS_FIX_AUTO:
c673ba1c
TI		 2833 case POS_FIX_LPIB:
2834 case POS_FIX_POSBUF:
4cb36310 2835 case POS_FIX_VIACOMBO:
a6f2fd55 2836 case POS_FIX_COMBO:
c673ba1c
TI		 2837 return fix;
2838 }
2839
c673ba1c
TI		 2840 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2841 if (q) {
2842 printk(KERN_INFO
2843 "hda_intel: position_fix set to %d "
2844 "for device %04x:%04x\n",
2845 q->value, q->subvendor, q->subdevice);
2846 return q->value;
3372a153 2847 }
bdd9ef24
DH		 2848
2849 /* Check VIA/ATI HD Audio Controller exist */
9477c58e
TI		 2850 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2851 snd_printd(SFX "Using VIACOMBO position fix\n");
bdd9ef24 2852 return POS_FIX_VIACOMBO;
9477c58e
TI		 2853 }
2854 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2855 snd_printd(SFX "Using LPIB position fix\n");
50e3bbf9 2856 return POS_FIX_LPIB;
bdd9ef24 2857 }
c673ba1c 2858 return POS_FIX_AUTO;
3372a153
TI		 2859}
2860
669ba27a
TI		 2861/*
2862 * black-lists for probe_mask
2863 */
2864static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2865 /* Thinkpad often breaks the controller communication when accessing
2866 * to the non-working (or non-existing) modem codec slot.
2867 */
2868 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2869 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2870 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 2871 /* broken BIOS */
2872 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 2873 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2874 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 2875 /* forced codec slots */
93574844 2876 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 2877 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 2878 /* WinFast VP200 H (Teradici) user reported broken communication */
2879 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 2880 {}
2881};
2882
f1eaaeec
TI		 2883#define AZX_FORCE_CODEC_MASK 0x100
2884
5aba4f8e 2885static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 2886{
2887 const struct snd_pci_quirk *q;
2888
f1eaaeec
TI		 2889 chip->codec_probe_mask = probe_mask[dev];
2890 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 2891 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2892 if (q) {
2893 printk(KERN_INFO
2894 "hda_intel: probe_mask set to 0x%x "
2895 "for device %04x:%04x\n",
2896 q->value, q->subvendor, q->subdevice);
f1eaaeec 2897 chip->codec_probe_mask = q->value;
669ba27a
TI		 2898 }
2899 }
f1eaaeec
TI		 2900
2901 /* check forced option */
2902 if (chip->codec_probe_mask != -1 &&
2903 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2904 chip->codec_mask = chip->codec_probe_mask & 0xff;
2905 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2906 chip->codec_mask);
2907 }
669ba27a
TI		 2908}
2909
4d8e22e0 2910/*
71623855 2911 * white/black-list for enable_msi
4d8e22e0 2912 */
71623855 2913static struct snd_pci_quirk msi_black_list[] __devinitdata = {
9dc8398b 2914 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 2915 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 2916 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 2917 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 2918 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 2919 {}
2920};
2921
2922static void __devinit check_msi(struct azx *chip)
2923{
2924 const struct snd_pci_quirk *q;
2925
71623855
TI		 2926 if (enable_msi >= 0) {
2927 chip->msi = !!enable_msi;
4d8e22e0 2928 return;
71623855
TI		 2929 }
2930 chip->msi = 1; /* enable MSI as default */
2931 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 2932 if (q) {
2933 printk(KERN_INFO
2934 "hda_intel: msi for device %04x:%04x set to %d\n",
2935 q->subvendor, q->subdevice, q->value);
2936 chip->msi = q->value;
80c43ed7
TI		 2937 return;
2938 }
2939
2940 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 2941 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2942 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 2943 chip->msi = 0;
4d8e22e0
TI		 2944 }
2945}
2946
a1585d76
TI		 2947/* check the snoop mode availability */
2948static void __devinit azx_check_snoop_available(struct azx *chip)
2949{
2950 bool snoop = chip->snoop;
2951
2952 switch (chip->driver_type) {
2953 case AZX_DRIVER_VIA:
2954 /* force to non-snoop mode for a new VIA controller
2955 * when BIOS is set
2956 */
2957 if (snoop) {
2958 u8 val;
2959 pci_read_config_byte(chip->pci, 0x42, &val);
2960 if (!(val & 0x80) && chip->pci->revision == 0x30)
2961 snoop = false;
2962 }
2963 break;
2964 case AZX_DRIVER_ATIHDMI_NS:
2965 /* new ATI HDMI requires non-snoop */
2966 snoop = false;
2967 break;
2968 }
2969
2970 if (snoop != chip->snoop) {
2971 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2972 snoop ? "snoop" : "non-snoop");
2973 chip->snoop = snoop;
2974 }
2975}
669ba27a 2976
1da177e4
LT		 2977/*
2978 * constructor
2979 */
a98f90fd 2980static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
9477c58e 2981 int dev, unsigned int driver_caps,
a98f90fd 2982 struct azx **rchip)
1da177e4 2983{
a98f90fd 2984 static struct snd_device_ops ops = {
1da177e4
LT		 2985 .dev_free = azx_dev_free,
2986 };
a82d51ed
TI		 2987 struct azx *chip;
2988 int err;
1da177e4
LT		 2989
2990 *rchip = NULL;
bcd72003 2991
927fc866
PM		 2992 err = pci_enable_device(pci);
2993 if (err < 0)
1da177e4
LT		 2994 return err;
2995
e560d8d8 2996 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 2997 if (!chip) {
1da177e4
LT		 2998 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2999 pci_disable_device(pci);
3000 return -ENOMEM;
3001 }
3002
3003 spin_lock_init(&chip->reg_lock);
62932df8 3004 mutex_init(&chip->open_mutex);
1da177e4
LT		 3005 chip->card = card;
3006 chip->pci = pci;
3007 chip->irq = -1;
9477c58e
TI		 3008 chip->driver_caps = driver_caps;
3009 chip->driver_type = driver_caps & 0xff;
4d8e22e0 3010 check_msi(chip);
555e219f 3011 chip->dev_index = dev;
9ad593f6 3012 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 3013 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 3014 INIT_LIST_HEAD(&chip->list);
a82d51ed 3015 init_vga_switcheroo(chip);
1da177e4 3016
beaffc39
SG		 3017 chip->position_fix[0] = chip->position_fix[1] =
3018 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 3019 /* combo mode uses LPIB for playback */
3020 if (chip->position_fix[0] == POS_FIX_COMBO) {
3021 chip->position_fix[0] = POS_FIX_LPIB;
3022 chip->position_fix[1] = POS_FIX_AUTO;
3023 }
3024
5aba4f8e 3025 check_probe_mask(chip, dev);
3372a153 3026
27346166 3027 chip->single_cmd = single_cmd;
27fe48d9 3028 chip->snoop = hda_snoop;
a1585d76 3029 azx_check_snoop_available(chip);
c74db86b 3030
5c0d7bc1
TI		 3031 if (bdl_pos_adj[dev] < 0) {
3032 switch (chip->driver_type) {
0c6341ac 3033 case AZX_DRIVER_ICH:
32679f95 3034 case AZX_DRIVER_PCH:
0c6341ac 3035 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 3036 break;
3037 default:
0c6341ac 3038 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 3039 break;
3040 }
3041 }
3042
a82d51ed
TI		 3043 if (check_hdmi_disabled(pci)) {
3044 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
3045 pci_name(pci));
3046 if (use_vga_switcheroo(chip)) {
3047 snd_printk(KERN_INFO SFX "Delaying initialization\n");
3048 chip->disabled = true;
3049 goto ok;
3050 }
3051 kfree(chip);
3052 pci_disable_device(pci);
3053 return -ENXIO;
3054 }
3055
3056 err = azx_first_init(chip);
3057 if (err < 0) {
3058 azx_free(chip);
3059 return err;
3060 }
3061
3062 ok:
3063 err = register_vga_switcheroo(chip);
3064 if (err < 0) {
3065 snd_printk(KERN_ERR SFX
3066 "Error registering VGA-switcheroo client\n");
3067 azx_free(chip);
3068 return err;
3069 }
3070
3071 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3072 if (err < 0) {
3073 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3074 azx_free(chip);
3075 return err;
3076 }
3077
3078 *rchip = chip;
3079 return 0;
3080}
3081
3082static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3083{
3084 int dev = chip->dev_index;
3085 struct pci_dev *pci = chip->pci;
3086 struct snd_card *card = chip->card;
3087 int i, err;
3088 unsigned short gcap;
3089
07e4ca50
TI		 3090#if BITS_PER_LONG != 64
3091 /* Fix up base address on ULI M5461 */
3092 if (chip->driver_type == AZX_DRIVER_ULI) {
3093 u16 tmp3;
3094 pci_read_config_word(pci, 0x40, &tmp3);
3095 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3096 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3097 }
3098#endif
3099
927fc866 3100 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 3101 if (err < 0)
1da177e4 3102 return err;
a82d51ed 3103 chip->region_requested = 1;
1da177e4 3104
927fc866 3105 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 3106 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 3107 if (chip->remap_addr == NULL) {
3108 snd_printk(KERN_ERR SFX "ioremap error\n");
a82d51ed 3109 return -ENXIO;
1da177e4
LT		 3110 }
3111
68e7fffc
TI		 3112 if (chip->msi)
3113 if (pci_enable_msi(pci) < 0)
3114 chip->msi = 0;
7376d013 3115
a82d51ed
TI		 3116 if (azx_acquire_irq(chip, 0) < 0)
3117 return -EBUSY;
1da177e4
LT		 3118
3119 pci_set_master(pci);
3120 synchronize_irq(chip->irq);
3121
bcd72003 3122 gcap = azx_readw(chip, GCAP);
4abc1cc2 3123 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 3124
dc4c2e6b 3125 /* disable SB600 64bit support for safety */
9477c58e 3126 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3127 struct pci_dev *p_smbus;
3128 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3129 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3130 NULL);
3131 if (p_smbus) {
3132 if (p_smbus->revision < 0x30)
3133 gcap &= ~ICH6_GCAP_64OK;
3134 pci_dev_put(p_smbus);
3135 }
3136 }
09240cf4 3137
9477c58e
TI		 3138 /* disable 64bit DMA address on some devices */
3139 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3140 snd_printd(SFX "Disabling 64bit DMA\n");
396087ea 3141 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3142 }
396087ea 3143
2ae66c26 3144 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3145 if (align_buffer_size >= 0)
3146 chip->align_buffer_size = !!align_buffer_size;
3147 else {
3148 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3149 chip->align_buffer_size = 0;
3150 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3151 chip->align_buffer_size = 1;
3152 else
3153 chip->align_buffer_size = 1;
3154 }
2ae66c26 3155
cf7aaca8 3156 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3157 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3158 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3159 else {
e930438c
YH		 3160 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3161 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3162 }
cf7aaca8 3163
8b6ed8e7
TI		 3164 /* read number of streams from GCAP register instead of using
3165 * hardcoded value
3166 */
3167 chip->capture_streams = (gcap >> 8) & 0x0f;
3168 chip->playback_streams = (gcap >> 12) & 0x0f;
3169 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3170 /* gcap didn't give any info, switching to old method */
3171
3172 switch (chip->driver_type) {
3173 case AZX_DRIVER_ULI:
3174 chip->playback_streams = ULI_NUM_PLAYBACK;
3175 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3176 break;
3177 case AZX_DRIVER_ATIHDMI:
1815b34a 3178 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3179 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3180 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3181 break;
c4da29ca 3182 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3183 default:
3184 chip->playback_streams = ICH6_NUM_PLAYBACK;
3185 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3186 break;
3187 }
07e4ca50 3188 }
8b6ed8e7
TI		 3189 chip->capture_index_offset = 0;
3190 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3191 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3192 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3193 GFP_KERNEL);
927fc866 3194 if (!chip->azx_dev) {
4abc1cc2 3195 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
a82d51ed 3196 return -ENOMEM;
07e4ca50
TI		 3197 }
3198
4ce107b9
TI		 3199 for (i = 0; i < chip->num_streams; i++) {
3200 /* allocate memory for the BDL for each stream */
3201 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3202 snd_dma_pci_data(chip->pci),
3203 BDL_SIZE, &chip->azx_dev[i].bdl);
3204 if (err < 0) {
3205 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
a82d51ed 3206 return -ENOMEM;
4ce107b9 3207 }
27fe48d9 3208 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3209 }
0be3b5d3 3210 /* allocate memory for the position buffer */
d01ce99f
TI		 3211 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3212 snd_dma_pci_data(chip->pci),
3213 chip->num_streams * 8, &chip->posbuf);
3214 if (err < 0) {
0be3b5d3 3215 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
a82d51ed 3216 return -ENOMEM;
1da177e4 3217 }
27fe48d9 3218 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3219 /* allocate CORB/RIRB */
81740861
TI		 3220 err = azx_alloc_cmd_io(chip);
3221 if (err < 0)
a82d51ed 3222 return err;
1da177e4
LT		 3223
3224 /* initialize streams */
3225 azx_init_stream(chip);
3226
3227 /* initialize chip */
cb53c626 3228 azx_init_pci(chip);
10e77dda 3229 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3230
3231 /* codec detection */
927fc866 3232 if (!chip->codec_mask) {
1da177e4 3233 snd_printk(KERN_ERR SFX "no codecs found!\n");
a82d51ed 3234 return -ENODEV;
1da177e4
LT		 3235 }
3236
07e4ca50 3237 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3238 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3239 sizeof(card->shortname));
3240 snprintf(card->longname, sizeof(card->longname),
3241 "%s at 0x%lx irq %i",
3242 card->shortname, chip->addr, chip->irq);
07e4ca50 3243
1da177e4 3244 return 0;
1da177e4
LT		 3245}
3246
cb53c626
TI		 3247static void power_down_all_codecs(struct azx *chip)
3248{
83012a7c 3249#ifdef CONFIG_PM
cb53c626
TI		 3250 /* The codecs were powered up in snd_hda_codec_new().
3251 * Now all initialization done, so turn them down if possible
3252 */
3253 struct hda_codec *codec;
3254 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3255 snd_hda_power_down(codec);
3256 }
3257#endif
3258}
3259
97c6a3d1 3260#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 3261/* callback from request_firmware_nowait() */
3262static void azx_firmware_cb(const struct firmware *fw, void *context)
3263{
3264 struct snd_card *card = context;
3265 struct azx *chip = card->private_data;
3266 struct pci_dev *pci = chip->pci;
3267
3268 if (!fw) {
3269 snd_printk(KERN_ERR SFX "Cannot load firmware, aborting\n");
3270 goto error;
3271 }
3272
3273 chip->fw = fw;
3274 if (!chip->disabled) {
3275 /* continue probing */
3276 if (azx_probe_continue(chip))
3277 goto error;
3278 }
3279 return; /* OK */
3280
3281 error:
3282 snd_card_free(card);
3283 pci_set_drvdata(pci, NULL);
3284}
97c6a3d1 3285#endif
5cb543db 3286
d01ce99f
TI		 3287static int __devinit azx_probe(struct pci_dev *pci,
3288 const struct pci_device_id *pci_id)
1da177e4 3289{
5aba4f8e 3290 static int dev;
a98f90fd
TI		 3291 struct snd_card *card;
3292 struct azx *chip;
5cb543db 3293 bool probe_now;
927fc866 3294 int err;
1da177e4 3295
5aba4f8e
TI		 3296 if (dev >= SNDRV_CARDS)
3297 return -ENODEV;
3298 if (!enable[dev]) {
3299 dev++;
3300 return -ENOENT;
3301 }
3302
e58de7ba
TI		 3303 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3304 if (err < 0) {
1da177e4 3305 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 3306 return err;
1da177e4
LT		 3307 }
3308
4ea6fbc8
TI		 3309 snd_card_set_dev(card, &pci->dev);
3310
5aba4f8e 3311 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3312 if (err < 0)
3313 goto out_free;
421a1252 3314 card->private_data = chip;
5cb543db 3315 probe_now = !chip->disabled;
1da177e4 3316
4918cdab
TI		 3317#ifdef CONFIG_SND_HDA_PATCH_LOADER
3318 if (patch[dev] && *patch[dev]) {
3319 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3320 patch[dev]);
5cb543db
TI		 3321 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3322 &pci->dev, GFP_KERNEL, card,
3323 azx_firmware_cb);
4918cdab
TI		 3324 if (err < 0)
3325 goto out_free;
5cb543db 3326 probe_now = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 3327 }
3328#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3329
5cb543db 3330 if (probe_now) {
a82d51ed
TI		 3331 err = azx_probe_continue(chip);
3332 if (err < 0)
3333 goto out_free;
3334 }
3335
3336 pci_set_drvdata(pci, card);
3337
b8dfc462
ML		 3338 if (pci_dev_run_wake(pci))
3339 pm_runtime_put_noidle(&pci->dev);
3340
a82d51ed
TI		 3341 dev++;
3342 return 0;
3343
3344out_free:
3345 snd_card_free(card);
3346 return err;
3347}
3348
3349static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3350{
3351 int dev = chip->dev_index;
3352 int err;
3353
2dca0bba
JK		 3354#ifdef CONFIG_SND_HDA_INPUT_BEEP
3355 chip->beep_mode = beep_mode[dev];
3356#endif
3357
1da177e4 3358 /* create codec instances */
a1e21c90 3359 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3360 if (err < 0)
3361 goto out_free;
4ea6fbc8 3362#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 3363 if (chip->fw) {
3364 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3365 chip->fw->data);
4ea6fbc8
TI		 3366 if (err < 0)
3367 goto out_free;
4918cdab
TI		 3368 release_firmware(chip->fw); /* no longer needed */
3369 chip->fw = NULL;
4ea6fbc8
TI		 3370 }
3371#endif
10e77dda 3372 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3373 err = azx_codec_configure(chip);
3374 if (err < 0)
3375 goto out_free;
3376 }
1da177e4
LT		 3377
3378 /* create PCM streams */
176d5335 3379 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3380 if (err < 0)
3381 goto out_free;
1da177e4
LT		 3382
3383 /* create mixer controls */
d01ce99f 3384 err = azx_mixer_create(chip);
41dda0fd
WF		 3385 if (err < 0)
3386 goto out_free;
1da177e4 3387
a82d51ed 3388 err = snd_card_register(chip->card);
41dda0fd
WF		 3389 if (err < 0)
3390 goto out_free;
1da177e4 3391
cb53c626
TI		 3392 chip->running = 1;
3393 power_down_all_codecs(chip);
0cbf0098 3394 azx_notifier_register(chip);
65fcd41d 3395 azx_add_card_list(chip);
1da177e4 3396
9121947d
TI		 3397 return 0;
3398
41dda0fd 3399out_free:
a82d51ed 3400 chip->init_failed = 1;
41dda0fd 3401 return err;
1da177e4
LT		 3402}
3403
3404static void __devexit azx_remove(struct pci_dev *pci)
3405{
9121947d 3406 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462
ML		 3407
3408 if (pci_dev_run_wake(pci))
3409 pm_runtime_get_noresume(&pci->dev);
3410
9121947d
TI		 3411 if (card)
3412 snd_card_free(card);
1da177e4
LT		 3413 pci_set_drvdata(pci, NULL);
3414}
3415
3416/* PCI IDs */
cebe41d4 3417static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3418 /* CPT */
9477c58e 3419 { PCI_DEVICE(0x8086, 0x1c20),
2ae66c26 3420 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
90accc58 3421 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
cea310e8 3422 /* PBG */
9477c58e 3423 { PCI_DEVICE(0x8086, 0x1d20),
2ae66c26
PLB		 3424 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3425 AZX_DCAPS_BUFSIZE},
d2edeb7c 3426 /* Panther Point */
9477c58e 3427 { PCI_DEVICE(0x8086, 0x1e20),
2ae66c26 3428 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
90accc58 3429 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
8bc039a1
SH		 3430 /* Lynx Point */
3431 { PCI_DEVICE(0x8086, 0x8c20),
3432 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
90accc58 3433 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
144dad99
JR		 3434 /* Lynx Point-LP */
3435 { PCI_DEVICE(0x8086, 0x9c20),
3436 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
90accc58 3437 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
144dad99
JR		 3438 /* Lynx Point-LP */
3439 { PCI_DEVICE(0x8086, 0x9c21),
3440 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
90accc58 3441 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
e926f2c8
WX		 3442 /* Haswell */
3443 { PCI_DEVICE(0x8086, 0x0c0c),
bdbe34de 3444 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
90accc58 3445 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
d279fae8
WX		 3446 { PCI_DEVICE(0x8086, 0x0d0c),
3447 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
90accc58 3448 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
99df18b3
PLB		 3449 /* 5 Series/3400 */
3450 { PCI_DEVICE(0x8086, 0x3b56),
3451 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3452 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
87218e9c 3453 /* SCH */
9477c58e 3454 { PCI_DEVICE(0x8086, 0x811b),
2ae66c26 3455 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
645e9035 3456 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
09904b95
LP		 3457 { PCI_DEVICE(0x8086, 0x080a),
3458 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
716e5db4 3459 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
645e9035 3460 /* ICH */
8b0bd226 3461 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 3462 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3463 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 3464 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 3465 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3466 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 3467 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 3468 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3469 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 3470 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 3471 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3472 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 3473 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 3474 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3475 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3476 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 3477 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3478 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3479 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 3480 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3481 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 3482 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 3483 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3484 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 3485 /* Generic Intel */
3486 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3487 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3488 .class_mask = 0xffffff,
2ae66c26 3489 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 3490 /* ATI SB 450/600/700/800/900 */
3491 { PCI_DEVICE(0x1002, 0x437b),
3492 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3493 { PCI_DEVICE(0x1002, 0x4383),
3494 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3495 /* AMD Hudson */
3496 { PCI_DEVICE(0x1022, 0x780d),
3497 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 3498 /* ATI HDMI */
9477c58e
TI		 3499 { PCI_DEVICE(0x1002, 0x793b),
3500 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3501 { PCI_DEVICE(0x1002, 0x7919),
3502 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3503 { PCI_DEVICE(0x1002, 0x960f),
3504 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3505 { PCI_DEVICE(0x1002, 0x970f),
3506 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3507 { PCI_DEVICE(0x1002, 0xaa00),
3508 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3509 { PCI_DEVICE(0x1002, 0xaa08),
3510 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3511 { PCI_DEVICE(0x1002, 0xaa10),
3512 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3513 { PCI_DEVICE(0x1002, 0xaa18),
3514 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3515 { PCI_DEVICE(0x1002, 0xaa20),
3516 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3517 { PCI_DEVICE(0x1002, 0xaa28),
3518 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3519 { PCI_DEVICE(0x1002, 0xaa30),
3520 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3521 { PCI_DEVICE(0x1002, 0xaa38),
3522 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3523 { PCI_DEVICE(0x1002, 0xaa40),
3524 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3525 { PCI_DEVICE(0x1002, 0xaa48),
3526 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 3527 { PCI_DEVICE(0x1002, 0x9902),
3528 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3529 { PCI_DEVICE(0x1002, 0xaaa0),
3530 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3531 { PCI_DEVICE(0x1002, 0xaaa8),
3532 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3533 { PCI_DEVICE(0x1002, 0xaab0),
3534 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 3535 /* VIA VT8251/VT8237A */
9477c58e
TI		 3536 { PCI_DEVICE(0x1106, 0x3288),
3537 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 3538 /* VIA GFX VT7122/VX900 */
3539 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3540 /* VIA GFX VT6122/VX11 */
3541 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 3542 /* SIS966 */
3543 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3544 /* ULI M5461 */
3545 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3546 /* NVIDIA MCP */
0c2fd1bf
TI		 3547 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3548 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3549 .class_mask = 0xffffff,
9477c58e 3550 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 3551 /* Teradici */
9477c58e
TI		 3552 { PCI_DEVICE(0x6549, 0x1200),
3553 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 3554 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 3555 /* CTHDA chips */
3556 { PCI_DEVICE(0x1102, 0x0010),
3557 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3558 { PCI_DEVICE(0x1102, 0x0012),
3559 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
313f6e2d
TI		 3560#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3561 /* the following entry conflicts with snd-ctxfi driver,
3562 * as ctxfi driver mutates from HD-audio to native mode with
3563 * a special command sequence.
3564 */
4e01f54b
TI		 3565 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3566 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3567 .class_mask = 0xffffff,
9477c58e 3568 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3569 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 3570#else
3571 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 3572 { PCI_DEVICE(0x1102, 0x0009),
3573 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3574 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 3575#endif
e35d4b11
OS		 3576 /* Vortex86MX */
3577 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 3578 /* VMware HDAudio */
3579 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 3580 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 3581 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3582 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3583 .class_mask = 0xffffff,
9477c58e 3584 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 3585 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3586 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3587 .class_mask = 0xffffff,
9477c58e 3588 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 3589 { 0, }
3590};
3591MODULE_DEVICE_TABLE(pci, azx_ids);
3592
3593/* pci_driver definition */
e9f66d9b 3594static struct pci_driver azx_driver = {
3733e424 3595 .name = KBUILD_MODNAME,
1da177e4
LT		 3596 .id_table = azx_ids,
3597 .probe = azx_probe,
3598 .remove = __devexit_p(azx_remove),
68cb2b55
TI		 3599 .driver = {
3600 .pm = AZX_PM_OPS,
3601 },
1da177e4
LT		 3602};
3603
e9f66d9b 3604module_pci_driver(azx_driver);
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