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1da177e4 LT |
1 | /* |
2 | * | |
3 | * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio. | |
4 | * | |
5 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
8 | * PeiSen Hou <pshou@realtek.com.tw> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the Free | |
12 | * Software Foundation; either version 2 of the License, or (at your option) | |
13 | * any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
18 | * more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along with | |
21 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
22 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
23 | * | |
24 | * CONTACTS: | |
25 | * | |
26 | * Matt Jared matt.jared@intel.com | |
27 | * Andy Kopp andy.kopp@intel.com | |
28 | * Dan Kogan dan.d.kogan@intel.com | |
29 | * | |
30 | * CHANGES: | |
31 | * | |
32 | * 2004.12.01 Major rewrite by tiwai, merged the work of pshou | |
33 | * | |
34 | */ | |
35 | ||
36 | #include <sound/driver.h> | |
37 | #include <asm/io.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/module.h> | |
41 | #include <linux/moduleparam.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/slab.h> | |
44 | #include <linux/pci.h> | |
45 | #include <sound/core.h> | |
46 | #include <sound/initval.h> | |
47 | #include "hda_codec.h" | |
48 | ||
49 | ||
50 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; | |
51 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; | |
52 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; | |
53 | static char *model[SNDRV_CARDS]; | |
c74db86b | 54 | static int position_fix[SNDRV_CARDS]; |
1da177e4 LT |
55 | |
56 | module_param_array(index, int, NULL, 0444); | |
57 | MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); | |
58 | module_param_array(id, charp, NULL, 0444); | |
59 | MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); | |
60 | module_param_array(enable, bool, NULL, 0444); | |
61 | MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); | |
62 | module_param_array(model, charp, NULL, 0444); | |
63 | MODULE_PARM_DESC(model, "Use the given board model."); | |
9bc533f5 | 64 | module_param_array(position_fix, int, NULL, 0444); |
c74db86b | 65 | MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = FIFO size, 1 = none, 2 = POSBUF)."); |
1da177e4 LT |
66 | |
67 | MODULE_LICENSE("GPL"); | |
68 | MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," | |
69 | "{Intel, ICH6M}," | |
2f1b3818 | 70 | "{Intel, ICH7}," |
f5d40b30 | 71 | "{Intel, ESB2}," |
fc20a562 TI |
72 | "{ATI, SB450}," |
73 | "{VIA, VT8251}," | |
74 | "{VIA, VT8237A}}"); | |
1da177e4 LT |
75 | MODULE_DESCRIPTION("Intel HDA driver"); |
76 | ||
77 | #define SFX "hda-intel: " | |
78 | ||
79 | /* | |
80 | * registers | |
81 | */ | |
82 | #define ICH6_REG_GCAP 0x00 | |
83 | #define ICH6_REG_VMIN 0x02 | |
84 | #define ICH6_REG_VMAJ 0x03 | |
85 | #define ICH6_REG_OUTPAY 0x04 | |
86 | #define ICH6_REG_INPAY 0x06 | |
87 | #define ICH6_REG_GCTL 0x08 | |
88 | #define ICH6_REG_WAKEEN 0x0c | |
89 | #define ICH6_REG_STATESTS 0x0e | |
90 | #define ICH6_REG_GSTS 0x10 | |
91 | #define ICH6_REG_INTCTL 0x20 | |
92 | #define ICH6_REG_INTSTS 0x24 | |
93 | #define ICH6_REG_WALCLK 0x30 | |
94 | #define ICH6_REG_SYNC 0x34 | |
95 | #define ICH6_REG_CORBLBASE 0x40 | |
96 | #define ICH6_REG_CORBUBASE 0x44 | |
97 | #define ICH6_REG_CORBWP 0x48 | |
98 | #define ICH6_REG_CORBRP 0x4A | |
99 | #define ICH6_REG_CORBCTL 0x4c | |
100 | #define ICH6_REG_CORBSTS 0x4d | |
101 | #define ICH6_REG_CORBSIZE 0x4e | |
102 | ||
103 | #define ICH6_REG_RIRBLBASE 0x50 | |
104 | #define ICH6_REG_RIRBUBASE 0x54 | |
105 | #define ICH6_REG_RIRBWP 0x58 | |
106 | #define ICH6_REG_RINTCNT 0x5a | |
107 | #define ICH6_REG_RIRBCTL 0x5c | |
108 | #define ICH6_REG_RIRBSTS 0x5d | |
109 | #define ICH6_REG_RIRBSIZE 0x5e | |
110 | ||
111 | #define ICH6_REG_IC 0x60 | |
112 | #define ICH6_REG_IR 0x64 | |
113 | #define ICH6_REG_IRS 0x68 | |
114 | #define ICH6_IRS_VALID (1<<1) | |
115 | #define ICH6_IRS_BUSY (1<<0) | |
116 | ||
117 | #define ICH6_REG_DPLBASE 0x70 | |
118 | #define ICH6_REG_DPUBASE 0x74 | |
119 | #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ | |
120 | ||
121 | /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ | |
122 | enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; | |
123 | ||
124 | /* stream register offsets from stream base */ | |
125 | #define ICH6_REG_SD_CTL 0x00 | |
126 | #define ICH6_REG_SD_STS 0x03 | |
127 | #define ICH6_REG_SD_LPIB 0x04 | |
128 | #define ICH6_REG_SD_CBL 0x08 | |
129 | #define ICH6_REG_SD_LVI 0x0c | |
130 | #define ICH6_REG_SD_FIFOW 0x0e | |
131 | #define ICH6_REG_SD_FIFOSIZE 0x10 | |
132 | #define ICH6_REG_SD_FORMAT 0x12 | |
133 | #define ICH6_REG_SD_BDLPL 0x18 | |
134 | #define ICH6_REG_SD_BDLPU 0x1c | |
135 | ||
136 | /* PCI space */ | |
137 | #define ICH6_PCIREG_TCSEL 0x44 | |
138 | ||
139 | /* | |
140 | * other constants | |
141 | */ | |
142 | ||
143 | /* max number of SDs */ | |
144 | #define MAX_ICH6_DEV 8 | |
145 | /* max number of fragments - we may use more if allocating more pages for BDL */ | |
146 | #define AZX_MAX_FRAG (PAGE_SIZE / (MAX_ICH6_DEV * 16)) | |
147 | /* max buffer size - no h/w limit, you can increase as you like */ | |
148 | #define AZX_MAX_BUF_SIZE (1024*1024*1024) | |
149 | /* max number of PCM devics per card */ | |
150 | #define AZX_MAX_PCMS 8 | |
151 | ||
152 | /* RIRB int mask: overrun[2], response[0] */ | |
153 | #define RIRB_INT_RESPONSE 0x01 | |
154 | #define RIRB_INT_OVERRUN 0x04 | |
155 | #define RIRB_INT_MASK 0x05 | |
156 | ||
157 | /* STATESTS int mask: SD2,SD1,SD0 */ | |
158 | #define STATESTS_INT_MASK 0x07 | |
f5d40b30 | 159 | #define AZX_MAX_CODECS 4 |
1da177e4 LT |
160 | |
161 | /* SD_CTL bits */ | |
162 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ | |
163 | #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ | |
164 | #define SD_CTL_STREAM_TAG_MASK (0xf << 20) | |
165 | #define SD_CTL_STREAM_TAG_SHIFT 20 | |
166 | ||
167 | /* SD_CTL and SD_STS */ | |
168 | #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ | |
169 | #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ | |
170 | #define SD_INT_COMPLETE 0x04 /* completion interrupt */ | |
171 | #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE) | |
172 | ||
173 | /* SD_STS */ | |
174 | #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ | |
175 | ||
176 | /* INTCTL and INTSTS */ | |
177 | #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ | |
178 | #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ | |
179 | #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ | |
180 | ||
181 | /* GCTL reset bit */ | |
182 | #define ICH6_GCTL_RESET (1<<0) | |
183 | ||
184 | /* CORB/RIRB control, read/write pointer */ | |
185 | #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */ | |
186 | #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */ | |
187 | #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */ | |
188 | /* below are so far hardcoded - should read registers in future */ | |
189 | #define ICH6_MAX_CORB_ENTRIES 256 | |
190 | #define ICH6_MAX_RIRB_ENTRIES 256 | |
191 | ||
c74db86b TI |
192 | /* position fix mode */ |
193 | enum { | |
194 | POS_FIX_FIFO, | |
195 | POS_FIX_NONE, | |
196 | POS_FIX_POSBUF | |
197 | }; | |
1da177e4 | 198 | |
f5d40b30 FL |
199 | /* Defines for ATI HD Audio support in SB450 south bridge */ |
200 | #define ATI_SB450_HDAUDIO_PCI_DEVICE_ID 0x437b | |
201 | #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 | |
202 | #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 | |
203 | ||
204 | ||
1da177e4 LT |
205 | /* |
206 | * Use CORB/RIRB for communication from/to codecs. | |
207 | * This is the way recommended by Intel (see below). | |
208 | */ | |
209 | #define USE_CORB_RIRB | |
210 | ||
1da177e4 LT |
211 | /* |
212 | */ | |
213 | ||
214 | typedef struct snd_azx azx_t; | |
215 | typedef struct snd_azx_rb azx_rb_t; | |
216 | typedef struct snd_azx_dev azx_dev_t; | |
217 | ||
218 | struct snd_azx_dev { | |
219 | u32 *bdl; /* virtual address of the BDL */ | |
220 | dma_addr_t bdl_addr; /* physical address of the BDL */ | |
221 | volatile u32 *posbuf; /* position buffer pointer */ | |
222 | ||
223 | unsigned int bufsize; /* size of the play buffer in bytes */ | |
224 | unsigned int fragsize; /* size of each period in bytes */ | |
225 | unsigned int frags; /* number for period in the play buffer */ | |
226 | unsigned int fifo_size; /* FIFO size */ | |
227 | ||
228 | void __iomem *sd_addr; /* stream descriptor pointer */ | |
229 | ||
230 | u32 sd_int_sta_mask; /* stream int status mask */ | |
231 | ||
232 | /* pcm support */ | |
233 | snd_pcm_substream_t *substream; /* assigned substream, set in PCM open */ | |
234 | unsigned int format_val; /* format value to be set in the controller and the codec */ | |
235 | unsigned char stream_tag; /* assigned stream */ | |
236 | unsigned char index; /* stream index */ | |
237 | ||
238 | unsigned int opened: 1; | |
239 | unsigned int running: 1; | |
240 | }; | |
241 | ||
242 | /* CORB/RIRB */ | |
243 | struct snd_azx_rb { | |
244 | u32 *buf; /* CORB/RIRB buffer | |
245 | * Each CORB entry is 4byte, RIRB is 8byte | |
246 | */ | |
247 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | |
248 | /* for RIRB */ | |
249 | unsigned short rp, wp; /* read/write pointers */ | |
250 | int cmds; /* number of pending requests */ | |
251 | u32 res; /* last read value */ | |
252 | }; | |
253 | ||
254 | struct snd_azx { | |
255 | snd_card_t *card; | |
256 | struct pci_dev *pci; | |
257 | ||
258 | /* pci resources */ | |
259 | unsigned long addr; | |
260 | void __iomem *remap_addr; | |
261 | int irq; | |
262 | ||
263 | /* locks */ | |
264 | spinlock_t reg_lock; | |
265 | struct semaphore open_mutex; | |
266 | ||
267 | /* streams */ | |
268 | azx_dev_t azx_dev[MAX_ICH6_DEV]; | |
269 | ||
270 | /* PCM */ | |
271 | unsigned int pcm_devs; | |
272 | snd_pcm_t *pcm[AZX_MAX_PCMS]; | |
273 | ||
274 | /* HD codec */ | |
275 | unsigned short codec_mask; | |
276 | struct hda_bus *bus; | |
277 | ||
278 | /* CORB/RIRB */ | |
279 | azx_rb_t corb; | |
280 | azx_rb_t rirb; | |
281 | ||
282 | /* BDL, CORB/RIRB and position buffers */ | |
283 | struct snd_dma_buffer bdl; | |
284 | struct snd_dma_buffer rb; | |
285 | struct snd_dma_buffer posbuf; | |
c74db86b TI |
286 | |
287 | /* flags */ | |
288 | int position_fix; | |
ce43fbae | 289 | unsigned int initialized: 1; |
1da177e4 LT |
290 | }; |
291 | ||
292 | /* | |
293 | * macros for easy use | |
294 | */ | |
295 | #define azx_writel(chip,reg,value) \ | |
296 | writel(value, (chip)->remap_addr + ICH6_REG_##reg) | |
297 | #define azx_readl(chip,reg) \ | |
298 | readl((chip)->remap_addr + ICH6_REG_##reg) | |
299 | #define azx_writew(chip,reg,value) \ | |
300 | writew(value, (chip)->remap_addr + ICH6_REG_##reg) | |
301 | #define azx_readw(chip,reg) \ | |
302 | readw((chip)->remap_addr + ICH6_REG_##reg) | |
303 | #define azx_writeb(chip,reg,value) \ | |
304 | writeb(value, (chip)->remap_addr + ICH6_REG_##reg) | |
305 | #define azx_readb(chip,reg) \ | |
306 | readb((chip)->remap_addr + ICH6_REG_##reg) | |
307 | ||
308 | #define azx_sd_writel(dev,reg,value) \ | |
309 | writel(value, (dev)->sd_addr + ICH6_REG_##reg) | |
310 | #define azx_sd_readl(dev,reg) \ | |
311 | readl((dev)->sd_addr + ICH6_REG_##reg) | |
312 | #define azx_sd_writew(dev,reg,value) \ | |
313 | writew(value, (dev)->sd_addr + ICH6_REG_##reg) | |
314 | #define azx_sd_readw(dev,reg) \ | |
315 | readw((dev)->sd_addr + ICH6_REG_##reg) | |
316 | #define azx_sd_writeb(dev,reg,value) \ | |
317 | writeb(value, (dev)->sd_addr + ICH6_REG_##reg) | |
318 | #define azx_sd_readb(dev,reg) \ | |
319 | readb((dev)->sd_addr + ICH6_REG_##reg) | |
320 | ||
321 | /* for pcm support */ | |
322 | #define get_azx_dev(substream) (azx_dev_t*)(substream->runtime->private_data) | |
323 | ||
324 | /* Get the upper 32bit of the given dma_addr_t | |
325 | * Compiler should optimize and eliminate the code if dma_addr_t is 32bit | |
326 | */ | |
327 | #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0) | |
328 | ||
329 | ||
330 | /* | |
331 | * Interface for HD codec | |
332 | */ | |
333 | ||
334 | #ifdef USE_CORB_RIRB | |
335 | /* | |
336 | * CORB / RIRB interface | |
337 | */ | |
338 | static int azx_alloc_cmd_io(azx_t *chip) | |
339 | { | |
340 | int err; | |
341 | ||
342 | /* single page (at least 4096 bytes) must suffice for both ringbuffes */ | |
343 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
344 | PAGE_SIZE, &chip->rb); | |
345 | if (err < 0) { | |
346 | snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n"); | |
347 | return err; | |
348 | } | |
349 | return 0; | |
350 | } | |
351 | ||
352 | static void azx_init_cmd_io(azx_t *chip) | |
353 | { | |
354 | /* CORB set up */ | |
355 | chip->corb.addr = chip->rb.addr; | |
356 | chip->corb.buf = (u32 *)chip->rb.area; | |
357 | azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); | |
358 | azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr)); | |
359 | ||
360 | /* set the corb write pointer to 0 */ | |
361 | azx_writew(chip, CORBWP, 0); | |
362 | /* reset the corb hw read pointer */ | |
363 | azx_writew(chip, CORBRP, ICH6_RBRWP_CLR); | |
364 | /* enable corb dma */ | |
365 | azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN); | |
366 | ||
367 | /* RIRB set up */ | |
368 | chip->rirb.addr = chip->rb.addr + 2048; | |
369 | chip->rirb.buf = (u32 *)(chip->rb.area + 2048); | |
370 | azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); | |
371 | azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr)); | |
372 | ||
373 | /* reset the rirb hw write pointer */ | |
374 | azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR); | |
375 | /* set N=1, get RIRB response interrupt for new entry */ | |
376 | azx_writew(chip, RINTCNT, 1); | |
377 | /* enable rirb dma and response irq */ | |
378 | #ifdef USE_CORB_RIRB | |
379 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); | |
380 | #else | |
381 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN); | |
382 | #endif | |
383 | chip->rirb.rp = chip->rirb.cmds = 0; | |
384 | } | |
385 | ||
386 | static void azx_free_cmd_io(azx_t *chip) | |
387 | { | |
388 | /* disable ringbuffer DMAs */ | |
389 | azx_writeb(chip, RIRBCTL, 0); | |
390 | azx_writeb(chip, CORBCTL, 0); | |
391 | } | |
392 | ||
393 | /* send a command */ | |
394 | static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct, | |
395 | unsigned int verb, unsigned int para) | |
396 | { | |
397 | azx_t *chip = codec->bus->private_data; | |
398 | unsigned int wp; | |
399 | u32 val; | |
400 | ||
401 | val = (u32)(codec->addr & 0x0f) << 28; | |
402 | val |= (u32)direct << 27; | |
403 | val |= (u32)nid << 20; | |
404 | val |= verb << 8; | |
405 | val |= para; | |
406 | ||
407 | /* add command to corb */ | |
408 | wp = azx_readb(chip, CORBWP); | |
409 | wp++; | |
410 | wp %= ICH6_MAX_CORB_ENTRIES; | |
411 | ||
412 | spin_lock_irq(&chip->reg_lock); | |
413 | chip->rirb.cmds++; | |
414 | chip->corb.buf[wp] = cpu_to_le32(val); | |
415 | azx_writel(chip, CORBWP, wp); | |
416 | spin_unlock_irq(&chip->reg_lock); | |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
421 | #define ICH6_RIRB_EX_UNSOL_EV (1<<4) | |
422 | ||
423 | /* retrieve RIRB entry - called from interrupt handler */ | |
424 | static void azx_update_rirb(azx_t *chip) | |
425 | { | |
426 | unsigned int rp, wp; | |
427 | u32 res, res_ex; | |
428 | ||
429 | wp = azx_readb(chip, RIRBWP); | |
430 | if (wp == chip->rirb.wp) | |
431 | return; | |
432 | chip->rirb.wp = wp; | |
433 | ||
434 | while (chip->rirb.rp != wp) { | |
435 | chip->rirb.rp++; | |
436 | chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; | |
437 | ||
438 | rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ | |
439 | res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); | |
440 | res = le32_to_cpu(chip->rirb.buf[rp]); | |
441 | if (res_ex & ICH6_RIRB_EX_UNSOL_EV) | |
442 | snd_hda_queue_unsol_event(chip->bus, res, res_ex); | |
443 | else if (chip->rirb.cmds) { | |
444 | chip->rirb.cmds--; | |
445 | chip->rirb.res = res; | |
446 | } | |
447 | } | |
448 | } | |
449 | ||
450 | /* receive a response */ | |
451 | static unsigned int azx_get_response(struct hda_codec *codec) | |
452 | { | |
453 | azx_t *chip = codec->bus->private_data; | |
454 | int timeout = 50; | |
455 | ||
456 | while (chip->rirb.cmds) { | |
457 | if (! --timeout) { | |
458 | snd_printk(KERN_ERR "azx_get_response timeout\n"); | |
459 | chip->rirb.rp = azx_readb(chip, RIRBWP); | |
460 | chip->rirb.cmds = 0; | |
461 | return -1; | |
462 | } | |
463 | msleep(1); | |
464 | } | |
465 | return chip->rirb.res; /* the last value */ | |
466 | } | |
467 | ||
468 | #else | |
469 | /* | |
470 | * Use the single immediate command instead of CORB/RIRB for simplicity | |
471 | * | |
472 | * Note: according to Intel, this is not preferred use. The command was | |
473 | * intended for the BIOS only, and may get confused with unsolicited | |
474 | * responses. So, we shouldn't use it for normal operation from the | |
475 | * driver. | |
476 | * I left the codes, however, for debugging/testing purposes. | |
477 | */ | |
478 | ||
479 | #define azx_alloc_cmd_io(chip) 0 | |
480 | #define azx_init_cmd_io(chip) | |
481 | #define azx_free_cmd_io(chip) | |
482 | ||
483 | /* send a command */ | |
484 | static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct, | |
485 | unsigned int verb, unsigned int para) | |
486 | { | |
487 | azx_t *chip = codec->bus->private_data; | |
488 | u32 val; | |
489 | int timeout = 50; | |
490 | ||
491 | val = (u32)(codec->addr & 0x0f) << 28; | |
492 | val |= (u32)direct << 27; | |
493 | val |= (u32)nid << 20; | |
494 | val |= verb << 8; | |
495 | val |= para; | |
496 | ||
497 | while (timeout--) { | |
498 | /* check ICB busy bit */ | |
499 | if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) { | |
500 | /* Clear IRV valid bit */ | |
501 | azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID); | |
502 | azx_writel(chip, IC, val); | |
503 | azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY); | |
504 | return 0; | |
505 | } | |
506 | udelay(1); | |
507 | } | |
508 | snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val); | |
509 | return -EIO; | |
510 | } | |
511 | ||
512 | /* receive a response */ | |
513 | static unsigned int azx_get_response(struct hda_codec *codec) | |
514 | { | |
515 | azx_t *chip = codec->bus->private_data; | |
516 | int timeout = 50; | |
517 | ||
518 | while (timeout--) { | |
519 | /* check IRV busy bit */ | |
520 | if (azx_readw(chip, IRS) & ICH6_IRS_VALID) | |
521 | return azx_readl(chip, IR); | |
522 | udelay(1); | |
523 | } | |
524 | snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS)); | |
525 | return (unsigned int)-1; | |
526 | } | |
527 | ||
528 | #define azx_update_rirb(chip) | |
529 | ||
530 | #endif /* USE_CORB_RIRB */ | |
531 | ||
532 | /* reset codec link */ | |
533 | static int azx_reset(azx_t *chip) | |
534 | { | |
535 | int count; | |
536 | ||
537 | /* reset controller */ | |
538 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); | |
539 | ||
540 | count = 50; | |
541 | while (azx_readb(chip, GCTL) && --count) | |
542 | msleep(1); | |
543 | ||
544 | /* delay for >= 100us for codec PLL to settle per spec | |
545 | * Rev 0.9 section 5.5.1 | |
546 | */ | |
547 | msleep(1); | |
548 | ||
549 | /* Bring controller out of reset */ | |
550 | azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); | |
551 | ||
552 | count = 50; | |
553 | while (! azx_readb(chip, GCTL) && --count) | |
554 | msleep(1); | |
555 | ||
556 | /* Brent Chartrand said to wait >= 540us for codecs to intialize */ | |
557 | msleep(1); | |
558 | ||
559 | /* check to see if controller is ready */ | |
560 | if (! azx_readb(chip, GCTL)) { | |
561 | snd_printd("azx_reset: controller not ready!\n"); | |
562 | return -EBUSY; | |
563 | } | |
564 | ||
565 | /* detect codecs */ | |
566 | if (! chip->codec_mask) { | |
567 | chip->codec_mask = azx_readw(chip, STATESTS); | |
568 | snd_printdd("codec_mask = 0x%x\n", chip->codec_mask); | |
569 | } | |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
574 | ||
575 | /* | |
576 | * Lowlevel interface | |
577 | */ | |
578 | ||
579 | /* enable interrupts */ | |
580 | static void azx_int_enable(azx_t *chip) | |
581 | { | |
582 | /* enable controller CIE and GIE */ | |
583 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | | |
584 | ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); | |
585 | } | |
586 | ||
587 | /* disable interrupts */ | |
588 | static void azx_int_disable(azx_t *chip) | |
589 | { | |
590 | int i; | |
591 | ||
592 | /* disable interrupts in stream descriptor */ | |
593 | for (i = 0; i < MAX_ICH6_DEV; i++) { | |
594 | azx_dev_t *azx_dev = &chip->azx_dev[i]; | |
595 | azx_sd_writeb(azx_dev, SD_CTL, | |
596 | azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); | |
597 | } | |
598 | ||
599 | /* disable SIE for all streams */ | |
600 | azx_writeb(chip, INTCTL, 0); | |
601 | ||
602 | /* disable controller CIE and GIE */ | |
603 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & | |
604 | ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); | |
605 | } | |
606 | ||
607 | /* clear interrupts */ | |
608 | static void azx_int_clear(azx_t *chip) | |
609 | { | |
610 | int i; | |
611 | ||
612 | /* clear stream status */ | |
613 | for (i = 0; i < MAX_ICH6_DEV; i++) { | |
614 | azx_dev_t *azx_dev = &chip->azx_dev[i]; | |
615 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); | |
616 | } | |
617 | ||
618 | /* clear STATESTS */ | |
619 | azx_writeb(chip, STATESTS, STATESTS_INT_MASK); | |
620 | ||
621 | /* clear rirb status */ | |
622 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
623 | ||
624 | /* clear int status */ | |
625 | azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); | |
626 | } | |
627 | ||
628 | /* start a stream */ | |
629 | static void azx_stream_start(azx_t *chip, azx_dev_t *azx_dev) | |
630 | { | |
631 | /* enable SIE */ | |
632 | azx_writeb(chip, INTCTL, | |
633 | azx_readb(chip, INTCTL) | (1 << azx_dev->index)); | |
634 | /* set DMA start and interrupt mask */ | |
635 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | | |
636 | SD_CTL_DMA_START | SD_INT_MASK); | |
637 | } | |
638 | ||
639 | /* stop a stream */ | |
640 | static void azx_stream_stop(azx_t *chip, azx_dev_t *azx_dev) | |
641 | { | |
642 | /* stop DMA */ | |
643 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & | |
644 | ~(SD_CTL_DMA_START | SD_INT_MASK)); | |
645 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | |
646 | /* disable SIE */ | |
647 | azx_writeb(chip, INTCTL, | |
648 | azx_readb(chip, INTCTL) & ~(1 << azx_dev->index)); | |
649 | } | |
650 | ||
651 | ||
652 | /* | |
653 | * initialize the chip | |
654 | */ | |
655 | static void azx_init_chip(azx_t *chip) | |
656 | { | |
f5d40b30 | 657 | unsigned char tcsel_reg, ati_misc_cntl2; |
1da177e4 LT |
658 | |
659 | /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) | |
660 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | |
661 | * Ensuring these bits are 0 clears playback static on some HD Audio codecs | |
662 | */ | |
663 | pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &tcsel_reg); | |
664 | pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, tcsel_reg & 0xf8); | |
665 | ||
666 | /* reset controller */ | |
667 | azx_reset(chip); | |
668 | ||
669 | /* initialize interrupts */ | |
670 | azx_int_clear(chip); | |
671 | azx_int_enable(chip); | |
672 | ||
673 | /* initialize the codec command I/O */ | |
674 | azx_init_cmd_io(chip); | |
675 | ||
c74db86b TI |
676 | if (chip->position_fix == POS_FIX_POSBUF) { |
677 | /* program the position buffer */ | |
678 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); | |
679 | azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr)); | |
680 | } | |
f5d40b30 FL |
681 | |
682 | /* For ATI SB450 azalia HD audio, we need to enable snoop */ | |
683 | if (chip->pci->vendor == PCI_VENDOR_ID_ATI && | |
684 | chip->pci->device == ATI_SB450_HDAUDIO_PCI_DEVICE_ID) { | |
685 | pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, | |
686 | &ati_misc_cntl2); | |
687 | pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, | |
688 | (ati_misc_cntl2 & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP); | |
689 | } | |
1da177e4 LT |
690 | } |
691 | ||
692 | ||
693 | /* | |
694 | * interrupt handler | |
695 | */ | |
696 | static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs) | |
697 | { | |
698 | azx_t *chip = dev_id; | |
699 | azx_dev_t *azx_dev; | |
700 | u32 status; | |
701 | int i; | |
702 | ||
703 | spin_lock(&chip->reg_lock); | |
704 | ||
705 | status = azx_readl(chip, INTSTS); | |
706 | if (status == 0) { | |
707 | spin_unlock(&chip->reg_lock); | |
708 | return IRQ_NONE; | |
709 | } | |
710 | ||
711 | for (i = 0; i < MAX_ICH6_DEV; i++) { | |
712 | azx_dev = &chip->azx_dev[i]; | |
713 | if (status & azx_dev->sd_int_sta_mask) { | |
714 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); | |
715 | if (azx_dev->substream && azx_dev->running) { | |
716 | spin_unlock(&chip->reg_lock); | |
717 | snd_pcm_period_elapsed(azx_dev->substream); | |
718 | spin_lock(&chip->reg_lock); | |
719 | } | |
720 | } | |
721 | } | |
722 | ||
723 | /* clear rirb int */ | |
724 | status = azx_readb(chip, RIRBSTS); | |
725 | if (status & RIRB_INT_MASK) { | |
726 | if (status & RIRB_INT_RESPONSE) | |
727 | azx_update_rirb(chip); | |
728 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
729 | } | |
730 | ||
731 | #if 0 | |
732 | /* clear state status int */ | |
733 | if (azx_readb(chip, STATESTS) & 0x04) | |
734 | azx_writeb(chip, STATESTS, 0x04); | |
735 | #endif | |
736 | spin_unlock(&chip->reg_lock); | |
737 | ||
738 | return IRQ_HANDLED; | |
739 | } | |
740 | ||
741 | ||
742 | /* | |
743 | * set up BDL entries | |
744 | */ | |
745 | static void azx_setup_periods(azx_dev_t *azx_dev) | |
746 | { | |
747 | u32 *bdl = azx_dev->bdl; | |
748 | dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr; | |
749 | int idx; | |
750 | ||
751 | /* reset BDL address */ | |
752 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
753 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
754 | ||
755 | /* program the initial BDL entries */ | |
756 | for (idx = 0; idx < azx_dev->frags; idx++) { | |
757 | unsigned int off = idx << 2; /* 4 dword step */ | |
758 | dma_addr_t addr = dma_addr + idx * azx_dev->fragsize; | |
759 | /* program the address field of the BDL entry */ | |
760 | bdl[off] = cpu_to_le32((u32)addr); | |
761 | bdl[off+1] = cpu_to_le32(upper_32bit(addr)); | |
762 | ||
763 | /* program the size field of the BDL entry */ | |
764 | bdl[off+2] = cpu_to_le32(azx_dev->fragsize); | |
765 | ||
766 | /* program the IOC to enable interrupt when buffer completes */ | |
767 | bdl[off+3] = cpu_to_le32(0x01); | |
768 | } | |
769 | } | |
770 | ||
771 | /* | |
772 | * set up the SD for streaming | |
773 | */ | |
774 | static int azx_setup_controller(azx_t *chip, azx_dev_t *azx_dev) | |
775 | { | |
776 | unsigned char val; | |
777 | int timeout; | |
778 | ||
779 | /* make sure the run bit is zero for SD */ | |
780 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START); | |
781 | /* reset stream */ | |
782 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET); | |
783 | udelay(3); | |
784 | timeout = 300; | |
785 | while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
786 | --timeout) | |
787 | ; | |
788 | val &= ~SD_CTL_STREAM_RESET; | |
789 | azx_sd_writeb(azx_dev, SD_CTL, val); | |
790 | udelay(3); | |
791 | ||
792 | timeout = 300; | |
793 | /* waiting for hardware to report that the stream is out of reset */ | |
794 | while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
795 | --timeout) | |
796 | ; | |
797 | ||
798 | /* program the stream_tag */ | |
799 | azx_sd_writel(azx_dev, SD_CTL, | |
800 | (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) | | |
801 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); | |
802 | ||
803 | /* program the length of samples in cyclic buffer */ | |
804 | azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); | |
805 | ||
806 | /* program the stream format */ | |
807 | /* this value needs to be the same as the one programmed */ | |
808 | azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); | |
809 | ||
810 | /* program the stream LVI (last valid index) of the BDL */ | |
811 | azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); | |
812 | ||
813 | /* program the BDL address */ | |
814 | /* lower BDL address */ | |
815 | azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr); | |
816 | /* upper BDL address */ | |
817 | azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr)); | |
818 | ||
c74db86b TI |
819 | if (chip->position_fix == POS_FIX_POSBUF) { |
820 | /* enable the position buffer */ | |
821 | if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) | |
822 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); | |
823 | } | |
824 | ||
1da177e4 LT |
825 | /* set the interrupt enable bits in the descriptor control register */ |
826 | azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); | |
827 | ||
828 | return 0; | |
829 | } | |
830 | ||
831 | ||
832 | /* | |
833 | * Codec initialization | |
834 | */ | |
835 | ||
836 | static int __devinit azx_codec_create(azx_t *chip, const char *model) | |
837 | { | |
838 | struct hda_bus_template bus_temp; | |
839 | int c, codecs, err; | |
840 | ||
841 | memset(&bus_temp, 0, sizeof(bus_temp)); | |
842 | bus_temp.private_data = chip; | |
843 | bus_temp.modelname = model; | |
844 | bus_temp.pci = chip->pci; | |
845 | bus_temp.ops.command = azx_send_cmd; | |
846 | bus_temp.ops.get_response = azx_get_response; | |
847 | ||
848 | if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0) | |
849 | return err; | |
850 | ||
851 | codecs = 0; | |
852 | for (c = 0; c < AZX_MAX_CODECS; c++) { | |
853 | if (chip->codec_mask & (1 << c)) { | |
854 | err = snd_hda_codec_new(chip->bus, c, NULL); | |
855 | if (err < 0) | |
856 | continue; | |
857 | codecs++; | |
858 | } | |
859 | } | |
860 | if (! codecs) { | |
861 | snd_printk(KERN_ERR SFX "no codecs initialized\n"); | |
862 | return -ENXIO; | |
863 | } | |
864 | ||
865 | return 0; | |
866 | } | |
867 | ||
868 | ||
869 | /* | |
870 | * PCM support | |
871 | */ | |
872 | ||
873 | /* assign a stream for the PCM */ | |
874 | static inline azx_dev_t *azx_assign_device(azx_t *chip, int stream) | |
875 | { | |
876 | int dev, i; | |
877 | dev = stream == SNDRV_PCM_STREAM_PLAYBACK ? 4 : 0; | |
878 | for (i = 0; i < 4; i++, dev++) | |
879 | if (! chip->azx_dev[dev].opened) { | |
880 | chip->azx_dev[dev].opened = 1; | |
881 | return &chip->azx_dev[dev]; | |
882 | } | |
883 | return NULL; | |
884 | } | |
885 | ||
886 | /* release the assigned stream */ | |
887 | static inline void azx_release_device(azx_dev_t *azx_dev) | |
888 | { | |
889 | azx_dev->opened = 0; | |
890 | } | |
891 | ||
892 | static snd_pcm_hardware_t azx_pcm_hw = { | |
893 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
894 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
895 | SNDRV_PCM_INFO_MMAP_VALID | | |
896 | SNDRV_PCM_INFO_PAUSE | | |
897 | SNDRV_PCM_INFO_RESUME), | |
898 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
899 | .rates = SNDRV_PCM_RATE_48000, | |
900 | .rate_min = 48000, | |
901 | .rate_max = 48000, | |
902 | .channels_min = 2, | |
903 | .channels_max = 2, | |
904 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, | |
905 | .period_bytes_min = 128, | |
906 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | |
907 | .periods_min = 2, | |
908 | .periods_max = AZX_MAX_FRAG, | |
909 | .fifo_size = 0, | |
910 | }; | |
911 | ||
912 | struct azx_pcm { | |
913 | azx_t *chip; | |
914 | struct hda_codec *codec; | |
915 | struct hda_pcm_stream *hinfo[2]; | |
916 | }; | |
917 | ||
918 | static int azx_pcm_open(snd_pcm_substream_t *substream) | |
919 | { | |
920 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
921 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
922 | azx_t *chip = apcm->chip; | |
923 | azx_dev_t *azx_dev; | |
924 | snd_pcm_runtime_t *runtime = substream->runtime; | |
925 | unsigned long flags; | |
926 | int err; | |
927 | ||
928 | down(&chip->open_mutex); | |
929 | azx_dev = azx_assign_device(chip, substream->stream); | |
930 | if (azx_dev == NULL) { | |
931 | up(&chip->open_mutex); | |
932 | return -EBUSY; | |
933 | } | |
934 | runtime->hw = azx_pcm_hw; | |
935 | runtime->hw.channels_min = hinfo->channels_min; | |
936 | runtime->hw.channels_max = hinfo->channels_max; | |
937 | runtime->hw.formats = hinfo->formats; | |
938 | runtime->hw.rates = hinfo->rates; | |
939 | snd_pcm_limit_hw_rates(runtime); | |
940 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | |
941 | if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) { | |
942 | azx_release_device(azx_dev); | |
943 | up(&chip->open_mutex); | |
944 | return err; | |
945 | } | |
946 | spin_lock_irqsave(&chip->reg_lock, flags); | |
947 | azx_dev->substream = substream; | |
948 | azx_dev->running = 0; | |
949 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
950 | ||
951 | runtime->private_data = azx_dev; | |
952 | up(&chip->open_mutex); | |
953 | return 0; | |
954 | } | |
955 | ||
956 | static int azx_pcm_close(snd_pcm_substream_t *substream) | |
957 | { | |
958 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
959 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
960 | azx_t *chip = apcm->chip; | |
961 | azx_dev_t *azx_dev = get_azx_dev(substream); | |
962 | unsigned long flags; | |
963 | ||
964 | down(&chip->open_mutex); | |
965 | spin_lock_irqsave(&chip->reg_lock, flags); | |
966 | azx_dev->substream = NULL; | |
967 | azx_dev->running = 0; | |
968 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
969 | azx_release_device(azx_dev); | |
970 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
971 | up(&chip->open_mutex); | |
972 | return 0; | |
973 | } | |
974 | ||
975 | static int azx_pcm_hw_params(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *hw_params) | |
976 | { | |
977 | return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
978 | } | |
979 | ||
980 | static int azx_pcm_hw_free(snd_pcm_substream_t *substream) | |
981 | { | |
982 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
983 | azx_dev_t *azx_dev = get_azx_dev(substream); | |
984 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
985 | ||
986 | /* reset BDL address */ | |
987 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
988 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
989 | azx_sd_writel(azx_dev, SD_CTL, 0); | |
990 | ||
991 | hinfo->ops.cleanup(hinfo, apcm->codec, substream); | |
992 | ||
993 | return snd_pcm_lib_free_pages(substream); | |
994 | } | |
995 | ||
996 | static int azx_pcm_prepare(snd_pcm_substream_t *substream) | |
997 | { | |
998 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
999 | azx_t *chip = apcm->chip; | |
1000 | azx_dev_t *azx_dev = get_azx_dev(substream); | |
1001 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
1002 | snd_pcm_runtime_t *runtime = substream->runtime; | |
1003 | ||
1004 | azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream); | |
1005 | azx_dev->fragsize = snd_pcm_lib_period_bytes(substream); | |
1006 | azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize; | |
1007 | azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate, | |
1008 | runtime->channels, | |
1009 | runtime->format, | |
1010 | hinfo->maxbps); | |
1011 | if (! azx_dev->format_val) { | |
1012 | snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n", | |
1013 | runtime->rate, runtime->channels, runtime->format); | |
1014 | return -EINVAL; | |
1015 | } | |
1016 | ||
1017 | snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n", | |
1018 | azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val); | |
1019 | azx_setup_periods(azx_dev); | |
1020 | azx_setup_controller(chip, azx_dev); | |
1021 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1022 | azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; | |
1023 | else | |
1024 | azx_dev->fifo_size = 0; | |
1025 | ||
1026 | return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag, | |
1027 | azx_dev->format_val, substream); | |
1028 | } | |
1029 | ||
1030 | static int azx_pcm_trigger(snd_pcm_substream_t *substream, int cmd) | |
1031 | { | |
1032 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1033 | azx_dev_t *azx_dev = get_azx_dev(substream); | |
1034 | azx_t *chip = apcm->chip; | |
1035 | int err = 0; | |
1036 | ||
1037 | spin_lock(&chip->reg_lock); | |
1038 | switch (cmd) { | |
1039 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
1040 | case SNDRV_PCM_TRIGGER_RESUME: | |
1041 | case SNDRV_PCM_TRIGGER_START: | |
1042 | azx_stream_start(chip, azx_dev); | |
1043 | azx_dev->running = 1; | |
1044 | break; | |
1045 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
1046 | case SNDRV_PCM_TRIGGER_STOP: | |
1047 | azx_stream_stop(chip, azx_dev); | |
1048 | azx_dev->running = 0; | |
1049 | break; | |
1050 | default: | |
1051 | err = -EINVAL; | |
1052 | } | |
1053 | spin_unlock(&chip->reg_lock); | |
1054 | if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH || | |
1055 | cmd == SNDRV_PCM_TRIGGER_STOP) { | |
1056 | int timeout = 5000; | |
1057 | while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout) | |
1058 | ; | |
1059 | } | |
1060 | return err; | |
1061 | } | |
1062 | ||
1063 | static snd_pcm_uframes_t azx_pcm_pointer(snd_pcm_substream_t *substream) | |
1064 | { | |
c74db86b TI |
1065 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
1066 | azx_t *chip = apcm->chip; | |
1da177e4 LT |
1067 | azx_dev_t *azx_dev = get_azx_dev(substream); |
1068 | unsigned int pos; | |
1069 | ||
c74db86b TI |
1070 | if (chip->position_fix == POS_FIX_POSBUF) { |
1071 | /* use the position buffer */ | |
1072 | pos = *azx_dev->posbuf; | |
1073 | } else { | |
1074 | /* read LPIB */ | |
1075 | pos = azx_sd_readl(azx_dev, SD_LPIB); | |
1076 | if (chip->position_fix == POS_FIX_FIFO) | |
1077 | pos += azx_dev->fifo_size; | |
1078 | } | |
1da177e4 LT |
1079 | if (pos >= azx_dev->bufsize) |
1080 | pos = 0; | |
1081 | return bytes_to_frames(substream->runtime, pos); | |
1082 | } | |
1083 | ||
1084 | static snd_pcm_ops_t azx_pcm_ops = { | |
1085 | .open = azx_pcm_open, | |
1086 | .close = azx_pcm_close, | |
1087 | .ioctl = snd_pcm_lib_ioctl, | |
1088 | .hw_params = azx_pcm_hw_params, | |
1089 | .hw_free = azx_pcm_hw_free, | |
1090 | .prepare = azx_pcm_prepare, | |
1091 | .trigger = azx_pcm_trigger, | |
1092 | .pointer = azx_pcm_pointer, | |
1093 | }; | |
1094 | ||
1095 | static void azx_pcm_free(snd_pcm_t *pcm) | |
1096 | { | |
1097 | kfree(pcm->private_data); | |
1098 | } | |
1099 | ||
1100 | static int __devinit create_codec_pcm(azx_t *chip, struct hda_codec *codec, | |
1101 | struct hda_pcm *cpcm, int pcm_dev) | |
1102 | { | |
1103 | int err; | |
1104 | snd_pcm_t *pcm; | |
1105 | struct azx_pcm *apcm; | |
1106 | ||
1107 | snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL); | |
1108 | snd_assert(cpcm->name, return -EINVAL); | |
1109 | ||
1110 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, | |
1111 | cpcm->stream[0].substreams, cpcm->stream[1].substreams, | |
1112 | &pcm); | |
1113 | if (err < 0) | |
1114 | return err; | |
1115 | strcpy(pcm->name, cpcm->name); | |
1116 | apcm = kmalloc(sizeof(*apcm), GFP_KERNEL); | |
1117 | if (apcm == NULL) | |
1118 | return -ENOMEM; | |
1119 | apcm->chip = chip; | |
1120 | apcm->codec = codec; | |
1121 | apcm->hinfo[0] = &cpcm->stream[0]; | |
1122 | apcm->hinfo[1] = &cpcm->stream[1]; | |
1123 | pcm->private_data = apcm; | |
1124 | pcm->private_free = azx_pcm_free; | |
1125 | if (cpcm->stream[0].substreams) | |
1126 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops); | |
1127 | if (cpcm->stream[1].substreams) | |
1128 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops); | |
1129 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1130 | snd_dma_pci_data(chip->pci), | |
1131 | 1024 * 64, 1024 * 128); | |
1132 | chip->pcm[pcm_dev] = pcm; | |
1133 | ||
1134 | return 0; | |
1135 | } | |
1136 | ||
1137 | static int __devinit azx_pcm_create(azx_t *chip) | |
1138 | { | |
1139 | struct list_head *p; | |
1140 | struct hda_codec *codec; | |
1141 | int c, err; | |
1142 | int pcm_dev; | |
1143 | ||
1144 | if ((err = snd_hda_build_pcms(chip->bus)) < 0) | |
1145 | return err; | |
1146 | ||
1147 | pcm_dev = 0; | |
1148 | list_for_each(p, &chip->bus->codec_list) { | |
1149 | codec = list_entry(p, struct hda_codec, list); | |
1150 | for (c = 0; c < codec->num_pcms; c++) { | |
1151 | if (pcm_dev >= AZX_MAX_PCMS) { | |
1152 | snd_printk(KERN_ERR SFX "Too many PCMs\n"); | |
1153 | return -EINVAL; | |
1154 | } | |
1155 | err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev); | |
1156 | if (err < 0) | |
1157 | return err; | |
1158 | pcm_dev++; | |
1159 | } | |
1160 | } | |
1161 | return 0; | |
1162 | } | |
1163 | ||
1164 | /* | |
1165 | * mixer creation - all stuff is implemented in hda module | |
1166 | */ | |
1167 | static int __devinit azx_mixer_create(azx_t *chip) | |
1168 | { | |
1169 | return snd_hda_build_controls(chip->bus); | |
1170 | } | |
1171 | ||
1172 | ||
1173 | /* | |
1174 | * initialize SD streams | |
1175 | */ | |
1176 | static int __devinit azx_init_stream(azx_t *chip) | |
1177 | { | |
1178 | int i; | |
1179 | ||
1180 | /* initialize each stream (aka device) | |
1181 | * assign the starting bdl address to each stream (device) and initialize | |
1182 | */ | |
1183 | for (i = 0; i < MAX_ICH6_DEV; i++) { | |
1184 | unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4); | |
1185 | azx_dev_t *azx_dev = &chip->azx_dev[i]; | |
1186 | azx_dev->bdl = (u32 *)(chip->bdl.area + off); | |
1187 | azx_dev->bdl_addr = chip->bdl.addr + off; | |
c74db86b TI |
1188 | if (chip->position_fix == POS_FIX_POSBUF) |
1189 | azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8); | |
1da177e4 LT |
1190 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
1191 | azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); | |
1192 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ | |
1193 | azx_dev->sd_int_sta_mask = 1 << i; | |
1194 | /* stream tag: must be non-zero and unique */ | |
1195 | azx_dev->index = i; | |
1196 | azx_dev->stream_tag = i + 1; | |
1197 | } | |
1198 | ||
1199 | return 0; | |
1200 | } | |
1201 | ||
1202 | ||
1203 | #ifdef CONFIG_PM | |
1204 | /* | |
1205 | * power management | |
1206 | */ | |
1207 | static int azx_suspend(snd_card_t *card, pm_message_t state) | |
1208 | { | |
1209 | azx_t *chip = card->pm_private_data; | |
1210 | int i; | |
1211 | ||
1212 | for (i = 0; i < chip->pcm_devs; i++) | |
1213 | if (chip->pcm[i]) | |
1214 | snd_pcm_suspend_all(chip->pcm[i]); | |
1215 | snd_hda_suspend(chip->bus, state); | |
1216 | azx_free_cmd_io(chip); | |
1217 | pci_disable_device(chip->pci); | |
1218 | return 0; | |
1219 | } | |
1220 | ||
1221 | static int azx_resume(snd_card_t *card) | |
1222 | { | |
1223 | azx_t *chip = card->pm_private_data; | |
1224 | ||
1225 | pci_enable_device(chip->pci); | |
1226 | pci_set_master(chip->pci); | |
1227 | azx_init_chip(chip); | |
1228 | snd_hda_resume(chip->bus); | |
1229 | return 0; | |
1230 | } | |
1231 | #endif /* CONFIG_PM */ | |
1232 | ||
1233 | ||
1234 | /* | |
1235 | * destructor | |
1236 | */ | |
1237 | static int azx_free(azx_t *chip) | |
1238 | { | |
ce43fbae | 1239 | if (chip->initialized) { |
1da177e4 LT |
1240 | int i; |
1241 | ||
1242 | for (i = 0; i < MAX_ICH6_DEV; i++) | |
1243 | azx_stream_stop(chip, &chip->azx_dev[i]); | |
1244 | ||
1245 | /* disable interrupts */ | |
1246 | azx_int_disable(chip); | |
1247 | azx_int_clear(chip); | |
1248 | ||
1249 | /* disable CORB/RIRB */ | |
1250 | azx_free_cmd_io(chip); | |
1251 | ||
1252 | /* disable position buffer */ | |
1253 | azx_writel(chip, DPLBASE, 0); | |
1254 | azx_writel(chip, DPUBASE, 0); | |
1255 | ||
1256 | /* wait a little for interrupts to finish */ | |
1257 | msleep(1); | |
1258 | ||
1259 | iounmap(chip->remap_addr); | |
1260 | } | |
1261 | ||
1262 | if (chip->irq >= 0) | |
1263 | free_irq(chip->irq, (void*)chip); | |
1264 | ||
1265 | if (chip->bdl.area) | |
1266 | snd_dma_free_pages(&chip->bdl); | |
1267 | if (chip->rb.area) | |
1268 | snd_dma_free_pages(&chip->rb); | |
1da177e4 LT |
1269 | if (chip->posbuf.area) |
1270 | snd_dma_free_pages(&chip->posbuf); | |
1da177e4 LT |
1271 | pci_release_regions(chip->pci); |
1272 | pci_disable_device(chip->pci); | |
1273 | kfree(chip); | |
1274 | ||
1275 | return 0; | |
1276 | } | |
1277 | ||
1278 | static int azx_dev_free(snd_device_t *device) | |
1279 | { | |
1280 | return azx_free(device->device_data); | |
1281 | } | |
1282 | ||
1283 | /* | |
1284 | * constructor | |
1285 | */ | |
c74db86b TI |
1286 | static int __devinit azx_create(snd_card_t *card, struct pci_dev *pci, |
1287 | int posfix, azx_t **rchip) | |
1da177e4 LT |
1288 | { |
1289 | azx_t *chip; | |
1290 | int err = 0; | |
1291 | static snd_device_ops_t ops = { | |
1292 | .dev_free = azx_dev_free, | |
1293 | }; | |
1294 | ||
1295 | *rchip = NULL; | |
1296 | ||
1297 | if ((err = pci_enable_device(pci)) < 0) | |
1298 | return err; | |
1299 | ||
1300 | chip = kcalloc(1, sizeof(*chip), GFP_KERNEL); | |
1301 | ||
1302 | if (NULL == chip) { | |
1303 | snd_printk(KERN_ERR SFX "cannot allocate chip\n"); | |
1304 | pci_disable_device(pci); | |
1305 | return -ENOMEM; | |
1306 | } | |
1307 | ||
1308 | spin_lock_init(&chip->reg_lock); | |
1309 | init_MUTEX(&chip->open_mutex); | |
1310 | chip->card = card; | |
1311 | chip->pci = pci; | |
1312 | chip->irq = -1; | |
1313 | ||
c74db86b TI |
1314 | chip->position_fix = posfix; |
1315 | ||
1da177e4 LT |
1316 | if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) { |
1317 | kfree(chip); | |
1318 | pci_disable_device(pci); | |
1319 | return err; | |
1320 | } | |
1321 | ||
1322 | chip->addr = pci_resource_start(pci,0); | |
1323 | chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0)); | |
1324 | if (chip->remap_addr == NULL) { | |
1325 | snd_printk(KERN_ERR SFX "ioremap error\n"); | |
1326 | err = -ENXIO; | |
1327 | goto errout; | |
1328 | } | |
1329 | ||
1330 | if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ, | |
1331 | "HDA Intel", (void*)chip)) { | |
1332 | snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq); | |
1333 | err = -EBUSY; | |
1334 | goto errout; | |
1335 | } | |
1336 | chip->irq = pci->irq; | |
1337 | ||
1338 | pci_set_master(pci); | |
1339 | synchronize_irq(chip->irq); | |
1340 | ||
1341 | /* allocate memory for the BDL for each stream */ | |
1342 | if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
1343 | PAGE_SIZE, &chip->bdl)) < 0) { | |
1344 | snd_printk(KERN_ERR SFX "cannot allocate BDL\n"); | |
1345 | goto errout; | |
1346 | } | |
c74db86b TI |
1347 | if (chip->position_fix == POS_FIX_POSBUF) { |
1348 | /* allocate memory for the position buffer */ | |
1349 | if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
1350 | MAX_ICH6_DEV * 8, &chip->posbuf)) < 0) { | |
1351 | snd_printk(KERN_ERR SFX "cannot allocate posbuf\n"); | |
1352 | goto errout; | |
1353 | } | |
1da177e4 | 1354 | } |
1da177e4 LT |
1355 | /* allocate CORB/RIRB */ |
1356 | if ((err = azx_alloc_cmd_io(chip)) < 0) | |
1357 | goto errout; | |
1358 | ||
1359 | /* initialize streams */ | |
1360 | azx_init_stream(chip); | |
1361 | ||
1362 | /* initialize chip */ | |
1363 | azx_init_chip(chip); | |
1364 | ||
ce43fbae TI |
1365 | chip->initialized = 1; |
1366 | ||
1da177e4 LT |
1367 | /* codec detection */ |
1368 | if (! chip->codec_mask) { | |
1369 | snd_printk(KERN_ERR SFX "no codecs found!\n"); | |
1370 | err = -ENODEV; | |
1371 | goto errout; | |
1372 | } | |
1373 | ||
1374 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) { | |
1375 | snd_printk(KERN_ERR SFX "Error creating device [card]!\n"); | |
1376 | goto errout; | |
1377 | } | |
1378 | ||
1379 | *rchip = chip; | |
1380 | return 0; | |
1381 | ||
1382 | errout: | |
1383 | azx_free(chip); | |
1384 | return err; | |
1385 | } | |
1386 | ||
1387 | static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) | |
1388 | { | |
1389 | static int dev; | |
1390 | snd_card_t *card; | |
1391 | azx_t *chip; | |
1392 | int err = 0; | |
1393 | ||
1394 | if (dev >= SNDRV_CARDS) | |
1395 | return -ENODEV; | |
1396 | if (! enable[dev]) { | |
1397 | dev++; | |
1398 | return -ENOENT; | |
1399 | } | |
1400 | ||
1401 | card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); | |
1402 | if (NULL == card) { | |
1403 | snd_printk(KERN_ERR SFX "Error creating card!\n"); | |
1404 | return -ENOMEM; | |
1405 | } | |
1406 | ||
c74db86b | 1407 | if ((err = azx_create(card, pci, position_fix[dev], &chip)) < 0) { |
1da177e4 LT |
1408 | snd_card_free(card); |
1409 | return err; | |
1410 | } | |
1411 | ||
1412 | strcpy(card->driver, "HDA-Intel"); | |
1413 | strcpy(card->shortname, "HDA Intel"); | |
1414 | sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq); | |
1415 | ||
1416 | /* create codec instances */ | |
1417 | if ((err = azx_codec_create(chip, model[dev])) < 0) { | |
1418 | snd_card_free(card); | |
1419 | return err; | |
1420 | } | |
1421 | ||
1422 | /* create PCM streams */ | |
1423 | if ((err = azx_pcm_create(chip)) < 0) { | |
1424 | snd_card_free(card); | |
1425 | return err; | |
1426 | } | |
1427 | ||
1428 | /* create mixer controls */ | |
1429 | if ((err = azx_mixer_create(chip)) < 0) { | |
1430 | snd_card_free(card); | |
1431 | return err; | |
1432 | } | |
1433 | ||
1434 | snd_card_set_pm_callback(card, azx_suspend, azx_resume, chip); | |
1435 | snd_card_set_dev(card, &pci->dev); | |
1436 | ||
1437 | if ((err = snd_card_register(card)) < 0) { | |
1438 | snd_card_free(card); | |
1439 | return err; | |
1440 | } | |
1441 | ||
1442 | pci_set_drvdata(pci, card); | |
1443 | dev++; | |
1444 | ||
1445 | return err; | |
1446 | } | |
1447 | ||
1448 | static void __devexit azx_remove(struct pci_dev *pci) | |
1449 | { | |
1450 | snd_card_free(pci_get_drvdata(pci)); | |
1451 | pci_set_drvdata(pci, NULL); | |
1452 | } | |
1453 | ||
1454 | /* PCI IDs */ | |
1455 | static struct pci_device_id azx_ids[] = { | |
1456 | { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH6 */ | |
1457 | { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH7 */ | |
2f1b3818 | 1458 | { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ESB2 */ |
f5d40b30 | 1459 | { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ATI SB450 */ |
fc20a562 | 1460 | { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* VIA VT8251/VT8237A */ |
e9edcee0 | 1461 | { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ALI 5461? */ |
1da177e4 LT |
1462 | { 0, } |
1463 | }; | |
1464 | MODULE_DEVICE_TABLE(pci, azx_ids); | |
1465 | ||
1466 | /* pci_driver definition */ | |
1467 | static struct pci_driver driver = { | |
1468 | .name = "HDA Intel", | |
1469 | .id_table = azx_ids, | |
1470 | .probe = azx_probe, | |
1471 | .remove = __devexit_p(azx_remove), | |
1472 | SND_PCI_PM_CALLBACKS | |
1473 | }; | |
1474 | ||
1475 | static int __init alsa_card_azx_init(void) | |
1476 | { | |
01d25d46 | 1477 | return pci_register_driver(&driver); |
1da177e4 LT |
1478 | } |
1479 | ||
1480 | static void __exit alsa_card_azx_exit(void) | |
1481 | { | |
1482 | pci_unregister_driver(&driver); | |
1483 | } | |
1484 | ||
1485 | module_init(alsa_card_azx_init) | |
1486 | module_exit(alsa_card_azx_exit) |