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ALSA: hda - Fix yet another race of vga_switcheroo registration
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4
LT		 64#include "hda_codec.h"
65
66
5aba4f8e
TI		 67static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
68static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 69static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 70static char *model[SNDRV_CARDS];
1dac6695 71static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 72static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 73static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 74static int probe_only[SNDRV_CARDS];
26a6cb6c 75static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 76static bool single_cmd;
71623855 77static int enable_msi = -1;
4ea6fbc8
TI		 78#ifdef CONFIG_SND_HDA_PATCH_LOADER
79static char *patch[SNDRV_CARDS];
80#endif
2dca0bba 81#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 82static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 83 CONFIG_SND_HDA_INPUT_BEEP_MODE};
84#endif
1da177e4 85
5aba4f8e 86module_param_array(index, int, NULL, 0444);
1da177e4 87MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 88module_param_array(id, charp, NULL, 0444);
1da177e4 89MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 90module_param_array(enable, bool, NULL, 0444);
91MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
92module_param_array(model, charp, NULL, 0444);
1da177e4 93MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 94module_param_array(position_fix, int, NULL, 0444);
4cb36310 95MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 96 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 97module_param_array(bdl_pos_adj, int, NULL, 0644);
98MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 99module_param_array(probe_mask, int, NULL, 0444);
606ad75f 100MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 101module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 102MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 103module_param_array(jackpoll_ms, int, NULL, 0444);
104MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 105module_param(single_cmd, bool, 0444);
d01ce99f
TI		 106MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
107 "(for debugging only).");
ac9ef6cf 108module_param(enable_msi, bint, 0444);
134a11f0 109MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 110#ifdef CONFIG_SND_HDA_PATCH_LOADER
111module_param_array(patch, charp, NULL, 0444);
112MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
113#endif
2dca0bba 114#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 115module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 116MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 117 "(0=off, 1=on) (default=1).");
2dca0bba 118#endif
606ad75f 119
83012a7c 120#ifdef CONFIG_PM
65fcd41d
TI		 121static int param_set_xint(const char *val, const struct kernel_param *kp);
122static struct kernel_param_ops param_ops_xint = {
123 .set = param_set_xint,
124 .get = param_get_int,
125};
126#define param_check_xint param_check_int
127
fee2fba3 128static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 129module_param(power_save, xint, 0644);
fee2fba3
TI		 130MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
131 "(in second, 0 = disable).");
1da177e4 132
dee1b66c
TI		 133/* reset the HD-audio controller in power save mode.
134 * this may give more power-saving, but will take longer time to
135 * wake up.
136 */
a67ff6a5 137static bool power_save_controller = 1;
dee1b66c
TI		 138module_param(power_save_controller, bool, 0644);
139MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
83012a7c 140#endif /* CONFIG_PM */
dee1b66c 141
7bfe059e
TI		 142static int align_buffer_size = -1;
143module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 144MODULE_PARM_DESC(align_buffer_size,
145 "Force buffer and period sizes to be multiple of 128 bytes.");
146
27fe48d9
TI		 147#ifdef CONFIG_X86
148static bool hda_snoop = true;
149module_param_named(snoop, hda_snoop, bool, 0444);
150MODULE_PARM_DESC(snoop, "Enable/disable snooping");
151#define azx_snoop(chip) (chip)->snoop
152#else
153#define hda_snoop true
154#define azx_snoop(chip) true
155#endif
156
157
1da177e4
LT		 158MODULE_LICENSE("GPL");
159MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
160 "{Intel, ICH6M},"
2f1b3818 161 "{Intel, ICH7},"
f5d40b30 162 "{Intel, ESB2},"
d2981393 163 "{Intel, ICH8},"
f9cc8a8b 164 "{Intel, ICH9},"
c34f5a04 165 "{Intel, ICH10},"
b29c2360 166 "{Intel, PCH},"
d2f2fcd2 167 "{Intel, CPT},"
d2edeb7c 168 "{Intel, PPT},"
8bc039a1 169 "{Intel, LPT},"
144dad99 170 "{Intel, LPT_LP},"
e926f2c8 171 "{Intel, HPT},"
cea310e8 172 "{Intel, PBG},"
4979bca9 173 "{Intel, SCH},"
fc20a562 174 "{ATI, SB450},"
89be83f8 175 "{ATI, SB600},"
778b6e1b 176 "{ATI, RS600},"
5b15c95f 177 "{ATI, RS690},"
e6db1119
WL		 178 "{ATI, RS780},"
179 "{ATI, R600},"
2797f724
HRK		 180 "{ATI, RV630},"
181 "{ATI, RV610},"
27da1834
WL		 182 "{ATI, RV670},"
183 "{ATI, RV635},"
184 "{ATI, RV620},"
185 "{ATI, RV770},"
fc20a562 186 "{VIA, VT8251},"
47672310 187 "{VIA, VT8237A},"
07e4ca50
TI		 188 "{SiS, SIS966},"
189 "{ULI, M5461}}");
1da177e4
LT		 190MODULE_DESCRIPTION("Intel HDA driver");
191
4abc1cc2
TI		 192#ifdef CONFIG_SND_VERBOSE_PRINTK
193#define SFX /* nop */
194#else
1da177e4 195#define SFX "hda-intel: "
4abc1cc2 196#endif
cb53c626 197
a82d51ed
TI		 198#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
199#ifdef CONFIG_SND_HDA_CODEC_HDMI
200#define SUPPORT_VGA_SWITCHEROO
201#endif
202#endif
203
204
1da177e4
LT		 205/*
206 * registers
207 */
208#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 209#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
210#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
211#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
212#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
213#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 214#define ICH6_REG_VMIN 0x02
215#define ICH6_REG_VMAJ 0x03
216#define ICH6_REG_OUTPAY 0x04
217#define ICH6_REG_INPAY 0x06
218#define ICH6_REG_GCTL 0x08
8a933ece 219#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 220#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
221#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 222#define ICH6_REG_WAKEEN 0x0c
223#define ICH6_REG_STATESTS 0x0e
224#define ICH6_REG_GSTS 0x10
b21fadb9 225#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 226#define ICH6_REG_INTCTL 0x20
227#define ICH6_REG_INTSTS 0x24
e5463720 228#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 229#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
230#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 231#define ICH6_REG_CORBLBASE 0x40
232#define ICH6_REG_CORBUBASE 0x44
233#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 234#define ICH6_REG_CORBRP 0x4a
235#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 236#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 237#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
238#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 239#define ICH6_REG_CORBSTS 0x4d
b21fadb9 240#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 241#define ICH6_REG_CORBSIZE 0x4e
242
243#define ICH6_REG_RIRBLBASE 0x50
244#define ICH6_REG_RIRBUBASE 0x54
245#define ICH6_REG_RIRBWP 0x58
b21fadb9 246#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 247#define ICH6_REG_RINTCNT 0x5a
248#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 249#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
250#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
251#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 252#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 253#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
254#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 255#define ICH6_REG_RIRBSIZE 0x5e
256
257#define ICH6_REG_IC 0x60
258#define ICH6_REG_IR 0x64
259#define ICH6_REG_IRS 0x68
260#define ICH6_IRS_VALID (1<<1)
261#define ICH6_IRS_BUSY (1<<0)
262
263#define ICH6_REG_DPLBASE 0x70
264#define ICH6_REG_DPUBASE 0x74
265#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
266
267/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
268enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
269
270/* stream register offsets from stream base */
271#define ICH6_REG_SD_CTL 0x00
272#define ICH6_REG_SD_STS 0x03
273#define ICH6_REG_SD_LPIB 0x04
274#define ICH6_REG_SD_CBL 0x08
275#define ICH6_REG_SD_LVI 0x0c
276#define ICH6_REG_SD_FIFOW 0x0e
277#define ICH6_REG_SD_FIFOSIZE 0x10
278#define ICH6_REG_SD_FORMAT 0x12
279#define ICH6_REG_SD_BDLPL 0x18
280#define ICH6_REG_SD_BDLPU 0x1c
281
282/* PCI space */
283#define ICH6_PCIREG_TCSEL 0x44
284
285/*
286 * other constants
287 */
288
289/* max number of SDs */
07e4ca50 290/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 291#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 292#define ICH6_NUM_PLAYBACK 4
293
294/* ULI has 6 playback and 5 capture */
07e4ca50 295#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 296#define ULI_NUM_PLAYBACK 6
297
778b6e1b 298/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 299#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 300#define ATIHDMI_NUM_PLAYBACK 1
301
f269002e
KY		 302/* TERA has 4 playback and 3 capture */
303#define TERA_NUM_CAPTURE 3
304#define TERA_NUM_PLAYBACK 4
305
07e4ca50
TI		 306/* this number is statically defined for simplicity */
307#define MAX_AZX_DEV 16
308
1da177e4 309/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 310#define BDL_SIZE 4096
311#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
312#define AZX_MAX_FRAG 32
1da177e4
LT		 313/* max buffer size - no h/w limit, you can increase as you like */
314#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 315
316/* RIRB int mask: overrun[2], response[0] */
317#define RIRB_INT_RESPONSE 0x01
318#define RIRB_INT_OVERRUN 0x04
319#define RIRB_INT_MASK 0x05
320
2f5983f2 321/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 322#define AZX_MAX_CODECS 8
323#define AZX_DEFAULT_CODECS 4
deadff16 324#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 325
326/* SD_CTL bits */
327#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
328#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 329#define SD_CTL_STRIPE (3 << 16) /* stripe control */
330#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
331#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 332#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
333#define SD_CTL_STREAM_TAG_SHIFT 20
334
335/* SD_CTL and SD_STS */
336#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
337#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
338#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 339#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
340 SD_INT_COMPLETE)
1da177e4
LT		 341
342/* SD_STS */
343#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
344
345/* INTCTL and INTSTS */
d01ce99f
TI		 346#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
347#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
348#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 349
1da177e4
LT		 350/* below are so far hardcoded - should read registers in future */
351#define ICH6_MAX_CORB_ENTRIES 256
352#define ICH6_MAX_RIRB_ENTRIES 256
353
c74db86b
TI		 354/* position fix mode */
355enum {
0be3b5d3 356 POS_FIX_AUTO,
d2e1c973 357 POS_FIX_LPIB,
0be3b5d3 358 POS_FIX_POSBUF,
4cb36310 359 POS_FIX_VIACOMBO,
a6f2fd55 360 POS_FIX_COMBO,
c74db86b 361};
1da177e4 362
f5d40b30 363/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 364#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
365#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
366
da3fca21
V		 367/* Defines for Nvidia HDA support */
368#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
369#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 370#define NVIDIA_HDA_ISTRM_COH 0x4d
371#define NVIDIA_HDA_OSTRM_COH 0x4c
372#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 373
90a5ad52
TI		 374/* Defines for Intel SCH HDA snoop control */
375#define INTEL_SCH_HDA_DEVC 0x78
376#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
377
0e153474
JC		 378/* Define IN stream 0 FIFO size offset in VIA controller */
379#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
380/* Define VIA HD Audio Device ID*/
381#define VIA_HDAC_DEVICE_ID 0x3288
382
c4da29ca
YL		 383/* HD Audio class code */
384#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 385
1da177e4
LT		 386/*
387 */
388
a98f90fd 389struct azx_dev {
4ce107b9 390 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 391 u32 *posbuf; /* position buffer pointer */
1da177e4 392
d01ce99f 393 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 394 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 395 unsigned int frags; /* number for period in the play buffer */
396 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 397 unsigned long start_wallclk; /* start + minimum wallclk */
398 unsigned long period_wallclk; /* wallclk for period */
1da177e4 399
d01ce99f 400 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 401
d01ce99f 402 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 403
404 /* pcm support */
d01ce99f
TI		 405 struct snd_pcm_substream *substream; /* assigned substream,
406 * set in PCM open
407 */
408 unsigned int format_val; /* format value to be set in the
409 * controller and the codec
410 */
1da177e4
LT		 411 unsigned char stream_tag; /* assigned stream */
412 unsigned char index; /* stream index */
d5cf9911 413 int assigned_key; /* last device# key assigned to */
1da177e4 414
927fc866
PM		 415 unsigned int opened :1;
416 unsigned int running :1;
675f25d4 417 unsigned int irq_pending :1;
0e153474
JC		 418 /*
419 * For VIA:
420 * A flag to ensure DMA position is 0
421 * when link position is not greater than FIFO size
422 */
423 unsigned int insufficient :1;
27fe48d9 424 unsigned int wc_marked:1;
915bf29e 425 unsigned int no_period_wakeup:1;
5d890f59
PLB		 426
427 struct timecounter azx_tc;
428 struct cyclecounter azx_cc;
1da177e4
LT		 429};
430
431/* CORB/RIRB */
a98f90fd 432struct azx_rb {
1da177e4
LT		 433 u32 *buf; /* CORB/RIRB buffer
434 * Each CORB entry is 4byte, RIRB is 8byte
435 */
436 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
437 /* for RIRB */
438 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 439 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
440 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 441};
442
01b65bfb
TI		 443struct azx_pcm {
444 struct azx *chip;
445 struct snd_pcm *pcm;
446 struct hda_codec *codec;
447 struct hda_pcm_stream *hinfo[2];
448 struct list_head list;
449};
450
a98f90fd
TI		 451struct azx {
452 struct snd_card *card;
1da177e4 453 struct pci_dev *pci;
555e219f 454 int dev_index;
1da177e4 455
07e4ca50
TI		 456 /* chip type specific */
457 int driver_type;
9477c58e 458 unsigned int driver_caps;
07e4ca50
TI		 459 int playback_streams;
460 int playback_index_offset;
461 int capture_streams;
462 int capture_index_offset;
463 int num_streams;
464
1da177e4
LT		 465 /* pci resources */
466 unsigned long addr;
467 void __iomem *remap_addr;
468 int irq;
469
470 /* locks */
471 spinlock_t reg_lock;
62932df8 472 struct mutex open_mutex;
f4c482a4 473 struct completion probe_wait;
1da177e4 474
07e4ca50 475 /* streams (x num_streams) */
a98f90fd 476 struct azx_dev *azx_dev;
1da177e4
LT		 477
478 /* PCM */
01b65bfb 479 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 480
481 /* HD codec */
482 unsigned short codec_mask;
f1eaaeec 483 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 484 struct hda_bus *bus;
2dca0bba 485 unsigned int beep_mode;
1da177e4
LT		 486
487 /* CORB/RIRB */
a98f90fd
TI		 488 struct azx_rb corb;
489 struct azx_rb rirb;
1da177e4 490
4ce107b9 491 /* CORB/RIRB and position buffers */
1da177e4
LT		 492 struct snd_dma_buffer rb;
493 struct snd_dma_buffer posbuf;
c74db86b 494
4918cdab
TI		 495#ifdef CONFIG_SND_HDA_PATCH_LOADER
496 const struct firmware *fw;
497#endif
498
c74db86b 499 /* flags */
beaffc39 500 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 501 int poll_count;
cb53c626 502 unsigned int running :1;
927fc866
PM		 503 unsigned int initialized :1;
504 unsigned int single_cmd :1;
505 unsigned int polling_mode :1;
68e7fffc 506 unsigned int msi :1;
a6a950a8 507 unsigned int irq_pending_warned :1;
6ce4a3bc 508 unsigned int probing :1; /* codec probing phase */
27fe48d9 509 unsigned int snoop:1;
52409aa6 510 unsigned int align_buffer_size:1;
a82d51ed
TI		 511 unsigned int region_requested:1;
512
513 /* VGA-switcheroo setup */
514 unsigned int use_vga_switcheroo:1;
128960a9 515 unsigned int vga_switcheroo_registered:1;
a82d51ed
TI		 516 unsigned int init_failed:1; /* delayed init failed */
517 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 518
519 /* for debugging */
feb27340 520 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 521
522 /* for pending irqs */
523 struct work_struct irq_pending_work;
0cbf0098
TI		 524
525 /* reboot notifier (for mysterious hangup problem at power-down) */
526 struct notifier_block reboot_notifier;
65fcd41d
TI		 527
528 /* card list (for power_save trigger) */
529 struct list_head list;
1da177e4
LT		 530};
531
1a8506d4
TI		 532#define CREATE_TRACE_POINTS
533#include "hda_intel_trace.h"
534
07e4ca50
TI		 535/* driver types */
536enum {
537 AZX_DRIVER_ICH,
32679f95 538 AZX_DRIVER_PCH,
4979bca9 539 AZX_DRIVER_SCH,
07e4ca50 540 AZX_DRIVER_ATI,
778b6e1b 541 AZX_DRIVER_ATIHDMI,
1815b34a 542 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 543 AZX_DRIVER_VIA,
544 AZX_DRIVER_SIS,
545 AZX_DRIVER_ULI,
da3fca21 546 AZX_DRIVER_NVIDIA,
f269002e 547 AZX_DRIVER_TERA,
14d34f16 548 AZX_DRIVER_CTX,
5ae763b1 549 AZX_DRIVER_CTHDA,
c4da29ca 550 AZX_DRIVER_GENERIC,
2f5983f2 551 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 552};
553
9477c58e
TI		 554/* driver quirks (capabilities) */
555/* bits 0-7 are used for indicating driver type */
556#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
557#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
558#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
559#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
560#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
561#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
562#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
563#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
564#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
565#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
566#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
567#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 568#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 569#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 570#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 571#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
90accc58 572#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
2ea3c6a2
TI		 573#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
574
575/* quirks for Intel PCH */
576#define AZX_DCAPS_INTEL_PCH \
577 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
578 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME)
9477c58e
TI		 579
580/* quirks for ATI SB / AMD Hudson */
581#define AZX_DCAPS_PRESET_ATI_SB \
582 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
583 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
584
585/* quirks for ATI/AMD HDMI */
586#define AZX_DCAPS_PRESET_ATI_HDMI \
587 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
588
589/* quirks for Nvidia */
590#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e
TI		 591 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
592 AZX_DCAPS_ALIGN_BUFSIZE)
9477c58e 593
5ae763b1
TI		 594#define AZX_DCAPS_PRESET_CTHDA \
595 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
596
a82d51ed
TI		 597/*
598 * VGA-switcher support
599 */
600#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 601#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
602#else
603#define use_vga_switcheroo(chip) 0
604#endif
605
606#if defined(SUPPORT_VGA_SWITCHEROO) || defined(CONFIG_SND_HDA_PATCH_LOADER)
a82d51ed
TI		 607#define DELAYED_INIT_MARK
608#define DELAYED_INITDATA_MARK
a82d51ed
TI		 609#else
610#define DELAYED_INIT_MARK __devinit
611#define DELAYED_INITDATA_MARK __devinitdata
a82d51ed
TI		 612#endif
613
614static char *driver_short_names[] DELAYED_INITDATA_MARK = {
07e4ca50 615 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 616 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 617 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 618 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 619 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 620 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 621 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
622 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 623 [AZX_DRIVER_ULI] = "HDA ULI M5461",
624 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 625 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 626 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 627 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 628 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 629};
630
1da177e4
LT		 631/*
632 * macros for easy use
633 */
634#define azx_writel(chip,reg,value) \
635 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
636#define azx_readl(chip,reg) \
637 readl((chip)->remap_addr + ICH6_REG_##reg)
638#define azx_writew(chip,reg,value) \
639 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
640#define azx_readw(chip,reg) \
641 readw((chip)->remap_addr + ICH6_REG_##reg)
642#define azx_writeb(chip,reg,value) \
643 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
644#define azx_readb(chip,reg) \
645 readb((chip)->remap_addr + ICH6_REG_##reg)
646
647#define azx_sd_writel(dev,reg,value) \
648 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
649#define azx_sd_readl(dev,reg) \
650 readl((dev)->sd_addr + ICH6_REG_##reg)
651#define azx_sd_writew(dev,reg,value) \
652 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
653#define azx_sd_readw(dev,reg) \
654 readw((dev)->sd_addr + ICH6_REG_##reg)
655#define azx_sd_writeb(dev,reg,value) \
656 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
657#define azx_sd_readb(dev,reg) \
658 readb((dev)->sd_addr + ICH6_REG_##reg)
659
660/* for pcm support */
a98f90fd 661#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 662
27fe48d9
TI		 663#ifdef CONFIG_X86
664static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
665{
666 if (azx_snoop(chip))
667 return;
668 if (addr && size) {
669 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
670 if (on)
671 set_memory_wc((unsigned long)addr, pages);
672 else
673 set_memory_wb((unsigned long)addr, pages);
674 }
675}
676
677static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
678 bool on)
679{
680 __mark_pages_wc(chip, buf->area, buf->bytes, on);
681}
682static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
683 struct snd_pcm_runtime *runtime, bool on)
684{
685 if (azx_dev->wc_marked != on) {
686 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
687 azx_dev->wc_marked = on;
688 }
689}
690#else
691/* NOP for other archs */
692static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
693 bool on)
694{
695}
696static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
697 struct snd_pcm_runtime *runtime, bool on)
698{
699}
700#endif
701
68e7fffc 702static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 703static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 704/*
705 * Interface for HD codec
706 */
707
1da177e4
LT		 708/*
709 * CORB / RIRB interface
710 */
a98f90fd 711static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 712{
713 int err;
714
715 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 716 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
717 snd_dma_pci_data(chip->pci),
1da177e4
LT		 718 PAGE_SIZE, &chip->rb);
719 if (err < 0) {
720 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
721 return err;
722 }
27fe48d9 723 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 724 return 0;
725}
726
a98f90fd 727static void azx_init_cmd_io(struct azx *chip)
1da177e4 728{
cdb1fbf2 729 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 730 /* CORB set up */
731 chip->corb.addr = chip->rb.addr;
732 chip->corb.buf = (u32 *)chip->rb.area;
733 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 734 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 735
07e4ca50
TI		 736 /* set the corb size to 256 entries (ULI requires explicitly) */
737 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 738 /* set the corb write pointer to 0 */
739 azx_writew(chip, CORBWP, 0);
740 /* reset the corb hw read pointer */
b21fadb9 741 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 742 /* enable corb dma */
b21fadb9 743 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 744
745 /* RIRB set up */
746 chip->rirb.addr = chip->rb.addr + 2048;
747 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 748 chip->rirb.wp = chip->rirb.rp = 0;
749 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 750 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 751 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 752
07e4ca50
TI		 753 /* set the rirb size to 256 entries (ULI requires explicitly) */
754 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 755 /* reset the rirb hw write pointer */
b21fadb9 756 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 757 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 758 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 759 azx_writew(chip, RINTCNT, 0xc0);
760 else
761 azx_writew(chip, RINTCNT, 1);
1da177e4 762 /* enable rirb dma and response irq */
1da177e4 763 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 764 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 765}
766
a98f90fd 767static void azx_free_cmd_io(struct azx *chip)
1da177e4 768{
cdb1fbf2 769 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 770 /* disable ringbuffer DMAs */
771 azx_writeb(chip, RIRBCTL, 0);
772 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 773 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 774}
775
deadff16
WF		 776static unsigned int azx_command_addr(u32 cmd)
777{
778 unsigned int addr = cmd >> 28;
779
780 if (addr >= AZX_MAX_CODECS) {
781 snd_BUG();
782 addr = 0;
783 }
784
785 return addr;
786}
787
788static unsigned int azx_response_addr(u32 res)
789{
790 unsigned int addr = res & 0xf;
791
792 if (addr >= AZX_MAX_CODECS) {
793 snd_BUG();
794 addr = 0;
795 }
796
797 return addr;
1da177e4
LT		 798}
799
800/* send a command */
33fa35ed 801static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 802{
33fa35ed 803 struct azx *chip = bus->private_data;
deadff16 804 unsigned int addr = azx_command_addr(val);
1da177e4 805 unsigned int wp;
1da177e4 806
c32649fe
WF		 807 spin_lock_irq(&chip->reg_lock);
808
1da177e4
LT		 809 /* add command to corb */
810 wp = azx_readb(chip, CORBWP);
811 wp++;
812 wp %= ICH6_MAX_CORB_ENTRIES;
813
deadff16 814 chip->rirb.cmds[addr]++;
1da177e4
LT		 815 chip->corb.buf[wp] = cpu_to_le32(val);
816 azx_writel(chip, CORBWP, wp);
c32649fe 817
1da177e4
LT		 818 spin_unlock_irq(&chip->reg_lock);
819
820 return 0;
821}
822
823#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
824
825/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 826static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 827{
828 unsigned int rp, wp;
deadff16 829 unsigned int addr;
1da177e4
LT		 830 u32 res, res_ex;
831
832 wp = azx_readb(chip, RIRBWP);
833 if (wp == chip->rirb.wp)
834 return;
835 chip->rirb.wp = wp;
deadff16 836
1da177e4
LT		 837 while (chip->rirb.rp != wp) {
838 chip->rirb.rp++;
839 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
840
841 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
842 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
843 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 844 addr = azx_response_addr(res_ex);
1da177e4
LT		 845 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
846 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 847 else if (chip->rirb.cmds[addr]) {
848 chip->rirb.res[addr] = res;
2add9b92 849 smp_wmb();
deadff16 850 chip->rirb.cmds[addr]--;
e310bb06 851 } else
9e3d352b 852 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
e310bb06 853 "last cmd=%#08x\n",
9e3d352b 854 pci_name(chip->pci),
e310bb06
WF		 855 res, res_ex,
856 chip->last_cmd[addr]);
1da177e4
LT		 857 }
858}
859
860/* receive a response */
deadff16
WF		 861static unsigned int azx_rirb_get_response(struct hda_bus *bus,
862 unsigned int addr)
1da177e4 863{
33fa35ed 864 struct azx *chip = bus->private_data;
5c79b1f8 865 unsigned long timeout;
32cf4023 866 unsigned long loopcounter;
1eb6dc7d 867 int do_poll = 0;
1da177e4 868
5c79b1f8
TI		 869 again:
870 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 871
872 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 873 if (chip->polling_mode || do_poll) {
e96224ae
TI		 874 spin_lock_irq(&chip->reg_lock);
875 azx_update_rirb(chip);
876 spin_unlock_irq(&chip->reg_lock);
877 }
deadff16 878 if (!chip->rirb.cmds[addr]) {
2add9b92 879 smp_rmb();
b613291f 880 bus->rirb_error = 0;
1eb6dc7d
ML		 881
882 if (!do_poll)
883 chip->poll_count = 0;
deadff16 884 return chip->rirb.res[addr]; /* the last value */
2add9b92 885 }
28a0d9df
TI		 886 if (time_after(jiffies, timeout))
887 break;
32cf4023 888 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 889 msleep(2); /* temporary workaround */
890 else {
891 udelay(10);
892 cond_resched();
893 }
28a0d9df 894 }
5c79b1f8 895
1eb6dc7d
ML		 896 if (!chip->polling_mode && chip->poll_count < 2) {
897 snd_printdd(SFX "azx_get_response timeout, "
898 "polling the codec once: last cmd=0x%08x\n",
899 chip->last_cmd[addr]);
900 do_poll = 1;
901 chip->poll_count++;
902 goto again;
903 }
904
905
23c4a881
TI		 906 if (!chip->polling_mode) {
907 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
908 "switching to polling mode: last cmd=0x%08x\n",
909 chip->last_cmd[addr]);
910 chip->polling_mode = 1;
911 goto again;
912 }
913
68e7fffc 914 if (chip->msi) {
4abc1cc2 915 snd_printk(KERN_WARNING SFX "No response from codec, "
feb27340
WF		 916 "disabling MSI: last cmd=0x%08x\n",
917 chip->last_cmd[addr]);
68e7fffc
TI		 918 free_irq(chip->irq, chip);
919 chip->irq = -1;
920 pci_disable_msi(chip->pci);
921 chip->msi = 0;
b613291f
TI		 922 if (azx_acquire_irq(chip, 1) < 0) {
923 bus->rirb_error = 1;
68e7fffc 924 return -1;
b613291f 925 }
68e7fffc
TI		 926 goto again;
927 }
928
6ce4a3bc
TI		 929 if (chip->probing) {
930 /* If this critical timeout happens during the codec probing
931 * phase, this is likely an access to a non-existing codec
932 * slot. Better to return an error and reset the system.
933 */
934 return -1;
935 }
936
8dd78330
TI		 937 /* a fatal communication error; need either to reset or to fallback
938 * to the single_cmd mode
939 */
b613291f 940 bus->rirb_error = 1;
b20f3b83 941 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 942 bus->response_reset = 1;
943 return -1; /* give a chance to retry */
944 }
945
946 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
947 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 948 chip->last_cmd[addr]);
8dd78330
TI		 949 chip->single_cmd = 1;
950 bus->response_reset = 0;
1a696978 951 /* release CORB/RIRB */
4fcd3920 952 azx_free_cmd_io(chip);
1a696978
TI		 953 /* disable unsolicited responses */
954 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 955 return -1;
1da177e4
LT		 956}
957
1da177e4
LT		 958/*
959 * Use the single immediate command instead of CORB/RIRB for simplicity
960 *
961 * Note: according to Intel, this is not preferred use. The command was
962 * intended for the BIOS only, and may get confused with unsolicited
963 * responses. So, we shouldn't use it for normal operation from the
964 * driver.
965 * I left the codes, however, for debugging/testing purposes.
966 */
967
b05a7d4f 968/* receive a response */
deadff16 969static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 970{
971 int timeout = 50;
972
973 while (timeout--) {
974 /* check IRV busy bit */
975 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
976 /* reuse rirb.res as the response return value */
deadff16 977 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 978 return 0;
979 }
980 udelay(1);
981 }
982 if (printk_ratelimit())
983 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
984 azx_readw(chip, IRS));
deadff16 985 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 986 return -EIO;
987}
988
1da177e4 989/* send a command */
33fa35ed 990static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 991{
33fa35ed 992 struct azx *chip = bus->private_data;
deadff16 993 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 994 int timeout = 50;
995
8dd78330 996 bus->rirb_error = 0;
1da177e4
LT		 997 while (timeout--) {
998 /* check ICB busy bit */
d01ce99f 999 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 1000 /* Clear IRV valid bit */
d01ce99f
TI		 1001 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1002 ICH6_IRS_VALID);
1da177e4 1003 azx_writel(chip, IC, val);
d01ce99f
TI		 1004 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1005 ICH6_IRS_BUSY);
deadff16 1006 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 1007 }
1008 udelay(1);
1009 }
1cfd52bc
MB		 1010 if (printk_ratelimit())
1011 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
1012 azx_readw(chip, IRS), val);
1da177e4
LT		 1013 return -EIO;
1014}
1015
1016/* receive a response */
deadff16
WF		 1017static unsigned int azx_single_get_response(struct hda_bus *bus,
1018 unsigned int addr)
1da177e4 1019{
33fa35ed 1020 struct azx *chip = bus->private_data;
deadff16 1021 return chip->rirb.res[addr];
1da177e4
LT		 1022}
1023
111d3af5
TI		 1024/*
1025 * The below are the main callbacks from hda_codec.
1026 *
1027 * They are just the skeleton to call sub-callbacks according to the
1028 * current setting of chip->single_cmd.
1029 */
1030
1031/* send a command */
33fa35ed 1032static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 1033{
33fa35ed 1034 struct azx *chip = bus->private_data;
43bbb6cc 1035
a82d51ed
TI		 1036 if (chip->disabled)
1037 return 0;
feb27340 1038 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 1039 if (chip->single_cmd)
33fa35ed 1040 return azx_single_send_cmd(bus, val);
111d3af5 1041 else
33fa35ed 1042 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 1043}
1044
1045/* get a response */
deadff16
WF		 1046static unsigned int azx_get_response(struct hda_bus *bus,
1047 unsigned int addr)
111d3af5 1048{
33fa35ed 1049 struct azx *chip = bus->private_data;
a82d51ed
TI		 1050 if (chip->disabled)
1051 return 0;
111d3af5 1052 if (chip->single_cmd)
deadff16 1053 return azx_single_get_response(bus, addr);
111d3af5 1054 else
deadff16 1055 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1056}
1057
83012a7c 1058#ifdef CONFIG_PM
68467f51 1059static void azx_power_notify(struct hda_bus *bus, bool power_up);
cb53c626 1060#endif
111d3af5 1061
1da177e4 1062/* reset codec link */
cd508fe5 1063static int azx_reset(struct azx *chip, int full_reset)
1da177e4
LT		 1064{
1065 int count;
1066
cd508fe5
JK		 1067 if (!full_reset)
1068 goto __skip;
1069
e8a7f136
DT		 1070 /* clear STATESTS */
1071 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1072
1da177e4
LT		 1073 /* reset controller */
1074 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1075
1076 count = 50;
1077 while (azx_readb(chip, GCTL) && --count)
1078 msleep(1);
1079
1080 /* delay for >= 100us for codec PLL to settle per spec
1081 * Rev 0.9 section 5.5.1
1082 */
1083 msleep(1);
1084
1085 /* Bring controller out of reset */
1086 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1087
1088 count = 50;
927fc866 1089 while (!azx_readb(chip, GCTL) && --count)
1da177e4
LT		 1090 msleep(1);
1091
927fc866 1092 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1da177e4
LT		 1093 msleep(1);
1094
cd508fe5 1095 __skip:
1da177e4 1096 /* check to see if controller is ready */
927fc866 1097 if (!azx_readb(chip, GCTL)) {
4abc1cc2 1098 snd_printd(SFX "azx_reset: controller not ready!\n");
1da177e4
LT		 1099 return -EBUSY;
1100 }
1101
41e2fce4 1102 /* Accept unsolicited responses */
1a696978
TI		 1103 if (!chip->single_cmd)
1104 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1105 ICH6_GCTL_UNSOL);
41e2fce4 1106
1da177e4 1107 /* detect codecs */
927fc866 1108 if (!chip->codec_mask) {
1da177e4 1109 chip->codec_mask = azx_readw(chip, STATESTS);
4abc1cc2 1110 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1da177e4
LT		 1111 }
1112
1113 return 0;
1114}
1115
1116
1117/*
1118 * Lowlevel interface
1119 */
1120
1121/* enable interrupts */
a98f90fd 1122static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1123{
1124 /* enable controller CIE and GIE */
1125 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1126 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1127}
1128
1129/* disable interrupts */
a98f90fd 1130static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1131{
1132 int i;
1133
1134 /* disable interrupts in stream descriptor */
07e4ca50 1135 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1136 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1137 azx_sd_writeb(azx_dev, SD_CTL,
1138 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1139 }
1140
1141 /* disable SIE for all streams */
1142 azx_writeb(chip, INTCTL, 0);
1143
1144 /* disable controller CIE and GIE */
1145 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1146 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1147}
1148
1149/* clear interrupts */
a98f90fd 1150static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1151{
1152 int i;
1153
1154 /* clear stream status */
07e4ca50 1155 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1156 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1157 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1158 }
1159
1160 /* clear STATESTS */
1161 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1162
1163 /* clear rirb status */
1164 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1165
1166 /* clear int status */
1167 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1168}
1169
1170/* start a stream */
a98f90fd 1171static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1172{
0e153474
JC		 1173 /*
1174 * Before stream start, initialize parameter
1175 */
1176 azx_dev->insufficient = 1;
1177
1da177e4 1178 /* enable SIE */
ccc5df05
WN		 1179 azx_writel(chip, INTCTL,
1180 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1181 /* set DMA start and interrupt mask */
1182 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1183 SD_CTL_DMA_START | SD_INT_MASK);
1184}
1185
1dddab40
TI		 1186/* stop DMA */
1187static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1188{
1da177e4
LT		 1189 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1190 ~(SD_CTL_DMA_START | SD_INT_MASK));
1191 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1192}
1193
1194/* stop a stream */
1195static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1196{
1197 azx_stream_clear(chip, azx_dev);
1da177e4 1198 /* disable SIE */
ccc5df05
WN		 1199 azx_writel(chip, INTCTL,
1200 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1201}
1202
1203
1204/*
cb53c626 1205 * reset and start the controller registers
1da177e4 1206 */
cd508fe5 1207static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1208{
cb53c626
TI		 1209 if (chip->initialized)
1210 return;
1da177e4
LT		 1211
1212 /* reset controller */
cd508fe5 1213 azx_reset(chip, full_reset);
1da177e4
LT		 1214
1215 /* initialize interrupts */
1216 azx_int_clear(chip);
1217 azx_int_enable(chip);
1218
1219 /* initialize the codec command I/O */
1a696978
TI		 1220 if (!chip->single_cmd)
1221 azx_init_cmd_io(chip);
1da177e4 1222
0be3b5d3
TI		 1223 /* program the position buffer */
1224 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1225 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1226
cb53c626
TI		 1227 chip->initialized = 1;
1228}
1229
1230/*
1231 * initialize the PCI registers
1232 */
1233/* update bits in a PCI register byte */
1234static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1235 unsigned char mask, unsigned char val)
1236{
1237 unsigned char data;
1238
1239 pci_read_config_byte(pci, reg, &data);
1240 data &= ~mask;
1241 data |= (val & mask);
1242 pci_write_config_byte(pci, reg, data);
1243}
1244
1245static void azx_init_pci(struct azx *chip)
1246{
1247 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1248 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1249 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1250 * codecs.
1251 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1252 */
46f2cc80 1253 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
9477c58e 1254 snd_printdd(SFX "Clearing TCSEL\n");
a09e89f6 1255 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1256 }
cb53c626 1257
9477c58e
TI		 1258 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1259 * we need to enable snoop.
1260 */
1261 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
27fe48d9 1262 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
cb53c626 1263 update_pci_byte(chip->pci,
27fe48d9
TI		 1264 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1265 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1266 }
1267
1268 /* For NVIDIA HDA, enable snoop */
1269 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
27fe48d9 1270 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
cb53c626
TI		 1271 update_pci_byte(chip->pci,
1272 NVIDIA_HDA_TRANSREG_ADDR,
1273 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1274 update_pci_byte(chip->pci,
1275 NVIDIA_HDA_ISTRM_COH,
1276 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1277 update_pci_byte(chip->pci,
1278 NVIDIA_HDA_OSTRM_COH,
1279 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1280 }
1281
1282 /* Enable SCH/PCH snoop if needed */
1283 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1284 unsigned short snoop;
90a5ad52 1285 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1286 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1287 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1288 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1289 if (!azx_snoop(chip))
1290 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1291 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1292 pci_read_config_word(chip->pci,
1293 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1294 }
27fe48d9
TI		 1295 snd_printdd(SFX "SCH snoop: %s\n",
1296 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1297 ? "Disabled" : "Enabled");
da3fca21 1298 }
1da177e4
LT		 1299}
1300
1301
9ad593f6
TI		 1302static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1303
1da177e4
LT		 1304/*
1305 * interrupt handler
1306 */
7d12e780 1307static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1308{
a98f90fd
TI		 1309 struct azx *chip = dev_id;
1310 struct azx_dev *azx_dev;
1da177e4 1311 u32 status;
9ef04066 1312 u8 sd_status;
fa00e046 1313 int i, ok;
1da177e4 1314
b8dfc462
ML		 1315#ifdef CONFIG_PM_RUNTIME
1316 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1317 return IRQ_NONE;
1318#endif
1319
1da177e4
LT		 1320 spin_lock(&chip->reg_lock);
1321
60911062
DC		 1322 if (chip->disabled) {
1323 spin_unlock(&chip->reg_lock);
a82d51ed 1324 return IRQ_NONE;
60911062 1325 }
a82d51ed 1326
1da177e4
LT		 1327 status = azx_readl(chip, INTSTS);
1328 if (status == 0) {
1329 spin_unlock(&chip->reg_lock);
1330 return IRQ_NONE;
1331 }
1332
07e4ca50 1333 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1334 azx_dev = &chip->azx_dev[i];
1335 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1336 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1337 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1338 if (!azx_dev->substream || !azx_dev->running ||
1339 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1340 continue;
1341 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1342 ok = azx_position_ok(chip, azx_dev);
1343 if (ok == 1) {
9ad593f6 1344 azx_dev->irq_pending = 0;
1da177e4
LT		 1345 spin_unlock(&chip->reg_lock);
1346 snd_pcm_period_elapsed(azx_dev->substream);
1347 spin_lock(&chip->reg_lock);
fa00e046 1348 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1349 /* bogus IRQ, process it later */
1350 azx_dev->irq_pending = 1;
6acaed38
TI		 1351 queue_work(chip->bus->workq,
1352 &chip->irq_pending_work);
1da177e4
LT		 1353 }
1354 }
1355 }
1356
1357 /* clear rirb int */
1358 status = azx_readb(chip, RIRBSTS);
1359 if (status & RIRB_INT_MASK) {
14d34f16 1360 if (status & RIRB_INT_RESPONSE) {
9477c58e 1361 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1362 udelay(80);
1da177e4 1363 azx_update_rirb(chip);
14d34f16 1364 }
1da177e4
LT		 1365 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1366 }
1367
1368#if 0
1369 /* clear state status int */
1370 if (azx_readb(chip, STATESTS) & 0x04)
1371 azx_writeb(chip, STATESTS, 0x04);
1372#endif
1373 spin_unlock(&chip->reg_lock);
1374
1375 return IRQ_HANDLED;
1376}
1377
1378
675f25d4
TI		 1379/*
1380 * set up a BDL entry
1381 */
5ae763b1
TI		 1382static int setup_bdle(struct azx *chip,
1383 struct snd_pcm_substream *substream,
675f25d4
TI		 1384 struct azx_dev *azx_dev, u32 **bdlp,
1385 int ofs, int size, int with_ioc)
1386{
675f25d4
TI		 1387 u32 *bdl = *bdlp;
1388
1389 while (size > 0) {
1390 dma_addr_t addr;
1391 int chunk;
1392
1393 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1394 return -EINVAL;
1395
77a23f26 1396 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1397 /* program the address field of the BDL entry */
1398 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1399 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1400 /* program the size field of the BDL entry */
fc4abee8 1401 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
5ae763b1
TI		 1402 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1403 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1404 u32 remain = 0x1000 - (ofs & 0xfff);
1405 if (chunk > remain)
1406 chunk = remain;
1407 }
675f25d4
TI		 1408 bdl[2] = cpu_to_le32(chunk);
1409 /* program the IOC to enable interrupt
1410 * only when the whole fragment is processed
1411 */
1412 size -= chunk;
1413 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1414 bdl += 4;
1415 azx_dev->frags++;
1416 ofs += chunk;
1417 }
1418 *bdlp = bdl;
1419 return ofs;
1420}
1421
1da177e4
LT		 1422/*
1423 * set up BDL entries
1424 */
555e219f
TI		 1425static int azx_setup_periods(struct azx *chip,
1426 struct snd_pcm_substream *substream,
4ce107b9 1427 struct azx_dev *azx_dev)
1da177e4 1428{
4ce107b9
TI		 1429 u32 *bdl;
1430 int i, ofs, periods, period_bytes;
555e219f 1431 int pos_adj;
1da177e4
LT		 1432
1433 /* reset BDL address */
1434 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1435 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1436
97b71c94 1437 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1438 periods = azx_dev->bufsize / period_bytes;
1439
1da177e4 1440 /* program the initial BDL entries */
4ce107b9
TI		 1441 bdl = (u32 *)azx_dev->bdl.area;
1442 ofs = 0;
1443 azx_dev->frags = 0;
555e219f 1444 pos_adj = bdl_pos_adj[chip->dev_index];
915bf29e 1445 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
675f25d4 1446 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1447 int pos_align = pos_adj;
555e219f 1448 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1449 if (!pos_adj)
e785d3d8
TI		 1450 pos_adj = pos_align;
1451 else
1452 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1453 pos_align;
675f25d4
TI		 1454 pos_adj = frames_to_bytes(runtime, pos_adj);
1455 if (pos_adj >= period_bytes) {
4abc1cc2 1456 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
555e219f 1457 bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1458 pos_adj = 0;
1459 } else {
5ae763b1 1460 ofs = setup_bdle(chip, substream, azx_dev,
915bf29e 1461 &bdl, ofs, pos_adj, true);
675f25d4
TI		 1462 if (ofs < 0)
1463 goto error;
4ce107b9 1464 }
555e219f
TI		 1465 } else
1466 pos_adj = 0;
675f25d4
TI		 1467 for (i = 0; i < periods; i++) {
1468 if (i == periods - 1 && pos_adj)
5ae763b1 1469 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
675f25d4
TI		 1470 period_bytes - pos_adj, 0);
1471 else
5ae763b1 1472 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
7bb8fb70 1473 period_bytes,
915bf29e 1474 !azx_dev->no_period_wakeup);
675f25d4
TI		 1475 if (ofs < 0)
1476 goto error;
1da177e4 1477 }
4ce107b9 1478 return 0;
675f25d4
TI		 1479
1480 error:
4abc1cc2 1481 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
675f25d4 1482 azx_dev->bufsize, period_bytes);
675f25d4 1483 return -EINVAL;
1da177e4
LT		 1484}
1485
1dddab40
TI		 1486/* reset stream */
1487static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1488{
1489 unsigned char val;
1490 int timeout;
1491
1dddab40
TI		 1492 azx_stream_clear(chip, azx_dev);
1493
d01ce99f
TI		 1494 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1495 SD_CTL_STREAM_RESET);
1da177e4
LT		 1496 udelay(3);
1497 timeout = 300;
1498 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1499 --timeout)
1500 ;
1501 val &= ~SD_CTL_STREAM_RESET;
1502 azx_sd_writeb(azx_dev, SD_CTL, val);
1503 udelay(3);
1504
1505 timeout = 300;
1506 /* waiting for hardware to report that the stream is out of reset */
1507 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1508 --timeout)
1509 ;
fa00e046
JK		 1510
1511 /* reset first position - may not be synced with hw at this time */
1512 *azx_dev->posbuf = 0;
1dddab40 1513}
1da177e4 1514
1dddab40
TI		 1515/*
1516 * set up the SD for streaming
1517 */
1518static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1519{
27fe48d9 1520 unsigned int val;
1dddab40
TI		 1521 /* make sure the run bit is zero for SD */
1522 azx_stream_clear(chip, azx_dev);
1da177e4 1523 /* program the stream_tag */
27fe48d9
TI		 1524 val = azx_sd_readl(azx_dev, SD_CTL);
1525 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1526 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1527 if (!azx_snoop(chip))
1528 val |= SD_CTL_TRAFFIC_PRIO;
1529 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1530
1531 /* program the length of samples in cyclic buffer */
1532 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1533
1534 /* program the stream format */
1535 /* this value needs to be the same as the one programmed */
1536 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1537
1538 /* program the stream LVI (last valid index) of the BDL */
1539 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1540
1541 /* program the BDL address */
1542 /* lower BDL address */
4ce107b9 1543 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1544 /* upper BDL address */
766979e0 1545 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1546
0be3b5d3 1547 /* enable the position buffer */
4cb36310
DH		 1548 if (chip->position_fix[0] != POS_FIX_LPIB ||
1549 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1550 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1551 azx_writel(chip, DPLBASE,
1552 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1553 }
c74db86b 1554
1da177e4 1555 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1556 azx_sd_writel(azx_dev, SD_CTL,
1557 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1558
1559 return 0;
1560}
1561
6ce4a3bc
TI		 1562/*
1563 * Probe the given codec address
1564 */
1565static int probe_codec(struct azx *chip, int addr)
1566{
1567 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1568 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1569 unsigned int res;
1570
a678cdee 1571 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1572 chip->probing = 1;
1573 azx_send_cmd(chip->bus, cmd);
deadff16 1574 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1575 chip->probing = 0;
a678cdee 1576 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1577 if (res == -1)
1578 return -EIO;
4abc1cc2 1579 snd_printdd(SFX "codec #%d probed OK\n", addr);
6ce4a3bc
TI		 1580 return 0;
1581}
1582
33fa35ed
TI		 1583static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1584 struct hda_pcm *cpcm);
6ce4a3bc 1585static void azx_stop_chip(struct azx *chip);
1da177e4 1586
8dd78330
TI		 1587static void azx_bus_reset(struct hda_bus *bus)
1588{
1589 struct azx *chip = bus->private_data;
8dd78330
TI		 1590
1591 bus->in_reset = 1;
1592 azx_stop_chip(chip);
cd508fe5 1593 azx_init_chip(chip, 1);
65f75983 1594#ifdef CONFIG_PM
8dd78330 1595 if (chip->initialized) {
01b65bfb
TI		 1596 struct azx_pcm *p;
1597 list_for_each_entry(p, &chip->pcm_list, list)
1598 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1599 snd_hda_suspend(chip->bus);
1600 snd_hda_resume(chip->bus);
1601 }
65f75983 1602#endif
8dd78330
TI		 1603 bus->in_reset = 0;
1604}
1605
26a6cb6c
DH		 1606static int get_jackpoll_interval(struct azx *chip)
1607{
1608 int i = jackpoll_ms[chip->dev_index];
1609 unsigned int j;
1610 if (i == 0)
1611 return 0;
1612 if (i < 50 || i > 60000)
1613 j = 0;
1614 else
1615 j = msecs_to_jiffies(i);
1616 if (j == 0)
1617 snd_printk(KERN_WARNING SFX
1618 "jackpoll_ms value out of range: %d\n", i);
1619 return j;
1620}
1621
1da177e4
LT		 1622/*
1623 * Codec initialization
1624 */
1625
2f5983f2 1626/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
a82d51ed 1627static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
7445dfc1 1628 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1629 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1630};
1631
a82d51ed 1632static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1633{
1634 struct hda_bus_template bus_temp;
34c25350
TI		 1635 int c, codecs, err;
1636 int max_slots;
1da177e4
LT		 1637
1638 memset(&bus_temp, 0, sizeof(bus_temp));
1639 bus_temp.private_data = chip;
1640 bus_temp.modelname = model;
1641 bus_temp.pci = chip->pci;
111d3af5
TI		 1642 bus_temp.ops.command = azx_send_cmd;
1643 bus_temp.ops.get_response = azx_get_response;
176d5335 1644 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1645 bus_temp.ops.bus_reset = azx_bus_reset;
83012a7c 1646#ifdef CONFIG_PM
11cd41b8 1647 bus_temp.power_save = &power_save;
cb53c626
TI		 1648 bus_temp.ops.pm_notify = azx_power_notify;
1649#endif
1da177e4 1650
d01ce99f
TI		 1651 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1652 if (err < 0)
1da177e4
LT		 1653 return err;
1654
9477c58e
TI		 1655 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1656 snd_printd(SFX "Enable delay in RIRB handling\n");
dc9c8e21 1657 chip->bus->needs_damn_long_delay = 1;
9477c58e 1658 }
dc9c8e21 1659
34c25350 1660 codecs = 0;
2f5983f2
TI		 1661 max_slots = azx_max_codecs[chip->driver_type];
1662 if (!max_slots)
7445dfc1 1663 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1664
1665 /* First try to probe all given codec slots */
1666 for (c = 0; c < max_slots; c++) {
f1eaaeec 1667 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1668 if (probe_codec(chip, c) < 0) {
1669 /* Some BIOSen give you wrong codec addresses
1670 * that don't exist
1671 */
4abc1cc2
TI		 1672 snd_printk(KERN_WARNING SFX
1673 "Codec #%d probe error; "
6ce4a3bc
TI		 1674 "disabling it...\n", c);
1675 chip->codec_mask &= ~(1 << c);
1676 /* More badly, accessing to a non-existing
1677 * codec often screws up the controller chip,
2448158e 1678 * and disturbs the further communications.
6ce4a3bc
TI		 1679 * Thus if an error occurs during probing,
1680 * better to reset the controller chip to
1681 * get back to the sanity state.
1682 */
1683 azx_stop_chip(chip);
cd508fe5 1684 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1685 }
1686 }
1687 }
1688
d507cd66
TI		 1689 /* AMD chipsets often cause the communication stalls upon certain
1690 * sequence like the pin-detection. It seems that forcing the synced
1691 * access works around the stall. Grrr...
1692 */
9477c58e
TI		 1693 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1694 snd_printd(SFX "Enable sync_write for stable communication\n");
d507cd66
TI		 1695 chip->bus->sync_write = 1;
1696 chip->bus->allow_bus_reset = 1;
1697 }
1698
6ce4a3bc 1699 /* Then create codec instances */
34c25350 1700 for (c = 0; c < max_slots; c++) {
f1eaaeec 1701 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1702 struct hda_codec *codec;
a1e21c90 1703 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1704 if (err < 0)
1705 continue;
26a6cb6c 1706 codec->jackpoll_interval = get_jackpoll_interval(chip);
2dca0bba 1707 codec->beep_mode = chip->beep_mode;
1da177e4 1708 codecs++;
19a982b6
TI		 1709 }
1710 }
1711 if (!codecs) {
1da177e4
LT		 1712 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1713 return -ENXIO;
1714 }
a1e21c90
TI		 1715 return 0;
1716}
1da177e4 1717
a1e21c90
TI		 1718/* configure each codec instance */
1719static int __devinit azx_codec_configure(struct azx *chip)
1720{
1721 struct hda_codec *codec;
1722 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1723 snd_hda_codec_configure(codec);
1724 }
1da177e4
LT		 1725 return 0;
1726}
1727
1728
1729/*
1730 * PCM support
1731 */
1732
1733/* assign a stream for the PCM */
ef18bede
WF		 1734static inline struct azx_dev *
1735azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1736{
07e4ca50 1737 int dev, i, nums;
ef18bede 1738 struct azx_dev *res = NULL;
d5cf9911
TI		 1739 /* make a non-zero unique key for the substream */
1740 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1741 (substream->stream + 1);
ef18bede
WF		 1742
1743 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1744 dev = chip->playback_index_offset;
1745 nums = chip->playback_streams;
1746 } else {
1747 dev = chip->capture_index_offset;
1748 nums = chip->capture_streams;
1749 }
1750 for (i = 0; i < nums; i++, dev++)
d01ce99f 1751 if (!chip->azx_dev[dev].opened) {
ef18bede 1752 res = &chip->azx_dev[dev];
d5cf9911 1753 if (res->assigned_key == key)
ef18bede 1754 break;
1da177e4 1755 }
ef18bede
WF		 1756 if (res) {
1757 res->opened = 1;
d5cf9911 1758 res->assigned_key = key;
ef18bede
WF		 1759 }
1760 return res;
1da177e4
LT		 1761}
1762
1763/* release the assigned stream */
a98f90fd 1764static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1765{
1766 azx_dev->opened = 0;
1767}
1768
5d890f59
PLB		 1769static cycle_t azx_cc_read(const struct cyclecounter *cc)
1770{
1771 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1772 struct snd_pcm_substream *substream = azx_dev->substream;
1773 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1774 struct azx *chip = apcm->chip;
1775
1776 return azx_readl(chip, WALLCLK);
1777}
1778
1779static void azx_timecounter_init(struct snd_pcm_substream *substream,
1780 bool force, cycle_t last)
1781{
1782 struct azx_dev *azx_dev = get_azx_dev(substream);
1783 struct timecounter *tc = &azx_dev->azx_tc;
1784 struct cyclecounter *cc = &azx_dev->azx_cc;
1785 u64 nsec;
1786
1787 cc->read = azx_cc_read;
1788 cc->mask = CLOCKSOURCE_MASK(32);
1789
1790 /*
1791 * Converting from 24 MHz to ns means applying a 125/3 factor.
1792 * To avoid any saturation issues in intermediate operations,
1793 * the 125 factor is applied first. The division is applied
1794 * last after reading the timecounter value.
1795 * Applying the 1/3 factor as part of the multiplication
1796 * requires at least 20 bits for a decent precision, however
1797 * overflows occur after about 4 hours or less, not a option.
1798 */
1799
1800 cc->mult = 125; /* saturation after 195 years */
1801 cc->shift = 0;
1802
1803 nsec = 0; /* audio time is elapsed time since trigger */
1804 timecounter_init(tc, cc, nsec);
1805 if (force)
1806 /*
1807 * force timecounter to use predefined value,
1808 * used for synchronized starts
1809 */
1810 tc->cycle_last = last;
1811}
1812
1813static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1814 struct timespec *ts)
1815{
1816 struct azx_dev *azx_dev = get_azx_dev(substream);
1817 u64 nsec;
1818
1819 nsec = timecounter_read(&azx_dev->azx_tc);
1820 nsec = div_u64(nsec, 3); /* can be optimized */
1821
1822 *ts = ns_to_timespec(nsec);
1823
1824 return 0;
1825}
1826
a98f90fd 1827static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1828 .info = (SNDRV_PCM_INFO_MMAP |
1829 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1830 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1831 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1832 /* No full-resume yet implemented */
1833 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1834 SNDRV_PCM_INFO_PAUSE |
7bb8fb70 1835 SNDRV_PCM_INFO_SYNC_START |
5d890f59 1836 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
7bb8fb70 1837 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1838 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1839 .rates = SNDRV_PCM_RATE_48000,
1840 .rate_min = 48000,
1841 .rate_max = 48000,
1842 .channels_min = 2,
1843 .channels_max = 2,
1844 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1845 .period_bytes_min = 128,
1846 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1847 .periods_min = 2,
1848 .periods_max = AZX_MAX_FRAG,
1849 .fifo_size = 0,
1850};
1851
a98f90fd 1852static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1853{
1854 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1855 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1856 struct azx *chip = apcm->chip;
1857 struct azx_dev *azx_dev;
1858 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1859 unsigned long flags;
1860 int err;
2ae66c26 1861 int buff_step;
1da177e4 1862
62932df8 1863 mutex_lock(&chip->open_mutex);
ef18bede 1864 azx_dev = azx_assign_device(chip, substream);
1da177e4 1865 if (azx_dev == NULL) {
62932df8 1866 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1867 return -EBUSY;
1868 }
1869 runtime->hw = azx_pcm_hw;
1870 runtime->hw.channels_min = hinfo->channels_min;
1871 runtime->hw.channels_max = hinfo->channels_max;
1872 runtime->hw.formats = hinfo->formats;
1873 runtime->hw.rates = hinfo->rates;
1874 snd_pcm_limit_hw_rates(runtime);
1875 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5d890f59
PLB		 1876
1877 /* avoid wrap-around with wall-clock */
1878 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1879 20,
1880 178000000);
1881
52409aa6 1882 if (chip->align_buffer_size)
2ae66c26
PLB		 1883 /* constrain buffer sizes to be multiple of 128
1884 bytes. This is more efficient in terms of memory
1885 access but isn't required by the HDA spec and
1886 prevents users from specifying exact period/buffer
1887 sizes. For example for 44.1kHz, a period size set
1888 to 20ms will be rounded to 19.59ms. */
1889 buff_step = 128;
1890 else
1891 /* Don't enforce steps on buffer sizes, still need to
1892 be multiple of 4 bytes (HDA spec). Tested on Intel
1893 HDA controllers, may not work on all devices where
1894 option needs to be disabled */
1895 buff_step = 4;
1896
5f1545bc 1897 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 1898 buff_step);
5f1545bc 1899 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 1900 buff_step);
b4a91cf0 1901 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 1902 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1903 if (err < 0) {
1da177e4 1904 azx_release_device(azx_dev);
cb53c626 1905 snd_hda_power_down(apcm->codec);
62932df8 1906 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1907 return err;
1908 }
70d321e6 1909 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1910 /* sanity check */
1911 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1912 snd_BUG_ON(!runtime->hw.channels_max) ||
1913 snd_BUG_ON(!runtime->hw.formats) ||
1914 snd_BUG_ON(!runtime->hw.rates)) {
1915 azx_release_device(azx_dev);
1916 hinfo->ops.close(hinfo, apcm->codec, substream);
1917 snd_hda_power_down(apcm->codec);
1918 mutex_unlock(&chip->open_mutex);
1919 return -EINVAL;
1920 }
5d890f59
PLB		 1921
1922 /* disable WALLCLOCK timestamps for capture streams
1923 until we figure out how to handle digital inputs */
1924 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1925 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1926
1da177e4
LT		 1927 spin_lock_irqsave(&chip->reg_lock, flags);
1928 azx_dev->substream = substream;
1929 azx_dev->running = 0;
1930 spin_unlock_irqrestore(&chip->reg_lock, flags);
1931
1932 runtime->private_data = azx_dev;
850f0e52 1933 snd_pcm_set_sync(substream);
62932df8 1934 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1935 return 0;
1936}
1937
a98f90fd 1938static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1939{
1940 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1941 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1942 struct azx *chip = apcm->chip;
1943 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1944 unsigned long flags;
1945
62932df8 1946 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1947 spin_lock_irqsave(&chip->reg_lock, flags);
1948 azx_dev->substream = NULL;
1949 azx_dev->running = 0;
1950 spin_unlock_irqrestore(&chip->reg_lock, flags);
1951 azx_release_device(azx_dev);
1952 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1953 snd_hda_power_down(apcm->codec);
62932df8 1954 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1955 return 0;
1956}
1957
d01ce99f
TI		 1958static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1959 struct snd_pcm_hw_params *hw_params)
1da177e4 1960{
27fe48d9
TI		 1961 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1962 struct azx *chip = apcm->chip;
1963 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94 1964 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 1965 int ret;
97b71c94 1966
27fe48d9 1967 mark_runtime_wc(chip, azx_dev, runtime, false);
97b71c94
TI		 1968 azx_dev->bufsize = 0;
1969 azx_dev->period_bytes = 0;
1970 azx_dev->format_val = 0;
27fe48d9 1971 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 1972 params_buffer_bytes(hw_params));
27fe48d9
TI		 1973 if (ret < 0)
1974 return ret;
1975 mark_runtime_wc(chip, azx_dev, runtime, true);
1976 return ret;
1da177e4
LT		 1977}
1978
a98f90fd 1979static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1980{
1981 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1982 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9
TI		 1983 struct azx *chip = apcm->chip;
1984 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1985 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1986
1987 /* reset BDL address */
1988 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1989 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1990 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1991 azx_dev->bufsize = 0;
1992 azx_dev->period_bytes = 0;
1993 azx_dev->format_val = 0;
1da177e4 1994
eb541337 1995 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 1996
27fe48d9 1997 mark_runtime_wc(chip, azx_dev, runtime, false);
1da177e4
LT		 1998 return snd_pcm_lib_free_pages(substream);
1999}
2000
a98f90fd 2001static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 2002{
2003 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 2004 struct azx *chip = apcm->chip;
2005 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 2006 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 2007 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 2008 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 2009 int err;
7c935976
SW		 2010 struct hda_spdif_out *spdif =
2011 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2012 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 2013
fa00e046 2014 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 2015 format_val = snd_hda_calc_stream_format(runtime->rate,
2016 runtime->channels,
2017 runtime->format,
32c168c8 2018 hinfo->maxbps,
7c935976 2019 ctls);
97b71c94 2020 if (!format_val) {
d01ce99f
TI		 2021 snd_printk(KERN_ERR SFX
2022 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1da177e4
LT		 2023 runtime->rate, runtime->channels, runtime->format);
2024 return -EINVAL;
2025 }
2026
97b71c94
TI		 2027 bufsize = snd_pcm_lib_buffer_bytes(substream);
2028 period_bytes = snd_pcm_lib_period_bytes(substream);
2029
4abc1cc2 2030 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
97b71c94
TI		 2031 bufsize, format_val);
2032
2033 if (bufsize != azx_dev->bufsize ||
2034 period_bytes != azx_dev->period_bytes ||
915bf29e
TI		 2035 format_val != azx_dev->format_val ||
2036 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
97b71c94
TI		 2037 azx_dev->bufsize = bufsize;
2038 azx_dev->period_bytes = period_bytes;
2039 azx_dev->format_val = format_val;
915bf29e 2040 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
97b71c94
TI		 2041 err = azx_setup_periods(chip, substream, azx_dev);
2042 if (err < 0)
2043 return err;
2044 }
2045
e5463720
JK		 2046 /* wallclk has 24Mhz clock source */
2047 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2048 runtime->rate) * 1000);
1da177e4
LT		 2049 azx_setup_controller(chip, azx_dev);
2050 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2051 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2052 else
2053 azx_dev->fifo_size = 0;
2054
62b7e5e0
TI		 2055 stream_tag = azx_dev->stream_tag;
2056 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 2057 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 2058 stream_tag > chip->capture_streams)
2059 stream_tag -= chip->capture_streams;
2060 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 2061 azx_dev->format_val, substream);
1da177e4
LT		 2062}
2063
a98f90fd 2064static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 2065{
2066 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2067 struct azx *chip = apcm->chip;
850f0e52
TI		 2068 struct azx_dev *azx_dev;
2069 struct snd_pcm_substream *s;
fa00e046 2070 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 2071 int nwait, timeout;
1da177e4 2072
1a8506d4
TI		 2073 azx_dev = get_azx_dev(substream);
2074 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2075
1da177e4 2076 switch (cmd) {
fa00e046
JK		 2077 case SNDRV_PCM_TRIGGER_START:
2078 rstart = 1;
1da177e4
LT		 2079 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2080 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 2081 start = 1;
1da177e4
LT		 2082 break;
2083 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 2084 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 2085 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 2086 start = 0;
1da177e4
LT		 2087 break;
2088 default:
850f0e52
TI		 2089 return -EINVAL;
2090 }
2091
2092 snd_pcm_group_for_each_entry(s, substream) {
2093 if (s->pcm->card != substream->pcm->card)
2094 continue;
2095 azx_dev = get_azx_dev(s);
2096 sbits |= 1 << azx_dev->index;
2097 nsync++;
2098 snd_pcm_trigger_done(s, substream);
2099 }
2100
2101 spin_lock(&chip->reg_lock);
172d3b20
PLB		 2102
2103 /* first, set SYNC bits of corresponding streams */
2104 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2105 azx_writel(chip, OLD_SSYNC,
2106 azx_readl(chip, OLD_SSYNC) | sbits);
2107 else
2108 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2109
850f0e52
TI		 2110 snd_pcm_group_for_each_entry(s, substream) {
2111 if (s->pcm->card != substream->pcm->card)
2112 continue;
2113 azx_dev = get_azx_dev(s);
e5463720
JK		 2114 if (start) {
2115 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2116 if (!rstart)
2117 azx_dev->start_wallclk -=
2118 azx_dev->period_wallclk;
850f0e52 2119 azx_stream_start(chip, azx_dev);
e5463720 2120 } else {
850f0e52 2121 azx_stream_stop(chip, azx_dev);
e5463720 2122 }
850f0e52 2123 azx_dev->running = start;
1da177e4
LT		 2124 }
2125 spin_unlock(&chip->reg_lock);
850f0e52 2126 if (start) {
850f0e52
TI		 2127 /* wait until all FIFOs get ready */
2128 for (timeout = 5000; timeout; timeout--) {
2129 nwait = 0;
2130 snd_pcm_group_for_each_entry(s, substream) {
2131 if (s->pcm->card != substream->pcm->card)
2132 continue;
2133 azx_dev = get_azx_dev(s);
2134 if (!(azx_sd_readb(azx_dev, SD_STS) &
2135 SD_STS_FIFO_READY))
2136 nwait++;
2137 }
2138 if (!nwait)
2139 break;
2140 cpu_relax();
2141 }
2142 } else {
2143 /* wait until all RUN bits are cleared */
2144 for (timeout = 5000; timeout; timeout--) {
2145 nwait = 0;
2146 snd_pcm_group_for_each_entry(s, substream) {
2147 if (s->pcm->card != substream->pcm->card)
2148 continue;
2149 azx_dev = get_azx_dev(s);
2150 if (azx_sd_readb(azx_dev, SD_CTL) &
2151 SD_CTL_DMA_START)
2152 nwait++;
2153 }
2154 if (!nwait)
2155 break;
2156 cpu_relax();
2157 }
1da177e4 2158 }
172d3b20
PLB		 2159 spin_lock(&chip->reg_lock);
2160 /* reset SYNC bits */
2161 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2162 azx_writel(chip, OLD_SSYNC,
2163 azx_readl(chip, OLD_SSYNC) & ~sbits);
2164 else
2165 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
5d890f59
PLB		 2166 if (start) {
2167 azx_timecounter_init(substream, 0, 0);
2168 if (nsync > 1) {
2169 cycle_t cycle_last;
2170
2171 /* same start cycle for master and group */
2172 azx_dev = get_azx_dev(substream);
2173 cycle_last = azx_dev->azx_tc.cycle_last;
2174
2175 snd_pcm_group_for_each_entry(s, substream) {
2176 if (s->pcm->card != substream->pcm->card)
2177 continue;
2178 azx_timecounter_init(s, 1, cycle_last);
2179 }
2180 }
2181 }
172d3b20 2182 spin_unlock(&chip->reg_lock);
850f0e52 2183 return 0;
1da177e4
LT		 2184}
2185
0e153474
JC		 2186/* get the current DMA position with correction on VIA chips */
2187static unsigned int azx_via_get_position(struct azx *chip,
2188 struct azx_dev *azx_dev)
2189{
2190 unsigned int link_pos, mini_pos, bound_pos;
2191 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2192 unsigned int fifo_size;
2193
2194 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2195 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2196 /* Playback, no problem using link position */
2197 return link_pos;
2198 }
2199
2200 /* Capture */
2201 /* For new chipset,
2202 * use mod to get the DMA position just like old chipset
2203 */
2204 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2205 mod_dma_pos %= azx_dev->period_bytes;
2206
2207 /* azx_dev->fifo_size can't get FIFO size of in stream.
2208 * Get from base address + offset.
2209 */
2210 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2211
2212 if (azx_dev->insufficient) {
2213 /* Link position never gather than FIFO size */
2214 if (link_pos <= fifo_size)
2215 return 0;
2216
2217 azx_dev->insufficient = 0;
2218 }
2219
2220 if (link_pos <= fifo_size)
2221 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2222 else
2223 mini_pos = link_pos - fifo_size;
2224
2225 /* Find nearest previous boudary */
2226 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2227 mod_link_pos = link_pos % azx_dev->period_bytes;
2228 if (mod_link_pos >= fifo_size)
2229 bound_pos = link_pos - mod_link_pos;
2230 else if (mod_dma_pos >= mod_mini_pos)
2231 bound_pos = mini_pos - mod_mini_pos;
2232 else {
2233 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2234 if (bound_pos >= azx_dev->bufsize)
2235 bound_pos = 0;
2236 }
2237
2238 /* Calculate real DMA position we want */
2239 return bound_pos + mod_dma_pos;
2240}
2241
9ad593f6 2242static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2243 struct azx_dev *azx_dev,
2244 bool with_check)
1da177e4 2245{
1da177e4 2246 unsigned int pos;
4cb36310 2247 int stream = azx_dev->substream->stream;
1a8506d4 2248 int delay = 0;
1da177e4 2249
4cb36310
DH		 2250 switch (chip->position_fix[stream]) {
2251 case POS_FIX_LPIB:
2252 /* read LPIB */
2253 pos = azx_sd_readl(azx_dev, SD_LPIB);
2254 break;
2255 case POS_FIX_VIACOMBO:
0e153474 2256 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2257 break;
2258 default:
2259 /* use the position buffer */
2260 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2261 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2262 if (!pos || pos == (u32)-1) {
2263 printk(KERN_WARNING
2264 "hda-intel: Invalid position buffer, "
2265 "using LPIB read method instead.\n");
2266 chip->position_fix[stream] = POS_FIX_LPIB;
2267 pos = azx_sd_readl(azx_dev, SD_LPIB);
2268 } else
2269 chip->position_fix[stream] = POS_FIX_POSBUF;
2270 }
2271 break;
c74db86b 2272 }
4cb36310 2273
1da177e4
LT		 2274 if (pos >= azx_dev->bufsize)
2275 pos = 0;
90accc58
PLB		 2276
2277 /* calculate runtime delay from LPIB */
2278 if (azx_dev->substream->runtime &&
2279 chip->position_fix[stream] == POS_FIX_POSBUF &&
2280 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2281 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
90accc58
PLB		 2282 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2283 delay = pos - lpib_pos;
2284 else
2285 delay = lpib_pos - pos;
2286 if (delay < 0)
2287 delay += azx_dev->bufsize;
2288 if (delay >= azx_dev->period_bytes) {
1f04661f
TI		 2289 snd_printk(KERN_WARNING SFX
2290 "Unstable LPIB (%d >= %d); "
2291 "disabling LPIB delay counting\n",
2292 delay, azx_dev->period_bytes);
2293 delay = 0;
2294 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
90accc58
PLB		 2295 }
2296 azx_dev->substream->runtime->delay =
2297 bytes_to_frames(azx_dev->substream->runtime, delay);
2298 }
1a8506d4 2299 trace_azx_get_position(chip, azx_dev, pos, delay);
9ad593f6
TI		 2300 return pos;
2301}
2302
2303static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2304{
2305 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2306 struct azx *chip = apcm->chip;
2307 struct azx_dev *azx_dev = get_azx_dev(substream);
2308 return bytes_to_frames(substream->runtime,
798cb7e8 2309 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2310}
2311
2312/*
2313 * Check whether the current DMA position is acceptable for updating
2314 * periods. Returns non-zero if it's OK.
2315 *
2316 * Many HD-audio controllers appear pretty inaccurate about
2317 * the update-IRQ timing. The IRQ is issued before actually the
2318 * data is processed. So, we need to process it afterwords in a
2319 * workqueue.
2320 */
2321static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2322{
e5463720 2323 u32 wallclk;
9ad593f6
TI		 2324 unsigned int pos;
2325
f48f606d
JK		 2326 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2327 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2328 return -1; /* bogus (too early) interrupt */
fa00e046 2329
798cb7e8 2330 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2331
d6d8bf54
TI		 2332 if (WARN_ONCE(!azx_dev->period_bytes,
2333 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2334 return -1; /* this shouldn't happen! */
edb39935 2335 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2336 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2337 /* NG - it's below the first next period boundary */
2338 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2339 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2340 return 1; /* OK, it's fine */
2341}
2342
2343/*
2344 * The work for pending PCM period updates.
2345 */
2346static void azx_irq_pending_work(struct work_struct *work)
2347{
2348 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2349 int i, pending, ok;
9ad593f6 2350
a6a950a8
TI		 2351 if (!chip->irq_pending_warned) {
2352 printk(KERN_WARNING
2353 "hda-intel: IRQ timing workaround is activated "
2354 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2355 chip->card->number);
2356 chip->irq_pending_warned = 1;
2357 }
2358
9ad593f6
TI		 2359 for (;;) {
2360 pending = 0;
2361 spin_lock_irq(&chip->reg_lock);
2362 for (i = 0; i < chip->num_streams; i++) {
2363 struct azx_dev *azx_dev = &chip->azx_dev[i];
2364 if (!azx_dev->irq_pending ||
2365 !azx_dev->substream ||
2366 !azx_dev->running)
2367 continue;
e5463720
JK		 2368 ok = azx_position_ok(chip, azx_dev);
2369 if (ok > 0) {
9ad593f6
TI		 2370 azx_dev->irq_pending = 0;
2371 spin_unlock(&chip->reg_lock);
2372 snd_pcm_period_elapsed(azx_dev->substream);
2373 spin_lock(&chip->reg_lock);
e5463720
JK		 2374 } else if (ok < 0) {
2375 pending = 0; /* too early */
9ad593f6
TI		 2376 } else
2377 pending++;
2378 }
2379 spin_unlock_irq(&chip->reg_lock);
2380 if (!pending)
2381 return;
08af495f 2382 msleep(1);
9ad593f6
TI		 2383 }
2384}
2385
2386/* clear irq_pending flags and assure no on-going workq */
2387static void azx_clear_irq_pending(struct azx *chip)
2388{
2389 int i;
2390
2391 spin_lock_irq(&chip->reg_lock);
2392 for (i = 0; i < chip->num_streams; i++)
2393 chip->azx_dev[i].irq_pending = 0;
2394 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2395}
2396
27fe48d9
TI		 2397#ifdef CONFIG_X86
2398static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2399 struct vm_area_struct *area)
2400{
2401 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2402 struct azx *chip = apcm->chip;
2403 if (!azx_snoop(chip))
2404 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2405 return snd_pcm_lib_default_mmap(substream, area);
2406}
2407#else
2408#define azx_pcm_mmap NULL
2409#endif
2410
a98f90fd 2411static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2412 .open = azx_pcm_open,
2413 .close = azx_pcm_close,
2414 .ioctl = snd_pcm_lib_ioctl,
2415 .hw_params = azx_pcm_hw_params,
2416 .hw_free = azx_pcm_hw_free,
2417 .prepare = azx_pcm_prepare,
2418 .trigger = azx_pcm_trigger,
2419 .pointer = azx_pcm_pointer,
5d890f59 2420 .wall_clock = azx_get_wallclock_tstamp,
27fe48d9 2421 .mmap = azx_pcm_mmap,
4ce107b9 2422 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2423};
2424
a98f90fd 2425static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2426{
176d5335
TI		 2427 struct azx_pcm *apcm = pcm->private_data;
2428 if (apcm) {
01b65bfb 2429 list_del(&apcm->list);
176d5335
TI		 2430 kfree(apcm);
2431 }
1da177e4
LT		 2432}
2433
acfa634f
TI		 2434#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2435
176d5335 2436static int
33fa35ed
TI		 2437azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2438 struct hda_pcm *cpcm)
1da177e4 2439{
33fa35ed 2440 struct azx *chip = bus->private_data;
a98f90fd 2441 struct snd_pcm *pcm;
1da177e4 2442 struct azx_pcm *apcm;
176d5335 2443 int pcm_dev = cpcm->device;
acfa634f 2444 unsigned int size;
176d5335 2445 int s, err;
1da177e4 2446
01b65bfb
TI		 2447 list_for_each_entry(apcm, &chip->pcm_list, list) {
2448 if (apcm->pcm->device == pcm_dev) {
2449 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2450 return -EBUSY;
2451 }
176d5335
TI		 2452 }
2453 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2454 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2455 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2456 &pcm);
2457 if (err < 0)
2458 return err;
18cb7109 2459 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2460 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2461 if (apcm == NULL)
2462 return -ENOMEM;
2463 apcm->chip = chip;
01b65bfb 2464 apcm->pcm = pcm;
1da177e4 2465 apcm->codec = codec;
1da177e4
LT		 2466 pcm->private_data = apcm;
2467 pcm->private_free = azx_pcm_free;
176d5335
TI		 2468 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2469 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2470 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2471 cpcm->pcm = pcm;
2472 for (s = 0; s < 2; s++) {
2473 apcm->hinfo[s] = &cpcm->stream[s];
2474 if (cpcm->stream[s].substreams)
2475 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2476 }
2477 /* buffer pre-allocation */
acfa634f
TI		 2478 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2479 if (size > MAX_PREALLOC_SIZE)
2480 size = MAX_PREALLOC_SIZE;
4ce107b9 2481 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2482 snd_dma_pci_data(chip->pci),
acfa634f 2483 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2484 return 0;
2485}
2486
2487/*
2488 * mixer creation - all stuff is implemented in hda module
2489 */
a98f90fd 2490static int __devinit azx_mixer_create(struct azx *chip)
1da177e4
LT		 2491{
2492 return snd_hda_build_controls(chip->bus);
2493}
2494
2495
2496/*
2497 * initialize SD streams
2498 */
a98f90fd 2499static int __devinit azx_init_stream(struct azx *chip)
1da177e4
LT		 2500{
2501 int i;
2502
2503 /* initialize each stream (aka device)
d01ce99f
TI		 2504 * assign the starting bdl address to each stream (device)
2505 * and initialize
1da177e4 2506 */
07e4ca50 2507 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2508 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2509 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2510 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2511 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2512 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2513 azx_dev->sd_int_sta_mask = 1 << i;
2514 /* stream tag: must be non-zero and unique */
2515 azx_dev->index = i;
2516 azx_dev->stream_tag = i + 1;
2517 }
2518
2519 return 0;
2520}
2521
68e7fffc
TI		 2522static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2523{
437a5a46
TI		 2524 if (request_irq(chip->pci->irq, azx_interrupt,
2525 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2526 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2527 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2528 "disabling device\n", chip->pci->irq);
2529 if (do_disconnect)
2530 snd_card_disconnect(chip->card);
2531 return -1;
2532 }
2533 chip->irq = chip->pci->irq;
69e13418 2534 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2535 return 0;
2536}
2537
1da177e4 2538
cb53c626
TI		 2539static void azx_stop_chip(struct azx *chip)
2540{
95e99fda 2541 if (!chip->initialized)
cb53c626
TI		 2542 return;
2543
2544 /* disable interrupts */
2545 azx_int_disable(chip);
2546 azx_int_clear(chip);
2547
2548 /* disable CORB/RIRB */
2549 azx_free_cmd_io(chip);
2550
2551 /* disable position buffer */
2552 azx_writel(chip, DPLBASE, 0);
2553 azx_writel(chip, DPUBASE, 0);
2554
2555 chip->initialized = 0;
2556}
2557
83012a7c 2558#ifdef CONFIG_PM
cb53c626 2559/* power-up/down the controller */
68467f51 2560static void azx_power_notify(struct hda_bus *bus, bool power_up)
cb53c626 2561{
33fa35ed 2562 struct azx *chip = bus->private_data;
cb53c626 2563
2ea3c6a2
TI		 2564 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2565 return;
2566
68467f51 2567 if (power_up)
b8dfc462
ML		 2568 pm_runtime_get_sync(&chip->pci->dev);
2569 else
2570 pm_runtime_put_sync(&chip->pci->dev);
cb53c626 2571}
65fcd41d
TI		 2572
2573static DEFINE_MUTEX(card_list_lock);
2574static LIST_HEAD(card_list);
2575
2576static void azx_add_card_list(struct azx *chip)
2577{
2578 mutex_lock(&card_list_lock);
2579 list_add(&chip->list, &card_list);
2580 mutex_unlock(&card_list_lock);
2581}
2582
2583static void azx_del_card_list(struct azx *chip)
2584{
2585 mutex_lock(&card_list_lock);
2586 list_del_init(&chip->list);
2587 mutex_unlock(&card_list_lock);
2588}
2589
2590/* trigger power-save check at writing parameter */
2591static int param_set_xint(const char *val, const struct kernel_param *kp)
2592{
2593 struct azx *chip;
2594 struct hda_codec *c;
2595 int prev = power_save;
2596 int ret = param_set_int(val, kp);
2597
2598 if (ret || prev == power_save)
2599 return ret;
2600
2601 mutex_lock(&card_list_lock);
2602 list_for_each_entry(chip, &card_list, list) {
2603 if (!chip->bus || chip->disabled)
2604 continue;
2605 list_for_each_entry(c, &chip->bus->codec_list, list)
2606 snd_hda_power_sync(c);
2607 }
2608 mutex_unlock(&card_list_lock);
2609 return 0;
2610}
2611#else
2612#define azx_add_card_list(chip) /* NOP */
2613#define azx_del_card_list(chip) /* NOP */
83012a7c 2614#endif /* CONFIG_PM */
5c0b9bec 2615
7ccbde57 2616#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 2617/*
2618 * power management
2619 */
68cb2b55 2620static int azx_suspend(struct device *dev)
1da177e4 2621{
68cb2b55
TI		 2622 struct pci_dev *pci = to_pci_dev(dev);
2623 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2624 struct azx *chip = card->private_data;
01b65bfb 2625 struct azx_pcm *p;
1da177e4 2626
421a1252 2627 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2628 azx_clear_irq_pending(chip);
01b65bfb
TI		 2629 list_for_each_entry(p, &chip->pcm_list, list)
2630 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2631 if (chip->initialized)
8dd78330 2632 snd_hda_suspend(chip->bus);
cb53c626 2633 azx_stop_chip(chip);
30b35399 2634 if (chip->irq >= 0) {
43001c95 2635 free_irq(chip->irq, chip);
30b35399
TI		 2636 chip->irq = -1;
2637 }
68e7fffc 2638 if (chip->msi)
43001c95 2639 pci_disable_msi(chip->pci);
421a1252
TI		 2640 pci_disable_device(pci);
2641 pci_save_state(pci);
68cb2b55 2642 pci_set_power_state(pci, PCI_D3hot);
1da177e4
LT		 2643 return 0;
2644}
2645
68cb2b55 2646static int azx_resume(struct device *dev)
1da177e4 2647{
68cb2b55
TI		 2648 struct pci_dev *pci = to_pci_dev(dev);
2649 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2650 struct azx *chip = card->private_data;
1da177e4 2651
d14a7e0b
TI		 2652 pci_set_power_state(pci, PCI_D0);
2653 pci_restore_state(pci);
30b35399
TI		 2654 if (pci_enable_device(pci) < 0) {
2655 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2656 "disabling device\n");
2657 snd_card_disconnect(card);
2658 return -EIO;
2659 }
2660 pci_set_master(pci);
68e7fffc
TI		 2661 if (chip->msi)
2662 if (pci_enable_msi(pci) < 0)
2663 chip->msi = 0;
2664 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2665 return -EIO;
cb53c626 2666 azx_init_pci(chip);
d804ad92 2667
7f30830b 2668 azx_init_chip(chip, 1);
d804ad92 2669
1da177e4 2670 snd_hda_resume(chip->bus);
421a1252 2671 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2672 return 0;
2673}
b8dfc462
ML		 2674#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2675
2676#ifdef CONFIG_PM_RUNTIME
2677static int azx_runtime_suspend(struct device *dev)
2678{
2679 struct snd_card *card = dev_get_drvdata(dev);
2680 struct azx *chip = card->private_data;
2681
2ea3c6a2
TI		 2682 if (!power_save_controller ||
2683 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
b8dfc462
ML		 2684 return -EAGAIN;
2685
2686 azx_stop_chip(chip);
2687 azx_clear_irq_pending(chip);
2688 return 0;
2689}
2690
2691static int azx_runtime_resume(struct device *dev)
2692{
2693 struct snd_card *card = dev_get_drvdata(dev);
2694 struct azx *chip = card->private_data;
2695
2696 azx_init_pci(chip);
2697 azx_init_chip(chip, 1);
2698 return 0;
2699}
2700#endif /* CONFIG_PM_RUNTIME */
2701
2702#ifdef CONFIG_PM
2703static const struct dev_pm_ops azx_pm = {
2704 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2705 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, NULL)
2706};
2707
68cb2b55
TI		 2708#define AZX_PM_OPS &azx_pm
2709#else
68cb2b55 2710#define AZX_PM_OPS NULL
b8dfc462 2711#endif /* CONFIG_PM */
1da177e4
LT		 2712
2713
0cbf0098
TI		 2714/*
2715 * reboot notifier for hang-up problem at power-down
2716 */
2717static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2718{
2719 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2720 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2721 azx_stop_chip(chip);
2722 return NOTIFY_OK;
2723}
2724
2725static void azx_notifier_register(struct azx *chip)
2726{
2727 chip->reboot_notifier.notifier_call = azx_halt;
2728 register_reboot_notifier(&chip->reboot_notifier);
2729}
2730
2731static void azx_notifier_unregister(struct azx *chip)
2732{
2733 if (chip->reboot_notifier.notifier_call)
2734 unregister_reboot_notifier(&chip->reboot_notifier);
2735}
2736
a82d51ed
TI		 2737static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2738static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2739
8393ec4a 2740#ifdef SUPPORT_VGA_SWITCHEROO
a82d51ed
TI		 2741static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2742
a82d51ed
TI		 2743static void azx_vs_set_state(struct pci_dev *pci,
2744 enum vga_switcheroo_state state)
2745{
2746 struct snd_card *card = pci_get_drvdata(pci);
2747 struct azx *chip = card->private_data;
2748 bool disabled;
2749
f4c482a4 2750 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 2751 if (chip->init_failed)
2752 return;
2753
2754 disabled = (state == VGA_SWITCHEROO_OFF);
2755 if (chip->disabled == disabled)
2756 return;
2757
2758 if (!chip->bus) {
2759 chip->disabled = disabled;
2760 if (!disabled) {
2761 snd_printk(KERN_INFO SFX
2762 "%s: Start delayed initialization\n",
2763 pci_name(chip->pci));
2764 if (azx_first_init(chip) < 0 ||
2765 azx_probe_continue(chip) < 0) {
2766 snd_printk(KERN_ERR SFX
2767 "%s: initialization error\n",
2768 pci_name(chip->pci));
2769 chip->init_failed = true;
2770 }
2771 }
2772 } else {
2773 snd_printk(KERN_INFO SFX
2774 "%s %s via VGA-switcheroo\n",
2775 disabled ? "Disabling" : "Enabling",
2776 pci_name(chip->pci));
2777 if (disabled) {
68cb2b55 2778 azx_suspend(&pci->dev);
a82d51ed 2779 chip->disabled = true;
128960a9
TI		 2780 if (snd_hda_lock_devices(chip->bus))
2781 snd_printk(KERN_WARNING SFX
2782 "Cannot lock devices!\n");
a82d51ed
TI		 2783 } else {
2784 snd_hda_unlock_devices(chip->bus);
2785 chip->disabled = false;
68cb2b55 2786 azx_resume(&pci->dev);
a82d51ed
TI		 2787 }
2788 }
2789}
2790
2791static bool azx_vs_can_switch(struct pci_dev *pci)
2792{
2793 struct snd_card *card = pci_get_drvdata(pci);
2794 struct azx *chip = card->private_data;
2795
f4c482a4 2796 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 2797 if (chip->init_failed)
2798 return false;
2799 if (chip->disabled || !chip->bus)
2800 return true;
2801 if (snd_hda_lock_devices(chip->bus))
2802 return false;
2803 snd_hda_unlock_devices(chip->bus);
2804 return true;
2805}
2806
2807static void __devinit init_vga_switcheroo(struct azx *chip)
2808{
2809 struct pci_dev *p = get_bound_vga(chip->pci);
2810 if (p) {
2811 snd_printk(KERN_INFO SFX
2812 "%s: Handle VGA-switcheroo audio client\n",
2813 pci_name(chip->pci));
2814 chip->use_vga_switcheroo = 1;
2815 pci_dev_put(p);
2816 }
2817}
2818
2819static const struct vga_switcheroo_client_ops azx_vs_ops = {
2820 .set_gpu_state = azx_vs_set_state,
2821 .can_switch = azx_vs_can_switch,
2822};
2823
2824static int __devinit register_vga_switcheroo(struct azx *chip)
2825{
128960a9
TI		 2826 int err;
2827
a82d51ed
TI		 2828 if (!chip->use_vga_switcheroo)
2829 return 0;
2830 /* FIXME: currently only handling DIS controller
2831 * is there any machine with two switchable HDMI audio controllers?
2832 */
128960a9 2833 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 2834 VGA_SWITCHEROO_DIS,
2835 chip->bus != NULL);
128960a9
TI		 2836 if (err < 0)
2837 return err;
2838 chip->vga_switcheroo_registered = 1;
2839 return 0;
a82d51ed
TI		 2840}
2841#else
2842#define init_vga_switcheroo(chip) /* NOP */
2843#define register_vga_switcheroo(chip) 0
8393ec4a 2844#define check_hdmi_disabled(pci) false
a82d51ed
TI		 2845#endif /* SUPPORT_VGA_SWITCHER */
2846
1da177e4
LT		 2847/*
2848 * destructor
2849 */
a98f90fd 2850static int azx_free(struct azx *chip)
1da177e4 2851{
4ce107b9
TI		 2852 int i;
2853
65fcd41d
TI		 2854 azx_del_card_list(chip);
2855
0cbf0098
TI		 2856 azx_notifier_unregister(chip);
2857
f4c482a4
TI		 2858 chip->init_failed = 1; /* to be sure */
2859 complete(&chip->probe_wait);
2860
a82d51ed
TI		 2861 if (use_vga_switcheroo(chip)) {
2862 if (chip->disabled && chip->bus)
2863 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 2864 if (chip->vga_switcheroo_registered)
2865 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 2866 }
2867
ce43fbae 2868 if (chip->initialized) {
9ad593f6 2869 azx_clear_irq_pending(chip);
07e4ca50 2870 for (i = 0; i < chip->num_streams; i++)
1da177e4 2871 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2872 azx_stop_chip(chip);
1da177e4
LT		 2873 }
2874
f000fd80 2875 if (chip->irq >= 0)
1da177e4 2876 free_irq(chip->irq, (void*)chip);
68e7fffc 2877 if (chip->msi)
30b35399 2878 pci_disable_msi(chip->pci);
f079c25a
TI		 2879 if (chip->remap_addr)
2880 iounmap(chip->remap_addr);
1da177e4 2881
4ce107b9
TI		 2882 if (chip->azx_dev) {
2883 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 2884 if (chip->azx_dev[i].bdl.area) {
2885 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 2886 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 2887 }
4ce107b9 2888 }
27fe48d9
TI		 2889 if (chip->rb.area) {
2890 mark_pages_wc(chip, &chip->rb, false);
1da177e4 2891 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 2892 }
2893 if (chip->posbuf.area) {
2894 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 2895 snd_dma_free_pages(&chip->posbuf);
27fe48d9 2896 }
a82d51ed
TI		 2897 if (chip->region_requested)
2898 pci_release_regions(chip->pci);
1da177e4 2899 pci_disable_device(chip->pci);
07e4ca50 2900 kfree(chip->azx_dev);
4918cdab
TI		 2901#ifdef CONFIG_SND_HDA_PATCH_LOADER
2902 if (chip->fw)
2903 release_firmware(chip->fw);
2904#endif
1da177e4
LT		 2905 kfree(chip);
2906
2907 return 0;
2908}
2909
a98f90fd 2910static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2911{
2912 return azx_free(device->device_data);
2913}
2914
8393ec4a 2915#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 2916/*
2917 * Check of disabled HDMI controller by vga-switcheroo
2918 */
2919static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2920{
2921 struct pci_dev *p;
2922
2923 /* check only discrete GPU */
2924 switch (pci->vendor) {
2925 case PCI_VENDOR_ID_ATI:
2926 case PCI_VENDOR_ID_AMD:
2927 case PCI_VENDOR_ID_NVIDIA:
2928 if (pci->devfn == 1) {
2929 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2930 pci->bus->number, 0);
2931 if (p) {
2932 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2933 return p;
2934 pci_dev_put(p);
2935 }
2936 }
2937 break;
2938 }
2939 return NULL;
2940}
2941
2942static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2943{
2944 bool vga_inactive = false;
2945 struct pci_dev *p = get_bound_vga(pci);
2946
2947 if (p) {
12b78a7f 2948 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 2949 vga_inactive = true;
2950 pci_dev_put(p);
2951 }
2952 return vga_inactive;
2953}
8393ec4a 2954#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 2955
3372a153
TI		 2956/*
2957 * white/black-listing for position_fix
2958 */
623ec047 2959static struct snd_pci_quirk position_fix_list[] __devinitdata = {
d2e1c973
TI		 2960 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2961 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2962 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2963 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 2964 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 2965 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 2966 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 2967 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 2968 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 2969 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2970 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 2971 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 2972 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 2973 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 2974 {}
2975};
2976
2977static int __devinit check_position_fix(struct azx *chip, int fix)
2978{
2979 const struct snd_pci_quirk *q;
2980
c673ba1c 2981 switch (fix) {
1dac6695 2982 case POS_FIX_AUTO:
c673ba1c
TI		 2983 case POS_FIX_LPIB:
2984 case POS_FIX_POSBUF:
4cb36310 2985 case POS_FIX_VIACOMBO:
a6f2fd55 2986 case POS_FIX_COMBO:
c673ba1c
TI		 2987 return fix;
2988 }
2989
c673ba1c
TI		 2990 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2991 if (q) {
2992 printk(KERN_INFO
2993 "hda_intel: position_fix set to %d "
2994 "for device %04x:%04x\n",
2995 q->value, q->subvendor, q->subdevice);
2996 return q->value;
3372a153 2997 }
bdd9ef24
DH		 2998
2999 /* Check VIA/ATI HD Audio Controller exist */
9477c58e
TI		 3000 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3001 snd_printd(SFX "Using VIACOMBO position fix\n");
bdd9ef24 3002 return POS_FIX_VIACOMBO;
9477c58e
TI		 3003 }
3004 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3005 snd_printd(SFX "Using LPIB position fix\n");
50e3bbf9 3006 return POS_FIX_LPIB;
bdd9ef24 3007 }
c673ba1c 3008 return POS_FIX_AUTO;
3372a153
TI		 3009}
3010
669ba27a
TI		 3011/*
3012 * black-lists for probe_mask
3013 */
3014static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
3015 /* Thinkpad often breaks the controller communication when accessing
3016 * to the non-working (or non-existing) modem codec slot.
3017 */
3018 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3019 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3020 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 3021 /* broken BIOS */
3022 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 3023 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3024 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 3025 /* forced codec slots */
93574844 3026 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 3027 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 3028 /* WinFast VP200 H (Teradici) user reported broken communication */
3029 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 3030 {}
3031};
3032
f1eaaeec
TI		 3033#define AZX_FORCE_CODEC_MASK 0x100
3034
5aba4f8e 3035static void __devinit check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 3036{
3037 const struct snd_pci_quirk *q;
3038
f1eaaeec
TI		 3039 chip->codec_probe_mask = probe_mask[dev];
3040 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 3041 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3042 if (q) {
3043 printk(KERN_INFO
3044 "hda_intel: probe_mask set to 0x%x "
3045 "for device %04x:%04x\n",
3046 q->value, q->subvendor, q->subdevice);
f1eaaeec 3047 chip->codec_probe_mask = q->value;
669ba27a
TI		 3048 }
3049 }
f1eaaeec
TI		 3050
3051 /* check forced option */
3052 if (chip->codec_probe_mask != -1 &&
3053 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3054 chip->codec_mask = chip->codec_probe_mask & 0xff;
3055 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3056 chip->codec_mask);
3057 }
669ba27a
TI		 3058}
3059
4d8e22e0 3060/*
71623855 3061 * white/black-list for enable_msi
4d8e22e0 3062 */
71623855 3063static struct snd_pci_quirk msi_black_list[] __devinitdata = {
9dc8398b 3064 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 3065 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 3066 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 3067 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 3068 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 3069 {}
3070};
3071
3072static void __devinit check_msi(struct azx *chip)
3073{
3074 const struct snd_pci_quirk *q;
3075
71623855
TI		 3076 if (enable_msi >= 0) {
3077 chip->msi = !!enable_msi;
4d8e22e0 3078 return;
71623855
TI		 3079 }
3080 chip->msi = 1; /* enable MSI as default */
3081 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 3082 if (q) {
3083 printk(KERN_INFO
3084 "hda_intel: msi for device %04x:%04x set to %d\n",
3085 q->subvendor, q->subdevice, q->value);
3086 chip->msi = q->value;
80c43ed7
TI		 3087 return;
3088 }
3089
3090 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 3091 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3092 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 3093 chip->msi = 0;
4d8e22e0
TI		 3094 }
3095}
3096
a1585d76
TI		 3097/* check the snoop mode availability */
3098static void __devinit azx_check_snoop_available(struct azx *chip)
3099{
3100 bool snoop = chip->snoop;
3101
3102 switch (chip->driver_type) {
3103 case AZX_DRIVER_VIA:
3104 /* force to non-snoop mode for a new VIA controller
3105 * when BIOS is set
3106 */
3107 if (snoop) {
3108 u8 val;
3109 pci_read_config_byte(chip->pci, 0x42, &val);
3110 if (!(val & 0x80) && chip->pci->revision == 0x30)
3111 snoop = false;
3112 }
3113 break;
3114 case AZX_DRIVER_ATIHDMI_NS:
3115 /* new ATI HDMI requires non-snoop */
3116 snoop = false;
3117 break;
3118 }
3119
3120 if (snoop != chip->snoop) {
3121 snd_printk(KERN_INFO SFX "Force to %s mode\n",
3122 snoop ? "snoop" : "non-snoop");
3123 chip->snoop = snoop;
3124 }
3125}
669ba27a 3126
1da177e4
LT		 3127/*
3128 * constructor
3129 */
a98f90fd 3130static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
9477c58e 3131 int dev, unsigned int driver_caps,
a98f90fd 3132 struct azx **rchip)
1da177e4 3133{
a98f90fd 3134 static struct snd_device_ops ops = {
1da177e4
LT		 3135 .dev_free = azx_dev_free,
3136 };
a82d51ed
TI		 3137 struct azx *chip;
3138 int err;
1da177e4
LT		 3139
3140 *rchip = NULL;
bcd72003 3141
927fc866
PM		 3142 err = pci_enable_device(pci);
3143 if (err < 0)
1da177e4
LT		 3144 return err;
3145
e560d8d8 3146 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 3147 if (!chip) {
1da177e4
LT		 3148 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
3149 pci_disable_device(pci);
3150 return -ENOMEM;
3151 }
3152
3153 spin_lock_init(&chip->reg_lock);
62932df8 3154 mutex_init(&chip->open_mutex);
1da177e4
LT		 3155 chip->card = card;
3156 chip->pci = pci;
3157 chip->irq = -1;
9477c58e
TI		 3158 chip->driver_caps = driver_caps;
3159 chip->driver_type = driver_caps & 0xff;
4d8e22e0 3160 check_msi(chip);
555e219f 3161 chip->dev_index = dev;
9ad593f6 3162 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 3163 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 3164 INIT_LIST_HEAD(&chip->list);
a82d51ed 3165 init_vga_switcheroo(chip);
f4c482a4 3166 init_completion(&chip->probe_wait);
1da177e4 3167
beaffc39
SG		 3168 chip->position_fix[0] = chip->position_fix[1] =
3169 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 3170 /* combo mode uses LPIB for playback */
3171 if (chip->position_fix[0] == POS_FIX_COMBO) {
3172 chip->position_fix[0] = POS_FIX_LPIB;
3173 chip->position_fix[1] = POS_FIX_AUTO;
3174 }
3175
5aba4f8e 3176 check_probe_mask(chip, dev);
3372a153 3177
27346166 3178 chip->single_cmd = single_cmd;
27fe48d9 3179 chip->snoop = hda_snoop;
a1585d76 3180 azx_check_snoop_available(chip);
c74db86b 3181
5c0d7bc1
TI		 3182 if (bdl_pos_adj[dev] < 0) {
3183 switch (chip->driver_type) {
0c6341ac 3184 case AZX_DRIVER_ICH:
32679f95 3185 case AZX_DRIVER_PCH:
0c6341ac 3186 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 3187 break;
3188 default:
0c6341ac 3189 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 3190 break;
3191 }
3192 }
3193
a82d51ed
TI		 3194 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3195 if (err < 0) {
3196 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3197 azx_free(chip);
3198 return err;
3199 }
3200
3201 *rchip = chip;
3202 return 0;
3203}
3204
3205static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3206{
3207 int dev = chip->dev_index;
3208 struct pci_dev *pci = chip->pci;
3209 struct snd_card *card = chip->card;
3210 int i, err;
3211 unsigned short gcap;
3212
07e4ca50
TI		 3213#if BITS_PER_LONG != 64
3214 /* Fix up base address on ULI M5461 */
3215 if (chip->driver_type == AZX_DRIVER_ULI) {
3216 u16 tmp3;
3217 pci_read_config_word(pci, 0x40, &tmp3);
3218 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3219 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3220 }
3221#endif
3222
927fc866 3223 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 3224 if (err < 0)
1da177e4 3225 return err;
a82d51ed 3226 chip->region_requested = 1;
1da177e4 3227
927fc866 3228 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 3229 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4
LT		 3230 if (chip->remap_addr == NULL) {
3231 snd_printk(KERN_ERR SFX "ioremap error\n");
a82d51ed 3232 return -ENXIO;
1da177e4
LT		 3233 }
3234
68e7fffc
TI		 3235 if (chip->msi)
3236 if (pci_enable_msi(pci) < 0)
3237 chip->msi = 0;
7376d013 3238
a82d51ed
TI		 3239 if (azx_acquire_irq(chip, 0) < 0)
3240 return -EBUSY;
1da177e4
LT		 3241
3242 pci_set_master(pci);
3243 synchronize_irq(chip->irq);
3244
bcd72003 3245 gcap = azx_readw(chip, GCAP);
4abc1cc2 3246 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
bcd72003 3247
dc4c2e6b 3248 /* disable SB600 64bit support for safety */
9477c58e 3249 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3250 struct pci_dev *p_smbus;
3251 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3252 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3253 NULL);
3254 if (p_smbus) {
3255 if (p_smbus->revision < 0x30)
3256 gcap &= ~ICH6_GCAP_64OK;
3257 pci_dev_put(p_smbus);
3258 }
3259 }
09240cf4 3260
9477c58e
TI		 3261 /* disable 64bit DMA address on some devices */
3262 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3263 snd_printd(SFX "Disabling 64bit DMA\n");
396087ea 3264 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3265 }
396087ea 3266
2ae66c26 3267 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3268 if (align_buffer_size >= 0)
3269 chip->align_buffer_size = !!align_buffer_size;
3270 else {
3271 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3272 chip->align_buffer_size = 0;
3273 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3274 chip->align_buffer_size = 1;
3275 else
3276 chip->align_buffer_size = 1;
3277 }
2ae66c26 3278
cf7aaca8 3279 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3280 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3281 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3282 else {
e930438c
YH		 3283 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3284 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3285 }
cf7aaca8 3286
8b6ed8e7
TI		 3287 /* read number of streams from GCAP register instead of using
3288 * hardcoded value
3289 */
3290 chip->capture_streams = (gcap >> 8) & 0x0f;
3291 chip->playback_streams = (gcap >> 12) & 0x0f;
3292 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3293 /* gcap didn't give any info, switching to old method */
3294
3295 switch (chip->driver_type) {
3296 case AZX_DRIVER_ULI:
3297 chip->playback_streams = ULI_NUM_PLAYBACK;
3298 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3299 break;
3300 case AZX_DRIVER_ATIHDMI:
1815b34a 3301 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3302 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3303 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3304 break;
c4da29ca 3305 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3306 default:
3307 chip->playback_streams = ICH6_NUM_PLAYBACK;
3308 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3309 break;
3310 }
07e4ca50 3311 }
8b6ed8e7
TI		 3312 chip->capture_index_offset = 0;
3313 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3314 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3315 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3316 GFP_KERNEL);
927fc866 3317 if (!chip->azx_dev) {
4abc1cc2 3318 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
a82d51ed 3319 return -ENOMEM;
07e4ca50
TI		 3320 }
3321
4ce107b9
TI		 3322 for (i = 0; i < chip->num_streams; i++) {
3323 /* allocate memory for the BDL for each stream */
3324 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3325 snd_dma_pci_data(chip->pci),
3326 BDL_SIZE, &chip->azx_dev[i].bdl);
3327 if (err < 0) {
3328 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
a82d51ed 3329 return -ENOMEM;
4ce107b9 3330 }
27fe48d9 3331 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3332 }
0be3b5d3 3333 /* allocate memory for the position buffer */
d01ce99f
TI		 3334 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3335 snd_dma_pci_data(chip->pci),
3336 chip->num_streams * 8, &chip->posbuf);
3337 if (err < 0) {
0be3b5d3 3338 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
a82d51ed 3339 return -ENOMEM;
1da177e4 3340 }
27fe48d9 3341 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3342 /* allocate CORB/RIRB */
81740861
TI		 3343 err = azx_alloc_cmd_io(chip);
3344 if (err < 0)
a82d51ed 3345 return err;
1da177e4
LT		 3346
3347 /* initialize streams */
3348 azx_init_stream(chip);
3349
3350 /* initialize chip */
cb53c626 3351 azx_init_pci(chip);
10e77dda 3352 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3353
3354 /* codec detection */
927fc866 3355 if (!chip->codec_mask) {
1da177e4 3356 snd_printk(KERN_ERR SFX "no codecs found!\n");
a82d51ed 3357 return -ENODEV;
1da177e4
LT		 3358 }
3359
07e4ca50 3360 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3361 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3362 sizeof(card->shortname));
3363 snprintf(card->longname, sizeof(card->longname),
3364 "%s at 0x%lx irq %i",
3365 card->shortname, chip->addr, chip->irq);
07e4ca50 3366
1da177e4 3367 return 0;
1da177e4
LT		 3368}
3369
cb53c626
TI		 3370static void power_down_all_codecs(struct azx *chip)
3371{
83012a7c 3372#ifdef CONFIG_PM
cb53c626
TI		 3373 /* The codecs were powered up in snd_hda_codec_new().
3374 * Now all initialization done, so turn them down if possible
3375 */
3376 struct hda_codec *codec;
3377 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3378 snd_hda_power_down(codec);
3379 }
3380#endif
3381}
3382
97c6a3d1 3383#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 3384/* callback from request_firmware_nowait() */
3385static void azx_firmware_cb(const struct firmware *fw, void *context)
3386{
3387 struct snd_card *card = context;
3388 struct azx *chip = card->private_data;
3389 struct pci_dev *pci = chip->pci;
3390
3391 if (!fw) {
3392 snd_printk(KERN_ERR SFX "Cannot load firmware, aborting\n");
3393 goto error;
3394 }
3395
3396 chip->fw = fw;
3397 if (!chip->disabled) {
3398 /* continue probing */
3399 if (azx_probe_continue(chip))
3400 goto error;
3401 }
3402 return; /* OK */
3403
3404 error:
3405 snd_card_free(card);
3406 pci_set_drvdata(pci, NULL);
3407}
97c6a3d1 3408#endif
5cb543db 3409
d01ce99f
TI		 3410static int __devinit azx_probe(struct pci_dev *pci,
3411 const struct pci_device_id *pci_id)
1da177e4 3412{
5aba4f8e 3413 static int dev;
a98f90fd
TI		 3414 struct snd_card *card;
3415 struct azx *chip;
5cb543db 3416 bool probe_now;
927fc866 3417 int err;
1da177e4 3418
5aba4f8e
TI		 3419 if (dev >= SNDRV_CARDS)
3420 return -ENODEV;
3421 if (!enable[dev]) {
3422 dev++;
3423 return -ENOENT;
3424 }
3425
e58de7ba
TI		 3426 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3427 if (err < 0) {
1da177e4 3428 snd_printk(KERN_ERR SFX "Error creating card!\n");
e58de7ba 3429 return err;
1da177e4
LT		 3430 }
3431
4ea6fbc8
TI		 3432 snd_card_set_dev(card, &pci->dev);
3433
5aba4f8e 3434 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3435 if (err < 0)
3436 goto out_free;
421a1252 3437 card->private_data = chip;
f4c482a4
TI		 3438
3439 pci_set_drvdata(pci, card);
3440
3441 err = register_vga_switcheroo(chip);
3442 if (err < 0) {
3443 snd_printk(KERN_ERR SFX
3444 "Error registering VGA-switcheroo client\n");
3445 goto out_free;
3446 }
3447
3448 if (check_hdmi_disabled(pci)) {
3449 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
3450 pci_name(pci));
3451 snd_printk(KERN_INFO SFX "Delaying initialization\n");
3452 chip->disabled = true;
3453 }
3454
5cb543db 3455 probe_now = !chip->disabled;
f4c482a4
TI		 3456 if (probe_now) {
3457 err = azx_first_init(chip);
3458 if (err < 0)
3459 goto out_free;
3460 }
1da177e4 3461
4918cdab
TI		 3462#ifdef CONFIG_SND_HDA_PATCH_LOADER
3463 if (patch[dev] && *patch[dev]) {
3464 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3465 patch[dev]);
5cb543db
TI		 3466 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3467 &pci->dev, GFP_KERNEL, card,
3468 azx_firmware_cb);
4918cdab
TI		 3469 if (err < 0)
3470 goto out_free;
5cb543db 3471 probe_now = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 3472 }
3473#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3474
5cb543db 3475 if (probe_now) {
a82d51ed
TI		 3476 err = azx_probe_continue(chip);
3477 if (err < 0)
3478 goto out_free;
3479 }
3480
b8dfc462
ML		 3481 if (pci_dev_run_wake(pci))
3482 pm_runtime_put_noidle(&pci->dev);
3483
a82d51ed 3484 dev++;
f4c482a4 3485 complete(&chip->probe_wait);
a82d51ed
TI		 3486 return 0;
3487
3488out_free:
3489 snd_card_free(card);
f4c482a4 3490 pci_set_drvdata(pci, NULL);
a82d51ed
TI		 3491 return err;
3492}
3493
3494static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3495{
3496 int dev = chip->dev_index;
3497 int err;
3498
2dca0bba
JK		 3499#ifdef CONFIG_SND_HDA_INPUT_BEEP
3500 chip->beep_mode = beep_mode[dev];
3501#endif
3502
1da177e4 3503 /* create codec instances */
a1e21c90 3504 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3505 if (err < 0)
3506 goto out_free;
4ea6fbc8 3507#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 3508 if (chip->fw) {
3509 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3510 chip->fw->data);
4ea6fbc8
TI		 3511 if (err < 0)
3512 goto out_free;
e39ae856 3513#ifndef CONFIG_PM
4918cdab
TI		 3514 release_firmware(chip->fw); /* no longer needed */
3515 chip->fw = NULL;
e39ae856 3516#endif
4ea6fbc8
TI		 3517 }
3518#endif
10e77dda 3519 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3520 err = azx_codec_configure(chip);
3521 if (err < 0)
3522 goto out_free;
3523 }
1da177e4
LT		 3524
3525 /* create PCM streams */
176d5335 3526 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3527 if (err < 0)
3528 goto out_free;
1da177e4
LT		 3529
3530 /* create mixer controls */
d01ce99f 3531 err = azx_mixer_create(chip);
41dda0fd
WF		 3532 if (err < 0)
3533 goto out_free;
1da177e4 3534
a82d51ed 3535 err = snd_card_register(chip->card);
41dda0fd
WF		 3536 if (err < 0)
3537 goto out_free;
1da177e4 3538
cb53c626
TI		 3539 chip->running = 1;
3540 power_down_all_codecs(chip);
0cbf0098 3541 azx_notifier_register(chip);
65fcd41d 3542 azx_add_card_list(chip);
1da177e4 3543
9121947d
TI		 3544 return 0;
3545
41dda0fd 3546out_free:
a82d51ed 3547 chip->init_failed = 1;
41dda0fd 3548 return err;
1da177e4
LT		 3549}
3550
3551static void __devexit azx_remove(struct pci_dev *pci)
3552{
9121947d 3553 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462
ML		 3554
3555 if (pci_dev_run_wake(pci))
3556 pm_runtime_get_noresume(&pci->dev);
3557
9121947d
TI		 3558 if (card)
3559 snd_card_free(card);
1da177e4
LT		 3560 pci_set_drvdata(pci, NULL);
3561}
3562
3563/* PCI IDs */
cebe41d4 3564static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3565 /* CPT */
9477c58e 3566 { PCI_DEVICE(0x8086, 0x1c20),
2ea3c6a2 3567 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
cea310e8 3568 /* PBG */
9477c58e 3569 { PCI_DEVICE(0x8086, 0x1d20),
2ea3c6a2 3570 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
d2edeb7c 3571 /* Panther Point */
9477c58e 3572 { PCI_DEVICE(0x8086, 0x1e20),
2ea3c6a2 3573 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 3574 /* Lynx Point */
3575 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 3576 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3577 /* Lynx Point-LP */
3578 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 3579 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3580 /* Lynx Point-LP */
3581 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 3582 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8
WX		 3583 /* Haswell */
3584 { PCI_DEVICE(0x8086, 0x0c0c),
2ea3c6a2 3585 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
d279fae8 3586 { PCI_DEVICE(0x8086, 0x0d0c),
2ea3c6a2 3587 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
99df18b3
PLB		 3588 /* 5 Series/3400 */
3589 { PCI_DEVICE(0x8086, 0x3b56),
2ea3c6a2 3590 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
87218e9c 3591 /* SCH */
9477c58e 3592 { PCI_DEVICE(0x8086, 0x811b),
2ae66c26 3593 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
645e9035 3594 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
09904b95
LP		 3595 { PCI_DEVICE(0x8086, 0x080a),
3596 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
716e5db4 3597 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
645e9035 3598 /* ICH */
8b0bd226 3599 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 3600 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3601 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 3602 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 3603 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3604 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 3605 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 3606 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3607 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 3608 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 3609 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3610 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 3611 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 3612 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3613 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3614 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 3615 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3616 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3617 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 3618 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3619 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 3620 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 3621 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3622 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 3623 /* Generic Intel */
3624 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3625 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3626 .class_mask = 0xffffff,
2ae66c26 3627 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 3628 /* ATI SB 450/600/700/800/900 */
3629 { PCI_DEVICE(0x1002, 0x437b),
3630 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3631 { PCI_DEVICE(0x1002, 0x4383),
3632 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3633 /* AMD Hudson */
3634 { PCI_DEVICE(0x1022, 0x780d),
3635 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 3636 /* ATI HDMI */
9477c58e
TI		 3637 { PCI_DEVICE(0x1002, 0x793b),
3638 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3639 { PCI_DEVICE(0x1002, 0x7919),
3640 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3641 { PCI_DEVICE(0x1002, 0x960f),
3642 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3643 { PCI_DEVICE(0x1002, 0x970f),
3644 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3645 { PCI_DEVICE(0x1002, 0xaa00),
3646 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3647 { PCI_DEVICE(0x1002, 0xaa08),
3648 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3649 { PCI_DEVICE(0x1002, 0xaa10),
3650 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3651 { PCI_DEVICE(0x1002, 0xaa18),
3652 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3653 { PCI_DEVICE(0x1002, 0xaa20),
3654 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3655 { PCI_DEVICE(0x1002, 0xaa28),
3656 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3657 { PCI_DEVICE(0x1002, 0xaa30),
3658 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3659 { PCI_DEVICE(0x1002, 0xaa38),
3660 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3661 { PCI_DEVICE(0x1002, 0xaa40),
3662 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3663 { PCI_DEVICE(0x1002, 0xaa48),
3664 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 3665 { PCI_DEVICE(0x1002, 0x9902),
3666 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3667 { PCI_DEVICE(0x1002, 0xaaa0),
3668 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3669 { PCI_DEVICE(0x1002, 0xaaa8),
3670 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3671 { PCI_DEVICE(0x1002, 0xaab0),
3672 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 3673 /* VIA VT8251/VT8237A */
9477c58e
TI		 3674 { PCI_DEVICE(0x1106, 0x3288),
3675 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 3676 /* VIA GFX VT7122/VX900 */
3677 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3678 /* VIA GFX VT6122/VX11 */
3679 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 3680 /* SIS966 */
3681 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3682 /* ULI M5461 */
3683 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3684 /* NVIDIA MCP */
0c2fd1bf
TI		 3685 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3686 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3687 .class_mask = 0xffffff,
9477c58e 3688 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 3689 /* Teradici */
9477c58e
TI		 3690 { PCI_DEVICE(0x6549, 0x1200),
3691 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 3692 { PCI_DEVICE(0x6549, 0x2200),
3693 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 3694 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 3695 /* CTHDA chips */
3696 { PCI_DEVICE(0x1102, 0x0010),
3697 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3698 { PCI_DEVICE(0x1102, 0x0012),
3699 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
313f6e2d
TI		 3700#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3701 /* the following entry conflicts with snd-ctxfi driver,
3702 * as ctxfi driver mutates from HD-audio to native mode with
3703 * a special command sequence.
3704 */
4e01f54b
TI		 3705 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3706 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3707 .class_mask = 0xffffff,
9477c58e 3708 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3709 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 3710#else
3711 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 3712 { PCI_DEVICE(0x1102, 0x0009),
3713 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3714 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 3715#endif
e35d4b11
OS		 3716 /* Vortex86MX */
3717 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 3718 /* VMware HDAudio */
3719 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 3720 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 3721 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3722 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3723 .class_mask = 0xffffff,
9477c58e 3724 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 3725 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3726 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3727 .class_mask = 0xffffff,
9477c58e 3728 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 3729 { 0, }
3730};
3731MODULE_DEVICE_TABLE(pci, azx_ids);
3732
3733/* pci_driver definition */
e9f66d9b 3734static struct pci_driver azx_driver = {
3733e424 3735 .name = KBUILD_MODNAME,
1da177e4
LT		 3736 .id_table = azx_ids,
3737 .probe = azx_probe,
3738 .remove = __devexit_p(azx_remove),
68cb2b55
TI		 3739 .driver = {
3740 .pm = AZX_PM_OPS,
3741 },
1da177e4
LT		 3742};
3743
e9f66d9b 3744module_pci_driver(azx_driver);
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