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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * | |
d01ce99f TI |
4 | * hda_intel.c - Implementation of primary alsa driver code base |
5 | * for Intel HD Audio. | |
1da177e4 LT |
6 | * |
7 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
10 | * PeiSen Hou <pshou@realtek.com.tw> | |
11 | * | |
1da177e4 LT |
12 | * CONTACTS: |
13 | * | |
14 | * Matt Jared matt.jared@intel.com | |
15 | * Andy Kopp andy.kopp@intel.com | |
16 | * Dan Kogan dan.d.kogan@intel.com | |
17 | * | |
18 | * CHANGES: | |
19 | * | |
20 | * 2004.12.01 Major rewrite by tiwai, merged the work of pshou | |
1da177e4 LT |
21 | */ |
22 | ||
1da177e4 LT |
23 | #include <linux/delay.h> |
24 | #include <linux/interrupt.h> | |
362775e2 | 25 | #include <linux/kernel.h> |
1da177e4 | 26 | #include <linux/module.h> |
24982c5f | 27 | #include <linux/dma-mapping.h> |
1da177e4 LT |
28 | #include <linux/moduleparam.h> |
29 | #include <linux/init.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/pci.h> | |
62932df8 | 32 | #include <linux/mutex.h> |
27fe48d9 | 33 | #include <linux/io.h> |
b8dfc462 | 34 | #include <linux/pm_runtime.h> |
5d890f59 PLB |
35 | #include <linux/clocksource.h> |
36 | #include <linux/time.h> | |
f4c482a4 | 37 | #include <linux/completion.h> |
586bc4aa | 38 | #include <linux/acpi.h> |
65fddcfc | 39 | #include <linux/pgtable.h> |
5d890f59 | 40 | |
27fe48d9 TI |
41 | #ifdef CONFIG_X86 |
42 | /* for snoop control */ | |
7f80f513 | 43 | #include <asm/set_memory.h> |
50279d9b | 44 | #include <asm/cpufeature.h> |
27fe48d9 | 45 | #endif |
1da177e4 LT |
46 | #include <sound/core.h> |
47 | #include <sound/initval.h> | |
98d8fc6c ML |
48 | #include <sound/hdaudio.h> |
49 | #include <sound/hda_i915.h> | |
82d9d54a | 50 | #include <sound/intel-dsp-config.h> |
9121947d | 51 | #include <linux/vgaarb.h> |
a82d51ed | 52 | #include <linux/vga_switcheroo.h> |
4918cdab | 53 | #include <linux/firmware.h> |
be57bfff | 54 | #include <sound/hda_codec.h> |
05e84878 | 55 | #include "hda_controller.h" |
347de1f8 | 56 | #include "hda_intel.h" |
1da177e4 | 57 | |
785d8c4b LY |
58 | #define CREATE_TRACE_POINTS |
59 | #include "hda_intel_trace.h" | |
60 | ||
b6050ef6 TI |
61 | /* position fix mode */ |
62 | enum { | |
63 | POS_FIX_AUTO, | |
64 | POS_FIX_LPIB, | |
65 | POS_FIX_POSBUF, | |
66 | POS_FIX_VIACOMBO, | |
67 | POS_FIX_COMBO, | |
f87e7f25 | 68 | POS_FIX_SKL, |
c02f77d3 | 69 | POS_FIX_FIFO, |
b6050ef6 TI |
70 | }; |
71 | ||
9a34af4a TI |
72 | /* Defines for ATI HD Audio support in SB450 south bridge */ |
73 | #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 | |
74 | #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 | |
75 | ||
76 | /* Defines for Nvidia HDA support */ | |
77 | #define NVIDIA_HDA_TRANSREG_ADDR 0x4e | |
78 | #define NVIDIA_HDA_ENABLE_COHBITS 0x0f | |
79 | #define NVIDIA_HDA_ISTRM_COH 0x4d | |
80 | #define NVIDIA_HDA_OSTRM_COH 0x4c | |
81 | #define NVIDIA_HDA_ENABLE_COHBIT 0x01 | |
82 | ||
83 | /* Defines for Intel SCH HDA snoop control */ | |
6639484d LY |
84 | #define INTEL_HDA_CGCTL 0x48 |
85 | #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) | |
9a34af4a TI |
86 | #define INTEL_SCH_HDA_DEVC 0x78 |
87 | #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) | |
88 | ||
9a34af4a TI |
89 | /* Define VIA HD Audio Device ID*/ |
90 | #define VIA_HDAC_DEVICE_ID 0x3288 | |
91 | ||
33124929 TI |
92 | /* max number of SDs */ |
93 | /* ICH, ATI and VIA have 4 playback and 4 capture */ | |
94 | #define ICH6_NUM_CAPTURE 4 | |
95 | #define ICH6_NUM_PLAYBACK 4 | |
96 | ||
97 | /* ULI has 6 playback and 5 capture */ | |
98 | #define ULI_NUM_CAPTURE 5 | |
99 | #define ULI_NUM_PLAYBACK 6 | |
100 | ||
101 | /* ATI HDMI may have up to 8 playbacks and 0 capture */ | |
102 | #define ATIHDMI_NUM_CAPTURE 0 | |
103 | #define ATIHDMI_NUM_PLAYBACK 8 | |
104 | ||
105 | /* TERA has 4 playback and 3 capture */ | |
106 | #define TERA_NUM_CAPTURE 3 | |
107 | #define TERA_NUM_PLAYBACK 4 | |
108 | ||
1da177e4 | 109 | |
5aba4f8e TI |
110 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; |
111 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; | |
a67ff6a5 | 112 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; |
5aba4f8e | 113 | static char *model[SNDRV_CARDS]; |
1dac6695 | 114 | static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
5c0d7bc1 | 115 | static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
5aba4f8e | 116 | static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
d4d9cd03 | 117 | static int probe_only[SNDRV_CARDS]; |
26a6cb6c | 118 | static int jackpoll_ms[SNDRV_CARDS]; |
41438f13 | 119 | static int single_cmd = -1; |
71623855 | 120 | static int enable_msi = -1; |
4ea6fbc8 TI |
121 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
122 | static char *patch[SNDRV_CARDS]; | |
123 | #endif | |
2dca0bba | 124 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
0920c9b4 | 125 | static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = |
2dca0bba JK |
126 | CONFIG_SND_HDA_INPUT_BEEP_MODE}; |
127 | #endif | |
7fba6aea | 128 | static bool dmic_detect = 1; |
1da177e4 | 129 | |
5aba4f8e | 130 | module_param_array(index, int, NULL, 0444); |
1da177e4 | 131 | MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); |
5aba4f8e | 132 | module_param_array(id, charp, NULL, 0444); |
1da177e4 | 133 | MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); |
5aba4f8e TI |
134 | module_param_array(enable, bool, NULL, 0444); |
135 | MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); | |
136 | module_param_array(model, charp, NULL, 0444); | |
1da177e4 | 137 | MODULE_PARM_DESC(model, "Use the given board model."); |
5aba4f8e | 138 | module_param_array(position_fix, int, NULL, 0444); |
4cb36310 | 139 | MODULE_PARM_DESC(position_fix, "DMA pointer read method." |
c02f77d3 | 140 | "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); |
555e219f TI |
141 | module_param_array(bdl_pos_adj, int, NULL, 0644); |
142 | MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); | |
5aba4f8e | 143 | module_param_array(probe_mask, int, NULL, 0444); |
606ad75f | 144 | MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); |
079e683e | 145 | module_param_array(probe_only, int, NULL, 0444); |
d4d9cd03 | 146 | MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); |
26a6cb6c DH |
147 | module_param_array(jackpoll_ms, int, NULL, 0444); |
148 | MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); | |
41438f13 | 149 | module_param(single_cmd, bint, 0444); |
d01ce99f TI |
150 | MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " |
151 | "(for debugging only)."); | |
ac9ef6cf | 152 | module_param(enable_msi, bint, 0444); |
134a11f0 | 153 | MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); |
4ea6fbc8 TI |
154 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
155 | module_param_array(patch, charp, NULL, 0444); | |
156 | MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); | |
157 | #endif | |
2dca0bba | 158 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
0920c9b4 | 159 | module_param_array(beep_mode, bool, NULL, 0444); |
2dca0bba | 160 | MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " |
0920c9b4 | 161 | "(0=off, 1=on) (default=1)."); |
2dca0bba | 162 | #endif |
7fba6aea TI |
163 | module_param(dmic_detect, bool, 0444); |
164 | MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " | |
165 | "(0=off, 1=on) (default=1); " | |
166 | "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); | |
606ad75f | 167 | |
83012a7c | 168 | #ifdef CONFIG_PM |
65fcd41d | 169 | static int param_set_xint(const char *val, const struct kernel_param *kp); |
9c27847d | 170 | static const struct kernel_param_ops param_ops_xint = { |
65fcd41d TI |
171 | .set = param_set_xint, |
172 | .get = param_get_int, | |
173 | }; | |
174 | #define param_check_xint param_check_int | |
175 | ||
fee2fba3 | 176 | static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; |
65fcd41d | 177 | module_param(power_save, xint, 0644); |
fee2fba3 TI |
178 | MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " |
179 | "(in second, 0 = disable)."); | |
1da177e4 | 180 | |
40088dc4 TI |
181 | static bool pm_blacklist = true; |
182 | module_param(pm_blacklist, bool, 0644); | |
6317e5eb | 183 | MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); |
40088dc4 | 184 | |
dee1b66c TI |
185 | /* reset the HD-audio controller in power save mode. |
186 | * this may give more power-saving, but will take longer time to | |
187 | * wake up. | |
188 | */ | |
8fc24426 TI |
189 | static bool power_save_controller = 1; |
190 | module_param(power_save_controller, bool, 0644); | |
dee1b66c | 191 | MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); |
e62a42ae | 192 | #else |
bb573928 | 193 | #define power_save 0 |
83012a7c | 194 | #endif /* CONFIG_PM */ |
dee1b66c | 195 | |
7bfe059e TI |
196 | static int align_buffer_size = -1; |
197 | module_param(align_buffer_size, bint, 0644); | |
2ae66c26 PLB |
198 | MODULE_PARM_DESC(align_buffer_size, |
199 | "Force buffer and period sizes to be multiple of 128 bytes."); | |
200 | ||
27fe48d9 | 201 | #ifdef CONFIG_X86 |
7c732015 TI |
202 | static int hda_snoop = -1; |
203 | module_param_named(snoop, hda_snoop, bint, 0444); | |
27fe48d9 | 204 | MODULE_PARM_DESC(snoop, "Enable/disable snooping"); |
27fe48d9 TI |
205 | #else |
206 | #define hda_snoop true | |
27fe48d9 TI |
207 | #endif |
208 | ||
209 | ||
1da177e4 LT |
210 | MODULE_LICENSE("GPL"); |
211 | MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," | |
212 | "{Intel, ICH6M}," | |
2f1b3818 | 213 | "{Intel, ICH7}," |
f5d40b30 | 214 | "{Intel, ESB2}," |
d2981393 | 215 | "{Intel, ICH8}," |
f9cc8a8b | 216 | "{Intel, ICH9}," |
c34f5a04 | 217 | "{Intel, ICH10}," |
b29c2360 | 218 | "{Intel, PCH}," |
d2f2fcd2 | 219 | "{Intel, CPT}," |
d2edeb7c | 220 | "{Intel, PPT}," |
8bc039a1 | 221 | "{Intel, LPT}," |
144dad99 | 222 | "{Intel, LPT_LP}," |
4eeca499 | 223 | "{Intel, WPT_LP}," |
c8b00fd2 | 224 | "{Intel, SPT}," |
b4565913 | 225 | "{Intel, SPT_LP}," |
e926f2c8 | 226 | "{Intel, HPT}," |
cea310e8 | 227 | "{Intel, PBG}," |
4979bca9 | 228 | "{Intel, SCH}," |
fc20a562 | 229 | "{ATI, SB450}," |
89be83f8 | 230 | "{ATI, SB600}," |
778b6e1b | 231 | "{ATI, RS600}," |
5b15c95f | 232 | "{ATI, RS690}," |
e6db1119 WL |
233 | "{ATI, RS780}," |
234 | "{ATI, R600}," | |
2797f724 HRK |
235 | "{ATI, RV630}," |
236 | "{ATI, RV610}," | |
27da1834 WL |
237 | "{ATI, RV670}," |
238 | "{ATI, RV635}," | |
239 | "{ATI, RV620}," | |
240 | "{ATI, RV770}," | |
fc20a562 | 241 | "{VIA, VT8251}," |
47672310 | 242 | "{VIA, VT8237A}," |
07e4ca50 TI |
243 | "{SiS, SIS966}," |
244 | "{ULI, M5461}}"); | |
1da177e4 LT |
245 | MODULE_DESCRIPTION("Intel HDA driver"); |
246 | ||
a82d51ed | 247 | #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) |
f8f1becf | 248 | #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) |
a82d51ed TI |
249 | #define SUPPORT_VGA_SWITCHEROO |
250 | #endif | |
251 | #endif | |
252 | ||
253 | ||
1da177e4 | 254 | /* |
1da177e4 | 255 | */ |
1da177e4 | 256 | |
07e4ca50 TI |
257 | /* driver types */ |
258 | enum { | |
259 | AZX_DRIVER_ICH, | |
32679f95 | 260 | AZX_DRIVER_PCH, |
4979bca9 | 261 | AZX_DRIVER_SCH, |
a4b4793f | 262 | AZX_DRIVER_SKL, |
fab1285a | 263 | AZX_DRIVER_HDMI, |
07e4ca50 | 264 | AZX_DRIVER_ATI, |
778b6e1b | 265 | AZX_DRIVER_ATIHDMI, |
1815b34a | 266 | AZX_DRIVER_ATIHDMI_NS, |
07e4ca50 TI |
267 | AZX_DRIVER_VIA, |
268 | AZX_DRIVER_SIS, | |
269 | AZX_DRIVER_ULI, | |
da3fca21 | 270 | AZX_DRIVER_NVIDIA, |
f269002e | 271 | AZX_DRIVER_TERA, |
14d34f16 | 272 | AZX_DRIVER_CTX, |
5ae763b1 | 273 | AZX_DRIVER_CTHDA, |
c563f473 | 274 | AZX_DRIVER_CMEDIA, |
b6fcab14 | 275 | AZX_DRIVER_ZHAOXIN, |
c4da29ca | 276 | AZX_DRIVER_GENERIC, |
2f5983f2 | 277 | AZX_NUM_DRIVERS, /* keep this as last entry */ |
07e4ca50 TI |
278 | }; |
279 | ||
37e661ee TI |
280 | #define azx_get_snoop_type(chip) \ |
281 | (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) | |
282 | #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) | |
283 | ||
b42b4afb TI |
284 | /* quirks for old Intel chipsets */ |
285 | #define AZX_DCAPS_INTEL_ICH \ | |
f34a4c9d | 286 | (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) |
b42b4afb | 287 | |
2ea3c6a2 | 288 | /* quirks for Intel PCH */ |
6603249d | 289 | #define AZX_DCAPS_INTEL_PCH_BASE \ |
103884a3 | 290 | (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ |
f34a4c9d | 291 | AZX_DCAPS_SNOOP_TYPE(SCH)) |
d7dab4db | 292 | |
dba9b7b6 | 293 | /* PCH up to IVB; no runtime PM; bind with i915 gfx */ |
6603249d | 294 | #define AZX_DCAPS_INTEL_PCH_NOPM \ |
dba9b7b6 | 295 | (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) |
6603249d | 296 | |
55913110 | 297 | /* PCH for HSW/BDW; with runtime PM */ |
dba9b7b6 | 298 | /* no i915 binding for this as HSW/BDW has another controller for HDMI */ |
d7dab4db | 299 | #define AZX_DCAPS_INTEL_PCH \ |
f5dac54d | 300 | (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) |
9477c58e | 301 | |
6603249d | 302 | /* HSW HDMI */ |
33499a15 | 303 | #define AZX_DCAPS_INTEL_HASWELL \ |
103884a3 | 304 | (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ |
dba9b7b6 | 305 | AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ |
f34a4c9d | 306 | AZX_DCAPS_SNOOP_TYPE(SCH)) |
33499a15 | 307 | |
54a0405d LY |
308 | /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ |
309 | #define AZX_DCAPS_INTEL_BROADWELL \ | |
103884a3 | 310 | (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ |
dba9b7b6 | 311 | AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ |
f34a4c9d | 312 | AZX_DCAPS_SNOOP_TYPE(SCH)) |
54a0405d | 313 | |
40cc2392 | 314 | #define AZX_DCAPS_INTEL_BAYTRAIL \ |
e454ff8e | 315 | (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) |
40cc2392 | 316 | |
2d846c74 | 317 | #define AZX_DCAPS_INTEL_BRASWELL \ |
dba9b7b6 | 318 | (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ |
e454ff8e | 319 | AZX_DCAPS_I915_COMPONENT) |
2d846c74 | 320 | |
d6795827 | 321 | #define AZX_DCAPS_INTEL_SKYLAKE \ |
dba9b7b6 | 322 | (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ |
e454ff8e | 323 | AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) |
d6795827 | 324 | |
2756d914 | 325 | #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE |
c87693da | 326 | |
9477c58e TI |
327 | /* quirks for ATI SB / AMD Hudson */ |
328 | #define AZX_DCAPS_PRESET_ATI_SB \ | |
f34a4c9d | 329 | (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ |
37e661ee | 330 | AZX_DCAPS_SNOOP_TYPE(ATI)) |
9477c58e TI |
331 | |
332 | /* quirks for ATI/AMD HDMI */ | |
333 | #define AZX_DCAPS_PRESET_ATI_HDMI \ | |
f34a4c9d | 334 | (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ |
db79afa1 | 335 | AZX_DCAPS_NO_MSI64) |
9477c58e | 336 | |
37e661ee TI |
337 | /* quirks for ATI HDMI with snoop off */ |
338 | #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ | |
339 | (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) | |
340 | ||
c02f77d3 TI |
341 | /* quirks for AMD SB */ |
342 | #define AZX_DCAPS_PRESET_AMD_SB \ | |
f34a4c9d | 343 | (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ |
c02f77d3 TI |
344 | AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME) |
345 | ||
9477c58e TI |
346 | /* quirks for Nvidia */ |
347 | #define AZX_DCAPS_PRESET_NVIDIA \ | |
3ab7511e | 348 | (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ |
37e661ee | 349 | AZX_DCAPS_SNOOP_TYPE(NVIDIA)) |
9477c58e | 350 | |
5ae763b1 | 351 | #define AZX_DCAPS_PRESET_CTHDA \ |
37e661ee | 352 | (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ |
cadd16ea | 353 | AZX_DCAPS_NO_64BIT |\ |
37e661ee | 354 | AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) |
5ae763b1 | 355 | |
a82d51ed | 356 | /* |
2b760d88 | 357 | * vga_switcheroo support |
a82d51ed TI |
358 | */ |
359 | #ifdef SUPPORT_VGA_SWITCHEROO | |
5cb543db | 360 | #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) |
dd23e1d5 | 361 | #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) |
5cb543db TI |
362 | #else |
363 | #define use_vga_switcheroo(chip) 0 | |
37a3a98e | 364 | #define needs_eld_notify_link(chip) false |
5cb543db TI |
365 | #endif |
366 | ||
03b135ce LY |
367 | #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ |
368 | ((pci)->device == 0x0c0c) || \ | |
369 | ((pci)->device == 0x0d0c) || \ | |
1bee263d KV |
370 | ((pci)->device == 0x160c) || \ |
371 | ((pci)->device == 0x490d)) | |
03b135ce | 372 | |
7e31a015 | 373 | #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) |
7c23b7c1 | 374 | |
bf82326f | 375 | static const char * const driver_short_names[] = { |
07e4ca50 | 376 | [AZX_DRIVER_ICH] = "HDA Intel", |
32679f95 | 377 | [AZX_DRIVER_PCH] = "HDA Intel PCH", |
4979bca9 | 378 | [AZX_DRIVER_SCH] = "HDA Intel MID", |
a4b4793f | 379 | [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ |
fab1285a | 380 | [AZX_DRIVER_HDMI] = "HDA Intel HDMI", |
07e4ca50 | 381 | [AZX_DRIVER_ATI] = "HDA ATI SB", |
778b6e1b | 382 | [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", |
1815b34a | 383 | [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", |
07e4ca50 TI |
384 | [AZX_DRIVER_VIA] = "HDA VIA VT82xx", |
385 | [AZX_DRIVER_SIS] = "HDA SIS966", | |
da3fca21 V |
386 | [AZX_DRIVER_ULI] = "HDA ULI M5461", |
387 | [AZX_DRIVER_NVIDIA] = "HDA NVidia", | |
f269002e | 388 | [AZX_DRIVER_TERA] = "HDA Teradici", |
14d34f16 | 389 | [AZX_DRIVER_CTX] = "HDA Creative", |
5ae763b1 | 390 | [AZX_DRIVER_CTHDA] = "HDA Creative", |
c563f473 | 391 | [AZX_DRIVER_CMEDIA] = "HDA C-Media", |
b6fcab14 | 392 | [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", |
c4da29ca | 393 | [AZX_DRIVER_GENERIC] = "HD-Audio Generic", |
07e4ca50 TI |
394 | }; |
395 | ||
68e7fffc | 396 | static int azx_acquire_irq(struct azx *chip, int do_disconnect); |
37a3a98e | 397 | static void set_default_power_save(struct azx *chip); |
111d3af5 | 398 | |
cb53c626 TI |
399 | /* |
400 | * initialize the PCI registers | |
401 | */ | |
402 | /* update bits in a PCI register byte */ | |
403 | static void update_pci_byte(struct pci_dev *pci, unsigned int reg, | |
404 | unsigned char mask, unsigned char val) | |
405 | { | |
406 | unsigned char data; | |
407 | ||
408 | pci_read_config_byte(pci, reg, &data); | |
409 | data &= ~mask; | |
410 | data |= (val & mask); | |
411 | pci_write_config_byte(pci, reg, data); | |
412 | } | |
413 | ||
414 | static void azx_init_pci(struct azx *chip) | |
415 | { | |
37e661ee TI |
416 | int snoop_type = azx_get_snoop_type(chip); |
417 | ||
cb53c626 TI |
418 | /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) |
419 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | |
420 | * Ensuring these bits are 0 clears playback static on some HD Audio | |
a09e89f6 AL |
421 | * codecs. |
422 | * The PCI register TCSEL is defined in the Intel manuals. | |
cb53c626 | 423 | */ |
46f2cc80 | 424 | if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { |
4e76a883 | 425 | dev_dbg(chip->card->dev, "Clearing TCSEL\n"); |
fb1d8ac2 | 426 | update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); |
9477c58e | 427 | } |
cb53c626 | 428 | |
9477c58e TI |
429 | /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, |
430 | * we need to enable snoop. | |
431 | */ | |
37e661ee | 432 | if (snoop_type == AZX_SNOOP_TYPE_ATI) { |
4e76a883 TI |
433 | dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", |
434 | azx_snoop(chip)); | |
cb53c626 | 435 | update_pci_byte(chip->pci, |
27fe48d9 TI |
436 | ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, |
437 | azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); | |
9477c58e TI |
438 | } |
439 | ||
440 | /* For NVIDIA HDA, enable snoop */ | |
37e661ee | 441 | if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { |
4e76a883 TI |
442 | dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", |
443 | azx_snoop(chip)); | |
cb53c626 TI |
444 | update_pci_byte(chip->pci, |
445 | NVIDIA_HDA_TRANSREG_ADDR, | |
446 | 0x0f, NVIDIA_HDA_ENABLE_COHBITS); | |
320dcc30 PC |
447 | update_pci_byte(chip->pci, |
448 | NVIDIA_HDA_ISTRM_COH, | |
449 | 0x01, NVIDIA_HDA_ENABLE_COHBIT); | |
450 | update_pci_byte(chip->pci, | |
451 | NVIDIA_HDA_OSTRM_COH, | |
452 | 0x01, NVIDIA_HDA_ENABLE_COHBIT); | |
9477c58e TI |
453 | } |
454 | ||
455 | /* Enable SCH/PCH snoop if needed */ | |
37e661ee | 456 | if (snoop_type == AZX_SNOOP_TYPE_SCH) { |
27fe48d9 | 457 | unsigned short snoop; |
90a5ad52 | 458 | pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); |
27fe48d9 TI |
459 | if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || |
460 | (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { | |
461 | snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; | |
462 | if (!azx_snoop(chip)) | |
463 | snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; | |
464 | pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); | |
90a5ad52 TI |
465 | pci_read_config_word(chip->pci, |
466 | INTEL_SCH_HDA_DEVC, &snoop); | |
90a5ad52 | 467 | } |
4e76a883 TI |
468 | dev_dbg(chip->card->dev, "SCH snoop: %s\n", |
469 | (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? | |
470 | "Disabled" : "Enabled"); | |
da3fca21 | 471 | } |
1da177e4 LT |
472 | } |
473 | ||
7c23b7c1 LH |
474 | /* |
475 | * In BXT-P A0, HD-Audio DMA requests is later than expected, | |
476 | * and makes an audio stream sensitive to system latencies when | |
477 | * 24/32 bits are playing. | |
478 | * Adjusting threshold of DMA fifo to force the DMA request | |
479 | * sooner to improve latency tolerance at the expense of power. | |
480 | */ | |
481 | static void bxt_reduce_dma_latency(struct azx *chip) | |
482 | { | |
483 | u32 val; | |
484 | ||
70eafad8 | 485 | val = azx_readl(chip, VS_EM4L); |
7c23b7c1 | 486 | val &= (0x3 << 20); |
70eafad8 | 487 | azx_writel(chip, VS_EM4L, val); |
7c23b7c1 LH |
488 | } |
489 | ||
1f9d3d98 LY |
490 | /* |
491 | * ML_LCAP bits: | |
492 | * bit 0: 6 MHz Supported | |
493 | * bit 1: 12 MHz Supported | |
494 | * bit 2: 24 MHz Supported | |
495 | * bit 3: 48 MHz Supported | |
496 | * bit 4: 96 MHz Supported | |
497 | * bit 5: 192 MHz Supported | |
498 | */ | |
499 | static int intel_get_lctl_scf(struct azx *chip) | |
500 | { | |
501 | struct hdac_bus *bus = azx_bus(chip); | |
bf82326f | 502 | static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; |
1f9d3d98 LY |
503 | u32 val, t; |
504 | int i; | |
505 | ||
506 | val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); | |
507 | ||
508 | for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { | |
509 | t = preferred_bits[i]; | |
510 | if (val & (1 << t)) | |
511 | return t; | |
512 | } | |
513 | ||
514 | dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); | |
515 | return 0; | |
516 | } | |
517 | ||
518 | static int intel_ml_lctl_set_power(struct azx *chip, int state) | |
519 | { | |
520 | struct hdac_bus *bus = azx_bus(chip); | |
521 | u32 val; | |
522 | int timeout; | |
523 | ||
524 | /* | |
525 | * the codecs are sharing the first link setting by default | |
526 | * If other links are enabled for stream, they need similar fix | |
527 | */ | |
528 | val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); | |
529 | val &= ~AZX_MLCTL_SPA; | |
530 | val |= state << AZX_MLCTL_SPA_SHIFT; | |
531 | writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); | |
532 | /* wait for CPA */ | |
533 | timeout = 50; | |
534 | while (timeout) { | |
535 | if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & | |
536 | AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) | |
537 | return 0; | |
538 | timeout--; | |
539 | udelay(10); | |
540 | } | |
541 | ||
542 | return -1; | |
543 | } | |
544 | ||
545 | static void intel_init_lctl(struct azx *chip) | |
546 | { | |
547 | struct hdac_bus *bus = azx_bus(chip); | |
548 | u32 val; | |
549 | int ret; | |
550 | ||
551 | /* 0. check lctl register value is correct or not */ | |
552 | val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); | |
553 | /* if SCF is already set, let's use it */ | |
554 | if ((val & ML_LCTL_SCF_MASK) != 0) | |
555 | return; | |
556 | ||
557 | /* | |
558 | * Before operating on SPA, CPA must match SPA. | |
559 | * Any deviation may result in undefined behavior. | |
560 | */ | |
561 | if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != | |
562 | ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) | |
563 | return; | |
564 | ||
565 | /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ | |
566 | ret = intel_ml_lctl_set_power(chip, 0); | |
567 | udelay(100); | |
568 | if (ret) | |
569 | goto set_spa; | |
570 | ||
571 | /* 2. update SCF to select a properly audio clock*/ | |
572 | val &= ~ML_LCTL_SCF_MASK; | |
573 | val |= intel_get_lctl_scf(chip); | |
574 | writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); | |
575 | ||
576 | set_spa: | |
577 | /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ | |
578 | intel_ml_lctl_set_power(chip, 1); | |
579 | udelay(100); | |
580 | } | |
581 | ||
0a673521 LH |
582 | static void hda_intel_init_chip(struct azx *chip, bool full_reset) |
583 | { | |
98d8fc6c | 584 | struct hdac_bus *bus = azx_bus(chip); |
7c23b7c1 | 585 | struct pci_dev *pci = chip->pci; |
6639484d | 586 | u32 val; |
0a673521 | 587 | |
e454ff8e | 588 | snd_hdac_set_codec_wakeup(bus, true); |
a4b4793f | 589 | if (chip->driver_type == AZX_DRIVER_SKL) { |
6639484d LY |
590 | pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); |
591 | val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; | |
592 | pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); | |
593 | } | |
0a673521 | 594 | azx_init_chip(chip, full_reset); |
a4b4793f | 595 | if (chip->driver_type == AZX_DRIVER_SKL) { |
6639484d LY |
596 | pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); |
597 | val = val | INTEL_HDA_CGCTL_MISCBDCGE; | |
598 | pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); | |
599 | } | |
e454ff8e TI |
600 | |
601 | snd_hdac_set_codec_wakeup(bus, false); | |
7c23b7c1 LH |
602 | |
603 | /* reduce dma latency to avoid noise */ | |
7e31a015 | 604 | if (IS_BXT(pci)) |
7c23b7c1 | 605 | bxt_reduce_dma_latency(chip); |
1f9d3d98 LY |
606 | |
607 | if (bus->mlcap != NULL) | |
608 | intel_init_lctl(chip); | |
0a673521 LH |
609 | } |
610 | ||
b6050ef6 TI |
611 | /* calculate runtime delay from LPIB */ |
612 | static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, | |
613 | unsigned int pos) | |
614 | { | |
7833c3f8 | 615 | struct snd_pcm_substream *substream = azx_dev->core.substream; |
b6050ef6 TI |
616 | int stream = substream->stream; |
617 | unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); | |
618 | int delay; | |
619 | ||
620 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) | |
621 | delay = pos - lpib_pos; | |
622 | else | |
623 | delay = lpib_pos - pos; | |
624 | if (delay < 0) { | |
7833c3f8 | 625 | if (delay >= azx_dev->core.delay_negative_threshold) |
b6050ef6 TI |
626 | delay = 0; |
627 | else | |
7833c3f8 | 628 | delay += azx_dev->core.bufsize; |
b6050ef6 TI |
629 | } |
630 | ||
7833c3f8 | 631 | if (delay >= azx_dev->core.period_bytes) { |
b6050ef6 TI |
632 | dev_info(chip->card->dev, |
633 | "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", | |
7833c3f8 | 634 | delay, azx_dev->core.period_bytes); |
b6050ef6 TI |
635 | delay = 0; |
636 | chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; | |
637 | chip->get_delay[stream] = NULL; | |
638 | } | |
639 | ||
640 | return bytes_to_frames(substream->runtime, delay); | |
641 | } | |
642 | ||
9ad593f6 TI |
643 | static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); |
644 | ||
7ca954a8 DR |
645 | /* called from IRQ */ |
646 | static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) | |
647 | { | |
9a34af4a | 648 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
7ca954a8 DR |
649 | int ok; |
650 | ||
651 | ok = azx_position_ok(chip, azx_dev); | |
652 | if (ok == 1) { | |
653 | azx_dev->irq_pending = 0; | |
654 | return ok; | |
2f35c630 | 655 | } else if (ok == 0) { |
7ca954a8 DR |
656 | /* bogus IRQ, process it later */ |
657 | azx_dev->irq_pending = 1; | |
2f35c630 | 658 | schedule_work(&hda->irq_pending_work); |
7ca954a8 DR |
659 | } |
660 | return 0; | |
661 | } | |
662 | ||
029d92c2 TI |
663 | #define display_power(chip, enable) \ |
664 | snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) | |
17eccb27 | 665 | |
9ad593f6 TI |
666 | /* |
667 | * Check whether the current DMA position is acceptable for updating | |
668 | * periods. Returns non-zero if it's OK. | |
669 | * | |
670 | * Many HD-audio controllers appear pretty inaccurate about | |
671 | * the update-IRQ timing. The IRQ is issued before actually the | |
672 | * data is processed. So, we need to process it afterwords in a | |
673 | * workqueue. | |
674 | */ | |
675 | static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) | |
676 | { | |
7833c3f8 | 677 | struct snd_pcm_substream *substream = azx_dev->core.substream; |
b6050ef6 | 678 | int stream = substream->stream; |
e5463720 | 679 | u32 wallclk; |
9ad593f6 TI |
680 | unsigned int pos; |
681 | ||
7833c3f8 TI |
682 | wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; |
683 | if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) | |
fa00e046 | 684 | return -1; /* bogus (too early) interrupt */ |
fa00e046 | 685 | |
b6050ef6 TI |
686 | if (chip->get_position[stream]) |
687 | pos = chip->get_position[stream](chip, azx_dev); | |
688 | else { /* use the position buffer as default */ | |
689 | pos = azx_get_pos_posbuf(chip, azx_dev); | |
690 | if (!pos || pos == (u32)-1) { | |
691 | dev_info(chip->card->dev, | |
692 | "Invalid position buffer, using LPIB read method instead.\n"); | |
693 | chip->get_position[stream] = azx_get_pos_lpib; | |
ccc98865 TI |
694 | if (chip->get_position[0] == azx_get_pos_lpib && |
695 | chip->get_position[1] == azx_get_pos_lpib) | |
696 | azx_bus(chip)->use_posbuf = false; | |
b6050ef6 TI |
697 | pos = azx_get_pos_lpib(chip, azx_dev); |
698 | chip->get_delay[stream] = NULL; | |
699 | } else { | |
700 | chip->get_position[stream] = azx_get_pos_posbuf; | |
701 | if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) | |
702 | chip->get_delay[stream] = azx_get_delay_from_lpib; | |
703 | } | |
704 | } | |
705 | ||
7833c3f8 | 706 | if (pos >= azx_dev->core.bufsize) |
b6050ef6 | 707 | pos = 0; |
9ad593f6 | 708 | |
7833c3f8 | 709 | if (WARN_ONCE(!azx_dev->core.period_bytes, |
d6d8bf54 | 710 | "hda-intel: zero azx_dev->period_bytes")) |
f48f606d | 711 | return -1; /* this shouldn't happen! */ |
7833c3f8 TI |
712 | if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && |
713 | pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) | |
f48f606d | 714 | /* NG - it's below the first next period boundary */ |
4f0189be | 715 | return chip->bdl_pos_adj ? 0 : -1; |
7833c3f8 | 716 | azx_dev->core.start_wallclk += wallclk; |
9ad593f6 TI |
717 | return 1; /* OK, it's fine */ |
718 | } | |
719 | ||
720 | /* | |
721 | * The work for pending PCM period updates. | |
722 | */ | |
723 | static void azx_irq_pending_work(struct work_struct *work) | |
724 | { | |
9a34af4a TI |
725 | struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); |
726 | struct azx *chip = &hda->chip; | |
7833c3f8 TI |
727 | struct hdac_bus *bus = azx_bus(chip); |
728 | struct hdac_stream *s; | |
729 | int pending, ok; | |
9ad593f6 | 730 | |
9a34af4a | 731 | if (!hda->irq_pending_warned) { |
4e76a883 TI |
732 | dev_info(chip->card->dev, |
733 | "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", | |
734 | chip->card->number); | |
9a34af4a | 735 | hda->irq_pending_warned = 1; |
a6a950a8 TI |
736 | } |
737 | ||
9ad593f6 TI |
738 | for (;;) { |
739 | pending = 0; | |
a41d1224 | 740 | spin_lock_irq(&bus->reg_lock); |
7833c3f8 TI |
741 | list_for_each_entry(s, &bus->stream_list, list) { |
742 | struct azx_dev *azx_dev = stream_to_azx_dev(s); | |
9ad593f6 | 743 | if (!azx_dev->irq_pending || |
7833c3f8 TI |
744 | !s->substream || |
745 | !s->running) | |
9ad593f6 | 746 | continue; |
e5463720 JK |
747 | ok = azx_position_ok(chip, azx_dev); |
748 | if (ok > 0) { | |
9ad593f6 | 749 | azx_dev->irq_pending = 0; |
a41d1224 | 750 | spin_unlock(&bus->reg_lock); |
7833c3f8 | 751 | snd_pcm_period_elapsed(s->substream); |
a41d1224 | 752 | spin_lock(&bus->reg_lock); |
e5463720 JK |
753 | } else if (ok < 0) { |
754 | pending = 0; /* too early */ | |
9ad593f6 TI |
755 | } else |
756 | pending++; | |
757 | } | |
a41d1224 | 758 | spin_unlock_irq(&bus->reg_lock); |
9ad593f6 TI |
759 | if (!pending) |
760 | return; | |
08af495f | 761 | msleep(1); |
9ad593f6 TI |
762 | } |
763 | } | |
764 | ||
765 | /* clear irq_pending flags and assure no on-going workq */ | |
766 | static void azx_clear_irq_pending(struct azx *chip) | |
767 | { | |
7833c3f8 TI |
768 | struct hdac_bus *bus = azx_bus(chip); |
769 | struct hdac_stream *s; | |
9ad593f6 | 770 | |
a41d1224 | 771 | spin_lock_irq(&bus->reg_lock); |
7833c3f8 TI |
772 | list_for_each_entry(s, &bus->stream_list, list) { |
773 | struct azx_dev *azx_dev = stream_to_azx_dev(s); | |
774 | azx_dev->irq_pending = 0; | |
775 | } | |
a41d1224 | 776 | spin_unlock_irq(&bus->reg_lock); |
1da177e4 LT |
777 | } |
778 | ||
68e7fffc TI |
779 | static int azx_acquire_irq(struct azx *chip, int do_disconnect) |
780 | { | |
a41d1224 TI |
781 | struct hdac_bus *bus = azx_bus(chip); |
782 | ||
437a5a46 TI |
783 | if (request_irq(chip->pci->irq, azx_interrupt, |
784 | chip->msi ? 0 : IRQF_SHARED, | |
de65360b | 785 | chip->card->irq_descr, chip)) { |
4e76a883 TI |
786 | dev_err(chip->card->dev, |
787 | "unable to grab IRQ %d, disabling device\n", | |
788 | chip->pci->irq); | |
68e7fffc TI |
789 | if (do_disconnect) |
790 | snd_card_disconnect(chip->card); | |
791 | return -1; | |
792 | } | |
a41d1224 | 793 | bus->irq = chip->pci->irq; |
f36da940 | 794 | chip->card->sync_irq = bus->irq; |
69e13418 | 795 | pci_intx(chip->pci, !chip->msi); |
68e7fffc TI |
796 | return 0; |
797 | } | |
798 | ||
b6050ef6 TI |
799 | /* get the current DMA position with correction on VIA chips */ |
800 | static unsigned int azx_via_get_position(struct azx *chip, | |
801 | struct azx_dev *azx_dev) | |
802 | { | |
803 | unsigned int link_pos, mini_pos, bound_pos; | |
804 | unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; | |
805 | unsigned int fifo_size; | |
806 | ||
1604eeee | 807 | link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); |
7833c3f8 | 808 | if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
b6050ef6 TI |
809 | /* Playback, no problem using link position */ |
810 | return link_pos; | |
811 | } | |
812 | ||
813 | /* Capture */ | |
814 | /* For new chipset, | |
815 | * use mod to get the DMA position just like old chipset | |
816 | */ | |
7833c3f8 TI |
817 | mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); |
818 | mod_dma_pos %= azx_dev->core.period_bytes; | |
b6050ef6 | 819 | |
7da20788 | 820 | fifo_size = azx_stream(azx_dev)->fifo_size - 1; |
b6050ef6 TI |
821 | |
822 | if (azx_dev->insufficient) { | |
823 | /* Link position never gather than FIFO size */ | |
824 | if (link_pos <= fifo_size) | |
825 | return 0; | |
826 | ||
827 | azx_dev->insufficient = 0; | |
828 | } | |
829 | ||
830 | if (link_pos <= fifo_size) | |
7833c3f8 | 831 | mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; |
b6050ef6 TI |
832 | else |
833 | mini_pos = link_pos - fifo_size; | |
834 | ||
835 | /* Find nearest previous boudary */ | |
7833c3f8 TI |
836 | mod_mini_pos = mini_pos % azx_dev->core.period_bytes; |
837 | mod_link_pos = link_pos % azx_dev->core.period_bytes; | |
b6050ef6 TI |
838 | if (mod_link_pos >= fifo_size) |
839 | bound_pos = link_pos - mod_link_pos; | |
840 | else if (mod_dma_pos >= mod_mini_pos) | |
841 | bound_pos = mini_pos - mod_mini_pos; | |
842 | else { | |
7833c3f8 TI |
843 | bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; |
844 | if (bound_pos >= azx_dev->core.bufsize) | |
b6050ef6 TI |
845 | bound_pos = 0; |
846 | } | |
847 | ||
848 | /* Calculate real DMA position we want */ | |
849 | return bound_pos + mod_dma_pos; | |
850 | } | |
851 | ||
c02f77d3 TI |
852 | #define AMD_FIFO_SIZE 32 |
853 | ||
854 | /* get the current DMA position with FIFO size correction */ | |
855 | static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) | |
856 | { | |
857 | struct snd_pcm_substream *substream = azx_dev->core.substream; | |
858 | struct snd_pcm_runtime *runtime = substream->runtime; | |
859 | unsigned int pos, delay; | |
860 | ||
861 | pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); | |
862 | if (!runtime) | |
863 | return pos; | |
864 | ||
865 | runtime->delay = AMD_FIFO_SIZE; | |
866 | delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); | |
867 | if (azx_dev->insufficient) { | |
868 | if (pos < delay) { | |
869 | delay = pos; | |
870 | runtime->delay = bytes_to_frames(runtime, pos); | |
871 | } else { | |
872 | azx_dev->insufficient = 0; | |
873 | } | |
874 | } | |
875 | ||
876 | /* correct the DMA position for capture stream */ | |
877 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { | |
878 | if (pos < delay) | |
879 | pos += azx_dev->core.bufsize; | |
880 | pos -= delay; | |
881 | } | |
882 | ||
883 | return pos; | |
884 | } | |
885 | ||
886 | static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, | |
887 | unsigned int pos) | |
888 | { | |
889 | struct snd_pcm_substream *substream = azx_dev->core.substream; | |
890 | ||
891 | /* just read back the calculated value in the above */ | |
892 | return substream->runtime->delay; | |
893 | } | |
894 | ||
f87e7f25 TI |
895 | static unsigned int azx_skl_get_dpib_pos(struct azx *chip, |
896 | struct azx_dev *azx_dev) | |
897 | { | |
898 | return _snd_hdac_chip_readl(azx_bus(chip), | |
899 | AZX_REG_VS_SDXDPIB_XBASE + | |
900 | (AZX_REG_VS_SDXDPIB_XINTERVAL * | |
901 | azx_dev->core.index)); | |
902 | } | |
903 | ||
904 | /* get the current DMA position with correction on SKL+ chips */ | |
905 | static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev) | |
906 | { | |
907 | /* DPIB register gives a more accurate position for playback */ | |
908 | if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
909 | return azx_skl_get_dpib_pos(chip, azx_dev); | |
910 | ||
911 | /* For capture, we need to read posbuf, but it requires a delay | |
912 | * for the possible boundary overlap; the read of DPIB fetches the | |
913 | * actual posbuf | |
914 | */ | |
915 | udelay(20); | |
916 | azx_skl_get_dpib_pos(chip, azx_dev); | |
917 | return azx_get_pos_posbuf(chip, azx_dev); | |
918 | } | |
919 | ||
83012a7c | 920 | #ifdef CONFIG_PM |
65fcd41d TI |
921 | static DEFINE_MUTEX(card_list_lock); |
922 | static LIST_HEAD(card_list); | |
923 | ||
924 | static void azx_add_card_list(struct azx *chip) | |
925 | { | |
9a34af4a | 926 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
65fcd41d | 927 | mutex_lock(&card_list_lock); |
9a34af4a | 928 | list_add(&hda->list, &card_list); |
65fcd41d TI |
929 | mutex_unlock(&card_list_lock); |
930 | } | |
931 | ||
932 | static void azx_del_card_list(struct azx *chip) | |
933 | { | |
9a34af4a | 934 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
65fcd41d | 935 | mutex_lock(&card_list_lock); |
9a34af4a | 936 | list_del_init(&hda->list); |
65fcd41d TI |
937 | mutex_unlock(&card_list_lock); |
938 | } | |
939 | ||
940 | /* trigger power-save check at writing parameter */ | |
941 | static int param_set_xint(const char *val, const struct kernel_param *kp) | |
942 | { | |
9a34af4a | 943 | struct hda_intel *hda; |
65fcd41d | 944 | struct azx *chip; |
65fcd41d TI |
945 | int prev = power_save; |
946 | int ret = param_set_int(val, kp); | |
947 | ||
948 | if (ret || prev == power_save) | |
949 | return ret; | |
950 | ||
951 | mutex_lock(&card_list_lock); | |
9a34af4a TI |
952 | list_for_each_entry(hda, &card_list, list) { |
953 | chip = &hda->chip; | |
a41d1224 | 954 | if (!hda->probe_continued || chip->disabled) |
65fcd41d | 955 | continue; |
a41d1224 | 956 | snd_hda_set_power_save(&chip->bus, power_save * 1000); |
65fcd41d TI |
957 | } |
958 | mutex_unlock(&card_list_lock); | |
959 | return 0; | |
960 | } | |
5c0b9bec | 961 | |
5c0b9bec TI |
962 | /* |
963 | * power management | |
964 | */ | |
3baffc4a | 965 | static bool azx_is_pm_ready(struct snd_card *card) |
1da177e4 | 966 | { |
2d9772ef TI |
967 | struct azx *chip; |
968 | struct hda_intel *hda; | |
1da177e4 | 969 | |
2d9772ef | 970 | if (!card) |
3baffc4a | 971 | return false; |
2d9772ef TI |
972 | chip = card->private_data; |
973 | hda = container_of(chip, struct hda_intel, chip); | |
342e8449 | 974 | if (chip->disabled || hda->init_failed || !chip->running) |
3baffc4a TI |
975 | return false; |
976 | return true; | |
977 | } | |
978 | ||
979 | static void __azx_runtime_suspend(struct azx *chip) | |
980 | { | |
3baffc4a TI |
981 | azx_stop_chip(chip); |
982 | azx_enter_link_reset(chip); | |
983 | azx_clear_irq_pending(chip); | |
e454ff8e | 984 | display_power(chip, false); |
3baffc4a TI |
985 | } |
986 | ||
f5dac54d | 987 | static void __azx_runtime_resume(struct azx *chip) |
3baffc4a TI |
988 | { |
989 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); | |
990 | struct hdac_bus *bus = azx_bus(chip); | |
991 | struct hda_codec *codec; | |
992 | int status; | |
993 | ||
e454ff8e TI |
994 | display_power(chip, true); |
995 | if (hda->need_i915_power) | |
996 | snd_hdac_i915_set_bclk(bus); | |
3baffc4a TI |
997 | |
998 | /* Read STATESTS before controller reset */ | |
999 | status = azx_readw(chip, STATESTS); | |
1000 | ||
1001 | azx_init_pci(chip); | |
1002 | hda_intel_init_chip(chip, true); | |
1003 | ||
f5dac54d KHF |
1004 | /* Avoid codec resume if runtime resume is for system suspend */ |
1005 | if (!chip->pm_prepared) { | |
a6e7d0a4 KV |
1006 | list_for_each_codec(codec, &chip->bus) { |
1007 | if (codec->relaxed_resume) | |
1008 | continue; | |
1009 | ||
1010 | if (codec->forced_resume || (status & (1 << codec->addr))) | |
1011 | pm_request_resume(hda_codec_dev(codec)); | |
1012 | } | |
3baffc4a TI |
1013 | } |
1014 | ||
1015 | /* power down again for link-controlled chips */ | |
e454ff8e | 1016 | if (!hda->need_i915_power) |
029d92c2 | 1017 | display_power(chip, false); |
3baffc4a TI |
1018 | } |
1019 | ||
1020 | #ifdef CONFIG_PM_SLEEP | |
f5dac54d KHF |
1021 | static int azx_prepare(struct device *dev) |
1022 | { | |
1023 | struct snd_card *card = dev_get_drvdata(dev); | |
1024 | struct azx *chip; | |
1025 | ||
1026 | chip = card->private_data; | |
1027 | chip->pm_prepared = 1; | |
1028 | ||
1029 | /* HDA controller always requires different WAKEEN for runtime suspend | |
1030 | * and system suspend, so don't use direct-complete here. | |
1031 | */ | |
1032 | return 0; | |
1033 | } | |
1034 | ||
1035 | static void azx_complete(struct device *dev) | |
1036 | { | |
1037 | struct snd_card *card = dev_get_drvdata(dev); | |
1038 | struct azx *chip; | |
1039 | ||
1040 | chip = card->private_data; | |
1041 | chip->pm_prepared = 0; | |
1042 | } | |
1043 | ||
3baffc4a TI |
1044 | static int azx_suspend(struct device *dev) |
1045 | { | |
1046 | struct snd_card *card = dev_get_drvdata(dev); | |
1047 | struct azx *chip; | |
1048 | struct hdac_bus *bus; | |
1049 | ||
1050 | if (!azx_is_pm_ready(card)) | |
c5c21523 TI |
1051 | return 0; |
1052 | ||
3baffc4a | 1053 | chip = card->private_data; |
a41d1224 | 1054 | bus = azx_bus(chip); |
f5dac54d | 1055 | __azx_runtime_suspend(chip); |
a41d1224 TI |
1056 | if (bus->irq >= 0) { |
1057 | free_irq(bus->irq, chip); | |
1058 | bus->irq = -1; | |
f36da940 | 1059 | chip->card->sync_irq = -1; |
30b35399 | 1060 | } |
a07187c9 | 1061 | |
68e7fffc | 1062 | if (chip->msi) |
43001c95 | 1063 | pci_disable_msi(chip->pci); |
785d8c4b LY |
1064 | |
1065 | trace_azx_suspend(chip); | |
1da177e4 LT |
1066 | return 0; |
1067 | } | |
1068 | ||
68cb2b55 | 1069 | static int azx_resume(struct device *dev) |
1da177e4 | 1070 | { |
68cb2b55 | 1071 | struct snd_card *card = dev_get_drvdata(dev); |
2d9772ef | 1072 | struct azx *chip; |
2d9772ef | 1073 | |
3baffc4a | 1074 | if (!azx_is_pm_ready(card)) |
2d9772ef | 1075 | return 0; |
1da177e4 | 1076 | |
2d9772ef | 1077 | chip = card->private_data; |
68e7fffc | 1078 | if (chip->msi) |
3baffc4a | 1079 | if (pci_enable_msi(chip->pci) < 0) |
68e7fffc TI |
1080 | chip->msi = 0; |
1081 | if (azx_acquire_irq(chip, 1) < 0) | |
30b35399 | 1082 | return -EIO; |
c4c8dd6e | 1083 | |
f5dac54d | 1084 | __azx_runtime_resume(chip); |
785d8c4b LY |
1085 | |
1086 | trace_azx_resume(chip); | |
1da177e4 LT |
1087 | return 0; |
1088 | } | |
b8dfc462 | 1089 | |
3e6db33a XZ |
1090 | /* put codec down to D3 at hibernation for Intel SKL+; |
1091 | * otherwise BIOS may still access the codec and screw up the driver | |
1092 | */ | |
3e6db33a XZ |
1093 | static int azx_freeze_noirq(struct device *dev) |
1094 | { | |
a4b4793f TI |
1095 | struct snd_card *card = dev_get_drvdata(dev); |
1096 | struct azx *chip = card->private_data; | |
3e6db33a XZ |
1097 | struct pci_dev *pci = to_pci_dev(dev); |
1098 | ||
10db5bcc TI |
1099 | if (!azx_is_pm_ready(card)) |
1100 | return 0; | |
a4b4793f | 1101 | if (chip->driver_type == AZX_DRIVER_SKL) |
3e6db33a XZ |
1102 | pci_set_power_state(pci, PCI_D3hot); |
1103 | ||
1104 | return 0; | |
1105 | } | |
1106 | ||
1107 | static int azx_thaw_noirq(struct device *dev) | |
1108 | { | |
a4b4793f TI |
1109 | struct snd_card *card = dev_get_drvdata(dev); |
1110 | struct azx *chip = card->private_data; | |
3e6db33a XZ |
1111 | struct pci_dev *pci = to_pci_dev(dev); |
1112 | ||
10db5bcc TI |
1113 | if (!azx_is_pm_ready(card)) |
1114 | return 0; | |
a4b4793f | 1115 | if (chip->driver_type == AZX_DRIVER_SKL) |
3e6db33a XZ |
1116 | pci_set_power_state(pci, PCI_D0); |
1117 | ||
1118 | return 0; | |
1119 | } | |
1120 | #endif /* CONFIG_PM_SLEEP */ | |
1121 | ||
b8dfc462 ML |
1122 | static int azx_runtime_suspend(struct device *dev) |
1123 | { | |
1124 | struct snd_card *card = dev_get_drvdata(dev); | |
2d9772ef | 1125 | struct azx *chip; |
b8dfc462 | 1126 | |
3baffc4a | 1127 | if (!azx_is_pm_ready(card)) |
2d9772ef | 1128 | return 0; |
2d9772ef | 1129 | chip = card->private_data; |
246efa4a | 1130 | |
7d4f606c | 1131 | /* enable controller wake up event */ |
f5dac54d | 1132 | azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); |
7d4f606c | 1133 | |
3baffc4a | 1134 | __azx_runtime_suspend(chip); |
785d8c4b | 1135 | trace_azx_runtime_suspend(chip); |
b8dfc462 ML |
1136 | return 0; |
1137 | } | |
1138 | ||
1139 | static int azx_runtime_resume(struct device *dev) | |
1140 | { | |
1141 | struct snd_card *card = dev_get_drvdata(dev); | |
2d9772ef | 1142 | struct azx *chip; |
b8dfc462 | 1143 | |
3baffc4a | 1144 | if (!azx_is_pm_ready(card)) |
2d9772ef | 1145 | return 0; |
2d9772ef | 1146 | chip = card->private_data; |
f5dac54d | 1147 | __azx_runtime_resume(chip); |
7d4f606c WX |
1148 | |
1149 | /* disable controller Wake Up event*/ | |
f5dac54d | 1150 | azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); |
7d4f606c | 1151 | |
785d8c4b | 1152 | trace_azx_runtime_resume(chip); |
b8dfc462 ML |
1153 | return 0; |
1154 | } | |
6eb827d2 TI |
1155 | |
1156 | static int azx_runtime_idle(struct device *dev) | |
1157 | { | |
1158 | struct snd_card *card = dev_get_drvdata(dev); | |
2d9772ef TI |
1159 | struct azx *chip; |
1160 | struct hda_intel *hda; | |
1161 | ||
1162 | if (!card) | |
1163 | return 0; | |
6eb827d2 | 1164 | |
2d9772ef TI |
1165 | chip = card->private_data; |
1166 | hda = container_of(chip, struct hda_intel, chip); | |
1618e84a | 1167 | if (chip->disabled || hda->init_failed) |
246efa4a DA |
1168 | return 0; |
1169 | ||
55ed9cd1 | 1170 | if (!power_save_controller || !azx_has_pm_runtime(chip) || |
342e8449 | 1171 | azx_bus(chip)->codec_powered || !chip->running) |
6eb827d2 TI |
1172 | return -EBUSY; |
1173 | ||
37a3a98e | 1174 | /* ELD notification gets broken when HD-audio bus is off */ |
dd23e1d5 | 1175 | if (needs_eld_notify_link(chip)) |
37a3a98e TI |
1176 | return -EBUSY; |
1177 | ||
6eb827d2 TI |
1178 | return 0; |
1179 | } | |
1180 | ||
b8dfc462 ML |
1181 | static const struct dev_pm_ops azx_pm = { |
1182 | SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) | |
3e6db33a | 1183 | #ifdef CONFIG_PM_SLEEP |
f5dac54d KHF |
1184 | .prepare = azx_prepare, |
1185 | .complete = azx_complete, | |
3e6db33a XZ |
1186 | .freeze_noirq = azx_freeze_noirq, |
1187 | .thaw_noirq = azx_thaw_noirq, | |
1188 | #endif | |
6eb827d2 | 1189 | SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) |
b8dfc462 ML |
1190 | }; |
1191 | ||
68cb2b55 TI |
1192 | #define AZX_PM_OPS &azx_pm |
1193 | #else | |
3baffc4a TI |
1194 | #define azx_add_card_list(chip) /* NOP */ |
1195 | #define azx_del_card_list(chip) /* NOP */ | |
68cb2b55 | 1196 | #define AZX_PM_OPS NULL |
b8dfc462 | 1197 | #endif /* CONFIG_PM */ |
1da177e4 LT |
1198 | |
1199 | ||
48c8b0eb | 1200 | static int azx_probe_continue(struct azx *chip); |
a82d51ed | 1201 | |
8393ec4a | 1202 | #ifdef SUPPORT_VGA_SWITCHEROO |
e23e7a14 | 1203 | static struct pci_dev *get_bound_vga(struct pci_dev *pci); |
a82d51ed | 1204 | |
a82d51ed TI |
1205 | static void azx_vs_set_state(struct pci_dev *pci, |
1206 | enum vga_switcheroo_state state) | |
1207 | { | |
1208 | struct snd_card *card = pci_get_drvdata(pci); | |
1209 | struct azx *chip = card->private_data; | |
9a34af4a | 1210 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
07f4f97d | 1211 | struct hda_codec *codec; |
a82d51ed TI |
1212 | bool disabled; |
1213 | ||
9a34af4a TI |
1214 | wait_for_completion(&hda->probe_wait); |
1215 | if (hda->init_failed) | |
a82d51ed TI |
1216 | return; |
1217 | ||
1218 | disabled = (state == VGA_SWITCHEROO_OFF); | |
1219 | if (chip->disabled == disabled) | |
1220 | return; | |
1221 | ||
a41d1224 | 1222 | if (!hda->probe_continued) { |
a82d51ed TI |
1223 | chip->disabled = disabled; |
1224 | if (!disabled) { | |
4e76a883 TI |
1225 | dev_info(chip->card->dev, |
1226 | "Start delayed initialization\n"); | |
2393e755 | 1227 | if (azx_probe_continue(chip) < 0) |
4e76a883 | 1228 | dev_err(chip->card->dev, "initialization error\n"); |
a82d51ed TI |
1229 | } |
1230 | } else { | |
2b760d88 | 1231 | dev_info(chip->card->dev, "%s via vga_switcheroo\n", |
4e76a883 | 1232 | disabled ? "Disabling" : "Enabling"); |
a82d51ed | 1233 | if (disabled) { |
07f4f97d LW |
1234 | list_for_each_codec(codec, &chip->bus) { |
1235 | pm_runtime_suspend(hda_codec_dev(codec)); | |
1236 | pm_runtime_disable(hda_codec_dev(codec)); | |
1237 | } | |
1238 | pm_runtime_suspend(card->dev); | |
1239 | pm_runtime_disable(card->dev); | |
2b760d88 | 1240 | /* when we get suspended by vga_switcheroo we end up in D3cold, |
246efa4a DA |
1241 | * however we have no ACPI handle, so pci/acpi can't put us there, |
1242 | * put ourselves there */ | |
1243 | pci->current_state = PCI_D3cold; | |
a82d51ed | 1244 | chip->disabled = true; |
a41d1224 | 1245 | if (snd_hda_lock_devices(&chip->bus)) |
4e76a883 TI |
1246 | dev_warn(chip->card->dev, |
1247 | "Cannot lock devices!\n"); | |
a82d51ed | 1248 | } else { |
a41d1224 | 1249 | snd_hda_unlock_devices(&chip->bus); |
a82d51ed | 1250 | chip->disabled = false; |
07f4f97d LW |
1251 | pm_runtime_enable(card->dev); |
1252 | list_for_each_codec(codec, &chip->bus) { | |
1253 | pm_runtime_enable(hda_codec_dev(codec)); | |
1254 | pm_runtime_resume(hda_codec_dev(codec)); | |
1255 | } | |
a82d51ed TI |
1256 | } |
1257 | } | |
1258 | } | |
1259 | ||
1260 | static bool azx_vs_can_switch(struct pci_dev *pci) | |
1261 | { | |
1262 | struct snd_card *card = pci_get_drvdata(pci); | |
1263 | struct azx *chip = card->private_data; | |
9a34af4a | 1264 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
a82d51ed | 1265 | |
9a34af4a TI |
1266 | wait_for_completion(&hda->probe_wait); |
1267 | if (hda->init_failed) | |
a82d51ed | 1268 | return false; |
a41d1224 | 1269 | if (chip->disabled || !hda->probe_continued) |
a82d51ed | 1270 | return true; |
a41d1224 | 1271 | if (snd_hda_lock_devices(&chip->bus)) |
a82d51ed | 1272 | return false; |
a41d1224 | 1273 | snd_hda_unlock_devices(&chip->bus); |
a82d51ed TI |
1274 | return true; |
1275 | } | |
1276 | ||
37a3a98e TI |
1277 | /* |
1278 | * The discrete GPU cannot power down unless the HDA controller runtime | |
1279 | * suspends, so activate runtime PM on codecs even if power_save == 0. | |
1280 | */ | |
1281 | static void setup_vga_switcheroo_runtime_pm(struct azx *chip) | |
1282 | { | |
1283 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); | |
1284 | struct hda_codec *codec; | |
1285 | ||
dd23e1d5 | 1286 | if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { |
37a3a98e TI |
1287 | list_for_each_codec(codec, &chip->bus) |
1288 | codec->auto_runtime_pm = 1; | |
1289 | /* reset the power save setup */ | |
1290 | if (chip->running) | |
1291 | set_default_power_save(chip); | |
1292 | } | |
1293 | } | |
1294 | ||
1295 | static void azx_vs_gpu_bound(struct pci_dev *pci, | |
1296 | enum vga_switcheroo_client_id client_id) | |
1297 | { | |
1298 | struct snd_card *card = pci_get_drvdata(pci); | |
1299 | struct azx *chip = card->private_data; | |
37a3a98e TI |
1300 | |
1301 | if (client_id == VGA_SWITCHEROO_DIS) | |
dd23e1d5 | 1302 | chip->bus.keep_power = 0; |
37a3a98e TI |
1303 | setup_vga_switcheroo_runtime_pm(chip); |
1304 | } | |
1305 | ||
e23e7a14 | 1306 | static void init_vga_switcheroo(struct azx *chip) |
a82d51ed | 1307 | { |
9a34af4a | 1308 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
a82d51ed | 1309 | struct pci_dev *p = get_bound_vga(chip->pci); |
bacd8614 | 1310 | struct pci_dev *parent; |
a82d51ed | 1311 | if (p) { |
4e76a883 | 1312 | dev_info(chip->card->dev, |
2b760d88 | 1313 | "Handle vga_switcheroo audio client\n"); |
9a34af4a | 1314 | hda->use_vga_switcheroo = 1; |
bacd8614 KHF |
1315 | |
1316 | /* cleared in either gpu_bound op or codec probe, or when its | |
1317 | * upstream port has _PR3 (i.e. dGPU). | |
1318 | */ | |
1319 | parent = pci_upstream_bridge(p); | |
1320 | chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; | |
07f4f97d | 1321 | chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; |
a82d51ed TI |
1322 | pci_dev_put(p); |
1323 | } | |
1324 | } | |
1325 | ||
1326 | static const struct vga_switcheroo_client_ops azx_vs_ops = { | |
1327 | .set_gpu_state = azx_vs_set_state, | |
1328 | .can_switch = azx_vs_can_switch, | |
37a3a98e | 1329 | .gpu_bound = azx_vs_gpu_bound, |
a82d51ed TI |
1330 | }; |
1331 | ||
e23e7a14 | 1332 | static int register_vga_switcheroo(struct azx *chip) |
a82d51ed | 1333 | { |
9a34af4a | 1334 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
4aaf448f | 1335 | struct pci_dev *p; |
128960a9 TI |
1336 | int err; |
1337 | ||
9a34af4a | 1338 | if (!hda->use_vga_switcheroo) |
a82d51ed | 1339 | return 0; |
4aaf448f JQ |
1340 | |
1341 | p = get_bound_vga(chip->pci); | |
1342 | err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); | |
1343 | pci_dev_put(p); | |
1344 | ||
128960a9 TI |
1345 | if (err < 0) |
1346 | return err; | |
9a34af4a | 1347 | hda->vga_switcheroo_registered = 1; |
246efa4a | 1348 | |
128960a9 | 1349 | return 0; |
a82d51ed TI |
1350 | } |
1351 | #else | |
1352 | #define init_vga_switcheroo(chip) /* NOP */ | |
1353 | #define register_vga_switcheroo(chip) 0 | |
8393ec4a | 1354 | #define check_hdmi_disabled(pci) false |
37a3a98e | 1355 | #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ |
a82d51ed TI |
1356 | #endif /* SUPPORT_VGA_SWITCHER */ |
1357 | ||
1da177e4 LT |
1358 | /* |
1359 | * destructor | |
1360 | */ | |
2393e755 | 1361 | static void azx_free(struct azx *chip) |
1da177e4 | 1362 | { |
c67e2228 | 1363 | struct pci_dev *pci = chip->pci; |
a07187c9 | 1364 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
a41d1224 | 1365 | struct hdac_bus *bus = azx_bus(chip); |
4ce107b9 | 1366 | |
2393e755 TI |
1367 | if (hda->freed) |
1368 | return; | |
1369 | ||
364aa716 | 1370 | if (azx_has_pm_runtime(chip) && chip->running) |
c67e2228 | 1371 | pm_runtime_get_noresume(&pci->dev); |
37a3a98e | 1372 | chip->running = 0; |
c67e2228 | 1373 | |
65fcd41d TI |
1374 | azx_del_card_list(chip); |
1375 | ||
9a34af4a TI |
1376 | hda->init_failed = 1; /* to be sure */ |
1377 | complete_all(&hda->probe_wait); | |
f4c482a4 | 1378 | |
9a34af4a | 1379 | if (use_vga_switcheroo(hda)) { |
a41d1224 TI |
1380 | if (chip->disabled && hda->probe_continued) |
1381 | snd_hda_unlock_devices(&chip->bus); | |
07f4f97d | 1382 | if (hda->vga_switcheroo_registered) |
128960a9 | 1383 | vga_switcheroo_unregister_client(chip->pci); |
a82d51ed TI |
1384 | } |
1385 | ||
a41d1224 | 1386 | if (bus->chip_init) { |
9ad593f6 | 1387 | azx_clear_irq_pending(chip); |
7833c3f8 | 1388 | azx_stop_all_streams(chip); |
1a7f60b9 | 1389 | azx_stop_chip(chip); |
1da177e4 LT |
1390 | } |
1391 | ||
a41d1224 TI |
1392 | if (bus->irq >= 0) |
1393 | free_irq(bus->irq, (void*)chip); | |
68e7fffc | 1394 | if (chip->msi) |
30b35399 | 1395 | pci_disable_msi(chip->pci); |
a41d1224 | 1396 | iounmap(bus->remap_addr); |
1da177e4 | 1397 | |
67908994 | 1398 | azx_free_stream_pages(chip); |
a41d1224 TI |
1399 | azx_free_streams(chip); |
1400 | snd_hdac_bus_exit(bus); | |
1401 | ||
a82d51ed TI |
1402 | if (chip->region_requested) |
1403 | pci_release_regions(chip->pci); | |
a41d1224 | 1404 | |
1da177e4 | 1405 | pci_disable_device(chip->pci); |
4918cdab | 1406 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
f0acd28c | 1407 | release_firmware(chip->fw); |
4918cdab | 1408 | #endif |
e454ff8e | 1409 | display_power(chip, false); |
98d8fc6c | 1410 | |
fc18282c | 1411 | if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) |
fcc88d91 | 1412 | snd_hdac_i915_exit(bus); |
1da177e4 | 1413 | |
2393e755 | 1414 | hda->freed = 1; |
1da177e4 LT |
1415 | } |
1416 | ||
a41d1224 TI |
1417 | static int azx_dev_disconnect(struct snd_device *device) |
1418 | { | |
1419 | struct azx *chip = device->device_data; | |
ca58f551 | 1420 | struct hdac_bus *bus = azx_bus(chip); |
a41d1224 TI |
1421 | |
1422 | chip->bus.shutdown = 1; | |
ca58f551 TI |
1423 | cancel_work_sync(&bus->unsol_work); |
1424 | ||
a41d1224 TI |
1425 | return 0; |
1426 | } | |
1427 | ||
a98f90fd | 1428 | static int azx_dev_free(struct snd_device *device) |
1da177e4 | 1429 | { |
2393e755 TI |
1430 | azx_free(device->device_data); |
1431 | return 0; | |
1da177e4 LT |
1432 | } |
1433 | ||
8393ec4a | 1434 | #ifdef SUPPORT_VGA_SWITCHEROO |
586bc4aa AD |
1435 | #ifdef CONFIG_ACPI |
1436 | /* ATPX is in the integrated GPU's namespace */ | |
1437 | static bool atpx_present(void) | |
1438 | { | |
1439 | struct pci_dev *pdev = NULL; | |
1440 | acpi_handle dhandle, atpx_handle; | |
1441 | acpi_status status; | |
1442 | ||
8cc0991c AD |
1443 | while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { |
1444 | dhandle = ACPI_HANDLE(&pdev->dev); | |
1445 | if (dhandle) { | |
1446 | status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); | |
1447 | if (!ACPI_FAILURE(status)) { | |
1448 | pci_dev_put(pdev); | |
1449 | return true; | |
1450 | } | |
1451 | } | |
1452 | } | |
1453 | while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { | |
586bc4aa AD |
1454 | dhandle = ACPI_HANDLE(&pdev->dev); |
1455 | if (dhandle) { | |
1456 | status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); | |
1457 | if (!ACPI_FAILURE(status)) { | |
1458 | pci_dev_put(pdev); | |
1459 | return true; | |
1460 | } | |
1461 | } | |
586bc4aa AD |
1462 | } |
1463 | return false; | |
1464 | } | |
1465 | #else | |
1466 | static bool atpx_present(void) | |
1467 | { | |
1468 | return false; | |
1469 | } | |
1470 | #endif | |
1471 | ||
9121947d | 1472 | /* |
2b760d88 | 1473 | * Check of disabled HDMI controller by vga_switcheroo |
9121947d | 1474 | */ |
e23e7a14 | 1475 | static struct pci_dev *get_bound_vga(struct pci_dev *pci) |
9121947d TI |
1476 | { |
1477 | struct pci_dev *p; | |
1478 | ||
1479 | /* check only discrete GPU */ | |
1480 | switch (pci->vendor) { | |
1481 | case PCI_VENDOR_ID_ATI: | |
1482 | case PCI_VENDOR_ID_AMD: | |
586bc4aa AD |
1483 | if (pci->devfn == 1) { |
1484 | p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), | |
1485 | pci->bus->number, 0); | |
1486 | if (p) { | |
1487 | /* ATPX is in the integrated GPU's ACPI namespace | |
1488 | * rather than the dGPU's namespace. However, | |
1489 | * the dGPU is the one who is involved in | |
1490 | * vgaswitcheroo. | |
1491 | */ | |
1492 | if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && | |
1493 | atpx_present()) | |
1494 | return p; | |
1495 | pci_dev_put(p); | |
1496 | } | |
1497 | } | |
1498 | break; | |
9121947d TI |
1499 | case PCI_VENDOR_ID_NVIDIA: |
1500 | if (pci->devfn == 1) { | |
1501 | p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), | |
1502 | pci->bus->number, 0); | |
1503 | if (p) { | |
b6d7b362 | 1504 | if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) |
9121947d TI |
1505 | return p; |
1506 | pci_dev_put(p); | |
1507 | } | |
1508 | } | |
1509 | break; | |
1510 | } | |
1511 | return NULL; | |
1512 | } | |
1513 | ||
e23e7a14 | 1514 | static bool check_hdmi_disabled(struct pci_dev *pci) |
9121947d TI |
1515 | { |
1516 | bool vga_inactive = false; | |
1517 | struct pci_dev *p = get_bound_vga(pci); | |
1518 | ||
1519 | if (p) { | |
12b78a7f | 1520 | if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) |
9121947d TI |
1521 | vga_inactive = true; |
1522 | pci_dev_put(p); | |
1523 | } | |
1524 | return vga_inactive; | |
1525 | } | |
8393ec4a | 1526 | #endif /* SUPPORT_VGA_SWITCHEROO */ |
9121947d | 1527 | |
3372a153 | 1528 | /* |
6317e5eb | 1529 | * allow/deny-listing for position_fix |
3372a153 | 1530 | */ |
a5dc05e4 | 1531 | static const struct snd_pci_quirk position_fix_list[] = { |
d2e1c973 TI |
1532 | SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), |
1533 | SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), | |
2f703e7a | 1534 | SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), |
d2e1c973 | 1535 | SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), |
dd37f8e8 | 1536 | SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), |
9f75c1b1 | 1537 | SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), |
e96d3127 | 1538 | SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), |
b01de4fb | 1539 | SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), |
61bb42c3 | 1540 | SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), |
9ec8ddad | 1541 | SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), |
45d4ebf1 | 1542 | SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), |
8815cd03 | 1543 | SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), |
b90c0764 | 1544 | SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), |
0e0280dc | 1545 | SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), |
3372a153 TI |
1546 | {} |
1547 | }; | |
1548 | ||
e23e7a14 | 1549 | static int check_position_fix(struct azx *chip, int fix) |
3372a153 TI |
1550 | { |
1551 | const struct snd_pci_quirk *q; | |
1552 | ||
c673ba1c | 1553 | switch (fix) { |
1dac6695 | 1554 | case POS_FIX_AUTO: |
c673ba1c TI |
1555 | case POS_FIX_LPIB: |
1556 | case POS_FIX_POSBUF: | |
4cb36310 | 1557 | case POS_FIX_VIACOMBO: |
a6f2fd55 | 1558 | case POS_FIX_COMBO: |
f87e7f25 | 1559 | case POS_FIX_SKL: |
c02f77d3 | 1560 | case POS_FIX_FIFO: |
c673ba1c TI |
1561 | return fix; |
1562 | } | |
1563 | ||
c673ba1c TI |
1564 | q = snd_pci_quirk_lookup(chip->pci, position_fix_list); |
1565 | if (q) { | |
4e76a883 TI |
1566 | dev_info(chip->card->dev, |
1567 | "position_fix set to %d for device %04x:%04x\n", | |
1568 | q->value, q->subvendor, q->subdevice); | |
c673ba1c | 1569 | return q->value; |
3372a153 | 1570 | } |
bdd9ef24 DH |
1571 | |
1572 | /* Check VIA/ATI HD Audio Controller exist */ | |
26f05717 | 1573 | if (chip->driver_type == AZX_DRIVER_VIA) { |
4e76a883 | 1574 | dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); |
bdd9ef24 | 1575 | return POS_FIX_VIACOMBO; |
9477c58e | 1576 | } |
c02f77d3 TI |
1577 | if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { |
1578 | dev_dbg(chip->card->dev, "Using FIFO position fix\n"); | |
1579 | return POS_FIX_FIFO; | |
1580 | } | |
9477c58e | 1581 | if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { |
4e76a883 | 1582 | dev_dbg(chip->card->dev, "Using LPIB position fix\n"); |
50e3bbf9 | 1583 | return POS_FIX_LPIB; |
bdd9ef24 | 1584 | } |
a4b4793f | 1585 | if (chip->driver_type == AZX_DRIVER_SKL) { |
f87e7f25 TI |
1586 | dev_dbg(chip->card->dev, "Using SKL position fix\n"); |
1587 | return POS_FIX_SKL; | |
1588 | } | |
c673ba1c | 1589 | return POS_FIX_AUTO; |
3372a153 TI |
1590 | } |
1591 | ||
b6050ef6 TI |
1592 | static void assign_position_fix(struct azx *chip, int fix) |
1593 | { | |
bf82326f | 1594 | static const azx_get_pos_callback_t callbacks[] = { |
b6050ef6 TI |
1595 | [POS_FIX_AUTO] = NULL, |
1596 | [POS_FIX_LPIB] = azx_get_pos_lpib, | |
1597 | [POS_FIX_POSBUF] = azx_get_pos_posbuf, | |
1598 | [POS_FIX_VIACOMBO] = azx_via_get_position, | |
1599 | [POS_FIX_COMBO] = azx_get_pos_lpib, | |
f87e7f25 | 1600 | [POS_FIX_SKL] = azx_get_pos_skl, |
c02f77d3 | 1601 | [POS_FIX_FIFO] = azx_get_pos_fifo, |
b6050ef6 TI |
1602 | }; |
1603 | ||
1604 | chip->get_position[0] = chip->get_position[1] = callbacks[fix]; | |
1605 | ||
1606 | /* combo mode uses LPIB only for playback */ | |
1607 | if (fix == POS_FIX_COMBO) | |
1608 | chip->get_position[1] = NULL; | |
1609 | ||
f87e7f25 | 1610 | if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && |
b6050ef6 TI |
1611 | (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { |
1612 | chip->get_delay[0] = chip->get_delay[1] = | |
1613 | azx_get_delay_from_lpib; | |
1614 | } | |
1615 | ||
c02f77d3 TI |
1616 | if (fix == POS_FIX_FIFO) |
1617 | chip->get_delay[0] = chip->get_delay[1] = | |
1618 | azx_get_delay_from_fifo; | |
b6050ef6 TI |
1619 | } |
1620 | ||
669ba27a | 1621 | /* |
6317e5eb | 1622 | * deny-lists for probe_mask |
669ba27a | 1623 | */ |
a5dc05e4 | 1624 | static const struct snd_pci_quirk probe_mask_list[] = { |
669ba27a TI |
1625 | /* Thinkpad often breaks the controller communication when accessing |
1626 | * to the non-working (or non-existing) modem codec slot. | |
1627 | */ | |
1628 | SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), | |
1629 | SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), | |
1630 | SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), | |
0edb9454 TI |
1631 | /* broken BIOS */ |
1632 | SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), | |
ef1681d8 TI |
1633 | /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ |
1634 | SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), | |
20db7cb0 | 1635 | /* forced codec slots */ |
93574844 | 1636 | SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), |
20db7cb0 | 1637 | SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), |
f3af9051 JK |
1638 | /* WinFast VP200 H (Teradici) user reported broken communication */ |
1639 | SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), | |
669ba27a TI |
1640 | {} |
1641 | }; | |
1642 | ||
f1eaaeec TI |
1643 | #define AZX_FORCE_CODEC_MASK 0x100 |
1644 | ||
e23e7a14 | 1645 | static void check_probe_mask(struct azx *chip, int dev) |
669ba27a TI |
1646 | { |
1647 | const struct snd_pci_quirk *q; | |
1648 | ||
f1eaaeec TI |
1649 | chip->codec_probe_mask = probe_mask[dev]; |
1650 | if (chip->codec_probe_mask == -1) { | |
669ba27a TI |
1651 | q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); |
1652 | if (q) { | |
4e76a883 TI |
1653 | dev_info(chip->card->dev, |
1654 | "probe_mask set to 0x%x for device %04x:%04x\n", | |
1655 | q->value, q->subvendor, q->subdevice); | |
f1eaaeec | 1656 | chip->codec_probe_mask = q->value; |
669ba27a TI |
1657 | } |
1658 | } | |
f1eaaeec TI |
1659 | |
1660 | /* check forced option */ | |
1661 | if (chip->codec_probe_mask != -1 && | |
1662 | (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { | |
a41d1224 | 1663 | azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; |
4e76a883 | 1664 | dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", |
a41d1224 | 1665 | (int)azx_bus(chip)->codec_mask); |
f1eaaeec | 1666 | } |
669ba27a TI |
1667 | } |
1668 | ||
4d8e22e0 | 1669 | /* |
6317e5eb | 1670 | * allow/deny-list for enable_msi |
4d8e22e0 | 1671 | */ |
6317e5eb | 1672 | static const struct snd_pci_quirk msi_deny_list[] = { |
693e0cb0 DH |
1673 | SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ |
1674 | SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ | |
1675 | SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ | |
1676 | SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ | |
9dc8398b | 1677 | SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ |
0a27fcfa | 1678 | SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ |
ecd21626 | 1679 | SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ |
83f72151 | 1680 | SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ |
4193d13b | 1681 | SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ |
3815595e | 1682 | SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ |
4d8e22e0 TI |
1683 | {} |
1684 | }; | |
1685 | ||
e23e7a14 | 1686 | static void check_msi(struct azx *chip) |
4d8e22e0 TI |
1687 | { |
1688 | const struct snd_pci_quirk *q; | |
1689 | ||
71623855 TI |
1690 | if (enable_msi >= 0) { |
1691 | chip->msi = !!enable_msi; | |
4d8e22e0 | 1692 | return; |
71623855 TI |
1693 | } |
1694 | chip->msi = 1; /* enable MSI as default */ | |
6317e5eb | 1695 | q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); |
4d8e22e0 | 1696 | if (q) { |
4e76a883 TI |
1697 | dev_info(chip->card->dev, |
1698 | "msi for device %04x:%04x set to %d\n", | |
1699 | q->subvendor, q->subdevice, q->value); | |
4d8e22e0 | 1700 | chip->msi = q->value; |
80c43ed7 TI |
1701 | return; |
1702 | } | |
1703 | ||
1704 | /* NVidia chipsets seem to cause troubles with MSI */ | |
9477c58e | 1705 | if (chip->driver_caps & AZX_DCAPS_NO_MSI) { |
4e76a883 | 1706 | dev_info(chip->card->dev, "Disabling MSI\n"); |
80c43ed7 | 1707 | chip->msi = 0; |
4d8e22e0 TI |
1708 | } |
1709 | } | |
1710 | ||
a1585d76 | 1711 | /* check the snoop mode availability */ |
e23e7a14 | 1712 | static void azx_check_snoop_available(struct azx *chip) |
a1585d76 | 1713 | { |
7c732015 | 1714 | int snoop = hda_snoop; |
a1585d76 | 1715 | |
7c732015 TI |
1716 | if (snoop >= 0) { |
1717 | dev_info(chip->card->dev, "Force to %s mode by module option\n", | |
1718 | snoop ? "snoop" : "non-snoop"); | |
1719 | chip->snoop = snoop; | |
78c9be61 | 1720 | chip->uc_buffer = !snoop; |
7c732015 TI |
1721 | return; |
1722 | } | |
1723 | ||
1724 | snoop = true; | |
37e661ee TI |
1725 | if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && |
1726 | chip->driver_type == AZX_DRIVER_VIA) { | |
a1585d76 TI |
1727 | /* force to non-snoop mode for a new VIA controller |
1728 | * when BIOS is set | |
1729 | */ | |
7c732015 TI |
1730 | u8 val; |
1731 | pci_read_config_byte(chip->pci, 0x42, &val); | |
af52f998 DW |
1732 | if (!(val & 0x80) && (chip->pci->revision == 0x30 || |
1733 | chip->pci->revision == 0x20)) | |
7c732015 | 1734 | snoop = false; |
a1585d76 TI |
1735 | } |
1736 | ||
37e661ee TI |
1737 | if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) |
1738 | snoop = false; | |
1739 | ||
7c732015 | 1740 | chip->snoop = snoop; |
78c9be61 | 1741 | if (!snoop) { |
7c732015 | 1742 | dev_info(chip->card->dev, "Force to non-snoop mode\n"); |
78c9be61 TI |
1743 | /* C-Media requires non-cached pages only for CORB/RIRB */ |
1744 | if (chip->driver_type != AZX_DRIVER_CMEDIA) | |
1745 | chip->uc_buffer = true; | |
1746 | } | |
a1585d76 | 1747 | } |
669ba27a | 1748 | |
99a2008d WX |
1749 | static void azx_probe_work(struct work_struct *work) |
1750 | { | |
9a34af4a TI |
1751 | struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); |
1752 | azx_probe_continue(&hda->chip); | |
99a2008d | 1753 | } |
99a2008d | 1754 | |
4f0189be TI |
1755 | static int default_bdl_pos_adj(struct azx *chip) |
1756 | { | |
2cf721db TI |
1757 | /* some exceptions: Atoms seem problematic with value 1 */ |
1758 | if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { | |
1759 | switch (chip->pci->device) { | |
1760 | case 0x0f04: /* Baytrail */ | |
1761 | case 0x2284: /* Braswell */ | |
1762 | return 32; | |
1763 | } | |
1764 | } | |
1765 | ||
4f0189be TI |
1766 | switch (chip->driver_type) { |
1767 | case AZX_DRIVER_ICH: | |
1768 | case AZX_DRIVER_PCH: | |
1769 | return 1; | |
1770 | default: | |
1771 | return 32; | |
1772 | } | |
1773 | } | |
1774 | ||
1da177e4 LT |
1775 | /* |
1776 | * constructor | |
1777 | */ | |
a43ff5ba TI |
1778 | static const struct hda_controller_ops pci_hda_ops; |
1779 | ||
e23e7a14 BP |
1780 | static int azx_create(struct snd_card *card, struct pci_dev *pci, |
1781 | int dev, unsigned int driver_caps, | |
1782 | struct azx **rchip) | |
1da177e4 | 1783 | { |
41f394a8 | 1784 | static const struct snd_device_ops ops = { |
a41d1224 | 1785 | .dev_disconnect = azx_dev_disconnect, |
1da177e4 LT |
1786 | .dev_free = azx_dev_free, |
1787 | }; | |
a07187c9 | 1788 | struct hda_intel *hda; |
a82d51ed TI |
1789 | struct azx *chip; |
1790 | int err; | |
1da177e4 LT |
1791 | |
1792 | *rchip = NULL; | |
bcd72003 | 1793 | |
927fc866 PM |
1794 | err = pci_enable_device(pci); |
1795 | if (err < 0) | |
1da177e4 LT |
1796 | return err; |
1797 | ||
2393e755 | 1798 | hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); |
a07187c9 | 1799 | if (!hda) { |
1da177e4 LT |
1800 | pci_disable_device(pci); |
1801 | return -ENOMEM; | |
1802 | } | |
1803 | ||
a07187c9 | 1804 | chip = &hda->chip; |
62932df8 | 1805 | mutex_init(&chip->open_mutex); |
1da177e4 LT |
1806 | chip->card = card; |
1807 | chip->pci = pci; | |
a43ff5ba | 1808 | chip->ops = &pci_hda_ops; |
9477c58e TI |
1809 | chip->driver_caps = driver_caps; |
1810 | chip->driver_type = driver_caps & 0xff; | |
4d8e22e0 | 1811 | check_msi(chip); |
555e219f | 1812 | chip->dev_index = dev; |
3a182c84 TI |
1813 | if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) |
1814 | chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); | |
01b65bfb | 1815 | INIT_LIST_HEAD(&chip->pcm_list); |
9a34af4a TI |
1816 | INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); |
1817 | INIT_LIST_HEAD(&hda->list); | |
a82d51ed | 1818 | init_vga_switcheroo(chip); |
9a34af4a | 1819 | init_completion(&hda->probe_wait); |
1da177e4 | 1820 | |
b6050ef6 | 1821 | assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); |
a6f2fd55 | 1822 | |
5aba4f8e | 1823 | check_probe_mask(chip, dev); |
3372a153 | 1824 | |
41438f13 TI |
1825 | if (single_cmd < 0) /* allow fallback to single_cmd at errors */ |
1826 | chip->fallback_to_single_cmd = 1; | |
1827 | else /* explicitly set to single_cmd or not */ | |
1828 | chip->single_cmd = single_cmd; | |
1829 | ||
a1585d76 | 1830 | azx_check_snoop_available(chip); |
c74db86b | 1831 | |
4f0189be TI |
1832 | if (bdl_pos_adj[dev] < 0) |
1833 | chip->bdl_pos_adj = default_bdl_pos_adj(chip); | |
1834 | else | |
1835 | chip->bdl_pos_adj = bdl_pos_adj[dev]; | |
5c0d7bc1 | 1836 | |
19abfefd | 1837 | err = azx_bus_init(chip, model[dev]); |
a41d1224 | 1838 | if (err < 0) { |
a41d1224 TI |
1839 | pci_disable_device(pci); |
1840 | return err; | |
1841 | } | |
1842 | ||
619a1f19 TI |
1843 | /* use the non-cached pages in non-snoop mode */ |
1844 | if (!azx_snoop(chip)) | |
1845 | azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC; | |
1846 | ||
7d9a1808 TI |
1847 | if (chip->driver_type == AZX_DRIVER_NVIDIA) { |
1848 | dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); | |
5f2cb361 | 1849 | chip->bus.core.needs_damn_long_delay = 1; |
7d9a1808 TI |
1850 | } |
1851 | ||
a82d51ed TI |
1852 | err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); |
1853 | if (err < 0) { | |
4e76a883 | 1854 | dev_err(card->dev, "Error creating device [card]!\n"); |
a82d51ed TI |
1855 | azx_free(chip); |
1856 | return err; | |
1857 | } | |
1858 | ||
99a2008d | 1859 | /* continue probing in work context as may trigger request module */ |
9a34af4a | 1860 | INIT_WORK(&hda->probe_work, azx_probe_work); |
99a2008d | 1861 | |
a82d51ed | 1862 | *rchip = chip; |
99a2008d | 1863 | |
a82d51ed TI |
1864 | return 0; |
1865 | } | |
1866 | ||
48c8b0eb | 1867 | static int azx_first_init(struct azx *chip) |
a82d51ed TI |
1868 | { |
1869 | int dev = chip->dev_index; | |
1870 | struct pci_dev *pci = chip->pci; | |
1871 | struct snd_card *card = chip->card; | |
a41d1224 | 1872 | struct hdac_bus *bus = azx_bus(chip); |
67908994 | 1873 | int err; |
a82d51ed | 1874 | unsigned short gcap; |
413cbf46 | 1875 | unsigned int dma_bits = 64; |
a82d51ed | 1876 | |
07e4ca50 TI |
1877 | #if BITS_PER_LONG != 64 |
1878 | /* Fix up base address on ULI M5461 */ | |
1879 | if (chip->driver_type == AZX_DRIVER_ULI) { | |
1880 | u16 tmp3; | |
1881 | pci_read_config_word(pci, 0x40, &tmp3); | |
1882 | pci_write_config_word(pci, 0x40, tmp3 | 0x10); | |
1883 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); | |
1884 | } | |
1885 | #endif | |
1886 | ||
927fc866 | 1887 | err = pci_request_regions(pci, "ICH HD audio"); |
a82d51ed | 1888 | if (err < 0) |
1da177e4 | 1889 | return err; |
a82d51ed | 1890 | chip->region_requested = 1; |
1da177e4 | 1891 | |
a41d1224 TI |
1892 | bus->addr = pci_resource_start(pci, 0); |
1893 | bus->remap_addr = pci_ioremap_bar(pci, 0); | |
1894 | if (bus->remap_addr == NULL) { | |
4e76a883 | 1895 | dev_err(card->dev, "ioremap error\n"); |
a82d51ed | 1896 | return -ENXIO; |
1da177e4 LT |
1897 | } |
1898 | ||
a4b4793f | 1899 | if (chip->driver_type == AZX_DRIVER_SKL) |
50279d9b GS |
1900 | snd_hdac_bus_parse_capabilities(bus); |
1901 | ||
1902 | /* | |
1903 | * Some Intel CPUs has always running timer (ART) feature and | |
1904 | * controller may have Global time sync reporting capability, so | |
1905 | * check both of these before declaring synchronized time reporting | |
1906 | * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME | |
1907 | */ | |
1908 | chip->gts_present = false; | |
1909 | ||
1910 | #ifdef CONFIG_X86 | |
1911 | if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) | |
1912 | chip->gts_present = true; | |
1913 | #endif | |
1914 | ||
db79afa1 BH |
1915 | if (chip->msi) { |
1916 | if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { | |
1917 | dev_dbg(card->dev, "Disabling 64bit MSI\n"); | |
1918 | pci->no_64bit_msi = true; | |
1919 | } | |
68e7fffc TI |
1920 | if (pci_enable_msi(pci) < 0) |
1921 | chip->msi = 0; | |
db79afa1 | 1922 | } |
7376d013 | 1923 | |
1da177e4 | 1924 | pci_set_master(pci); |
1da177e4 | 1925 | |
bcd72003 | 1926 | gcap = azx_readw(chip, GCAP); |
4e76a883 | 1927 | dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); |
bcd72003 | 1928 | |
413cbf46 TI |
1929 | /* AMD devices support 40 or 48bit DMA, take the safe one */ |
1930 | if (chip->pci->vendor == PCI_VENDOR_ID_AMD) | |
1931 | dma_bits = 40; | |
1932 | ||
dc4c2e6b | 1933 | /* disable SB600 64bit support for safety */ |
9477c58e | 1934 | if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { |
dc4c2e6b | 1935 | struct pci_dev *p_smbus; |
413cbf46 | 1936 | dma_bits = 40; |
dc4c2e6b AB |
1937 | p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, |
1938 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
1939 | NULL); | |
1940 | if (p_smbus) { | |
1941 | if (p_smbus->revision < 0x30) | |
fb1d8ac2 | 1942 | gcap &= ~AZX_GCAP_64OK; |
dc4c2e6b AB |
1943 | pci_dev_put(p_smbus); |
1944 | } | |
1945 | } | |
09240cf4 | 1946 | |
3ab7511e AB |
1947 | /* NVidia hardware normally only supports up to 40 bits of DMA */ |
1948 | if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) | |
1949 | dma_bits = 40; | |
1950 | ||
9477c58e TI |
1951 | /* disable 64bit DMA address on some devices */ |
1952 | if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { | |
4e76a883 | 1953 | dev_dbg(card->dev, "Disabling 64bit DMA\n"); |
fb1d8ac2 | 1954 | gcap &= ~AZX_GCAP_64OK; |
9477c58e | 1955 | } |
396087ea | 1956 | |
2ae66c26 | 1957 | /* disable buffer size rounding to 128-byte multiples if supported */ |
7bfe059e TI |
1958 | if (align_buffer_size >= 0) |
1959 | chip->align_buffer_size = !!align_buffer_size; | |
1960 | else { | |
103884a3 | 1961 | if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) |
7bfe059e | 1962 | chip->align_buffer_size = 0; |
7bfe059e TI |
1963 | else |
1964 | chip->align_buffer_size = 1; | |
1965 | } | |
2ae66c26 | 1966 | |
cf7aaca8 | 1967 | /* allow 64bit DMA address if supported by H/W */ |
413cbf46 TI |
1968 | if (!(gcap & AZX_GCAP_64OK)) |
1969 | dma_bits = 32; | |
412b979c QL |
1970 | if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { |
1971 | dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); | |
413cbf46 | 1972 | } else { |
412b979c QL |
1973 | dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); |
1974 | dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); | |
09240cf4 | 1975 | } |
cf7aaca8 | 1976 | |
8b6ed8e7 TI |
1977 | /* read number of streams from GCAP register instead of using |
1978 | * hardcoded value | |
1979 | */ | |
1980 | chip->capture_streams = (gcap >> 8) & 0x0f; | |
1981 | chip->playback_streams = (gcap >> 12) & 0x0f; | |
1982 | if (!chip->playback_streams && !chip->capture_streams) { | |
bcd72003 TD |
1983 | /* gcap didn't give any info, switching to old method */ |
1984 | ||
1985 | switch (chip->driver_type) { | |
1986 | case AZX_DRIVER_ULI: | |
1987 | chip->playback_streams = ULI_NUM_PLAYBACK; | |
1988 | chip->capture_streams = ULI_NUM_CAPTURE; | |
bcd72003 TD |
1989 | break; |
1990 | case AZX_DRIVER_ATIHDMI: | |
1815b34a | 1991 | case AZX_DRIVER_ATIHDMI_NS: |
bcd72003 TD |
1992 | chip->playback_streams = ATIHDMI_NUM_PLAYBACK; |
1993 | chip->capture_streams = ATIHDMI_NUM_CAPTURE; | |
bcd72003 | 1994 | break; |
c4da29ca | 1995 | case AZX_DRIVER_GENERIC: |
bcd72003 TD |
1996 | default: |
1997 | chip->playback_streams = ICH6_NUM_PLAYBACK; | |
1998 | chip->capture_streams = ICH6_NUM_CAPTURE; | |
bcd72003 TD |
1999 | break; |
2000 | } | |
07e4ca50 | 2001 | } |
8b6ed8e7 TI |
2002 | chip->capture_index_offset = 0; |
2003 | chip->playback_index_offset = chip->capture_streams; | |
07e4ca50 | 2004 | chip->num_streams = chip->playback_streams + chip->capture_streams; |
07e4ca50 | 2005 | |
df56c3db JK |
2006 | /* sanity check for the SDxCTL.STRM field overflow */ |
2007 | if (chip->num_streams > 15 && | |
2008 | (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { | |
2009 | dev_warn(chip->card->dev, "number of I/O streams is %d, " | |
2010 | "forcing separate stream tags", chip->num_streams); | |
2011 | chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; | |
2012 | } | |
2013 | ||
a41d1224 TI |
2014 | /* initialize streams */ |
2015 | err = azx_init_streams(chip); | |
81740861 | 2016 | if (err < 0) |
a82d51ed | 2017 | return err; |
1da177e4 | 2018 | |
a41d1224 TI |
2019 | err = azx_alloc_stream_pages(chip); |
2020 | if (err < 0) | |
2021 | return err; | |
1da177e4 LT |
2022 | |
2023 | /* initialize chip */ | |
cb53c626 | 2024 | azx_init_pci(chip); |
e4d9e513 | 2025 | |
e454ff8e | 2026 | snd_hdac_i915_set_bclk(bus); |
e4d9e513 | 2027 | |
0a673521 | 2028 | hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); |
1da177e4 LT |
2029 | |
2030 | /* codec detection */ | |
a41d1224 | 2031 | if (!azx_bus(chip)->codec_mask) { |
4e76a883 | 2032 | dev_err(card->dev, "no codecs found!\n"); |
9479e75f | 2033 | /* keep running the rest for the runtime PM */ |
1da177e4 LT |
2034 | } |
2035 | ||
f495222e TI |
2036 | if (azx_acquire_irq(chip, 0) < 0) |
2037 | return -EBUSY; | |
2038 | ||
07e4ca50 | 2039 | strcpy(card->driver, "HDA-Intel"); |
18cb7109 TI |
2040 | strlcpy(card->shortname, driver_short_names[chip->driver_type], |
2041 | sizeof(card->shortname)); | |
2042 | snprintf(card->longname, sizeof(card->longname), | |
2043 | "%s at 0x%lx irq %i", | |
a41d1224 | 2044 | card->shortname, bus->addr, bus->irq); |
07e4ca50 | 2045 | |
1da177e4 | 2046 | return 0; |
1da177e4 LT |
2047 | } |
2048 | ||
97c6a3d1 | 2049 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
5cb543db TI |
2050 | /* callback from request_firmware_nowait() */ |
2051 | static void azx_firmware_cb(const struct firmware *fw, void *context) | |
2052 | { | |
2053 | struct snd_card *card = context; | |
2054 | struct azx *chip = card->private_data; | |
5cb543db | 2055 | |
25faa4bd TI |
2056 | if (fw) |
2057 | chip->fw = fw; | |
2058 | else | |
2059 | dev_err(card->dev, "Cannot load firmware, continue without patching\n"); | |
5cb543db TI |
2060 | if (!chip->disabled) { |
2061 | /* continue probing */ | |
25faa4bd | 2062 | azx_probe_continue(chip); |
5cb543db | 2063 | } |
5cb543db | 2064 | } |
97c6a3d1 | 2065 | #endif |
5cb543db | 2066 | |
f46ea609 DR |
2067 | static int disable_msi_reset_irq(struct azx *chip) |
2068 | { | |
a41d1224 | 2069 | struct hdac_bus *bus = azx_bus(chip); |
f46ea609 DR |
2070 | int err; |
2071 | ||
a41d1224 TI |
2072 | free_irq(bus->irq, chip); |
2073 | bus->irq = -1; | |
f36da940 | 2074 | chip->card->sync_irq = -1; |
f46ea609 DR |
2075 | pci_disable_msi(chip->pci); |
2076 | chip->msi = 0; | |
2077 | err = azx_acquire_irq(chip, 1); | |
2078 | if (err < 0) | |
2079 | return err; | |
2080 | ||
2081 | return 0; | |
2082 | } | |
2083 | ||
8769b278 DR |
2084 | static void pcm_mmap_prepare(struct snd_pcm_substream *substream, |
2085 | struct vm_area_struct *area) | |
2086 | { | |
2087 | #ifdef CONFIG_X86 | |
2088 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
2089 | struct azx *chip = apcm->chip; | |
78c9be61 | 2090 | if (chip->uc_buffer) |
8769b278 DR |
2091 | area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); |
2092 | #endif | |
2093 | } | |
2094 | ||
6317e5eb | 2095 | /* Denylist for skipping the whole probe: |
3c6fd1f0 TI |
2096 | * some HD-audio PCI entries are exposed without any codecs, and such devices |
2097 | * should be ignored from the beginning. | |
2098 | */ | |
6317e5eb | 2099 | static const struct pci_device_id driver_denylist[] = { |
977dfef4 TI |
2100 | { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ |
2101 | { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ | |
2102 | { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ | |
3c6fd1f0 TI |
2103 | {} |
2104 | }; | |
2105 | ||
a43ff5ba TI |
2106 | static const struct hda_controller_ops pci_hda_ops = { |
2107 | .disable_msi_reset_irq = disable_msi_reset_irq, | |
8769b278 | 2108 | .pcm_mmap_prepare = pcm_mmap_prepare, |
7ca954a8 | 2109 | .position_check = azx_position_check, |
40830813 DR |
2110 | }; |
2111 | ||
e23e7a14 BP |
2112 | static int azx_probe(struct pci_dev *pci, |
2113 | const struct pci_device_id *pci_id) | |
1da177e4 | 2114 | { |
5aba4f8e | 2115 | static int dev; |
a98f90fd | 2116 | struct snd_card *card; |
9a34af4a | 2117 | struct hda_intel *hda; |
a98f90fd | 2118 | struct azx *chip; |
aad730d0 | 2119 | bool schedule_probe; |
927fc866 | 2120 | int err; |
1da177e4 | 2121 | |
6317e5eb TI |
2122 | if (pci_match_id(driver_denylist, pci)) { |
2123 | dev_info(&pci->dev, "Skipping the device on the denylist\n"); | |
3c6fd1f0 TI |
2124 | return -ENODEV; |
2125 | } | |
2126 | ||
5aba4f8e TI |
2127 | if (dev >= SNDRV_CARDS) |
2128 | return -ENODEV; | |
2129 | if (!enable[dev]) { | |
2130 | dev++; | |
2131 | return -ENOENT; | |
2132 | } | |
2133 | ||
82d9d54a JK |
2134 | /* |
2135 | * stop probe if another Intel's DSP driver should be activated | |
2136 | */ | |
7fba6aea | 2137 | if (dmic_detect) { |
82d9d54a | 2138 | err = snd_intel_dsp_driver_probe(pci); |
ae035947 PLB |
2139 | if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { |
2140 | dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); | |
82d9d54a | 2141 | return -ENODEV; |
ae035947 | 2142 | } |
7fba6aea TI |
2143 | } else { |
2144 | dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); | |
82d9d54a JK |
2145 | } |
2146 | ||
60c5772b TI |
2147 | err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, |
2148 | 0, &card); | |
e58de7ba | 2149 | if (err < 0) { |
4e76a883 | 2150 | dev_err(&pci->dev, "Error creating card!\n"); |
e58de7ba | 2151 | return err; |
1da177e4 LT |
2152 | } |
2153 | ||
a43ff5ba | 2154 | err = azx_create(card, pci, dev, pci_id->driver_data, &chip); |
41dda0fd WF |
2155 | if (err < 0) |
2156 | goto out_free; | |
421a1252 | 2157 | card->private_data = chip; |
9a34af4a | 2158 | hda = container_of(chip, struct hda_intel, chip); |
f4c482a4 TI |
2159 | |
2160 | pci_set_drvdata(pci, card); | |
2161 | ||
2162 | err = register_vga_switcheroo(chip); | |
2163 | if (err < 0) { | |
2b760d88 | 2164 | dev_err(card->dev, "Error registering vga_switcheroo client\n"); |
f4c482a4 TI |
2165 | goto out_free; |
2166 | } | |
2167 | ||
2168 | if (check_hdmi_disabled(pci)) { | |
4e76a883 TI |
2169 | dev_info(card->dev, "VGA controller is disabled\n"); |
2170 | dev_info(card->dev, "Delaying initialization\n"); | |
f4c482a4 TI |
2171 | chip->disabled = true; |
2172 | } | |
2173 | ||
aad730d0 | 2174 | schedule_probe = !chip->disabled; |
1da177e4 | 2175 | |
4918cdab TI |
2176 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
2177 | if (patch[dev] && *patch[dev]) { | |
4e76a883 TI |
2178 | dev_info(card->dev, "Applying patch firmware '%s'\n", |
2179 | patch[dev]); | |
5cb543db TI |
2180 | err = request_firmware_nowait(THIS_MODULE, true, patch[dev], |
2181 | &pci->dev, GFP_KERNEL, card, | |
2182 | azx_firmware_cb); | |
4918cdab TI |
2183 | if (err < 0) |
2184 | goto out_free; | |
aad730d0 | 2185 | schedule_probe = false; /* continued in azx_firmware_cb() */ |
4918cdab TI |
2186 | } |
2187 | #endif /* CONFIG_SND_HDA_PATCH_LOADER */ | |
2188 | ||
aad730d0 | 2189 | #ifndef CONFIG_SND_HDA_I915 |
6ee8eeb4 TI |
2190 | if (CONTROLLER_IN_GPU(pci)) |
2191 | dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); | |
99a2008d | 2192 | #endif |
99a2008d | 2193 | |
aad730d0 | 2194 | if (schedule_probe) |
9a34af4a | 2195 | schedule_work(&hda->probe_work); |
a82d51ed | 2196 | |
a82d51ed | 2197 | dev++; |
88d071fc | 2198 | if (chip->disabled) |
9a34af4a | 2199 | complete_all(&hda->probe_wait); |
a82d51ed TI |
2200 | return 0; |
2201 | ||
2202 | out_free: | |
2203 | snd_card_free(card); | |
2204 | return err; | |
2205 | } | |
2206 | ||
1ba8f9d3 HG |
2207 | #ifdef CONFIG_PM |
2208 | /* On some boards setting power_save to a non 0 value leads to clicking / | |
2209 | * popping sounds when ever we enter/leave powersaving mode. Ideally we would | |
2210 | * figure out how to avoid these sounds, but that is not always feasible. | |
2211 | * So we keep a list of devices where we disable powersaving as its known | |
2212 | * to causes problems on these devices. | |
2213 | */ | |
6317e5eb | 2214 | static const struct snd_pci_quirk power_save_denylist[] = { |
1ba8f9d3 | 2215 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ |
8e82a728 | 2216 | SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), |
1ba8f9d3 | 2217 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ |
39070a98 HG |
2218 | SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), |
2219 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ | |
45e5fbc2 HG |
2220 | SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), |
2221 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ | |
1ba8f9d3 | 2222 | SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), |
b529ef24 HG |
2223 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */ |
2224 | SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0), | |
38d9c12c | 2225 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ |
d8feb608 HG |
2226 | SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0), |
2227 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ | |
5cb6b5fc HG |
2228 | SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), |
2229 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ | |
38d9c12c HG |
2230 | /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ |
2231 | SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), | |
5cb6b5fc HG |
2232 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ |
2233 | SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), | |
f91f1806 HG |
2234 | /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ |
2235 | SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), | |
cae30527 HW |
2236 | /* https://bugs.launchpad.net/bugs/1821663 */ |
2237 | SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), | |
dd6dd536 HG |
2238 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ |
2239 | SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), | |
1ba8f9d3 HG |
2240 | /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ |
2241 | SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), | |
721f1e6c JK |
2242 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ |
2243 | SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), | |
2244 | /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ | |
2245 | SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), | |
cae30527 HW |
2246 | /* https://bugs.launchpad.net/bugs/1821663 */ |
2247 | SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), | |
1ba8f9d3 HG |
2248 | {} |
2249 | }; | |
2250 | #endif /* CONFIG_PM */ | |
2251 | ||
37a3a98e TI |
2252 | static void set_default_power_save(struct azx *chip) |
2253 | { | |
2254 | int val = power_save; | |
2255 | ||
2256 | #ifdef CONFIG_PM | |
2257 | if (pm_blacklist) { | |
2258 | const struct snd_pci_quirk *q; | |
2259 | ||
6317e5eb | 2260 | q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); |
37a3a98e | 2261 | if (q && val) { |
6317e5eb | 2262 | dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", |
37a3a98e TI |
2263 | q->subvendor, q->subdevice); |
2264 | val = 0; | |
2265 | } | |
2266 | } | |
2267 | #endif /* CONFIG_PM */ | |
2268 | snd_hda_set_power_save(&chip->bus, val * 1000); | |
2269 | } | |
2270 | ||
e62a42ae | 2271 | /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ |
bf82326f | 2272 | static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { |
e62a42ae DR |
2273 | [AZX_DRIVER_NVIDIA] = 8, |
2274 | [AZX_DRIVER_TERA] = 1, | |
2275 | }; | |
2276 | ||
48c8b0eb | 2277 | static int azx_probe_continue(struct azx *chip) |
a82d51ed | 2278 | { |
9a34af4a | 2279 | struct hda_intel *hda = container_of(chip, struct hda_intel, chip); |
98d8fc6c | 2280 | struct hdac_bus *bus = azx_bus(chip); |
c67e2228 | 2281 | struct pci_dev *pci = chip->pci; |
a82d51ed TI |
2282 | int dev = chip->dev_index; |
2283 | int err; | |
2284 | ||
305a0ade | 2285 | to_hda_bus(bus)->bus_probing = 1; |
a41d1224 | 2286 | hda->probe_continued = 1; |
795614dd | 2287 | |
fcc88d91 | 2288 | /* bind with i915 if needed */ |
dba9b7b6 | 2289 | if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { |
98d8fc6c | 2290 | err = snd_hdac_i915_init(bus); |
535115b5 TI |
2291 | if (err < 0) { |
2292 | /* if the controller is bound only with HDMI/DP | |
2293 | * (for HSW and BDW), we need to abort the probe; | |
2294 | * for other chips, still continue probing as other | |
2295 | * codecs can be on the same link. | |
2296 | */ | |
bed2e98e TI |
2297 | if (CONTROLLER_IN_GPU(pci)) { |
2298 | dev_err(chip->card->dev, | |
2299 | "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); | |
535115b5 | 2300 | goto out_free; |
fcc88d91 TI |
2301 | } else { |
2302 | /* don't bother any longer */ | |
e454ff8e | 2303 | chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; |
fcc88d91 | 2304 | } |
535115b5 | 2305 | } |
e454ff8e TI |
2306 | |
2307 | /* HSW/BDW controllers need this power */ | |
2308 | if (CONTROLLER_IN_GPU(pci)) | |
2309 | hda->need_i915_power = 1; | |
fcc88d91 TI |
2310 | } |
2311 | ||
2312 | /* Request display power well for the HDA controller or codec. For | |
2313 | * Haswell/Broadwell, both the display HDA controller and codec need | |
2314 | * this power. For other platforms, like Baytrail/Braswell, only the | |
2315 | * display codec needs the power and it can be released after probe. | |
2316 | */ | |
4f799e73 | 2317 | display_power(chip, true); |
99a2008d | 2318 | |
5c90680e TI |
2319 | err = azx_first_init(chip); |
2320 | if (err < 0) | |
2321 | goto out_free; | |
2322 | ||
2dca0bba JK |
2323 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
2324 | chip->beep_mode = beep_mode[dev]; | |
2325 | #endif | |
2326 | ||
1da177e4 | 2327 | /* create codec instances */ |
9479e75f TI |
2328 | if (bus->codec_mask) { |
2329 | err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); | |
2330 | if (err < 0) | |
2331 | goto out_free; | |
2332 | } | |
96d2bd6e | 2333 | |
4ea6fbc8 | 2334 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
4918cdab | 2335 | if (chip->fw) { |
a41d1224 | 2336 | err = snd_hda_load_patch(&chip->bus, chip->fw->size, |
4918cdab | 2337 | chip->fw->data); |
4ea6fbc8 TI |
2338 | if (err < 0) |
2339 | goto out_free; | |
e39ae856 | 2340 | #ifndef CONFIG_PM |
4918cdab TI |
2341 | release_firmware(chip->fw); /* no longer needed */ |
2342 | chip->fw = NULL; | |
e39ae856 | 2343 | #endif |
4ea6fbc8 TI |
2344 | } |
2345 | #endif | |
9479e75f | 2346 | if (bus->codec_mask && !(probe_only[dev] & 1)) { |
a1e21c90 TI |
2347 | err = azx_codec_configure(chip); |
2348 | if (err < 0) | |
2349 | goto out_free; | |
2350 | } | |
1da177e4 | 2351 | |
a82d51ed | 2352 | err = snd_card_register(chip->card); |
41dda0fd WF |
2353 | if (err < 0) |
2354 | goto out_free; | |
1da177e4 | 2355 | |
37a3a98e TI |
2356 | setup_vga_switcheroo_runtime_pm(chip); |
2357 | ||
cb53c626 | 2358 | chip->running = 1; |
65fcd41d | 2359 | azx_add_card_list(chip); |
07f4f97d | 2360 | |
37a3a98e | 2361 | set_default_power_save(chip); |
07f4f97d | 2362 | |
3ba21113 RS |
2363 | if (azx_has_pm_runtime(chip)) { |
2364 | pm_runtime_use_autosuspend(&pci->dev); | |
30ff5957 | 2365 | pm_runtime_put_autosuspend(&pci->dev); |
3ba21113 | 2366 | } |
1da177e4 | 2367 | |
41dda0fd | 2368 | out_free: |
2393e755 TI |
2369 | if (err < 0) { |
2370 | azx_free(chip); | |
2371 | return err; | |
2372 | } | |
2373 | ||
2374 | if (!hda->need_i915_power) | |
029d92c2 | 2375 | display_power(chip, false); |
9a34af4a | 2376 | complete_all(&hda->probe_wait); |
305a0ade | 2377 | to_hda_bus(bus)->bus_probing = 0; |
2393e755 | 2378 | return 0; |
1da177e4 LT |
2379 | } |
2380 | ||
e23e7a14 | 2381 | static void azx_remove(struct pci_dev *pci) |
1da177e4 | 2382 | { |
9121947d | 2383 | struct snd_card *card = pci_get_drvdata(pci); |
991f86d7 TI |
2384 | struct azx *chip; |
2385 | struct hda_intel *hda; | |
2386 | ||
2387 | if (card) { | |
0b8c8219 | 2388 | /* cancel the pending probing work */ |
991f86d7 TI |
2389 | chip = card->private_data; |
2390 | hda = container_of(chip, struct hda_intel, chip); | |
ab949d51 TI |
2391 | /* FIXME: below is an ugly workaround. |
2392 | * Both device_release_driver() and driver_probe_device() | |
2393 | * take *both* the device's and its parent's lock before | |
2394 | * calling the remove() and probe() callbacks. The codec | |
2395 | * probe takes the locks of both the codec itself and its | |
2396 | * parent, i.e. the PCI controller dev. Meanwhile, when | |
2397 | * the PCI controller is unbound, it takes its lock, too | |
2398 | * ==> ouch, a deadlock! | |
2399 | * As a workaround, we unlock temporarily here the controller | |
2400 | * device during cancel_work_sync() call. | |
2401 | */ | |
2402 | device_unlock(&pci->dev); | |
0b8c8219 | 2403 | cancel_work_sync(&hda->probe_work); |
ab949d51 | 2404 | device_lock(&pci->dev); |
b8dfc462 | 2405 | |
9121947d | 2406 | snd_card_free(card); |
991f86d7 | 2407 | } |
1da177e4 LT |
2408 | } |
2409 | ||
b2a0bafa TI |
2410 | static void azx_shutdown(struct pci_dev *pci) |
2411 | { | |
2412 | struct snd_card *card = pci_get_drvdata(pci); | |
2413 | struct azx *chip; | |
2414 | ||
2415 | if (!card) | |
2416 | return; | |
2417 | chip = card->private_data; | |
2418 | if (chip && chip->running) | |
2419 | azx_stop_chip(chip); | |
2420 | } | |
2421 | ||
1da177e4 | 2422 | /* PCI IDs */ |
6f51f6cf | 2423 | static const struct pci_device_id azx_ids[] = { |
d2f2fcd2 | 2424 | /* CPT */ |
9477c58e | 2425 | { PCI_DEVICE(0x8086, 0x1c20), |
d7dab4db | 2426 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
cea310e8 | 2427 | /* PBG */ |
9477c58e | 2428 | { PCI_DEVICE(0x8086, 0x1d20), |
d7dab4db | 2429 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
d2edeb7c | 2430 | /* Panther Point */ |
9477c58e | 2431 | { PCI_DEVICE(0x8086, 0x1e20), |
de5d0ad5 | 2432 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
8bc039a1 SH |
2433 | /* Lynx Point */ |
2434 | { PCI_DEVICE(0x8086, 0x8c20), | |
2ea3c6a2 | 2435 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
77f07800 TI |
2436 | /* 9 Series */ |
2437 | { PCI_DEVICE(0x8086, 0x8ca0), | |
2438 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, | |
884b088f JR |
2439 | /* Wellsburg */ |
2440 | { PCI_DEVICE(0x8086, 0x8d20), | |
2441 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, | |
2442 | { PCI_DEVICE(0x8086, 0x8d21), | |
2443 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, | |
5cf92c8b AY |
2444 | /* Lewisburg */ |
2445 | { PCI_DEVICE(0x8086, 0xa1f0), | |
e7480b34 | 2446 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, |
5cf92c8b | 2447 | { PCI_DEVICE(0x8086, 0xa270), |
e7480b34 | 2448 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, |
144dad99 JR |
2449 | /* Lynx Point-LP */ |
2450 | { PCI_DEVICE(0x8086, 0x9c20), | |
2ea3c6a2 | 2451 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
144dad99 JR |
2452 | /* Lynx Point-LP */ |
2453 | { PCI_DEVICE(0x8086, 0x9c21), | |
2ea3c6a2 | 2454 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
4eeca499 JR |
2455 | /* Wildcat Point-LP */ |
2456 | { PCI_DEVICE(0x8086, 0x9ca0), | |
2457 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, | |
c8b00fd2 JR |
2458 | /* Sunrise Point */ |
2459 | { PCI_DEVICE(0x8086, 0xa170), | |
a4b4793f | 2460 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, |
b4565913 DR |
2461 | /* Sunrise Point-LP */ |
2462 | { PCI_DEVICE(0x8086, 0x9d70), | |
3e9ad24b | 2463 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, |
35639a0e VK |
2464 | /* Kabylake */ |
2465 | { PCI_DEVICE(0x8086, 0xa171), | |
a4b4793f | 2466 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, |
35639a0e VK |
2467 | /* Kabylake-LP */ |
2468 | { PCI_DEVICE(0x8086, 0x9d71), | |
3e9ad24b | 2469 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, |
6858107e VK |
2470 | /* Kabylake-H */ |
2471 | { PCI_DEVICE(0x8086, 0xa2f0), | |
a4b4793f | 2472 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, |
e79b0006 MD |
2473 | /* Coffelake */ |
2474 | { PCI_DEVICE(0x8086, 0xa348), | |
3e9ad24b | 2475 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
2357f6f0 GS |
2476 | /* Cannonlake */ |
2477 | { PCI_DEVICE(0x8086, 0x9dc8), | |
3e9ad24b | 2478 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
d4c2ccdb PLB |
2479 | /* CometLake-LP */ |
2480 | { PCI_DEVICE(0x8086, 0x02C8), | |
2481 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, | |
2482 | /* CometLake-H */ | |
2483 | { PCI_DEVICE(0x8086, 0x06C8), | |
2484 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, | |
b73a5854 CC |
2485 | /* CometLake-S */ |
2486 | { PCI_DEVICE(0x8086, 0xa3f0), | |
2487 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, | |
491f8331 GS |
2488 | /* Icelake */ |
2489 | { PCI_DEVICE(0x8086, 0x34c8), | |
3e9ad24b | 2490 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, |
d50313a5 PLB |
2491 | /* Icelake-H */ |
2492 | { PCI_DEVICE(0x8086, 0x3dc8), | |
2493 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, | |
4750c212 PX |
2494 | /* Jasperlake */ |
2495 | { PCI_DEVICE(0x8086, 0x38c8), | |
2496 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, | |
78be2228 YZ |
2497 | { PCI_DEVICE(0x8086, 0x4dc8), |
2498 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, | |
4750c212 PX |
2499 | /* Tigerlake */ |
2500 | { PCI_DEVICE(0x8086, 0xa0c8), | |
2501 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, | |
d50313a5 PLB |
2502 | /* Tigerlake-H */ |
2503 | { PCI_DEVICE(0x8086, 0x43c8), | |
2504 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, | |
69b08bdf KV |
2505 | /* DG1 */ |
2506 | { PCI_DEVICE(0x8086, 0x490d), | |
2507 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, | |
f94287b6 LPS |
2508 | /* Elkhart Lake */ |
2509 | { PCI_DEVICE(0x8086, 0x4b55), | |
2510 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, | |
d50313a5 PLB |
2511 | { PCI_DEVICE(0x8086, 0x4b58), |
2512 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, | |
c87693da LH |
2513 | /* Broxton-P(Apollolake) */ |
2514 | { PCI_DEVICE(0x8086, 0x5a98), | |
3e9ad24b | 2515 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, |
9859a971 LH |
2516 | /* Broxton-T */ |
2517 | { PCI_DEVICE(0x8086, 0x1a98), | |
a4b4793f | 2518 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, |
44b46d73 VK |
2519 | /* Gemini-Lake */ |
2520 | { PCI_DEVICE(0x8086, 0x3198), | |
3e9ad24b | 2521 | .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, |
e926f2c8 | 2522 | /* Haswell */ |
4a7c516b | 2523 | { PCI_DEVICE(0x8086, 0x0a0c), |
fab1285a | 2524 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, |
e926f2c8 | 2525 | { PCI_DEVICE(0x8086, 0x0c0c), |
fab1285a | 2526 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, |
d279fae8 | 2527 | { PCI_DEVICE(0x8086, 0x0d0c), |
fab1285a | 2528 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, |
862d7618 ML |
2529 | /* Broadwell */ |
2530 | { PCI_DEVICE(0x8086, 0x160c), | |
54a0405d | 2531 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, |
99df18b3 PLB |
2532 | /* 5 Series/3400 */ |
2533 | { PCI_DEVICE(0x8086, 0x3b56), | |
2c1350fd | 2534 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
f748abcc | 2535 | /* Poulsbo */ |
9477c58e | 2536 | { PCI_DEVICE(0x8086, 0x811b), |
6603249d | 2537 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, |
f748abcc | 2538 | /* Oaktrail */ |
09904b95 | 2539 | { PCI_DEVICE(0x8086, 0x080a), |
6603249d | 2540 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, |
e44007e0 CCE |
2541 | /* BayTrail */ |
2542 | { PCI_DEVICE(0x8086, 0x0f04), | |
40cc2392 | 2543 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, |
f31b2ffc LY |
2544 | /* Braswell */ |
2545 | { PCI_DEVICE(0x8086, 0x2284), | |
2d846c74 | 2546 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, |
b42b4afb | 2547 | /* ICH6 */ |
8b0bd226 | 2548 | { PCI_DEVICE(0x8086, 0x2668), |
b42b4afb TI |
2549 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
2550 | /* ICH7 */ | |
8b0bd226 | 2551 | { PCI_DEVICE(0x8086, 0x27d8), |
b42b4afb TI |
2552 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
2553 | /* ESB2 */ | |
8b0bd226 | 2554 | { PCI_DEVICE(0x8086, 0x269a), |
b42b4afb TI |
2555 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
2556 | /* ICH8 */ | |
8b0bd226 | 2557 | { PCI_DEVICE(0x8086, 0x284b), |
b42b4afb TI |
2558 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
2559 | /* ICH9 */ | |
8b0bd226 | 2560 | { PCI_DEVICE(0x8086, 0x293e), |
b42b4afb TI |
2561 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
2562 | /* ICH9 */ | |
8b0bd226 | 2563 | { PCI_DEVICE(0x8086, 0x293f), |
b42b4afb TI |
2564 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
2565 | /* ICH10 */ | |
8b0bd226 | 2566 | { PCI_DEVICE(0x8086, 0x3a3e), |
b42b4afb TI |
2567 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
2568 | /* ICH10 */ | |
8b0bd226 | 2569 | { PCI_DEVICE(0x8086, 0x3a6e), |
b42b4afb | 2570 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, |
b6864535 TI |
2571 | /* Generic Intel */ |
2572 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), | |
2573 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
2574 | .class_mask = 0xffffff, | |
103884a3 | 2575 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, |
9477c58e TI |
2576 | /* ATI SB 450/600/700/800/900 */ |
2577 | { PCI_DEVICE(0x1002, 0x437b), | |
2578 | .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, | |
2579 | { PCI_DEVICE(0x1002, 0x4383), | |
2580 | .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, | |
2581 | /* AMD Hudson */ | |
2582 | { PCI_DEVICE(0x1022, 0x780d), | |
2583 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, | |
c02f77d3 TI |
2584 | /* AMD, X370 & co */ |
2585 | { PCI_DEVICE(0x1022, 0x1457), | |
2586 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, | |
de768ce4 TI |
2587 | /* AMD, X570 & co */ |
2588 | { PCI_DEVICE(0x1022, 0x1487), | |
2589 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, | |
3deef52c KHF |
2590 | /* AMD Stoney */ |
2591 | { PCI_DEVICE(0x1022, 0x157a), | |
2592 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | | |
2593 | AZX_DCAPS_PM_RUNTIME }, | |
9ceace3c VM |
2594 | /* AMD Raven */ |
2595 | { PCI_DEVICE(0x1022, 0x15e3), | |
d2c63b7d | 2596 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, |
87218e9c | 2597 | /* ATI HDMI */ |
fd48331f MSB |
2598 | { PCI_DEVICE(0x1002, 0x0002), |
2599 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, | |
650474fb AD |
2600 | { PCI_DEVICE(0x1002, 0x1308), |
2601 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, | |
5022813d MSB |
2602 | { PCI_DEVICE(0x1002, 0x157a), |
2603 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, | |
d716fb03 AB |
2604 | { PCI_DEVICE(0x1002, 0x15b3), |
2605 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, | |
9477c58e TI |
2606 | { PCI_DEVICE(0x1002, 0x793b), |
2607 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2608 | { PCI_DEVICE(0x1002, 0x7919), | |
2609 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2610 | { PCI_DEVICE(0x1002, 0x960f), | |
2611 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2612 | { PCI_DEVICE(0x1002, 0x970f), | |
2613 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
650474fb AD |
2614 | { PCI_DEVICE(0x1002, 0x9840), |
2615 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, | |
9477c58e TI |
2616 | { PCI_DEVICE(0x1002, 0xaa00), |
2617 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2618 | { PCI_DEVICE(0x1002, 0xaa08), | |
2619 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2620 | { PCI_DEVICE(0x1002, 0xaa10), | |
2621 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2622 | { PCI_DEVICE(0x1002, 0xaa18), | |
2623 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2624 | { PCI_DEVICE(0x1002, 0xaa20), | |
2625 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2626 | { PCI_DEVICE(0x1002, 0xaa28), | |
2627 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2628 | { PCI_DEVICE(0x1002, 0xaa30), | |
2629 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2630 | { PCI_DEVICE(0x1002, 0xaa38), | |
2631 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2632 | { PCI_DEVICE(0x1002, 0xaa40), | |
2633 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2634 | { PCI_DEVICE(0x1002, 0xaa48), | |
2635 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
bbaa0d66 CL |
2636 | { PCI_DEVICE(0x1002, 0xaa50), |
2637 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2638 | { PCI_DEVICE(0x1002, 0xaa58), | |
2639 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2640 | { PCI_DEVICE(0x1002, 0xaa60), | |
2641 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2642 | { PCI_DEVICE(0x1002, 0xaa68), | |
2643 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2644 | { PCI_DEVICE(0x1002, 0xaa80), | |
2645 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2646 | { PCI_DEVICE(0x1002, 0xaa88), | |
2647 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2648 | { PCI_DEVICE(0x1002, 0xaa90), | |
2649 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
2650 | { PCI_DEVICE(0x1002, 0xaa98), | |
2651 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | |
1815b34a | 2652 | { PCI_DEVICE(0x1002, 0x9902), |
37e661ee | 2653 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
1815b34a | 2654 | { PCI_DEVICE(0x1002, 0xaaa0), |
37e661ee | 2655 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
1815b34a | 2656 | { PCI_DEVICE(0x1002, 0xaaa8), |
37e661ee | 2657 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
1815b34a | 2658 | { PCI_DEVICE(0x1002, 0xaab0), |
37e661ee | 2659 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, |
5022813d MSB |
2660 | { PCI_DEVICE(0x1002, 0xaac0), |
2661 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, | |
0fa372b6 TI |
2662 | { PCI_DEVICE(0x1002, 0xaac8), |
2663 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, | |
5022813d | 2664 | { PCI_DEVICE(0x1002, 0xaad8), |
73b1422b AD |
2665 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
2666 | AZX_DCAPS_PM_RUNTIME }, | |
8eb22214 | 2667 | { PCI_DEVICE(0x1002, 0xaae0), |
73b1422b AD |
2668 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
2669 | AZX_DCAPS_PM_RUNTIME }, | |
2670 | { PCI_DEVICE(0x1002, 0xaae8), | |
2671 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | | |
2672 | AZX_DCAPS_PM_RUNTIME }, | |
8eb22214 | 2673 | { PCI_DEVICE(0x1002, 0xaaf0), |
73b1422b AD |
2674 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
2675 | AZX_DCAPS_PM_RUNTIME }, | |
8d68a872 | 2676 | { PCI_DEVICE(0x1002, 0xaaf8), |
73b1422b AD |
2677 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
2678 | AZX_DCAPS_PM_RUNTIME }, | |
8d68a872 | 2679 | { PCI_DEVICE(0x1002, 0xab00), |
73b1422b AD |
2680 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
2681 | AZX_DCAPS_PM_RUNTIME }, | |
8d68a872 | 2682 | { PCI_DEVICE(0x1002, 0xab08), |
73b1422b AD |
2683 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
2684 | AZX_DCAPS_PM_RUNTIME }, | |
8d68a872 | 2685 | { PCI_DEVICE(0x1002, 0xab10), |
73b1422b AD |
2686 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
2687 | AZX_DCAPS_PM_RUNTIME }, | |
8d68a872 | 2688 | { PCI_DEVICE(0x1002, 0xab18), |
73b1422b AD |
2689 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
2690 | AZX_DCAPS_PM_RUNTIME }, | |
8d68a872 | 2691 | { PCI_DEVICE(0x1002, 0xab20), |
73b1422b | 2692 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
27a7c670 HW |
2693 | AZX_DCAPS_PM_RUNTIME }, |
2694 | { PCI_DEVICE(0x1002, 0xab28), | |
2695 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | | |
73b1422b | 2696 | AZX_DCAPS_PM_RUNTIME }, |
8d68a872 | 2697 | { PCI_DEVICE(0x1002, 0xab38), |
73b1422b AD |
2698 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | |
2699 | AZX_DCAPS_PM_RUNTIME }, | |
87218e9c | 2700 | /* VIA VT8251/VT8237A */ |
26f05717 | 2701 | { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, |
754fdff8 AL |
2702 | /* VIA GFX VT7122/VX900 */ |
2703 | { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, | |
2704 | /* VIA GFX VT6122/VX11 */ | |
2705 | { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, | |
87218e9c TI |
2706 | /* SIS966 */ |
2707 | { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, | |
2708 | /* ULI M5461 */ | |
2709 | { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, | |
2710 | /* NVIDIA MCP */ | |
0c2fd1bf TI |
2711 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), |
2712 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
2713 | .class_mask = 0xffffff, | |
9477c58e | 2714 | .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, |
f269002e | 2715 | /* Teradici */ |
9477c58e TI |
2716 | { PCI_DEVICE(0x6549, 0x1200), |
2717 | .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, | |
f0b3da98 LD |
2718 | { PCI_DEVICE(0x6549, 0x2200), |
2719 | .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, | |
4e01f54b | 2720 | /* Creative X-Fi (CA0110-IBG) */ |
f2a8ecaf TI |
2721 | /* CTHDA chips */ |
2722 | { PCI_DEVICE(0x1102, 0x0010), | |
2723 | .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, | |
2724 | { PCI_DEVICE(0x1102, 0x0012), | |
2725 | .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, | |
8eeaa2f9 | 2726 | #if !IS_ENABLED(CONFIG_SND_CTXFI) |
313f6e2d TI |
2727 | /* the following entry conflicts with snd-ctxfi driver, |
2728 | * as ctxfi driver mutates from HD-audio to native mode with | |
2729 | * a special command sequence. | |
2730 | */ | |
4e01f54b TI |
2731 | { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), |
2732 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
2733 | .class_mask = 0xffffff, | |
9477c58e | 2734 | .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | |
ef85f299 | 2735 | AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, |
313f6e2d TI |
2736 | #else |
2737 | /* this entry seems still valid -- i.e. without emu20kx chip */ | |
9477c58e TI |
2738 | { PCI_DEVICE(0x1102, 0x0009), |
2739 | .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | | |
ef85f299 | 2740 | AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, |
313f6e2d | 2741 | #endif |
c563f473 TI |
2742 | /* CM8888 */ |
2743 | { PCI_DEVICE(0x13f6, 0x5011), | |
2744 | .driver_data = AZX_DRIVER_CMEDIA | | |
37e661ee | 2745 | AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, |
e35d4b11 OS |
2746 | /* Vortex86MX */ |
2747 | { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, | |
0f0714c5 BB |
2748 | /* VMware HDAudio */ |
2749 | { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, | |
9176b672 | 2750 | /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ |
c4da29ca YL |
2751 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), |
2752 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
2753 | .class_mask = 0xffffff, | |
9477c58e | 2754 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, |
9176b672 AB |
2755 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), |
2756 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | |
2757 | .class_mask = 0xffffff, | |
9477c58e | 2758 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, |
b6fcab14 TW |
2759 | /* Zhaoxin */ |
2760 | { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, | |
1da177e4 LT |
2761 | { 0, } |
2762 | }; | |
2763 | MODULE_DEVICE_TABLE(pci, azx_ids); | |
2764 | ||
2765 | /* pci_driver definition */ | |
e9f66d9b | 2766 | static struct pci_driver azx_driver = { |
3733e424 | 2767 | .name = KBUILD_MODNAME, |
1da177e4 LT |
2768 | .id_table = azx_ids, |
2769 | .probe = azx_probe, | |
e23e7a14 | 2770 | .remove = azx_remove, |
b2a0bafa | 2771 | .shutdown = azx_shutdown, |
68cb2b55 TI |
2772 | .driver = { |
2773 | .pm = AZX_PM_OPS, | |
2774 | }, | |
1da177e4 LT |
2775 | }; |
2776 | ||
e9f66d9b | 2777 | module_pci_driver(azx_driver); |